From bafbe39778a972d0f2869980de22fb00c03a6a35 Mon Sep 17 00:00:00 2001 From: Adrian Kuegel Date: Wed, 8 May 2024 10:22:02 +0200 Subject: [PATCH 001/328] [NVPTX] Add support for atomic add for bf16 type (#89586) atom.add.noftz.bf16 is supported since SM 9.0 and PTX 7.8 --- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 3 + llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 11 +- llvm/test/CodeGen/NVPTX/atomics-sm90.ll | 151 ++++++++++++++++++++ 3 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/NVPTX/atomics-sm90.ll diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 44b61a937d64..b03803f52b78 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -6125,6 +6125,9 @@ NVPTXTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const { if (Ty->isHalfTy() && STI.getSmVersion() >= 70 && STI.getPTXVersion() >= 63) return AtomicExpansionKind::None; + if (Ty->isBFloatTy() && STI.getSmVersion() >= 90 && + STI.getPTXVersion() >= 78) + return AtomicExpansionKind::None; if (Ty->isFloatTy()) return AtomicExpansionKind::None; if (Ty->isDoubleTy() && STI.hasAtomAddF64()) diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td index 5f6e28283c5d..440af085cb8e 100644 --- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td +++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td @@ -1545,7 +1545,7 @@ multiclass F_ATOMIC_2_imp, - Requires], Pred)>; + Requires], Pred)>; } multiclass F_ATOMIC_2, hasPTX<63>]>; +defm INT_PTX_ATOM_ADD_G_BF16 : F_ATOMIC_2, hasPTX<78>]>; +defm INT_PTX_ATOM_ADD_S_BF16 : F_ATOMIC_2, hasPTX<78>]>; +defm INT_PTX_ATOM_ADD_GEN_BF16 : F_ATOMIC_2, hasPTX<78>]>; + defm INT_PTX_ATOM_ADD_G_F32 : F_ATOMIC_2; defm INT_PTX_ATOM_ADD_S_F32 : F_ATOMIC_2 { defm _s32 : ATOM2S_impl; defm _u32 : ATOM2S_impl; defm _u64 : ATOM2S_impl; + defm _bf16 : ATOM2S_impl, hasPTX<78>]>; defm _f16 : ATOM2S_impl, hasPTX<63>]>; defm _f32 : ATOM2S_impl; +; CHECK-NEXT: .reg .b32 %r<4>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.u32 %r1, [test_param_0]; +; CHECK-NEXT: ld.param.b16 %rs1, [test_param_3]; +; CHECK-NEXT: atom.add.noftz.bf16 %rs2, [%r1], %rs1; +; CHECK-NEXT: ld.param.u32 %r2, [test_param_1]; +; CHECK-NEXT: mov.b16 %rs3, 0x3F80; +; CHECK-NEXT: atom.add.noftz.bf16 %rs4, [%r1], %rs3; +; CHECK-NEXT: ld.param.u32 %r3, [test_param_2]; +; CHECK-NEXT: atom.global.add.noftz.bf16 %rs5, [%r2], %rs1; +; CHECK-NEXT: atom.shared.add.noftz.bf16 %rs6, [%r3], %rs1; +; CHECK-NEXT: ret; +; +; CHECK64-LABEL: test( +; CHECK64: { +; CHECK64-NEXT: .reg .b16 %rs<7>; +; CHECK64-NEXT: .reg .b64 %rd<4>; +; CHECK64-EMPTY: +; CHECK64-NEXT: // %bb.0: +; CHECK64-NEXT: ld.param.u64 %rd1, [test_param_0]; +; CHECK64-NEXT: ld.param.b16 %rs1, [test_param_3]; +; CHECK64-NEXT: atom.add.noftz.bf16 %rs2, [%rd1], %rs1; +; CHECK64-NEXT: ld.param.u64 %rd2, [test_param_1]; +; CHECK64-NEXT: mov.b16 %rs3, 0x3F80; +; CHECK64-NEXT: atom.add.noftz.bf16 %rs4, [%rd1], %rs3; +; CHECK64-NEXT: ld.param.u64 %rd3, [test_param_2]; +; CHECK64-NEXT: atom.global.add.noftz.bf16 %rs5, [%rd2], %rs1; +; CHECK64-NEXT: atom.shared.add.noftz.bf16 %rs6, [%rd3], %rs1; +; CHECK64-NEXT: ret; +; +; CHECKPTX71-LABEL: test( +; CHECKPTX71: { +; CHECKPTX71-NEXT: .reg .pred %p<5>; +; CHECKPTX71-NEXT: .reg .b16 %rs<18>; +; CHECKPTX71-NEXT: .reg .b32 %r<58>; +; CHECKPTX71-NEXT: .reg .f32 %f<12>; +; CHECKPTX71-EMPTY: +; CHECKPTX71-NEXT: // %bb.0: +; CHECKPTX71-NEXT: ld.param.b16 %rs1, [test_param_3]; +; CHECKPTX71-NEXT: ld.param.u32 %r23, [test_param_2]; +; CHECKPTX71-NEXT: ld.param.u32 %r22, [test_param_1]; +; CHECKPTX71-NEXT: ld.param.u32 %r24, [test_param_0]; +; CHECKPTX71-NEXT: and.b32 %r1, %r24, -4; +; CHECKPTX71-NEXT: and.b32 %r25, %r24, 3; +; CHECKPTX71-NEXT: shl.b32 %r2, %r25, 3; +; CHECKPTX71-NEXT: mov.b32 %r26, 65535; +; CHECKPTX71-NEXT: shl.b32 %r27, %r26, %r2; +; CHECKPTX71-NEXT: not.b32 %r3, %r27; +; CHECKPTX71-NEXT: ld.u32 %r54, [%r1]; +; CHECKPTX71-NEXT: cvt.f32.bf16 %f2, %rs1; +; CHECKPTX71-NEXT: $L__BB0_1: // %atomicrmw.start +; CHECKPTX71-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECKPTX71-NEXT: shr.u32 %r28, %r54, %r2; +; CHECKPTX71-NEXT: cvt.u16.u32 %rs2, %r28; +; CHECKPTX71-NEXT: cvt.f32.bf16 %f1, %rs2; +; CHECKPTX71-NEXT: add.rn.f32 %f3, %f1, %f2; +; CHECKPTX71-NEXT: cvt.rn.bf16.f32 %rs4, %f3; +; CHECKPTX71-NEXT: cvt.u32.u16 %r29, %rs4; +; CHECKPTX71-NEXT: shl.b32 %r30, %r29, %r2; +; CHECKPTX71-NEXT: and.b32 %r31, %r54, %r3; +; CHECKPTX71-NEXT: or.b32 %r32, %r31, %r30; +; CHECKPTX71-NEXT: atom.cas.b32 %r6, [%r1], %r54, %r32; +; CHECKPTX71-NEXT: setp.ne.s32 %p1, %r6, %r54; +; CHECKPTX71-NEXT: mov.u32 %r54, %r6; +; CHECKPTX71-NEXT: @%p1 bra $L__BB0_1; +; CHECKPTX71-NEXT: // %bb.2: // %atomicrmw.end +; CHECKPTX71-NEXT: ld.u32 %r55, [%r1]; +; CHECKPTX71-NEXT: $L__BB0_3: // %atomicrmw.start9 +; CHECKPTX71-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECKPTX71-NEXT: shr.u32 %r33, %r55, %r2; +; CHECKPTX71-NEXT: cvt.u16.u32 %rs6, %r33; +; CHECKPTX71-NEXT: cvt.f32.bf16 %f4, %rs6; +; CHECKPTX71-NEXT: add.rn.f32 %f5, %f4, 0f3F800000; +; CHECKPTX71-NEXT: cvt.rn.bf16.f32 %rs8, %f5; +; CHECKPTX71-NEXT: cvt.u32.u16 %r34, %rs8; +; CHECKPTX71-NEXT: shl.b32 %r35, %r34, %r2; +; CHECKPTX71-NEXT: and.b32 %r36, %r55, %r3; +; CHECKPTX71-NEXT: or.b32 %r37, %r36, %r35; +; CHECKPTX71-NEXT: atom.cas.b32 %r9, [%r1], %r55, %r37; +; CHECKPTX71-NEXT: setp.ne.s32 %p2, %r9, %r55; +; CHECKPTX71-NEXT: mov.u32 %r55, %r9; +; CHECKPTX71-NEXT: @%p2 bra $L__BB0_3; +; CHECKPTX71-NEXT: // %bb.4: // %atomicrmw.end8 +; CHECKPTX71-NEXT: and.b32 %r10, %r22, -4; +; CHECKPTX71-NEXT: shl.b32 %r38, %r22, 3; +; CHECKPTX71-NEXT: and.b32 %r11, %r38, 24; +; CHECKPTX71-NEXT: shl.b32 %r40, %r26, %r11; +; CHECKPTX71-NEXT: not.b32 %r12, %r40; +; CHECKPTX71-NEXT: ld.global.u32 %r56, [%r10]; +; CHECKPTX71-NEXT: $L__BB0_5: // %atomicrmw.start27 +; CHECKPTX71-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECKPTX71-NEXT: shr.u32 %r41, %r56, %r11; +; CHECKPTX71-NEXT: cvt.u16.u32 %rs10, %r41; +; CHECKPTX71-NEXT: cvt.f32.bf16 %f6, %rs10; +; CHECKPTX71-NEXT: add.rn.f32 %f8, %f6, %f2; +; CHECKPTX71-NEXT: cvt.rn.bf16.f32 %rs12, %f8; +; CHECKPTX71-NEXT: cvt.u32.u16 %r42, %rs12; +; CHECKPTX71-NEXT: shl.b32 %r43, %r42, %r11; +; CHECKPTX71-NEXT: and.b32 %r44, %r56, %r12; +; CHECKPTX71-NEXT: or.b32 %r45, %r44, %r43; +; CHECKPTX71-NEXT: atom.global.cas.b32 %r15, [%r10], %r56, %r45; +; CHECKPTX71-NEXT: setp.ne.s32 %p3, %r15, %r56; +; CHECKPTX71-NEXT: mov.u32 %r56, %r15; +; CHECKPTX71-NEXT: @%p3 bra $L__BB0_5; +; CHECKPTX71-NEXT: // %bb.6: // %atomicrmw.end26 +; CHECKPTX71-NEXT: and.b32 %r16, %r23, -4; +; CHECKPTX71-NEXT: shl.b32 %r46, %r23, 3; +; CHECKPTX71-NEXT: and.b32 %r17, %r46, 24; +; CHECKPTX71-NEXT: shl.b32 %r48, %r26, %r17; +; CHECKPTX71-NEXT: not.b32 %r18, %r48; +; CHECKPTX71-NEXT: ld.shared.u32 %r57, [%r16]; +; CHECKPTX71-NEXT: $L__BB0_7: // %atomicrmw.start45 +; CHECKPTX71-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECKPTX71-NEXT: shr.u32 %r49, %r57, %r17; +; CHECKPTX71-NEXT: cvt.u16.u32 %rs14, %r49; +; CHECKPTX71-NEXT: cvt.f32.bf16 %f9, %rs14; +; CHECKPTX71-NEXT: add.rn.f32 %f11, %f9, %f2; +; CHECKPTX71-NEXT: cvt.rn.bf16.f32 %rs16, %f11; +; CHECKPTX71-NEXT: cvt.u32.u16 %r50, %rs16; +; CHECKPTX71-NEXT: shl.b32 %r51, %r50, %r17; +; CHECKPTX71-NEXT: and.b32 %r52, %r57, %r18; +; CHECKPTX71-NEXT: or.b32 %r53, %r52, %r51; +; CHECKPTX71-NEXT: atom.shared.cas.b32 %r21, [%r16], %r57, %r53; +; CHECKPTX71-NEXT: setp.ne.s32 %p4, %r21, %r57; +; CHECKPTX71-NEXT: mov.u32 %r57, %r21; +; CHECKPTX71-NEXT: @%p4 bra $L__BB0_7; +; CHECKPTX71-NEXT: // %bb.8: // %atomicrmw.end44 +; CHECKPTX71-NEXT: ret; + %r1 = atomicrmw fadd ptr %dp0, bfloat %val seq_cst + %r2 = atomicrmw fadd ptr %dp0, bfloat 1.0 seq_cst + %r3 = atomicrmw fadd ptr addrspace(1) %dp1, bfloat %val seq_cst + %r4 = atomicrmw fadd ptr addrspace(3) %dp3, bfloat %val seq_cst + ret void +} + +attributes #1 = { argmemonly nounwind } -- GitLab From 3aba4b5b4fe1634fc6f9919f987ddf1bb5a57813 Mon Sep 17 00:00:00 2001 From: Nikolas Klauser Date: Wed, 8 May 2024 10:34:55 +0200 Subject: [PATCH 002/328] [libc++][NFC] Refactor __is_transparent to be a variable template (#90865) --- libcxx/include/__functional/is_transparent.h | 5 +-- libcxx/include/map | 40 ++++++++++---------- libcxx/include/set | 40 ++++++++++---------- libcxx/include/unordered_map | 32 ++++++---------- libcxx/include/unordered_set | 36 ++++++------------ 5 files changed, 66 insertions(+), 87 deletions(-) diff --git a/libcxx/include/__functional/is_transparent.h b/libcxx/include/__functional/is_transparent.h index 13fc94f71c6b..b2d62f2e3ead 100644 --- a/libcxx/include/__functional/is_transparent.h +++ b/libcxx/include/__functional/is_transparent.h @@ -11,7 +11,6 @@ #define _LIBCPP___FUNCTIONAL_IS_TRANSPARENT #include <__config> -#include <__type_traits/integral_constant.h> #include <__type_traits/void_t.h> #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) @@ -23,10 +22,10 @@ _LIBCPP_BEGIN_NAMESPACE_STD #if _LIBCPP_STD_VER >= 14 template -struct __is_transparent : false_type {}; +inline const bool __is_transparent_v = false; template -struct __is_transparent<_Tp, _Up, __void_t > : true_type {}; +inline const bool __is_transparent_v<_Tp, _Up, __void_t > = true; #endif diff --git a/libcxx/include/map b/libcxx/include/map index 2276cc043709..1d1c062a0267 100644 --- a/libcxx/include/map +++ b/libcxx/include/map @@ -1367,11 +1367,11 @@ public: _LIBCPP_HIDE_FROM_ABI iterator find(const key_type& __k) { return __tree_.find(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator find(const key_type& __k) const { return __tree_.find(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI iterator find(const _K2& __k) { return __tree_.find(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI const_iterator find(const _K2& __k) const { return __tree_.find(__k); } @@ -1379,7 +1379,7 @@ public: _LIBCPP_HIDE_FROM_ABI size_type count(const key_type& __k) const { return __tree_.__count_unique(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI size_type count(const _K2& __k) const { return __tree_.__count_multi(__k); } @@ -1387,7 +1387,7 @@ public: #if _LIBCPP_STD_VER >= 20 _LIBCPP_HIDE_FROM_ABI bool contains(const key_type& __k) const { return find(__k) != end(); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI bool contains(const _K2& __k) const { return find(__k) != end(); } @@ -1396,12 +1396,12 @@ public: _LIBCPP_HIDE_FROM_ABI iterator lower_bound(const key_type& __k) { return __tree_.lower_bound(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator lower_bound(const key_type& __k) const { return __tree_.lower_bound(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI iterator lower_bound(const _K2& __k) { return __tree_.lower_bound(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI const_iterator lower_bound(const _K2& __k) const { return __tree_.lower_bound(__k); } @@ -1410,11 +1410,11 @@ public: _LIBCPP_HIDE_FROM_ABI iterator upper_bound(const key_type& __k) { return __tree_.upper_bound(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator upper_bound(const key_type& __k) const { return __tree_.upper_bound(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI iterator upper_bound(const _K2& __k) { return __tree_.upper_bound(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI const_iterator upper_bound(const _K2& __k) const { return __tree_.upper_bound(__k); } @@ -1427,11 +1427,11 @@ public: return __tree_.__equal_range_unique(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) { return __tree_.__equal_range_multi(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) const { return __tree_.__equal_range_multi(__k); } @@ -1959,11 +1959,11 @@ public: _LIBCPP_HIDE_FROM_ABI iterator find(const key_type& __k) { return __tree_.find(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator find(const key_type& __k) const { return __tree_.find(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI iterator find(const _K2& __k) { return __tree_.find(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI const_iterator find(const _K2& __k) const { return __tree_.find(__k); } @@ -1971,7 +1971,7 @@ public: _LIBCPP_HIDE_FROM_ABI size_type count(const key_type& __k) const { return __tree_.__count_multi(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI size_type count(const _K2& __k) const { return __tree_.__count_multi(__k); } @@ -1979,7 +1979,7 @@ public: #if _LIBCPP_STD_VER >= 20 _LIBCPP_HIDE_FROM_ABI bool contains(const key_type& __k) const { return find(__k) != end(); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI bool contains(const _K2& __k) const { return find(__k) != end(); } @@ -1988,12 +1988,12 @@ public: _LIBCPP_HIDE_FROM_ABI iterator lower_bound(const key_type& __k) { return __tree_.lower_bound(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator lower_bound(const key_type& __k) const { return __tree_.lower_bound(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI iterator lower_bound(const _K2& __k) { return __tree_.lower_bound(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI const_iterator lower_bound(const _K2& __k) const { return __tree_.lower_bound(__k); } @@ -2002,11 +2002,11 @@ public: _LIBCPP_HIDE_FROM_ABI iterator upper_bound(const key_type& __k) { return __tree_.upper_bound(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator upper_bound(const key_type& __k) const { return __tree_.upper_bound(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI iterator upper_bound(const _K2& __k) { return __tree_.upper_bound(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI const_iterator upper_bound(const _K2& __k) const { return __tree_.upper_bound(__k); } @@ -2019,11 +2019,11 @@ public: return __tree_.__equal_range_multi(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) { return __tree_.__equal_range_multi(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) const { return __tree_.__equal_range_multi(__k); } diff --git a/libcxx/include/set b/libcxx/include/set index 763c26cea01f..d9377ee6c332 100644 --- a/libcxx/include/set +++ b/libcxx/include/set @@ -825,11 +825,11 @@ public: _LIBCPP_HIDE_FROM_ABI iterator find(const key_type& __k) { return __tree_.find(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator find(const key_type& __k) const { return __tree_.find(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI iterator find(const _K2& __k) { return __tree_.find(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI const_iterator find(const _K2& __k) const { return __tree_.find(__k); } @@ -837,7 +837,7 @@ public: _LIBCPP_HIDE_FROM_ABI size_type count(const key_type& __k) const { return __tree_.__count_unique(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI size_type count(const _K2& __k) const { return __tree_.__count_multi(__k); } @@ -845,7 +845,7 @@ public: #if _LIBCPP_STD_VER >= 20 _LIBCPP_HIDE_FROM_ABI bool contains(const key_type& __k) const { return find(__k) != end(); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI bool contains(const _K2& __k) const { return find(__k) != end(); } @@ -854,12 +854,12 @@ public: _LIBCPP_HIDE_FROM_ABI iterator lower_bound(const key_type& __k) { return __tree_.lower_bound(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator lower_bound(const key_type& __k) const { return __tree_.lower_bound(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI iterator lower_bound(const _K2& __k) { return __tree_.lower_bound(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI const_iterator lower_bound(const _K2& __k) const { return __tree_.lower_bound(__k); } @@ -868,11 +868,11 @@ public: _LIBCPP_HIDE_FROM_ABI iterator upper_bound(const key_type& __k) { return __tree_.upper_bound(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator upper_bound(const key_type& __k) const { return __tree_.upper_bound(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI iterator upper_bound(const _K2& __k) { return __tree_.upper_bound(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI const_iterator upper_bound(const _K2& __k) const { return __tree_.upper_bound(__k); } @@ -885,11 +885,11 @@ public: return __tree_.__equal_range_unique(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) { return __tree_.__equal_range_multi(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) const { return __tree_.__equal_range_multi(__k); } @@ -1283,11 +1283,11 @@ public: _LIBCPP_HIDE_FROM_ABI iterator find(const key_type& __k) { return __tree_.find(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator find(const key_type& __k) const { return __tree_.find(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI iterator find(const _K2& __k) { return __tree_.find(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI const_iterator find(const _K2& __k) const { return __tree_.find(__k); } @@ -1295,7 +1295,7 @@ public: _LIBCPP_HIDE_FROM_ABI size_type count(const key_type& __k) const { return __tree_.__count_multi(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI size_type count(const _K2& __k) const { return __tree_.__count_multi(__k); } @@ -1303,7 +1303,7 @@ public: #if _LIBCPP_STD_VER >= 20 _LIBCPP_HIDE_FROM_ABI bool contains(const key_type& __k) const { return find(__k) != end(); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI bool contains(const _K2& __k) const { return find(__k) != end(); } @@ -1312,12 +1312,12 @@ public: _LIBCPP_HIDE_FROM_ABI iterator lower_bound(const key_type& __k) { return __tree_.lower_bound(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator lower_bound(const key_type& __k) const { return __tree_.lower_bound(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI iterator lower_bound(const _K2& __k) { return __tree_.lower_bound(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI const_iterator lower_bound(const _K2& __k) const { return __tree_.lower_bound(__k); } @@ -1326,11 +1326,11 @@ public: _LIBCPP_HIDE_FROM_ABI iterator upper_bound(const key_type& __k) { return __tree_.upper_bound(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator upper_bound(const key_type& __k) const { return __tree_.upper_bound(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI iterator upper_bound(const _K2& __k) { return __tree_.upper_bound(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI const_iterator upper_bound(const _K2& __k) const { return __tree_.upper_bound(__k); } @@ -1343,11 +1343,11 @@ public: return __tree_.__equal_range_multi(__k); } #if _LIBCPP_STD_VER >= 14 - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) { return __tree_.__equal_range_multi(__k); } - template ::value, int> = 0> + template , int> = 0> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) const { return __tree_.__equal_range_multi(__k); } diff --git a/libcxx/include/unordered_map b/libcxx/include/unordered_map index 8c21d703a5c0..c838cd96b112 100644 --- a/libcxx/include/unordered_map +++ b/libcxx/include/unordered_map @@ -1384,13 +1384,11 @@ public: _LIBCPP_HIDE_FROM_ABI iterator find(const key_type& __k) { return __table_.find(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator find(const key_type& __k) const { return __table_.find(__k); } #if _LIBCPP_STD_VER >= 20 - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI iterator find(const _K2& __k) { return __table_.find(__k); } - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI const_iterator find(const _K2& __k) const { return __table_.find(__k); } @@ -1398,8 +1396,7 @@ public: _LIBCPP_HIDE_FROM_ABI size_type count(const key_type& __k) const { return __table_.__count_unique(__k); } #if _LIBCPP_STD_VER >= 20 - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI size_type count(const _K2& __k) const { return __table_.__count_unique(__k); } @@ -1408,8 +1405,7 @@ public: #if _LIBCPP_STD_VER >= 20 _LIBCPP_HIDE_FROM_ABI bool contains(const key_type& __k) const { return find(__k) != end(); } - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI bool contains(const _K2& __k) const { return find(__k) != end(); } @@ -1423,12 +1419,12 @@ public: } #if _LIBCPP_STD_VER >= 20 template ::value && __is_transparent::value>* = nullptr> + enable_if_t<__is_transparent_v && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) { return __table_.__equal_range_unique(__k); } template ::value && __is_transparent::value>* = nullptr> + enable_if_t<__is_transparent_v && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) const { return __table_.__equal_range_unique(__k); } @@ -2135,13 +2131,11 @@ public: _LIBCPP_HIDE_FROM_ABI iterator find(const key_type& __k) { return __table_.find(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator find(const key_type& __k) const { return __table_.find(__k); } #if _LIBCPP_STD_VER >= 20 - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI iterator find(const _K2& __k) { return __table_.find(__k); } - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI const_iterator find(const _K2& __k) const { return __table_.find(__k); } @@ -2149,8 +2143,7 @@ public: _LIBCPP_HIDE_FROM_ABI size_type count(const key_type& __k) const { return __table_.__count_multi(__k); } #if _LIBCPP_STD_VER >= 20 - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI size_type count(const _K2& __k) const { return __table_.__count_multi(__k); } @@ -2159,8 +2152,7 @@ public: #if _LIBCPP_STD_VER >= 20 _LIBCPP_HIDE_FROM_ABI bool contains(const key_type& __k) const { return find(__k) != end(); } - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI bool contains(const _K2& __k) const { return find(__k) != end(); } @@ -2174,12 +2166,12 @@ public: } #if _LIBCPP_STD_VER >= 20 template ::value && __is_transparent::value>* = nullptr> + enable_if_t<__is_transparent_v && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) { return __table_.__equal_range_multi(__k); } template ::value && __is_transparent::value>* = nullptr> + enable_if_t<__is_transparent_v && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) const { return __table_.__equal_range_multi(__k); } diff --git a/libcxx/include/unordered_set b/libcxx/include/unordered_set index 69fe6b768788..5de1458beb1e 100644 --- a/libcxx/include/unordered_set +++ b/libcxx/include/unordered_set @@ -839,13 +839,11 @@ public: _LIBCPP_HIDE_FROM_ABI iterator find(const key_type& __k) { return __table_.find(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator find(const key_type& __k) const { return __table_.find(__k); } #if _LIBCPP_STD_VER >= 20 - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI iterator find(const _K2& __k) { return __table_.find(__k); } - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI const_iterator find(const _K2& __k) const { return __table_.find(__k); } @@ -853,8 +851,7 @@ public: _LIBCPP_HIDE_FROM_ABI size_type count(const key_type& __k) const { return __table_.__count_unique(__k); } #if _LIBCPP_STD_VER >= 20 - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI size_type count(const _K2& __k) const { return __table_.__count_unique(__k); } @@ -863,8 +860,7 @@ public: #if _LIBCPP_STD_VER >= 20 _LIBCPP_HIDE_FROM_ABI bool contains(const key_type& __k) const { return find(__k) != end(); } - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI bool contains(const _K2& __k) const { return find(__k) != end(); } @@ -877,13 +873,11 @@ public: return __table_.__equal_range_unique(__k); } #if _LIBCPP_STD_VER >= 20 - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) { return __table_.__equal_range_unique(__k); } - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) const { return __table_.__equal_range_unique(__k); } @@ -1442,13 +1436,11 @@ public: _LIBCPP_HIDE_FROM_ABI iterator find(const key_type& __k) { return __table_.find(__k); } _LIBCPP_HIDE_FROM_ABI const_iterator find(const key_type& __k) const { return __table_.find(__k); } #if _LIBCPP_STD_VER >= 20 - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI iterator find(const _K2& __k) { return __table_.find(__k); } - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI const_iterator find(const _K2& __k) const { return __table_.find(__k); } @@ -1456,8 +1448,7 @@ public: _LIBCPP_HIDE_FROM_ABI size_type count(const key_type& __k) const { return __table_.__count_multi(__k); } #if _LIBCPP_STD_VER >= 20 - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI size_type count(const _K2& __k) const { return __table_.__count_multi(__k); } @@ -1466,8 +1457,7 @@ public: #if _LIBCPP_STD_VER >= 20 _LIBCPP_HIDE_FROM_ABI bool contains(const key_type& __k) const { return find(__k) != end(); } - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI bool contains(const _K2& __k) const { return find(__k) != end(); } @@ -1480,13 +1470,11 @@ public: return __table_.__equal_range_multi(__k); } #if _LIBCPP_STD_VER >= 20 - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) { return __table_.__equal_range_multi(__k); } - template ::value && __is_transparent::value>* = nullptr> + template && __is_transparent_v>* = nullptr> _LIBCPP_HIDE_FROM_ABI pair equal_range(const _K2& __k) const { return __table_.__equal_range_multi(__k); } -- GitLab From 9ef28cf88ca6e45c3ecb75c649463f8797db68d2 Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra Date: Wed, 8 May 2024 09:43:49 +0100 Subject: [PATCH 003/328] VectorCombine: add test for crash #88796 (#91200) --- llvm/test/Transforms/VectorCombine/pr88796.ll | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 llvm/test/Transforms/VectorCombine/pr88796.ll diff --git a/llvm/test/Transforms/VectorCombine/pr88796.ll b/llvm/test/Transforms/VectorCombine/pr88796.ll new file mode 100644 index 000000000000..d5cd52e11d39 --- /dev/null +++ b/llvm/test/Transforms/VectorCombine/pr88796.ll @@ -0,0 +1,11 @@ +; REQUIRES: asserts +; RUN: not --crash opt -passes=vector-combine -disable-output %s + +define i32 @test() { +entry: + %0 = tail call i16 @llvm.vector.reduce.and.nxv8i16( trunc ( shufflevector ( insertelement ( poison, i32 268435456, i64 0), poison, zeroinitializer) to )) + ret i32 0 +} + +declare i16 @llvm.vector.reduce.and.nxv8i16() + -- GitLab From 57b9c15227ec15a5e2abf4587d7d0ad536cff9e6 Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra Date: Wed, 8 May 2024 09:47:55 +0100 Subject: [PATCH 004/328] VectorCombine: fix logical error after m_Trunc match (#91201) The matcher m_Trunc() matches an Operator with a given Opcode, which could either be an Instruction or ConstExpr. VectorCombine::foldTruncFromReductions() incorrectly assumes that the pattern matched is always an Instruction, and attempts a cast. Fix this. Fixes #88796. --- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 12 ++++++------ llvm/test/Transforms/VectorCombine/pr88796.ll | 9 +++++++-- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp index bbb70134870a..8573a8adf53b 100644 --- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -1961,17 +1961,17 @@ bool VectorCombine::foldTruncFromReductions(Instruction &I) { if (!match(ReductionSrc, m_OneUse(m_Trunc(m_Value(TruncSrc))))) return false; - auto *Trunc = cast(ReductionSrc); auto *TruncSrcTy = cast(TruncSrc->getType()); auto *ReductionSrcTy = cast(ReductionSrc->getType()); Type *ResultTy = I.getType(); TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; - InstructionCost OldCost = - TTI.getCastInstrCost(Instruction::Trunc, ReductionSrcTy, TruncSrcTy, - TTI::CastContextHint::None, CostKind, Trunc) + - TTI.getArithmeticReductionCost(ReductionOpc, ReductionSrcTy, std::nullopt, - CostKind); + InstructionCost OldCost = TTI.getArithmeticReductionCost( + ReductionOpc, ReductionSrcTy, std::nullopt, CostKind); + if (auto *Trunc = dyn_cast(ReductionSrc)) + OldCost += + TTI.getCastInstrCost(Instruction::Trunc, ReductionSrcTy, TruncSrcTy, + TTI::CastContextHint::None, CostKind, Trunc); InstructionCost NewCost = TTI.getArithmeticReductionCost(ReductionOpc, TruncSrcTy, std::nullopt, CostKind) + diff --git a/llvm/test/Transforms/VectorCombine/pr88796.ll b/llvm/test/Transforms/VectorCombine/pr88796.ll index d5cd52e11d39..4f26f5dcbb92 100644 --- a/llvm/test/Transforms/VectorCombine/pr88796.ll +++ b/llvm/test/Transforms/VectorCombine/pr88796.ll @@ -1,7 +1,12 @@ -; REQUIRES: asserts -; RUN: not --crash opt -passes=vector-combine -disable-output %s +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes=vector-combine -S %s | FileCheck %s define i32 @test() { +; CHECK-LABEL: define i32 @test() { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = tail call i16 @llvm.vector.reduce.and.nxv8i16( trunc ( shufflevector ( insertelement ( poison, i32 268435456, i64 0), poison, zeroinitializer) to )) +; CHECK-NEXT: ret i32 0 +; entry: %0 = tail call i16 @llvm.vector.reduce.and.nxv8i16( trunc ( shufflevector ( insertelement ( poison, i32 268435456, i64 0), poison, zeroinitializer) to )) ret i32 0 -- GitLab From 746bf297e2f0f637d2e1c197bf04a32ab04b669a Mon Sep 17 00:00:00 2001 From: Kiran Chandramohan Date: Wed, 8 May 2024 10:00:03 +0100 Subject: [PATCH 005/328] [Flang][OpenMP] Add checks for EXIT from associated loops (#91315) Extend the checker that deals with CYCLE to handle EXIT also. The difference for EXIT is that it is not allowed to EXIT from the innermost associated loops while it is OK to CYCLE in the innermost associated loop. Also add an incrementer on leaving the DO loop for EXIT checks. --- flang/lib/Semantics/check-omp-structure.cpp | 47 ++++++++++++++------- flang/test/Semantics/OpenMP/do08.f90 | 31 ++++++++++++++ 2 files changed, 63 insertions(+), 15 deletions(-) diff --git a/flang/lib/Semantics/check-omp-structure.cpp b/flang/lib/Semantics/check-omp-structure.cpp index 70863c5f20e8..2493eb3ed367 100644 --- a/flang/lib/Semantics/check-omp-structure.cpp +++ b/flang/lib/Semantics/check-omp-structure.cpp @@ -84,52 +84,69 @@ private: parser::CharBlock source_; }; -class OmpCycleChecker { +class OmpCycleAndExitChecker { public: - OmpCycleChecker(SemanticsContext &context, std::int64_t cycleLevel) - : context_{context}, cycleLevel_{cycleLevel} {} + OmpCycleAndExitChecker(SemanticsContext &context, std::int64_t level) + : context_{context}, level_{level} {} template bool Pre(const T &) { return true; } template void Post(const T &) {} bool Pre(const parser::DoConstruct &dc) { - cycleLevel_--; + level_--; const auto &constructName{std::get<0>(std::get<0>(dc.t).statement.t)}; if (constructName) { constructNamesAndLevels_.emplace( - constructName.value().ToString(), cycleLevel_); + constructName.value().ToString(), level_); } return true; } + void Post(const parser::DoConstruct &dc) { level_++; } + bool Pre(const parser::CycleStmt &cyclestmt) { std::map::iterator it; bool err{false}; if (cyclestmt.v) { it = constructNamesAndLevels_.find(cyclestmt.v->source.ToString()); err = (it != constructNamesAndLevels_.end() && it->second > 0); - } else { - // If there is no label then the cycle statement is associated with the - // closest enclosing DO. Use its level for the checks. - err = cycleLevel_ > 0; + } else { // If there is no label then use the level of the last enclosing DO + err = level_ > 0; } if (err) { - context_.Say(*cycleSource_, + context_.Say(*source_, "CYCLE statement to non-innermost associated loop of an OpenMP DO " "construct"_err_en_US); } return true; } + bool Pre(const parser::ExitStmt &exitStmt) { + std::map::iterator it; + bool err{false}; + if (exitStmt.v) { + it = constructNamesAndLevels_.find(exitStmt.v->source.ToString()); + err = (it != constructNamesAndLevels_.end() && it->second >= 0); + } else { // If there is no label then use the level of the last enclosing DO + err = level_ >= 0; + } + if (err) { + context_.Say(*source_, + "EXIT statement terminates associated loop of an OpenMP DO " + "construct"_err_en_US); + } + return true; + } + bool Pre(const parser::Statement &actionstmt) { - cycleSource_ = &actionstmt.source; + source_ = &actionstmt.source; return true; } private: SemanticsContext &context_; - const parser::CharBlock *cycleSource_; - std::int64_t cycleLevel_; + const parser::CharBlock *source_; + std::int64_t level_; std::map constructNamesAndLevels_; }; @@ -657,8 +674,8 @@ std::int64_t OmpStructureChecker::GetOrdCollapseLevel( void OmpStructureChecker::CheckCycleConstraints( const parser::OpenMPLoopConstruct &x) { std::int64_t ordCollapseLevel{GetOrdCollapseLevel(x)}; - OmpCycleChecker ompCycleChecker{context_, ordCollapseLevel}; - parser::Walk(x, ompCycleChecker); + OmpCycleAndExitChecker checker{context_, ordCollapseLevel}; + parser::Walk(x, checker); } void OmpStructureChecker::CheckDistLinear( diff --git a/flang/test/Semantics/OpenMP/do08.f90 b/flang/test/Semantics/OpenMP/do08.f90 index 3ba63072a80b..5143dff0dd31 100644 --- a/flang/test/Semantics/OpenMP/do08.f90 +++ b/flang/test/Semantics/OpenMP/do08.f90 @@ -4,6 +4,8 @@ program omp integer i, j, k + logical cond(10,10,10) + cond = .false. !ERROR: The value of the parameter in the COLLAPSE or ORDERED clause must not be larger than the number of nested loops following the construct. !$omp do collapse(3) @@ -135,4 +137,33 @@ program omp end do foo !$omp end do + !$omp do collapse(3) + loopk: do k=1,10 + loopj: do j=1,10 + loopi: do i=1,10 + ifi : if (.true.) then + !ERROR: EXIT statement terminates associated loop of an OpenMP DO construct + if (cond(i,j,k)) exit + if (cond(i,j,k)) exit ifi + !ERROR: EXIT statement terminates associated loop of an OpenMP DO construct + if (cond(i,j,k)) exit loopi + !ERROR: EXIT statement terminates associated loop of an OpenMP DO construct + if (cond(i,j,k)) exit loopj + end if ifi + end do loopi + end do loopj + end do loopk + !$omp end do + + !$omp do collapse(2) + loopk: do k=1,10 + loopj: do j=1,10 + do i=1,10 + end do + !ERROR: EXIT statement terminates associated loop of an OpenMP DO construct + if (cond(i,j,k)) exit + end do loopj + end do loopk + !$omp end do + end program omp -- GitLab From 602df270a9bfcb52980a93c85eb615c0d91eba0c Mon Sep 17 00:00:00 2001 From: Kiran Chandramohan Date: Wed, 8 May 2024 10:00:48 +0100 Subject: [PATCH 006/328] [Flang] RFC: Add support for -w option 1/n (#90420) Add support for the -w option to switch OFF all Flang warnings. This patch only supports switching OFF the frontend warnings. TODO : Support for MLIR, LLVM and Driver warnings. TODO : Support interactions between -w, -pedantic, -Wall --- clang/include/clang/Driver/Options.td | 2 +- clang/lib/Driver/ToolChains/Flang.cpp | 4 +++ .../flang/Frontend/CompilerInvocation.h | 8 +++++ flang/lib/Frontend/CompilerInvocation.cpp | 10 ++++++ flang/test/Driver/w-option.f90 | 31 +++++++++++++++++++ 5 files changed, 54 insertions(+), 1 deletion(-) create mode 100644 flang/test/Driver/w-option.f90 diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 2c319ba38a29..734ae7833f5c 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -5703,7 +5703,7 @@ def whatsloaded : Flag<["-"], "whatsloaded">; def why_load : Flag<["-"], "why_load">; def whyload : Flag<["-"], "whyload">, Alias; def w : Flag<["-"], "w">, HelpText<"Suppress all warnings">, - Visibility<[ClangOption, CC1Option]>, + Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, MarshallingInfoFlag>; def x : JoinedOrSeparate<["-"], "x">, Flags<[NoXarchOption]>, diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index 8955b9fb653c..436a9c418a5f 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -748,6 +748,10 @@ void Flang::ConstructJob(Compilation &C, const JobAction &JA, // Add other compile options addOtherOptions(Args, CmdArgs); + // Disable all warnings + // TODO: Handle interactions between -w, -pedantic, -Wall, -WOption + Args.AddLastArg(CmdArgs, options::OPT_w); + // Forward flags for OpenMP. We don't do this if the current action is an // device offloading action other than OpenMP. if (Args.hasFlag(options::OPT_fopenmp, options::OPT_fopenmp_EQ, diff --git a/flang/include/flang/Frontend/CompilerInvocation.h b/flang/include/flang/Frontend/CompilerInvocation.h index 4924d090eaf9..0fefaecfe4f0 100644 --- a/flang/include/flang/Frontend/CompilerInvocation.h +++ b/flang/include/flang/Frontend/CompilerInvocation.h @@ -114,8 +114,10 @@ class CompilerInvocation : public CompilerInvocationBase { // Fortran Dialect options Fortran::common::IntrinsicTypeDefaultKinds defaultKinds; + // Fortran Warning options bool enableConformanceChecks = false; bool enableUsageChecks = false; + bool disableWarnings = false; /// Used in e.g. unparsing to dump the analyzed rather than the original /// parse-tree objects. @@ -197,6 +199,9 @@ public: bool &getEnableUsageChecks() { return enableUsageChecks; } const bool &getEnableUsageChecks() const { return enableUsageChecks; } + bool &getDisableWarnings() { return disableWarnings; } + const bool &getDisableWarnings() const { return disableWarnings; } + Fortran::parser::AnalyzedObjectsAsFortran &getAsFortran() { return asFortran; } @@ -226,6 +231,9 @@ public: // Enables the usage checks void setEnableUsageChecks() { enableUsageChecks = true; } + // Disables all Warnings + void setDisableWarnings() { disableWarnings = true; } + /// Useful setters void setArgv0(const char *dir) { argv0 = dir; } diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp index f1b7b5397539..4318286e7415 100644 --- a/flang/lib/Frontend/CompilerInvocation.cpp +++ b/flang/lib/Frontend/CompilerInvocation.cpp @@ -975,6 +975,11 @@ static bool parseDialectArgs(CompilerInvocation &res, llvm::opt::ArgList &args, res.setEnableConformanceChecks(); res.setEnableUsageChecks(); } + + // -w + if (args.hasArg(clang::driver::options::OPT_w)) + res.setDisableWarnings(); + // -std=f2018 // TODO: Set proper options when more fortran standards // are supported. @@ -1403,6 +1408,11 @@ void CompilerInvocation::setFortranOpts() { if (getEnableUsageChecks()) fortranOptions.features.WarnOnAllUsage(); + + if (getDisableWarnings()) { + fortranOptions.features.DisableAllNonstandardWarnings(); + fortranOptions.features.DisableAllUsageWarnings(); + } } std::unique_ptr diff --git a/flang/test/Driver/w-option.f90 b/flang/test/Driver/w-option.f90 new file mode 100644 index 000000000000..e34cddaab373 --- /dev/null +++ b/flang/test/Driver/w-option.f90 @@ -0,0 +1,31 @@ +! Test the default setting. Emit warnings only. +! RUN: %flang -c %s 2>&1 | FileCheck %s -check-prefix=DEFAULT + +! Test that the warnings are not generated with `-w` option. +! RUN: %flang -c -w %s 2>&1 | FileCheck --allow-empty %s -check-prefix=WARNING + +! Test that warnings are portability messages are generated. +! RUN: %flang -c -pedantic %s 2>&1 | FileCheck %s -check-prefixes=DEFAULT,PORTABILITY + +! Test that warnings and portability messages are not generated. +! TODO: Support the last flag wins behaviour. +! RUN: %flang -c -pedantic -w %s 2>&1 | FileCheck --allow-empty %s -check-prefixes=WARNING,PORTABILITY-WARNING +! RUN: %flang -c -w -pedantic %s 2>&1 | FileCheck --allow-empty %s -check-prefixes=WARNING,PORTABILITY-WARNING +! DEFAULT: warning: Label '40' is in a construct that should not be used as a branch target here +! DEFAULT: warning: Label '50' is in a construct that should not be used as a branch target here +! WARNING-NOT: warning +! PORTABILITY: portability: Statement function 'sf1' should not contain an array constructor +! PORTABILITY-WARNING-NOT: portability + +subroutine sub01(n) + integer n + GOTO (40,50,60) n + if (n .eq. 1) then +40 print *, "xyz" +50 end if +60 continue +end subroutine sub01 + +subroutine sub02 + sf1(n) = sum([(j,j=1,n)]) +end subroutine sub02 -- GitLab From 1a498103ee5c4d101e70dc49db11938d8b87b518 Mon Sep 17 00:00:00 2001 From: Benjamin Maxwell Date: Wed, 8 May 2024 10:01:47 +0100 Subject: [PATCH 007/328] [mlir][ArmSME][test] Prepare tests for tile allocation changes (#91358) This patch: 1. Removes some duplicate test cases 2. Removes unnecessary uses of `-convert-arm-sme-to-llvm` 3. Ensures tile values have uses via `test.some_use()` 1 and 2 will make these tests easier to update. 3 will be needed as ArmSME operations will be pure. --- .../ArmSMEToLLVM/arm-sme-to-llvm.mlir | 24 +- .../Conversion/ArmSMEToLLVM/unsupported.mlir | 2 +- .../ArmSMEToSCF/arm-sme-to-scf.mlir | 6 + ...cation.mlir => basic-tile-allocation.mlir} | 297 ++++++++++-------- mlir/test/Dialect/ArmSME/enable-arm-za.mlir | 20 +- .../Dialect/ArmSME/outer-product-fusion.mlir | 7 +- mlir/test/Dialect/ArmSME/tile-zero-masks.mlir | 43 ++- 7 files changed, 234 insertions(+), 165 deletions(-) rename mlir/test/Dialect/ArmSME/{tile-allocation.mlir => basic-tile-allocation.mlir} (52%) diff --git a/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir b/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir index 81087cc02099..f48046a8d799 100644 --- a/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir +++ b/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir @@ -25,6 +25,7 @@ func.func @arm_sme_load_tile_slice_hor_i8(%src : memref, %mask : vector< %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[16]x[16]xi8> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index : memref, vector<[16]xi1>, vector<[16]x[16]xi8> + "test.some_use" (%tile_update) : (vector<[16]x[16]xi8>) -> () return } @@ -36,6 +37,7 @@ func.func @arm_sme_load_tile_slice_hor_i16(%src : memref, %mask : vecto %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[8]x[8]xi16> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index : memref, vector<[8]xi1>, vector<[8]x[8]xi16> + "test.some_use" (%tile_update) : (vector<[8]x[8]xi16>) -> () return } @@ -47,6 +49,7 @@ func.func @arm_sme_load_tile_slice_hor_i32(%src : memref, %mask : vecto %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[4]x[4]xi32> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index : memref, vector<[4]xi1>, vector<[4]x[4]xi32> + "test.some_use" (%tile_update) : (vector<[4]x[4]xi32>) -> () return } @@ -58,6 +61,7 @@ func.func @arm_sme_load_tile_slice_hor_i64(%src : memref, %mask : vecto %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[2]x[2]xi64> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index : memref, vector<[2]xi1>, vector<[2]x[2]xi64> + "test.some_use" (%tile_update) : (vector<[2]x[2]xi64>) -> () return } @@ -69,6 +73,7 @@ func.func @arm_sme_load_tile_slice_hor_i128(%src : memref, %mask : vec %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[1]x[1]xi128> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index : memref, vector<[1]xi1>, vector<[1]x[1]xi128> + "test.some_use" (%tile_update) : (vector<[1]x[1]xi128>) -> () return } @@ -80,6 +85,7 @@ func.func @arm_sme_load_tile_slice_hor_f16(%src : memref, %mask : vecto %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[8]x[8]xf16> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index : memref, vector<[8]xi1>, vector<[8]x[8]xf16> + "test.some_use" (%tile_update) : (vector<[8]x[8]xf16>) -> () return } @@ -91,6 +97,7 @@ func.func @arm_sme_load_tile_slice_hor_bf16(%src : memref, %mask : vec %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index : memref, vector<[8]xi1>, vector<[8]x[8]xbf16> + "test.some_use" (%tile_update) : (vector<[8]x[8]xbf16>) -> () return } @@ -102,6 +109,7 @@ func.func @arm_sme_load_tile_slice_hor_f32(%src : memref, %mask : vecto %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[4]x[4]xf32> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index : memref, vector<[4]xi1>, vector<[4]x[4]xf32> + "test.some_use" (%tile_update) : (vector<[4]x[4]xf32>) -> () return } @@ -113,6 +121,7 @@ func.func @arm_sme_load_tile_slice_hor_f64(%src : memref, %mask : vecto %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[2]x[2]xf64> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index : memref, vector<[2]xi1>, vector<[2]x[2]xf64> + "test.some_use" (%tile_update) : (vector<[2]x[2]xf64>) -> () return } @@ -124,6 +133,7 @@ func.func @arm_sme_load_tile_slice_ver_i8(%src : memref, %mask : vector< %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[16]x[16]xi8> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index layout : memref, vector<[16]xi1>, vector<[16]x[16]xi8> + "test.some_use" (%tile_update) : (vector<[16]x[16]xi8>) -> () return } @@ -135,6 +145,7 @@ func.func @arm_sme_load_tile_slice_ver_i16(%src : memref, %mask : vecto %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[8]x[8]xi16> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index layout : memref, vector<[8]xi1>, vector<[8]x[8]xi16> + "test.some_use" (%tile_update) : (vector<[8]x[8]xi16>) -> () return } @@ -146,6 +157,7 @@ func.func @arm_sme_load_tile_slice_ver_i32(%src : memref, %mask : vecto %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[4]x[4]xi32> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index layout : memref, vector<[4]xi1>, vector<[4]x[4]xi32> + "test.some_use" (%tile_update) : (vector<[4]x[4]xi32>) -> () return } @@ -157,6 +169,7 @@ func.func @arm_sme_load_tile_slice_ver_i64(%src : memref, %mask : vecto %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[2]x[2]xi64> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index layout : memref, vector<[2]xi1>, vector<[2]x[2]xi64> + "test.some_use" (%tile_update) : (vector<[2]x[2]xi64>) -> () return } @@ -168,6 +181,7 @@ func.func @arm_sme_load_tile_slice_ver_i128(%src : memref, %mask : vec %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[1]x[1]xi128> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index layout : memref, vector<[1]xi1>, vector<[1]x[1]xi128> + "test.some_use" (%tile_update) : (vector<[1]x[1]xi128>) -> () return } @@ -179,6 +193,7 @@ func.func @arm_sme_load_tile_slice_ver_f16(%src : memref, %mask : vecto %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[8]x[8]xf16> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index layout : memref, vector<[8]xi1>, vector<[8]x[8]xf16> + "test.some_use" (%tile_update) : (vector<[8]x[8]xf16>) -> () return } @@ -190,6 +205,7 @@ func.func @arm_sme_load_tile_slice_ver_bf16(%src : memref, %mask : vec %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index layout : memref, vector<[8]xi1>, vector<[8]x[8]xbf16> + "test.some_use" (%tile_update) : (vector<[8]x[8]xbf16>) -> () return } @@ -201,6 +217,7 @@ func.func @arm_sme_load_tile_slice_ver_f32(%src : memref, %mask : vecto %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[4]x[4]xf32> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index layout : memref, vector<[4]xi1>, vector<[4]x[4]xf32> + "test.some_use" (%tile_update) : (vector<[4]x[4]xf32>) -> () return } @@ -212,6 +229,7 @@ func.func @arm_sme_load_tile_slice_ver_f64(%src : memref, %mask : vecto %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[2]x[2]xf64> %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index layout : memref, vector<[2]xi1>, vector<[2]x[2]xf64> + "test.some_use" (%tile_update) : (vector<[2]x[2]xf64>) -> () return } @@ -441,7 +459,8 @@ func.func @arm_sme_store_tile_slice_ver_f64(%tile_slice_index : index, %mask : v func.func @arm_sme_move_vector_to_tile_slice_hor_i32(%vector : vector<[4]xi32>, %tile_slice_index : index) -> () { %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[4]x[4]xi32> - arm_sme.move_vector_to_tile_slice %vector, %tile, %tile_slice_index : vector<[4]xi32> into vector<[4]x[4]xi32> + %tile_update = arm_sme.move_vector_to_tile_slice %vector, %tile, %tile_slice_index : vector<[4]xi32> into vector<[4]x[4]xi32> + "test.some_use" (%tile_update) : (vector<[4]x[4]xi32>) -> () return } @@ -452,7 +471,8 @@ func.func @arm_sme_move_vector_to_tile_slice_hor_i32(%vector : vector<[4]xi32>, func.func @arm_sme_move_vector_to_tile_slice_ver_bf16(%vector : vector<[8]xbf16>, %tile_slice_index : index) -> () { %c0 = arith.constant 0 : index %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> - arm_sme.move_vector_to_tile_slice %vector, %tile, %tile_slice_index layout : vector<[8]xbf16> into vector<[8]x[8]xbf16> + %tile_update = arm_sme.move_vector_to_tile_slice %vector, %tile, %tile_slice_index layout : vector<[8]xbf16> into vector<[8]x[8]xbf16> + "test.some_use" (%tile_update) : (vector<[8]x[8]xbf16>) -> () return } diff --git a/mlir/test/Conversion/ArmSMEToLLVM/unsupported.mlir b/mlir/test/Conversion/ArmSMEToLLVM/unsupported.mlir index 59665c471921..15767ff1dec3 100644 --- a/mlir/test/Conversion/ArmSMEToLLVM/unsupported.mlir +++ b/mlir/test/Conversion/ArmSMEToLLVM/unsupported.mlir @@ -9,6 +9,6 @@ func.func @arm_sme_outerproduct_unsupported_type(%lhs : vector<[16]xi8>, %rhs : // expected-error@+2 {{failed to legalize operation 'arm_sme.outerproduct'}} // expected-error@+1 {{unsupported type}} %0 = arm_sme.outerproduct %lhs, %rhs acc(%acc) : vector<[16]xi8>, vector<[16]xi8> - "prevent.dce"(%0) : (vector<[16]x[16]xi8>) -> () + "test.some_use"(%0) : (vector<[16]x[16]xi8>) -> () } diff --git a/mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir b/mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir index 6c393bc38af9..a2f2beff78c4 100644 --- a/mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir +++ b/mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir @@ -20,6 +20,7 @@ func.func @arm_sme_tile_load_hor(%src : memref) { %c0 = arith.constant 0 : index %tile = arm_sme.tile_load %src[%c0, %c0] : memref, vector<[4]x[4]xi32> + "test.some_use" (%tile) : (vector<[4]x[4]xi32>) -> () return } @@ -30,6 +31,7 @@ func.func @arm_sme_tile_load_hor(%src : memref) { func.func @arm_sme_tile_load_ver(%src : memref) { %c0 = arith.constant 0 : index %tile = arm_sme.tile_load %src[%c0, %c0] layout : memref, vector<[4]x[4]xi32> + "test.some_use" (%tile) : (vector<[4]x[4]xi32>) -> () return } @@ -60,6 +62,7 @@ func.func @arm_sme_tile_load_hor_with_mask_and_pad_zero(%src : memref) %pad = arith.constant 0 : i32 %mask = vector.create_mask %c3, %c2 : vector<[4]x[4]xi1> %tile = arm_sme.tile_load %src[%c0, %c0], %pad, %mask : memref, vector<[4]x[4]xi32> + "test.some_use" (%tile) : (vector<[4]x[4]xi32>) -> () return } @@ -94,6 +97,7 @@ func.func @arm_sme_tile_load_hor_with_mask_and_nonzero_pad(%src : memref %tile = arm_sme.tile_load %src[%c0, %c0], %pad, %mask : memref, vector<[4]x[4]xi32> + "test.some_use" (%tile) : (vector<[4]x[4]xi32>) -> () return } @@ -104,6 +108,7 @@ func.func @arm_sme_tile_load_zero_pad__unsupported_mask_op(%src : memref, vector<[4]x[4]xi32> + "test.some_use" (%tile) : (vector<[4]x[4]xi32>) -> () return } @@ -113,6 +118,7 @@ func.func @arm_sme_tile_load_nonzero_pad__unsupported_mask_op(%src : memref, vector<[4]x[4]xi32> + "test.some_use" (%tile) : (vector<[4]x[4]xi32>) -> () return } diff --git a/mlir/test/Dialect/ArmSME/tile-allocation.mlir b/mlir/test/Dialect/ArmSME/basic-tile-allocation.mlir similarity index 52% rename from mlir/test/Dialect/ArmSME/tile-allocation.mlir rename to mlir/test/Dialect/ArmSME/basic-tile-allocation.mlir index 9c368dd4fa23..e144bac970a7 100644 --- a/mlir/test/Dialect/ArmSME/tile-allocation.mlir +++ b/mlir/test/Dialect/ArmSME/basic-tile-allocation.mlir @@ -1,9 +1,10 @@ -// RUN: mlir-opt %s -allocate-arm-sme-tiles -split-input-file -verify-diagnostics | FileCheck %s +// RUN: mlir-opt %s -allocate-arm-sme-tiles -split-input-file | FileCheck %s // ----- +// Note: Tile IDs >= 16 are in-memory tile IDs (i.e. spills). + // CHECK-LABEL: mixed_tiles -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 65534 : i32} func.func @mixed_tiles() { // ZA0.Q, ZA2.Q, ZA4.Q, ZA6.Q, ZA8.Q, ZA10.Q, ZA12.Q, ZA14.Q // CHECK-NEXT: tile_id = 0 @@ -18,76 +19,61 @@ func.func @mixed_tiles() { // CHECK-NEXT: tile_id = 7 %za7_q = arm_sme.get_tile : vector<[1]x[1]xi128> // ZA15.Q is still free. + "test.some_use"(%za0_h) : (vector<[8]x[8]xi16>) -> () + "test.some_use"(%za1_s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%za3_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za7_q) : (vector<[1]x[1]xi128>) -> () return } // ----- // CHECK-LABEL: za_b -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 65535 : i32} func.func @za_b() { // CHECK-NEXT: tile_id = 0 %za0_b = arm_sme.get_tile : vector<[16]x[16]xi8> - return -} - -// ----- - -func.func @za_b__out_of_tiles() { - %za0_b = arm_sme.get_tile : vector<[16]x[16]xi8> - // expected-warning @below {{failed to allocate SME virtual tile to operation, all tile operations will go through memory, expect degraded performance}} + // Next tile is in-memory: + // CHECK-NEXT: tile_id = 16 %next_tile = arm_sme.get_tile : vector<[16]x[16]xi8> + "test.some_use"(%za0_b) : (vector<[16]x[16]xi8>) -> () + "test.some_use"(%next_tile) : (vector<[16]x[16]xi8>) -> () return } // ----- +// CHECK-LABEL: za_b_overlapping_za_q func.func @za_b_overlapping_za_q() { + // CHECK-NEXT: tile_id = 0 %za0_b = arm_sme.get_tile : vector<[16]x[16]xi8> - // expected-warning @below {{failed to allocate SME virtual tile to operation, all tile operations will go through memory, expect degraded performance}} + // Next tile is in-memory: + // CHECK-NEXT: tile_id = 16 %next_tile = arm_sme.get_tile : vector<[1]x[1]xi128> - return -} - -// ----- - -// CHECK-LABEL: za0_h -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 43690 : i32} -func.func @za0_h() { - // CHECK-NEXT: tile_id = 0 - %za0_h = arm_sme.get_tile : vector<[8]x[8]xi16> + "test.some_use"(%za0_b) : (vector<[16]x[16]xi8>) -> () + "test.some_use"(%next_tile) : (vector<[1]x[1]xi128>) -> () return } // ----- // CHECK-LABEL: za_h -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 65535 : i32} func.func @za_h() { // CHECK-NEXT: tile_id = 0 %za0_h = arm_sme.get_tile : vector<[8]x[8]xi16> // CHECK-NEXT: tile_id = 1 %za1_h = arm_sme.get_tile : vector<[8]x[8]xi16> - return -} - -// ----- - -// CHECK-LABEL: za_h__out_of_tiles -func.func @za_h__out_of_tiles() { - // CHECK-NEXT: tile_id = 0 - %za0_h = arm_sme.get_tile : vector<[8]x[8]xi16> - // CHECK-NEXT: tile_id = 1 - %za1_h = arm_sme.get_tile : vector<[8]x[8]xi16> - // expected-warning @below {{failed to allocate SME virtual tile to operation, all tile operations will go through memory, expect degraded performance}} + // Next tile is in-memory: + // CHECK-NEXT: tile_id = 16 %next_tile = arm_sme.get_tile : vector<[8]x[8]xi16> + "test.some_use"(%za0_h) : (vector<[8]x[8]xi16>) -> () + "test.some_use"(%za1_h) : (vector<[8]x[8]xi16>) -> () + "test.some_use"(%next_tile) : (vector<[8]x[8]xi16>) -> () return } // ----- // CHECK-LABEL: za_h_overlapping_za_s -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 65535 : i32} func.func @za_h_overlapping_za_s() { // ZA0.Q, ZA2.Q, ZA4.Q, ZA6.Q, ZA8.Q, ZA10.Q, ZA12.Q, ZA14.Q // CHECK-NEXT: tile_id = 0 @@ -98,13 +84,15 @@ func.func @za_h_overlapping_za_s() { // ZA3.Q, ZA7.Q, ZA11.Q, ZA15.Q // CHECK-NEXT: tile_id = 3 %za3_s = arm_sme.get_tile : vector<[4]x[4]xi32> + "test.some_use"(%za0_h) : (vector<[8]x[8]xi16>) -> () + "test.some_use"(%za1_s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%za3_s) : (vector<[4]x[4]xi32>) -> () return } // ----- // CHECK-LABEL: za_h_overlapping_za_d -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 65535 : i32} func.func @za_h_overlapping_za_d() { // ZA0.Q, ZA2.Q, ZA4.Q, ZA6.Q, ZA8.Q, ZA10.Q, ZA12.Q, ZA14.Q // CHECK-NEXT: tile_id = 0 @@ -121,40 +109,55 @@ func.func @za_h_overlapping_za_d() { // ZA7.Q, ZA15.Q // CHECK-NEXT: tile_id = 7 %za7_d = arm_sme.get_tile : vector<[2]x[2]xi64> + "test.some_use"(%za0_h) : (vector<[8]x[8]xi16>) -> () + "test.some_use"(%za1_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za3_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za5_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za7_d) : (vector<[2]x[2]xi64>) -> () return } // ----- +// CHECK-LABEL: za_h_overlapping_za_q func.func @za_h_overlapping_za_q() { + // CHECK-NEXT: tile_id = 0 %za0_h = arm_sme.get_tile : vector<[8]x[8]xi16> - %za0_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za2_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za4_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za6_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za8_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za10_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za12_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za14_q = arm_sme.get_tile : vector<[1]x[1]xi128> - // expected-warning @below {{failed to allocate SME virtual tile to operation, all tile operations will go through memory, expect degraded performance}} + // CHECK-NEXT: tile_id = 1 + %za1_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 3 + %za3_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 5 + %za5_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 7 + %za7_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 9 + %za9_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 11 + %za11_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 13 + %za13_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 15 + %za15_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // Next tile is in-memory: + // CHECK-NEXT: tile_id = 16 %next_tile = arm_sme.get_tile : vector<[1]x[1]xi128> - return -} - -// ----- - -// CHECK-LABEL: za0_s -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 34952 : i32} -func.func @za0_s() { - // CHECK-NEXT: tile_id = 0 - %za0_s = arm_sme.get_tile : vector<[4]x[4]xi32> + "test.some_use"(%za0_h) : (vector<[8]x[8]xi16>) -> () + "test.some_use"(%za1_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za3_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za5_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za7_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za9_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za11_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za13_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za15_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%next_tile) : (vector<[1]x[1]xi128>) -> () return } // ----- // CHECK-LABEL: za_s -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 65535 : i32} func.func @za_s() { // CHECK-NEXT: tile_id = 0 %za0_s = arm_sme.get_tile : vector<[4]x[4]xi32> @@ -164,25 +167,20 @@ func.func @za_s() { %za2_s = arm_sme.get_tile : vector<[4]x[4]xi32> // CHECK-NEXT: tile_id = 3 %za3_s = arm_sme.get_tile : vector<[4]x[4]xi32> - return -} - -// ----- - -func.func @za_s__out_of_tiles() { - %za0_s = arm_sme.get_tile : vector<[4]x[4]xi32> - %za1_s = arm_sme.get_tile : vector<[4]x[4]xi32> - %za2_s = arm_sme.get_tile : vector<[4]x[4]xi32> - %za3_s = arm_sme.get_tile : vector<[4]x[4]xi32> - // expected-warning @below {{failed to allocate SME virtual tile to operation, all tile operations will go through memory, expect degraded performance}} + // Next tile is in-memory: + // CHECK-NEXT: tile_id = 16 %next_tile = arm_sme.get_tile : vector<[4]x[4]xi32> + "test.some_use"(%za0_s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%za1_s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%za2_s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%za3_s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%next_tile) : (vector<[4]x[4]xi32>) -> () return } // ----- // CHECK-LABEL: za_s_overlapping_za_d -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 65535 : i32} func.func @za_s_overlapping_za_d() { // ZA0.Q, ZA4.Q, ZA8.Q, ZA12.Q // CHECK-NEXT: tile_id = 0 @@ -199,44 +197,67 @@ func.func @za_s_overlapping_za_d() { // ZA7.Q, ZA15.Q // CHECK-NEXT: tile_id = 7 %za7_d = arm_sme.get_tile : vector<[2]x[2]xi64> + "test.some_use"(%za0_s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%za1_s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%za2_s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%za3_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za7_d) : (vector<[2]x[2]xi64>) -> () return } // ----- +// CHECK-LABEL: za_s_overlapping_za_q func.func @za_s_overlapping_za_q() { + // CHECK-NEXT: tile_id = 0 %za0_s = arm_sme.get_tile : vector<[4]x[4]xi32> + // CHECK-NEXT: tile_id = 1 %za1_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 2 %za2_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 3 %za3_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 5 %za5_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 6 %za6_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 7 %za7_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 9 %za9_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 10 %za10_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 11 %za11_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 13 %za13_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 14 %za14_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 15 %za15_q = arm_sme.get_tile : vector<[1]x[1]xi128> - // expected-warning @below {{failed to allocate SME virtual tile to operation, all tile operations will go through memory, expect degraded performance}} + // Next tile is in-memory: + // CHECK-NEXT: tile_id = 16 %next_tile = arm_sme.get_tile : vector<[1]x[1]xi128> - return -} - -// ----- - -// CHECK-LABEL: za0_d -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 32896 : i32} -func.func @za0_d() { - // CHECK-NEXT: tile_id = 0 - %za0_d = arm_sme.get_tile : vector<[2]x[2]xi64> + "test.some_use"(%za0_s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%za1_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za2_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za3_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za5_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za6_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za7_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za9_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za10_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za11_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za13_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za14_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za15_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%next_tile) : (vector<[1]x[1]xi128>) -> () return } // ----- // CHECK-LABEL: za_d -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 65535 : i32} func.func @za_d() { // CHECK-NEXT: tile_id = 0 %za0_d = arm_sme.get_tile : vector<[2]x[2]xi64> @@ -254,62 +275,80 @@ func.func @za_d() { %za6_d = arm_sme.get_tile : vector<[2]x[2]xi64> // CHECK-NEXT: tile_id = 7 %za7_d = arm_sme.get_tile : vector<[2]x[2]xi64> - return -} - -// ----- - -func.func @za_d__out_of_tiles() { - %za0_d = arm_sme.get_tile : vector<[2]x[2]xi64> - %za1_d = arm_sme.get_tile : vector<[2]x[2]xi64> - %za2_d = arm_sme.get_tile : vector<[2]x[2]xi64> - %za3_d = arm_sme.get_tile : vector<[2]x[2]xi64> - %za4_d = arm_sme.get_tile : vector<[2]x[2]xi64> - %za5_d = arm_sme.get_tile : vector<[2]x[2]xi64> - %za6_d = arm_sme.get_tile : vector<[2]x[2]xi64> - %za7_d = arm_sme.get_tile : vector<[2]x[2]xi64> - // expected-warning @below {{failed to allocate SME virtual tile to operation, all tile operations will go through memory, expect degraded performance}} + // Next tile is in-memory: + // CHECK-NEXT: tile_id = 16 %next_tile = arm_sme.get_tile : vector<[2]x[2]xi64> + "test.some_use"(%za0_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za1_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za2_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za3_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za4_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za5_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za6_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za7_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%next_tile) : (vector<[2]x[2]xi64>) -> () return } // ----- +// CHECK-LABEL: za_d_overlapping_za_q func.func @za_d_overlapping_za_q() { + // CHECK-NEXT: tile_id = 0 %za0_d = arm_sme.get_tile : vector<[2]x[2]xi64> + // CHECK-NEXT: tile_id = 1 %za1_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 2 %za2_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 3 %za3_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 4 %za4_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 5 %za5_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 6 %za6_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 7 %za7_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 9 %za9_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 10 %za10_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 11 %za11_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 12 %za12_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 13 %za13_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 14 %za14_q = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK-NEXT: tile_id = 15 %za15_q = arm_sme.get_tile : vector<[1]x[1]xi128> - // expected-warning @below {{failed to allocate SME virtual tile to operation, all tile operations will go through memory, expect degraded performance}} + // Next tile is in-memory: + // CHECK-NEXT: tile_id = 16 %next_tile = arm_sme.get_tile : vector<[1]x[1]xi128> - return -} - -// ----- - -// CHECK-LABEL: za0_q -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 32768 : i32} -func.func @za0_q() { - // CHECK-NEXT: tile_id = 0 - %za0_q = arm_sme.get_tile : vector<[1]x[1]xi128> + "test.some_use"(%za0_d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%za1_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za2_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za3_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za4_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za5_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za6_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za7_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za9_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za10_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za11_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za12_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za13_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za14_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za15_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%next_tile) : (vector<[1]x[1]xi128>) -> () return } // ----- // CHECK-LABEL: za_q -// CHECK-SAME: attributes {arm_sme.tiles_in_use = 65535 : i32} func.func @za_q() { // CHECK-NEXT: tile_id = 0 %za0_q = arm_sme.get_tile : vector<[1]x[1]xi128> @@ -343,29 +382,25 @@ func.func @za_q() { %za14_q = arm_sme.get_tile : vector<[1]x[1]xi128> // CHECK-NEXT: tile_id = 15 %za15_q = arm_sme.get_tile : vector<[1]x[1]xi128> - return -} - -// ----- - -func.func @za_q__out_of_tiles() { - %za0_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za1_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za2_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za3_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za4_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za5_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za6_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za7_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za8_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za9_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za10_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za11_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za12_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za13_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za14_q = arm_sme.get_tile : vector<[1]x[1]xi128> - %za15_q = arm_sme.get_tile : vector<[1]x[1]xi128> - // expected-warning @below {{failed to allocate SME virtual tile to operation, all tile operations will go through memory, expect degraded performance}} + // Next tile is in-memory: + // CHECK-NEXT: tile_id = 16 %next_tile = arm_sme.get_tile : vector<[1]x[1]xi128> + "test.some_use"(%za0_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za1_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za2_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za3_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za4_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za5_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za6_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za7_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za8_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za9_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za10_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za11_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za12_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za13_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za14_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%za15_q) : (vector<[1]x[1]xi128>) -> () + "test.some_use"(%next_tile) : (vector<[1]x[1]xi128>) -> () return } diff --git a/mlir/test/Dialect/ArmSME/enable-arm-za.mlir b/mlir/test/Dialect/ArmSME/enable-arm-za.mlir index a20203d7e557..d3325513a848 100644 --- a/mlir/test/Dialect/ArmSME/enable-arm-za.mlir +++ b/mlir/test/Dialect/ArmSME/enable-arm-za.mlir @@ -1,10 +1,9 @@ -// RUN: mlir-opt %s -enable-arm-streaming=za-mode=new-za -convert-arm-sme-to-llvm | FileCheck %s -check-prefix=ENABLE-ZA -// RUN: mlir-opt %s -enable-arm-streaming -convert-arm-sme-to-llvm | FileCheck %s -check-prefix=DISABLE-ZA -// RUN: mlir-opt %s -enable-arm-streaming=za-mode=in-za -convert-arm-sme-to-llvm | FileCheck %s -check-prefix=IN-ZA -// RUN: mlir-opt %s -enable-arm-streaming=za-mode=out-za -convert-arm-sme-to-llvm | FileCheck %s -check-prefix=OUT-ZA -// RUN: mlir-opt %s -enable-arm-streaming=za-mode=inout-za -convert-arm-sme-to-llvm | FileCheck %s -check-prefix=INOUT-ZA -// RUN: mlir-opt %s -enable-arm-streaming=za-mode=preserves-za -convert-arm-sme-to-llvm | FileCheck %s -check-prefix=PRESERVES-ZA -// RUN: mlir-opt %s -convert-arm-sme-to-llvm | FileCheck %s -check-prefix=NO-ARM-STREAMING +// RUN: mlir-opt %s -enable-arm-streaming=za-mode=new-za | FileCheck %s -check-prefix=ENABLE-ZA +// RUN: mlir-opt %s -enable-arm-streaming | FileCheck %s -check-prefix=DISABLE-ZA +// RUN: mlir-opt %s -enable-arm-streaming=za-mode=in-za | FileCheck %s -check-prefix=IN-ZA +// RUN: mlir-opt %s -enable-arm-streaming=za-mode=out-za | FileCheck %s -check-prefix=OUT-ZA +// RUN: mlir-opt %s -enable-arm-streaming=za-mode=inout-za | FileCheck %s -check-prefix=INOUT-ZA +// RUN: mlir-opt %s -enable-arm-streaming=za-mode=preserves-za | FileCheck %s -check-prefix=PRESERVES-ZA // CHECK-LABEL: @declaration func.func private @declaration() @@ -22,11 +21,4 @@ func.func private @declaration() // DISABLE-ZA-LABEL: @arm_new_za // DISABLE-ZA-NOT: arm_new_za // DISABLE-ZA-SAME: attributes {arm_streaming} -// NO-ARM-STREAMING-LABEL: @arm_new_za -// NO-ARM-STREAMING-NOT: arm_new_za -// NO-ARM-STREAMING-NOT: arm_streaming -// NO-ARM-STREAMING-NOT: arm_in_za -// NO-ARM-STREAMING-NOT: arm_out_za -// NO-ARM-STREAMING-NOT: arm_inout_za -// NO-ARM-STREAMING-NOT: arm_preserves_za func.func @arm_new_za() { return } diff --git a/mlir/test/Dialect/ArmSME/outer-product-fusion.mlir b/mlir/test/Dialect/ArmSME/outer-product-fusion.mlir index 01f54a4cf186..4887d611643f 100644 --- a/mlir/test/Dialect/ArmSME/outer-product-fusion.mlir +++ b/mlir/test/Dialect/ArmSME/outer-product-fusion.mlir @@ -1,4 +1,4 @@ -// RUN: mlir-opt %s -arm-sme-outer-product-fusion -cse -split-input-file -allow-unregistered-dialect | FileCheck %s +// RUN: mlir-opt %s -arm-sme-outer-product-fusion -cse -split-input-file | FileCheck %s // CHECK-LABEL: @outerproduct_add_widening_2way_f16f16f32 // CHECK-SAME: %[[A0:.*]]: vector<[4]xf16>, %[[B0:.*]]: vector<[4]xf16>, %[[A1:.*]]: vector<[4]xf16>, %[[B1:.*]]: vector<[4]xf16>, @@ -929,6 +929,7 @@ func.func @outerproduct_widening_4way__missing_acc( %2 = arm_sme.outerproduct %a2_ext, %b2_ext acc(%1) : vector<[4]xi32>, vector<[4]xi32> // Missing accumulator breaks use-def chain. %3 = arm_sme.outerproduct %a3_ext, %b3_ext : vector<[4]xi32>, vector<[4]xi32> + "test.some_use"(%2) : (vector<[4]x[4]xi32>) -> () return %3 : vector<[4]x[4]xi32> } @@ -1014,7 +1015,7 @@ func.func @outerproduct_widening_2way__cant_erase( %acc = arith.constant dense<1.0> : vector<[4]x[4]xf32> %0 = arm_sme.outerproduct %a0_ext, %b0_ext acc(%acc) : vector<[4]xf32>, vector<[4]xf32> - "fake.use"(%0) : (vector<[4]x[4]xf32>) -> () + "test.some_use"(%0) : (vector<[4]x[4]xf32>) -> () %1 = arm_sme.outerproduct %a1_ext, %b1_ext acc(%0) : vector<[4]xf32>, vector<[4]xf32> return %1 : vector<[4]x[4]xf32> @@ -1048,7 +1049,7 @@ func.func @outerproduct_widening_4way__multi_use_cant_erase( %0 = arm_sme.outerproduct %a0_ext, %b0_ext : vector<[4]xi32>, vector<[4]xi32> %1 = arm_sme.outerproduct %a1_ext, %b1_ext acc(%0) : vector<[4]xi32>, vector<[4]xi32> - "fake.use"(%1) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%1) : (vector<[4]x[4]xi32>) -> () %2 = arm_sme.outerproduct %a2_ext, %b2_ext acc(%1) : vector<[4]xi32>, vector<[4]xi32> %3 = arm_sme.outerproduct %a3_ext, %b3_ext acc(%2) : vector<[4]xi32>, vector<[4]xi32> diff --git a/mlir/test/Dialect/ArmSME/tile-zero-masks.mlir b/mlir/test/Dialect/ArmSME/tile-zero-masks.mlir index 04412e4db1c5..cac2dcc24d10 100644 --- a/mlir/test/Dialect/ArmSME/tile-zero-masks.mlir +++ b/mlir/test/Dialect/ArmSME/tile-zero-masks.mlir @@ -9,6 +9,7 @@ func.func @zero_za_b() { // CHECK: "arm_sme.intr.zero"() <{tile_mask = 255 : i32}> : () -> () %zero_za0b = arm_sme.zero : vector<[16]x[16]xi8> + "test.some_use"(%zero_za0b) : (vector<[16]x[16]xi8>) -> () return } @@ -16,10 +17,12 @@ func.func @zero_za_b() { // CHECK-LABEL: zero_za_h func.func @zero_za_h() { - // CHECK: "arm_sme.intr.zero"() <{tile_mask = 85 : i32}> : () -> () + // CHECK: "arm_sme.intr.zero"() <{tile_mask = 85 : i32}> : () -> () %zero_za0h = arm_sme.zero : vector<[8]x[8]xi16> - // CHECK-NEXT: "arm_sme.intr.zero"() <{tile_mask = 170 : i32}> : () -> () + // CHECK: "arm_sme.intr.zero"() <{tile_mask = 170 : i32}> : () -> () %zero_za1h = arm_sme.zero : vector<[8]x[8]xf16> + "test.some_use"(%zero_za0h) : (vector<[8]x[8]xi16>) -> () + "test.some_use"(%zero_za1h) : (vector<[8]x[8]xf16>) -> () return } @@ -27,14 +30,18 @@ func.func @zero_za_h() { // CHECK-LABEL: zero_za_s func.func @zero_za_s() { - // CHECK: arm_sme.intr.zero"() <{tile_mask = 17 : i32}> : () -> () + // CHECK: arm_sme.intr.zero"() <{tile_mask = 17 : i32}> : () -> () %zero_za0s = arm_sme.zero : vector<[4]x[4]xi32> - // CHECK-NEXT: arm_sme.intr.zero"() <{tile_mask = 34 : i32}> : () -> () + // CHECK: arm_sme.intr.zero"() <{tile_mask = 34 : i32}> : () -> () %zero_za1s = arm_sme.zero : vector<[4]x[4]xi32> - // CHECK-NEXT: arm_sme.intr.zero"() <{tile_mask = 68 : i32}> : () -> () + // CHECK: arm_sme.intr.zero"() <{tile_mask = 68 : i32}> : () -> () %zero_za2s = arm_sme.zero : vector<[4]x[4]xi32> - // CHECK-NEXT: arm_sme.intr.zero"() <{tile_mask = 136 : i32}> : () -> () + // CHECK: arm_sme.intr.zero"() <{tile_mask = 136 : i32}> : () -> () %zero_za3s = arm_sme.zero : vector<[4]x[4]xf32> + "test.some_use"(%zero_za0s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%zero_za1s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%zero_za2s) : (vector<[4]x[4]xi32>) -> () + "test.some_use"(%zero_za3s) : (vector<[4]x[4]xf32>) -> () return } @@ -42,21 +49,29 @@ func.func @zero_za_s() { // CHECK-LABEL: zero_za_d func.func @zero_za_d() { - // CHECK: "arm_sme.intr.zero"() <{tile_mask = 1 : i32}> : () -> () + // CHECK: "arm_sme.intr.zero"() <{tile_mask = 1 : i32}> : () -> () %zero_za0d = arm_sme.zero : vector<[2]x[2]xi64> - // CHECK-NEXT: "arm_sme.intr.zero"() <{tile_mask = 2 : i32}> : () -> () + // CHECK: "arm_sme.intr.zero"() <{tile_mask = 2 : i32}> : () -> () %zero_za1d = arm_sme.zero : vector<[2]x[2]xi64> - // CHECK-NEXT: "arm_sme.intr.zero"() <{tile_mask = 4 : i32}> : () -> () + // CHECK: "arm_sme.intr.zero"() <{tile_mask = 4 : i32}> : () -> () %zero_za2d = arm_sme.zero : vector<[2]x[2]xi64> - // CHECK-NEXT: "arm_sme.intr.zero"() <{tile_mask = 8 : i32}> : () -> () + // CHECK: "arm_sme.intr.zero"() <{tile_mask = 8 : i32}> : () -> () %zero_za3d = arm_sme.zero : vector<[2]x[2]xi64> - // CHECK-NEXT: "arm_sme.intr.zero"() <{tile_mask = 16 : i32}> : () -> () + // CHECK: "arm_sme.intr.zero"() <{tile_mask = 16 : i32}> : () -> () %zero_za4d = arm_sme.zero : vector<[2]x[2]xi64> - // CHECK-NEXT: "arm_sme.intr.zero"() <{tile_mask = 32 : i32}> : () -> () + // CHECK: "arm_sme.intr.zero"() <{tile_mask = 32 : i32}> : () -> () %zero_za5d = arm_sme.zero : vector<[2]x[2]xi64> - // CHECK-NEXT: "arm_sme.intr.zero"() <{tile_mask = 64 : i32}> : () -> () + // CHECK: "arm_sme.intr.zero"() <{tile_mask = 64 : i32}> : () -> () %zero_za6d = arm_sme.zero : vector<[2]x[2]xi64> - // CHECK-NEXT: "arm_sme.intr.zero"() <{tile_mask = 128 : i32}> : () -> () + // CHECK: "arm_sme.intr.zero"() <{tile_mask = 128 : i32}> : () -> () %zero_za7d = arm_sme.zero : vector<[2]x[2]xf64> + "test.some_use"(%zero_za0d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%zero_za1d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%zero_za2d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%zero_za3d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%zero_za4d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%zero_za5d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%zero_za6d) : (vector<[2]x[2]xi64>) -> () + "test.some_use"(%zero_za7d) : (vector<[2]x[2]xf64>) -> () return } -- GitLab From dd4bf22b9380e797362fac1415a1796da338b2db Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 8 May 2024 10:21:41 +0100 Subject: [PATCH 008/328] [X86] combineBlendOfPermutes - don't introduce lane-crossing permutes without AVX2 support. Fixes #91433 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 19 ++++++++++------ .../test/CodeGen/X86/vector-shuffle-256-v4.ll | 22 +++++++++++++++++++ .../X86/vector-shuffle-combining-avx.ll | 3 ++- 3 files changed, 36 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 8ec4984dfa55..3ae68c438aa7 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -40078,10 +40078,10 @@ static SDValue combineCommutableSHUFP(SDValue N, MVT VT, const SDLoc &DL, // Attempt to fold BLEND(PERMUTE(X),PERMUTE(Y)) -> PERMUTE(BLEND(X,Y)) // iff we don't demand the same element index for both X and Y. -static SDValue combineBlendOfPermutes(MVT VT, SDValue N0, SDValue N1, - ArrayRef BlendMask, - const APInt &DemandedElts, - SelectionDAG &DAG, const SDLoc &DL) { +static SDValue +combineBlendOfPermutes(MVT VT, SDValue N0, SDValue N1, ArrayRef BlendMask, + const APInt &DemandedElts, SelectionDAG &DAG, + const X86Subtarget &Subtarget, const SDLoc &DL) { assert(isBlendOrUndef(BlendMask) && "Blend shuffle expected"); if (!N0.hasOneUse() || !N1.hasOneUse()) return SDValue(); @@ -40156,6 +40156,11 @@ static SDValue combineBlendOfPermutes(MVT VT, SDValue N0, SDValue N1, return SDValue(); } + // Don't introduce lane-crossing permutes without AVX2. + if (VT.is256BitVector() && !Subtarget.hasAVX2() && + isLaneCrossingShuffleMask(128, VT.getScalarSizeInBits(), NewPermuteMask)) + return SDValue(); + SDValue NewBlend = DAG.getVectorShuffle(VT, DL, DAG.getBitcast(VT, Ops0[0]), DAG.getBitcast(VT, Ops1[0]), NewBlendMask); @@ -41918,9 +41923,9 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode( case X86ISD::BLENDI: { SmallVector BlendMask; DecodeBLENDMask(NumElts, Op.getConstantOperandVal(2), BlendMask); - if (SDValue R = combineBlendOfPermutes(VT.getSimpleVT(), Op.getOperand(0), - Op.getOperand(1), BlendMask, - DemandedElts, TLO.DAG, SDLoc(Op))) + if (SDValue R = combineBlendOfPermutes( + VT.getSimpleVT(), Op.getOperand(0), Op.getOperand(1), BlendMask, + DemandedElts, TLO.DAG, Subtarget, SDLoc(Op))) return TLO.CombineTo(Op, R); break; } diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll index bc95fd42e6b8..ced9304f4c59 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll @@ -699,6 +699,28 @@ define <4 x double> @shuffle_v4f64_0437(<4 x double> %a, <4 x double> %b) { ret <4 x double> %shuffle } +; PR91433 +define <4 x double> @shuffle_v4f64_2303(<4 x double> %a) { +; AVX1-LABEL: shuffle_v4f64_2303: +; AVX1: # %bb.0: +; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,2,3] +; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1] +; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] +; AVX1-NEXT: retq +; +; AVX2-LABEL: shuffle_v4f64_2303: +; AVX2: # %bb.0: +; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,3,0,3] +; AVX2-NEXT: retq +; +; AVX512VL-LABEL: shuffle_v4f64_2303: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,3,0,3] +; AVX512VL-NEXT: retq + %shuffle = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> + ret <4 x double> %shuffle +} + define <4 x double> @shuffle_v4f64_0z3z(<4 x double> %a, <4 x double> %b) { ; ALL-LABEL: shuffle_v4f64_0z3z: ; ALL: # %bb.0: diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll index 81ce14132c87..0c65f756f296 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll @@ -308,8 +308,9 @@ define <4 x float> @combine_vpermilvar_4f32_as_insertps(<4 x float> %a0) { define <8 x i32> @combine_blend_of_permutes_v8i32(<4 x i64> %a0, <4 x i64> %a1) { ; AVX1-LABEL: combine_blend_of_permutes_v8i32: ; AVX1: # %bb.0: -; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1] +; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm1[2,3,0,1] +; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3,4],ymm0[5,6],ymm1[7] ; AVX1-NEXT: ret{{[l|q]}} ; ; AVX2-LABEL: combine_blend_of_permutes_v8i32: -- GitLab From 8f21294897befee48f9f72734ea1b0ad4c920aa0 Mon Sep 17 00:00:00 2001 From: YunQiang Su Date: Wed, 8 May 2024 17:30:14 +0800 Subject: [PATCH 009/328] MIPS: Use pcrel|sdata4 for eh_frame (#91291) Gas uses encoding DW_EH_PE_absptr for PIC, and gnu ld converts it to DW_EH_PE_sdata4|DW_EH_PE_pcrel. LLD doesn't have this workarounding, thus complains ``` relocation R_MIPS_32 cannot be used against local symbol; recompile with -fPIC relocation R_MIPS_64 cannot be used against local symbol; recompile with -fPIC ``` So, let's generates asm/obj files with `DW_EH_PE_sdata4|DW_EH_PE_pcrel` encoding. In fact, GNU ld supports such OBJs well. For N64, maybe we should use sdata8, while GNU ld doesn't support it well, and in fact sdata4 is enough now. So we just ignore the `Large` for `MCObjectFileInfo::initELFMCObjectFileInfo`. Maybe we should switch back to sdata8 once GNU LD supports it well. Fixes: #58377. --- lld/test/ELF/mips-eh_frame-pic.s | 8 +++++--- llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | 4 +--- llvm/lib/MC/MCObjectFileInfo.cpp | 4 +++- llvm/test/CodeGen/Mips/ehframe-indirect.ll | 6 +++--- llvm/test/DebugInfo/Mips/eh_frame.ll | 6 +++--- llvm/test/MC/Mips/eh-frame.s | 9 ++++----- 6 files changed, 19 insertions(+), 18 deletions(-) diff --git a/lld/test/ELF/mips-eh_frame-pic.s b/lld/test/ELF/mips-eh_frame-pic.s index c04dbdf57b08..79076e74a7e3 100644 --- a/lld/test/ELF/mips-eh_frame-pic.s +++ b/lld/test/ELF/mips-eh_frame-pic.s @@ -16,7 +16,7 @@ # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux --position-independent %s -o %t-pic.o # RUN: llvm-readobj -r %t-pic.o | FileCheck %s --check-prefixes=RELOCS,PIC64-RELOCS # RUN: ld.lld -shared %t-pic.o -o %t-pic.so -# RUN: llvm-dwarfdump --eh-frame %t-pic.so | FileCheck %s --check-prefix=PIC-EH-FRAME +# RUN: llvm-dwarfdump --eh-frame %t-pic.so | FileCheck %s --check-prefix=PIC64-EH-FRAME ## Also check MIPS32: # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t-nopic32.o @@ -31,7 +31,7 @@ # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux --position-independent %s -o %t-pic32.o # RUN: llvm-readobj -r %t-pic32.o | FileCheck %s --check-prefixes=RELOCS,PIC32-RELOCS # RUN: ld.lld -shared %t-pic32.o -o %t-pic32.so -# RUN: llvm-dwarfdump --eh-frame %t-pic32.so | FileCheck %s --check-prefix=PIC-EH-FRAME +# RUN: llvm-dwarfdump --eh-frame %t-pic32.so | FileCheck %s --check-prefix=PIC32-EH-FRAME # RELOCS: .rel{{a?}}.eh_frame { # ABS32-RELOCS-NEXT: 0x1C R_MIPS_32 .text @@ -44,7 +44,9 @@ ## ^^ fde pointer encoding: DW_EH_PE_sdata8 # ABS32-EH-FRAME: Augmentation data: 0B ## ^^ fde pointer encoding: DW_EH_PE_sdata4 -# PIC-EH-FRAME: Augmentation data: 1B +# PIC32-EH-FRAME: Augmentation data: 1B +## ^^ fde pointer encoding: DW_EH_PE_pcrel | DW_EH_PE_sdata4 +# PIC64-EH-FRAME: Augmentation data: 1B ## ^^ fde pointer encoding: DW_EH_PE_pcrel | DW_EH_PE_sdata4 ## Note: ld.bfd converts the R_MIPS_64 relocs to DW_EH_PE_pcrel | DW_EH_PE_sdata8 ## for N64 ABI (and DW_EH_PE_pcrel | DW_EH_PE_sdata4 for MIPS32) diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp index 622773cc73f7..3e1897ce670a 100644 --- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp +++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp @@ -212,13 +212,11 @@ void TargetLoweringObjectFileELF::Initialize(MCContext &Ctx, // identify N64 from just a triple. TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; - // We don't support PC-relative LSDA references in GAS so we use the default - // DW_EH_PE_absptr for those. // FreeBSD must be explicit about the data size and using pcrel since it's // assembler/linker won't do the automatic conversion that the Linux tools // do. - if (TgtM.getTargetTriple().isOSFreeBSD()) { + if (isPositionIndependent() || TgtM.getTargetTriple().isOSFreeBSD()) { PersonalityEncoding |= dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; LSDAEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; } diff --git a/llvm/lib/MC/MCObjectFileInfo.cpp b/llvm/lib/MC/MCObjectFileInfo.cpp index 1f8f8ec55727..045b566aae78 100644 --- a/llvm/lib/MC/MCObjectFileInfo.cpp +++ b/llvm/lib/MC/MCObjectFileInfo.cpp @@ -343,7 +343,9 @@ void MCObjectFileInfo::initELFMCObjectFileInfo(const Triple &T, bool Large) { case Triple::mips64el: // We cannot use DW_EH_PE_sdata8 for the large PositionIndependent case // since there is no R_MIPS_PC64 relocation (only a 32-bit version). - if (PositionIndependent && !Large) + // In fact DW_EH_PE_sdata4 is enough for us now, and GNU ld doesn't + // support pcrel|sdata8 well. Let's use sdata4 for now. + if (PositionIndependent) FDECFIEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; else FDECFIEncoding = Ctx->getAsmInfo()->getCodePointerSize() == 4 diff --git a/llvm/test/CodeGen/Mips/ehframe-indirect.ll b/llvm/test/CodeGen/Mips/ehframe-indirect.ll index e36fa2f9ce42..1cd2b86a8e15 100644 --- a/llvm/test/CodeGen/Mips/ehframe-indirect.ll +++ b/llvm/test/CodeGen/Mips/ehframe-indirect.ll @@ -17,9 +17,9 @@ define i32 @main() personality ptr @__gxx_personality_v0 { ; ALL: .cfi_startproc ; Linux must rely on the assembler/linker converting the encodings. -; LINUX: .cfi_personality 128, DW.ref.__gxx_personality_v0 -; LINUX-O32: .cfi_lsda 0, $exception0 -; LINUX-NEW: .cfi_lsda 0, .Lexception0 +; LINUX: .cfi_personality 155, DW.ref.__gxx_personality_v0 +; LINUX-O32: .cfi_lsda 27, $exception0 +; LINUX-NEW: .cfi_lsda 27, .Lexception0 ; FreeBSD can (and must) be more direct about the encodings it wants. ; FREEBSD: .cfi_personality 155, DW.ref.__gxx_personality_v0 diff --git a/llvm/test/DebugInfo/Mips/eh_frame.ll b/llvm/test/DebugInfo/Mips/eh_frame.ll index 60d4dc76777e..d53bc156ef29 100644 --- a/llvm/test/DebugInfo/Mips/eh_frame.ll +++ b/llvm/test/DebugInfo/Mips/eh_frame.ll @@ -17,9 +17,9 @@ ; STATIC-DAG: R_MIPS_32 00000000 .gcc_except_table ; PIC-LABEL: Relocation section '.rel.eh_frame' -; PIC-DAG: R_MIPS_32 00000000 DW.ref.__gxx_personality_v0 -; PIC-DAG: R_MIPS_PC32 -; PIC-DAG: R_MIPS_32 00000000 .gcc_except_table +; PIC-DAG: R_MIPS_PC32 00000000 DW.ref.__gxx_personality_v0 +; PIC-DAG: R_MIPS_PC32 00000000 .L0 +; PIC-DAG: R_MIPS_PC32 00000000 .L0 ; CHECK-READELF: DW.ref.__gxx_personality_v0 ; CHECK-READELF-STATIC-NEXT: R_MIPS_32 00000000 .text diff --git a/llvm/test/MC/Mips/eh-frame.s b/llvm/test/MC/Mips/eh-frame.s index fd145317bf4d..dac142325f9f 100644 --- a/llvm/test/MC/Mips/eh-frame.s +++ b/llvm/test/MC/Mips/eh-frame.s @@ -33,14 +33,13 @@ // RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,PIC64 %s // RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_PIC %s -/// However using the large code model forces R_MIPS_64 since there is no R_MIPS_PC64 relocation: // RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips64-unknown-linux-gnu --position-independent --large-code-model -// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,ABS64 %s -// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_ABS %s +// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,PIC64 %s +// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_PIC %s // RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips64el-unknown-linux-gnu --position-independent --large-code-model -// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,ABS64 %s -// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_ABS %s +// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,PIC64 %s +// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_PIC %s func: .cfi_startproc -- GitLab From df311a27629618f6ba645bfe3f46e981000cb5da Mon Sep 17 00:00:00 2001 From: Aleksandr Popov <42888396+aleks-tmb@users.noreply.github.com> Date: Wed, 8 May 2024 11:54:49 +0200 Subject: [PATCH 010/328] Add interface to check if a call has a deopt bundle (NFC) (#91348) Encapsulate check that a call has a deopt bundle to make it easier to change the deopt scheme. --- llvm/include/llvm/IR/InstrTypes.h | 5 +++++ llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 ++-- llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp | 3 +-- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/IR/InstrTypes.h b/llvm/include/llvm/IR/InstrTypes.h index b9af3a6ca42c..eaade9ce4755 100644 --- a/llvm/include/llvm/IR/InstrTypes.h +++ b/llvm/include/llvm/IR/InstrTypes.h @@ -2614,6 +2614,11 @@ public: op_iterator populateBundleOperandInfos(ArrayRef Bundles, const unsigned BeginIndex); + /// Return true if the call has deopt state bundle. + bool hasDeoptState() const { + return getOperandBundle(LLVMContext::OB_deopt).has_value(); + } + public: /// Return the BundleOpInfo for the operand at index OpIdx. /// diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 6661127162e5..5289b993476d 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -2851,7 +2851,7 @@ bool IRTranslator::translateInvoke(const User &U, return false; // FIXME: support whatever these are. - if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) + if (I.hasDeoptState()) return false; // FIXME: support control flow guard targets. diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index f47aea29625f..55aed43070df 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -3357,7 +3357,7 @@ void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { break; } } - } else if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) { + } else if (I.hasDeoptState()) { // Currently we do not lower any intrinsic calls with deopt operand bundles. // Eventually we will support lowering the @llvm.experimental.deoptimize // intrinsic, and right now there are no plans to support other intrinsics @@ -9197,7 +9197,7 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) { SDValue Callee = getValue(I.getCalledOperand()); - if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) + if (I.hasDeoptState()) LowerCallSiteWithDeoptBundle(&I, Callee, nullptr); else // Check if we can potentially perform a tail call. More detailed checking diff --git a/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp b/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp index 286273c897aa..858e54c4a9bc 100644 --- a/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp +++ b/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp @@ -3046,8 +3046,7 @@ bool RewriteStatepointsForGC::runOnFunction(Function &F, DominatorTree &DT, // which doesn't know how to produce a proper deopt state. So if we see a // non-leaf memcpy/memmove without deopt state just treat it as a leaf // copy and don't produce a statepoint. - if (!AllowStatepointWithNoDeoptInfo && - !Call->getOperandBundle(LLVMContext::OB_deopt)) { + if (!AllowStatepointWithNoDeoptInfo && !Call->hasDeoptState()) { assert((isa(Call) || isa(Call)) && "Don't expect any other calls here!"); return false; -- GitLab From d4fef93724e290a82d498f0d8df1a84a5ff50ab3 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Wed, 8 May 2024 11:57:19 +0200 Subject: [PATCH 011/328] [bazel][libc] Split up mutex libraries like ab3a9e724d87a4272782f76b90fb0872a6a86939 did --- .../llvm-project-overlay/libc/BUILD.bazel | 34 ++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index aa9f665c350a..055630cb6a00 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -1090,6 +1090,38 @@ libc_support_library( ], ) +libc_support_library( + name = "__support_threads_linux_futex_word_type", + hdrs = [ + "src/__support/threads/linux/futex_word.h", + ], + target_compatible_with = select({ + "@platforms//os:linux": [], + "//conditions:default": ["@platforms//:incompatible"], + }), + deps = [ + ":__support_osutil_syscall", + ], +) + +libc_support_library( + name = "__support_threads_linux_futex_utils", + hdrs = [ + "src/__support/threads/linux/futex_utils.h", + ], + target_compatible_with = select({ + "@platforms//os:linux": [], + "//conditions:default": ["@platforms//:incompatible"], + }), + deps = [ + ":__support_cpp_atomic", + ":__support_cpp_optional", + ":__support_osutil_syscall", + ":__support_threads_linux_futex_word_type", + ":types_struct_timespec", + ], +) + libc_support_library( name = "__support_threads_mutex", hdrs = [ @@ -1102,11 +1134,11 @@ libc_support_library( }), textual_hdrs = [ "src/__support/threads/linux/mutex.h", - "src/__support/threads/linux/futex_word.h", ], deps = [ ":__support_cpp_atomic", ":__support_osutil_syscall", + ":__support_threads_linux_futex_utils", ], ) -- GitLab From aefad851672e6dd17592895066a39aa5b388e5db Mon Sep 17 00:00:00 2001 From: Kadir Cetinkaya Date: Wed, 8 May 2024 10:23:39 +0200 Subject: [PATCH 012/328] [clangd] Fix data race surfaced in clangd-tsan buildbot We can have concurrent accesses to same PreambleData (e.g. code-completion and ast-builds). Hence we need to deep copy TargetOpts. --- clang-tools-extra/clangd/Preamble.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/clang-tools-extra/clangd/Preamble.cpp b/clang-tools-extra/clangd/Preamble.cpp index d5818e0ca309..ecd490145dd3 100644 --- a/clang-tools-extra/clangd/Preamble.cpp +++ b/clang-tools-extra/clangd/Preamble.cpp @@ -918,7 +918,9 @@ void PreamblePatch::apply(CompilerInvocation &CI) const { // no guarantees around using arbitrary options when reusing PCHs, and // different target opts can result in crashes, see // ParsedASTTest.PreambleWithDifferentTarget. - CI.TargetOpts = Baseline->TargetOpts; + // Make sure this is a deep copy, as the same Baseline might be used + // concurrently. + *CI.TargetOpts = *Baseline->TargetOpts; // No need to map an empty file. if (PatchContents.empty()) -- GitLab From 341aecc2dd0f6debcbe9f251a6d2e8a60d327eea Mon Sep 17 00:00:00 2001 From: Weaver Date: Wed, 8 May 2024 11:12:14 +0100 Subject: [PATCH 013/328] =?UTF-8?q?Revert=20"Revert=20"Revert=20"[OpenMP][?= =?UTF-8?q?TR12]=20change=20property=20of=20map-type=20modifier."=E2=80=A6?= =?UTF-8?q?=20(#91141)"?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit a99ce615f19fec6fbb835490b89f53cba3cf9eff. Caused test failure on following buildbot: https://lab.llvm.org/buildbot/#/builders/139/builds/65066 --- .../clang/Basic/DiagnosticParseKinds.td | 5 - clang/lib/Parse/ParseOpenMP.cpp | 51 ++------- clang/test/OpenMP/target_ast_print.cpp | 58 ---------- clang/test/OpenMP/target_map_messages.cpp | 105 ++++++++---------- 4 files changed, 54 insertions(+), 165 deletions(-) diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td index 44bc4e0e130d..fdffb35ea0d9 100644 --- a/clang/include/clang/Basic/DiagnosticParseKinds.td +++ b/clang/include/clang/Basic/DiagnosticParseKinds.td @@ -1438,9 +1438,6 @@ def err_omp_decl_in_declare_simd_variant : Error< def err_omp_sink_and_source_iteration_not_allowd: Error<" '%0 %select{sink:|source:}1' must be with '%select{omp_cur_iteration - 1|omp_cur_iteration}1'">; def err_omp_unknown_map_type : Error< "incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'">; -def err_omp_more_one_map_type : Error<"map type is already specified">; -def note_previous_map_type_specified_here - : Note<"map type '%0' is previous specified here">; def err_omp_unknown_map_type_modifier : Error< "incorrect map type modifier, expected one of: 'always', 'close', 'mapper'" "%select{|, 'present'|, 'present', 'iterator'}0%select{|, 'ompx_hold'}1">; @@ -1448,8 +1445,6 @@ def err_omp_map_type_missing : Error< "missing map type">; def err_omp_map_type_modifier_missing : Error< "missing map type modifier">; -def err_omp_map_modifier_specification_list : Error< - "empty modifier-specification-list is not allowed">; def err_omp_declare_simd_inbranch_notinbranch : Error< "unexpected '%0' clause, '%1' is specified already">; def err_omp_expected_clause_argument diff --git a/clang/lib/Parse/ParseOpenMP.cpp b/clang/lib/Parse/ParseOpenMP.cpp index 5265d8f1922c..18ba1185ee8d 100644 --- a/clang/lib/Parse/ParseOpenMP.cpp +++ b/clang/lib/Parse/ParseOpenMP.cpp @@ -4228,20 +4228,13 @@ bool Parser::parseMapperModifier(SemaOpenMP::OpenMPVarListDataTy &Data) { return T.consumeClose(); } -static OpenMPMapClauseKind isMapType(Parser &P); - /// Parse map-type-modifiers in map clause. -/// map([ [map-type-modifier[,] [map-type-modifier[,] ...] [map-type] : ] list) +/// map([ [map-type-modifier[,] [map-type-modifier[,] ...] map-type : ] list) /// where, map-type-modifier ::= always | close | mapper(mapper-identifier) | /// present -/// where, map-type ::= alloc | delete | from | release | to | tofrom bool Parser::parseMapTypeModifiers(SemaOpenMP::OpenMPVarListDataTy &Data) { - bool HasMapType = false; - SourceLocation PreMapLoc = Tok.getLocation(); - StringRef PreMapName = ""; while (getCurToken().isNot(tok::colon)) { OpenMPMapModifierKind TypeModifier = isMapModifier(*this); - OpenMPMapClauseKind MapKind = isMapType(*this); if (TypeModifier == OMPC_MAP_MODIFIER_always || TypeModifier == OMPC_MAP_MODIFIER_close || TypeModifier == OMPC_MAP_MODIFIER_present || @@ -4264,19 +4257,6 @@ bool Parser::parseMapTypeModifiers(SemaOpenMP::OpenMPVarListDataTy &Data) { Diag(Data.MapTypeModifiersLoc.back(), diag::err_omp_missing_comma) << "map type modifier"; - } else if (getLangOpts().OpenMP >= 60 && MapKind != OMPC_MAP_unknown) { - if (!HasMapType) { - HasMapType = true; - Data.ExtraModifier = MapKind; - MapKind = OMPC_MAP_unknown; - PreMapLoc = Tok.getLocation(); - PreMapName = Tok.getIdentifierInfo()->getName(); - } else { - Diag(Tok, diag::err_omp_more_one_map_type); - Diag(PreMapLoc, diag::note_previous_map_type_specified_here) - << PreMapName; - } - ConsumeToken(); } else { // For the case of unknown map-type-modifier or a map-type. // Map-type is followed by a colon; the function returns when it @@ -4287,14 +4267,8 @@ bool Parser::parseMapTypeModifiers(SemaOpenMP::OpenMPVarListDataTy &Data) { continue; } // Potential map-type token as it is followed by a colon. - if (PP.LookAhead(0).is(tok::colon)) { - if (getLangOpts().OpenMP >= 60) { - break; - } else { - return false; - } - } - + if (PP.LookAhead(0).is(tok::colon)) + return false; Diag(Tok, diag::err_omp_unknown_map_type_modifier) << (getLangOpts().OpenMP >= 51 ? (getLangOpts().OpenMP >= 52 ? 2 : 1) : 0) @@ -4304,14 +4278,6 @@ bool Parser::parseMapTypeModifiers(SemaOpenMP::OpenMPVarListDataTy &Data) { if (getCurToken().is(tok::comma)) ConsumeToken(); } - if (getLangOpts().OpenMP >= 60 && !HasMapType) { - if (!Tok.is(tok::colon)) { - Diag(Tok, diag::err_omp_unknown_map_type); - ConsumeToken(); - } else { - Data.ExtraModifier = OMPC_MAP_unknown; - } - } return false; } @@ -4323,12 +4289,13 @@ static OpenMPMapClauseKind isMapType(Parser &P) { if (!Tok.isOneOf(tok::identifier, tok::kw_delete)) return OMPC_MAP_unknown; Preprocessor &PP = P.getPreprocessor(); - unsigned MapType = - getOpenMPSimpleClauseType(OMPC_map, PP.getSpelling(Tok), P.getLangOpts()); + OpenMPMapClauseKind MapType = + static_cast(getOpenMPSimpleClauseType( + OMPC_map, PP.getSpelling(Tok), P.getLangOpts())); if (MapType == OMPC_MAP_to || MapType == OMPC_MAP_from || MapType == OMPC_MAP_tofrom || MapType == OMPC_MAP_alloc || MapType == OMPC_MAP_delete || MapType == OMPC_MAP_release) - return static_cast(MapType); + return MapType; return OMPC_MAP_unknown; } @@ -4712,10 +4679,8 @@ bool Parser::ParseOpenMPVarList(OpenMPDirectiveKind DKind, // Only parse map-type-modifier[s] and map-type if a colon is present in // the map clause. if (ColonPresent) { - if (getLangOpts().OpenMP >= 60 && getCurToken().is(tok::colon)) - Diag(Tok, diag::err_omp_map_modifier_specification_list); IsInvalidMapperModifier = parseMapTypeModifiers(Data); - if (getLangOpts().OpenMP < 60 && !IsInvalidMapperModifier) + if (!IsInvalidMapperModifier) parseMapType(*this, Data); else SkipUntil(tok::colon, tok::annot_pragma_openmp_end, StopBeforeMatch); diff --git a/clang/test/OpenMP/target_ast_print.cpp b/clang/test/OpenMP/target_ast_print.cpp index ac5ed285d97e..f4c10fe3a181 100644 --- a/clang/test/OpenMP/target_ast_print.cpp +++ b/clang/test/OpenMP/target_ast_print.cpp @@ -1201,64 +1201,6 @@ foo(); } #endif // OMP52 -#ifdef OMP60 - -///==========================================================================/// -// RUN: %clang_cc1 -DOMP60 -verify -Wno-vla -fopenmp -fopenmp-version=60 -ast-print %s | FileCheck %s --check-prefix OMP60 -// RUN: %clang_cc1 -DOMP60 -fopenmp -fopenmp-version=60 -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP60 -fopenmp -fopenmp-version=60 -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefix OMP60 - -// RUN: %clang_cc1 -DOMP60 -verify -Wno-vla -fopenmp-simd -fopenmp-version=60 -ast-print %s | FileCheck %s --check-prefix OMP60 -// RUN: %clang_cc1 -DOMP60 -fopenmp-simd -fopenmp-version=60 -x c++ -std=c++11 -emit-pch -o %t %s -// RUN: %clang_cc1 -DOMP60 -fopenmp-simd -fopenmp-version=60 -std=c++11 -include-pch %t -fsyntax-only -verify -Wno-vla %s -ast-print | FileCheck %s --check-prefix OMP60 - -void foo() {} -template -T tmain(T argc, T *argv) { - T i; -#pragma omp target map(from always: i) - foo(); -#pragma omp target map(from, close: i) - foo(); -#pragma omp target map(always,close: i) - foo(); - return 0; -} -//OMP60: template T tmain(T argc, T *argv) { -//OMP60-NEXT: T i; -//OMP60-NEXT: #pragma omp target map(always,from: i) -//OMP60-NEXT: foo(); -//OMP60-NEXT: #pragma omp target map(close,from: i) -//OMP60-NEXT: foo(); -//OMP60-NEXT: #pragma omp target map(always,close,tofrom: i) -//OMP60-NEXT: foo(); -//OMP60-NEXT: return 0; -//OMP60-NEXT:} -//OMP60: template<> int tmain(int argc, int *argv) { -//OMP60-NEXT: int i; -//OMP60-NEXT: #pragma omp target map(always,from: i) -//OMP60-NEXT: foo(); -//OMP60-NEXT: #pragma omp target map(close,from: i) -//OMP60-NEXT: foo(); -//OMP60-NEXT: #pragma omp target map(always,close,tofrom: i) -//OMP60-NEXT: foo(); -//OMP60-NEXT: return 0; -//OMP60-NEXT:} -//OMP60: template<> char tmain(char argc, char *argv) { -//OMP60-NEXT: char i; -//OMP60-NEXT: #pragma omp target map(always,from: i) -//OMP60-NEXT: foo(); -//OMP60-NEXT: #pragma omp target map(close,from: i) -//OMP60-NEXT: foo(); -//OMP60-NEXT: #pragma omp target map(always,close,tofrom: i) -//OMP60-NEXT: foo(); -//OMP60-NEXT: return 0; -//OMP60-NEXT:} -int main (int argc, char **argv) { - return tmain(argc, &argc) + tmain(argv[0][0], argv[0]); -} -#endif // OMP60 - #ifdef OMPX // RUN: %clang_cc1 -DOMPX -verify -Wno-vla -fopenmp -fopenmp-extensions -ast-print %s | FileCheck %s --check-prefix=OMPX diff --git a/clang/test/OpenMP/target_map_messages.cpp b/clang/test/OpenMP/target_map_messages.cpp index 3bd432b47e63..a6776ee12c0e 100644 --- a/clang/test/OpenMP/target_map_messages.cpp +++ b/clang/test/OpenMP/target_map_messages.cpp @@ -1,35 +1,34 @@ // -fopenmp, -fno-openmp-extensions -// RUN: %clang_cc1 -verify=expected,ge50,lt51,lt60,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,lt50,lt51,lt60,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,lt50,lt51,lt60,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,ge50,lt51,lt60,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,ge50,ge51,lt60,omp,ge51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=51 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,ge50,ge51,ge52,lt60,omp,ge52-omp,omp52 -fopenmp -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,ge50,ge52,ge60,omp,ge60-omp,omp60 -fopenmp -fno-openmp-extensions -fopenmp-version=60 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp,lt51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,ge51,omp,ge51-omp -fopenmp -fno-openmp-extensions -fopenmp-version=51 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,ge51,ge52,omp,ge52-omp,omp52 -fopenmp -fno-openmp-extensions -fopenmp-version=52 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla // RUN: %clang_cc1 -DCCODE -verify -fopenmp -fno-openmp-extensions -ferror-limit 300 -x c %s -Wno-openmp -Wuninitialized -Wno-vla // -fopenmp-simd, -fno-openmp-extensions -// RUN: %clang_cc1 -verify=expected,ge50,lt51,lt60,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,lt50,lt51,lt60,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,lt50,lt51,lt60,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,ge50,lt51,lt60,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,ge50,ge51,lt60,omp,ge51-omp -fopenmp-simd -fno-openmp-extensions -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,lt51,omp,lt51-omp -fopenmp-simd -fno-openmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,ge51,omp,ge51-omp -fopenmp-simd -fno-openmp-extensions -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla // RUN: %clang_cc1 -DCCODE -verify -fopenmp-simd -fno-openmp-extensions -ferror-limit 300 -x c %s -Wno-openmp-mapping -Wuninitialized -Wno-vla // -fopenmp -fopenmp-extensions -// RUN: %clang_cc1 -verify=expected,ge50,lt51,lt60,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,lt50,lt51,lt60,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,lt50,lt51,lt60,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,ge50,lt51,lt60,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,ge50,ge51,lt60,ompx,ge51-ompx -fopenmp -fopenmp-extensions -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,lt51,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,lt51,ompx,lt51-ompx -fopenmp -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,ge51,ompx,ge51-ompx -fopenmp -fopenmp-extensions -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla // RUN: %clang_cc1 -DCCODE -verify -fopenmp -fopenmp-extensions -ferror-limit 300 -x c %s -Wno-openmp -Wuninitialized -Wno-vla // -fopenmp-simd -fopenmp-extensions -// RUN: %clang_cc1 -verify=expected,ge50,lt51,lt60,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,lt50,lt51,lt60,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,lt50,lt51,lt60,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,ge50,lt51,lt60,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla -// RUN: %clang_cc1 -verify=expected,ge50,ge51,lt60,ompx,ge51-ompx -fopenmp-simd -fopenmp-extensions -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,lt51,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=40 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,lt50,lt51,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=45 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,lt51,ompx,lt51-ompx -fopenmp-simd -fopenmp-extensions -fopenmp-version=50 -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla +// RUN: %clang_cc1 -verify=expected,ge50,ge51,ompx,ge51-ompx -fopenmp-simd -fopenmp-extensions -ferror-limit 300 %s -Wno-openmp-target -Wuninitialized -Wno-vla // RUN: %clang_cc1 -DCCODE -verify -fopenmp-simd -fopenmp-extensions -ferror-limit 300 -x c %s -Wno-openmp-mapping -Wuninitialized -Wno-vla // Check @@ -114,7 +113,7 @@ struct SA { #pragma omp target map(b[true:true]) {} - #pragma omp target map(: c,f) // lt60-error {{missing map type}} // ge60-error {{empty modifier-specification-list is not allowed}} + #pragma omp target map(: c,f) // expected-error {{missing map type}} {} #pragma omp target map(always, tofrom: c,f) {} @@ -160,28 +159,28 @@ struct SA { // expected-error@+1 {{use of undeclared identifier 'present'}} #pragma omp target map(present) {} - // ge52-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} + // ge52-omp-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} // ge51-omp-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-omp-error@+1 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} #pragma omp target map(ompx_hold, tofrom: c,f) {} - // ge52-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} + // ge52-omp-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} // ge51-omp-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-omp-error@+1 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} #pragma omp target map(ompx_hold, tofrom: c[1:2],f) {} - // ge52-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} + // ge52-omp-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} // ge51-omp-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-omp-error@+1 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} #pragma omp target map(ompx_hold, tofrom: c,f[1:2]) {} - // ge52-error@+4 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} + // ge52-omp-error@+4 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} // expected-error@+3 {{section length is unspecified and cannot be inferred because subscripted value is not an array}} // ge51-omp-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-omp-error@+1 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} #pragma omp target map(ompx_hold, tofrom: c[:],f) {} - // ge52-error@+4 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} + // ge52-omp-error@+4 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} // expected-error@+3 {{section length is unspecified and cannot be inferred because subscripted value is not an array}} // ge51-omp-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-omp-error@+1 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} @@ -194,19 +193,19 @@ struct SA { {} #pragma omp target map(always, close, always, close, tofrom: a) // expected-error 2 {{same map type modifier has been specified more than once}} {} - // ge60-error@+3 {{same map type modifier has been specified more than once}} // ge51-error@+2 {{same map type modifier has been specified more than once}} // lt51-error@+1 2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} #pragma omp target map(present, present, tofrom: a) {} - // ge52-error@+4 2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} + // ge52-omp-error@+5 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} + // ge52-omp-error@+4 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} // ompx-error@+3 {{same map type modifier has been specified more than once}} // ge51-omp-error@+2 2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-omp-error@+1 2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} #pragma omp target map(ompx_hold, ompx_hold, tofrom: a) {} - // ge60-error@+9 {{same map type modifier has been specified more than once}} - // ge52-error@+8 2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} + // ge52-omp-error@+9 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} + // ge52-omp-error@+8 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} // expected-error@+7 2 {{same map type modifier has been specified more than once}} // ge51-error@+6 {{same map type modifier has been specified more than once}} // lt51-ompx-error@+5 2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'ompx_hold'}} @@ -220,45 +219,34 @@ struct SA { {} #pragma omp target map( , , tofrom: a) // expected-error {{missing map type modifier}} expected-error {{missing map type modifier}} {} - #pragma omp target map( , , : a) // expected-error {{missing map type modifier}} expected-error {{missing map type modifier}} lt60-error {{missing map type}} + #pragma omp target map( , , : a) // expected-error {{missing map type modifier}} expected-error {{missing map type modifier}} expected-error {{missing map type}} {} - // ge60-error@+4 2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator'}} // ge51-error@+3 2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-error@+2 2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} // expected-error@+1 {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}} #pragma omp target map( d, f, bf: a) {} - // ge60-error@+5 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'iterator}} // expected-error@+4 {{missing map type modifier}} // ge51-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} - // lt60-error@+1 {{missing map type}} + // expected-error@+1 {{missing map type}} #pragma omp target map( , f, : a) {} - #pragma omp target map(always close: a) // lt60-error {{missing map type}} ge52-error{{missing ',' after map type modifier}} + #pragma omp target map(always close: a) // expected-error {{missing map type}} omp52-error{{missing ',' after map type modifier}} {} - #pragma omp target map(always close bf: a) // ge52-error 2 {{missing ',' after map type modifier}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}} + #pragma omp target map(always close bf: a) // omp52-error 2 {{missing ',' after map type modifier}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}} {} - // ge52-error@+4 {{missing ',' after map type modifier}} + // omp52-error@+4 {{missing ',' after map type modifier}} // ge51-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} - // lt60-error@+1 {{missing map type}} + // expected-error@+1 {{missing map type}} #pragma omp target map(always tofrom close: a) {} - // ge60-note@+4 {{map type 'tofrom' is previous specified here}} - // ge60-error@+3 {{map type is already specified}} // ge51-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-error@+1 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} #pragma omp target map(tofrom from: a) {} - // ge60-note@+5 {{map type 'to' is previous specified here}} - // ge60-error@+4 {{map type is already specified}} - // ge52-error@+3 {{missing ',' after map type modifier}} - // ge51-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} - // lt51-error@+1 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} - #pragma omp target map(to always from: a) - {} - #pragma omp target map(close bf: a) // ge52-error {{missing ',' after map type modifier}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}} + #pragma omp target map(close bf: a) // omp52-error {{missing ',' after map type modifier}} expected-error {{incorrect map type, expected one of 'to', 'from', 'tofrom', 'alloc', 'release', or 'delete'}} {} #pragma omp target map(([b[I]][bf])f) // lt50-error {{expected ',' or ']' in lambda capture list}} lt50-error {{expected ')'}} lt50-note {{to match this '('}} {} @@ -278,7 +266,6 @@ struct SA { // lt51-omp-error@+1 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} #pragma omp target map(iterator(it=0:10, it=0:20), tofrom:a) {} - // ge60-error@+7 {{expected '(' after 'iterator'}} // ge51-ompx-error@+6 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present', 'ompx_hold'}} // lt51-ompx-error@+5 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'ompx_hold'}} // lt51-error@+4 {{expected '(' after 'iterator'}} @@ -707,20 +694,20 @@ T tmain(T argc) { foo(); #pragma omp target data map(always, tofrom: x) -#pragma omp target data map(always: x) // lt60-error {{missing map type}} +#pragma omp target data map(always: x) // expected-error {{missing map type}} // ge51-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} -// lt60-error@+1 {{missing map type}} +// expected-error@+1 {{missing map type}} #pragma omp target data map(tofrom, always: x) #pragma omp target data map(always, tofrom: always, tofrom, x) #pragma omp target map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}} foo(); #pragma omp target data map(close, tofrom: x) -#pragma omp target data map(close: x) // lt60-error {{missing map type}} +#pragma omp target data map(close: x) // expected-error {{missing map type}} // ge51-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} -// lt60-error@+1 {{missing map type}} +// expected-error@+1 {{missing map type}} #pragma omp target data map(tofrom, close: x) #pragma omp target data map(close, tofrom: close, tofrom, x) foo(); @@ -842,19 +829,19 @@ int main(int argc, char **argv) { foo(); #pragma omp target data map(always, tofrom: x) -#pragma omp target data map(always: x) // lt60-error {{missing map type}} +#pragma omp target data map(always: x) // expected-error {{missing map type}} // ge51-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} -// lt60-error@+1 {{missing map type}} +// expected-error@+1 {{missing map type}} #pragma omp target data map(tofrom, always: x) #pragma omp target data map(always, tofrom: always, tofrom, x) #pragma omp target map(tofrom j) // expected-error {{expected ',' or ')' in 'map' clause}} foo(); #pragma omp target data map(close, tofrom: x) -#pragma omp target data map(close: x) // lt60-error {{missing map type}} +#pragma omp target data map(close: x) // expected-error {{missing map type}} // ge51-error@+3 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper', 'present'}} // lt51-error@+2 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} -// lt60-error@+1 {{missing map type}} +// expected-error@+1 {{missing map type}} #pragma omp target data map(tofrom, close: x) foo(); // lt51-error@+1 {{incorrect map type modifier, expected one of: 'always', 'close', 'mapper'}} -- GitLab From 927913fac74b671b5202eb00a52907d8445c7691 Mon Sep 17 00:00:00 2001 From: Harald van Dijk Date: Wed, 8 May 2024 11:33:47 +0100 Subject: [PATCH 014/328] [RemoveDIs] Fix remapping of DbgLabelRecords. (#91447) We already remapped DILocations for DbgVariableRecords, but DbgLabelRecords have debug locations too that need to be mapped the same way. --- llvm/lib/Transforms/Utils/ValueMapper.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/Utils/ValueMapper.cpp b/llvm/lib/Transforms/Utils/ValueMapper.cpp index 6ebdd85d37b4..1c877ee937fb 100644 --- a/llvm/lib/Transforms/Utils/ValueMapper.cpp +++ b/llvm/lib/Transforms/Utils/ValueMapper.cpp @@ -538,17 +538,20 @@ Value *Mapper::mapValue(const Value *V) { } void Mapper::remapDbgRecord(DbgRecord &DR) { + // Remap DILocations. + auto *MappedDILoc = mapMetadata(DR.getDebugLoc()); + DR.setDebugLoc(DebugLoc(cast(MappedDILoc))); + if (DbgLabelRecord *DLR = dyn_cast(&DR)) { + // Remap labels. DLR->setLabel(cast(mapMetadata(DLR->getLabel()))); return; } DbgVariableRecord &V = cast(DR); - // Remap variables and DILocations. + // Remap variables. auto *MappedVar = mapMetadata(V.getVariable()); - auto *MappedDILoc = mapMetadata(V.getDebugLoc()); V.setVariable(cast(MappedVar)); - V.setDebugLoc(DebugLoc(cast(MappedDILoc))); bool IgnoreMissingLocals = Flags & RF_IgnoreMissingLocals; -- GitLab From 19220110acf5ed5cf8be035b7e4a7aed69f0adb1 Mon Sep 17 00:00:00 2001 From: "Felix (Ting Wang)" Date: Wed, 8 May 2024 18:37:51 +0800 Subject: [PATCH 015/328] [PowerPC][AIX] Refactor existing logic to handle non-zero offsets for aix-small-local-dynamic-tls (#89182) To enable optimized small local-dynamic access sequence for non-zero offsets, this patch refactors existing 2a50921553798d2db52ca6330c89f0f8a5bc2215. --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 45 +++--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 89 ++++++----- ...aix-small-local-dynamic-tls-largeaccess.ll | 148 +++++++----------- .../aix-small-local-dynamic-tls-types.ll | 6 +- 4 files changed, 129 insertions(+), 159 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index 405326f4530a..a63824735490 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -205,8 +205,8 @@ public: void LowerPATCHPOINT(StackMaps &SM, const MachineInstr &MI); void EmitTlsCall(const MachineInstr *MI, MCSymbolRefExpr::VariantKind VK); void EmitAIXTlsCallHelper(const MachineInstr *MI); - const MCExpr *getAdjustedLocalExecExpr(const MachineOperand &MO, - int64_t Offset); + const MCExpr *getAdjustedFasterLocalExpr(const MachineOperand &MO, + int64_t Offset); bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget(); bool Changed = AsmPrinter::runOnMachineFunction(MF); @@ -1598,7 +1598,8 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) { // machine operand (which is a TargetGlobalTLSAddress) is expected to be // the same operand for both loads and stores. for (const MachineOperand &TempMO : MI->operands()) { - if (((TempMO.getTargetFlags() == PPCII::MO_TPREL_FLAG)) && + if (((TempMO.getTargetFlags() == PPCII::MO_TPREL_FLAG || + TempMO.getTargetFlags() == PPCII::MO_TLSLD_FLAG)) && TempMO.getOperandNo() == 1) OpNum = 1; } @@ -1634,8 +1635,8 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) { case PPC::ADDI8: { // A faster non-TOC-based local-[exec|dynamic] sequence is represented by // `addi` or a load/store instruction (that directly loads or stores off of - // the thread pointer) with an immediate operand having the MO_TPREL_FLAG. - // Such instructions do not otherwise arise. + // the thread pointer) with an immediate operand having the + // [MO_TPREL_FLAG|MO_TLSLD_FLAG]. Such instructions do not otherwise arise. if (!HasAIXSmallLocalTLS) break; bool IsMIADDI8 = MI->getOpcode() == PPC::ADDI8; @@ -1647,7 +1648,7 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) { Flag == PPCII::MO_TPREL_PCREL_FLAG || Flag == PPCII::MO_TLSLD_FLAG) { LowerPPCMachineInstrToMCInst(MI, TmpInst, *this); - const MCExpr *Expr = getAdjustedLocalExecExpr(MO, MO.getOffset()); + const MCExpr *Expr = getAdjustedFasterLocalExpr(MO, MO.getOffset()); if (Expr) TmpInst.getOperand(OpNum) = MCOperand::createExpr(Expr); @@ -1677,14 +1678,15 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) { EmitToStreamer(*OutStreamer, TmpInst); } -// For non-TOC-based local-exec variables that have a non-zero offset, +// For non-TOC-based local-[exec|dynamic] variables that have a non-zero offset, // we need to create a new MCExpr that adds the non-zero offset to the address -// of the local-exec variable that will be used in either an addi, load or -// store. However, the final displacement for these instructions must be +// of the local-[exec|dynamic] variable that will be used in either an addi, +// load or store. However, the final displacement for these instructions must be // between [-32768, 32768), so if the TLS address + its non-zero offset is // greater than 32KB, a new MCExpr is produced to accommodate this situation. -const MCExpr *PPCAsmPrinter::getAdjustedLocalExecExpr(const MachineOperand &MO, - int64_t Offset) { +const MCExpr * +PPCAsmPrinter::getAdjustedFasterLocalExpr(const MachineOperand &MO, + int64_t Offset) { // Non-zero offsets (for loads, stores or `addi`) require additional handling. // When the offset is zero, there is no need to create an adjusted MCExpr. if (!Offset) @@ -1692,13 +1694,9 @@ const MCExpr *PPCAsmPrinter::getAdjustedLocalExecExpr(const MachineOperand &MO, assert(MO.isGlobal() && "Only expecting a global MachineOperand here!"); const GlobalValue *GValue = MO.getGlobal(); - // TODO: Handle the aix-small-local-dynamic-tls non-zero offset case. TLSModel::Model Model = TM.getTLSModel(GValue); - if (Model == TLSModel::LocalDynamic) { - return nullptr; - } - assert(Model == TLSModel::LocalExec && - "Only local-exec accesses are handled!"); + assert((Model == TLSModel::LocalExec || Model == TLSModel::LocalDynamic) && + "Only local-[exec|dynamic] accesses are handled!"); bool IsGlobalADeclaration = GValue->isDeclarationForLinker(); // Find the GlobalVariable that corresponds to the particular TLS variable @@ -1719,7 +1717,10 @@ const MCExpr *PPCAsmPrinter::getAdjustedLocalExecExpr(const MachineOperand &MO, // For when TLS variables are extern, this is safe to do because we can // assume that the address of extern TLS variables are zero. const MCExpr *Expr = MCSymbolRefExpr::create( - getSymbol(GValue), MCSymbolRefExpr::VK_PPC_AIX_TLSLE, OutContext); + getSymbol(GValue), + Model == TLSModel::LocalExec ? MCSymbolRefExpr::VK_PPC_AIX_TLSLE + : MCSymbolRefExpr::VK_PPC_AIX_TLSLD, + OutContext); Expr = MCBinaryExpr::createAdd( Expr, MCConstantExpr::create(Offset, OutContext), OutContext); if (FinalAddress >= 32768) { @@ -1732,10 +1733,10 @@ const MCExpr *PPCAsmPrinter::getAdjustedLocalExecExpr(const MachineOperand &MO, ptrdiff_t Delta = ((FinalAddress + 32768) & ~0xFFFF); // Check that the total instruction displacement fits within [-32768,32768). [[maybe_unused]] ptrdiff_t InstDisp = TLSVarAddress + Offset - Delta; - assert(((InstDisp < 32768) && - (InstDisp >= -32768)) && - "Expecting the instruction displacement for local-exec TLS " - "variables to be between [-32768, 32768)!"); + assert( + ((InstDisp < 32768) && (InstDisp >= -32768)) && + "Expecting the instruction displacement for local-[exec|dynamic] TLS " + "variables to be between [-32768, 32768)!"); Expr = MCBinaryExpr::createAdd( Expr, MCConstantExpr::create(-Delta, OutContext), OutContext); } diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 48ee8b5d8d81..68621558e3fa 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -7587,29 +7587,23 @@ static bool hasAIXSmallTLSAttr(SDValue Val) { return false; } -// Is an ADDI eligible for folding for non-TOC-based local-exec accesses? -static bool isEligibleToFoldADDIForLocalExecAccesses(SelectionDAG *DAG, - SDValue ADDIToFold) { +// Is an ADDI eligible for folding for non-TOC-based local-[exec|dynamic] +// accesses? +static bool isEligibleToFoldADDIForFasterLocalAccesses(SelectionDAG *DAG, + SDValue ADDIToFold) { // Check if ADDIToFold (the ADDI that we want to fold into local-exec // accesses), is truly an ADDI. if (!ADDIToFold.isMachineOpcode() || (ADDIToFold.getMachineOpcode() != PPC::ADDI8)) return false; - // Folding is only allowed for the AIX small-local-exec TLS target attribute - // or when the 'aix-small-tls' global variable attribute is present. + // Folding is only allowed for the AIX small-local-[exec|dynamic] TLS target + // attribute or when the 'aix-small-tls' global variable attribute is present. const PPCSubtarget &Subtarget = DAG->getMachineFunction().getSubtarget(); SDValue TLSVarNode = ADDIToFold.getOperand(1); - if (!(Subtarget.hasAIXSmallLocalExecTLS() || hasAIXSmallTLSAttr(TLSVarNode))) - return false; - - // The first operand of the ADDIToFold should be the thread pointer. - // This transformation is only performed if the first operand of the - // addi is the thread pointer. - SDValue TPRegNode = ADDIToFold.getOperand(0); - RegisterSDNode *TPReg = dyn_cast(TPRegNode.getNode()); - if (!TPReg || (TPReg->getReg() != Subtarget.getThreadPointerRegister())) + if (!(Subtarget.hasAIXSmallLocalDynamicTLS() || + Subtarget.hasAIXSmallLocalExecTLS() || hasAIXSmallTLSAttr(TLSVarNode))) return false; // The second operand of the ADDIToFold should be the global TLS address @@ -7619,24 +7613,36 @@ static bool isEligibleToFoldADDIForLocalExecAccesses(SelectionDAG *DAG, if (!GA) return false; - // The local-exec TLS variable should only have the MO_TPREL_FLAG target flag, - // so this optimization is not performed otherwise if the flag is not set. + if (DAG->getTarget().getTLSModel(GA->getGlobal()) == TLSModel::LocalExec) { + // The first operand of the ADDIToFold should be the thread pointer. + // This transformation is only performed if the first operand of the + // addi is the thread pointer. + SDValue TPRegNode = ADDIToFold.getOperand(0); + RegisterSDNode *TPReg = dyn_cast(TPRegNode.getNode()); + if (!TPReg || (TPReg->getReg() != Subtarget.getThreadPointerRegister())) + return false; + } + + // The local-[exec|dynamic] TLS variable should only have the + // [MO_TPREL_FLAG|MO_TLSLD_FLAG] target flags, so this optimization is not + // performed otherwise if the flag is not set. unsigned TargetFlags = GA->getTargetFlags(); - if (TargetFlags != PPCII::MO_TPREL_FLAG) + if (!(TargetFlags == PPCII::MO_TPREL_FLAG || + TargetFlags == PPCII::MO_TLSLD_FLAG)) return false; // If all conditions are satisfied, the ADDI is valid for folding. return true; } -// For non-TOC-based local-exec access where an addi is feeding into another -// addi, fold this sequence into a single addi if possible. -// Before this optimization, the sequence appears as: -// addi rN, r13, sym@le +// For non-TOC-based local-[exec|dynamic] access where an addi is feeding into +// another addi, fold this sequence into a single addi if possible. Before this +// optimization, the sequence appears as: +// addi rN, r13, sym@[le|ld] // addi rM, rN, imm // After this optimization, we can fold the two addi into a single one: -// addi rM, r13, sym@le + imm -static void foldADDIForLocalExecAccesses(SDNode *N, SelectionDAG *DAG) { +// addi rM, r13, sym@[le|ld] + imm +static void foldADDIForFasterLocalAccesses(SDNode *N, SelectionDAG *DAG) { if (N->getMachineOpcode() != PPC::ADDI8) return; @@ -7644,27 +7650,17 @@ static void foldADDIForLocalExecAccesses(SDNode *N, SelectionDAG *DAG) { // we want optimized out. SDValue InitialADDI = N->getOperand(0); - if (!isEligibleToFoldADDIForLocalExecAccesses(DAG, InitialADDI)) + if (!isEligibleToFoldADDIForFasterLocalAccesses(DAG, InitialADDI)) return; - // At this point, InitialADDI can be folded into a non-TOC-based local-exec - // access. The first operand of InitialADDI should be the thread pointer, - // which has been checked in isEligibleToFoldADDIForLocalExecAccesses(). - SDValue TPRegNode = InitialADDI.getOperand(0); - [[maybe_unused]] RegisterSDNode *TPReg = dyn_cast(TPRegNode.getNode()); - [[maybe_unused]] const PPCSubtarget &Subtarget = - DAG->getMachineFunction().getSubtarget(); - assert((TPReg && (TPReg->getReg() == Subtarget.getThreadPointerRegister())) && - "Expecting the first operand to be a thread pointer for folding addi " - "in local-exec accesses!"); - // The second operand of the InitialADDI should be the global TLS address - // (the local-exec TLS variable), with the MO_TPREL_FLAG target flag. - // This has been checked in isEligibleToFoldADDIForLocalExecAccesses(). + // (the local-[exec|dynamic] TLS variable), with the + // [MO_TPREL_FLAG|MO_TLSLD_FLAG] target flag. This has been checked in + // isEligibleToFoldADDIForFasterLocalAccesses(). SDValue TLSVarNode = InitialADDI.getOperand(1); GlobalAddressSDNode *GA = dyn_cast(TLSVarNode); assert(GA && "Expecting a valid GlobalAddressSDNode when folding addi into " - "local-exec accesses!"); + "local-[exec|dynamic] accesses!"); unsigned TargetFlags = GA->getTargetFlags(); // The second operand of the addi that we want to preserve will be an @@ -7676,7 +7672,7 @@ static void foldADDIForLocalExecAccesses(SDNode *N, SelectionDAG *DAG) { TLSVarNode = DAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(GA), MVT::i64, Offset, TargetFlags); - (void)DAG->UpdateNodeOperands(N, TPRegNode, TLSVarNode); + (void)DAG->UpdateNodeOperands(N, InitialADDI.getOperand(0), TLSVarNode); if (InitialADDI.getNode()->use_empty()) DAG->RemoveDeadNode(InitialADDI.getNode()); } @@ -7693,8 +7689,9 @@ void PPCDAGToDAGISel::PeepholePPC64() { if (isVSXSwap(SDValue(N, 0))) reduceVSXSwap(N, CurDAG); - // This optimization is performed for non-TOC-based local-exec accesses. - foldADDIForLocalExecAccesses(N, CurDAG); + // This optimization is performed for non-TOC-based local-[exec|dynamic] + // accesses. + foldADDIForFasterLocalAccesses(N, CurDAG); unsigned FirstOp; unsigned StorageOpcode = N->getMachineOpcode(); @@ -7852,13 +7849,15 @@ void PPCDAGToDAGISel::PeepholePPC64() { ImmOpnd = CurDAG->getTargetConstant(Offset, SDLoc(ImmOpnd), ImmOpnd.getValueType()); } else if (Offset != 0) { - // This optimization is performed for non-TOC-based local-exec accesses. - if (isEligibleToFoldADDIForLocalExecAccesses(CurDAG, Base)) { + // This optimization is performed for non-TOC-based local-[exec|dynamic] + // accesses. + if (isEligibleToFoldADDIForFasterLocalAccesses(CurDAG, Base)) { // Add the non-zero offset information into the load or store - // instruction to be used for non-TOC-based local-exec accesses. + // instruction to be used for non-TOC-based local-[exec|dynamic] + // accesses. GlobalAddressSDNode *GA = dyn_cast(ImmOpnd); assert(GA && "Expecting a valid GlobalAddressSDNode when folding " - "addi into local-exec accesses!"); + "addi into local-[exec|dynamic] accesses!"); ImmOpnd = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(GA), MVT::i64, Offset, GA->getTargetFlags()); diff --git a/llvm/test/CodeGen/PowerPC/aix-small-local-dynamic-tls-largeaccess.ll b/llvm/test/CodeGen/PowerPC/aix-small-local-dynamic-tls-largeaccess.ll index d3fa94779dd7..44d62124ac58 100644 --- a/llvm/test/CodeGen/PowerPC/aix-small-local-dynamic-tls-largeaccess.ll +++ b/llvm/test/CodeGen/PowerPC/aix-small-local-dynamic-tls-largeaccess.ll @@ -39,23 +39,18 @@ define signext i32 @test1() { ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stdu r1, -48(r1) ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r3, L..C0(r2) # target-flags(ppc-tlsldm) @"_$TLSML" ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r0, 64(r1) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r6, 4 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: bla .__tls_get_mod[PR] -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r5, 1 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r4, ElementIntTLSv1[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r5, ElementIntTLSv1[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r5, ElementIntTLS2[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r6, 24(r4) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r4, 1 +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r5, 4 +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r4, ElementIntTLSv1[TL]@ld(r3) ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r4, 2 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r4, 320(r5) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r4, ElementIntTLS3[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r5, 3 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r5, 324(r4) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r4, ElementIntTLS4[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r3, ElementIntTLS5[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r6, 328(r4) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r5, ElementIntTLSv1[TL]@ld+24(r3) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r5, (ElementIntTLS4[TL]@ld+328)-65536(r3) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r4, (ElementIntTLS2[TL]@ld+320)-65536(r3) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r4, 3 +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r4, (ElementIntTLS3[TL]@ld+324)-65536(r3) ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r4, 88 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r4, 332(r3) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r4, (ElementIntTLS5[TL]@ld+332)-65536(r3) ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r3, 102 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: addi r1, r1, 48 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r0, 16(r1) @@ -68,24 +63,19 @@ define signext i32 @test1() { ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stdu r1, -48(r1) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: addis r3, L..C0@u(r2) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r0, 64(r1) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r6, 4 ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r3, L..C0@l(r3) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: bla .__tls_get_mod[PR] -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r5, 1 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r4, ElementIntTLSv1[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r5, ElementIntTLSv1[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r5, ElementIntTLS2[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r6, 24(r4) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r4, 1 +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r5, 4 +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r4, ElementIntTLSv1[TL]@ld(r3) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r4, 2 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r4, 320(r5) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r4, ElementIntTLS3[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r5, 3 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r5, 324(r4) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r4, ElementIntTLS4[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r3, ElementIntTLS5[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r6, 328(r4) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r5, ElementIntTLSv1[TL]@ld+24(r3) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r5, (ElementIntTLS4[TL]@ld+328)-65536(r3) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r4, (ElementIntTLS2[TL]@ld+320)-65536(r3) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r4, 3 +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r4, (ElementIntTLS3[TL]@ld+324)-65536(r3) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r4, 88 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r4, 332(r3) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r4, (ElementIntTLS5[TL]@ld+332)-65536(r3) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r3, 102 ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: addi r1, r1, 48 ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r0, 16(r1) @@ -132,26 +122,21 @@ define i64 @test2() { ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r0, 64(r1) ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: bla .__tls_get_mod[PR] ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: mr r6, r3 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r3, ElementLongTLS6[UL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r4, 212 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r4, 424(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r3, ElementLongTLS2[TL]@ld(r6) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r3, 212 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r4, 203 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r4, 1200(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r3, L..C1(r2) # target-flags(ppc-tlsgdm) @MyTLSGDVar -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r4, L..C2(r2) # target-flags(ppc-tlsgd) @MyTLSGDVar +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r4, (ElementLongTLS2[TL]@ld+1200)-131072(r6) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r4, L..C1(r2) # target-flags(ppc-tlsgd) @MyTLSGDVar +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r3, ElementLongTLS6[UL]@ld+424(r6) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r3, L..C2(r2) # target-flags(ppc-tlsgdm) @MyTLSGDVar ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: bla .__tls_get_addr[PR] ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r4, 44 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r4, 440(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r3, ElementLongTLS3[TL]@ld(r6) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r4, 6 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r4, 2000(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r3, ElementLongTLS4[TL]@ld(r6) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r3, 6 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r4, 100 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r4, 6800(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r3, ElementLongTLS5[TL]@ld(r6) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r4, 882 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r4, 8400(r3) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r3, (ElementLongTLS3[TL]@ld+2000)-196608(r6) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r3, 882 +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r4, (ElementLongTLS4[TL]@ld+6800)-196608(r6) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r3, (ElementLongTLS5[TL]@ld+8400)-196608(r6) ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r3, 1191 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: addi r1, r1, 48 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r0, 16(r1) @@ -166,29 +151,24 @@ define i64 @test2() { ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r0, 64(r1) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r3, L..C0@l(r3) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: bla .__tls_get_mod[PR] -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r4, 212 +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: addis r4, L..C1@u(r2) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: mr r6, r3 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r3, ElementLongTLS6[UL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r4, 424(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r3, ElementLongTLS2[TL]@ld(r6) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r4, 203 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r4, 1200(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: addis r3, L..C1@u(r2) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: addis r4, L..C2@u(r2) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r3, L..C1@l(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r4, L..C2@l(r4) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r3, 212 +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r4, L..C1@l(r4) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r3, ElementLongTLS6[UL]@ld+424(r6) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r3, 203 +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r3, (ElementLongTLS2[TL]@ld+1200)-131072(r6) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: addis r3, L..C2@u(r2) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r3, L..C2@l(r3) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: bla .__tls_get_addr[PR] ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r4, 44 ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r4, 440(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r3, ElementLongTLS3[TL]@ld(r6) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r4, 6 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r4, 2000(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r3, ElementLongTLS4[TL]@ld(r6) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r3, 6 ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r4, 100 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r4, 6800(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r3, ElementLongTLS5[TL]@ld(r6) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r4, 882 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r4, 8400(r3) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r3, (ElementLongTLS3[TL]@ld+2000)-196608(r6) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r3, 882 +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r4, (ElementLongTLS4[TL]@ld+6800)-196608(r6) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r3, (ElementLongTLS5[TL]@ld+8400)-196608(r6) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r3, 1191 ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: addi r1, r1, 48 ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r0, 16(r1) @@ -230,23 +210,19 @@ define signext i32 @test3() { ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stdu r1, -48(r1) ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r3, L..C0(r2) # target-flags(ppc-tlsldm) @"_$TLSML" ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r0, 64(r1) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r6, 2 +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r6, 3 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: bla .__tls_get_mod[PR] +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r5, 2 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r4, 1 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r5, ElementIntTLS2[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r7, ElementIntTLS3[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r6, 320(r5) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r5, 3 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r6, ElementIntTLS4[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r5, 324(r7) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r5, L..C3(r2) # target-flags(ppc-tlsld) @ElementIntTLSv2 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r7, ElementIntTLS5[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stwux r4, r3, r5 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r4, 4 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r4, 24(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r3, 88 -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r4, 328(r6) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r3, 332(r7) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r6, (ElementIntTLS3[TL]@ld+324)-65536(r3) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r6, L..C3(r2) # target-flags(ppc-tlsld) @ElementIntTLSv2 +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r5, (ElementIntTLS2[TL]@ld+320)-65536(r3) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r5, 88 +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r5, (ElementIntTLS5[TL]@ld+332)-65536(r3) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r5, 4 +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r5, (ElementIntTLS4[TL]@ld+328)-65536(r3) +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stwux r4, r3, r6 +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: stw r5, 24(r3) ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: li r3, 102 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: addi r1, r1, 48 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r0, 16(r1) @@ -262,22 +238,18 @@ define signext i32 @test3() { ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: addis r6, L..C3@u(r2) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r3, L..C0@l(r3) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r6, L..C3@l(r6) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r7, 3 ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: bla .__tls_get_mod[PR] ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r5, 2 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r4, ElementIntTLS2[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r5, 320(r4) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r4, 1 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r5, ElementIntTLS3[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r7, 324(r5) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r5, ElementIntTLS4[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r7, ElementIntTLS5[TL]@ld(r3) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r5, (ElementIntTLS2[TL]@ld+320)-65536(r3) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r5, 3 +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r5, (ElementIntTLS3[TL]@ld+324)-65536(r3) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r5, 88 +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r5, (ElementIntTLS5[TL]@ld+332)-65536(r3) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r5, 4 +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r5, (ElementIntTLS4[TL]@ld+328)-65536(r3) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stwux r4, r3, r6 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r4, 4 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r4, 24(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r3, 88 -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r4, 328(r5) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r3, 332(r7) +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: stw r5, 24(r3) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: li r3, 102 ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: addi r1, r1, 48 ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r0, 16(r1) diff --git a/llvm/test/CodeGen/PowerPC/aix-small-local-dynamic-tls-types.ll b/llvm/test/CodeGen/PowerPC/aix-small-local-dynamic-tls-types.ll index 161a58a90296..489260b4e0ae 100644 --- a/llvm/test/CodeGen/PowerPC/aix-small-local-dynamic-tls-types.ll +++ b/llvm/test/CodeGen/PowerPC/aix-small-local-dynamic-tls-types.ll @@ -51,8 +51,7 @@ define nonnull ptr @AddrTest1() local_unnamed_addr { ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r3, L..C0(r2) # target-flags(ppc-tlsldm) @"_$TLSML" ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: std r0, 64(r1) ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: bla .__tls_get_mod[PR] -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r3, a[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: addi r3, r3, 12 +; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: la r3, a[TL]@ld+12(r3) ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: addi r1, r1, 48 ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: ld r0, 16(r1) ; SMALL-LOCAL-DYNAMIC-SMALLCM64-NEXT: mtlr r0 @@ -66,8 +65,7 @@ define nonnull ptr @AddrTest1() local_unnamed_addr { ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: std r0, 64(r1) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r3, L..C0@l(r3) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: bla .__tls_get_mod[PR] -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r3, a[TL]@ld(r3) -; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: addi r3, r3, 12 +; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: la r3, a[TL]@ld+12(r3) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: addi r1, r1, 48 ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: ld r0, 16(r1) ; SMALL-LOCAL-DYNAMIC-LARGECM64-NEXT: mtlr r0 -- GitLab From 6fa09616da7436f85eb7e1e1fd74e1ac078ddb0d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Don=C3=A1t=20Nagy?= Date: Wed, 8 May 2024 12:38:33 +0200 Subject: [PATCH 016/328] [analyzer] Use explicit call description mode in MIGChecker (#91331) This commit explicitly specifies the matching mode (C library function, any non-method function, or C++ method) for the `CallDescription`s constructed in the checker `osx.MIG`. The code was simplified to use a `CallDescriptionMap` instead of a raw vector of pairs. This change won't cause major functional changes, but isn't NFC because it ensures that e.g. call descriptions for a non-method function won't accidentally match a method that has the same name. Separate commits have already performed this change in other checkers: - easy cases: e2f1cbae45f81f3cd9a4d3c2bcf69a094eb060fa, 6d64f8e1feee014e72730a78b62d9d415df112ff - MallocChecker: d6d84b5d1448e4f2e24b467a0abcf42fe9d543e9 - iterator checkers: 06eedffe0d2782922e63cc25cb927f4acdaf7b30 - InvalidPtr checker: 024281d4d26344f9613b9115ea1fcbdbdba23235 - apiModeling.llvm.ReturnValue: 97dd8e3c4f38ef345b01fbbf0a2052c7875ff7e0 ... and follow-up commits will handle the remaining few checkers. My goal is to ensure that the call description mode is always explicitly specified and eliminate (or strongly restrict) the vague "may be either a method or a simple function" mode that's the current default. --- .../StaticAnalyzer/Checkers/MIGChecker.cpp | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/clang/lib/StaticAnalyzer/Checkers/MIGChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/MIGChecker.cpp index 153a0a51e980..9757a00f1fb2 100644 --- a/clang/lib/StaticAnalyzer/Checkers/MIGChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/MIGChecker.cpp @@ -46,13 +46,13 @@ class MIGChecker : public Checker, // additionally an argument of a MIG routine, the checker keeps track of that // information and issues a warning when an error is returned from the // respective routine. - std::vector> Deallocators = { + CallDescriptionMap Deallocators = { #define CALL(required_args, deallocated_arg, ...) \ - {{{__VA_ARGS__}, required_args}, deallocated_arg} - // E.g., if the checker sees a C function 'vm_deallocate' that is - // defined on class 'IOUserClient' that has exactly 3 parameters, it knows - // that argument #1 (starting from 0, i.e. the second argument) is going - // to be consumed in the sense of the MIG consume-on-success convention. + {{CDM::SimpleFunc, {__VA_ARGS__}, required_args}, deallocated_arg} + // E.g., if the checker sees a C function 'vm_deallocate' that has + // exactly 3 parameters, it knows that argument #1 (starting from 0, i.e. + // the second argument) is going to be consumed in the sense of the MIG + // consume-on-success convention. CALL(3, 1, "vm_deallocate"), CALL(3, 1, "mach_vm_deallocate"), CALL(2, 0, "mig_deallocate"), @@ -78,6 +78,9 @@ class MIGChecker : public Checker, CALL(1, 0, "thread_inspect_deallocate"), CALL(1, 0, "upl_deallocate"), CALL(1, 0, "vm_map_deallocate"), +#undef CALL +#define CALL(required_args, deallocated_arg, ...) \ + {{CDM::CXXMethod, {__VA_ARGS__}, required_args}, deallocated_arg} // E.g., if the checker sees a method 'releaseAsyncReference64()' that is // defined on class 'IOUserClient' that takes exactly 1 argument, it knows // that the argument is going to be consumed in the sense of the MIG @@ -87,7 +90,7 @@ class MIGChecker : public Checker, #undef CALL }; - CallDescription OsRefRetain{{"os_ref_retain"}, 1}; + CallDescription OsRefRetain{CDM::SimpleFunc, {"os_ref_retain"}, 1}; void checkReturnAux(const ReturnStmt *RS, CheckerContext &C) const; @@ -198,15 +201,12 @@ void MIGChecker::checkPostCall(const CallEvent &Call, CheckerContext &C) const { if (!isInMIGCall(C)) return; - auto I = llvm::find_if(Deallocators, - [&](const std::pair &Item) { - return Item.first.matches(Call); - }); - if (I == Deallocators.end()) + const unsigned *ArgIdxPtr = Deallocators.lookup(Call); + if (!ArgIdxPtr) return; ProgramStateRef State = C.getState(); - unsigned ArgIdx = I->second; + unsigned ArgIdx = *ArgIdxPtr; SVal Arg = Call.getArgSVal(ArgIdx); const ParmVarDecl *PVD = getOriginParam(Arg, C); if (!PVD || State->contains(PVD)) -- GitLab From 943617d12ccbd3cf317f0bbec03d9efc700f3953 Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Wed, 8 May 2024 08:03:22 -0400 Subject: [PATCH 017/328] Typo fix; NFC --- clang/lib/CodeGen/CGExprAgg.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/CodeGen/CGExprAgg.cpp b/clang/lib/CodeGen/CGExprAgg.cpp index cd9936a6dc0b..6172eb9cdc1b 100644 --- a/clang/lib/CodeGen/CGExprAgg.cpp +++ b/clang/lib/CodeGen/CGExprAgg.cpp @@ -1736,7 +1736,7 @@ void AggExprEmitter::VisitCXXParenListOrInitListExpr( for (const auto *Field : record->fields()) assert( (Field->isUnnamedBitField() || Field->isAnonymousStructOrUnion()) && - "Only unnamed bitfields or ananymous class allowed"); + "Only unnamed bitfields or anonymous class allowed"); #endif return; } -- GitLab From c5509fedc5757fffece385d9d068e36b26793ade Mon Sep 17 00:00:00 2001 From: Xiang Li Date: Wed, 8 May 2024 05:26:34 -0700 Subject: [PATCH 018/328] [HLSL] Support packoffset attribute in AST (#89836) Add HLSLPackOffsetAttr to save packoffset in AST. Since we have to parse the attribute manually in ParseHLSLAnnotations, we could create the ParsedAttribute with a integer offset parameter instead of string. This approach avoids parsing the string if the offset is saved as a string in HLSLPackOffsetAttr. For #57914. --- clang/include/clang/Basic/Attr.td | 12 ++ clang/include/clang/Basic/AttrDocs.td | 20 +++ clang/include/clang/Basic/DiagnosticGroups.td | 3 + .../clang/Basic/DiagnosticParseKinds.td | 2 + .../clang/Basic/DiagnosticSemaKinds.td | 5 + clang/lib/Parse/ParseHLSL.cpp | 88 +++++++++++++ clang/lib/Sema/SemaDeclAttr.cpp | 52 ++++++++ clang/lib/Sema/SemaHLSL.cpp | 80 ++++++++++++ clang/test/AST/HLSL/packoffset.hlsl | 100 ++++++++++++++ clang/test/SemaHLSL/packoffset-invalid.hlsl | 122 ++++++++++++++++++ 10 files changed, 484 insertions(+) create mode 100644 clang/test/AST/HLSL/packoffset.hlsl create mode 100644 clang/test/SemaHLSL/packoffset-invalid.hlsl diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 0225598cbbe8..52552ba48856 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -4415,6 +4415,18 @@ def HLSLResourceBinding: InheritableAttr { let Documentation = [HLSLResourceBindingDocs]; } +def HLSLPackOffset: HLSLAnnotationAttr { + let Spellings = [HLSLAnnotation<"packoffset">]; + let LangOpts = [HLSL]; + let Args = [IntArgument<"Subcomponent">, IntArgument<"Component">]; + let Documentation = [HLSLPackOffsetDocs]; + let AdditionalMembers = [{ + unsigned getOffset() { + return subcomponent * 4 + component; + } + }]; +} + def HLSLSV_DispatchThreadID: HLSLAnnotationAttr { let Spellings = [HLSLAnnotation<"SV_DispatchThreadID">]; let Subjects = SubjectList<[ParmVar, Field]>; diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index 8e6faabfae64..f351822ac74b 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -7408,6 +7408,26 @@ The full documentation is available here: https://docs.microsoft.com/en-us/windo }]; } +def HLSLPackOffsetDocs : Documentation { + let Category = DocCatFunction; + let Content = [{ +The packoffset attribute is used to change the layout of a cbuffer. +Attribute spelling in HLSL is: ``packoffset( c[Subcomponent][.component] )``. +A subcomponent is a register number, which is an integer. A component is in the form of [.xyzw]. + +Examples: + +.. code-block:: c++ + + cbuffer A { + float3 a : packoffset(c0.y); + float4 b : packoffset(c4); + } + +The full documentation is available here: https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-variable-packoffset + }]; +} + def HLSLSV_DispatchThreadIDDocs : Documentation { let Category = DocCatFunction; let Content = [{ diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td index 60f87da2a738..2beb1d45124b 100644 --- a/clang/include/clang/Basic/DiagnosticGroups.td +++ b/clang/include/clang/Basic/DiagnosticGroups.td @@ -1507,6 +1507,9 @@ def BranchProtection : DiagGroup<"branch-protection">; // Warnings for HLSL Clang extensions def HLSLExtension : DiagGroup<"hlsl-extensions">; +// Warning for mix packoffset and non-packoffset. +def HLSLMixPackOffset : DiagGroup<"mix-packoffset">; + // Warnings for DXIL validation def DXILValidation : DiagGroup<"dxil-validation">; diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td index fdffb35ea0d9..bc9d7cacc50b 100644 --- a/clang/include/clang/Basic/DiagnosticParseKinds.td +++ b/clang/include/clang/Basic/DiagnosticParseKinds.td @@ -1754,5 +1754,7 @@ def err_hlsl_separate_attr_arg_and_number : Error<"wrong argument format for hls def ext_hlsl_access_specifiers : ExtWarn< "access specifiers are a clang HLSL extension">, InGroup; +def err_hlsl_unsupported_component : Error<"invalid component '%0' used; expected 'x', 'y', 'z', or 'w'">; +def err_hlsl_packoffset_invalid_reg : Error<"invalid resource class specifier '%0' for packoffset, expected 'c'">; } // end of Parser diagnostics diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 9317ae675c72..d6863f90edb6 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -12184,6 +12184,11 @@ def err_hlsl_init_priority_unsupported : Error< def err_hlsl_unsupported_register_type : Error<"invalid resource class specifier '%0' used; expected 'b', 's', 't', or 'u'">; def err_hlsl_unsupported_register_number : Error<"register number should be an integer">; def err_hlsl_expected_space : Error<"invalid space specifier '%0' used; expected 'space' followed by an integer, like space1">; +def warn_hlsl_packoffset_mix : Warning<"cannot mix packoffset elements with nonpackoffset elements in a cbuffer">, + InGroup; +def err_hlsl_packoffset_overlap : Error<"packoffset overlap between %0, %1">; +def err_hlsl_packoffset_cross_reg_boundary : Error<"packoffset cannot cross register boundary">; +def err_hlsl_packoffset_alignment_mismatch : Error<"packoffset at 'y' not match alignment %0 required by %1">; def err_hlsl_pointers_unsupported : Error< "%select{pointers|references}0 are unsupported in HLSL">; diff --git a/clang/lib/Parse/ParseHLSL.cpp b/clang/lib/Parse/ParseHLSL.cpp index f4cbece31f18..e9c8d6dca7bf 100644 --- a/clang/lib/Parse/ParseHLSL.cpp +++ b/clang/lib/Parse/ParseHLSL.cpp @@ -183,6 +183,94 @@ void Parser::ParseHLSLAnnotations(ParsedAttributes &Attrs, return; } } break; + case ParsedAttr::AT_HLSLPackOffset: { + // Parse 'packoffset( c[Subcomponent][.component] )'. + // Check '('. + if (ExpectAndConsume(tok::l_paren, diag::err_expected_lparen_after)) { + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + // Check c[Subcomponent] as an identifier. + if (!Tok.is(tok::identifier)) { + Diag(Tok.getLocation(), diag::err_expected) << tok::identifier; + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + StringRef OffsetStr = Tok.getIdentifierInfo()->getName(); + SourceLocation SubComponentLoc = Tok.getLocation(); + if (OffsetStr[0] != 'c') { + Diag(Tok.getLocation(), diag::err_hlsl_packoffset_invalid_reg) + << OffsetStr; + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + OffsetStr = OffsetStr.substr(1); + unsigned SubComponent = 0; + if (!OffsetStr.empty()) { + // Make sure SubComponent is a number. + if (OffsetStr.getAsInteger(10, SubComponent)) { + Diag(SubComponentLoc.getLocWithOffset(1), + diag::err_hlsl_unsupported_register_number); + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + } + unsigned Component = 0; + ConsumeToken(); // consume identifier. + SourceLocation ComponentLoc; + if (Tok.is(tok::period)) { + ConsumeToken(); // consume period. + if (!Tok.is(tok::identifier)) { + Diag(Tok.getLocation(), diag::err_expected) << tok::identifier; + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + StringRef ComponentStr = Tok.getIdentifierInfo()->getName(); + ComponentLoc = Tok.getLocation(); + ConsumeToken(); // consume identifier. + // Make sure Component is a single character. + if (ComponentStr.size() != 1) { + Diag(ComponentLoc, diag::err_hlsl_unsupported_component) + << ComponentStr; + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + switch (ComponentStr[0]) { + case 'x': + case 'r': + Component = 0; + break; + case 'y': + case 'g': + Component = 1; + break; + case 'z': + case 'b': + Component = 2; + break; + case 'w': + case 'a': + Component = 3; + break; + default: + Diag(ComponentLoc, diag::err_hlsl_unsupported_component) + << ComponentStr; + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + } + ASTContext &Ctx = Actions.getASTContext(); + QualType SizeTy = Ctx.getSizeType(); + uint64_t SizeTySize = Ctx.getTypeSize(SizeTy); + ArgExprs.push_back(IntegerLiteral::Create( + Ctx, llvm::APInt(SizeTySize, SubComponent), SizeTy, SubComponentLoc)); + ArgExprs.push_back(IntegerLiteral::Create( + Ctx, llvm::APInt(SizeTySize, Component), SizeTy, ComponentLoc)); + if (ExpectAndConsume(tok::r_paren, diag::err_expected)) { + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + } break; case ParsedAttr::UnknownAttribute: Diag(Loc, diag::err_unknown_hlsl_semantic) << II; return; diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 6ca42856459f..6d957ac09e1c 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -7309,6 +7309,55 @@ static void handleHLSLSV_DispatchThreadIDAttr(Sema &S, Decl *D, D->addAttr(::new (S.Context) HLSLSV_DispatchThreadIDAttr(S.Context, AL)); } +static void handleHLSLPackOffsetAttr(Sema &S, Decl *D, const ParsedAttr &AL) { + if (!isa(D) || !isa(D->getDeclContext())) { + S.Diag(AL.getLoc(), diag::err_hlsl_attr_invalid_ast_node) + << AL << "shader constant in a constant buffer"; + return; + } + + uint32_t SubComponent; + if (!checkUInt32Argument(S, AL, AL.getArgAsExpr(0), SubComponent)) + return; + uint32_t Component; + if (!checkUInt32Argument(S, AL, AL.getArgAsExpr(1), Component)) + return; + + QualType T = cast(D)->getType().getCanonicalType(); + // Check if T is an array or struct type. + // TODO: mark matrix type as aggregate type. + bool IsAggregateTy = (T->isArrayType() || T->isStructureType()); + + // Check Component is valid for T. + if (Component) { + unsigned Size = S.getASTContext().getTypeSize(T); + if (IsAggregateTy || Size > 128) { + S.Diag(AL.getLoc(), diag::err_hlsl_packoffset_cross_reg_boundary); + return; + } else { + // Make sure Component + sizeof(T) <= 4. + if ((Component * 32 + Size) > 128) { + S.Diag(AL.getLoc(), diag::err_hlsl_packoffset_cross_reg_boundary); + return; + } + QualType EltTy = T; + if (const auto *VT = T->getAs()) + EltTy = VT->getElementType(); + unsigned Align = S.getASTContext().getTypeAlign(EltTy); + if (Align > 32 && Component == 1) { + // NOTE: Component 3 will hit err_hlsl_packoffset_cross_reg_boundary. + // So we only need to check Component 1 here. + S.Diag(AL.getLoc(), diag::err_hlsl_packoffset_alignment_mismatch) + << Align << EltTy; + return; + } + } + } + + D->addAttr(::new (S.Context) + HLSLPackOffsetAttr(S.Context, AL, SubComponent, Component)); +} + static void handleHLSLShaderAttr(Sema &S, Decl *D, const ParsedAttr &AL) { StringRef Str; SourceLocation ArgLoc; @@ -9730,6 +9779,9 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, case ParsedAttr::AT_HLSLSV_DispatchThreadID: handleHLSLSV_DispatchThreadIDAttr(S, D, AL); break; + case ParsedAttr::AT_HLSLPackOffset: + handleHLSLPackOffsetAttr(S, D, AL); + break; case ParsedAttr::AT_HLSLShader: handleHLSLShaderAttr(S, D, AL); break; diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp index bb9e37f18d37..6a12c417e2f3 100644 --- a/clang/lib/Sema/SemaHLSL.cpp +++ b/clang/lib/Sema/SemaHLSL.cpp @@ -39,9 +39,89 @@ Decl *SemaHLSL::ActOnStartBuffer(Scope *BufferScope, bool CBuffer, return Result; } +// Calculate the size of a legacy cbuffer type based on +// https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-packing-rules +static unsigned calculateLegacyCbufferSize(const ASTContext &Context, + QualType T) { + unsigned Size = 0; + constexpr unsigned CBufferAlign = 128; + if (const RecordType *RT = T->getAs()) { + const RecordDecl *RD = RT->getDecl(); + for (const FieldDecl *Field : RD->fields()) { + QualType Ty = Field->getType(); + unsigned FieldSize = calculateLegacyCbufferSize(Context, Ty); + unsigned FieldAlign = 32; + if (Ty->isAggregateType()) + FieldAlign = CBufferAlign; + Size = llvm::alignTo(Size, FieldAlign); + Size += FieldSize; + } + } else if (const ConstantArrayType *AT = Context.getAsConstantArrayType(T)) { + if (unsigned ElementCount = AT->getSize().getZExtValue()) { + unsigned ElementSize = + calculateLegacyCbufferSize(Context, AT->getElementType()); + unsigned AlignedElementSize = llvm::alignTo(ElementSize, CBufferAlign); + Size = AlignedElementSize * (ElementCount - 1) + ElementSize; + } + } else if (const VectorType *VT = T->getAs()) { + unsigned ElementCount = VT->getNumElements(); + unsigned ElementSize = + calculateLegacyCbufferSize(Context, VT->getElementType()); + Size = ElementSize * ElementCount; + } else { + Size = Context.getTypeSize(T); + } + return Size; +} + void SemaHLSL::ActOnFinishBuffer(Decl *Dcl, SourceLocation RBrace) { auto *BufDecl = cast(Dcl); BufDecl->setRBraceLoc(RBrace); + + // Validate packoffset. + llvm::SmallVector> PackOffsetVec; + bool HasPackOffset = false; + bool HasNonPackOffset = false; + for (auto *Field : BufDecl->decls()) { + VarDecl *Var = dyn_cast(Field); + if (!Var) + continue; + if (Field->hasAttr()) { + PackOffsetVec.emplace_back(Var, Field->getAttr()); + HasPackOffset = true; + } else { + HasNonPackOffset = true; + } + } + + if (HasPackOffset && HasNonPackOffset) + Diag(BufDecl->getLocation(), diag::warn_hlsl_packoffset_mix); + + if (HasPackOffset) { + ASTContext &Context = getASTContext(); + // Make sure no overlap in packoffset. + // Sort PackOffsetVec by offset. + std::sort(PackOffsetVec.begin(), PackOffsetVec.end(), + [](const std::pair &LHS, + const std::pair &RHS) { + return LHS.second->getOffset() < RHS.second->getOffset(); + }); + + for (unsigned i = 0; i < PackOffsetVec.size() - 1; i++) { + VarDecl *Var = PackOffsetVec[i].first; + HLSLPackOffsetAttr *Attr = PackOffsetVec[i].second; + unsigned Size = calculateLegacyCbufferSize(Context, Var->getType()); + unsigned Begin = Attr->getOffset() * 32; + unsigned End = Begin + Size; + unsigned NextBegin = PackOffsetVec[i + 1].second->getOffset() * 32; + if (End > NextBegin) { + VarDecl *NextVar = PackOffsetVec[i + 1].first; + Diag(NextVar->getLocation(), diag::err_hlsl_packoffset_overlap) + << NextVar << Var; + } + } + } + SemaRef.PopDeclContext(); } diff --git a/clang/test/AST/HLSL/packoffset.hlsl b/clang/test/AST/HLSL/packoffset.hlsl new file mode 100644 index 000000000000..9cfd88eeec33 --- /dev/null +++ b/clang/test/AST/HLSL/packoffset.hlsl @@ -0,0 +1,100 @@ +// RUN: %clang_cc1 -triple dxil-unknown-shadermodel6.3-library -S -finclude-default-header -ast-dump -x hlsl %s | FileCheck %s + + +// CHECK: HLSLBufferDecl {{.*}} cbuffer A +cbuffer A +{ + // CHECK-NEXT: VarDecl {{.*}} A1 'float4' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 0 + float4 A1 : packoffset(c); + // CHECK-NEXT: VarDecl {{.*}} col:11 A2 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 1 0 + float A2 : packoffset(c1); + // CHECK-NEXT: VarDecl {{.*}} col:11 A3 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 1 1 + float A3 : packoffset(c1.y); +} + +// CHECK: HLSLBufferDecl {{.*}} cbuffer B +cbuffer B +{ + // CHECK: VarDecl {{.*}} B0 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 1 + float B0 : packoffset(c0.g); + // CHECK-NEXT: VarDecl {{.*}} B1 'double' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 2 + double B1 : packoffset(c0.b); + // CHECK-NEXT: VarDecl {{.*}} B2 'half' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 0 + half B2 : packoffset(c0.r); +} + +// CHECK: HLSLBufferDecl {{.*}} cbuffer C +cbuffer C +{ + // CHECK: VarDecl {{.*}} C0 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 1 + float C0 : packoffset(c0.y); + // CHECK-NEXT: VarDecl {{.*}} C1 'float2' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 2 + float2 C1 : packoffset(c0.z); + // CHECK-NEXT: VarDecl {{.*}} C2 'half' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 + half C2 : packoffset(c0.x); +} + + +// CHECK: HLSLBufferDecl {{.*}} cbuffer D +cbuffer D +{ + // CHECK: VarDecl {{.*}} D0 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 1 + float D0 : packoffset(c0.y); + // CHECK-NEXT: VarDecl {{.*}} D1 'float[2]' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 1 0 + float D1[2] : packoffset(c1.x); + // CHECK-NEXT: VarDecl {{.*}} D2 'half3' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 2 1 + half3 D2 : packoffset(c2.y); + // CHECK-NEXT: VarDecl {{.*}} D3 'double' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 2 + double D3 : packoffset(c0.z); +} + +struct ST { + float a; + float2 b; + half c; +}; + +// CHECK: HLSLBufferDecl {{.*}} cbuffer S +cbuffer S { + // CHECK: VarDecl {{.*}} S0 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 1 + float S0 : packoffset(c0.y); + // CHECK: VarDecl {{.*}} S1 'ST' + // CHECK: HLSLPackOffsetAttr {{.*}} 1 0 + ST S1 : packoffset(c1); + // CHECK: VarDecl {{.*}} S2 'double2' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 2 0 + double2 S2 : packoffset(c2); +} + +struct ST2 { + float s0; + ST s1; + half s2; +}; + +// CHECK: HLSLBufferDecl {{.*}} cbuffer S2 +cbuffer S2 { + // CHECK: VarDecl {{.*}} S20 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 3 + float S20 : packoffset(c0.a); + // CHECK: VarDecl {{.*}} S21 'ST2' + // CHECK: HLSLPackOffsetAttr {{.*}} 1 0 + ST2 S21 : packoffset(c1); + // CHECK: VarDecl {{.*}} S22 'half' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 3 1 + half S22 : packoffset(c3.y); +} diff --git a/clang/test/SemaHLSL/packoffset-invalid.hlsl b/clang/test/SemaHLSL/packoffset-invalid.hlsl new file mode 100644 index 000000000000..c5983f6fd7e0 --- /dev/null +++ b/clang/test/SemaHLSL/packoffset-invalid.hlsl @@ -0,0 +1,122 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.3-library -verify %s + +// expected-warning@+1{{cannot mix packoffset elements with nonpackoffset elements in a cbuffer}} +cbuffer Mix +{ + float4 M1 : packoffset(c0); + float M2; + float M3 : packoffset(c1.y); +} + +// expected-warning@+1{{cannot mix packoffset elements with nonpackoffset elements in a cbuffer}} +cbuffer Mix2 +{ + float4 M4; + float M5 : packoffset(c1.y); + float M6 ; +} + +// expected-error@+1{{attribute 'packoffset' only applies to shader constant in a constant buffer}} +float4 g : packoffset(c0); + +cbuffer IllegalOffset +{ + // expected-error@+1{{invalid resource class specifier 't2' for packoffset, expected 'c'}} + float4 i1 : packoffset(t2); + // expected-error@+1{{invalid component 'm' used; expected 'x', 'y', 'z', or 'w'}} + float i2 : packoffset(c1.m); +} + +cbuffer Overlap +{ + float4 o1 : packoffset(c0); + // expected-error@+1{{packoffset overlap between 'o2', 'o1'}} + float2 o2 : packoffset(c0.z); +} + +cbuffer CrossReg +{ + // expected-error@+1{{packoffset cannot cross register boundary}} + float4 c1 : packoffset(c0.y); + // expected-error@+1{{packoffset cannot cross register boundary}} + float2 c2 : packoffset(c1.w); +} + +struct ST { + float s; +}; + +cbuffer Aggregate +{ + // expected-error@+1{{packoffset cannot cross register boundary}} + ST A1 : packoffset(c0.y); + // expected-error@+1{{packoffset cannot cross register boundary}} + float A2[2] : packoffset(c1.w); +} + +cbuffer Double { + // expected-error@+1{{packoffset at 'y' not match alignment 64 required by 'double'}} + double d : packoffset(c.y); + // expected-error@+1{{packoffset cannot cross register boundary}} + double2 d2 : packoffset(c.z); + // expected-error@+1{{packoffset cannot cross register boundary}} + double3 d3 : packoffset(c.z); +} + +cbuffer ParsingFail { +// expected-error@+1{{expected identifier}} +float pf0 : packoffset(); +// expected-error@+1{{expected identifier}} +float pf1 : packoffset((c0)); +// expected-error@+1{{expected ')'}} +float pf2 : packoffset(c0, x); +// expected-error@+1{{invalid component 'X' used}} +float pf3 : packoffset(c.X); +// expected-error@+1{{expected '(' after ''}} +float pf4 : packoffset; +// expected-error@+1{{expected identifier}} +float pf5 : packoffset(; +// expected-error@+1{{expected '(' after '}} +float pf6 : packoffset); +// expected-error@+1{{expected '(' after '}} +float pf7 : packoffset c0.x; + +// expected-error@+1{{invalid component 'xy' used}} +float pf8 : packoffset(c0.xy); +// expected-error@+1{{invalid component 'rg' used}} +float pf9 : packoffset(c0.rg); +// expected-error@+1{{invalid component 'yes' used}} +float pf10 : packoffset(c0.yes); +// expected-error@+1{{invalid component 'woo'}} +float pf11 : packoffset(c0.woo); +// expected-error@+1{{invalid component 'xr' used}} +float pf12 : packoffset(c0.xr); +} + +struct ST2 { + float a; + float2 b; +}; + +cbuffer S { + float S0 : packoffset(c0.y); + ST2 S1[2] : packoffset(c1); + // expected-error@+1{{packoffset overlap between 'S2', 'S1'}} + half2 S2 : packoffset(c1.w); + half2 S3 : packoffset(c2.w); +} + +struct ST23 { + float s0; + ST2 s1; +}; + +cbuffer S2 { + float S20 : packoffset(c0.y); + ST2 S21 : packoffset(c1); + half2 S22 : packoffset(c2.w); + double S23[2] : packoffset(c3); + // expected-error@+1{{packoffset overlap between 'S24', 'S23'}} + float S24 : packoffset(c3.z); + float S25 : packoffset(c4.z); +} -- GitLab From 737e0bcfe344bd9a8c4e4c3c2e80fdbe93bfaafb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= Date: Wed, 8 May 2024 14:27:02 +0200 Subject: [PATCH 019/328] [GlobalIsel] combine ext of trunc with flags (#87115) https://github.com/llvm/llvm-project/pull/85592 https://discourse.llvm.org/t/rfc-add-nowrap-flags-to-trunc/77453 https://github.com/llvm/llvm-project/pull/88609 --- .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 13 +- .../CodeGen/GlobalISel/GenericMachineInstrs.h | 53 +++ .../CodeGen/GlobalISel/MachineIRBuilder.h | 6 +- .../include/llvm/Target/GlobalISel/Combine.td | 18 +- .../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 83 +++- .../lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 5 +- .../CodeGen/GlobalISel/MachineIRBuilder.cpp | 12 +- .../AArch64/GlobalISel/combine-with-flags.mir | 353 ++++++++++++++++++ 8 files changed, 522 insertions(+), 21 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/combine-with-flags.mir diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h index 4f1c9642e117..ecaece8b6834 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h @@ -599,10 +599,6 @@ public: /// This variant does not erase \p MI after calling the build function. void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo); - /// Use a function which takes in a MachineIRBuilder to perform a combine. - /// By default, it erases the instruction \p MI from the function. - void applyBuildFnMO(const MachineOperand &MO, BuildFnTy &MatchInfo); - bool matchOrShiftToFunnelShift(MachineInstr &MI, BuildFnTy &MatchInfo); bool matchFunnelShiftToRotate(MachineInstr &MI); void applyFunnelShiftToRotate(MachineInstr &MI); @@ -814,6 +810,12 @@ public: /// Match constant LHS ops that should be commuted. bool matchCommuteConstantToRHS(MachineInstr &MI); + /// Combine sext of trunc. + bool matchSextOfTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo); + + /// Combine zext of trunc. + bool matchZextOfTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo); + /// Match constant LHS FP ops that should be commuted. bool matchCommuteFPConstantToRHS(MachineInstr &MI); @@ -857,6 +859,9 @@ public: /// register and different indices. bool matchExtractVectorElementWithDifferentIndices(const MachineOperand &MO, BuildFnTy &MatchInfo); + /// Use a function which takes in a MachineIRBuilder to perform a combine. + /// By default, it erases the instruction def'd on \p MO from the function. + void applyBuildFnMO(const MachineOperand &MO, BuildFnTy &MatchInfo); /// Combine insert vector element OOB. bool matchInsertVectorElementOOB(MachineInstr &MI, BuildFnTy &MatchInfo); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h index 705ef0fa7f2b..2a3145b635e6 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h @@ -792,6 +792,59 @@ public: } }; +/// Represents a cast operation. +/// It models the llvm::CastInst concept. +/// The exception is bitcast. +class GCastOp : public GenericMachineInstr { +public: + Register getSrcReg() const { return getOperand(1).getReg(); } + + static bool classof(const MachineInstr *MI) { + switch (MI->getOpcode()) { + case TargetOpcode::G_ADDRSPACE_CAST: + case TargetOpcode::G_FPEXT: + case TargetOpcode::G_FPTOSI: + case TargetOpcode::G_FPTOUI: + case TargetOpcode::G_FPTRUNC: + case TargetOpcode::G_INTTOPTR: + case TargetOpcode::G_PTRTOINT: + case TargetOpcode::G_SEXT: + case TargetOpcode::G_SITOFP: + case TargetOpcode::G_TRUNC: + case TargetOpcode::G_UITOFP: + case TargetOpcode::G_ZEXT: + case TargetOpcode::G_ANYEXT: + return true; + default: + return false; + } + }; +}; + +/// Represents a sext. +class GSext : public GCastOp { +public: + static bool classof(const MachineInstr *MI) { + return MI->getOpcode() == TargetOpcode::G_SEXT; + }; +}; + +/// Represents a zext. +class GZext : public GCastOp { +public: + static bool classof(const MachineInstr *MI) { + return MI->getOpcode() == TargetOpcode::G_ZEXT; + }; +}; + +/// Represents a trunc. +class GTrunc : public GCastOp { +public: + static bool classof(const MachineInstr *MI) { + return MI->getOpcode() == TargetOpcode::G_TRUNC; + }; +}; + } // namespace llvm #endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index e15f7a7172e1..92e05ee858a7 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -746,7 +746,8 @@ public: /// \pre \p Op must be smaller than \p Res /// /// \return The newly created instruction. - MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op); + MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op, + std::optional Flags = std::nullopt); /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. @@ -1231,7 +1232,8 @@ public: /// \pre \p Res must be smaller than \p Op /// /// \return The newly created instruction. - MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op); + MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op, + std::optional Flags = std::nullopt); /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1 /// diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td index 72c5de03f4e7..d0e125390347 100644 --- a/llvm/include/llvm/Target/GlobalISel/Combine.td +++ b/llvm/include/llvm/Target/GlobalISel/Combine.td @@ -180,6 +180,8 @@ def FmContract : MIFlagEnum<"FmContract">; def FmAfn : MIFlagEnum<"FmAfn">; def FmReassoc : MIFlagEnum<"FmReassoc">; def IsExact : MIFlagEnum<"IsExact">; +def NoSWrap : MIFlagEnum<"NoSWrap">; +def NoUWrap : MIFlagEnum<"NoUWrap">; def MIFlags; // def not; -> Already defined as a SDNode @@ -1501,6 +1503,20 @@ def extract_vector_element_freeze : GICombineRule< [{ return Helper.matchExtractVectorElementWithFreeze(${root}, ${matchinfo}); }]), (apply [{ Helper.applyBuildFnMO(${root}, ${matchinfo}); }])>; +def sext_trunc : GICombineRule< + (defs root:$root, build_fn_matchinfo:$matchinfo), + (match (G_TRUNC $src, $x, (MIFlags NoSWrap)), + (G_SEXT $root, $src), + [{ return Helper.matchSextOfTrunc(${root}, ${matchinfo}); }]), + (apply [{ Helper.applyBuildFnMO(${root}, ${matchinfo}); }])>; + +def zext_trunc : GICombineRule< + (defs root:$root, build_fn_matchinfo:$matchinfo), + (match (G_TRUNC $src, $x, (MIFlags NoUWrap)), + (G_ZEXT $root, $src), + [{ return Helper.matchZextOfTrunc(${root}, ${matchinfo}); }]), + (apply [{ Helper.applyBuildFnMO(${root}, ${matchinfo}); }])>; + def extract_vector_element_shuffle_vector : GICombineRule< (defs root:$root, build_fn_matchinfo:$matchinfo), (match (G_SHUFFLE_VECTOR $src, $src1, $src2, $mask), @@ -1666,7 +1682,7 @@ def all_combines : GICombineGroup<[trivial_combines, vector_ops_combines, sub_add_reg, select_to_minmax, redundant_binop_in_equality, fsub_to_fneg, commute_constant_to_rhs, match_ands, match_ors, combine_concat_vector, double_icmp_zero_and_or_combine, match_addos, - combine_shuffle_concat]>; + sext_trunc, zext_trunc, combine_shuffle_concat]>; // A combine group used to for prelegalizer combiners at -O0. The combines in // this group have been selected based on experiments to balance code size and diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index 653e7689b577..9999776b9826 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -4137,14 +4137,6 @@ void CombinerHelper::applyBuildFn( MI.eraseFromParent(); } -void CombinerHelper::applyBuildFnMO(const MachineOperand &MO, - BuildFnTy &MatchInfo) { - MachineInstr *Root = getDefIgnoringCopies(MO.getReg(), MRI); - Builder.setInstrAndDebugLoc(*Root); - MatchInfo(Builder); - Root->eraseFromParent(); -} - void CombinerHelper::applyBuildFnNoErase( MachineInstr &MI, std::function &MatchInfo) { MatchInfo(Builder); @@ -7252,3 +7244,78 @@ bool CombinerHelper::matchAddOverflow(MachineInstr &MI, BuildFnTy &MatchInfo) { return false; } + +void CombinerHelper::applyBuildFnMO(const MachineOperand &MO, + BuildFnTy &MatchInfo) { + MachineInstr *Root = getDefIgnoringCopies(MO.getReg(), MRI); + MatchInfo(Builder); + Root->eraseFromParent(); +} + +bool CombinerHelper::matchSextOfTrunc(const MachineOperand &MO, + BuildFnTy &MatchInfo) { + GSext *Sext = cast(getDefIgnoringCopies(MO.getReg(), MRI)); + GTrunc *Trunc = cast(getDefIgnoringCopies(Sext->getSrcReg(), MRI)); + + Register Dst = Sext->getReg(0); + Register Src = Trunc->getSrcReg(); + + LLT DstTy = MRI.getType(Dst); + LLT SrcTy = MRI.getType(Src); + + if (DstTy == SrcTy) { + MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); }; + return true; + } + + if (DstTy.getScalarSizeInBits() < SrcTy.getScalarSizeInBits() && + isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}})) { + MatchInfo = [=](MachineIRBuilder &B) { + B.buildTrunc(Dst, Src, MachineInstr::MIFlag::NoSWrap); + }; + return true; + } + + if (DstTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits() && + isLegalOrBeforeLegalizer({TargetOpcode::G_SEXT, {DstTy, SrcTy}})) { + MatchInfo = [=](MachineIRBuilder &B) { B.buildSExt(Dst, Src); }; + return true; + } + + return false; +} + +bool CombinerHelper::matchZextOfTrunc(const MachineOperand &MO, + BuildFnTy &MatchInfo) { + GZext *Zext = cast(getDefIgnoringCopies(MO.getReg(), MRI)); + GTrunc *Trunc = cast(getDefIgnoringCopies(Zext->getSrcReg(), MRI)); + + Register Dst = Zext->getReg(0); + Register Src = Trunc->getSrcReg(); + + LLT DstTy = MRI.getType(Dst); + LLT SrcTy = MRI.getType(Src); + + if (DstTy == SrcTy) { + MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); }; + return true; + } + + if (DstTy.getScalarSizeInBits() < SrcTy.getScalarSizeInBits() && + isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}})) { + MatchInfo = [=](MachineIRBuilder &B) { + B.buildTrunc(Dst, Src, MachineInstr::MIFlag::NoUWrap); + }; + return true; + } + + if (DstTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits() && + isLegalOrBeforeLegalizer({TargetOpcode::G_ZEXT, {DstTy, SrcTy}})) { + MatchInfo = [=](MachineIRBuilder &B) { + B.buildZExt(Dst, Src, MachineInstr::MIFlag::NonNeg); + }; + return true; + } + + return false; +} diff --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp index 529e50c8ebe0..c8199a42d15c 100644 --- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp +++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp @@ -64,8 +64,11 @@ KnownBits GISelKnownBits::getKnownBits(MachineInstr &MI) { KnownBits GISelKnownBits::getKnownBits(Register R) { const LLT Ty = MRI.getType(R); + // Since the number of lanes in a scalable vector is unknown at compile time, + // we track one bit which is implicitly broadcast to all lanes. This means + // that all lanes in a scalable vector are considered demanded. APInt DemandedElts = - Ty.isVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1); + Ty.isFixedVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1); return getKnownBits(R, DemandedElts); } diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 2e8407813ba6..afe270356940 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -490,8 +490,9 @@ MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res, } MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res, - const SrcOp &Op) { - return buildInstr(TargetOpcode::G_ZEXT, Res, Op); + const SrcOp &Op, + std::optional Flags) { + return buildInstr(TargetOpcode::G_ZEXT, Res, Op, Flags); } unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const { @@ -869,9 +870,10 @@ MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID, return buildIntrinsic(ID, Results, HasSideEffects, isConvergent); } -MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res, - const SrcOp &Op) { - return buildInstr(TargetOpcode::G_TRUNC, Res, Op); +MachineInstrBuilder +MachineIRBuilder::buildTrunc(const DstOp &Res, const SrcOp &Op, + std::optional Flags) { + return buildInstr(TargetOpcode::G_TRUNC, Res, Op, Flags); } MachineInstrBuilder diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-with-flags.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-with-flags.mir new file mode 100644 index 000000000000..6eece5c56258 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-with-flags.mir @@ -0,0 +1,353 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s + +--- +name: zext_trunc_nuw +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: zext_trunc_nuw + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: $x1 = COPY [[COPY]](s64) + %0:_(s64) = COPY $x0 + %2:_(s32) = nuw G_TRUNC %0 + %3:_(s64) = G_ZEXT %2 + $x1 = COPY %3 +... +--- +name: zext_trunc_nsw +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: zext_trunc_nsw + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = nsw G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s32) + ; CHECK-NEXT: $x1 = COPY [[ZEXT]](s64) + %0:_(s64) = COPY $x0 + %2:_(s32) = nsw G_TRUNC %0 + %3:_(s64) = G_ZEXT %2 + $x1 = COPY %3 +... +--- +name: zext_trunc +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: zext_trunc + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s32) + ; CHECK-NEXT: $x1 = COPY [[ZEXT]](s64) + %0:_(s64) = COPY $x0 + %2:_(s32) = G_TRUNC %0 + %3:_(s64) = G_ZEXT %2 + $x1 = COPY %3 +... +--- +name: zext_trunc_nuw_vector +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: zext_trunc_nuw_vector + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 + ; CHECK-NEXT: %bv0:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY]](s32), [[COPY1]](s32) + ; CHECK-NEXT: $q0 = COPY %bv0(<4 x s32>) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 + %0:_(s32) = COPY $w0 + %1:_(s32) = COPY $w1 + %2:_(s32) = COPY $w2 + %3:_(s32) = COPY $w3 + %bv0:_(<4 x s32>) = G_BUILD_VECTOR %0:_(s32), %1:_(s32), %0:_(s32), %1:_(s32) + %trunc:_(<4 x s16>) = nuw G_TRUNC %bv0 + %zext:_(<4 x s32>) = G_ZEXT %trunc + $q0 = COPY %zext(<4 x s32>) + RET_ReallyLR implicit $w0 +... +--- +name: sext_trunc_nsw +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: sext_trunc_nsw + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: $x1 = COPY [[COPY]](s64) + %0:_(s64) = COPY $x0 + %2:_(s32) = nsw G_TRUNC %0 + %3:_(s64) = G_SEXT %2 + $x1 = COPY %3 +... +--- +name: sext_trunc_nuw +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: sext_trunc_nuw + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = nuw G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s32) + ; CHECK-NEXT: $x1 = COPY [[SEXT]](s64) + %0:_(s64) = COPY $x0 + %2:_(s32) = nuw G_TRUNC %0 + %3:_(s64) = G_SEXT %2 + $x1 = COPY %3 +... +--- +name: sext_trunc +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: sext_trunc + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s32) + ; CHECK-NEXT: $x1 = COPY [[SEXT]](s64) + %0:_(s64) = COPY $x0 + %2:_(s32) = G_TRUNC %0 + %3:_(s64) = G_SEXT %2 + $x1 = COPY %3 +... +--- +name: sext_trunc_nsw_types_wrong +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: sext_trunc_nsw_types_wrong + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = nsw G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: $w1 = COPY [[TRUNC]](s32) + %0:_(s64) = COPY $x0 + %2:_(s16) = nsw G_TRUNC %0 + %3:_(s32) = G_SEXT %2 + $w1 = COPY %3 +... +--- +name: sext_trunc_nsw_nuw +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: sext_trunc_nsw_nuw + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: $x1 = COPY [[COPY]](s64) + %0:_(s64) = COPY $x0 + %2:_(s32) = nsw nuw G_TRUNC %0 + %3:_(s64) = G_SEXT %2 + $x1 = COPY %3 +... +--- +name: sext_trunc_nsw_nuw_vector +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: sext_trunc_nsw_nuw_vector + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3 + ; CHECK-NEXT: %bv0:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: $q0 = COPY %bv0(<4 x s32>) + %0:_(s32) = COPY $w0 + %1:_(s32) = COPY $w1 + %2:_(s32) = COPY $w2 + %3:_(s32) = COPY $w3 + %bv0:_(<4 x s32>) = G_BUILD_VECTOR %0:_(s32), %1:_(s32), %2:_(s32), %3:_(s32) + %t:_(<4 x s16>) = nsw nuw G_TRUNC %bv0 + %s:_(<4 x s32>) = G_SEXT %t + $q0 = COPY %s +... +--- +name: zext_trunc_vector +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: zext_trunc_vector + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3 + ; CHECK-NEXT: %bv0:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: %t:_(<4 x s16>) = G_TRUNC %bv0(<4 x s32>) + ; CHECK-NEXT: %z:_(<4 x s32>) = G_ZEXT %t(<4 x s16>) + ; CHECK-NEXT: $q0 = COPY %z(<4 x s32>) + %0:_(s32) = COPY $w0 + %1:_(s32) = COPY $w1 + %2:_(s32) = COPY $w2 + %3:_(s32) = COPY $w3 + %bv0:_(<4 x s32>) = G_BUILD_VECTOR %0:_(s32), %1:_(s32), %2:_(s32), %3:_(s32) + %t:_(<4 x s16>) = G_TRUNC %bv0 + %z:_(<4 x s32>) = G_ZEXT %t + $q0 = COPY %z +... +--- +name: zext_trunc_nsw_vector +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: zext_trunc_nsw_vector + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3 + ; CHECK-NEXT: %bv0:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: %t:_(<4 x s16>) = nsw G_TRUNC %bv0(<4 x s32>) + ; CHECK-NEXT: %z:_(<4 x s32>) = G_ZEXT %t(<4 x s16>) + ; CHECK-NEXT: $q0 = COPY %z(<4 x s32>) + %0:_(s32) = COPY $w0 + %1:_(s32) = COPY $w1 + %2:_(s32) = COPY $w2 + %3:_(s32) = COPY $w3 + %bv0:_(<4 x s32>) = G_BUILD_VECTOR %0:_(s32), %1:_(s32), %2:_(s32), %3:_(s32) + %t:_(<4 x s16>) = nsw G_TRUNC %bv0 + %z:_(<4 x s32>) = G_ZEXT %t + $q0 = COPY %z +... +--- +name: zext_trunc_nuw_vector2 +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: zext_trunc_nuw_vector2 + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3 + ; CHECK-NEXT: %bv0:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: $q0 = COPY %bv0(<4 x s32>) + %0:_(s32) = COPY $w0 + %1:_(s32) = COPY $w1 + %2:_(s32) = COPY $w2 + %3:_(s32) = COPY $w3 + %bv0:_(<4 x s32>) = G_BUILD_VECTOR %0:_(s32), %1:_(s32), %2:_(s32), %3:_(s32) + %t:_(<4 x s16>) = nuw G_TRUNC %bv0 + %z:_(<4 x s32>) = G_ZEXT %t + $q0 = COPY %z +... +--- +name: zext_trunc_nuw_vector_wrong_type +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: zext_trunc_nuw_vector_wrong_type + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: %bv0:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64) + ; CHECK-NEXT: %z:_(<2 x s32>) = nuw G_TRUNC %bv0(<2 x s64>) + ; CHECK-NEXT: $d0 = COPY %z(<2 x s32>) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %bv0:_(<2 x s64>) = G_BUILD_VECTOR %0:_(s64), %1:_(s64) + %t:_(<2 x s16>) = nuw G_TRUNC %bv0 + %z:_(<2 x s32>) = G_ZEXT %t + $d0 = COPY %z +... +--- +name: zext_trunc_nuw_scalable_vector +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: zext_trunc_nuw_scalable_vector + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: %sv0:_() = G_SPLAT_VECTOR [[COPY]](s64) + ; CHECK-NEXT: $z0 = COPY %sv0() + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %sv0:_() = G_SPLAT_VECTOR %0:_(s64) + %t:_() = nuw G_TRUNC %sv0 + %z:_() = G_ZEXT %t + $z0 = COPY %z +... +--- +name: zext_trunc_nuw_to_zext +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: zext_trunc_nuw_to_zext + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: %2:_(s64) = nneg G_ZEXT [[COPY]](s32) + ; CHECK-NEXT: $x1 = COPY %2(s64) + %0:_(s32) = COPY $w0 + %2:_(s16) = nuw G_TRUNC %0 + %3:_(s64) = G_ZEXT %2 + $x1 = COPY %3 +... +--- +name: zext_trunc_nuw_to_trunc +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: zext_trunc_nuw_to_trunc + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = nuw G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: $w1 = COPY [[TRUNC]](s32) + %0:_(s64) = COPY $x0 + %2:_(s16) = nuw G_TRUNC %0 + %3:_(s32) = G_ZEXT %2 + $w1 = COPY %3 +... +--- +name: sext_trunc_nsw_to_sext +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: sext_trunc_nsw_to_sext + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32) + ; CHECK-NEXT: $x1 = COPY [[SEXT]](s64) + %0:_(s32) = COPY $w0 + %2:_(s16) = nsw G_TRUNC %0 + %3:_(s64) = G_SEXT %2 + $x1 = COPY %3 +... +--- +name: sext_trunc_nsw_to_trunc +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: sext_trunc_nsw_to_trunc + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = nsw G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: $w1 = COPY [[TRUNC]](s32) + %0:_(s64) = COPY $x0 + %2:_(s16) = nsw G_TRUNC %0 + %3:_(s32) = G_SEXT %2 + $w1 = COPY %3 +... -- GitLab From db4cf7c0fc713c09bbe10dd2be4a3d0fb081014c Mon Sep 17 00:00:00 2001 From: Renato Golin Date: Wed, 8 May 2024 13:33:20 +0100 Subject: [PATCH 020/328] Update CODEOWNERS Adding myself to linalg dialect --- .github/CODEOWNERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index ad81bf1684b6..e25b2f50b1b4 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -64,8 +64,8 @@ clang/test/AST/Interp/ @tbaederr /mlir/Dialect/*/Transforms/Bufferize.cpp @matthias-springer # Linalg Dialect in MLIR. -/mlir/include/mlir/Dialect/Linalg/* @dcaballe @nicolasvasilache -/mlir/lib/Dialect/Linalg/* @dcaballe @nicolasvasilache +/mlir/include/mlir/Dialect/Linalg/* @dcaballe @nicolasvasilache @rengolin +/mlir/lib/Dialect/Linalg/* @dcaballe @nicolasvasilache @rengolin /mlir/lib/Dialect/Linalg/Transforms/DecomposeLinalgOps.cpp @MaheshRavishankar @nicolasvasilache /mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp @MaheshRavishankar @nicolasvasilache /mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp @MaheshRavishankar @nicolasvasilache -- GitLab From c84c74e67839a5207d7c6318fc37e607f088a994 Mon Sep 17 00:00:00 2001 From: Paul Walker Date: Fri, 3 May 2024 15:55:24 +0100 Subject: [PATCH 021/328] [LLVM][CodeGen][SVE] Add tests for vector extracts from unpacked types. --- .../sve-extract-fixed-from-scalable-vector.ll | 78 ++++++++++++++++++- 1 file changed, 76 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll b/llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll index b9c531fe3352..e91aac430110 100644 --- a/llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll +++ b/llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll @@ -307,11 +307,85 @@ define <4 x i64> @extract_v4i64_nxv8i64_0( %arg) { ret <4 x i64> %ext } +define <4 x half> @extract_v4f16_nxv2f16_0( %arg) { +; CHECK-LABEL: extract_v4f16_nxv2f16_0: +; CHECK: // %bb.0: +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: addvl sp, sp, #-1 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: cntd x8 +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: addpl x9, sp, #6 +; CHECK-NEXT: subs x8, x8, #4 +; CHECK-NEXT: csel x8, xzr, x8, lo +; CHECK-NEXT: st1h { z0.d }, p0, [sp, #3, mul vl] +; CHECK-NEXT: cmp x8, #0 +; CHECK-NEXT: csel x8, x8, xzr, lo +; CHECK-NEXT: lsl x8, x8, #1 +; CHECK-NEXT: ldr d0, [x9, x8] +; CHECK-NEXT: addvl sp, sp, #1 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret + %ext = call <4 x half> @llvm.vector.extract.v4f16.nxv2f16( %arg, i64 0) + ret <4 x half> %ext +} + +define <4 x half> @extract_v4f16_nxv2f16_4( %arg) { +; CHECK-LABEL: extract_v4f16_nxv2f16_4: +; CHECK: // %bb.0: +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: addvl sp, sp, #-1 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: cntd x8 +; CHECK-NEXT: mov w9, #4 // =0x4 +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: subs x8, x8, #4 +; CHECK-NEXT: csel x8, xzr, x8, lo +; CHECK-NEXT: st1h { z0.d }, p0, [sp, #3, mul vl] +; CHECK-NEXT: cmp x8, #4 +; CHECK-NEXT: csel x8, x8, x9, lo +; CHECK-NEXT: addpl x9, sp, #6 +; CHECK-NEXT: lsl x8, x8, #1 +; CHECK-NEXT: ldr d0, [x9, x8] +; CHECK-NEXT: addvl sp, sp, #1 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret + %ext = call <4 x half> @llvm.vector.extract.v4f16.nxv2f16( %arg, i64 4) + ret <4 x half> %ext +} + +define <2 x half> @extract_v2f16_nxv4f16_2( %arg) { +; CHECK-LABEL: extract_v2f16_nxv4f16_2: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.s, z0.s[3] +; CHECK-NEXT: mov z0.s, z0.s[2] +; CHECK-NEXT: mov v0.h[1], v1.h[0] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %ext = call <2 x half> @llvm.vector.extract.v2f16.nxv4f16( %arg, i64 2) + ret <2 x half> %ext +} + +define <2 x half> @extract_v2f16_nxv4f16_6( %arg) { +; CHECK-LABEL: extract_v2f16_nxv4f16_6: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.s, z0.s[7] +; CHECK-NEXT: mov z0.s, z0.s[6] +; CHECK-NEXT: mov v0.h[1], v1.h[0] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %ext = call <2 x half> @llvm.vector.extract.v2f16.nxv4f16( %arg, i64 6) + ret <2 x half> %ext +} -declare <2 x i64> @llvm.vector.extract.v2i64.nxv8i64(, i64) -declare <4 x i64> @llvm.vector.extract.v4i64.nxv8i64(, i64) declare <4 x float> @llvm.vector.extract.v4f32.nxv16f32(, i64) declare <2 x float> @llvm.vector.extract.v2f32.nxv16f32(, i64) +declare <4 x half> @llvm.vector.extract.v4f16.nxv2f16(, i64); +declare <2 x half> @llvm.vector.extract.v2f16.nxv4f16(, i64); +declare <2 x i64> @llvm.vector.extract.v2i64.nxv8i64(, i64) +declare <4 x i64> @llvm.vector.extract.v4i64.nxv8i64(, i64) declare <4 x i32> @llvm.vector.extract.v4i32.nxv16i32(, i64) declare <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(, i64) declare <8 x i16> @llvm.vector.extract.v8i16.nxv32i16(, i64) -- GitLab From 686a206b2665b6ba9245980489daa79dc8547079 Mon Sep 17 00:00:00 2001 From: Nabeel Omer Date: Wed, 8 May 2024 14:32:56 +0100 Subject: [PATCH 022/328] [SampleProfileLoader] Fix integer overflow in generateMDProfMetadata (#90217) This patch fixes an integer overflow in the SampleProfileLoader pass. The issue occurs when weights are saturated and Profi isn't being used. This patch also adds a newline to a debug message to make it more readable. --- llvm/lib/Transforms/IPO/SampleProfile.cpp | 6 +- .../SampleProfile/Inputs/overflow.proftext | 2 + .../test/Transforms/SampleProfile/overflow.ll | 77 +++++++++++++++++++ 3 files changed, 83 insertions(+), 2 deletions(-) create mode 100644 llvm/test/Transforms/SampleProfile/Inputs/overflow.proftext create mode 100644 llvm/test/Transforms/SampleProfile/overflow.ll diff --git a/llvm/lib/Transforms/IPO/SampleProfile.cpp b/llvm/lib/Transforms/IPO/SampleProfile.cpp index 6cbd138842c8..0920179fb76b 100644 --- a/llvm/lib/Transforms/IPO/SampleProfile.cpp +++ b/llvm/lib/Transforms/IPO/SampleProfile.cpp @@ -1715,13 +1715,15 @@ void SampleProfileLoader::generateMDProfMetadata(Function &F) { // if needed. Sample counts in profiles are 64-bit unsigned values, // but internally branch weights are expressed as 32-bit values. if (Weight > std::numeric_limits::max()) { - LLVM_DEBUG(dbgs() << " (saturated due to uint32_t overflow)"); + LLVM_DEBUG(dbgs() << " (saturated due to uint32_t overflow)\n"); Weight = std::numeric_limits::max(); } if (!SampleProfileUseProfi) { // Weight is added by one to avoid propagation errors introduced by // 0 weights. - Weights.push_back(static_cast(Weight + 1)); + Weights.push_back(static_cast( + Weight == std::numeric_limits::max() ? Weight + : Weight + 1)); } else { // Profi creates proper weights that do not require "+1" adjustments but // we evenly split the weight among branches with the same destination. diff --git a/llvm/test/Transforms/SampleProfile/Inputs/overflow.proftext b/llvm/test/Transforms/SampleProfile/Inputs/overflow.proftext new file mode 100644 index 000000000000..753294a49e99 --- /dev/null +++ b/llvm/test/Transforms/SampleProfile/Inputs/overflow.proftext @@ -0,0 +1,2 @@ +_Z3testi:29600000000:29600000000 + 5: 29600000000 diff --git a/llvm/test/Transforms/SampleProfile/overflow.ll b/llvm/test/Transforms/SampleProfile/overflow.ll new file mode 100644 index 000000000000..06be3ce50023 --- /dev/null +++ b/llvm/test/Transforms/SampleProfile/overflow.ll @@ -0,0 +1,77 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4 + +; Checks that we are able to handle overflowing counters correctly. + +; RUN: opt < %s -passes='sample-profile,print' -sample-profile-file=%S/Inputs/overflow.proftext -disable-output 2>&1 | FileCheck %s + +; Original Source: +; int sqrt(int); +; int test(int i) { +; if (i == 5) { +; return 42; +; } +; else { +; return sqrt(i); +; } +;} + +define dso_local noundef i32 @_Z3testi(i32 noundef %i) local_unnamed_addr #0 !dbg !10 { +; CHECK-LABEL: '_Z3testi' +; CHECK-NEXT: ---- Branch Probabilities ---- +; CHECK-NEXT: edge %entry -> %return probability is 0x00000000 / 0x80000000 = 0.00% +; CHECK-NEXT: edge %entry -> %if.else probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] +; CHECK-NEXT: edge %if.else -> %return probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge] +; +entry: + tail call void @llvm.dbg.value(metadata i32 %i, metadata !16, metadata !DIExpression()), !dbg !17 + %cmp = icmp eq i32 %i, 5, !dbg !18 + br i1 %cmp, label %return, label %if.else, !dbg !20 + +if.else: ; preds = %entry + %call = tail call noundef i32 @_Z4sqrti(i32 noundef %i), !dbg !21 + br label %return, !dbg !23 + +return: ; preds = %entry, %if.else + %retval.0 = phi i32 [ %call, %if.else ], [ 42, %entry ], !dbg !24 + ret i32 %retval.0, !dbg !25 +} + +declare !dbg !26 noundef i32 @_Z4sqrti(i32 noundef) + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) + +attributes #0 = { "use-sample-profile" } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8} +!llvm.ident = !{!9} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.cpp", directory: "/", checksumkind: CSK_MD5, checksum: "cb38d90153a7ebdd6ecf3058eb0524c7") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 8, !"PIC Level", i32 2} +!6 = !{i32 7, !"PIE Level", i32 2} +!7 = !{i32 7, !"uwtable", i32 2} +!8 = !{i32 7, !"debug-info-assignment-tracking", i1 true} +!9 = !{!"clang"} +!10 = distinct !DISubprogram(name: "test", linkageName: "_Z3loli", scope: !11, file: !11, line: 3, type: !12, scopeLine: 3, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !15) +!11 = !DIFile(filename: "./test.cpp", directory: "/", checksumkind: CSK_MD5, checksum: "cb38d90153a7ebdd6ecf3058eb0524c7") +!12 = !DISubroutineType(types: !13) +!13 = !{!14, !14} +!14 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!15 = !{!16} +!16 = !DILocalVariable(name: "i", arg: 1, scope: !10, file: !11, line: 3, type: !14) +!17 = !DILocation(line: 0, scope: !10) +!18 = !DILocation(line: 4, column: 11, scope: !19) +!19 = distinct !DILexicalBlock(scope: !10, file: !11, line: 4, column: 9) +!20 = !DILocation(line: 4, column: 9, scope: !10) +!21 = !DILocation(line: 8, column: 16, scope: !22) +!22 = distinct !DILexicalBlock(scope: !19, file: !11, line: 7, column: 10) +!23 = !DILocation(line: 8, column: 9, scope: !22) +!24 = !DILocation(line: 0, scope: !19) +!25 = !DILocation(line: 10, column: 1, scope: !10) +!26 = !DISubprogram(name: "sqrt", linkageName: "_Z4sqrti", scope: !11, file: !11, line: 1, type: !12, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) + -- GitLab From 3ceacd8b9567a25308f7aaa73d266ee3b4c6ab5f Mon Sep 17 00:00:00 2001 From: Paul T Robinson Date: Wed, 8 May 2024 06:37:24 -0700 Subject: [PATCH 023/328] [Coro] Relax a debug-info test (#91401) Debug-info metadata does not have a strictly defined order. Check that elements are linked to each other correctly, not that metadata appears in a particular order. --- clang/test/CodeGenCoroutines/coro-dwarf.cpp | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/clang/test/CodeGenCoroutines/coro-dwarf.cpp b/clang/test/CodeGenCoroutines/coro-dwarf.cpp index f951b63dc117..0ab70ef55c1d 100644 --- a/clang/test/CodeGenCoroutines/coro-dwarf.cpp +++ b/clang/test/CodeGenCoroutines/coro-dwarf.cpp @@ -71,14 +71,10 @@ void f_coro(int val, MoveOnly moParam, MoveAndCopy mcParam) { // CHECK: !{{[0-9]+}} = !DILocalVariable(name: "mcParam", arg: 3, scope: ![[SP]], file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) // CHECK: !{{[0-9]+}} = !DILocalVariable(name: "__promise", -// CHECK: !{{[0-9]+}} = distinct !DISubprogram(linkageName: "_Z6f_coroi8MoveOnly11MoveAndCopy.__await_suspend_wrapper__init" -// CHECK-NEXT: !{{[0-9]+}} = !DIFile -// CHECK-NEXT: !{{[0-9]+}} = !DISubroutineType -// CHECK-NEXT: !{{[0-9]+}} = !DILocalVariable(arg: 1, -// CHECK-NEXT: !{{[0-9]+}} = !DILocation -// CHECK-NEXT: !{{[0-9]+}} = !DILocalVariable(arg: 2, +// CHECK: ![[INIT:[0-9]+]] = distinct !DISubprogram(linkageName: "_Z6f_coroi8MoveOnly11MoveAndCopy.__await_suspend_wrapper__init" +// CHECK: !{{[0-9]+}} = !DILocalVariable(arg: 1, scope: ![[INIT]] +// CHECK: !{{[0-9]+}} = !DILocalVariable(arg: 2, scope: ![[INIT]] -// CHECK: !{{[0-9]+}} = distinct !DISubprogram(linkageName: "_Z6f_coroi8MoveOnly11MoveAndCopy.__await_suspend_wrapper__final" -// CHECK-NEXT: !{{[0-9]+}} = !DILocalVariable(arg: 1, -// CHECK-NEXT: !{{[0-9]+}} = !DILocation -// CHECK-NEXT: !{{[0-9]+}} = !DILocalVariable(arg: 2, +// CHECK: ![[FINAL:[0-9]+]] = distinct !DISubprogram(linkageName: "_Z6f_coroi8MoveOnly11MoveAndCopy.__await_suspend_wrapper__final" +// CHECK: !{{[0-9]+}} = !DILocalVariable(arg: 1, scope: ![[FINAL]] +// CHECK: !{{[0-9]+}} = !DILocalVariable(arg: 2, scope: ![[FINAL]] -- GitLab From 665af09a86b8d80af33f170fca89ced9986cf1e5 Mon Sep 17 00:00:00 2001 From: Xiang Li Date: Wed, 8 May 2024 06:40:06 -0700 Subject: [PATCH 024/328] [DirectX backend] emits metadata for DXIL version. (#88350) Emit named metadata "dx.version" for DXIL version. Default to DXIL 1.0 --- llvm/include/llvm/TargetParser/Triple.h | 4 + llvm/lib/Target/DirectX/DXILMetadata.cpp | 12 +++ llvm/lib/Target/DirectX/DXILMetadata.h | 1 + .../Target/DirectX/DXILTranslateMetadata.cpp | 1 + llvm/lib/TargetParser/Triple.cpp | 11 +++ .../CodeGen/DirectX/Metadata/dxilVer-1.0.ll | 12 +++ .../CodeGen/DirectX/Metadata/dxilVer-1.8.ll | 12 +++ llvm/unittests/TargetParser/TripleTest.cpp | 79 +++++++++++++++++++ 8 files changed, 132 insertions(+) create mode 100644 llvm/test/CodeGen/DirectX/Metadata/dxilVer-1.0.ll create mode 100644 llvm/test/CodeGen/DirectX/Metadata/dxilVer-1.8.ll diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h index 7da30e6cf96f..20cca5928782 100644 --- a/llvm/include/llvm/TargetParser/Triple.h +++ b/llvm/include/llvm/TargetParser/Triple.h @@ -428,6 +428,10 @@ public: /// (SubArch). This should only be called with Vulkan SPIR-V triples. VersionTuple getVulkanVersion() const; + /// Parse the DXIL version number from the DXIL version + /// (SubArch). This should only be called with DXIL triples. + VersionTuple getDXILVersion() const; + /// @} /// @name Direct Component Access /// @{ diff --git a/llvm/lib/Target/DirectX/DXILMetadata.cpp b/llvm/lib/Target/DirectX/DXILMetadata.cpp index 03758dc76e7e..ed0434ac98a1 100644 --- a/llvm/lib/Target/DirectX/DXILMetadata.cpp +++ b/llvm/lib/Target/DirectX/DXILMetadata.cpp @@ -90,6 +90,18 @@ void dxil::createShaderModelMD(Module &M) { Entry->addOperand(MDNode::get(Ctx, Vals)); } +void dxil::createDXILVersionMD(Module &M) { + Triple TT(Triple::normalize(M.getTargetTriple())); + VersionTuple Ver = TT.getDXILVersion(); + LLVMContext &Ctx = M.getContext(); + IRBuilder<> B(Ctx); + NamedMDNode *Entry = M.getOrInsertNamedMetadata("dx.version"); + Metadata *Vals[2]; + Vals[0] = ConstantAsMetadata::get(B.getInt32(Ver.getMajor())); + Vals[1] = ConstantAsMetadata::get(B.getInt32(Ver.getMinor().value_or(0))); + Entry->addOperand(MDNode::get(Ctx, Vals)); +} + static uint32_t getShaderStage(Triple::EnvironmentType Env) { return (uint32_t)Env - (uint32_t)llvm::Triple::Pixel; } diff --git a/llvm/lib/Target/DirectX/DXILMetadata.h b/llvm/lib/Target/DirectX/DXILMetadata.h index cd9f4c83fbd0..e05db8d5370d 100644 --- a/llvm/lib/Target/DirectX/DXILMetadata.h +++ b/llvm/lib/Target/DirectX/DXILMetadata.h @@ -34,6 +34,7 @@ public: }; void createShaderModelMD(Module &M); +void createDXILVersionMD(Module &M); void createEntryMD(Module &M, const uint64_t ShaderFlags); } // namespace dxil diff --git a/llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp b/llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp index 80d94bf0c9d4..ae6d6f96904c 100644 --- a/llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp +++ b/llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp @@ -48,6 +48,7 @@ bool DXILTranslateMetadata::runOnModule(Module &M) { if (ValVerMD.isEmpty()) ValVerMD.update(VersionTuple(1, 0)); dxil::createShaderModelMD(M); + dxil::createDXILVersionMD(M); const dxil::Resources &Res = getAnalysis().getDXILResource(); diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp index f3f244c814e7..18ec60296810 100644 --- a/llvm/lib/TargetParser/Triple.cpp +++ b/llvm/lib/TargetParser/Triple.cpp @@ -1420,6 +1420,17 @@ VersionTuple Triple::getVulkanVersion() const { return VersionTuple(0); } +VersionTuple Triple::getDXILVersion() const { + if (getArch() != dxil || getOS() != ShaderModel) + llvm_unreachable("invalid DXIL triple"); + StringRef Arch = getArchName(); + Arch.consume_front("dxilv"); + VersionTuple DXILVersion = parseVersionFromName(Arch); + // FIXME: validate DXIL version against Shader Model version. + // Tracked by https://github.com/llvm/llvm-project/issues/91388 + return DXILVersion; +} + void Triple::setTriple(const Twine &Str) { *this = Triple(Str); } diff --git a/llvm/test/CodeGen/DirectX/Metadata/dxilVer-1.0.ll b/llvm/test/CodeGen/DirectX/Metadata/dxilVer-1.0.ll new file mode 100644 index 000000000000..254479e5f94c --- /dev/null +++ b/llvm/test/CodeGen/DirectX/Metadata/dxilVer-1.0.ll @@ -0,0 +1,12 @@ +; RUN: opt -S -dxil-metadata-emit %s | FileCheck %s +target triple = "dxil-pc-shadermodel6.0-vertex" + +; CHECK: !dx.version = !{![[DXVER:[0-9]+]]} +; CHECK: ![[DXVER]] = !{i32 1, i32 0} + +define void @entry() #0 { +entry: + ret void +} + +attributes #0 = { noinline nounwind "hlsl.shader"="vertex" } diff --git a/llvm/test/CodeGen/DirectX/Metadata/dxilVer-1.8.ll b/llvm/test/CodeGen/DirectX/Metadata/dxilVer-1.8.ll new file mode 100644 index 000000000000..efeb5a1b2486 --- /dev/null +++ b/llvm/test/CodeGen/DirectX/Metadata/dxilVer-1.8.ll @@ -0,0 +1,12 @@ +; RUN: opt -S -dxil-metadata-emit %s | FileCheck %s +target triple = "dxil-pc-shadermodel6.8-compute" + +; CHECK: !dx.version = !{![[DXVER:[0-9]+]]} +; CHECK: ![[DXVER]] = !{i32 1, i32 8} + +define void @entry() #0 { +entry: + ret void +} + +attributes #0 = { noinline nounwind "hlsl.numthreads"="1,2,1" "hlsl.shader"="compute" } diff --git a/llvm/unittests/TargetParser/TripleTest.cpp b/llvm/unittests/TargetParser/TripleTest.cpp index b8f5fbd87407..8e90ee6858f4 100644 --- a/llvm/unittests/TargetParser/TripleTest.cpp +++ b/llvm/unittests/TargetParser/TripleTest.cpp @@ -437,6 +437,85 @@ TEST(TripleTest, ParsedIDs) { EXPECT_EQ(VersionTuple(1, 3), T.getVulkanVersion()); EXPECT_EQ(Triple::Compute, T.getEnvironment()); + T = Triple("dxilv1.0--shadermodel6.0-pixel"); + EXPECT_EQ(Triple::dxil, T.getArch()); + EXPECT_EQ(Triple::DXILSubArch_v1_0, T.getSubArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::ShaderModel, T.getOS()); + EXPECT_EQ(VersionTuple(1, 0), T.getDXILVersion()); + EXPECT_EQ(Triple::Pixel, T.getEnvironment()); + + T = Triple("dxilv1.1--shadermodel6.1-vertex"); + EXPECT_EQ(Triple::dxil, T.getArch()); + EXPECT_EQ(Triple::DXILSubArch_v1_1, T.getSubArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::ShaderModel, T.getOS()); + EXPECT_EQ(VersionTuple(1, 1), T.getDXILVersion()); + EXPECT_EQ(Triple::Vertex, T.getEnvironment()); + + T = Triple("dxilv1.2--shadermodel6.2-geometry"); + EXPECT_EQ(Triple::dxil, T.getArch()); + EXPECT_EQ(Triple::DXILSubArch_v1_2, T.getSubArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::ShaderModel, T.getOS()); + EXPECT_EQ(VersionTuple(1, 2), T.getDXILVersion()); + EXPECT_EQ(Triple::Geometry, T.getEnvironment()); + + T = Triple("dxilv1.3--shadermodel6.3-library"); + EXPECT_EQ(Triple::dxil, T.getArch()); + EXPECT_EQ(Triple::DXILSubArch_v1_3, T.getSubArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::ShaderModel, T.getOS()); + EXPECT_EQ(VersionTuple(1, 3), T.getDXILVersion()); + EXPECT_EQ(Triple::Library, T.getEnvironment()); + + T = Triple("dxilv1.4--shadermodel6.4-hull"); + EXPECT_EQ(Triple::dxil, T.getArch()); + EXPECT_EQ(Triple::DXILSubArch_v1_4, T.getSubArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::ShaderModel, T.getOS()); + EXPECT_EQ(VersionTuple(1, 4), T.getDXILVersion()); + EXPECT_EQ(Triple::Hull, T.getEnvironment()); + + T = Triple("dxilv1.5--shadermodel6.5-domain"); + EXPECT_EQ(Triple::dxil, T.getArch()); + EXPECT_EQ(Triple::DXILSubArch_v1_5, T.getSubArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::ShaderModel, T.getOS()); + EXPECT_EQ(VersionTuple(1, 5), T.getDXILVersion()); + EXPECT_EQ(Triple::Domain, T.getEnvironment()); + + T = Triple("dxilv1.6--shadermodel6.6-compute"); + EXPECT_EQ(Triple::dxil, T.getArch()); + EXPECT_EQ(Triple::DXILSubArch_v1_6, T.getSubArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::ShaderModel, T.getOS()); + EXPECT_EQ(VersionTuple(1, 6), T.getDXILVersion()); + EXPECT_EQ(Triple::Compute, T.getEnvironment()); + + T = Triple("dxilv1.7-unknown-shadermodel6.7-mesh"); + EXPECT_EQ(Triple::dxil, T.getArch()); + EXPECT_EQ(Triple::DXILSubArch_v1_7, T.getSubArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::ShaderModel, T.getOS()); + EXPECT_EQ(VersionTuple(1, 7), T.getDXILVersion()); + EXPECT_EQ(Triple::Mesh, T.getEnvironment()); + + T = Triple("dxilv1.8-unknown-shadermodel6.8-amplification"); + EXPECT_EQ(Triple::dxil, T.getArch()); + EXPECT_EQ(Triple::DXILSubArch_v1_8, T.getSubArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::ShaderModel, T.getOS()); + EXPECT_EQ(VersionTuple(1, 8), T.getDXILVersion()); + EXPECT_EQ(Triple::Amplification, T.getEnvironment()); + + T = Triple("dxilv1.8-unknown-shadermodel6.15-library"); + EXPECT_EQ(Triple::dxil, T.getArch()); + EXPECT_EQ(Triple::DXILSubArch_v1_8, T.getSubArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::ShaderModel, T.getOS()); + EXPECT_EQ(VersionTuple(1, 8), T.getDXILVersion()); + T = Triple("x86_64-unknown-fuchsia"); EXPECT_EQ(Triple::x86_64, T.getArch()); EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); -- GitLab From 40b322baef143df271d8b9142028aaeeec2a4d78 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Wed, 8 May 2024 14:46:27 +0100 Subject: [PATCH 025/328] [SCEV] Add tests for missed NSW preservation during loop guard handling. Add test coverage for missed simplification. --- .../backedge-taken-count-guard-info.ll | 34 ++++++++++++++ ...count-expansion-loop-guard-preserve-nsw.ll | 47 +++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 llvm/test/Transforms/IndVarSimplify/trip-count-expansion-loop-guard-preserve-nsw.ll diff --git a/llvm/test/Analysis/ScalarEvolution/backedge-taken-count-guard-info.ll b/llvm/test/Analysis/ScalarEvolution/backedge-taken-count-guard-info.ll index 1f475e80e562..da4487ce9cd4 100644 --- a/llvm/test/Analysis/ScalarEvolution/backedge-taken-count-guard-info.ll +++ b/llvm/test/Analysis/ScalarEvolution/backedge-taken-count-guard-info.ll @@ -69,4 +69,38 @@ exit: ret void } +declare void @use(i32) + +define void @rewrite_preserve_add_nsw(i32 %a) { +; CHECK-LABEL: 'rewrite_preserve_add_nsw' +; CHECK-NEXT: Classifying expressions for: @rewrite_preserve_add_nsw +; CHECK-NEXT: %add = add nsw i32 %a, 4 +; CHECK-NEXT: --> (4 + %a) U: [-2147483644,-2147483648) S: [-2147483644,-2147483648) +; CHECK-NEXT: %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] +; CHECK-NEXT: --> {0,+,1}<%loop> U: [0,-2147483648) S: [0,-2147483648) Exits: (0 smax (4 + %a)) LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %iv.next = add i32 %iv, 1 +; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483647) S: [1,-2147483647) Exits: (1 + (0 smax (4 + %a))) LoopDispositions: { %loop: Computable } +; CHECK-NEXT: Determining loop execution counts for: @rewrite_preserve_add_nsw +; CHECK-NEXT: Loop %loop: backedge-taken count is (0 smax (4 + %a)) +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is i32 2147483647 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (0 smax (4 + %a)) +; CHECK-NEXT: Loop %loop: Trip multiple is 1 +; +entry: + %add = add nsw i32 %a, 4 + call void @use(i32 noundef %add) + %pre = icmp sgt i32 %a, -4 + br i1 %pre, label %loop, label %exit + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] + call void @clobber() + %iv.next = add i32 %iv, 1 + %ec = icmp slt i32 %iv, %add + br i1 %ec, label %loop, label %exit + +exit: + ret void +} + declare void @clobber() diff --git a/llvm/test/Transforms/IndVarSimplify/trip-count-expansion-loop-guard-preserve-nsw.ll b/llvm/test/Transforms/IndVarSimplify/trip-count-expansion-loop-guard-preserve-nsw.ll new file mode 100644 index 000000000000..f86639ea4c50 --- /dev/null +++ b/llvm/test/Transforms/IndVarSimplify/trip-count-expansion-loop-guard-preserve-nsw.ll @@ -0,0 +1,47 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes=indvars -S %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32" + +define void @rewrite_preserve_add_nsw(i32 %a) { +; CHECK-LABEL: define void @rewrite_preserve_add_nsw( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[A]], 4 +; CHECK-NEXT: call void @use(i32 noundef [[ADD]]) +; CHECK-NEXT: [[PRE:%.*]] = icmp sgt i32 [[A]], -4 +; CHECK-NEXT: br i1 [[PRE]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]] +; CHECK: loop.preheader: +; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[ADD]], i32 0) +; CHECK-NEXT: [[TMP0:%.*]] = add nuw i32 [[SMAX]], 1 +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[LOOP_PREHEADER]] ] +; CHECK-NEXT: call void @clobber() +; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp ne i32 [[IV_NEXT]], [[TMP0]] +; CHECK-NEXT: br i1 [[EC]], label [[LOOP]], label [[EXIT_LOOPEXIT:%.*]] +; CHECK: exit.loopexit: +; CHECK-NEXT: br label [[EXIT]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + %add = add nsw i32 %a, 4 + call void @use(i32 noundef %add) + %pre = icmp sgt i32 %a, -4 + br i1 %pre, label %loop, label %exit + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] + call void @clobber() + %iv.next = add i32 %iv, 1 + %ec = icmp slt i32 %iv, %add + br i1 %ec, label %loop, label %exit + +exit: + ret void +} + +declare void @clobber() +declare void @use(i32) -- GitLab From f97f04ec4392c79163179331211ea8c48e61799b Mon Sep 17 00:00:00 2001 From: Daniel Chen Date: Wed, 8 May 2024 09:47:53 -0400 Subject: [PATCH 026/328] [mlir] Fixing a regression that '-D' option of llvm-tblgen is unregistered. (#91329) PR #89664 introduced a regression that it unregistered llvm-tblgen option `-D` for macros. The test `TestOps.cpp` failed due to passing a macros to llvm-tblgen. It caused our internal build to fail because we append `-DLOCAL_NAME` into `LLVM_TABLEGEN_FLANGS` in `llvm/lib/cmake/llvm/TableGen.cmake` as ``` list(APPEND LLVM_TABLEGEN_FLAGS "-DLOCAL_NAME") ``` And in `./llvm/lib/Target/PowerPC/PPC.td`, we check it for some downstream code as: ``` ... #ifdef LOCAL_NAME ... #endif ``` Now we got error message from mlir-src-sharder as ``` mlir-src-sharder -op-shard-index=1 -DLOCAL_NAME llvm-project/mlir/test/lib/Dialect/Test/TestOps.cpp --write-if-changed -o tools/mlir/test/lib/Dialect/Test/TestOps.1.cpp -d tools/mlir/test/lib/Dialect/Test/TestOps.1.cpp.d mlir-src-sharder: Unknown command line argument '-DLOCAL_NAME'. Try: 'llvm-project/build/bin/mlir-src-sharder --help' mlir-src-sharder: Did you mean '-I'? ``` This PR is to fix the regression. --- mlir/tools/mlir-src-sharder/mlir-src-sharder.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/mlir/tools/mlir-src-sharder/mlir-src-sharder.cpp b/mlir/tools/mlir-src-sharder/mlir-src-sharder.cpp index dc1e2939c7d2..5bfc24ef3b47 100644 --- a/mlir/tools/mlir-src-sharder/mlir-src-sharder.cpp +++ b/mlir/tools/mlir-src-sharder/mlir-src-sharder.cpp @@ -62,6 +62,16 @@ int main(int argc, char **argv) { "write-if-changed", llvm::cl::desc("Only write to the output file if it changed")); + // `ResetCommandLineParser` at the above unregistered the "D" option + // of `llvm-tblgen`, which caused `TestOps.cpp` to fail due to + // "Unknnown command line argument '-D...`" when a macros name is + // present. The following is a workaround to re-register it again. + llvm::cl::list MacroNames( + "D", + llvm::cl::desc( + "Name of the macro to be defined -- ignored by mlir-src-sharder"), + llvm::cl::value_desc("macro name"), llvm::cl::Prefix); + llvm::InitLLVM y(argc, argv); llvm::cl::ParseCommandLineOptions(argc, argv); -- GitLab From 9c09b0840e82490ed194207adc03d3e7284b8764 Mon Sep 17 00:00:00 2001 From: Xiang Li Date: Wed, 8 May 2024 06:48:04 -0700 Subject: [PATCH 027/328] Revert "[HLSL] Support packoffset attribute in AST (#89836)" (#91473) This reverts commit c5509fedc5757fffece385d9d068e36b26793ade. --- clang/include/clang/Basic/Attr.td | 12 -- clang/include/clang/Basic/AttrDocs.td | 20 --- clang/include/clang/Basic/DiagnosticGroups.td | 3 - .../clang/Basic/DiagnosticParseKinds.td | 2 - .../clang/Basic/DiagnosticSemaKinds.td | 5 - clang/lib/Parse/ParseHLSL.cpp | 88 ------------- clang/lib/Sema/SemaDeclAttr.cpp | 52 -------- clang/lib/Sema/SemaHLSL.cpp | 80 ------------ clang/test/AST/HLSL/packoffset.hlsl | 100 -------------- clang/test/SemaHLSL/packoffset-invalid.hlsl | 122 ------------------ 10 files changed, 484 deletions(-) delete mode 100644 clang/test/AST/HLSL/packoffset.hlsl delete mode 100644 clang/test/SemaHLSL/packoffset-invalid.hlsl diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 52552ba48856..0225598cbbe8 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -4415,18 +4415,6 @@ def HLSLResourceBinding: InheritableAttr { let Documentation = [HLSLResourceBindingDocs]; } -def HLSLPackOffset: HLSLAnnotationAttr { - let Spellings = [HLSLAnnotation<"packoffset">]; - let LangOpts = [HLSL]; - let Args = [IntArgument<"Subcomponent">, IntArgument<"Component">]; - let Documentation = [HLSLPackOffsetDocs]; - let AdditionalMembers = [{ - unsigned getOffset() { - return subcomponent * 4 + component; - } - }]; -} - def HLSLSV_DispatchThreadID: HLSLAnnotationAttr { let Spellings = [HLSLAnnotation<"SV_DispatchThreadID">]; let Subjects = SubjectList<[ParmVar, Field]>; diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index f351822ac74b..8e6faabfae64 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -7408,26 +7408,6 @@ The full documentation is available here: https://docs.microsoft.com/en-us/windo }]; } -def HLSLPackOffsetDocs : Documentation { - let Category = DocCatFunction; - let Content = [{ -The packoffset attribute is used to change the layout of a cbuffer. -Attribute spelling in HLSL is: ``packoffset( c[Subcomponent][.component] )``. -A subcomponent is a register number, which is an integer. A component is in the form of [.xyzw]. - -Examples: - -.. code-block:: c++ - - cbuffer A { - float3 a : packoffset(c0.y); - float4 b : packoffset(c4); - } - -The full documentation is available here: https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-variable-packoffset - }]; -} - def HLSLSV_DispatchThreadIDDocs : Documentation { let Category = DocCatFunction; let Content = [{ diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td index 2beb1d45124b..60f87da2a738 100644 --- a/clang/include/clang/Basic/DiagnosticGroups.td +++ b/clang/include/clang/Basic/DiagnosticGroups.td @@ -1507,9 +1507,6 @@ def BranchProtection : DiagGroup<"branch-protection">; // Warnings for HLSL Clang extensions def HLSLExtension : DiagGroup<"hlsl-extensions">; -// Warning for mix packoffset and non-packoffset. -def HLSLMixPackOffset : DiagGroup<"mix-packoffset">; - // Warnings for DXIL validation def DXILValidation : DiagGroup<"dxil-validation">; diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td index bc9d7cacc50b..fdffb35ea0d9 100644 --- a/clang/include/clang/Basic/DiagnosticParseKinds.td +++ b/clang/include/clang/Basic/DiagnosticParseKinds.td @@ -1754,7 +1754,5 @@ def err_hlsl_separate_attr_arg_and_number : Error<"wrong argument format for hls def ext_hlsl_access_specifiers : ExtWarn< "access specifiers are a clang HLSL extension">, InGroup; -def err_hlsl_unsupported_component : Error<"invalid component '%0' used; expected 'x', 'y', 'z', or 'w'">; -def err_hlsl_packoffset_invalid_reg : Error<"invalid resource class specifier '%0' for packoffset, expected 'c'">; } // end of Parser diagnostics diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index d6863f90edb6..9317ae675c72 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -12184,11 +12184,6 @@ def err_hlsl_init_priority_unsupported : Error< def err_hlsl_unsupported_register_type : Error<"invalid resource class specifier '%0' used; expected 'b', 's', 't', or 'u'">; def err_hlsl_unsupported_register_number : Error<"register number should be an integer">; def err_hlsl_expected_space : Error<"invalid space specifier '%0' used; expected 'space' followed by an integer, like space1">; -def warn_hlsl_packoffset_mix : Warning<"cannot mix packoffset elements with nonpackoffset elements in a cbuffer">, - InGroup; -def err_hlsl_packoffset_overlap : Error<"packoffset overlap between %0, %1">; -def err_hlsl_packoffset_cross_reg_boundary : Error<"packoffset cannot cross register boundary">; -def err_hlsl_packoffset_alignment_mismatch : Error<"packoffset at 'y' not match alignment %0 required by %1">; def err_hlsl_pointers_unsupported : Error< "%select{pointers|references}0 are unsupported in HLSL">; diff --git a/clang/lib/Parse/ParseHLSL.cpp b/clang/lib/Parse/ParseHLSL.cpp index e9c8d6dca7bf..f4cbece31f18 100644 --- a/clang/lib/Parse/ParseHLSL.cpp +++ b/clang/lib/Parse/ParseHLSL.cpp @@ -183,94 +183,6 @@ void Parser::ParseHLSLAnnotations(ParsedAttributes &Attrs, return; } } break; - case ParsedAttr::AT_HLSLPackOffset: { - // Parse 'packoffset( c[Subcomponent][.component] )'. - // Check '('. - if (ExpectAndConsume(tok::l_paren, diag::err_expected_lparen_after)) { - SkipUntil(tok::r_paren, StopAtSemi); // skip through ) - return; - } - // Check c[Subcomponent] as an identifier. - if (!Tok.is(tok::identifier)) { - Diag(Tok.getLocation(), diag::err_expected) << tok::identifier; - SkipUntil(tok::r_paren, StopAtSemi); // skip through ) - return; - } - StringRef OffsetStr = Tok.getIdentifierInfo()->getName(); - SourceLocation SubComponentLoc = Tok.getLocation(); - if (OffsetStr[0] != 'c') { - Diag(Tok.getLocation(), diag::err_hlsl_packoffset_invalid_reg) - << OffsetStr; - SkipUntil(tok::r_paren, StopAtSemi); // skip through ) - return; - } - OffsetStr = OffsetStr.substr(1); - unsigned SubComponent = 0; - if (!OffsetStr.empty()) { - // Make sure SubComponent is a number. - if (OffsetStr.getAsInteger(10, SubComponent)) { - Diag(SubComponentLoc.getLocWithOffset(1), - diag::err_hlsl_unsupported_register_number); - SkipUntil(tok::r_paren, StopAtSemi); // skip through ) - return; - } - } - unsigned Component = 0; - ConsumeToken(); // consume identifier. - SourceLocation ComponentLoc; - if (Tok.is(tok::period)) { - ConsumeToken(); // consume period. - if (!Tok.is(tok::identifier)) { - Diag(Tok.getLocation(), diag::err_expected) << tok::identifier; - SkipUntil(tok::r_paren, StopAtSemi); // skip through ) - return; - } - StringRef ComponentStr = Tok.getIdentifierInfo()->getName(); - ComponentLoc = Tok.getLocation(); - ConsumeToken(); // consume identifier. - // Make sure Component is a single character. - if (ComponentStr.size() != 1) { - Diag(ComponentLoc, diag::err_hlsl_unsupported_component) - << ComponentStr; - SkipUntil(tok::r_paren, StopAtSemi); // skip through ) - return; - } - switch (ComponentStr[0]) { - case 'x': - case 'r': - Component = 0; - break; - case 'y': - case 'g': - Component = 1; - break; - case 'z': - case 'b': - Component = 2; - break; - case 'w': - case 'a': - Component = 3; - break; - default: - Diag(ComponentLoc, diag::err_hlsl_unsupported_component) - << ComponentStr; - SkipUntil(tok::r_paren, StopAtSemi); // skip through ) - return; - } - } - ASTContext &Ctx = Actions.getASTContext(); - QualType SizeTy = Ctx.getSizeType(); - uint64_t SizeTySize = Ctx.getTypeSize(SizeTy); - ArgExprs.push_back(IntegerLiteral::Create( - Ctx, llvm::APInt(SizeTySize, SubComponent), SizeTy, SubComponentLoc)); - ArgExprs.push_back(IntegerLiteral::Create( - Ctx, llvm::APInt(SizeTySize, Component), SizeTy, ComponentLoc)); - if (ExpectAndConsume(tok::r_paren, diag::err_expected)) { - SkipUntil(tok::r_paren, StopAtSemi); // skip through ) - return; - } - } break; case ParsedAttr::UnknownAttribute: Diag(Loc, diag::err_unknown_hlsl_semantic) << II; return; diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 6d957ac09e1c..6ca42856459f 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -7309,55 +7309,6 @@ static void handleHLSLSV_DispatchThreadIDAttr(Sema &S, Decl *D, D->addAttr(::new (S.Context) HLSLSV_DispatchThreadIDAttr(S.Context, AL)); } -static void handleHLSLPackOffsetAttr(Sema &S, Decl *D, const ParsedAttr &AL) { - if (!isa(D) || !isa(D->getDeclContext())) { - S.Diag(AL.getLoc(), diag::err_hlsl_attr_invalid_ast_node) - << AL << "shader constant in a constant buffer"; - return; - } - - uint32_t SubComponent; - if (!checkUInt32Argument(S, AL, AL.getArgAsExpr(0), SubComponent)) - return; - uint32_t Component; - if (!checkUInt32Argument(S, AL, AL.getArgAsExpr(1), Component)) - return; - - QualType T = cast(D)->getType().getCanonicalType(); - // Check if T is an array or struct type. - // TODO: mark matrix type as aggregate type. - bool IsAggregateTy = (T->isArrayType() || T->isStructureType()); - - // Check Component is valid for T. - if (Component) { - unsigned Size = S.getASTContext().getTypeSize(T); - if (IsAggregateTy || Size > 128) { - S.Diag(AL.getLoc(), diag::err_hlsl_packoffset_cross_reg_boundary); - return; - } else { - // Make sure Component + sizeof(T) <= 4. - if ((Component * 32 + Size) > 128) { - S.Diag(AL.getLoc(), diag::err_hlsl_packoffset_cross_reg_boundary); - return; - } - QualType EltTy = T; - if (const auto *VT = T->getAs()) - EltTy = VT->getElementType(); - unsigned Align = S.getASTContext().getTypeAlign(EltTy); - if (Align > 32 && Component == 1) { - // NOTE: Component 3 will hit err_hlsl_packoffset_cross_reg_boundary. - // So we only need to check Component 1 here. - S.Diag(AL.getLoc(), diag::err_hlsl_packoffset_alignment_mismatch) - << Align << EltTy; - return; - } - } - } - - D->addAttr(::new (S.Context) - HLSLPackOffsetAttr(S.Context, AL, SubComponent, Component)); -} - static void handleHLSLShaderAttr(Sema &S, Decl *D, const ParsedAttr &AL) { StringRef Str; SourceLocation ArgLoc; @@ -9779,9 +9730,6 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, case ParsedAttr::AT_HLSLSV_DispatchThreadID: handleHLSLSV_DispatchThreadIDAttr(S, D, AL); break; - case ParsedAttr::AT_HLSLPackOffset: - handleHLSLPackOffsetAttr(S, D, AL); - break; case ParsedAttr::AT_HLSLShader: handleHLSLShaderAttr(S, D, AL); break; diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp index 6a12c417e2f3..bb9e37f18d37 100644 --- a/clang/lib/Sema/SemaHLSL.cpp +++ b/clang/lib/Sema/SemaHLSL.cpp @@ -39,89 +39,9 @@ Decl *SemaHLSL::ActOnStartBuffer(Scope *BufferScope, bool CBuffer, return Result; } -// Calculate the size of a legacy cbuffer type based on -// https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-packing-rules -static unsigned calculateLegacyCbufferSize(const ASTContext &Context, - QualType T) { - unsigned Size = 0; - constexpr unsigned CBufferAlign = 128; - if (const RecordType *RT = T->getAs()) { - const RecordDecl *RD = RT->getDecl(); - for (const FieldDecl *Field : RD->fields()) { - QualType Ty = Field->getType(); - unsigned FieldSize = calculateLegacyCbufferSize(Context, Ty); - unsigned FieldAlign = 32; - if (Ty->isAggregateType()) - FieldAlign = CBufferAlign; - Size = llvm::alignTo(Size, FieldAlign); - Size += FieldSize; - } - } else if (const ConstantArrayType *AT = Context.getAsConstantArrayType(T)) { - if (unsigned ElementCount = AT->getSize().getZExtValue()) { - unsigned ElementSize = - calculateLegacyCbufferSize(Context, AT->getElementType()); - unsigned AlignedElementSize = llvm::alignTo(ElementSize, CBufferAlign); - Size = AlignedElementSize * (ElementCount - 1) + ElementSize; - } - } else if (const VectorType *VT = T->getAs()) { - unsigned ElementCount = VT->getNumElements(); - unsigned ElementSize = - calculateLegacyCbufferSize(Context, VT->getElementType()); - Size = ElementSize * ElementCount; - } else { - Size = Context.getTypeSize(T); - } - return Size; -} - void SemaHLSL::ActOnFinishBuffer(Decl *Dcl, SourceLocation RBrace) { auto *BufDecl = cast(Dcl); BufDecl->setRBraceLoc(RBrace); - - // Validate packoffset. - llvm::SmallVector> PackOffsetVec; - bool HasPackOffset = false; - bool HasNonPackOffset = false; - for (auto *Field : BufDecl->decls()) { - VarDecl *Var = dyn_cast(Field); - if (!Var) - continue; - if (Field->hasAttr()) { - PackOffsetVec.emplace_back(Var, Field->getAttr()); - HasPackOffset = true; - } else { - HasNonPackOffset = true; - } - } - - if (HasPackOffset && HasNonPackOffset) - Diag(BufDecl->getLocation(), diag::warn_hlsl_packoffset_mix); - - if (HasPackOffset) { - ASTContext &Context = getASTContext(); - // Make sure no overlap in packoffset. - // Sort PackOffsetVec by offset. - std::sort(PackOffsetVec.begin(), PackOffsetVec.end(), - [](const std::pair &LHS, - const std::pair &RHS) { - return LHS.second->getOffset() < RHS.second->getOffset(); - }); - - for (unsigned i = 0; i < PackOffsetVec.size() - 1; i++) { - VarDecl *Var = PackOffsetVec[i].first; - HLSLPackOffsetAttr *Attr = PackOffsetVec[i].second; - unsigned Size = calculateLegacyCbufferSize(Context, Var->getType()); - unsigned Begin = Attr->getOffset() * 32; - unsigned End = Begin + Size; - unsigned NextBegin = PackOffsetVec[i + 1].second->getOffset() * 32; - if (End > NextBegin) { - VarDecl *NextVar = PackOffsetVec[i + 1].first; - Diag(NextVar->getLocation(), diag::err_hlsl_packoffset_overlap) - << NextVar << Var; - } - } - } - SemaRef.PopDeclContext(); } diff --git a/clang/test/AST/HLSL/packoffset.hlsl b/clang/test/AST/HLSL/packoffset.hlsl deleted file mode 100644 index 9cfd88eeec33..000000000000 --- a/clang/test/AST/HLSL/packoffset.hlsl +++ /dev/null @@ -1,100 +0,0 @@ -// RUN: %clang_cc1 -triple dxil-unknown-shadermodel6.3-library -S -finclude-default-header -ast-dump -x hlsl %s | FileCheck %s - - -// CHECK: HLSLBufferDecl {{.*}} cbuffer A -cbuffer A -{ - // CHECK-NEXT: VarDecl {{.*}} A1 'float4' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 0 - float4 A1 : packoffset(c); - // CHECK-NEXT: VarDecl {{.*}} col:11 A2 'float' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 1 0 - float A2 : packoffset(c1); - // CHECK-NEXT: VarDecl {{.*}} col:11 A3 'float' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 1 1 - float A3 : packoffset(c1.y); -} - -// CHECK: HLSLBufferDecl {{.*}} cbuffer B -cbuffer B -{ - // CHECK: VarDecl {{.*}} B0 'float' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 1 - float B0 : packoffset(c0.g); - // CHECK-NEXT: VarDecl {{.*}} B1 'double' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 2 - double B1 : packoffset(c0.b); - // CHECK-NEXT: VarDecl {{.*}} B2 'half' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 0 - half B2 : packoffset(c0.r); -} - -// CHECK: HLSLBufferDecl {{.*}} cbuffer C -cbuffer C -{ - // CHECK: VarDecl {{.*}} C0 'float' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 1 - float C0 : packoffset(c0.y); - // CHECK-NEXT: VarDecl {{.*}} C1 'float2' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 2 - float2 C1 : packoffset(c0.z); - // CHECK-NEXT: VarDecl {{.*}} C2 'half' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 - half C2 : packoffset(c0.x); -} - - -// CHECK: HLSLBufferDecl {{.*}} cbuffer D -cbuffer D -{ - // CHECK: VarDecl {{.*}} D0 'float' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 1 - float D0 : packoffset(c0.y); - // CHECK-NEXT: VarDecl {{.*}} D1 'float[2]' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 1 0 - float D1[2] : packoffset(c1.x); - // CHECK-NEXT: VarDecl {{.*}} D2 'half3' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 2 1 - half3 D2 : packoffset(c2.y); - // CHECK-NEXT: VarDecl {{.*}} D3 'double' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 2 - double D3 : packoffset(c0.z); -} - -struct ST { - float a; - float2 b; - half c; -}; - -// CHECK: HLSLBufferDecl {{.*}} cbuffer S -cbuffer S { - // CHECK: VarDecl {{.*}} S0 'float' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 1 - float S0 : packoffset(c0.y); - // CHECK: VarDecl {{.*}} S1 'ST' - // CHECK: HLSLPackOffsetAttr {{.*}} 1 0 - ST S1 : packoffset(c1); - // CHECK: VarDecl {{.*}} S2 'double2' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 2 0 - double2 S2 : packoffset(c2); -} - -struct ST2 { - float s0; - ST s1; - half s2; -}; - -// CHECK: HLSLBufferDecl {{.*}} cbuffer S2 -cbuffer S2 { - // CHECK: VarDecl {{.*}} S20 'float' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 3 - float S20 : packoffset(c0.a); - // CHECK: VarDecl {{.*}} S21 'ST2' - // CHECK: HLSLPackOffsetAttr {{.*}} 1 0 - ST2 S21 : packoffset(c1); - // CHECK: VarDecl {{.*}} S22 'half' - // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 3 1 - half S22 : packoffset(c3.y); -} diff --git a/clang/test/SemaHLSL/packoffset-invalid.hlsl b/clang/test/SemaHLSL/packoffset-invalid.hlsl deleted file mode 100644 index c5983f6fd7e0..000000000000 --- a/clang/test/SemaHLSL/packoffset-invalid.hlsl +++ /dev/null @@ -1,122 +0,0 @@ -// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.3-library -verify %s - -// expected-warning@+1{{cannot mix packoffset elements with nonpackoffset elements in a cbuffer}} -cbuffer Mix -{ - float4 M1 : packoffset(c0); - float M2; - float M3 : packoffset(c1.y); -} - -// expected-warning@+1{{cannot mix packoffset elements with nonpackoffset elements in a cbuffer}} -cbuffer Mix2 -{ - float4 M4; - float M5 : packoffset(c1.y); - float M6 ; -} - -// expected-error@+1{{attribute 'packoffset' only applies to shader constant in a constant buffer}} -float4 g : packoffset(c0); - -cbuffer IllegalOffset -{ - // expected-error@+1{{invalid resource class specifier 't2' for packoffset, expected 'c'}} - float4 i1 : packoffset(t2); - // expected-error@+1{{invalid component 'm' used; expected 'x', 'y', 'z', or 'w'}} - float i2 : packoffset(c1.m); -} - -cbuffer Overlap -{ - float4 o1 : packoffset(c0); - // expected-error@+1{{packoffset overlap between 'o2', 'o1'}} - float2 o2 : packoffset(c0.z); -} - -cbuffer CrossReg -{ - // expected-error@+1{{packoffset cannot cross register boundary}} - float4 c1 : packoffset(c0.y); - // expected-error@+1{{packoffset cannot cross register boundary}} - float2 c2 : packoffset(c1.w); -} - -struct ST { - float s; -}; - -cbuffer Aggregate -{ - // expected-error@+1{{packoffset cannot cross register boundary}} - ST A1 : packoffset(c0.y); - // expected-error@+1{{packoffset cannot cross register boundary}} - float A2[2] : packoffset(c1.w); -} - -cbuffer Double { - // expected-error@+1{{packoffset at 'y' not match alignment 64 required by 'double'}} - double d : packoffset(c.y); - // expected-error@+1{{packoffset cannot cross register boundary}} - double2 d2 : packoffset(c.z); - // expected-error@+1{{packoffset cannot cross register boundary}} - double3 d3 : packoffset(c.z); -} - -cbuffer ParsingFail { -// expected-error@+1{{expected identifier}} -float pf0 : packoffset(); -// expected-error@+1{{expected identifier}} -float pf1 : packoffset((c0)); -// expected-error@+1{{expected ')'}} -float pf2 : packoffset(c0, x); -// expected-error@+1{{invalid component 'X' used}} -float pf3 : packoffset(c.X); -// expected-error@+1{{expected '(' after ''}} -float pf4 : packoffset; -// expected-error@+1{{expected identifier}} -float pf5 : packoffset(; -// expected-error@+1{{expected '(' after '}} -float pf6 : packoffset); -// expected-error@+1{{expected '(' after '}} -float pf7 : packoffset c0.x; - -// expected-error@+1{{invalid component 'xy' used}} -float pf8 : packoffset(c0.xy); -// expected-error@+1{{invalid component 'rg' used}} -float pf9 : packoffset(c0.rg); -// expected-error@+1{{invalid component 'yes' used}} -float pf10 : packoffset(c0.yes); -// expected-error@+1{{invalid component 'woo'}} -float pf11 : packoffset(c0.woo); -// expected-error@+1{{invalid component 'xr' used}} -float pf12 : packoffset(c0.xr); -} - -struct ST2 { - float a; - float2 b; -}; - -cbuffer S { - float S0 : packoffset(c0.y); - ST2 S1[2] : packoffset(c1); - // expected-error@+1{{packoffset overlap between 'S2', 'S1'}} - half2 S2 : packoffset(c1.w); - half2 S3 : packoffset(c2.w); -} - -struct ST23 { - float s0; - ST2 s1; -}; - -cbuffer S2 { - float S20 : packoffset(c0.y); - ST2 S21 : packoffset(c1); - half2 S22 : packoffset(c2.w); - double S23[2] : packoffset(c3); - // expected-error@+1{{packoffset overlap between 'S24', 'S23'}} - float S24 : packoffset(c3.z); - float S25 : packoffset(c4.z); -} -- GitLab From c6efcc925c9969d616bc463171c0423d6a9766af Mon Sep 17 00:00:00 2001 From: Christian Ulmann Date: Wed, 8 May 2024 15:53:14 +0200 Subject: [PATCH 028/328] [MLIR][Mem2Reg] Improve performance by avoiding recomputations (#91444) This commit ensures that Mem2Reg reuses the `DominanceInfo` as well as block index maps to avoid expensive recomputations. Due to the recent migration to `OpBuilder`, the promotion of a slot does no longer replace blocks. Having stable blocks makes the `DominanceInfo` preservable and additionally allows to cache block index maps between different promotions. Performance measurements on very large functions show an up to 4x speedup by these changes. --- mlir/include/mlir/Transforms/Mem2Reg.h | 1 + mlir/lib/Transforms/Mem2Reg.cpp | 65 ++++++++++++++++++-------- 2 files changed, 47 insertions(+), 19 deletions(-) diff --git a/mlir/include/mlir/Transforms/Mem2Reg.h b/mlir/include/mlir/Transforms/Mem2Reg.h index b4f939d65414..fee7fb312750 100644 --- a/mlir/include/mlir/Transforms/Mem2Reg.h +++ b/mlir/include/mlir/Transforms/Mem2Reg.h @@ -28,6 +28,7 @@ struct Mem2RegStatistics { LogicalResult tryToPromoteMemorySlots(ArrayRef allocators, OpBuilder &builder, const DataLayout &dataLayout, + DominanceInfo &dominance, Mem2RegStatistics statistics = {}); } // namespace mlir diff --git a/mlir/lib/Transforms/Mem2Reg.cpp b/mlir/lib/Transforms/Mem2Reg.cpp index 1d7ba4ca4f83..8adbbcd01cb4 100644 --- a/mlir/lib/Transforms/Mem2Reg.cpp +++ b/mlir/lib/Transforms/Mem2Reg.cpp @@ -18,7 +18,6 @@ #include "mlir/Transforms/Passes.h" #include "mlir/Transforms/RegionUtils.h" #include "llvm/ADT/STLExtras.h" -#include "llvm/Support/Casting.h" #include "llvm/Support/GenericIteratedDominanceFrontier.h" namespace mlir { @@ -158,6 +157,8 @@ private: const DataLayout &dataLayout; }; +using BlockIndexCache = DenseMap>; + /// The MemorySlotPromoter handles the state of promoting a memory slot. It /// wraps a slot and its associated allocator. This will perform the mutation of /// IR. @@ -166,7 +167,8 @@ public: MemorySlotPromoter(MemorySlot slot, PromotableAllocationOpInterface allocator, OpBuilder &builder, DominanceInfo &dominance, const DataLayout &dataLayout, MemorySlotPromotionInfo info, - const Mem2RegStatistics &statistics); + const Mem2RegStatistics &statistics, + BlockIndexCache &blockIndexCache); /// Actually promotes the slot by mutating IR. Promoting a slot DOES /// invalidate the MemorySlotPromotionInfo of other slots. Preparation of @@ -207,6 +209,9 @@ private: const DataLayout &dataLayout; MemorySlotPromotionInfo info; const Mem2RegStatistics &statistics; + + /// Shared cache of block indices of specific regions. + BlockIndexCache &blockIndexCache; }; } // namespace @@ -214,9 +219,11 @@ private: MemorySlotPromoter::MemorySlotPromoter( MemorySlot slot, PromotableAllocationOpInterface allocator, OpBuilder &builder, DominanceInfo &dominance, const DataLayout &dataLayout, - MemorySlotPromotionInfo info, const Mem2RegStatistics &statistics) + MemorySlotPromotionInfo info, const Mem2RegStatistics &statistics, + BlockIndexCache &blockIndexCache) : slot(slot), allocator(allocator), builder(builder), dominance(dominance), - dataLayout(dataLayout), info(std::move(info)), statistics(statistics) { + dataLayout(dataLayout), info(std::move(info)), statistics(statistics), + blockIndexCache(blockIndexCache) { #ifndef NDEBUG auto isResultOrNewBlockArgument = [&]() { if (BlockArgument arg = dyn_cast(slot.ptr)) @@ -500,15 +507,29 @@ void MemorySlotPromoter::computeReachingDefInRegion(Region *region, } } +/// Gets or creates a block index mapping for `region`. +static const DenseMap & +getOrCreateBlockIndices(BlockIndexCache &blockIndexCache, Region *region) { + auto [it, inserted] = blockIndexCache.try_emplace(region); + if (!inserted) + return it->second; + + DenseMap &blockIndices = it->second; + SetVector topologicalOrder = getTopologicallySortedBlocks(*region); + for (auto [index, block] : llvm::enumerate(topologicalOrder)) + blockIndices[block] = index; + return blockIndices; +} + /// Sorts `ops` according to dominance. Relies on the topological order of basic -/// blocks to get a deterministic ordering. -static void dominanceSort(SmallVector &ops, Region ®ion) { +/// blocks to get a deterministic ordering. Uses `blockIndexCache` to avoid the +/// potentially expensive recomputation of a block index map. +static void dominanceSort(SmallVector &ops, Region ®ion, + BlockIndexCache &blockIndexCache) { // Produce a topological block order and construct a map to lookup the indices // of blocks. - DenseMap topoBlockIndices; - SetVector topologicalOrder = getTopologicallySortedBlocks(region); - for (auto [index, block] : llvm::enumerate(topologicalOrder)) - topoBlockIndices[block] = index; + const DenseMap &topoBlockIndices = + getOrCreateBlockIndices(blockIndexCache, ®ion); // Combining the topological order of the basic blocks together with block // internal operation order guarantees a deterministic, dominance respecting @@ -527,7 +548,8 @@ void MemorySlotPromoter::removeBlockingUses() { llvm::make_first_range(info.userToBlockingUses)); // Sort according to dominance. - dominanceSort(usersToRemoveUses, *slot.ptr.getParentBlock()->getParent()); + dominanceSort(usersToRemoveUses, *slot.ptr.getParentBlock()->getParent(), + blockIndexCache); llvm::SmallVector toErase; // List of all replaced values in the slot. @@ -605,20 +627,25 @@ void MemorySlotPromoter::promoteSlot() { LogicalResult mlir::tryToPromoteMemorySlots( ArrayRef allocators, OpBuilder &builder, - const DataLayout &dataLayout, Mem2RegStatistics statistics) { + const DataLayout &dataLayout, DominanceInfo &dominance, + Mem2RegStatistics statistics) { bool promotedAny = false; + // A cache that stores deterministic block indices which are used to determine + // a valid operation modification order. The block index maps are computed + // lazily and cached to avoid expensive recomputation. + BlockIndexCache blockIndexCache; + for (PromotableAllocationOpInterface allocator : allocators) { for (MemorySlot slot : allocator.getPromotableSlots()) { if (slot.ptr.use_empty()) continue; - DominanceInfo dominance; MemorySlotPromotionAnalyzer analyzer(slot, dominance, dataLayout); std::optional info = analyzer.computeInfo(); if (info) { MemorySlotPromoter(slot, allocator, builder, dominance, dataLayout, - std::move(*info), statistics) + std::move(*info), statistics, blockIndexCache) .promoteSlot(); promotedAny = true; } @@ -640,6 +667,10 @@ struct Mem2Reg : impl::Mem2RegBase { bool changed = false; + auto &dataLayoutAnalysis = getAnalysis(); + const DataLayout &dataLayout = dataLayoutAnalysis.getAtOrAbove(scopeOp); + auto &dominance = getAnalysis(); + for (Region ®ion : scopeOp->getRegions()) { if (region.getBlocks().empty()) continue; @@ -655,16 +686,12 @@ struct Mem2Reg : impl::Mem2RegBase { allocators.emplace_back(allocator); }); - auto &dataLayoutAnalysis = getAnalysis(); - const DataLayout &dataLayout = dataLayoutAnalysis.getAtOrAbove(scopeOp); - // Attempt promoting until no promotion succeeds. if (failed(tryToPromoteMemorySlots(allocators, builder, dataLayout, - statistics))) + dominance, statistics))) break; changed = true; - getAnalysisManager().invalidate({}); } } if (!changed) -- GitLab From 2c1c67674cb3beb4e091a9f446de5858631cf8ae Mon Sep 17 00:00:00 2001 From: srcarroll <50210727+srcarroll@users.noreply.github.com> Date: Wed, 8 May 2024 09:11:53 -0500 Subject: [PATCH 029/328] [mlir][transform] Consistent `linalg` `transform` op syntax for dynamic index lists (#90897) This patch is a first pass at making consistent syntax across the `LinalgTransformOp`s that use dynamic index lists for size parameters. Previously, there were two different forms: inline types in the list, or place them in the functional style tuple. This patch goes for the latter. In order to do this, the `printPackedOrDynamicIndexList`, `printDynamicIndexList` and their `parse` counterparts were modified so that the types can be optionally provided to the corresponding custom directives. All affected ops now use tablegen `assemblyFormat`, so custom `parse`/`print` functions have been removed. There are a couple ops that will likely add dynamic size support, and once that happens it should be made sure that the assembly remains consistent with the changes in this patch. The affected ops are as follows: `pack`, `pack_greedily`, `tile_using_forall`. The `tile_using_for` and `vectorize` ops already used this syntax, but their custom assembly was removed. --------- Co-authored-by: Oleksandr "Alex" Zinenko --- .../Linalg/TransformOps/LinalgTransformOps.td | 41 +++-- .../mlir/Dialect/Transform/Utils/Utils.h | 16 +- .../mlir/Interfaces/ViewLikeInterface.h | 11 +- .../TransformOps/LinalgTransformOps.cpp | 154 ------------------ mlir/lib/Dialect/Transform/Utils/Utils.cpp | 19 ++- mlir/lib/Interfaces/ViewLikeInterface.cpp | 2 +- mlir/test/Dialect/LLVM/transform-e2e.mlir | 2 +- .../Linalg/generalize-tensor-pack-tile.mlir | 6 +- .../Linalg/generalize-tensor-unpack-tile.mlir | 6 +- .../Linalg/matmul-shared-memory-padding.mlir | 4 +- .../Dialect/Linalg/multisize-tiling-full.mlir | 16 +- mlir/test/Dialect/Linalg/promote.mlir | 4 +- .../Dialect/Linalg/promotion_options.mlir | 2 +- mlir/test/Dialect/Linalg/tile-conv.mlir | 2 +- mlir/test/Dialect/Linalg/tile-indexed.mlir | 4 +- mlir/test/Dialect/Linalg/tile-softmax.mlir | 4 +- mlir/test/Dialect/Linalg/tile-tensors.mlir | 8 +- mlir/test/Dialect/Linalg/tile-to-forall.mlir | 24 +-- ...compose-masked-vectorize-and-cleanups.mlir | 4 +- .../Dialect/Linalg/transform-op-fuse.mlir | 2 +- ...-op-hoist-pad-build-packing-loop-nest.mlir | 10 +- .../Linalg/transform-op-hoist-pad.mlir | 10 +- .../Linalg/transform-op-mmt4d-to-fma.mlir | 4 +- .../Dialect/Linalg/transform-op-pack.mlir | 4 +- .../transform-op-peel-and-vectorize-conv.mlir | 4 +- .../transform-op-peel-and-vectorize.mlir | 2 +- .../Linalg/transform-op-scalarize.mlir | 2 +- .../Dialect/Linalg/transform-op-tile.mlir | 14 +- .../Dialect/Linalg/transform-ops-invalid.mlir | 2 +- mlir/test/Dialect/Linalg/transform-ops.mlir | 6 +- .../Dialect/Linalg/transform-patterns.mlir | 20 +-- .../vectorize-tensor-extract-masked.mlir | 12 +- mlir/test/Dialect/Tensor/tiling.mlir | 34 ++-- mlir/test/Dialect/Transform/ops.mlir | 8 +- .../Transform/selective-targeting.mlir | 2 +- .../test/Dialect/Vector/transform-vector.mlir | 2 +- .../Linalg/CPU/ArmSME/matmul-transpose-a.mlir | 2 +- .../Dialect/Linalg/CPU/ArmSME/matmul.mlir | 2 +- .../ArmSME/multi-tile-matmul-mixed-types.mlir | 2 +- .../Linalg/CPU/ArmSME/multi-tile-matmul.mlir | 2 +- .../Dialect/Linalg/CPU/ArmSVE/matmul.mlir | 2 +- .../Integration/Dialect/Linalg/CPU/mmt4d.mlir | 4 +- .../Dialect/Linalg/CPU/pack-unpack-mmt4d.mlir | 4 +- .../Dialect/Linalg/CPU/test-conv-1d-call.mlir | 2 +- .../Linalg/CPU/test-conv-1d-nwc-wcf-call.mlir | 2 +- .../Dialect/Linalg/CPU/test-conv-2d-call.mlir | 2 +- .../CPU/test-conv-2d-nhwc-hwcf-call.mlir | 2 +- .../Dialect/Linalg/CPU/test-conv-3d-call.mlir | 2 +- .../CPU/test-conv-3d-ndhwc-dhwcf-call.mlir | 2 +- .../Linalg/CPU/test-tensor-matmul.mlir | 2 +- .../tile-pad-using-interface.mlir | 12 +- .../TilingInterface/tile-using-interface.mlir | 18 +- .../dialects/transform_structured_ext.py | 4 +- 53 files changed, 210 insertions(+), 323 deletions(-) diff --git a/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td b/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td index 55d82fd5825b..5585ba27fdad 100644 --- a/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td +++ b/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td @@ -783,10 +783,9 @@ def PackOp : Op($packed_sizes, - $static_packed_sizes, - type($packed_sizes)) + $static_packed_sizes) attr-dict - `:` functional-type($target, results) + `:` functional-type(operands, results) }]; let builders = [ @@ -890,14 +889,13 @@ def PackGreedilyOp : Op($matmul_packed_sizes, - $static_matmul_packed_sizes, - type($matmul_packed_sizes)) + $static_matmul_packed_sizes) (`matmul_padded_sizes_next_multiple_of` `=` $matmul_padded_sizes_next_multiple_of^)? `matmul_inner_dims_order` `=` $matmul_inner_dims_order ) attr-dict - `:` functional-type($target, results) + `:` functional-type(operands, results) }]; let hasVerifier = 1; @@ -1899,7 +1897,17 @@ def TileUsingForOp : Op, ]; - let hasCustomAssemblyFormat = 1; + let assemblyFormat = [{ + $target + `tile_sizes` custom( + $dynamic_sizes, + $static_sizes, + $scalable_sizes) + (`interchange` `=` $interchange^)? + attr-dict + `:` functional-type(operands, results) + }]; + let hasVerifier = 1; let extraClassDeclaration = [{ @@ -2017,17 +2025,13 @@ def TileUsingForallOp : let assemblyFormat = [{ $target oilist( `num_threads` custom($packed_num_threads, - type($packed_num_threads), $num_threads, - type($num_threads), $static_num_threads) | `tile_sizes` custom($packed_tile_sizes, - type($packed_tile_sizes), $tile_sizes, - type($tile_sizes), $static_tile_sizes)) (`(` `mapping` `=` $mapping^ `)`)? attr-dict - `:` functional-type($target, results) + `:` functional-type(operands, results) }]; let hasVerifier = 1; @@ -2162,7 +2166,18 @@ def VectorizeOp : Op( + $vector_sizes, + $static_vector_sizes, + $scalable_sizes)) + attr-dict + `:` type($target)(`,`type($vector_sizes)^)? + }]; + let hasVerifier = 1; let extraClassDeclaration = [{ diff --git a/mlir/include/mlir/Dialect/Transform/Utils/Utils.h b/mlir/include/mlir/Dialect/Transform/Utils/Utils.h index 868054e5e2ae..be31f5beea8c 100644 --- a/mlir/include/mlir/Dialect/Transform/Utils/Utils.h +++ b/mlir/include/mlir/Dialect/Transform/Utils/Utils.h @@ -37,6 +37,12 @@ void printPackedOrDynamicIndexList(OpAsmPrinter &printer, Operation *op, Value packed, Type packedType, OperandRange values, TypeRange valueTypes, DenseI64ArrayAttr integers); +inline void printPackedOrDynamicIndexList(OpAsmPrinter &printer, Operation *op, + Value packed, OperandRange values, + DenseI64ArrayAttr integers) { + printPackedOrDynamicIndexList(printer, op, packed, Type(), values, + TypeRange{}, integers); +} /// Parser hook for custom directive in assemblyFormat. /// @@ -47,7 +53,15 @@ void printPackedOrDynamicIndexList(OpAsmPrinter &printer, Operation *op, ParseResult parsePackedOrDynamicIndexList( OpAsmParser &parser, std::optional &packed, Type &packedType, SmallVectorImpl &values, - SmallVectorImpl &valueTypes, DenseI64ArrayAttr &integers); + SmallVectorImpl *valueTypes, DenseI64ArrayAttr &integers); +inline ParseResult parsePackedOrDynamicIndexList( + OpAsmParser &parser, std::optional &packed, + SmallVectorImpl &values, + DenseI64ArrayAttr &integers) { + Type packedType; + return parsePackedOrDynamicIndexList(parser, packed, packedType, values, + nullptr, integers); +} } // namespace transform } // namespace mlir diff --git a/mlir/include/mlir/Interfaces/ViewLikeInterface.h b/mlir/include/mlir/Interfaces/ViewLikeInterface.h index 931309b0c596..d6479143a0a5 100644 --- a/mlir/include/mlir/Interfaces/ViewLikeInterface.h +++ b/mlir/include/mlir/Interfaces/ViewLikeInterface.h @@ -106,9 +106,16 @@ public: /// empty then assume that all indices are non-scalable. void printDynamicIndexList( OpAsmPrinter &printer, Operation *op, OperandRange values, - ArrayRef integers, TypeRange valueTypes = TypeRange(), - ArrayRef scalables = {}, + ArrayRef integers, ArrayRef scalables, + TypeRange valueTypes = TypeRange(), AsmParser::Delimiter delimiter = AsmParser::Delimiter::Square); +inline void printDynamicIndexList( + OpAsmPrinter &printer, Operation *op, OperandRange values, + ArrayRef integers, TypeRange valueTypes = TypeRange(), + AsmParser::Delimiter delimiter = AsmParser::Delimiter::Square) { + return printDynamicIndexList(printer, op, values, integers, {}, valueTypes, + delimiter); +} /// Parser hook for custom directive in assemblyFormat. /// diff --git a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp index ae04281032d7..13582a140a96 100644 --- a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp +++ b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp @@ -2823,86 +2823,6 @@ SmallVector transform::TileUsingForOp::getMixedSizes() { return results; } -// We want to parse `DenseI64ArrayAttr` using the short form without the -// `array` prefix to be consistent in the IR with `parseDynamicIndexList`. -ParseResult parseOptionalInterchange(OpAsmParser &parser, - OperationState &result) { - if (failed(parser.parseOptionalKeyword("interchange"))) - return success(); - if (failed(parser.parseEqual())) - return failure(); - result.addAttribute( - transform::TileUsingForOp::getInterchangeAttrName(result.name), - DenseI64ArrayAttr::parse(parser, Type{})); - return success(); -} - -void printOptionalInterchange(OpAsmPrinter &p, - ArrayRef interchangeVals) { - if (!interchangeVals.empty()) { - p << " interchange = ["; - llvm::interleaveComma(interchangeVals, p, - [&](int64_t integer) { p << integer; }); - p << "]"; - } -} - -ParseResult transform::TileUsingForOp::parse(OpAsmParser &parser, - OperationState &result) { - OpAsmParser::UnresolvedOperand target; - SmallVector dynamicSizes; - DenseI64ArrayAttr staticSizes; - FunctionType functionalType; - llvm::SMLoc operandLoc; - DenseBoolArrayAttr scalableVals; - - if (parser.parseOperand(target) || parser.getCurrentLocation(&operandLoc) || - parseDynamicIndexList(parser, dynamicSizes, staticSizes, scalableVals) || - parseOptionalInterchange(parser, result) || - parser.parseOptionalAttrDict(result.attributes) || - parser.parseColonType(functionalType)) - return ParseResult::failure(); - - size_t numExpectedLoops = - staticSizes.size() - llvm::count(staticSizes.asArrayRef(), 0); - if (functionalType.getNumResults() != numExpectedLoops + 1) { - return parser.emitError(parser.getNameLoc()) - << "expected " << (numExpectedLoops + 1) << " result type(s)"; - } - if (functionalType.getNumInputs() != dynamicSizes.size() + 1) { - return parser.emitError(operandLoc) - << "expected " << dynamicSizes.size() + 1 << " operand type(s)"; - } - if (parser.resolveOperand(target, functionalType.getInputs().front(), - result.operands) || - parser.resolveOperands(dynamicSizes, - functionalType.getInputs().drop_front(), - operandLoc, result.operands)) { - return failure(); - } - - result.addAttribute(getScalableSizesAttrName(result.name), scalableVals); - - result.addAttribute(getStaticSizesAttrName(result.name), staticSizes); - result.addTypes(functionalType.getResults()); - return success(); -} - -void TileUsingForOp::print(OpAsmPrinter &p) { - p << ' ' << getTarget(); - printDynamicIndexList(p, getOperation(), getDynamicSizes(), getStaticSizes(), - /*valueTypes=*/{}, getScalableSizesAttr(), - OpAsmParser::Delimiter::Square); - printOptionalInterchange(p, getInterchange()); - p.printOptionalAttrDict( - (*this)->getAttrs(), - /*elidedAttrs=*/{getInterchangeAttrName(getOperation()->getName()), - getScalableSizesAttrName(getOperation()->getName()), - getStaticSizesAttrName(getOperation()->getName())}); - p << " : "; - p.printFunctionalType(getOperands().getTypes(), getResults().getTypes()); -} - void transform::TileUsingForOp::getEffects( SmallVectorImpl &effects) { consumesHandle(getTarget(), effects); @@ -3219,80 +3139,6 @@ transform::VectorizeChildrenAndApplyPatternsOp::applyToOne( // VectorizeOp //===----------------------------------------------------------------------===// -static const StringLiteral kVectorSizesKeyword = "vector_sizes"; - -ParseResult transform::VectorizeOp::parse(OpAsmParser &parser, - OperationState &result) { - OpAsmParser::UnresolvedOperand target; - SmallVector dynamicSizes; - DenseI64ArrayAttr staticSizes; - SmallVector operandTypes; - llvm::SMLoc operandLoc; - DenseBoolArrayAttr scalableVals; - - if (parser.parseOperand(target) || parser.getCurrentLocation(&operandLoc)) - return ParseResult::failure(); - - if (succeeded(parser.parseOptionalKeyword(kVectorSizesKeyword))) { - if (failed(parseDynamicIndexList(parser, dynamicSizes, staticSizes, - scalableVals))) - return ParseResult::failure(); - } - - if (succeeded(parser.parseOptionalKeyword( - getVectorizeNdExtractAttrName(result.name)))) - result.addAttribute(getVectorizeNdExtractAttrName(result.name), - parser.getBuilder().getUnitAttr()); - - if (parser.parseOptionalAttrDict(result.attributes) || - parser.parseColonTypeList(operandTypes)) - return ParseResult::failure(); - - if (operandTypes.size() != dynamicSizes.size() + 1) { - return parser.emitError(operandLoc) - << "expected " << dynamicSizes.size() + 1 << " operand type(s)"; - } - if (parser.resolveOperand(target, operandTypes.front(), result.operands) || - parser.resolveOperands(dynamicSizes, ArrayRef(operandTypes).drop_front(), - operandLoc, result.operands)) { - return failure(); - } - - if (scalableVals) - result.addAttribute(getScalableSizesAttrName(result.name), scalableVals); - if (staticSizes) - result.addAttribute(getStaticVectorSizesAttrName(result.name), staticSizes); - - return success(); -} - -void transform::VectorizeOp::print(OpAsmPrinter &p) { - p << ' ' << getTarget() << ' '; - if (!getMixedVectorSizes().empty()) { - p << kVectorSizesKeyword << ' '; - printDynamicIndexList(p, getOperation(), getVectorSizes(), - getStaticVectorSizesAttr(), - /*valueTypes=*/{}, getScalableSizesAttr(), - OpAsmParser::Delimiter::Square); - } - - if (getVectorizeNdExtract()) - p << getVectorizeNdExtractAttrName() << ' '; - - p.printOptionalAttrDict( - (*this)->getAttrs(), - /*elidedAttrs=*/{ - getScalableSizesAttrName(getOperation()->getName()), - getStaticVectorSizesAttrName(getOperation()->getName())}); - p << " : "; - p << getTarget().getType(); - if (!getVectorSizes().empty()) { - p << ", "; - llvm::interleaveComma(getVectorSizes(), p, - [&](Value operand) { p << operand.getType(); }); - } -} - DiagnosedSilenceableFailure transform::VectorizeOp::apply( transform::TransformRewriter &rewriter, mlir::transform::TransformResults &transformResults, diff --git a/mlir/lib/Dialect/Transform/Utils/Utils.cpp b/mlir/lib/Dialect/Transform/Utils/Utils.cpp index 08068d285b4c..2ce21fe8a9c1 100644 --- a/mlir/lib/Dialect/Transform/Utils/Utils.cpp +++ b/mlir/lib/Dialect/Transform/Utils/Utils.cpp @@ -20,7 +20,11 @@ void mlir::transform::printPackedOrDynamicIndexList( if (packed) { assert(values.empty() && (!integers || integers.empty()) && "expected no values/integers"); - printer << "*(" << packed << " : " << packedType << ")"; + printer << "*(" << packed; + if (packedType) { + printer << " : " << packedType; + } + printer << ")"; return; } printDynamicIndexList(printer, op, values, integers, valueTypes); @@ -29,19 +33,20 @@ void mlir::transform::printPackedOrDynamicIndexList( ParseResult mlir::transform::parsePackedOrDynamicIndexList( OpAsmParser &parser, std::optional &packed, Type &packedType, SmallVectorImpl &values, - SmallVectorImpl &valueTypes, DenseI64ArrayAttr &integers) { + SmallVectorImpl *valueTypes, DenseI64ArrayAttr &integers) { OpAsmParser::UnresolvedOperand packedOperand; if (parser.parseOptionalStar().succeeded()) { if (parser.parseLParen().failed() || - parser.parseOperand(packedOperand).failed() || - parser.parseColonType(packedType).failed() || - parser.parseRParen().failed()) { + parser.parseOperand(packedOperand).failed()) + return failure(); + if (packedType && (parser.parseColonType(packedType).failed())) + return failure(); + if (parser.parseRParen().failed()) return failure(); - } packed.emplace(packedOperand); integers = parser.getBuilder().getDenseI64ArrayAttr({}); return success(); } - return parseDynamicIndexList(parser, values, integers, &valueTypes); + return parseDynamicIndexList(parser, values, integers, valueTypes); } diff --git a/mlir/lib/Interfaces/ViewLikeInterface.cpp b/mlir/lib/Interfaces/ViewLikeInterface.cpp index 6d1ff03756ac..ca33636336bf 100644 --- a/mlir/lib/Interfaces/ViewLikeInterface.cpp +++ b/mlir/lib/Interfaces/ViewLikeInterface.cpp @@ -113,7 +113,7 @@ static char getRightDelimiter(AsmParser::Delimiter delimiter) { void mlir::printDynamicIndexList(OpAsmPrinter &printer, Operation *op, OperandRange values, ArrayRef integers, - TypeRange valueTypes, ArrayRef scalables, + ArrayRef scalables, TypeRange valueTypes, AsmParser::Delimiter delimiter) { char leftDelimiter = getLeftDelimiter(delimiter); char rightDelimiter = getRightDelimiter(delimiter); diff --git a/mlir/test/Dialect/LLVM/transform-e2e.mlir b/mlir/test/Dialect/LLVM/transform-e2e.mlir index adbbbba32a40..c00b47fb936e 100644 --- a/mlir/test/Dialect/LLVM/transform-e2e.mlir +++ b/mlir/test/Dialect/LLVM/transform-e2e.mlir @@ -15,7 +15,7 @@ func.func @matmul_tensors( module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%module_op: !transform.any_op {transform.consumed}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %module_op : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [2, 2, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [2, 2, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) %2 = transform.get_parent_op %1 {isolated_from_above} : (!transform.any_op) -> !transform.any_op transform.structured.vectorize_children_and_apply_patterns %2 : (!transform.any_op) -> !transform.any_op %b = transform.bufferization.one_shot_bufferize layout{IdentityLayoutMap} diff --git a/mlir/test/Dialect/Linalg/generalize-tensor-pack-tile.mlir b/mlir/test/Dialect/Linalg/generalize-tensor-pack-tile.mlir index 0a197a0ee9fa..d0c53ae46800 100644 --- a/mlir/test/Dialect/Linalg/generalize-tensor-pack-tile.mlir +++ b/mlir/test/Dialect/Linalg/generalize-tensor-pack-tile.mlir @@ -27,7 +27,7 @@ func.func @KCRS_to_KCRSsr(%arg0: tensor<1x1x128x64xf32>, %arg1: tensor<1x1x4x8x8 module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:4 = transform.structured.tile_using_for %0 [1, 1, 1, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:4 = transform.structured.tile_using_for %0 tile_sizes [1, 1, 1, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -54,7 +54,7 @@ func.func @pad_and_pack(%arg0: tensor<13x15xf32>, %arg1: tensor<2x8x8x2xf32>, %a module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [1, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [1, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -85,7 +85,7 @@ func.func @KC_to_CKkc(%arg0: tensor<128x256xf32>, %arg1: tensor<32x4x32x8xf32>) module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [1, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [1, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Dialect/Linalg/generalize-tensor-unpack-tile.mlir b/mlir/test/Dialect/Linalg/generalize-tensor-unpack-tile.mlir index 7d64331c9878..c15859d898ec 100644 --- a/mlir/test/Dialect/Linalg/generalize-tensor-unpack-tile.mlir +++ b/mlir/test/Dialect/Linalg/generalize-tensor-unpack-tile.mlir @@ -8,7 +8,7 @@ func.func @KCRSsr_to_KCRS(%arg0: tensor<1x1x4x8x8x32xf32>, %arg1: tensor<1x1x128 module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.unpack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:4 = transform.structured.tile_using_for %0 [1, 1, 32, 8] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:4 = transform.structured.tile_using_for %0 tile_sizes [1, 1, 32, 8] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -68,7 +68,7 @@ func.func @unpack_and_extract_slice(%arg0: tensor<2x8x8x2xf32>, %arg1: tensor<13 module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.unpack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [8, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [8, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -100,7 +100,7 @@ func.func @CKkc_to_KC(%arg0: tensor<32x4x32x8xf32>, %arg1: tensor<128x256xf32>) module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.unpack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [32, 8] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [32, 8] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Dialect/Linalg/matmul-shared-memory-padding.mlir b/mlir/test/Dialect/Linalg/matmul-shared-memory-padding.mlir index c3ac69f65b7c..3f8d2ea06641 100644 --- a/mlir/test/Dialect/Linalg/matmul-shared-memory-padding.mlir +++ b/mlir/test/Dialect/Linalg/matmul-shared-memory-padding.mlir @@ -52,7 +52,7 @@ module attributes {transform.with_named_sequence} { : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) // Tile linalg.matmul a second time. - %tiled_linalg_op, %loops = transform.structured.tile_using_for %tiled_matmul_op[0, 0, 16] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %tiled_linalg_op, %loops = transform.structured.tile_using_for %tiled_matmul_op tile_sizes [0, 0, 16] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) // Pad linalg.matmul. %padded, %pad, %copy_back = transform.structured.pad %tiled_linalg_op @@ -171,7 +171,7 @@ module attributes {transform.with_named_sequence} { : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) // Tile linalg.matmul a second time. - %tiled_linalg_op, %loops = transform.structured.tile_using_for %tiled_matmul_op[0, 0, 16] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %tiled_linalg_op, %loops = transform.structured.tile_using_for %tiled_matmul_op tile_sizes [0, 0, 16] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) // Pad linalg.matmul. %padded, %pad, %copy_back = transform.structured.pad %tiled_linalg_op diff --git a/mlir/test/Dialect/Linalg/multisize-tiling-full.mlir b/mlir/test/Dialect/Linalg/multisize-tiling-full.mlir index 592eb781cd4f..15b24b56608e 100644 --- a/mlir/test/Dialect/Linalg/multisize-tiling-full.mlir +++ b/mlir/test/Dialect/Linalg/multisize-tiling-full.mlir @@ -8,13 +8,13 @@ module attributes {transform.with_named_sequence} { %1:3 = transform.structured.multitile_sizes %0 { dimension = 0, target_size = 3} : (!transform.any_op) -> !transform.any_op %t:3 = transform.structured.multitile_sizes %0 { dimension = 1, target_size = 10} : (!transform.any_op) -> !transform.any_op %2:2 = transform.structured.split %0 after %1#2 { dimension = 0 } : !transform.any_op, !transform.any_op - %3:2 = transform.structured.tile_using_for %2#0 [%1#0] : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) - %4:2 = transform.structured.tile_using_for %2#1 [%1#1] : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) + %3:2 = transform.structured.tile_using_for %2#0 tile_sizes [%1#0] : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) + %4:2 = transform.structured.tile_using_for %2#1 tile_sizes [%1#1] : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) %5 = transform.merge_handles %3#0, %4#0 : !transform.any_op %tt:3 = transform.replicate num(%5) %t#0, %t#1, %t#2 : !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op %6:2 = transform.structured.split %5 after %tt#2 { dimension = 1 } : !transform.any_op, !transform.any_op - transform.structured.tile_using_for %6#0 [0, %tt#0] : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) - transform.structured.tile_using_for %6#1 [0, %tt#1] : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) + transform.structured.tile_using_for %6#0 tile_sizes [0, %tt#0] : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) + transform.structured.tile_using_for %6#1 tile_sizes [0, %tt#1] : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } } @@ -110,13 +110,13 @@ module attributes {transform.with_named_sequence} { %1:3 = transform.structured.multitile_sizes %0 { dimension = 0, target_size = 3} : (!transform.any_op) -> !transform.param %t:3 = transform.structured.multitile_sizes %0 { dimension = 1, target_size = 10} : (!transform.any_op) -> !transform.param %2:2 = transform.structured.split %0 after %1#2 { dimension = 0 } : !transform.any_op, !transform.param - %3:2 = transform.structured.tile_using_for %2#0 [%1#0] : (!transform.any_op, !transform.param) -> (!transform.any_op, !transform.any_op) - %4:2 = transform.structured.tile_using_for %2#1 [%1#1] : (!transform.any_op, !transform.param) -> (!transform.any_op, !transform.any_op) + %3:2 = transform.structured.tile_using_for %2#0 tile_sizes [%1#0] : (!transform.any_op, !transform.param) -> (!transform.any_op, !transform.any_op) + %4:2 = transform.structured.tile_using_for %2#1 tile_sizes [%1#1] : (!transform.any_op, !transform.param) -> (!transform.any_op, !transform.any_op) %5 = transform.merge_handles %3#0, %4#0 : !transform.any_op %tt:3 = transform.replicate num(%5) %t#0, %t#1, %t#2 : !transform.any_op, !transform.param, !transform.param, !transform.param %6:2 = transform.structured.split %5 after %tt#2 { dimension = 1 } : !transform.any_op, !transform.param - transform.structured.tile_using_for %6#0 [0, %tt#0] : (!transform.any_op, !transform.param) -> (!transform.any_op, !transform.any_op) - transform.structured.tile_using_for %6#1 [0, %tt#1] : (!transform.any_op, !transform.param) -> (!transform.any_op, !transform.any_op) + transform.structured.tile_using_for %6#0 tile_sizes [0, %tt#0] : (!transform.any_op, !transform.param) -> (!transform.any_op, !transform.any_op) + transform.structured.tile_using_for %6#1 tile_sizes [0, %tt#1] : (!transform.any_op, !transform.param) -> (!transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Dialect/Linalg/promote.mlir b/mlir/test/Dialect/Linalg/promote.mlir index fb5f357f3faa..2d640057df34 100644 --- a/mlir/test/Dialect/Linalg/promote.mlir +++ b/mlir/test/Dialect/Linalg/promote.mlir @@ -183,7 +183,7 @@ func.func @gemm_shared(%a : memref, %b : memref, %c : memref !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [16, 16, 16] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [16, 16, 16] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) %2 = transform.structured.promote %1 { operands_to_promote = [0, 1], mapping = [#gpu.memory_space] } : (!transform.any_op) -> !transform.any_op transform.yield } @@ -227,7 +227,7 @@ func.func @gemm_private(%a : memref, %b : memref, %c : memref< module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [16, 16, 16] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [16, 16, 16] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) %2 = transform.structured.promote %1 { operands_to_promote = [0, 1], mapping = [#gpu.memory_space] } : (!transform.any_op) -> !transform.any_op transform.yield } diff --git a/mlir/test/Dialect/Linalg/promotion_options.mlir b/mlir/test/Dialect/Linalg/promotion_options.mlir index 3bf74b708cb8..caa72ba24316 100644 --- a/mlir/test/Dialect/Linalg/promotion_options.mlir +++ b/mlir/test/Dialect/Linalg/promotion_options.mlir @@ -37,7 +37,7 @@ func.func @gemm(%a : memref, %b : memref, %c : memref module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [16, 16, 16] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [16, 16, 16] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) %2 = transform.structured.promote %1 { operands_to_promote = [0, 2], force_full_tiles = [false, false], use_full_tiles_by_default } : (!transform.any_op) -> !transform.any_op transform.yield } diff --git a/mlir/test/Dialect/Linalg/tile-conv.mlir b/mlir/test/Dialect/Linalg/tile-conv.mlir index c42bdbe982c4..f674996e42f3 100644 --- a/mlir/test/Dialect/Linalg/tile-conv.mlir +++ b/mlir/test/Dialect/Linalg/tile-conv.mlir @@ -12,7 +12,7 @@ func.func @conv(%arg0 : memref, %arg1 : memref, %arg2 : memref module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.conv_2d"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loop:2 = transform.structured.tile_using_for %0 [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loop:2 = transform.structured.tile_using_for %0 tile_sizes [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Dialect/Linalg/tile-indexed.mlir b/mlir/test/Dialect/Linalg/tile-indexed.mlir index c176dc19c7e9..b4aa0a33bc59 100644 --- a/mlir/test/Dialect/Linalg/tile-indexed.mlir +++ b/mlir/test/Dialect/Linalg/tile-indexed.mlir @@ -14,7 +14,7 @@ func.func @indexed_vector(%arg0: memref<50xindex>) { module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loop = transform.structured.tile_using_for %0 [10] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1, %loop = transform.structured.tile_using_for %0 tile_sizes [10] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } } @@ -46,7 +46,7 @@ func.func @indexed_matrix(%arg0: memref<50x50xindex>) { module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loop:2 = transform.structured.tile_using_for %0 [10, 25] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loop:2 = transform.structured.tile_using_for %0 tile_sizes [10, 25] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Dialect/Linalg/tile-softmax.mlir b/mlir/test/Dialect/Linalg/tile-softmax.mlir index ec848e2deb74..7d201b58a8c3 100644 --- a/mlir/test/Dialect/Linalg/tile-softmax.mlir +++ b/mlir/test/Dialect/Linalg/tile-softmax.mlir @@ -39,7 +39,7 @@ func.func @softmax(%arg0: tensor<16x64x256xf32>) -> tensor<16x64x256xf32> { module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.softmax"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loop:2 = transform.structured.tile_using_for %0 [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loop:2 = transform.structured.tile_using_for %0 tile_sizes [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -149,7 +149,7 @@ func.func @softmax_memref(%arg0: memref<16x64x256xf32>, %arg1: memref<16x64x256x module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.softmax"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loop:2 = transform.structured.tile_using_for %0 [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loop:2 = transform.structured.tile_using_for %0 tile_sizes [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Dialect/Linalg/tile-tensors.mlir b/mlir/test/Dialect/Linalg/tile-tensors.mlir index cdef71ded8b2..89183813c080 100644 --- a/mlir/test/Dialect/Linalg/tile-tensors.mlir +++ b/mlir/test/Dialect/Linalg/tile-tensors.mlir @@ -30,7 +30,7 @@ func.func @matmul_tensors( module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [2, 3, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [2, 3, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -57,7 +57,7 @@ func.func @matmul_tensors_with_size_zeros( module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1 = transform.structured.tile_using_for %0 [0, 0, 0] : (!transform.any_op) -> (!transform.any_op) + %1 = transform.structured.tile_using_for %0 tile_sizes [0, 0, 0] : (!transform.any_op) -> (!transform.any_op) transform.yield } } @@ -90,7 +90,7 @@ func.func @generic_op_tensors( module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [2, 3, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [2, 3, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -163,7 +163,7 @@ func.func @fold_extract_slice( module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [2, 3, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [2, 3, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Dialect/Linalg/tile-to-forall.mlir b/mlir/test/Dialect/Linalg/tile-to-forall.mlir index 12e2dea5530b..8545dfd25ecc 100644 --- a/mlir/test/Dialect/Linalg/tile-to-forall.mlir +++ b/mlir/test/Dialect/Linalg/tile-to-forall.mlir @@ -130,8 +130,8 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op %sz = transform.structured.match ops{["test.dummy"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1:2 = transform.structured.tile_using_forall %0 tile_sizes *(%sz : !transform.any_op) - : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1:2 = transform.structured.tile_using_forall %0 tile_sizes *(%sz) + : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } } @@ -333,8 +333,8 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op %sz = transform.structured.match ops{["test.dummy"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1:2 = transform.structured.tile_using_forall %0 tile_sizes [%sz : !transform.any_op, 20] - : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1:2 = transform.structured.tile_using_forall %0 tile_sizes [%sz, 20] + : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } } @@ -492,8 +492,8 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op %sz = transform.param.constant 10 : i64 -> !transform.param - %1:2 = transform.structured.tile_using_forall %0 tile_sizes [%sz : !transform.param, 20] - : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1:2 = transform.structured.tile_using_forall %0 tile_sizes [%sz, 20] + : (!transform.any_op, !transform.param) -> (!transform.any_op, !transform.any_op) transform.yield } } @@ -513,8 +513,8 @@ module attributes {transform.with_named_sequence} { %c20 = transform.param.constant 20 : i64 -> !transform.param %sz = transform.merge_handles %c10, %c20 : !transform.param // expected-error @below {{requires exactly one parameter associated}} - %1:2 = transform.structured.tile_using_forall %0 tile_sizes [%sz : !transform.param, 20] - : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1:2 = transform.structured.tile_using_forall %0 tile_sizes [%sz, 20] + : (!transform.any_op, !transform.param) -> (!transform.any_op, !transform.any_op) transform.yield } } @@ -562,8 +562,8 @@ module attributes {transform.with_named_sequence} { %c10 = transform.param.constant 10 : i64 -> !transform.any_param %c20 = transform.param.constant 20 : i64 -> !transform.any_param %sz = transform.merge_handles %c10, %c20 : !transform.any_param - %1:2 = transform.structured.tile_using_forall %0 tile_sizes *(%sz : !transform.any_param) - : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1:2 = transform.structured.tile_using_forall %0 tile_sizes *(%sz) + : (!transform.any_op, !transform.any_param) -> (!transform.any_op, !transform.any_op) transform.yield } } @@ -581,8 +581,8 @@ module attributes {transform.with_named_sequence} { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op %sz = transform.param.constant "[10 : i64, 20 : i64]" -> !transform.any_param // expected-error @below {{expected the parameter to be associated with an integer attribute}} - %1:2 = transform.structured.tile_using_forall %0 tile_sizes *(%sz : !transform.any_param) - : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1:2 = transform.structured.tile_using_forall %0 tile_sizes *(%sz) + : (!transform.any_op, !transform.any_param) -> (!transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Dialect/Linalg/transform-op-compose-masked-vectorize-and-cleanups.mlir b/mlir/test/Dialect/Linalg/transform-op-compose-masked-vectorize-and-cleanups.mlir index 477261882421..61fe3da34e1d 100644 --- a/mlir/test/Dialect/Linalg/transform-op-compose-masked-vectorize-and-cleanups.mlir +++ b/mlir/test/Dialect/Linalg/transform-op-compose-masked-vectorize-and-cleanups.mlir @@ -22,9 +22,9 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%module: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %module : (!transform.any_op) -> !transform.any_op - %tiled_linalg_op, %loops:3 = transform.structured.tile_using_for %0[64, 128, 256] + %tiled_linalg_op, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [64, 128, 256] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) - %tiled_linalg_op_0, %loops_1:3 = transform.structured.tile_using_for %tiled_linalg_op[8, 8, 8] + %tiled_linalg_op_0, %loops_1:3 = transform.structured.tile_using_for %tiled_linalg_op tile_sizes [8, 8, 8] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.structured.vectorize %tiled_linalg_op_0 vector_sizes [8, 8, 8] : !transform.any_op diff --git a/mlir/test/Dialect/Linalg/transform-op-fuse.mlir b/mlir/test/Dialect/Linalg/transform-op-fuse.mlir index 69daf8c80a16..3a023deb1132 100644 --- a/mlir/test/Dialect/Linalg/transform-op-fuse.mlir +++ b/mlir/test/Dialect/Linalg/transform-op-fuse.mlir @@ -95,7 +95,7 @@ module attributes {transform.with_named_sequence} { %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op %1, %loops:2 = transform.structured.fuse %0 {tile_sizes = [5, 0, 7], tile_interchange = [0, 2, 1]} : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) - %2, %loops_2 = transform.structured.tile_using_for %1 [0, 4] + %2, %loops_2 = transform.structured.tile_using_for %1 tile_sizes [0, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } diff --git a/mlir/test/Dialect/Linalg/transform-op-hoist-pad-build-packing-loop-nest.mlir b/mlir/test/Dialect/Linalg/transform-op-hoist-pad-build-packing-loop-nest.mlir index 1be5bf098c33..ae63ed5f1a41 100644 --- a/mlir/test/Dialect/Linalg/transform-op-hoist-pad-build-packing-loop-nest.mlir +++ b/mlir/test/Dialect/Linalg/transform-op-hoist-pad-build-packing-loop-nest.mlir @@ -15,7 +15,7 @@ module attributes {transform.with_named_sequence} { %matmul = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul tile_sizes [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) %matmul_padded, %0, %copy_back = transform.structured.pad %matmul_l1 { padding_values=[0.0: f32, 0.0 : f32, 0.0 : f32], @@ -49,7 +49,7 @@ module attributes {transform.with_named_sequence} { %matmul = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul tile_sizes [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) %matmul_padded, %0, %copy_back = transform.structured.pad %matmul_l1 { padding_values=[0.0: f32, 0.0 : f32, 0.0 : f32], @@ -89,7 +89,7 @@ module attributes {transform.with_named_sequence} { %matmul = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul tile_sizes [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) %matmul_padded, %0, %copy_back = transform.structured.pad %matmul_l1 { padding_values=[0.0: f32, 0.0 : f32, 0.0 : f32], @@ -129,7 +129,7 @@ module attributes {transform.with_named_sequence} { %matmul = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul tile_sizes [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) %matmul_padded, %0, %copy_back = transform.structured.pad %matmul_l1 { padding_values=[0.0: f32, 0.0 : f32, 0.0 : f32], @@ -167,7 +167,7 @@ module attributes {transform.with_named_sequence} { %matmul = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %matmul_l1, %loops_l1:2 = transform.structured.tile_using_for %matmul [5, 0, 7] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %matmul_l1, %loops_l1:2 = transform.structured.tile_using_for %matmul tile_sizes [5, 0, 7] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) %matmul_padded, %0, %copy_back = transform.structured.pad %matmul_l1 { padding_values=[0.0: f32, 0.0 : f32, 0.0 : f32], diff --git a/mlir/test/Dialect/Linalg/transform-op-hoist-pad.mlir b/mlir/test/Dialect/Linalg/transform-op-hoist-pad.mlir index 37cb9b2376fb..499d9904c06b 100644 --- a/mlir/test/Dialect/Linalg/transform-op-hoist-pad.mlir +++ b/mlir/test/Dialect/Linalg/transform-op-hoist-pad.mlir @@ -15,7 +15,7 @@ module attributes {transform.with_named_sequence} { : (!transform.any_op) -> !transform.any_op - %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul tile_sizes [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) %matmul_padded, %0, %copy_back = transform.structured.pad %matmul_l1 { padding_values=[0.0: f32, 0.0 : f32, 0.0 : f32], @@ -53,7 +53,7 @@ module attributes {transform.with_named_sequence} { : (!transform.any_op) -> !transform.any_op - %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul tile_sizes [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) %matmul_padded, %0, %copy_back = transform.structured.pad %matmul_l1 { padding_values=[0.0: f32, 0.0 : f32, 0.0 : f32], @@ -98,7 +98,7 @@ module attributes {transform.with_named_sequence} { : (!transform.any_op) -> !transform.any_op - %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul tile_sizes [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) %matmul_padded, %0, %copy_back = transform.structured.pad %matmul_l1 { padding_values=[0.0: f32, 0.0 : f32, 0.0 : f32], @@ -145,7 +145,7 @@ module attributes {transform.with_named_sequence} { : (!transform.any_op) -> !transform.any_op - %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %matmul_l1, %loops_l1 = transform.structured.tile_using_for %matmul tile_sizes [5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) %matmul_padded, %0, %copy_back = transform.structured.pad %matmul_l1 { padding_values=[0.0: f32, 0.0 : f32, 0.0 : f32], @@ -191,7 +191,7 @@ module attributes {transform.with_named_sequence} { : (!transform.any_op) -> !transform.any_op - %matmul_l1, %loops_l1:2 = transform.structured.tile_using_for %matmul [5, 0, 7] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %matmul_l1, %loops_l1:2 = transform.structured.tile_using_for %matmul tile_sizes [5, 0, 7] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) %matmul_padded, %0, %copy_back = transform.structured.pad %matmul_l1 { padding_values=[0.0: f32, 0.0 : f32, 0.0 : f32], diff --git a/mlir/test/Dialect/Linalg/transform-op-mmt4d-to-fma.mlir b/mlir/test/Dialect/Linalg/transform-op-mmt4d-to-fma.mlir index 6aba2b3bb368..b5c6e610f58f 100644 --- a/mlir/test/Dialect/Linalg/transform-op-mmt4d-to-fma.mlir +++ b/mlir/test/Dialect/Linalg/transform-op-mmt4d-to-fma.mlir @@ -20,10 +20,10 @@ module attributes {transform.with_named_sequence} { // Step 1: Tile // Tile parallel dims - %tiled_linalg_op_p, %loops:4 = transform.structured.tile_using_for %mmt4d[1, 1, 0, 8, 8, 0] + %tiled_linalg_op_p, %loops:4 = transform.structured.tile_using_for %mmt4d tile_sizes [1, 1, 0, 8, 8, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) // Tile reduction dims - %tiled_linalg_op_r, %loops2:2 = transform.structured.tile_using_for %tiled_linalg_op_p[0, 0, 1, 0, 0, 1] + %tiled_linalg_op_r, %loops2:2 = transform.structured.tile_using_for %tiled_linalg_op_p tile_sizes [0, 0, 1, 0, 0, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) // Step 2: Vectorize diff --git a/mlir/test/Dialect/Linalg/transform-op-pack.mlir b/mlir/test/Dialect/Linalg/transform-op-pack.mlir index cf6339ce3de8..6c26ebd0a5b8 100644 --- a/mlir/test/Dialect/Linalg/transform-op-pack.mlir +++ b/mlir/test/Dialect/Linalg/transform-op-pack.mlir @@ -372,8 +372,8 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op %sz = transform.structured.match ops{["some_tile_size"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1 = transform.structured.pack %0 packed_sizes = [0, %sz : !transform.any_op, %sz : !transform.any_op] - : (!transform.any_op) -> (!transform.op<"linalg.generic">) + %1 = transform.structured.pack %0 packed_sizes = [0, %sz, %sz] + : (!transform.any_op, !transform.any_op, !transform.any_op) -> (!transform.op<"linalg.generic">) transform.yield } } diff --git a/mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize-conv.mlir b/mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize-conv.mlir index 7f3997633a30..4bb40bef9fba 100644 --- a/mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize-conv.mlir +++ b/mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize-conv.mlir @@ -61,11 +61,11 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%root: !transform.any_op {transform.consume}) { // 1. Tile parallel dims %1 = transform.structured.match ops{["linalg.depthwise_conv_2d_nhwc_hwc"]} in %root : (!transform.any_op) -> !transform.any_op - %tiled_linalg_op_0, %loops_1:4 = transform.structured.tile_using_for %1[1, 1, 4, [4], 0, 0] : (!transform.any_op) -> (!transform.any_op, !transform.op<"scf.for">, !transform.op<"scf.for">, !transform.op<"scf.for">, !transform.op<"scf.for">) + %tiled_linalg_op_0, %loops_1:4 = transform.structured.tile_using_for %1 tile_sizes [1, 1, 4, [4], 0, 0] : (!transform.any_op) -> (!transform.any_op, !transform.op<"scf.for">, !transform.op<"scf.for">, !transform.op<"scf.for">, !transform.op<"scf.for">) // 2. Tile reduction dims %2 = transform.structured.match ops{["linalg.depthwise_conv_2d_nhwc_hwc"]} in %loops_1#3 : (!transform.op<"scf.for">) -> !transform.any_op - %tiled_linalg_op_1, %loops_2:2 = transform.structured.tile_using_for %2[0, 0, 0, 0, 1, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %tiled_linalg_op_1, %loops_2:2 = transform.structured.tile_using_for %2 tile_sizes [0, 0, 0, 0, 1, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) // 3. Decompose 2D conv into 2 x 1D conv %3 = transform.structured.match ops{["linalg.depthwise_conv_2d_nhwc_hwc"]} in %loops_1#3 : (!transform.op<"scf.for">) -> !transform.any_op diff --git a/mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize.mlir b/mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize.mlir index b7e316f8925d..05a032b1ece0 100644 --- a/mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize.mlir +++ b/mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize.mlir @@ -67,7 +67,7 @@ module attributes {transform.with_named_sequence} { %matmul = transform.structured.match ops{["linalg.matmul"]} in %root : (!transform.any_op) -> !transform.any_op // 1. Scalable tiling %_, %loop_1, %loop_2, %loop_3 = - transform.structured.tile_using_for %matmul [8, [16], 1] : (!transform.any_op) + transform.structured.tile_using_for %matmul tile_sizes [8, [16], 1] : (!transform.any_op) -> (!transform.any_op, !transform.op<"scf.for">, !transform.op<"scf.for">,!transform.op<"scf.for">) // 2. Loop peeling (only the middle dimension) diff --git a/mlir/test/Dialect/Linalg/transform-op-scalarize.mlir b/mlir/test/Dialect/Linalg/transform-op-scalarize.mlir index 7d642c8995f0..91949f58931a 100644 --- a/mlir/test/Dialect/Linalg/transform-op-scalarize.mlir +++ b/mlir/test/Dialect/Linalg/transform-op-scalarize.mlir @@ -21,7 +21,7 @@ func.func @scalarize(%arg0: tensor<24x12xf32>, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops = transform.structured.tile_using_for %0 [10, 0, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1, %loops = transform.structured.tile_using_for %0 tile_sizes [10, 0, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) %2 = transform.structured.scalarize %1 : (!transform.any_op) -> !transform.any_op transform.yield } diff --git a/mlir/test/Dialect/Linalg/transform-op-tile.mlir b/mlir/test/Dialect/Linalg/transform-op-tile.mlir index ea8c5e612479..d244670f7375 100644 --- a/mlir/test/Dialect/Linalg/transform-op-tile.mlir +++ b/mlir/test/Dialect/Linalg/transform-op-tile.mlir @@ -3,7 +3,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [4, 4, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [4, 4, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -42,7 +42,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op %1 = transform.structured.match ops{["func.call"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %2, %loops:3 = transform.structured.tile_using_for %0 [%1, %1, 4] : (!transform.any_op, !transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %2, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [%1, %1, 4] : (!transform.any_op, !transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -86,7 +86,7 @@ module attributes {transform.with_named_sequence} { // expected-note @below {{for this parameter}} %1 = transform.test_produce_param (0 : i64) : !transform.param // expected-error @below {{expected as many parameter values (0) as target ops (2)}} - transform.structured.tile_using_for %0 [%1, %1, %1] + transform.structured.tile_using_for %0 tile_sizes [%1, %1, %1] : (!transform.any_op, !transform.param, !transform.param, !transform.param) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield @@ -113,7 +113,7 @@ module attributes {transform.with_named_sequence} { // expected-note @below {{for this handle}} %1 = transform.structured.match ops{["arith.constant"]} in %arg1 : (!transform.any_op) -> !transform.any_op // expected-error @below {{expected as many dynamic size-producing operations (0) as target ops (2)}} - transform.structured.tile_using_for %0 [%1, %1, 1] + transform.structured.tile_using_for %0 tile_sizes [%1, %1, 1] : (!transform.any_op, !transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield @@ -194,7 +194,7 @@ module { module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loop = transform.structured.tile_using_for %0 [[4]] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1, %loop = transform.structured.tile_using_for %0 tile_sizes [[4]] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } } @@ -230,7 +230,7 @@ func.func @scalable_and_fixed_length_tile( module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [4, 4, [4]] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [4, 4, [4]] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -249,7 +249,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op // expected-error @below {{too many tiles provided, expected at most 3 found 4}} - %1, %loops = transform.structured.tile_using_for %0 [1, 0, 0, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1, %loops = transform.structured.tile_using_for %0 tile_sizes [1, 0, 0, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Dialect/Linalg/transform-ops-invalid.mlir b/mlir/test/Dialect/Linalg/transform-ops-invalid.mlir index e7d9815ab222..e86d4962530a 100644 --- a/mlir/test/Dialect/Linalg/transform-ops-invalid.mlir +++ b/mlir/test/Dialect/Linalg/transform-ops-invalid.mlir @@ -77,7 +77,7 @@ transform.sequence failures(propagate) { transform.sequence failures(propagate) { ^bb0(%arg0: !transform.any_op): %0 = transform.param.constant 2 : i64 -> !transform.param - // expected-error@below {{custom op 'transform.structured.vectorize' expected 2 operand type(s)}} + // expected-error@below {{custom op 'transform.structured.vectorize' 1 operands present, but expected 2}} transform.structured.vectorize %arg0 vector_sizes [%0, 2] : !transform.any_op, !transform.param, !transform.param } diff --git a/mlir/test/Dialect/Linalg/transform-ops.mlir b/mlir/test/Dialect/Linalg/transform-ops.mlir index 8f6274fd22c2..733f305f850c 100644 --- a/mlir/test/Dialect/Linalg/transform-ops.mlir +++ b/mlir/test/Dialect/Linalg/transform-ops.mlir @@ -3,7 +3,7 @@ transform.sequence failures(propagate) { ^bb1(%arg0: !transform.any_op): // CHECK %{{.*}}, %{{.*}}:2 = transform.structured.tile - %0, %1:2 = transform.structured.tile_using_for %arg0 [2, 0, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %0, %1:2 = transform.structured.tile_using_for %arg0 tile_sizes [2, 0, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) } // check that the Attributes of `tile_using_for` are preserved through printing @@ -11,9 +11,9 @@ transform.sequence failures(propagate) { transform.sequence failures(propagate) { ^bb1(%arg0: !transform.any_op): // CHECK %{{.*}}, %{{.*}}:2 = transform.structured.tile %arg0 [2, 0, 3] interchange = [2, 1] {test_attr1 = 1 : i64, test_attr2} - %0, %1:2 = transform.structured.tile_using_for %arg0 [2, 0, 3] interchange = [2, 1] {test_attr1 = 1 : i64, test_attr2}: (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %0, %1:2 = transform.structured.tile_using_for %arg0 tile_sizes [2, 0, 3] interchange = [2, 1] {test_attr1 = 1 : i64, test_attr2}: (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) // CHECK %{{.*}}, %{{.*}}:2 = transform.structured.tile %arg0 [4, 5, 3] {test_attr3 = 1 : i64, test_attr4} - %2, %3:2 = transform.structured.tile_using_for %0 [0, 5, 3] {test_attr3 = 1 : i64, test_attr4}: (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %2, %3:2 = transform.structured.tile_using_for %0 tile_sizes [0, 5, 3] {test_attr3 = 1 : i64, test_attr4}: (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) } transform.sequence failures(propagate) { diff --git a/mlir/test/Dialect/Linalg/transform-patterns.mlir b/mlir/test/Dialect/Linalg/transform-patterns.mlir index 5a9b490c07ff..87b7664198da 100644 --- a/mlir/test/Dialect/Linalg/transform-patterns.mlir +++ b/mlir/test/Dialect/Linalg/transform-patterns.mlir @@ -12,7 +12,7 @@ func.func @dot(%x: memref>, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.dot"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loop = transform.structured.tile_using_for %0 [8000] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1, %loop = transform.structured.tile_using_for %0 tile_sizes [8000] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } } @@ -38,7 +38,7 @@ func.func @matvec(%A: memref>, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matvec"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [5, 6] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [5, 6] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -67,10 +67,10 @@ func.func @matmul(%A: memref>, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [2000, 3000, 4000] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) - %2, %loops_2:3 = transform.structured.tile_using_for %1 [200, 300, 400] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) - %3, %loops_3:3 = transform.structured.tile_using_for %2 [20, 30, 40] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) - %4, %loops_4:3 = transform.structured.tile_using_for %3 [2, 3, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [2000, 3000, 4000] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %2, %loops_2:3 = transform.structured.tile_using_for %1 tile_sizes [200, 300, 400] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %3, %loops_3:3 = transform.structured.tile_using_for %2 tile_sizes [20, 30, 40] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %4, %loops_4:3 = transform.structured.tile_using_for %3 tile_sizes [2, 3, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -170,7 +170,7 @@ func.func @matvec_perm(%A: memref>, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matvec"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [5, 6] interchange = [1, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [5, 6] interchange = [1, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -199,9 +199,9 @@ func.func @matmul_perm(%A: memref>, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [2000, 3000, 4000] interchange = [1, 2, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) - %2, %loops_2:3 = transform.structured.tile_using_for %1 [200, 300, 400] interchange = [1, 0, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) - %3, %loops_3:3 = transform.structured.tile_using_for %2 [20, 30, 40] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [2000, 3000, 4000] interchange = [1, 2, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %2, %loops_2:3 = transform.structured.tile_using_for %1 tile_sizes [200, 300, 400] interchange = [1, 0, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %3, %loops_3:3 = transform.structured.tile_using_for %2 tile_sizes [20, 30, 40] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Dialect/Linalg/vectorize-tensor-extract-masked.mlir b/mlir/test/Dialect/Linalg/vectorize-tensor-extract-masked.mlir index edc38b42f5cd..e68d297dc41f 100644 --- a/mlir/test/Dialect/Linalg/vectorize-tensor-extract-masked.mlir +++ b/mlir/test/Dialect/Linalg/vectorize-tensor-extract-masked.mlir @@ -28,7 +28,7 @@ func.func @masked_static_vectorize_nd_tensor_extract_with_affine_apply_contiguou module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - transform.structured.vectorize %0 vector_sizes [1, 4] vectorize_nd_extract : !transform.any_op + transform.structured.vectorize %0 vector_sizes [1, 4] {vectorize_nd_extract} : !transform.any_op transform.yield } } @@ -85,7 +85,7 @@ func.func @masked_dynamic_vectorize_nd_tensor_extract_with_affine_apply_contiguo module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - transform.structured.vectorize %0 vector_sizes [1, 4] vectorize_nd_extract : !transform.any_op + transform.structured.vectorize %0 vector_sizes [1, 4] {vectorize_nd_extract} : !transform.any_op transform.yield } } @@ -125,7 +125,7 @@ func.func @masked_vectorize_nd_tensor_extract_with_affine_apply_gather(%6: tenso module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - transform.structured.vectorize %0 vector_sizes [1, 4] vectorize_nd_extract : !transform.any_op + transform.structured.vectorize %0 vector_sizes [1, 4] {vectorize_nd_extract} : !transform.any_op transform.yield } } @@ -182,7 +182,7 @@ func.func @masked_dynamic_vectorize_nd_tensor_extract_with_affine_apply_gather(% module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - transform.structured.vectorize %0 vector_sizes [1, 4] vectorize_nd_extract : !transform.any_op + transform.structured.vectorize %0 vector_sizes [1, 4] {vectorize_nd_extract} : !transform.any_op transform.yield } } @@ -234,7 +234,7 @@ func.func @extract_masked_vectorize(%arg0: tensor, %arg1: tensor !transform.any_op - transform.structured.vectorize %0 vector_sizes [3, 3] vectorize_nd_extract : !transform.any_op + transform.structured.vectorize %0 vector_sizes [3, 3] {vectorize_nd_extract} : !transform.any_op transform.yield } } @@ -279,7 +279,7 @@ func.func @tensor_extract_dynamic_shape(%arg1: tensor<123x321xf32>, %arg2: tenso module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - transform.structured.vectorize %0 vector_sizes [1, 3, 8] vectorize_nd_extract : !transform.any_op + transform.structured.vectorize %0 vector_sizes [1, 3, 8] {vectorize_nd_extract} : !transform.any_op transform.yield } } diff --git a/mlir/test/Dialect/Tensor/tiling.mlir b/mlir/test/Dialect/Tensor/tiling.mlir index 1afbd3d0504f..e02ab06a9d53 100644 --- a/mlir/test/Dialect/Tensor/tiling.mlir +++ b/mlir/test/Dialect/Tensor/tiling.mlir @@ -34,7 +34,7 @@ func.func @dynamic_pad_tensor_3_4(%input_tensor: tensor, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pad"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -73,7 +73,7 @@ func.func @dynamic_pad_tensor_0_3(%input_tensor: tensor, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pad"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loop = transform.structured.tile_using_for %0 [0, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1, %loop = transform.structured.tile_using_for %0 tile_sizes [0, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } } @@ -109,7 +109,7 @@ func.func @static_pad_tensor_3_4(%input_tensor: tensor<7x9xf32>, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pad"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -142,7 +142,7 @@ func.func @static_pad_tensor_0_3(%input_tensor: tensor<7x9xf32>, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pad"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loop = transform.structured.tile_using_for %0 [0, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1, %loop = transform.structured.tile_using_for %0 tile_sizes [0, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } } @@ -179,7 +179,7 @@ func.func @static_pad_tile_evenly_0_3(%input_tensor: tensor<7x9xf32>, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pad"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loop = transform.structured.tile_using_for %0 [0, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1, %loop = transform.structured.tile_using_for %0 tile_sizes [0, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } } @@ -217,7 +217,7 @@ func.func @NC_to_NCnc(%arg0: tensor<128x256xf32>, %arg1: tensor<4x8x32x32xf32>) module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -247,7 +247,7 @@ func.func @KC_to_CKkc(%arg0: tensor<128x256xf32>, %arg1: tensor<32x4x32x8xf32>) module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -284,7 +284,7 @@ func.func @pad_and_pack_static(%input: tensor<13x15xf32>, %output: tensor<2x8x8x module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -335,7 +335,7 @@ func.func @pad_and_pack_partially_dynamic(%input: tensor, %output: tens module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -391,7 +391,7 @@ func.func @pad_and_pack_fully_dynamic(%source: tensor, %dest: tensor !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -440,7 +440,7 @@ func.func @NCnc_to_NC(%source: tensor<8x8x32x16xf32>, %dest: tensor<256x128xf32> module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.unpack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -488,7 +488,7 @@ func.func @CKkc_to_KC(%source: tensor<32x4x32x8xf32>, %dest: tensor<128x256xf32> module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.unpack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -526,7 +526,7 @@ func.func @perfect_CKkc_to_KC(%source: tensor<32x4x2x4xf32>, %dest: tensor<8x128 module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.unpack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -570,7 +570,7 @@ func.func @dynamic_perfect_CKkc_to_KC(%source: tensor, %dest: tenso module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.unpack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -607,7 +607,7 @@ func.func @perfect_NKPQk_to_NPQK(%source: tensor<1x4x6x6x2xf32>, %dest: tensor<1 module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.unpack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:4 = transform.structured.tile_using_for %0 [1, 1, 1, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:4 = transform.structured.tile_using_for %0 tile_sizes [1, 1, 1, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -635,7 +635,7 @@ func.func @fully_dynamic_unpack(%source: tensor, %dest: tensor !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [4, 8] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [4, 8] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -671,7 +671,7 @@ func.func @perfect_NPQK_to_NKPQk(%source: tensor<1x6x6x8xf32>, %dest: tensor<1x4 module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["tensor.pack"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:4 = transform.structured.tile_using_for %0 [1, 1, 1, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:4 = transform.structured.tile_using_for %0 tile_sizes [1, 1, 1, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Dialect/Transform/ops.mlir b/mlir/test/Dialect/Transform/ops.mlir index ecef7e181e90..b03a9f4d760d 100644 --- a/mlir/test/Dialect/Transform/ops.mlir +++ b/mlir/test/Dialect/Transform/ops.mlir @@ -101,19 +101,19 @@ transform.sequence failures(propagate) { } // CHECK: transform.sequence -// CHECK: transform.structured.tile_using_for %0[4, 4, [4]] +// CHECK: transform.structured.tile_using_for %0 tile_sizes [4, 4, [4]] transform.sequence failures(propagate) { ^bb0(%arg1: !transform.any_op): %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - transform.structured.tile_using_for %0 [4, 4, [4]] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + transform.structured.tile_using_for %0 tile_sizes [4, 4, [4]] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) } // CHECK: transform.sequence -// CHECK: transform.structured.tile_using_for %0{{\[}}[2], 4, 8] +// CHECK: transform.structured.tile_using_for %0 tile_sizes {{\[}}[2], 4, 8] transform.sequence failures(propagate) { ^bb0(%arg1: !transform.any_op): %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - transform.structured.tile_using_for %0 [[2], 4, 8] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + transform.structured.tile_using_for %0 tile_sizes [[2], 4, 8] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) } // CHECK: transform.sequence diff --git a/mlir/test/Dialect/Transform/selective-targeting.mlir b/mlir/test/Dialect/Transform/selective-targeting.mlir index e88104315649..69342100935c 100644 --- a/mlir/test/Dialect/Transform/selective-targeting.mlir +++ b/mlir/test/Dialect/Transform/selective-targeting.mlir @@ -79,7 +79,7 @@ module attributes {transform.with_named_sequence} { transform.sequence %arg0 : !transform.any_op failures(propagate) { ^bb1(%arg1: !transform.any_op): %0 = pdl_match @pdl_target_attrA in %arg1 : (!transform.any_op) -> !transform.any_op - transform.structured.tile_using_for %0 [4, 4, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + transform.structured.tile_using_for %0 tile_sizes [4, 4, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) %1 = pdl_match @pdl_target_attrC in %arg1 : (!transform.any_op) -> !transform.any_op %2 = get_parent_op %1 {isolated_from_above} : (!transform.any_op) -> !transform.any_op transform.structured.vectorize_children_and_apply_patterns %2 : (!transform.any_op) -> !transform.any_op diff --git a/mlir/test/Dialect/Vector/transform-vector.mlir b/mlir/test/Dialect/Vector/transform-vector.mlir index a0ca8c2fa9b6..75b29e22b4d2 100644 --- a/mlir/test/Dialect/Vector/transform-vector.mlir +++ b/mlir/test/Dialect/Vector/transform-vector.mlir @@ -16,7 +16,7 @@ func.func @matmul_tensors( module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%module_op: !transform.any_op {transform.consumed}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %module_op : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [8, 4, 2] + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [8, 4, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) %2 = transform.get_parent_op %1 {isolated_from_above} : (!transform.any_op) -> !transform.any_op transform.structured.vectorize_children_and_apply_patterns %2 : (!transform.any_op) -> !transform.any_op diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir index 34c5351c8703..a8b6457d64be 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir @@ -61,7 +61,7 @@ module attributes {transform.with_named_sequence} { // Step 1: Tile for size [4] x [4], which corresponds to SVLs x SVLs, where // SVLs is the number of 32-bit elements in a vector of SVL bits. - %tiled_linalg_op, %loops:3 = transform.structured.tile_using_for %matmul_transpose_a[[4], [4], 1] + %tiled_linalg_op, %loops:3 = transform.structured.tile_using_for %matmul_transpose_a tile_sizes [[4], [4], 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) // Step 2: Vectorize. diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir index 2bfdaa8e8a2b..091665223188 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir @@ -59,7 +59,7 @@ module attributes {transform.with_named_sequence} { // Step 1: Tile for size [4] x [4], which corresponds to SVLs x SVLs, where // SVLs is the number of 32-bit elements in a vector of SVL bits. - %tiled_linalg_op, %loops:3 = transform.structured.tile_using_for %matmul[[4], [4], 1] + %tiled_linalg_op, %loops:3 = transform.structured.tile_using_for %matmul tile_sizes [[4], [4], 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) // Step 2: Vectorize. diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir index 9f06226a4f65..10ffed268817 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir @@ -84,7 +84,7 @@ module attributes {transform.with_named_sequence} { // Step 1: Tile for size [8] x [8] (unrolled by 4), which corresponds to // (2 x SVLs) x (2 x SVLs), where SVLs is the number of 32-bit elements in a // vector of SVL bits. This uses all four 32-bit SME virtual tiles. - %tiled_linalg_op, %loop_i, %loop_j, %loop_k = transform.structured.tile_using_for %matmul[[8], [8], 4] + %tiled_linalg_op, %loop_i, %loop_j, %loop_k = transform.structured.tile_using_for %matmul tile_sizes [[8], [8], 4] : (!transform.any_op) -> (!transform.any_op, !transform.op<"scf.for">, !transform.op<"scf.for">, !transform.op<"scf.for">) // Step 2: Vectorize. diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir index e376bdde24a1..ada744b322fe 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir @@ -72,7 +72,7 @@ module attributes {transform.with_named_sequence} { // Step 1: Tile for size [8] x [8] (unrolled by 4), which corresponds to // (2 x SVLs) x (2 x SVLs), where SVLs is the number of 32-bit elements in a // vector of SVL bits. This uses all four 32-bit SME virtual tiles. - %tiled_linalg_op, %loop_i, %loop_j, %loop_k = transform.structured.tile_using_for %matmul[[8], [8], 4] + %tiled_linalg_op, %loop_i, %loop_j, %loop_k = transform.structured.tile_using_for %matmul tile_sizes [[8], [8], 4] : (!transform.any_op) -> (!transform.any_op, !transform.op<"scf.for">, !transform.op<"scf.for">, !transform.op<"scf.for">) // Step 2: Vectorize. diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir index 68e474fe5cef..edb9de922808 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir @@ -96,7 +96,7 @@ module attributes {transform.with_named_sequence} { : (!transform.op<"func.func">) -> !transform.any_op // Step 1: Tile - %tiled_matmul, %loops:3 = transform.structured.tile_using_for %matmul [2, [4], 1] + %tiled_matmul, %loops:3 = transform.structured.tile_using_for %matmul tile_sizes [2, [4], 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) // Step 2: Vectorize diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/mmt4d.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/mmt4d.mlir index 92c7039c8496..183625f9748c 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/mmt4d.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/mmt4d.mlir @@ -70,10 +70,10 @@ module @transforms attributes { transform.with_named_sequence } { // Step 1: Tile // Tile parallel dims - %tiled_linalg_op_p, %loops:4 = transform.structured.tile_using_for %mmt4d[1, 1, 0, 3, 3, 0] + %tiled_linalg_op_p, %loops:4 = transform.structured.tile_using_for %mmt4d tile_sizes [1, 1, 0, 3, 3, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) // Tile reduction dims - %tiled_linalg_op_r, %loops2:2 = transform.structured.tile_using_for %tiled_linalg_op_p[0, 0, 1, 0, 0, 1] + %tiled_linalg_op_r, %loops2:2 = transform.structured.tile_using_for %tiled_linalg_op_p tile_sizes [0, 0, 1, 0, 0, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) // Step 2: Vectorize diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/pack-unpack-mmt4d.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/pack-unpack-mmt4d.mlir index 5680882dccb1..10b29dd70177 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/pack-unpack-mmt4d.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/pack-unpack-mmt4d.mlir @@ -107,10 +107,10 @@ module @transforms attributes { transform.with_named_sequence } { // Step 1: Tile // Tile parallel dims - %tiled_linalg_op_p, %loops:4 = transform.structured.tile_using_for %mmt4d[1, 1, 0, 8, 8, 0] + %tiled_linalg_op_p, %loops:4 = transform.structured.tile_using_for %mmt4d tile_sizes [1, 1, 0, 8, 8, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) // Tile reduction dims - %tiled_linalg_op_r, %loops2:2 = transform.structured.tile_using_for %tiled_linalg_op_p[0, 0, 1, 0, 0, 1] + %tiled_linalg_op_r, %loops2:2 = transform.structured.tile_using_for %tiled_linalg_op_p tile_sizes [0, 0, 1, 0, 0, 1] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) // Step 2: Vectorize diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-1d-call.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-1d-call.mlir index 443963fb8c59..9b46056918b5 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-1d-call.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-1d-call.mlir @@ -27,7 +27,7 @@ func.func @conv_1d(%arg0: memref, %arg1: memref, %arg2: memref !transform.any_op - %1, %loop = transform.structured.tile_using_for %0 [4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + %1, %loop = transform.structured.tile_using_for %0 tile_sizes [4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-1d-nwc-wcf-call.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-1d-nwc-wcf-call.mlir index f652d707de05..d6726fe1a6b4 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-1d-nwc-wcf-call.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-1d-nwc-wcf-call.mlir @@ -29,7 +29,7 @@ func.func @conv_1d_nwc_wcf(%arg0: memref, %arg1: memref, % module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.conv_1d_nwc_wcf"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 4] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-2d-call.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-2d-call.mlir index 2eaba8233d69..bb77d5eb9b8d 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-2d-call.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-2d-call.mlir @@ -27,7 +27,7 @@ func.func @conv_2d(%arg0: memref, %arg1: memref, %arg2: memref module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.conv_2d"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [2, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 tile_sizes [2, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-2d-nhwc-hwcf-call.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-2d-nhwc-hwcf-call.mlir index eac8d8a6ea43..39415dff1cbb 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-2d-nhwc-hwcf-call.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-2d-nhwc-hwcf-call.mlir @@ -29,7 +29,7 @@ func.func @conv_2d_nhwc_hwcf(%arg0: memref, %arg1: memref !transform.any_op - %1, %loops:4 = transform.structured.tile_using_for %0 [2, 3, 3, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:4 = transform.structured.tile_using_for %0 tile_sizes [2, 3, 3, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-3d-call.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-3d-call.mlir index d5584cd67702..ece054ac7176 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-3d-call.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-3d-call.mlir @@ -27,7 +27,7 @@ func.func @conv_3d(%arg0: memref, %arg1: memref, %arg2: me module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.conv_3d"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [2, 2, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [2, 2, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-3d-ndhwc-dhwcf-call.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-3d-ndhwc-dhwcf-call.mlir index 7dca79334565..ce169ee470c3 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-3d-ndhwc-dhwcf-call.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/test-conv-3d-ndhwc-dhwcf-call.mlir @@ -29,7 +29,7 @@ func.func @conv_3d_ndhwc_dhwcf(%arg0: memref, %arg1: memref !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [0, 5, 5, 5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [0, 5, 5, 5] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/test-tensor-matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/test-tensor-matmul.mlir index fda7ffb0c753..41296cdfcb2d 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/test-tensor-matmul.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/test-tensor-matmul.mlir @@ -39,7 +39,7 @@ func.func @main() { module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [1, 2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 tile_sizes [1, 2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } diff --git a/mlir/test/Interfaces/TilingInterface/tile-pad-using-interface.mlir b/mlir/test/Interfaces/TilingInterface/tile-pad-using-interface.mlir index ba56206f03d7..7d247aefcf6b 100644 --- a/mlir/test/Interfaces/TilingInterface/tile-pad-using-interface.mlir +++ b/mlir/test/Interfaces/TilingInterface/tile-pad-using-interface.mlir @@ -14,7 +14,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %pad = transform.structured.match ops{["tensor.pad"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b, %c = transform.structured.tile_using_for %pad [2, 3] + %a, %b, %c = transform.structured.tile_using_for %pad tile_sizes [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } @@ -57,7 +57,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %pad = transform.structured.match ops{["tensor.pad"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b = transform.structured.tile_using_for %pad [0, 3] + %a, %b = transform.structured.tile_using_for %pad tile_sizes [0, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } @@ -97,7 +97,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %pad = transform.structured.match ops{["tensor.pad"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b, %c = transform.structured.tile_using_for %pad [2, 3] + %a, %b, %c = transform.structured.tile_using_for %pad tile_sizes [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } @@ -134,7 +134,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %pad = transform.structured.match ops{["tensor.pad"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b = transform.structured.tile_using_for %pad [0, 3] + %a, %b = transform.structured.tile_using_for %pad tile_sizes [0, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } @@ -170,7 +170,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %pad = transform.structured.match ops{["tensor.pad"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b, %c = transform.structured.tile_using_for %pad [2, 3] + %a, %b, %c = transform.structured.tile_using_for %pad tile_sizes [2, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } @@ -192,7 +192,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %pad = transform.structured.match ops{["tensor.pad"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b = transform.structured.tile_using_for %pad [0, 3] + %a, %b = transform.structured.tile_using_for %pad tile_sizes [0, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op) transform.yield } diff --git a/mlir/test/Interfaces/TilingInterface/tile-using-interface.mlir b/mlir/test/Interfaces/TilingInterface/tile-using-interface.mlir index 607836faafb7..488a52e8e3e9 100644 --- a/mlir/test/Interfaces/TilingInterface/tile-using-interface.mlir +++ b/mlir/test/Interfaces/TilingInterface/tile-using-interface.mlir @@ -11,7 +11,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %matmul = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b, %c = transform.structured.tile_using_for %matmul [10, 20] + %a, %b, %c = transform.structured.tile_using_for %matmul tile_sizes [10, 20] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } @@ -63,7 +63,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %matmul = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b, %c, %d = transform.structured.tile_using_for %matmul [10, 20, 30] + %a, %b, %c, %d = transform.structured.tile_using_for %matmul tile_sizes [10, 20, 30] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } @@ -122,7 +122,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %generic = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b, %c = transform.structured.tile_using_for %generic [10, 0, 20] + %a, %b, %c = transform.structured.tile_using_for %generic tile_sizes [10, 0, 20] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } @@ -175,7 +175,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %conv = transform.structured.match ops{["linalg.conv_2d_nhwc_hwcf"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b, %c, %d = transform.structured.tile_using_for %conv [0, 0, 0, 0, 10, 20, 30] + %a, %b, %c, %d = transform.structured.tile_using_for %conv tile_sizes [0, 0, 0, 0, 10, 20, 30] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } @@ -254,7 +254,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %generic = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b, %c = transform.structured.tile_using_for %generic [10, 20] + %a, %b, %c = transform.structured.tile_using_for %generic tile_sizes [10, 20] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } @@ -282,7 +282,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %matmul = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b, %c, %d = transform.structured.tile_using_for %matmul [10, 20, 30] interchange = [1, 2, 0] + %a, %b, %c, %d = transform.structured.tile_using_for %matmul tile_sizes [10, 20, 30] interchange = [1, 2, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } @@ -338,7 +338,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %copy = transform.structured.match ops{["linalg.copy"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a, %b, %c = transform.structured.tile_using_for %copy [10, 20] + %a, %b, %c = transform.structured.tile_using_for %copy tile_sizes [10, 20] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } @@ -369,7 +369,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %generic = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a = transform.structured.tile_using_for %generic [] + %a = transform.structured.tile_using_for %generic tile_sizes [] : (!transform.any_op) -> (!transform.any_op) transform.yield } @@ -396,7 +396,7 @@ module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1 : !transform.any_op {transform.readonly}) { %generic = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %a = transform.structured.tile_using_for %generic [] + %a = transform.structured.tile_using_for %generic tile_sizes [] : (!transform.any_op) -> (!transform.any_op) transform.yield } diff --git a/mlir/test/python/dialects/transform_structured_ext.py b/mlir/test/python/dialects/transform_structured_ext.py index f4c092ba9ee9..935534edba7a 100644 --- a/mlir/test/python/dialects/transform_structured_ext.py +++ b/mlir/test/python/dialects/transform_structured_ext.py @@ -501,7 +501,7 @@ def testTileToForallMixedDynamic(target): structured.TileUsingForallOp(target, num_threads=[n, 3, 4]) # CHECK-LABEL: TEST: testTileToForallMixedDynamic # CHECK: = transform.structured.tile_using_forall - # CHECK-SAME: num_threads [%{{.*}} : !transform.any_op, 3, 4] + # CHECK-SAME: num_threads [%{{.*}}, 3, 4] : (!transform.any_op, !transform.any_op) @run @@ -511,7 +511,7 @@ def testTileToForallPackedDynamic(target): structured.TileUsingForallOp(target, num_threads=n) # CHECK-LABEL: TEST: testTileToForallPackedDynamic # CHECK: = transform.structured.tile_using_forall - # CHECK-SAME: num_threads *(%0 : !transform.any_op) + # CHECK-SAME: num_threads *(%0) : (!transform.any_op, !transform.any_op) @run -- GitLab From d6d613aaebc0ae503409ba7719a43b4a55e1ee70 Mon Sep 17 00:00:00 2001 From: martinboehme Date: Wed, 8 May 2024 16:12:53 +0200 Subject: [PATCH 030/328] [clang][dataflow] Make `SolverTest` a type-parameterized test. (#91455) This allows the tests to be run against any implementation of `Solver` instead of begin specific to `WatchedLiteralsSolver` as they currently are. --- clang/docs/tools/clang-formatted-files.txt | 3 +- .../Analysis/FlowSensitive/CMakeLists.txt | 2 +- .../{SolverTest.cpp => SolverTest.h} | 166 ++++++++++-------- .../WatchedLiteralsSolverTest.cpp | 26 +++ .../unittests/Analysis/FlowSensitive/BUILD.gn | 2 +- 5 files changed, 124 insertions(+), 75 deletions(-) rename clang/unittests/Analysis/FlowSensitive/{SolverTest.cpp => SolverTest.h} (62%) create mode 100644 clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp diff --git a/clang/docs/tools/clang-formatted-files.txt b/clang/docs/tools/clang-formatted-files.txt index 2252d0ccde96..eaeadf2656b0 100644 --- a/clang/docs/tools/clang-formatted-files.txt +++ b/clang/docs/tools/clang-formatted-files.txt @@ -632,11 +632,12 @@ clang/unittests/Analysis/FlowSensitive/MapLatticeTest.cpp clang/unittests/Analysis/FlowSensitive/MatchSwitchTest.cpp clang/unittests/Analysis/FlowSensitive/MultiVarConstantPropagationTest.cpp clang/unittests/Analysis/FlowSensitive/SingleVarConstantPropagationTest.cpp -clang/unittests/Analysis/FlowSensitive/SolverTest.cpp +clang/unittests/Analysis/FlowSensitive/SolverTest.h clang/unittests/Analysis/FlowSensitive/TestingSupport.cpp clang/unittests/Analysis/FlowSensitive/TestingSupport.h clang/unittests/Analysis/FlowSensitive/TestingSupportTest.cpp clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp +clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp clang/unittests/AST/ASTImporterFixtures.cpp clang/unittests/AST/ASTImporterFixtures.h clang/unittests/AST/ASTImporterObjCTest.cpp diff --git a/clang/unittests/Analysis/FlowSensitive/CMakeLists.txt b/clang/unittests/Analysis/FlowSensitive/CMakeLists.txt index 94160d949637..cfabb80576bc 100644 --- a/clang/unittests/Analysis/FlowSensitive/CMakeLists.txt +++ b/clang/unittests/Analysis/FlowSensitive/CMakeLists.txt @@ -19,7 +19,6 @@ add_clang_unittest(ClangAnalysisFlowSensitiveTests SignAnalysisTest.cpp SimplifyConstraintsTest.cpp SingleVarConstantPropagationTest.cpp - SolverTest.cpp TestingSupport.cpp TestingSupportTest.cpp TransferBranchTest.cpp @@ -27,6 +26,7 @@ add_clang_unittest(ClangAnalysisFlowSensitiveTests TypeErasedDataflowAnalysisTest.cpp UncheckedOptionalAccessModelTest.cpp ValueTest.cpp + WatchedLiteralsSolverTest.cpp ) clang_target_link_libraries(ClangAnalysisFlowSensitiveTests diff --git a/clang/unittests/Analysis/FlowSensitive/SolverTest.cpp b/clang/unittests/Analysis/FlowSensitive/SolverTest.h similarity index 62% rename from clang/unittests/Analysis/FlowSensitive/SolverTest.cpp rename to clang/unittests/Analysis/FlowSensitive/SolverTest.h index 71f6da93594e..b37534438121 100644 --- a/clang/unittests/Analysis/FlowSensitive/SolverTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/SolverTest.h @@ -1,4 +1,4 @@ -//===- unittests/Analysis/FlowSensitive/SolverTest.cpp --------------------===// +//===--- SolverTest.h - Type-parameterized test for solvers ---------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,43 +6,53 @@ // //===----------------------------------------------------------------------===// -#include +#ifndef LLVM_CLANG_ANALYSIS_FLOW_SENSITIVE_SOLVER_TEST_H_ +#define LLVM_CLANG_ANALYSIS_FLOW_SENSITIVE_SOLVER_TEST_H_ #include "TestingSupport.h" -#include "clang/Analysis/FlowSensitive/Arena.h" -#include "clang/Analysis/FlowSensitive/Formula.h" #include "clang/Analysis/FlowSensitive/Solver.h" -#include "clang/Analysis/FlowSensitive/WatchedLiteralsSolver.h" -#include "clang/Basic/LLVM.h" -#include "llvm/ADT/ArrayRef.h" #include "gmock/gmock.h" #include "gtest/gtest.h" -#include + +namespace clang::dataflow::test { namespace { -using namespace clang; -using namespace dataflow; +constexpr auto AssignedTrue = Solver::Result::Assignment::AssignedTrue; +constexpr auto AssignedFalse = Solver::Result::Assignment::AssignedFalse; -using test::ConstraintContext; -using test::parseFormulas; using testing::_; using testing::AnyOf; using testing::Pair; using testing::UnorderedElementsAre; -constexpr auto AssignedTrue = Solver::Result::Assignment::AssignedTrue; -constexpr auto AssignedFalse = Solver::Result::Assignment::AssignedFalse; +} // namespace -// Checks if the conjunction of `Vals` is satisfiable and returns the -// corresponding result. -Solver::Result solve(llvm::ArrayRef Vals) { - return WatchedLiteralsSolver().solve(Vals); -} +/// Type-parameterized test for implementations of the `Solver` interface. +/// To use: +/// 1. Implement a specialization of `createSolverWithLowTimeout()` for the +/// solver you want to test. +/// 2. Instantiate the test suite for the solver you want to test using +/// `INSTANTIATE_TYPED_TEST_SUITE_P()`. +/// See WatchedLiteralsSolverTest.cpp for an example. +template class SolverTest : public ::testing::Test { +protected: + // Checks if the conjunction of `Vals` is satisfiable and returns the + // corresponding result. + Solver::Result solve(llvm::ArrayRef Vals) { + return SolverT().solve(Vals); + } + + // Create a specialization for the solver type to test. + SolverT createSolverWithLowTimeout(); +}; + +TYPED_TEST_SUITE_P(SolverTest); MATCHER(unsat, "") { return arg.getStatus() == Solver::Result::Status::Unsatisfiable; } + MATCHER_P(sat, SolutionMatcher, "is satisfiable, where solution " + (testing::DescribeMatcher< @@ -55,57 +65,57 @@ MATCHER_P(sat, SolutionMatcher, result_listener); } -TEST(SolverTest, Var) { +TYPED_TEST_P(SolverTest, Var) { ConstraintContext Ctx; auto X = Ctx.atom(); // X - EXPECT_THAT(solve({X}), + EXPECT_THAT(this->solve({X}), sat(UnorderedElementsAre(Pair(X->getAtom(), AssignedTrue)))); } -TEST(SolverTest, NegatedVar) { +TYPED_TEST_P(SolverTest, NegatedVar) { ConstraintContext Ctx; auto X = Ctx.atom(); auto NotX = Ctx.neg(X); // !X - EXPECT_THAT(solve({NotX}), + EXPECT_THAT(this->solve({NotX}), sat(UnorderedElementsAre(Pair(X->getAtom(), AssignedFalse)))); } -TEST(SolverTest, UnitConflict) { +TYPED_TEST_P(SolverTest, UnitConflict) { ConstraintContext Ctx; auto X = Ctx.atom(); auto NotX = Ctx.neg(X); // X ^ !X - EXPECT_THAT(solve({X, NotX}), unsat()); + EXPECT_THAT(this->solve({X, NotX}), unsat()); } -TEST(SolverTest, DistinctVars) { +TYPED_TEST_P(SolverTest, DistinctVars) { ConstraintContext Ctx; auto X = Ctx.atom(); auto Y = Ctx.atom(); auto NotY = Ctx.neg(Y); // X ^ !Y - EXPECT_THAT(solve({X, NotY}), + EXPECT_THAT(this->solve({X, NotY}), sat(UnorderedElementsAre(Pair(X->getAtom(), AssignedTrue), Pair(Y->getAtom(), AssignedFalse)))); } -TEST(SolverTest, DoubleNegation) { +TYPED_TEST_P(SolverTest, DoubleNegation) { ConstraintContext Ctx; auto X = Ctx.atom(); auto NotX = Ctx.neg(X); auto NotNotX = Ctx.neg(NotX); // !!X ^ !X - EXPECT_THAT(solve({NotNotX, NotX}), unsat()); + EXPECT_THAT(this->solve({NotNotX, NotX}), unsat()); } -TEST(SolverTest, NegatedDisjunction) { +TYPED_TEST_P(SolverTest, NegatedDisjunction) { ConstraintContext Ctx; auto X = Ctx.atom(); auto Y = Ctx.atom(); @@ -113,10 +123,10 @@ TEST(SolverTest, NegatedDisjunction) { auto NotXOrY = Ctx.neg(XOrY); // !(X v Y) ^ (X v Y) - EXPECT_THAT(solve({NotXOrY, XOrY}), unsat()); + EXPECT_THAT(this->solve({NotXOrY, XOrY}), unsat()); } -TEST(SolverTest, NegatedConjunction) { +TYPED_TEST_P(SolverTest, NegatedConjunction) { ConstraintContext Ctx; auto X = Ctx.atom(); auto Y = Ctx.atom(); @@ -124,48 +134,48 @@ TEST(SolverTest, NegatedConjunction) { auto NotXAndY = Ctx.neg(XAndY); // !(X ^ Y) ^ (X ^ Y) - EXPECT_THAT(solve({NotXAndY, XAndY}), unsat()); + EXPECT_THAT(this->solve({NotXAndY, XAndY}), unsat()); } -TEST(SolverTest, DisjunctionSameVarWithNegation) { +TYPED_TEST_P(SolverTest, DisjunctionSameVarWithNegation) { ConstraintContext Ctx; auto X = Ctx.atom(); auto NotX = Ctx.neg(X); auto XOrNotX = Ctx.disj(X, NotX); // X v !X - EXPECT_THAT(solve({XOrNotX}), sat(_)); + EXPECT_THAT(this->solve({XOrNotX}), sat(_)); } -TEST(SolverTest, DisjunctionSameVar) { +TYPED_TEST_P(SolverTest, DisjunctionSameVar) { ConstraintContext Ctx; auto X = Ctx.atom(); auto XOrX = Ctx.disj(X, X); // X v X - EXPECT_THAT(solve({XOrX}), sat(_)); + EXPECT_THAT(this->solve({XOrX}), sat(_)); } -TEST(SolverTest, ConjunctionSameVarsConflict) { +TYPED_TEST_P(SolverTest, ConjunctionSameVarsConflict) { ConstraintContext Ctx; auto X = Ctx.atom(); auto NotX = Ctx.neg(X); auto XAndNotX = Ctx.conj(X, NotX); // X ^ !X - EXPECT_THAT(solve({XAndNotX}), unsat()); + EXPECT_THAT(this->solve({XAndNotX}), unsat()); } -TEST(SolverTest, ConjunctionSameVar) { +TYPED_TEST_P(SolverTest, ConjunctionSameVar) { ConstraintContext Ctx; auto X = Ctx.atom(); auto XAndX = Ctx.conj(X, X); // X ^ X - EXPECT_THAT(solve({XAndX}), sat(_)); + EXPECT_THAT(this->solve({XAndX}), sat(_)); } -TEST(SolverTest, PureVar) { +TYPED_TEST_P(SolverTest, PureVar) { ConstraintContext Ctx; auto X = Ctx.atom(); auto Y = Ctx.atom(); @@ -175,12 +185,12 @@ TEST(SolverTest, PureVar) { auto NotXOrNotY = Ctx.disj(NotX, NotY); // (!X v Y) ^ (!X v !Y) - EXPECT_THAT(solve({NotXOrY, NotXOrNotY}), + EXPECT_THAT(this->solve({NotXOrY, NotXOrNotY}), sat(UnorderedElementsAre(Pair(X->getAtom(), AssignedFalse), Pair(Y->getAtom(), _)))); } -TEST(SolverTest, MustAssumeVarIsFalse) { +TYPED_TEST_P(SolverTest, MustAssumeVarIsFalse) { ConstraintContext Ctx; auto X = Ctx.atom(); auto Y = Ctx.atom(); @@ -191,12 +201,12 @@ TEST(SolverTest, MustAssumeVarIsFalse) { auto NotXOrNotY = Ctx.disj(NotX, NotY); // (X v Y) ^ (!X v Y) ^ (!X v !Y) - EXPECT_THAT(solve({XOrY, NotXOrY, NotXOrNotY}), + EXPECT_THAT(this->solve({XOrY, NotXOrY, NotXOrNotY}), sat(UnorderedElementsAre(Pair(X->getAtom(), AssignedFalse), Pair(Y->getAtom(), AssignedTrue)))); } -TEST(SolverTest, DeepConflict) { +TYPED_TEST_P(SolverTest, DeepConflict) { ConstraintContext Ctx; auto X = Ctx.atom(); auto Y = Ctx.atom(); @@ -208,10 +218,10 @@ TEST(SolverTest, DeepConflict) { auto XOrNotY = Ctx.disj(X, NotY); // (X v Y) ^ (!X v Y) ^ (!X v !Y) ^ (X v !Y) - EXPECT_THAT(solve({XOrY, NotXOrY, NotXOrNotY, XOrNotY}), unsat()); + EXPECT_THAT(this->solve({XOrY, NotXOrY, NotXOrNotY, XOrNotY}), unsat()); } -TEST(SolverTest, IffIsEquivalentToDNF) { +TYPED_TEST_P(SolverTest, IffIsEquivalentToDNF) { ConstraintContext Ctx; auto X = Ctx.atom(); auto Y = Ctx.atom(); @@ -222,19 +232,19 @@ TEST(SolverTest, IffIsEquivalentToDNF) { auto NotEquivalent = Ctx.neg(Ctx.iff(XIffY, XIffYDNF)); // !((X <=> Y) <=> ((X ^ Y) v (!X ^ !Y))) - EXPECT_THAT(solve({NotEquivalent}), unsat()); + EXPECT_THAT(this->solve({NotEquivalent}), unsat()); } -TEST(SolverTest, IffSameVars) { +TYPED_TEST_P(SolverTest, IffSameVars) { ConstraintContext Ctx; auto X = Ctx.atom(); auto XEqX = Ctx.iff(X, X); // X <=> X - EXPECT_THAT(solve({XEqX}), sat(_)); + EXPECT_THAT(this->solve({XEqX}), sat(_)); } -TEST(SolverTest, IffDistinctVars) { +TYPED_TEST_P(SolverTest, IffDistinctVars) { ConstraintContext Ctx; auto X = Ctx.atom(); auto Y = Ctx.atom(); @@ -242,36 +252,36 @@ TEST(SolverTest, IffDistinctVars) { // X <=> Y EXPECT_THAT( - solve({XEqY}), + this->solve({XEqY}), sat(AnyOf(UnorderedElementsAre(Pair(X->getAtom(), AssignedTrue), Pair(Y->getAtom(), AssignedTrue)), UnorderedElementsAre(Pair(X->getAtom(), AssignedFalse), Pair(Y->getAtom(), AssignedFalse))))); } -TEST(SolverTest, IffWithUnits) { +TYPED_TEST_P(SolverTest, IffWithUnits) { ConstraintContext Ctx; auto X = Ctx.atom(); auto Y = Ctx.atom(); auto XEqY = Ctx.iff(X, Y); // (X <=> Y) ^ X ^ Y - EXPECT_THAT(solve({XEqY, X, Y}), + EXPECT_THAT(this->solve({XEqY, X, Y}), sat(UnorderedElementsAre(Pair(X->getAtom(), AssignedTrue), Pair(Y->getAtom(), AssignedTrue)))); } -TEST(SolverTest, IffWithUnitsConflict) { +TYPED_TEST_P(SolverTest, IffWithUnitsConflict) { Arena A; auto Constraints = parseFormulas(A, R"( (V0 = V1) V0 !V1 )"); - EXPECT_THAT(solve(Constraints), unsat()); + EXPECT_THAT(this->solve(Constraints), unsat()); } -TEST(SolverTest, IffTransitiveConflict) { +TYPED_TEST_P(SolverTest, IffTransitiveConflict) { Arena A; auto Constraints = parseFormulas(A, R"( (V0 = V1) @@ -279,63 +289,63 @@ TEST(SolverTest, IffTransitiveConflict) { V2 !V0 )"); - EXPECT_THAT(solve(Constraints), unsat()); + EXPECT_THAT(this->solve(Constraints), unsat()); } -TEST(SolverTest, DeMorgan) { +TYPED_TEST_P(SolverTest, DeMorgan) { Arena A; auto Constraints = parseFormulas(A, R"( (!(V0 | V1) = (!V0 & !V1)) (!(V2 & V3) = (!V2 | !V3)) )"); - EXPECT_THAT(solve(Constraints), sat(_)); + EXPECT_THAT(this->solve(Constraints), sat(_)); } -TEST(SolverTest, RespectsAdditionalConstraints) { +TYPED_TEST_P(SolverTest, RespectsAdditionalConstraints) { Arena A; auto Constraints = parseFormulas(A, R"( (V0 = V1) V0 !V1 )"); - EXPECT_THAT(solve(Constraints), unsat()); + EXPECT_THAT(this->solve(Constraints), unsat()); } -TEST(SolverTest, ImplicationIsEquivalentToDNF) { +TYPED_TEST_P(SolverTest, ImplicationIsEquivalentToDNF) { Arena A; auto Constraints = parseFormulas(A, R"( !((V0 => V1) = (!V0 | V1)) )"); - EXPECT_THAT(solve(Constraints), unsat()); + EXPECT_THAT(this->solve(Constraints), unsat()); } -TEST(SolverTest, ImplicationConflict) { +TYPED_TEST_P(SolverTest, ImplicationConflict) { Arena A; auto Constraints = parseFormulas(A, R"( (V0 => V1) (V0 & !V1) )"); - EXPECT_THAT(solve(Constraints), unsat()); + EXPECT_THAT(this->solve(Constraints), unsat()); } -TEST(SolverTest, ReachedLimitsReflectsTimeouts) { +TYPED_TEST_P(SolverTest, ReachedLimitsReflectsTimeouts) { Arena A; auto Constraints = parseFormulas(A, R"( (!(V0 | V1) = (!V0 & !V1)) (!(V2 & V3) = (!V2 & !V3)) )"); - WatchedLiteralsSolver solver(10); + TypeParam solver = this->createSolverWithLowTimeout(); ASSERT_EQ(solver.solve(Constraints).getStatus(), Solver::Result::Status::TimedOut); EXPECT_TRUE(solver.reachedLimit()); } -TEST(SolverTest, SimpleButLargeContradiction) { +TYPED_TEST_P(SolverTest, SimpleButLargeContradiction) { // This test ensures that the solver takes a short-cut on known // contradictory inputs, without using max_iterations. At the time // this test is added, formulas that are easily recognized to be // contradictory at CNF construction time would lead to timeout. - WatchedLiteralsSolver solver(10); + TypeParam solver = this->createSolverWithLowTimeout(); ConstraintContext Ctx; auto first = Ctx.atom(); auto last = first; @@ -358,4 +368,16 @@ TEST(SolverTest, SimpleButLargeContradiction) { EXPECT_FALSE(solver.reachedLimit()); } -} // namespace +REGISTER_TYPED_TEST_SUITE_P( + SolverTest, Var, NegatedVar, UnitConflict, DistinctVars, DoubleNegation, + NegatedDisjunction, NegatedConjunction, DisjunctionSameVarWithNegation, + DisjunctionSameVar, ConjunctionSameVarsConflict, ConjunctionSameVar, + PureVar, MustAssumeVarIsFalse, DeepConflict, IffIsEquivalentToDNF, + IffSameVars, IffDistinctVars, IffWithUnits, IffWithUnitsConflict, + IffTransitiveConflict, DeMorgan, RespectsAdditionalConstraints, + ImplicationIsEquivalentToDNF, ImplicationConflict, + ReachedLimitsReflectsTimeouts, SimpleButLargeContradiction); + +} // namespace clang::dataflow::test + +#endif // LLVM_CLANG_ANALYSIS_FLOW_SENSITIVE_TESTING_SUPPORT_H_ diff --git a/clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp b/clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp new file mode 100644 index 000000000000..0a2514a2d7c1 --- /dev/null +++ b/clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp @@ -0,0 +1,26 @@ +//===- unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp -----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "clang/Analysis/FlowSensitive/WatchedLiteralsSolver.h" +#include "SolverTest.h" + +namespace clang::dataflow::test { + +template <> +WatchedLiteralsSolver +SolverTest::createSolverWithLowTimeout() { + return WatchedLiteralsSolver(10); +} + +namespace { + +INSTANTIATE_TYPED_TEST_SUITE_P(WatchedLiteralsSolverTest, SolverTest, + WatchedLiteralsSolver); + +} // namespace +} // namespace clang::dataflow::test diff --git a/llvm/utils/gn/secondary/clang/unittests/Analysis/FlowSensitive/BUILD.gn b/llvm/utils/gn/secondary/clang/unittests/Analysis/FlowSensitive/BUILD.gn index df5b4587bf1c..e16ca31b81a8 100644 --- a/llvm/utils/gn/secondary/clang/unittests/Analysis/FlowSensitive/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/unittests/Analysis/FlowSensitive/BUILD.gn @@ -33,7 +33,6 @@ unittest("ClangAnalysisFlowSensitiveTests") { "SignAnalysisTest.cpp", "SimplifyConstraintsTest.cpp", "SingleVarConstantPropagationTest.cpp", - "SolverTest.cpp", "TestingSupport.cpp", "TestingSupportTest.cpp", "TransferBranchTest.cpp", @@ -41,5 +40,6 @@ unittest("ClangAnalysisFlowSensitiveTests") { "TypeErasedDataflowAnalysisTest.cpp", "UncheckedOptionalAccessModelTest.cpp", "ValueTest.cpp", + "WatchedLiteralsSolverTest.cpp", ] } -- GitLab From b5afda8d760998641cf08a6d229252924b0ad146 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 8 May 2024 15:46:11 +0200 Subject: [PATCH 031/328] AMDGPU: Add some more ctlz_zero_undef tests --- llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll | 473 ++++++++++++++++++++ 1 file changed, 473 insertions(+) diff --git a/llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll b/llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll index 21aff62b9226..54adde38d6d2 100644 --- a/llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll +++ b/llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll @@ -4,9 +4,17 @@ ; RUN: llc -mtriple=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=EG %s ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9-GISEL %s +declare i7 @llvm.ctlz.i7(i7, i1) nounwind readnone +declare <2 x i7> @llvm.ctlz.v2i7(<2 x i7>, i1) nounwind readnone declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone +declare <2 x i8> @llvm.ctlz.v2i8(<2 x i8>, i1) nounwind readnone declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone +declare i18 @llvm.ctlz.i18(i18, i1) nounwind readnone + +declare <2 x i16> @llvm.ctlz.v2i16(<2 x i16>, i1) nounwind readnone +declare <3 x i16> @llvm.ctlz.v3i16(<3 x i16>, i1) nounwind readnone +declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone @@ -2158,3 +2166,468 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_cmp_non0(ptr addrspace(1 store i32 %sel, ptr addrspace(1) %out ret void } + +define i7 @v_ctlz_zero_undef_i7(i7 %val) { +; SI-LABEL: v_ctlz_zero_undef_i7: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_and_b32_e32 v0, 0x7f, v0 +; SI-NEXT: v_ffbh_u32_e32 v0, v0 +; SI-NEXT: v_subrev_i32_e32 v0, vcc, 25, v0 +; SI-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_ctlz_zero_undef_i7: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_and_b32_e32 v0, 0x7f, v0 +; VI-NEXT: v_ffbh_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 +; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0 +; VI-NEXT: v_add_u16_e32 v0, -9, v0 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; EG-LABEL: v_ctlz_zero_undef_i7: +; EG: ; %bb.0: +; EG-NEXT: CF_END +; EG-NEXT: PAD +; +; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i7: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x7f, v0 +; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v0 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v0, 25, v0 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %ctlz = call i7 @llvm.ctlz.i7(i7 %val, i1 true) + ret i7 %ctlz +} + +define amdgpu_kernel void @s_ctlz_zero_undef_i18(ptr addrspace(1) noalias %out, i18 %val) nounwind { +; SI-LABEL: s_ctlz_zero_undef_i18: +; SI: ; %bb.0: +; SI-NEXT: s_load_dword s2, s[0:1], 0xb +; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s3, 0xf000 +; SI-NEXT: s_waitcnt lgkmcnt(0) +; SI-NEXT: s_and_b32 s2, s2, 0x3ffff +; SI-NEXT: s_flbit_i32_b32 s2, s2 +; SI-NEXT: s_add_i32 s4, s2, -14 +; SI-NEXT: s_mov_b32 s2, -1 +; SI-NEXT: v_mov_b32_e32 v0, s4 +; SI-NEXT: s_bfe_u32 s4, s4, 0x20010 +; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v0, s4 +; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:2 +; SI-NEXT: s_endpgm +; +; VI-LABEL: s_ctlz_zero_undef_i18: +; VI: ; %bb.0: +; VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_and_b32 s2, s2, 0x3ffff +; VI-NEXT: s_flbit_i32_b32 s2, s2 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: s_add_i32 s2, s2, -14 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: s_add_u32 s0, s0, 2 +; VI-NEXT: flat_store_short v[0:1], v2 +; VI-NEXT: s_addc_u32 s1, s1, 0 +; VI-NEXT: s_bfe_u32 s2, s2, 0x20010 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: flat_store_byte v[0:1], v2 +; VI-NEXT: s_endpgm +; +; EG-LABEL: s_ctlz_zero_undef_i18: +; EG: ; %bb.0: +; EG-NEXT: ALU 30, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT MSKOR T1.XW, T3.X +; EG-NEXT: MEM_RAT MSKOR T0.XW, T2.X +; EG-NEXT: CF_END +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x, +; EG-NEXT: 262143(3.673406e-40), 0(0.000000e+00) +; EG-NEXT: FFBH_UINT T0.W, PV.W, +; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x, +; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) +; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x, +; EG-NEXT: -14(nan), 0(0.000000e+00) +; EG-NEXT: AND_INT T2.W, PV.W, literal.x, +; EG-NEXT: LSHL * T1.W, T1.W, literal.y, +; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) +; EG-NEXT: LSHL T1.X, PV.W, PS, +; EG-NEXT: LSHL * T1.W, literal.x, PS, +; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) +; EG-NEXT: MOV T1.Y, 0.0, +; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: AND_INT T3.W, PV.W, literal.x, +; EG-NEXT: MOV * T4.W, literal.y, +; EG-NEXT: 3(4.203895e-45), 2(2.802597e-45) +; EG-NEXT: BFE_UINT T0.W, T0.W, literal.x, PS, +; EG-NEXT: LSHL * T3.W, PV.W, literal.y, +; EG-NEXT: 16(2.242078e-44), 3(4.203895e-45) +; EG-NEXT: LSHL T0.X, PV.W, PS, +; EG-NEXT: LSHL * T0.W, literal.x, PS, +; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) +; EG-NEXT: MOV T0.Y, 0.0, +; EG-NEXT: MOV T1.Z, 0.0, +; EG-NEXT: MOV * T0.Z, 0.0, +; EG-NEXT: LSHR T2.X, T2.W, literal.x, +; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; GFX9-GISEL-LABEL: s_ctlz_zero_undef_i18: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_and_b32 s0, s4, 0x3ffff +; GFX9-GISEL-NEXT: s_flbit_i32_b32 s0, s0 +; GFX9-GISEL-NEXT: s_sub_i32 s0, s0, 14 +; GFX9-GISEL-NEXT: s_and_b32 s0, s0, 0x3ffff +; GFX9-GISEL-NEXT: s_lshr_b32 s1, s0, 16 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-GISEL-NEXT: global_store_short v0, v1, s[2:3] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: global_store_byte v0, v1, s[2:3] offset:2 +; GFX9-GISEL-NEXT: s_endpgm + %ctlz = call i18 @llvm.ctlz.i18(i18 %val, i1 true) nounwind readnone + store i18 %ctlz, ptr addrspace(1) %out, align 4 + ret void +} + +define i18 @v_ctlz_zero_undef_i18(i18 %val) { +; SI-LABEL: v_ctlz_zero_undef_i18: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_and_b32_e32 v0, 0x3ffff, v0 +; SI-NEXT: v_ffbh_u32_e32 v0, v0 +; SI-NEXT: v_add_i32_e32 v0, vcc, -14, v0 +; SI-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_ctlz_zero_undef_i18: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_and_b32_e32 v0, 0x3ffff, v0 +; VI-NEXT: v_ffbh_u32_e32 v0, v0 +; VI-NEXT: v_add_u32_e32 v0, vcc, -14, v0 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; EG-LABEL: v_ctlz_zero_undef_i18: +; EG: ; %bb.0: +; EG-NEXT: CF_END +; EG-NEXT: PAD +; +; GFX9-GISEL-LABEL: v_ctlz_zero_undef_i18: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ffff, v0 +; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v0 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v0, 14, v0 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %ctlz = call i18 @llvm.ctlz.i18(i18 %val, i1 true) + ret i18 %ctlz +} + +define <2 x i18> @v_ctlz_zero_undef_v2i18(<2 x i18> %val) { +; SI-LABEL: v_ctlz_zero_undef_v2i18: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0x3ffff, v1 +; SI-NEXT: v_and_b32_e32 v0, 0x3ffff, v0 +; SI-NEXT: v_ffbh_u32_e32 v0, v0 +; SI-NEXT: v_ffbh_u32_e32 v1, v1 +; SI-NEXT: v_add_i32_e32 v0, vcc, -14, v0 +; SI-NEXT: v_add_i32_e32 v1, vcc, -14, v1 +; SI-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_ctlz_zero_undef_v2i18: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_and_b32_e32 v1, 0x3ffff, v1 +; VI-NEXT: v_and_b32_e32 v0, 0x3ffff, v0 +; VI-NEXT: v_ffbh_u32_e32 v0, v0 +; VI-NEXT: v_ffbh_u32_e32 v1, v1 +; VI-NEXT: v_add_u32_e32 v0, vcc, -14, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, -14, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; EG-LABEL: v_ctlz_zero_undef_v2i18: +; EG: ; %bb.0: +; EG-NEXT: CF_END +; EG-NEXT: PAD +; +; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i18: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ffff, v0 +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x3ffff, v1 +; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v0 +; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v1 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v0, 14, v0 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v1, 14, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %ctlz = call <2 x i18> @llvm.ctlz.v2i18(<2 x i18> %val, i1 true) + ret <2 x i18> %ctlz +} + +define <2 x i16> @v_ctlz_zero_undef_v2i16(<2 x i16> %val) { +; SI-LABEL: v_ctlz_zero_undef_v2i16: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; SI-NEXT: v_ffbh_u32_e32 v1, v1 +; SI-NEXT: v_ffbh_u32_e32 v0, v0 +; SI-NEXT: v_add_i32_e32 v1, vcc, -16, v1 +; SI-NEXT: v_add_i32_e32 v0, vcc, -16, v0 +; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; SI-NEXT: v_or_b32_e32 v0, v0, v2 +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; SI-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_ctlz_zero_undef_v2i16: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_ffbh_u32_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_ffbh_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 +; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0 +; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; VI-NEXT: v_add_u32_e32 v0, vcc, 0xfff00000, v0 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; EG-LABEL: v_ctlz_zero_undef_v2i16: +; EG: ; %bb.0: +; EG-NEXT: CF_END +; EG-NEXT: PAD +; +; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i16: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_ffbh_u32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v1, 16, v1 +; GFX9-GISEL-NEXT: v_ffbh_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v0, 16, v0 +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %ctlz = call <2 x i16> @llvm.ctlz.v2i16(<2 x i16> %val, i1 true) + ret <2 x i16> %ctlz +} + +define <3 x i16> @v_ctlz_zero_undef_v3i16(<3 x i16> %val) { +; SI-LABEL: v_ctlz_zero_undef_v3i16: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: v_ffbh_u32_e32 v1, v1 +; SI-NEXT: v_ffbh_u32_e32 v0, v0 +; SI-NEXT: v_ffbh_u32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_add_i32_e32 v0, vcc, -16, v0 +; SI-NEXT: v_add_i32_e32 v3, vcc, -16, v2 +; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v3 +; SI-NEXT: v_or_b32_e32 v0, v1, v0 +; SI-NEXT: v_add_i32_e32 v0, vcc, 0xfff00000, v0 +; SI-NEXT: v_or_b32_e32 v2, 0x100000, v2 +; SI-NEXT: v_alignbit_b32 v1, v3, v0, 16 +; SI-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_ctlz_zero_undef_v3i16: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_ffbh_u32_sdwa v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_ffbh_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 +; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0 +; VI-NEXT: v_ffbh_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 +; VI-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; VI-NEXT: v_add_u32_e32 v1, vcc, -16, v1 +; VI-NEXT: v_add_u32_e32 v0, vcc, 0xfff00000, v0 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; EG-LABEL: v_ctlz_zero_undef_v3i16: +; EG: ; %bb.0: +; EG-NEXT: CF_END +; EG-NEXT: PAD +; +; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v3i16: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_ffbh_u32_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v2, 16, v2 +; GFX9-GISEL-NEXT: v_ffbh_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v0, 16, v0 +; GFX9-GISEL-NEXT: v_ffbh_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 +; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v1, 16, v1 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %ctlz = call <3 x i16> @llvm.ctlz.v3i16(<3 x i16> %val, i1 true) + ret <3 x i16> %ctlz +} + +define <4 x i16> @v_ctlz_zero_undef_v4i16(<4 x i16> %val) { +; SI-LABEL: v_ctlz_zero_undef_v4i16: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; SI-NEXT: v_ffbh_u32_e32 v3, v3 +; SI-NEXT: v_ffbh_u32_e32 v2, v2 +; SI-NEXT: v_ffbh_u32_e32 v1, v1 +; SI-NEXT: v_ffbh_u32_e32 v0, v0 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_add_i32_e32 v2, vcc, -16, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_add_i32_e32 v0, vcc, -16, v0 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; SI-NEXT: v_or_b32_e32 v2, v3, v2 +; SI-NEXT: v_or_b32_e32 v0, v1, v0 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0xfff00000, v2 +; SI-NEXT: v_add_i32_e32 v0, vcc, 0xfff00000, v0 +; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16 +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; SI-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_ctlz_zero_undef_v4i16: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_ffbh_u32_sdwa v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_ffbh_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 +; VI-NEXT: v_ffbh_u32_sdwa v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_ffbh_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 +; VI-NEXT: v_add_u32_e32 v1, vcc, -16, v1 +; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0 +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; VI-NEXT: v_add_u32_e32 v0, vcc, 0xfff00000, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0xfff00000, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; EG-LABEL: v_ctlz_zero_undef_v4i16: +; EG: ; %bb.0: +; EG-NEXT: CF_END +; EG-NEXT: PAD +; +; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v4i16: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_ffbh_u32_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v2, 16, v2 +; GFX9-GISEL-NEXT: v_ffbh_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-GISEL-NEXT: v_ffbh_u32_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v0, 16, v0 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v3, 16, v3 +; GFX9-GISEL-NEXT: v_ffbh_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v1, 16, v1 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2 +; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v3 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v1, 16, v2 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %ctlz = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %val, i1 true) + ret <4 x i16> %ctlz +} + +define <2 x i8> @v_ctlz_zero_undef_v2i8(<2 x i8> %val) { +; SI-LABEL: v_ctlz_zero_undef_v2i8: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 +; SI-NEXT: v_and_b32_e32 v0, 0xff, v0 +; SI-NEXT: v_ffbh_u32_e32 v1, v1 +; SI-NEXT: v_ffbh_u32_e32 v0, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; SI-NEXT: v_subrev_i32_e32 v0, vcc, 24, v0 +; SI-NEXT: v_and_b32_e32 v0, 0xff, v0 +; SI-NEXT: v_or_b32_e32 v0, v1, v0 +; SI-NEXT: v_add_i32_e32 v0, vcc, 0xffffe800, v0 +; SI-NEXT: v_bfe_u32 v1, v0, 8, 8 +; SI-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_ctlz_zero_undef_v2i8: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_ffbh_u32_sdwa v1, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 +; VI-NEXT: v_ffbh_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 +; VI-NEXT: v_add_u16_e32 v1, 0xe800, v1 +; VI-NEXT: v_subrev_u16_e32 v0, 24, v0 +; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshrrev_b16_e32 v1, 8, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; EG-LABEL: v_ctlz_zero_undef_v2i8: +; EG: ; %bb.0: +; EG-NEXT: CF_END +; EG-NEXT: PAD +; +; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i8: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_ffbh_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 +; GFX9-GISEL-NEXT: v_ffbh_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v0, 24, v0 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v1, 24, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %ctlz = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> %val, i1 true) + ret <2 x i8> %ctlz +} + +define <2 x i7> @v_ctlz_zero_undef_v2i7(<2 x i7> %val) { +; SI-LABEL: v_ctlz_zero_undef_v2i7: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0x7f, v1 +; SI-NEXT: v_and_b32_e32 v0, 0x7f, v0 +; SI-NEXT: v_ffbh_u32_e32 v0, v0 +; SI-NEXT: v_ffbh_u32_e32 v1, v1 +; SI-NEXT: v_subrev_i32_e32 v0, vcc, 25, v0 +; SI-NEXT: v_subrev_i32_e32 v1, vcc, 25, v1 +; SI-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_ctlz_zero_undef_v2i7: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_and_b32_e32 v2, 0x7f007f, v0 +; VI-NEXT: v_bfe_u32 v0, v0, 16, 7 +; VI-NEXT: v_ffbh_u32_e32 v0, v0 +; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0 +; VI-NEXT: v_add_u16_e32 v1, -9, v0 +; VI-NEXT: v_and_b32_e32 v0, 0x7f, v2 +; VI-NEXT: v_ffbh_u32_e32 v0, v0 +; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0 +; VI-NEXT: v_add_u16_e32 v0, -9, v0 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; EG-LABEL: v_ctlz_zero_undef_v2i7: +; EG: ; %bb.0: +; EG-NEXT: CF_END +; EG-NEXT: PAD +; +; GFX9-GISEL-LABEL: v_ctlz_zero_undef_v2i7: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x7f, v0 +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x7f, v1 +; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v0, v0 +; GFX9-GISEL-NEXT: v_ffbh_u32_e32 v1, v1 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v0, 25, v0 +; GFX9-GISEL-NEXT: v_subrev_u32_e32 v1, 25, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %ctlz = call <2 x i7> @llvm.ctlz.v2i7(<2 x i7> %val, i1 true) + ret <2 x i7> %ctlz +} -- GitLab From 27a062e9ca7c92e89ed4084c3c3affb9fa39aabb Mon Sep 17 00:00:00 2001 From: serge-sans-paille Date: Wed, 8 May 2024 14:21:31 +0000 Subject: [PATCH 032/328] [libc++] Implement std::gcd using the binary version (#77747) The binary version is four times faster than current implementation in my setup, and generally considered a better implementation. Code inspired by https://en.algorithmica.org/hpc/algorithms/gcd/ which itself is inspired by https://lemire.me/blog/2013/12/26/fastest-way-to-compute-the-greatest-common-divisor/ Fix #77648 --- libcxx/benchmarks/CMakeLists.txt | 3 +- libcxx/benchmarks/numeric/gcd.bench.cpp | 53 +++++++++++ libcxx/include/__numeric/gcd_lcm.h | 44 ++++++++- .../test/libcxx/transitive_includes/cxx03.csv | 1 + .../test/libcxx/transitive_includes/cxx11.csv | 1 + .../test/libcxx/transitive_includes/cxx14.csv | 1 + .../test/libcxx/transitive_includes/cxx17.csv | 1 + .../test/libcxx/transitive_includes/cxx20.csv | 1 + .../test/libcxx/transitive_includes/cxx26.csv | 23 +++++ .../numeric.ops/numeric.ops.gcd/gcd.pass.cpp | 89 ++++++++++++++++++- 10 files changed, 213 insertions(+), 4 deletions(-) create mode 100644 libcxx/benchmarks/numeric/gcd.bench.cpp diff --git a/libcxx/benchmarks/CMakeLists.txt b/libcxx/benchmarks/CMakeLists.txt index 5dc3be0c367e..93b549a316e3 100644 --- a/libcxx/benchmarks/CMakeLists.txt +++ b/libcxx/benchmarks/CMakeLists.txt @@ -122,7 +122,7 @@ endif() add_library( cxx-benchmarks-flags-libcxx INTERFACE) target_link_libraries( cxx-benchmarks-flags-libcxx INTERFACE cxx-benchmarks-flags) target_compile_options(cxx-benchmarks-flags-libcxx INTERFACE ${SANITIZER_FLAGS} -Wno-user-defined-literals -Wno-suggest-override) -target_link_options( cxx-benchmarks-flags-libcxx INTERFACE -nostdlib++ "-L${BENCHMARK_LIBCXX_INSTALL}/lib" "-L${BENCHMARK_LIBCXX_INSTALL}/lib64" ${SANITIZER_FLAGS}) +target_link_options( cxx-benchmarks-flags-libcxx INTERFACE -lm -nostdlib++ "-L${BENCHMARK_LIBCXX_INSTALL}/lib" "-L${BENCHMARK_LIBCXX_INSTALL}/lib64" ${SANITIZER_FLAGS}) set(libcxx_benchmark_targets) @@ -220,6 +220,7 @@ set(BENCHMARK_TESTS lexicographical_compare_three_way.bench.cpp map.bench.cpp monotonic_buffer.bench.cpp + numeric/gcd.bench.cpp ordered_set.bench.cpp shared_mutex_vs_mutex.bench.cpp stop_token.bench.cpp diff --git a/libcxx/benchmarks/numeric/gcd.bench.cpp b/libcxx/benchmarks/numeric/gcd.bench.cpp new file mode 100644 index 000000000000..f8b6a856cd0d --- /dev/null +++ b/libcxx/benchmarks/numeric/gcd.bench.cpp @@ -0,0 +1,53 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include +#include +#include +#include + +template +static std::array generate(std::uniform_int_distribution distribution = std::uniform_int_distribution{ + std::numeric_limits::min() + 1, std::numeric_limits::max()}) { + std::mt19937 generator; + std::array result; + std::generate_n(result.begin(), result.size(), [&] { return distribution(generator); }); + return result; +} + +static void bm_gcd_random(benchmark::State& state) { + std::array data = generate(); + while (state.KeepRunningBatch(data.size())) + for (auto v0 : data) + for (auto v1 : data) + benchmark::DoNotOptimize(std::gcd(v0, v1)); +} +BENCHMARK(bm_gcd_random); + +static void bm_gcd_trivial(benchmark::State& state) { + int lhs = ~static_cast(0), rhs = 1; + for (auto _ : state) { + benchmark::DoNotOptimize(lhs); + benchmark::DoNotOptimize(rhs); + benchmark::DoNotOptimize(std::gcd(lhs, rhs)); + } +} +BENCHMARK(bm_gcd_trivial); + +static void bm_gcd_complex(benchmark::State& state) { + int lhs = 2971215073, rhs = 1836311903; + for (auto _ : state) { + benchmark::DoNotOptimize(lhs); + benchmark::DoNotOptimize(rhs); + benchmark::DoNotOptimize(std::gcd(lhs, rhs)); + } +} +BENCHMARK(bm_gcd_complex); + +BENCHMARK_MAIN(); diff --git a/libcxx/include/__numeric/gcd_lcm.h b/libcxx/include/__numeric/gcd_lcm.h index 48df2338051e..5d735a51a47e 100644 --- a/libcxx/include/__numeric/gcd_lcm.h +++ b/libcxx/include/__numeric/gcd_lcm.h @@ -10,7 +10,9 @@ #ifndef _LIBCPP___NUMERIC_GCD_LCM_H #define _LIBCPP___NUMERIC_GCD_LCM_H +#include <__algorithm/min.h> #include <__assert> +#include <__bit/countr.h> #include <__config> #include <__type_traits/common_type.h> #include <__type_traits/is_integral.h> @@ -50,9 +52,47 @@ struct __ct_abs<_Result, _Source, false> { }; template -_LIBCPP_CONSTEXPR _LIBCPP_HIDDEN _Tp __gcd(_Tp __m, _Tp __n) { +_LIBCPP_CONSTEXPR _LIBCPP_HIDDEN _Tp __gcd(_Tp __a, _Tp __b) { static_assert((!is_signed<_Tp>::value), ""); - return __n == 0 ? __m : std::__gcd<_Tp>(__n, __m % __n); + + // From: https://lemire.me/blog/2013/12/26/fastest-way-to-compute-the-greatest-common-divisor + // + // If power of two divides both numbers, we can push it out. + // - gcd( 2^x * a, 2^x * b) = 2^x * gcd(a, b) + // + // If and only if exactly one number is even, we can divide that number by that power. + // - if a, b are odd, then gcd(2^x * a, b) = gcd(a, b) + // + // And standard gcd algorithm where instead of modulo, minus is used. + + if (__a < __b) { + _Tp __tmp = __b; + __b = __a; + __a = __tmp; + } + if (__b == 0) + return __a; + __a %= __b; // Make both argument of the same size, and early result in the easy case. + if (__a == 0) + return __b; + + int __az = std::__countr_zero(__a); + int __bz = std::__countr_zero(__b); + int __shift = std::min(__az, __bz); + __a >>= __az; + __b >>= __bz; + do { + _Tp __diff = __a - __b; + if (__a > __b) { + __a = __b; + __b = __diff; + } else { + __b = __b - __a; + } + if (__diff != 0) + __b >>= std::__countr_zero(__diff); + } while (__b != 0); + return __a << __shift; } template diff --git a/libcxx/test/libcxx/transitive_includes/cxx03.csv b/libcxx/test/libcxx/transitive_includes/cxx03.csv index cf0af3b8bb39..92601fab5b77 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx03.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx03.csv @@ -570,6 +570,7 @@ numeric cstddef numeric cstdint numeric execution numeric functional +numeric initializer_list numeric iterator numeric limits numeric new diff --git a/libcxx/test/libcxx/transitive_includes/cxx11.csv b/libcxx/test/libcxx/transitive_includes/cxx11.csv index f514ee3028f6..c05eb42deb9a 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx11.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx11.csv @@ -575,6 +575,7 @@ numeric cstddef numeric cstdint numeric execution numeric functional +numeric initializer_list numeric iterator numeric limits numeric new diff --git a/libcxx/test/libcxx/transitive_includes/cxx14.csv b/libcxx/test/libcxx/transitive_includes/cxx14.csv index 43e3f996adba..09252b7b7d2d 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx14.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx14.csv @@ -578,6 +578,7 @@ numeric cstddef numeric cstdint numeric execution numeric functional +numeric initializer_list numeric iterator numeric limits numeric new diff --git a/libcxx/test/libcxx/transitive_includes/cxx17.csv b/libcxx/test/libcxx/transitive_includes/cxx17.csv index 43e3f996adba..09252b7b7d2d 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx17.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx17.csv @@ -578,6 +578,7 @@ numeric cstddef numeric cstdint numeric execution numeric functional +numeric initializer_list numeric iterator numeric limits numeric new diff --git a/libcxx/test/libcxx/transitive_includes/cxx20.csv b/libcxx/test/libcxx/transitive_includes/cxx20.csv index 8463f17db411..ce4ccc3d1161 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx20.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx20.csv @@ -589,6 +589,7 @@ numeric cstddef numeric cstdint numeric execution numeric functional +numeric initializer_list numeric iterator numeric limits numeric new diff --git a/libcxx/test/libcxx/transitive_includes/cxx26.csv b/libcxx/test/libcxx/transitive_includes/cxx26.csv index 62d931c0eeba..f68249aeec78 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx26.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx26.csv @@ -176,6 +176,29 @@ experimental/simd limits experimental/type_traits initializer_list experimental/type_traits type_traits experimental/utility utility +experimental/vector experimental/memory_resource +experimental/vector vector +ext/hash_map algorithm +ext/hash_map cmath +ext/hash_map cstddef +ext/hash_map cstdint +ext/hash_map cstring +ext/hash_map functional +ext/hash_map initializer_list +ext/hash_map limits +ext/hash_map new +ext/hash_map stdexcept +ext/hash_map string +ext/hash_set algorithm +ext/hash_set cmath +ext/hash_set cstddef +ext/hash_set cstdint +ext/hash_set cstring +ext/hash_set functional +ext/hash_set initializer_list +ext/hash_set limits +ext/hash_set new +ext/hash_set string filesystem compare filesystem cstddef filesystem cstdint diff --git a/libcxx/test/std/numerics/numeric.ops/numeric.ops.gcd/gcd.pass.cpp b/libcxx/test/std/numerics/numeric.ops/numeric.ops.gcd/gcd.pass.cpp index 831c226f9c8e..212804356a05 100644 --- a/libcxx/test/std/numerics/numeric.ops/numeric.ops.gcd/gcd.pass.cpp +++ b/libcxx/test/std/numerics/numeric.ops/numeric.ops.gcd/gcd.pass.cpp @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "test_macros.h" @@ -48,6 +49,74 @@ constexpr bool test0(int in1, int in2, int out) return true; } +template +T basic_gcd_(T m, T n) { + return n == 0 ? m : basic_gcd_(n, m % n); +} + +template +T basic_gcd(T m, T n) { + using Tp = std::make_unsigned_t; + if (m < 0 && m != std::numeric_limits::min()) + m = -m; + if (n < 0 && n != std::numeric_limits::min()) + n = -n; + return basic_gcd_(static_cast(m), static_cast(n)); +} + +template +void do_fuzzy_tests() { + std::mt19937 gen(1938); + std::uniform_int_distribution distrib; + + constexpr int nb_rounds = 10000; + for (int i = 0; i < nb_rounds; ++i) { + Input n = distrib(gen); + Input m = distrib(gen); + assert(std::gcd(n, m) == basic_gcd(n, m)); + } +} + +template +void do_limit_tests() { + Input inputs[] = { + // The behavior of std::gcd is undefined if the absolute value of one of its + // operand is not representable in the result type. + std::numeric_limits::min() + (std::is_signed::value ? 3 : 0), + std::numeric_limits::min() + 1, + std::numeric_limits::min() + 2, + std::numeric_limits::max(), + std::numeric_limits::max() - 1, + std::numeric_limits::max() - 2, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + (Input)-1, + (Input)-2, + (Input)-3, + (Input)-4, + (Input)-5, + (Input)-6, + (Input)-7, + (Input)-8, + (Input)-9, + (Input)-10, + }; + + for (auto n : inputs) { + for (auto m : inputs) { + assert(std::gcd(n, m) == basic_gcd(n, m)); + } + } +} template constexpr bool do_test(int = 0) @@ -143,5 +212,23 @@ int main(int argc, char**) assert(res == 2); } - return 0; + do_fuzzy_tests(); + do_fuzzy_tests(); + do_fuzzy_tests(); + do_fuzzy_tests(); + do_fuzzy_tests(); + do_fuzzy_tests(); + do_fuzzy_tests(); + do_fuzzy_tests(); + + do_limit_tests(); + do_limit_tests(); + do_limit_tests(); + do_limit_tests(); + do_limit_tests(); + do_limit_tests(); + do_limit_tests(); + do_limit_tests(); + + return 0; } -- GitLab From 73bb8d9d92f689863c94d48517e89d35dae0ebcf Mon Sep 17 00:00:00 2001 From: Jonathan Peyton Date: Wed, 8 May 2024 09:23:50 -0500 Subject: [PATCH 033/328] [OpenMP] Fix child processes to use affinity_none (#91391) When a child process is forked with OpenMP already initialized, the child process resets its affinity mask and sets proc-bind-var to false so that the entire original affinity mask is used. This patch corrects an issue with the affinity initialization code setting affinity to compact instead of none for this special case of forked children. The test trying to catch this only testing explicit setting of KMP_AFFINITY=none. Add test run for no KMP_AFFINITY setting. Fixes: #91098 --- openmp/runtime/src/kmp_settings.cpp | 2 ++ openmp/runtime/test/affinity/redetect.c | 1 + 2 files changed, 3 insertions(+) diff --git a/openmp/runtime/src/kmp_settings.cpp b/openmp/runtime/src/kmp_settings.cpp index b9c8289b5c51..8b6092cb1085 100644 --- a/openmp/runtime/src/kmp_settings.cpp +++ b/openmp/runtime/src/kmp_settings.cpp @@ -6420,6 +6420,8 @@ void __kmp_env_initialize(char const *string) { } if ((__kmp_nested_proc_bind.bind_types[0] != proc_bind_intel) && (__kmp_nested_proc_bind.bind_types[0] != proc_bind_default)) { + if (__kmp_nested_proc_bind.bind_types[0] == proc_bind_false) + __kmp_affinity.type = affinity_none; if (__kmp_affinity.type == affinity_default) { __kmp_affinity.type = affinity_compact; __kmp_affinity.flags.dups = FALSE; diff --git a/openmp/runtime/test/affinity/redetect.c b/openmp/runtime/test/affinity/redetect.c index dba83b72cc42..4b96d1bd92ee 100644 --- a/openmp/runtime/test/affinity/redetect.c +++ b/openmp/runtime/test/affinity/redetect.c @@ -1,4 +1,5 @@ // RUN: %libomp-compile +// RUN: %libomp-run // RUN: env KMP_AFFINITY=none %libomp-run // REQUIRES: linux -- GitLab From 6ed8434edc5934210a38be99f33b6baed83df85c Mon Sep 17 00:00:00 2001 From: Prathamesh Tagore <63031630+meshtag@users.noreply.github.com> Date: Wed, 8 May 2024 19:54:43 +0530 Subject: [PATCH 034/328] [mlir][fold-memref-alias-ops] Add support for folding memref.expand_shape involving dynamic dims (#89093) `fold-memref-alias-ops` bails out in presence of dynamic shapes in `memref.expand_shape` op. Handle this case. --- .../mlir/Dialect/MemRef/Utils/MemRefUtils.h | 29 +++++++ .../MemRef/Transforms/FoldMemRefAliasOps.cpp | 85 ++++++++++++++----- mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp | 23 +++++ .../Dialect/MemRef/fold-memref-alias-ops.mlir | 81 +++++++++++++----- 4 files changed, 180 insertions(+), 38 deletions(-) diff --git a/mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h b/mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h index 7d9a5e6ca759..46003ed84686 100644 --- a/mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h +++ b/mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h @@ -64,6 +64,35 @@ getLinearizedMemRefOffsetAndSize(OpBuilder &builder, Location loc, int srcBits, // it means both the allocations and associated stores can be removed. void eraseDeadAllocAndStores(RewriterBase &rewriter, Operation *parentOp); +/// Given a set of sizes, return the suffix product. +/// +/// When applied to slicing, this is the calculation needed to derive the +/// strides (i.e. the number of linear indices to skip along the (k-1) most +/// minor dimensions to get the next k-slice). +/// +/// This is the basis to linearize an n-D offset confined to `[0 ... sizes]`. +/// +/// Assuming `sizes` is `[s0, .. sn]`, return the vector +/// `[s1 * ... * sn, s2 * ... * sn, ..., sn, 1]`. +/// +/// It is the caller's responsibility to provide valid OpFoldResult type values +/// and construct valid IR in the end. +/// +/// `sizes` elements are asserted to be non-negative. +/// +/// Return an empty vector if `sizes` is empty. +/// +/// The function emits an IR block which computes suffix product for provided +/// sizes. +SmallVector +computeSuffixProductIRBlock(Location loc, OpBuilder &builder, + ArrayRef sizes); +inline SmallVector +computeStridesIRBlock(Location loc, OpBuilder &builder, + ArrayRef sizes) { + return computeSuffixProductIRBlock(loc, builder, sizes); +} + } // namespace memref } // namespace mlir diff --git a/mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp b/mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp index aa44455ada7f..29a5bc9a7ae5 100644 --- a/mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp +++ b/mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp @@ -19,6 +19,7 @@ #include "mlir/Dialect/MemRef/IR/MemRef.h" #include "mlir/Dialect/MemRef/Transforms/Passes.h" #include "mlir/Dialect/MemRef/Transforms/Transforms.h" +#include "mlir/Dialect/MemRef/Utils/MemRefUtils.h" #include "mlir/Dialect/NVGPU/IR/NVGPUDialect.h" #include "mlir/Dialect/Utils/IndexingUtils.h" #include "mlir/Dialect/Vector/IR/VectorOps.h" @@ -63,39 +64,85 @@ resolveSourceIndicesExpandShape(Location loc, PatternRewriter &rewriter, memref::ExpandShapeOp expandShapeOp, ValueRange indices, SmallVectorImpl &sourceIndices) { - // The below implementation uses computeSuffixProduct method, which only - // allows int64_t values (i.e., static shape). Bail out if it has dynamic - // shapes. - if (!expandShapeOp.getResultType().hasStaticShape()) + // Record the rewriter context for constructing ops later. + MLIRContext *ctx = rewriter.getContext(); + + // Capture expand_shape's input dimensions as `SmallVector`. + // This is done for the purpose of inferring the output shape via + // `inferExpandOutputShape` which will in turn be used for suffix product + // calculation later. + SmallVector srcShape; + MemRefType srcType = expandShapeOp.getSrcType(); + + for (int64_t i = 0, e = srcType.getRank(); i < e; ++i) { + if (srcType.isDynamicDim(i)) { + srcShape.push_back( + rewriter.create(loc, expandShapeOp.getSrc(), i) + .getResult()); + } else { + srcShape.push_back(rewriter.getIndexAttr(srcType.getShape()[i])); + } + } + + auto outputShape = inferExpandShapeOutputShape( + rewriter, loc, expandShapeOp.getResultType(), + expandShapeOp.getReassociationIndices(), srcShape); + if (!outputShape.has_value()) return failure(); - MLIRContext *ctx = rewriter.getContext(); + // Traverse all reassociation groups to determine the appropriate indices + // corresponding to each one of them post op folding. for (ArrayRef groups : expandShapeOp.getReassociationIndices()) { assert(!groups.empty() && "association indices groups cannot be empty"); + // Flag to indicate the presence of dynamic dimensions in current + // reassociation group. int64_t groupSize = groups.size(); - // Construct the expression for the index value w.r.t to expand shape op - // source corresponding the indices wrt to expand shape op result. - SmallVector sizes(groupSize); - for (int64_t i = 0; i < groupSize; ++i) - sizes[i] = expandShapeOp.getResultType().getDimSize(groups[i]); - SmallVector suffixProduct = computeSuffixProduct(sizes); - SmallVector dims(groupSize); - bindDimsList(ctx, MutableArrayRef{dims}); - AffineExpr srcIndexExpr = linearize(ctx, dims, suffixProduct); + // Group output dimensions utilized in this reassociation group for suffix + // product calculation. + SmallVector sizesVal(groupSize); + for (int64_t i = 0; i < groupSize; ++i) { + sizesVal[i] = (*outputShape)[groups[i]]; + } + + // Calculate suffix product of relevant output dimension sizes. + SmallVector suffixProduct = + memref::computeSuffixProductIRBlock(loc, rewriter, sizesVal); + + // Create affine expression variables for dimensions and symbols in the + // newly constructed affine map. + SmallVector dims(groupSize), symbols(groupSize); + bindDimsList(ctx, dims); + bindSymbolsList(ctx, symbols); - /// Apply permutation and create AffineApplyOp. + // Linearize binded dimensions and symbols to construct the resultant + // affine expression for this indice. + AffineExpr srcIndexExpr = linearize(ctx, dims, symbols); + + // Record the load index corresponding to each dimension in the + // reassociation group. These are later supplied as operands to the affine + // map used for calulating relevant index post op folding. SmallVector dynamicIndices(groupSize); for (int64_t i = 0; i < groupSize; i++) dynamicIndices[i] = indices[groups[i]]; - // Creating maximally folded and composd affine.apply composes better with - // other transformations without interleaving canonicalization passes. + // Supply suffix product results followed by load op indices as operands + // to the map. + SmallVector mapOperands; + llvm::append_range(mapOperands, suffixProduct); + llvm::append_range(mapOperands, dynamicIndices); + + // Creating maximally folded and composed affine.apply composes better + // with other transformations without interleaving canonicalization + // passes. OpFoldResult ofr = affine::makeComposedFoldedAffineApply( rewriter, loc, AffineMap::get(/*numDims=*/groupSize, - /*numSymbols=*/0, srcIndexExpr), - dynamicIndices); + /*numSymbols=*/groupSize, /*expression=*/srcIndexExpr), + mapOperands); + + // Push index value in the op post folding corresponding to this + // reassociation group. sourceIndices.push_back( getValueOrCreateConstantIndexOp(rewriter, loc, ofr)); } diff --git a/mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp b/mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp index 556a82de2166..c93e5a9dcd39 100644 --- a/mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp +++ b/mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp @@ -15,6 +15,7 @@ #include "mlir/Dialect/Arith/Utils/Utils.h" #include "mlir/Dialect/MemRef/IR/MemRef.h" #include "mlir/Dialect/Vector/IR/VectorOps.h" +#include "llvm/ADT/STLExtras.h" namespace mlir { namespace memref { @@ -155,5 +156,27 @@ void eraseDeadAllocAndStores(RewriterBase &rewriter, Operation *parentOp) { rewriter.eraseOp(op); } +static SmallVector +computeSuffixProductIRBlockImpl(Location loc, OpBuilder &builder, + ArrayRef sizes, + OpFoldResult unit) { + SmallVector strides(sizes.size(), unit); + AffineExpr s0, s1; + bindSymbols(builder.getContext(), s0, s1); + + for (int64_t r = strides.size() - 1; r > 0; --r) { + strides[r - 1] = affine::makeComposedFoldedAffineApply( + builder, loc, s0 * s1, {strides[r], sizes[r]}); + } + return strides; +} + +SmallVector +computeSuffixProductIRBlock(Location loc, OpBuilder &builder, + ArrayRef sizes) { + OpFoldResult unit = builder.getIndexAttr(1); + return computeSuffixProductIRBlockImpl(loc, builder, sizes, unit); +} + } // namespace memref } // namespace mlir diff --git a/mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir b/mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir index 254cd4015eed..99b5f78b03fb 100644 --- a/mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir +++ b/mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir @@ -468,23 +468,66 @@ func.func @fold_static_stride_subview_with_affine_load_store_expand_shape_3d(%ar // ----- -// CHECK-LABEL: fold_dynamic_subview_with_memref_load_store_expand_shape -// CHECK-SAME: (%[[ARG0:.*]]: memref<16x?xf32, strided<[16, 1]>>, %[[ARG1:.*]]: index, %[[ARG2:.*]]: index, %[[SZ0:.*]]: index) -func.func @fold_dynamic_subview_with_memref_load_store_expand_shape(%arg0 : memref<16x?xf32, strided<[16, 1]>>, %arg1 : index, %arg2 : index, %sz0: index) -> f32 { +// CHECK-LABEL: fold_dynamic_subview_with_memref_load_expand_shape +// CHECK-SAME: (%[[ARG0:.*]]: memref<16x?xf32, strided<[16, 1]>>, %[[ARG1:.*]]: index, %[[ARG2:.*]]: index, %[[ARG3:.*]]: index) -> f32 +func.func @fold_dynamic_subview_with_memref_load_expand_shape(%arg0 : memref<16x?xf32, strided<[16, 1]>>, %arg1 : index, %arg2 : index, %sz0: index) -> f32 { %c0 = arith.constant 0 : index %expand_shape = memref.expand_shape %arg0 [[0, 1], [2, 3]] output_shape [1, 16, %sz0, 1] : memref<16x?xf32, strided<[16, 1]>> into memref<1x16x?x1xf32, strided<[256, 16, 1, 1]>> %0 = memref.load %expand_shape[%c0, %arg1, %arg2, %c0] : memref<1x16x?x1xf32, strided<[256, 16, 1, 1]>> return %0 : f32 } -// CHECK: %[[C0:.*]] = arith.constant 0 : index -// CHECK: %[[EXPAND_SHAPE:.*]] = memref.expand_shape %[[ARG0]] {{\[\[}}0, 1], [2, 3]] output_shape [1, 16, %[[SZ0]], 1] : memref<16x?xf32, strided<[16, 1]>> into memref<1x16x?x1xf32, strided<[256, 16, 1, 1]>> -// CHECK: %[[VAL_0:.*]] = memref.load %[[EXPAND_SHAPE]][%[[C0]], %[[ARG1]], %[[ARG2]], %[[C0]]] : memref<1x16x?x1xf32, strided<[256, 16, 1, 1]>> -// CHECK: return %[[VAL_0]] : f32 +// CHECK-NEXT: %[[VAL1:.*]] = memref.load %[[ARG0]][%[[ARG1]], %[[ARG2]]] : memref<16x?xf32, strided<[16, 1]>> +// CHECK-NEXT: return %[[VAL1]] : f32 // ----- -// CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1) -> (d0 * 1024 + d1)> -// CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1) -> (d0 + d1)> +// CHECK-LABEL: fold_dynamic_subview_with_memref_store_expand_shape +// CHECK-SAME: (%[[ARG0:.*]]: memref<16x?xf32, strided<[16, 1]>>, %[[ARG1:.*]]: index, %[[ARG2:.*]]: index, %[[ARG3:.*]]: index) +func.func @fold_dynamic_subview_with_memref_store_expand_shape(%arg0 : memref<16x?xf32, strided<[16, 1]>>, %arg1 : index, %arg2 : index, %sz0 : index) { + %c0 = arith.constant 0 : index + %c1f32 = arith.constant 1.0 : f32 + %expand_shape = memref.expand_shape %arg0 [[0, 1], [2, 3]] output_shape [1, 16, %sz0, 1] : memref<16x?xf32, strided<[16, 1]>> into memref<1x16x?x1xf32, strided<[256, 16, 1, 1]>> + memref.store %c1f32, %expand_shape[%c0, %arg1, %arg2, %c0] : memref<1x16x?x1xf32, strided<[256, 16, 1, 1]>> + return +} +// CHECK: %[[C1F32:.*]] = arith.constant 1.000000e+00 : f32 +// CHECK-NEXT: memref.store %[[C1F32]], %[[ARG0]][%[[ARG1]], %[[ARG2]]] : memref<16x?xf32, strided<[16, 1]>> +// CHECK-NEXT: return + +// ----- + +// CHECK-DAG: #[[$MAP0:.*]] = affine_map<()[s0, s1] -> (s0 + s1)> +// CHECK-DAG: #[[$MAP1:.*]] = affine_map<()[s0] -> (s0 * 3)> +// CHECK-LABEL: fold_memref_alias_expand_shape_subview_load_store_dynamic_dim +// CHECK-SAME: (%[[ARG0:.*]]: memref<2048x16xf32>, %[[ARG1:.*]]: index, %[[ARG2:.*]]: index, %[[ARG3:.*]]: index, %[[ARG4:.*]]: index) +func.func @fold_memref_alias_expand_shape_subview_load_store_dynamic_dim(%alloc: memref<2048x16xf32>, %c10: index, %c5: index, %c0: index, %sz0: index) { + %subview = memref.subview %alloc[%c5, 0] [%c10, 16] [1, 1] : memref<2048x16xf32> to memref> + %expand_shape = memref.expand_shape %subview [[0], [1, 2, 3]] output_shape [1, 16, %sz0, 1] : memref> into memref> + %dim = memref.dim %expand_shape, %c0 : memref> + + affine.for %arg6 = 0 to %dim step 64 { + affine.for %arg7 = 0 to 16 step 16 { + %dummy_load = affine.load %expand_shape[%arg6, 0, %arg7, %arg7] : memref> + affine.store %dummy_load, %subview[%arg6, %arg7] : memref> + } + } + return +} +// CHECK-NEXT: memref.subview +// CHECK-NEXT: %[[EXPAND_SHAPE:.*]] = memref.expand_shape +// CHECK-NEXT: %[[DIM:.*]] = memref.dim %[[EXPAND_SHAPE]], %[[ARG3]] : memref> +// CHECK-NEXT: affine.for %[[ARG4:.*]] = 0 to %[[DIM]] step 64 { +// CHECK-NEXT: affine.for %[[ARG5:.*]] = 0 to 16 step 16 { +// CHECK-NEXT: %[[VAL0:.*]] = affine.apply #[[$MAP0]]()[%[[ARG2]], %[[ARG4]]] +// CHECK-NEXT: %[[VAL1:.*]] = affine.apply #[[$MAP1]]()[%[[ARG5]]] +// CHECK-NEXT: %[[VAL2:.*]] = affine.load %[[ARG0]][%[[VAL0]], %[[VAL1]]] : memref<2048x16xf32> +// CHECK-NEXT: %[[VAL3:.*]] = affine.apply #[[$MAP0]]()[%[[ARG2]], %[[ARG4]]] +// CHECK-NEXT: affine.store %[[VAL2]], %[[ARG0]][%[[VAL3]], %[[ARG5]]] : memref<2048x16xf32> + +// ----- + +// CHECK-DAG: #[[$MAP0:.*]] = affine_map<()[s0, s1] -> (s0 * 1024 + s1)> +// CHECK-DAG: #[[$MAP1:.*]] = affine_map<()[s0, s1] -> (s0 + s1)> // CHECK-LABEL: fold_static_stride_subview_with_affine_load_store_expand_shape // CHECK-SAME: (%[[ARG0:.*]]: memref<1024x1024xf32>, %[[ARG1:.*]]: memref<1xf32>, %[[ARG2:.*]]: index) func.func @fold_static_stride_subview_with_affine_load_store_expand_shape(%arg0: memref<1024x1024xf32>, %arg1: memref<1xf32>, %arg2: index) -> f32 { @@ -506,14 +549,14 @@ func.func @fold_static_stride_subview_with_affine_load_store_expand_shape(%arg0: // CHECK-NEXT: affine.for %[[ARG4:.*]] = 0 to 1024 { // CHECK-NEXT: affine.for %[[ARG5:.*]] = 0 to 1020 { // CHECK-NEXT: affine.for %[[ARG6:.*]] = 0 to 1 { -// CHECK-NEXT: %[[IDX1:.*]] = affine.apply #[[$MAP0]](%[[ARG3]], %[[ARG4]]) -// CHECK-NEXT: %[[IDX2:.*]] = affine.apply #[[$MAP1]](%[[ARG5]], %[[ARG6]]) +// CHECK-NEXT: %[[IDX1:.*]] = affine.apply #[[$MAP0]]()[%[[ARG3]], %[[ARG4]]] +// CHECK-NEXT: %[[IDX2:.*]] = affine.apply #[[$MAP1]]()[%[[ARG5]], %[[ARG6]]] // CHECK-NEXT: affine.load %[[ARG0]][%[[IDX1]], %[[IDX2]]] : memref<1024x1024xf32> // ----- -// CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1) -> (d0 * 1025 + d1)> -// CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1) -> (d0 + d1)> +// CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1)[s0] -> (d0 + d1 + s0 * 1024)> +// CHECK-DAG: #[[$MAP1:.*]] = affine_map<()[s0, s1] -> (s0 + s1)> // CHECK-LABEL: fold_static_stride_subview_with_affine_load_store_expand_shape_when_access_index_is_an_expression // CHECK-SAME: (%[[ARG0:.*]]: memref<1024x1024xf32>, %[[ARG1:.*]]: memref<1xf32>, %[[ARG2:.*]]: index) func.func @fold_static_stride_subview_with_affine_load_store_expand_shape_when_access_index_is_an_expression(%arg0: memref<1024x1024xf32>, %arg1: memref<1xf32>, %arg2: index) -> f32 { @@ -535,14 +578,14 @@ func.func @fold_static_stride_subview_with_affine_load_store_expand_shape_when_a // CHECK-NEXT: affine.for %[[ARG4:.*]] = 0 to 1024 { // CHECK-NEXT: affine.for %[[ARG5:.*]] = 0 to 1020 { // CHECK-NEXT: affine.for %[[ARG6:.*]] = 0 to 1 { -// CHECK-NEXT: %[[TMP1:.*]] = affine.apply #[[$MAP0]](%[[ARG3]], %[[ARG4]]) -// CHECK-NEXT: %[[TMP3:.*]] = affine.apply #[[$MAP1]](%[[ARG5]], %[[ARG6]]) +// CHECK-NEXT: %[[TMP1:.*]] = affine.apply #[[$MAP0]](%[[ARG3]], %[[ARG4]])[%[[ARG3]]] +// CHECK-NEXT: %[[TMP3:.*]] = affine.apply #[[$MAP1]]()[%[[ARG5]], %[[ARG6]]] // CHECK-NEXT: affine.load %[[ARG0]][%[[TMP1]], %[[TMP3]]] : memref<1024x1024xf32> // ----- -// CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0) -> (d0 * 1024)> -// CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1) -> (d0 + d1)> +// CHECK-DAG: #[[$MAP0:.*]] = affine_map<()[s0] -> (s0 * 1024)> +// CHECK-DAG: #[[$MAP1:.*]] = affine_map<()[s0, s1] -> (s0 + s1)> // CHECK-LABEL: fold_static_stride_subview_with_affine_load_store_expand_shape_with_constant_access_index // CHECK-SAME: (%[[ARG0:.*]]: memref<1024x1024xf32>, %[[ARG1:.*]]: memref<1xf32>, %[[ARG2:.*]]: index) func.func @fold_static_stride_subview_with_affine_load_store_expand_shape_with_constant_access_index(%arg0: memref<1024x1024xf32>, %arg1: memref<1xf32>, %arg2: index) -> f32 { @@ -565,8 +608,8 @@ func.func @fold_static_stride_subview_with_affine_load_store_expand_shape_with_c // CHECK-NEXT: affine.for %[[ARG4:.*]] = 0 to 1024 { // CHECK-NEXT: affine.for %[[ARG5:.*]] = 0 to 1020 { // CHECK-NEXT: affine.for %[[ARG6:.*]] = 0 to 1 { -// CHECK-NEXT: %[[TMP1:.*]] = affine.apply #[[$MAP0]](%[[ARG3]]) -// CHECK-NEXT: %[[TMP2:.*]] = affine.apply #[[$MAP1]](%[[ARG5]], %[[ARG6]]) +// CHECK-NEXT: %[[TMP1:.*]] = affine.apply #[[$MAP0]]()[%[[ARG3]]] +// CHECK-NEXT: %[[TMP2:.*]] = affine.apply #[[$MAP1]]()[%[[ARG5]], %[[ARG6]]] // CHECK-NEXT: memref.load %[[ARG0]][%[[TMP1]], %[[TMP2]]] : memref<1024x1024xf32> // ----- -- GitLab From 2475efa91d8b4fa8f1a2d16052cb6d14be7d5dc6 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Wed, 8 May 2024 06:53:12 -0700 Subject: [PATCH 035/328] [SLP]Fix PR91467: Look through scalar cast, when trying to cast to another type. Need to look through the SExt/ZExt scalars to be gathered, when trying to reduce their width after minbitwidth analysis to prevent permanent attempts to revectorize such gathered instructions. --- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 6 +++++- .../SLPVectorizer/AArch64/gather-with-minbith-user.ll | 9 +-------- .../SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll | 7 +------ .../SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll | 3 +-- 4 files changed, 8 insertions(+), 17 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 98561f9ca044..cc9219ca02cf 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -11419,8 +11419,12 @@ Value *BoUpSLP::gather(ArrayRef VL, Value *Root, Type *ScalarTy) { if (Scalar->getType() != Ty) { assert(Scalar->getType()->isIntegerTy() && Ty->isIntegerTy() && "Expected integer types only."); + Value *V = Scalar; + if (auto *CI = dyn_cast(Scalar); + isa_and_nonnull(CI)) + V = CI->getOperand(0); Scalar = Builder.CreateIntCast( - Scalar, Ty, !isKnownNonNegative(Scalar, SimplifyQuery(*DL))); + V, Ty, !isKnownNonNegative(Scalar, SimplifyQuery(*DL))); } Vec = Builder.CreateInsertElement(Vec, Scalar, Builder.getInt32(Pos)); diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll index 76bb882171b1..3ebe920d1734 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll @@ -5,14 +5,7 @@ define void @h() { ; CHECK-LABEL: define void @h() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16 -; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 0 to i1 -; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i1> , i1 [[TMP6]], i32 4 -; CHECK-NEXT: [[TMP1:%.*]] = sub <8 x i1> [[TMP0]], zeroinitializer -; CHECK-NEXT: [[TMP2:%.*]] = add <8 x i1> [[TMP0]], zeroinitializer -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP2]], <8 x i32> -; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i1> [[TMP3]], zeroinitializer -; CHECK-NEXT: [[TMP4:%.*]] = zext <8 x i1> [[TMP5]] to <8 x i16> -; CHECK-NEXT: store <8 x i16> [[TMP4]], ptr [[ARRAYIDX2]], align 2 +; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 2 ; CHECK-NEXT: ret void ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll index 2ab6e919c23b..6404cf4a2cd1 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll @@ -5,12 +5,7 @@ define void @h() { ; CHECK-LABEL: define void @h() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16 -; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 0 to i1 -; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i1> , i1 [[TMP0]], i32 4 -; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i1> zeroinitializer, [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i1> zeroinitializer, [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = zext <8 x i1> [[TMP3]] to <8 x i16> -; CHECK-NEXT: store <8 x i16> [[TMP4]], ptr [[ARRAYIDX2]], align 2 +; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 2 ; CHECK-NEXT: ret void ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll index 1bb87bf6205f..3c8e98485ffc 100644 --- a/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll +++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll @@ -4,10 +4,9 @@ define void @test(ptr %a, i8 %0, i16 %b.promoted.i) { ; CHECK-LABEL: define void @test( ; CHECK-SAME: ptr [[A:%.*]], i8 [[TMP0:%.*]], i16 [[B_PROMOTED_I:%.*]]) #[[ATTR0:[0-9]+]] { -; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP0]] to i128 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[B_PROMOTED_I]], i32 0 ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP5:%.*]] = trunc i128 [[TMP2]] to i16 +; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP0]] to i16 ; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i16> poison, i16 [[TMP5]], i32 0 ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i16> [[TMP6]], <4 x i16> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP4]], [[TMP7]] -- GitLab From 2868e26d0a6f257d3a8f303c7918f37c690e35a4 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Wed, 8 May 2024 07:35:47 -0700 Subject: [PATCH 036/328] Use cmake to find perl executable (#91275) `clang/tools/scan-build` is implemented in `perl`. However given `perl` is not mentioned as a required dependency in `GettingStarted.rst` we should make this optional. This adds a `find_package(Perl)` check to cmake and disables the `scan-build` tests when no perl executable is found. Ideally we would also check if dependent perl modules like `Hash::Util` are present on the system, but I don't see any pre-existing cmake macros to easily test this. So for now I go with a plain check for the `perl` package, at least this allows to use `cmake -DCMAKE_DISABLE_FIND_PACKAGE_Perl=ON` to manually disable `perl` and the tests. --- clang/CMakeLists.txt | 2 ++ clang/test/Analysis/scan-build/deduplication.test | 1 - .../Analysis/scan-build/exclude_directories.test | 3 --- clang/test/Analysis/scan-build/help.test | 3 --- clang/test/Analysis/scan-build/html_output.test | 1 - clang/test/Analysis/scan-build/lit.local.cfg | 13 ++++++++----- .../test/Analysis/scan-build/plist_html_output.test | 1 - clang/test/Analysis/scan-build/plist_output.test | 1 - .../scan-build/rebuild_index/rebuild_index.test | 3 --- .../Analysis/scan-build/silence-core-checkers.test | 3 --- clang/test/lit.site.cfg.py.in | 1 + 11 files changed, 11 insertions(+), 21 deletions(-) diff --git a/clang/CMakeLists.txt b/clang/CMakeLists.txt index cf97e3c6e851..c20ce47a12ab 100644 --- a/clang/CMakeLists.txt +++ b/clang/CMakeLists.txt @@ -523,6 +523,8 @@ endif() if( CLANG_INCLUDE_TESTS ) + find_package(Perl) + add_subdirectory(unittests) list(APPEND CLANG_TEST_DEPS ClangUnitTests) list(APPEND CLANG_TEST_PARAMS diff --git a/clang/test/Analysis/scan-build/deduplication.test b/clang/test/Analysis/scan-build/deduplication.test index 56d888e5fc12..2ec3061701fc 100644 --- a/clang/test/Analysis/scan-build/deduplication.test +++ b/clang/test/Analysis/scan-build/deduplication.test @@ -1,4 +1,3 @@ -// FIXME: Actually, "perl". REQUIRES: shell RUN: rm -rf %t.output_dir && mkdir %t.output_dir diff --git a/clang/test/Analysis/scan-build/exclude_directories.test b/clang/test/Analysis/scan-build/exclude_directories.test index c161e51b6d26..2c79ed842af1 100644 --- a/clang/test/Analysis/scan-build/exclude_directories.test +++ b/clang/test/Analysis/scan-build/exclude_directories.test @@ -1,6 +1,3 @@ -// FIXME: Actually, "perl". -REQUIRES: shell - RUN: rm -rf %t.output_dir && mkdir %t.output_dir RUN: %scan-build -o %t.output_dir %clang -S \ RUN: %S/Inputs/multidirectory_project/directory1/file1.c \ diff --git a/clang/test/Analysis/scan-build/help.test b/clang/test/Analysis/scan-build/help.test index 61915d326094..d1f17cd69f51 100644 --- a/clang/test/Analysis/scan-build/help.test +++ b/clang/test/Analysis/scan-build/help.test @@ -1,6 +1,3 @@ -// FIXME: Actually, "perl". -REQUIRES: shell - RUN: %scan-build -h | FileCheck %s RUN: %scan-build --help | FileCheck %s diff --git a/clang/test/Analysis/scan-build/html_output.test b/clang/test/Analysis/scan-build/html_output.test index add35d83b958..c2b509d9ef66 100644 --- a/clang/test/Analysis/scan-build/html_output.test +++ b/clang/test/Analysis/scan-build/html_output.test @@ -1,4 +1,3 @@ -// FIXME: Actually, "perl". REQUIRES: shell RUN: rm -rf %t.output_dir && mkdir %t.output_dir diff --git a/clang/test/Analysis/scan-build/lit.local.cfg b/clang/test/Analysis/scan-build/lit.local.cfg index fab52b1c7bd6..aed76ca0e808 100644 --- a/clang/test/Analysis/scan-build/lit.local.cfg +++ b/clang/test/Analysis/scan-build/lit.local.cfg @@ -1,8 +1,8 @@ # -*- Python -*- -import lit.util import lit.formats import os +import platform use_lit_shell = os.environ.get("LIT_USE_INTERNAL_SHELL") config.test_format = lit.formats.ShTest(use_lit_shell == "0") @@ -12,13 +12,16 @@ clang_path = config.clang if config.have_llvm_driver else os.path.realpath(confi config.substitutions.append( ( "%scan-build", - "'%s' --use-analyzer=%s " + "'%s' '%s' --use-analyzer=%s " % ( - lit.util.which( - "scan-build", - os.path.join(config.clang_src_dir, "tools", "scan-build", "bin"), + config.perl_executable, + os.path.join( + config.clang_src_dir, "tools", "scan-build", "bin", "scan-build" ), clang_path, ), ) ) + +if not config.perl_executable or platform.system() == "Windows": + config.unsupported = True diff --git a/clang/test/Analysis/scan-build/plist_html_output.test b/clang/test/Analysis/scan-build/plist_html_output.test index c07891e35fbf..ca9c5256b9d7 100644 --- a/clang/test/Analysis/scan-build/plist_html_output.test +++ b/clang/test/Analysis/scan-build/plist_html_output.test @@ -1,4 +1,3 @@ -// FIXME: Actually, "perl". REQUIRES: shell RUN: rm -rf %t.output_dir && mkdir %t.output_dir diff --git a/clang/test/Analysis/scan-build/plist_output.test b/clang/test/Analysis/scan-build/plist_output.test index 0112e84630ed..4d01640bff6e 100644 --- a/clang/test/Analysis/scan-build/plist_output.test +++ b/clang/test/Analysis/scan-build/plist_output.test @@ -1,4 +1,3 @@ -// FIXME: Actually, "perl". REQUIRES: shell RUN: rm -rf %t.output_dir && mkdir %t.output_dir diff --git a/clang/test/Analysis/scan-build/rebuild_index/rebuild_index.test b/clang/test/Analysis/scan-build/rebuild_index/rebuild_index.test index ab70435c6054..711a74f3fd02 100644 --- a/clang/test/Analysis/scan-build/rebuild_index/rebuild_index.test +++ b/clang/test/Analysis/scan-build/rebuild_index/rebuild_index.test @@ -1,6 +1,3 @@ -// FIXME: Actually, "perl". -REQUIRES: shell - RUN: rm -rf %t.output_dir && mkdir %t.output_dir RUN: cp %S/report-1.html %t.output_dir RUN: cp %S/report-2.html %t.output_dir diff --git a/clang/test/Analysis/scan-build/silence-core-checkers.test b/clang/test/Analysis/scan-build/silence-core-checkers.test index 6d9a3017fcd6..7ffa744a545c 100644 --- a/clang/test/Analysis/scan-build/silence-core-checkers.test +++ b/clang/test/Analysis/scan-build/silence-core-checkers.test @@ -1,6 +1,3 @@ -// FIXME: Actually, "perl". -REQUIRES: shell - RUN: rm -rf %t.output_dir && mkdir %t.output_dir RUN: %scan-build -o %t.output_dir \ RUN: %clang -S %S/Inputs/null_dereference_and_division_by_zero.c \ diff --git a/clang/test/lit.site.cfg.py.in b/clang/test/lit.site.cfg.py.in index 6641811c5883..ec6d30e6c220 100644 --- a/clang/test/lit.site.cfg.py.in +++ b/clang/test/lit.site.cfg.py.in @@ -34,6 +34,7 @@ config.enable_backtrace = @ENABLE_BACKTRACES@ config.enable_threads = @LLVM_ENABLE_THREADS@ config.reverse_iteration = @LLVM_ENABLE_REVERSE_ITERATION@ config.host_arch = "@HOST_ARCH@" +config.perl_executable = "@PERL_EXECUTABLE@" config.python_executable = "@Python3_EXECUTABLE@" config.use_z3_solver = lit_config.params.get('USE_Z3_SOLVER', "@USE_Z3_SOLVER@") config.has_plugins = @CLANG_PLUGIN_SUPPORT@ -- GitLab From 3a8316216807d64a586b971f51695e23883331f7 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Wed, 8 May 2024 16:38:38 +0200 Subject: [PATCH 037/328] [bazel] Add missing dependency for 6ed8434edc5934210a38be99f33b6baed83df85c --- utils/bazel/llvm-project-overlay/mlir/BUILD.bazel | 1 + 1 file changed, 1 insertion(+) diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index b75ed99df5b2..6a7bc5c9fea0 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -12945,6 +12945,7 @@ cc_library( ":ArithUtils", ":MemRefDialect", ":VectorDialect", + "//llvm:Support", ], ) -- GitLab From 50b45b24220ead33cf5cedc49c13e0336297e4eb Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Wed, 8 May 2024 15:45:38 +0100 Subject: [PATCH 038/328] [LAA] Add tests with forward dependences known via assumes. --- .../offset-range-known-via-assume.ll | 244 ++++++++++++++++++ 1 file changed, 244 insertions(+) create mode 100644 llvm/test/Analysis/LoopAccessAnalysis/offset-range-known-via-assume.ll diff --git a/llvm/test/Analysis/LoopAccessAnalysis/offset-range-known-via-assume.ll b/llvm/test/Analysis/LoopAccessAnalysis/offset-range-known-via-assume.ll new file mode 100644 index 000000000000..7e36da78d6aa --- /dev/null +++ b/llvm/test/Analysis/LoopAccessAnalysis/offset-range-known-via-assume.ll @@ -0,0 +1,244 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes='print' -disable-output %s 2>&1 | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +declare void @llvm.assume(i1) + +declare void @use(ptr noundef) + +; TODO: %offset is known positive via assume, so we should be able to detect the +; forward dependence. +define void @offset_i8_known_positive_via_assume_forward_dep_1(ptr %A, i64 %offset, i64 %N) { +; CHECK-LABEL: 'offset_i8_known_positive_via_assume_forward_dep_1' +; CHECK-NEXT: loop: +; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Check 0: +; CHECK-NEXT: Comparing group ([[GRP1:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; CHECK-NEXT: Against group ([[GRP2:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.off = getelementptr inbounds i8, ptr %off, i64 %iv +; CHECK-NEXT: Grouped accesses: +; CHECK-NEXT: Group [[GRP1]]: +; CHECK-NEXT: (Low: %A High: (%N + %A)) +; CHECK-NEXT: Member: {%A,+,1}<%loop> +; CHECK-NEXT: Group [[GRP2]]: +; CHECK-NEXT: (Low: (%offset + %A) High: (%offset + %N + %A)) +; CHECK-NEXT: Member: {(%offset + %A),+,1}<%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %c = icmp sgt i64 %offset, 0 + call void @llvm.assume(i1 %c) + %off = getelementptr inbounds i8, ptr %A, i64 %offset + call void @use(ptr noundef %off) + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.off = getelementptr inbounds i8, ptr %off, i64 %iv + %l = load i8 , ptr %gep.off, align 4 + %add = add nsw i8 %l, 5 + %gep = getelementptr inbounds i8, ptr %A, i64 %iv + store i8 %add, ptr %gep, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, %N + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @offset_i32_known_positive_via_assume_forward_dep_1(ptr %A, i64 %offset, i64 %N) { +; CHECK-LABEL: 'offset_i32_known_positive_via_assume_forward_dep_1' +; CHECK-NEXT: loop: +; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Check 0: +; CHECK-NEXT: Comparing group ([[GRP3:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep = getelementptr inbounds i32, ptr %A, i64 %iv +; CHECK-NEXT: Against group ([[GRP4:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.off = getelementptr inbounds i32, ptr %off, i64 %iv +; CHECK-NEXT: Grouped accesses: +; CHECK-NEXT: Group [[GRP3]]: +; CHECK-NEXT: (Low: %A High: (-3 + (4 * %N) + %A)) +; CHECK-NEXT: Member: {%A,+,4}<%loop> +; CHECK-NEXT: Group [[GRP4]]: +; CHECK-NEXT: (Low: ((4 * %offset) + %A) High: (-3 + (4 * %offset) + (4 * %N) + %A)) +; CHECK-NEXT: Member: {((4 * %offset) + %A),+,4}<%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-NEXT: {((4 * %offset) + %A),+,4}<%loop> Added Flags: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %c = icmp sgt i64 %offset, 0 + call void @llvm.assume(i1 %c) + %off = getelementptr inbounds i32, ptr %A, i64 %offset + call void @use(ptr noundef %off) + + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.off = getelementptr inbounds i32, ptr %off, i64 %iv + %l = load i8 , ptr %gep.off, align 4 + %add = add nsw i8 %l, 5 + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + store i8 %add, ptr %gep, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, %N + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +; TODO: %offset is known positive via assume, so we should be able to detect the +; forward dependence. +define void @offset_known_positive_via_assume_forward_dep_2(ptr %A, i64 %offset, i64 %N) { +; CHECK-LABEL: 'offset_known_positive_via_assume_forward_dep_2' +; CHECK-NEXT: loop: +; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Check 0: +; CHECK-NEXT: Comparing group ([[GRP5:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep = getelementptr inbounds i32, ptr %A, i64 %iv +; CHECK-NEXT: Against group ([[GRP6:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.off = getelementptr inbounds i32, ptr %off, i64 %iv +; CHECK-NEXT: Grouped accesses: +; CHECK-NEXT: Group [[GRP5]]: +; CHECK-NEXT: (Low: %A High: ((4 * %N) + %A)) +; CHECK-NEXT: Member: {%A,+,4}<%loop> +; CHECK-NEXT: Group [[GRP6]]: +; CHECK-NEXT: (Low: ((4 * %offset) + %A) High: ((4 * %offset) + (4 * %N) + %A)) +; CHECK-NEXT: Member: {((4 * %offset) + %A),+,4}<%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %c = icmp sgt i64 %offset, 0 + call void @llvm.assume(i1 %c) + %c.2 = icmp slt i64 %offset, 20 + call void @llvm.assume(i1 %c.2) + %off = getelementptr inbounds i32, ptr %A, i64 %offset + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.off = getelementptr inbounds i32, ptr %off, i64 %iv + %l = load i32, ptr %gep.off, align 4 + %add = add nsw i32 %l, 5 + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + store i32 %add, ptr %gep, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, %N + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +; The range of %offset is known via assumes, but it may be positive or negative. +define void @offset_may_be_negative_via_assume_unknown_dep(ptr %A, i64 %offset, i64 %N) { +; CHECK-LABEL: 'offset_may_be_negative_via_assume_unknown_dep' +; CHECK-NEXT: loop: +; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Check 0: +; CHECK-NEXT: Comparing group ([[GRP7:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.mul.2 = getelementptr inbounds i32, ptr %A, i64 %iv +; CHECK-NEXT: Against group ([[GRP8:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep = getelementptr inbounds i32, ptr %off, i64 %iv +; CHECK-NEXT: Grouped accesses: +; CHECK-NEXT: Group [[GRP7]]: +; CHECK-NEXT: (Low: %A High: ((4 * %N) + %A)) +; CHECK-NEXT: Member: {%A,+,4}<%loop> +; CHECK-NEXT: Group [[GRP8]]: +; CHECK-NEXT: (Low: ((4 * %offset) + %A) High: ((4 * %offset) + (4 * %N) + %A)) +; CHECK-NEXT: Member: {((4 * %offset) + %A),+,4}<%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %c = icmp sgt i64 %offset, -4 + call void @llvm.assume(i1 %c) + %c.2 = icmp slt i64 %offset, 20 + call void @llvm.assume(i1 %c.2) + %off = getelementptr inbounds i32, ptr %A, i64 %offset + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i32, ptr %off, i64 %iv + %l = load i32, ptr %gep, align 4 + %add = add nsw i32 %l, 5 + %gep.mul.2 = getelementptr inbounds i32, ptr %A, i64 %iv + store i32 %add, ptr %gep.mul.2, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, %N + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @offset_no_assumes(ptr %A, i64 %offset, i64 %N) { +; CHECK-LABEL: 'offset_no_assumes' +; CHECK-NEXT: loop: +; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Check 0: +; CHECK-NEXT: Comparing group ([[GRP9:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep = getelementptr inbounds i32, ptr %A, i64 %iv +; CHECK-NEXT: Against group ([[GRP10:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.off = getelementptr inbounds i32, ptr %off, i64 %iv +; CHECK-NEXT: Grouped accesses: +; CHECK-NEXT: Group [[GRP9]]: +; CHECK-NEXT: (Low: %A High: ((4 * %N) + %A)) +; CHECK-NEXT: Member: {%A,+,4}<%loop> +; CHECK-NEXT: Group [[GRP10]]: +; CHECK-NEXT: (Low: ((4 * %offset) + %A) High: ((4 * %offset) + (4 * %N) + %A)) +; CHECK-NEXT: Member: {((4 * %offset) + %A),+,4}<%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %off = getelementptr inbounds i32, ptr %A, i64 %offset + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.off = getelementptr inbounds i32, ptr %off, i64 %iv + %l = load i32, ptr %gep.off, align 4 + %add = add nsw i32 %l, 5 + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + store i32 %add, ptr %gep, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, %N + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} -- GitLab From 11a6799740f824282650aa9ec249b55dcf1a8aae Mon Sep 17 00:00:00 2001 From: Jacob Lambert Date: Wed, 8 May 2024 08:11:15 -0700 Subject: [PATCH 039/328] [clang][CodeGen] Omit pre-opt link when post-opt is link requested (#85672) Currently, when the -relink-builtin-bitcodes-postop option is used we link builtin bitcodes twice: once before optimization, and again after optimization. With this change, we omit the pre-opt linking when the option is set, and we rename the option to the following: -Xclang -mlink-builtin-bitcodes-postopt (-Xclang -mno-link-builtin-bitcodes-postopt) The goal of this change is to reduce compile time. We do lose the theoretical benefits of pre-opt linking, but in practice these are small than the overhead of linking twice. However we may be able to address this in a future patch by adjusting the position of the builtin-bitcode linking pass. Compilations not setting the option are unaffected --- clang/include/clang/Basic/CodeGenOptions.def | 1 + clang/include/clang/Driver/Options.td | 5 +++ clang/lib/CodeGen/BackendConsumer.h | 4 -- clang/lib/CodeGen/BackendUtil.cpp | 12 +----- clang/lib/CodeGen/CodeGenAction.cpp | 37 +------------------ clang/lib/CodeGen/LinkInModulesPass.cpp | 8 +--- .../test/CodeGen/linking-bitcode-postopt.cpp | 31 ++++++++++++++++ 7 files changed, 43 insertions(+), 55 deletions(-) create mode 100644 clang/test/CodeGen/linking-bitcode-postopt.cpp diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def index b964e4557478..07b0ca1691a6 100644 --- a/clang/include/clang/Basic/CodeGenOptions.def +++ b/clang/include/clang/Basic/CodeGenOptions.def @@ -309,6 +309,7 @@ CODEGENOPT(UnrollLoops , 1, 0) ///< Control whether loops are unrolled. CODEGENOPT(RerollLoops , 1, 0) ///< Control whether loops are rerolled. CODEGENOPT(NoUseJumpTables , 1, 0) ///< Set when -fno-jump-tables is enabled. VALUE_CODEGENOPT(UnwindTables, 2, 0) ///< Unwind tables (1) or asynchronous unwind tables (2) +CODEGENOPT(LinkBitcodePostopt, 1, 0) ///< Link builtin bitcodes after optimization pipeline. CODEGENOPT(VectorizeLoop , 1, 0) ///< Run loop vectorizer. CODEGENOPT(VectorizeSLP , 1, 0) ///< Run SLP vectorizer. CODEGENOPT(ProfileSampleAccurate, 1, 0) ///< Sample profile is accurate. diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 734ae7833f5c..322cc12af34a 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -7092,6 +7092,11 @@ def mlink_bitcode_file : Separate<["-"], "mlink-bitcode-file">, def mlink_builtin_bitcode : Separate<["-"], "mlink-builtin-bitcode">, HelpText<"Link and internalize needed symbols from the given bitcode file " "before performing optimizations.">; +defm link_builtin_bitcode_postopt: BoolMOption<"link-builtin-bitcode-postopt", + CodeGenOpts<"LinkBitcodePostopt">, DefaultFalse, + PosFlag, + NegFlag>; def vectorize_loops : Flag<["-"], "vectorize-loops">, HelpText<"Run the Loop vectorization passes">, MarshallingInfoFlag>; diff --git a/clang/lib/CodeGen/BackendConsumer.h b/clang/lib/CodeGen/BackendConsumer.h index fd0f1984d6c0..f9edbe901bb8 100644 --- a/clang/lib/CodeGen/BackendConsumer.h +++ b/clang/lib/CodeGen/BackendConsumer.h @@ -115,10 +115,6 @@ public: // Links each entry in LinkModules into our module. Returns true on error. bool LinkInModules(llvm::Module *M, bool ShouldLinkFiles = true); - // Load a bitcode module from -mlink-builtin-bitcode option using - // methods from a BackendConsumer instead of CompilerInstance - bool ReloadModules(llvm::Module *M); - /// Get the best possible source location to represent a diagnostic that /// may have associated debug info. const FullSourceLoc getBestLocationFromDebugLoc( diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index 119ec4704002..90985c08fe7f 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -120,11 +120,6 @@ static cl::opt ClPGOColdFuncAttr( "Mark cold functions with optnone."))); extern cl::opt ProfileCorrelate; - -// Re-link builtin bitcodes after optimization -cl::opt ClRelinkBuiltinBitcodePostop( - "relink-builtin-bitcode-postop", cl::Optional, - cl::desc("Re-link builtin bitcodes after optimization.")); } // namespace llvm namespace { @@ -1055,11 +1050,8 @@ void EmitAssemblyHelper::RunOptimizationPipeline( } } - // Re-link against any bitcodes supplied via the -mlink-builtin-bitcode option - // Some optimizations may generate new function calls that would not have - // been linked pre-optimization (i.e. fused sincos calls generated by - // AMDGPULibCalls::fold_sincos.) - if (ClRelinkBuiltinBitcodePostop) + // Link against bitcodes supplied via the -mlink-builtin-bitcode option + if (CodeGenOpts.LinkBitcodePostopt) MPM.addPass(LinkInModulesPass(BC, false)); // Add a verifier pass if requested. We don't have to do this if the action diff --git a/clang/lib/CodeGen/CodeGenAction.cpp b/clang/lib/CodeGen/CodeGenAction.cpp index 1a6b628016f7..0255f05b1f90 100644 --- a/clang/lib/CodeGen/CodeGenAction.cpp +++ b/clang/lib/CodeGen/CodeGenAction.cpp @@ -60,10 +60,6 @@ using namespace llvm; #define DEBUG_TYPE "codegenaction" -namespace llvm { -extern cl::opt ClRelinkBuiltinBitcodePostop; -} - namespace clang { class BackendConsumer; class ClangDiagnosticHandler final : public DiagnosticHandler { @@ -232,35 +228,6 @@ void BackendConsumer::HandleInterestingDecl(DeclGroupRef D) { HandleTopLevelDecl(D); } -bool BackendConsumer::ReloadModules(llvm::Module *M) { - for (const CodeGenOptions::BitcodeFileToLink &F : - CodeGenOpts.LinkBitcodeFiles) { - auto BCBuf = FileMgr.getBufferForFile(F.Filename); - if (!BCBuf) { - Diags.Report(diag::err_cannot_open_file) - << F.Filename << BCBuf.getError().message(); - LinkModules.clear(); - return true; - } - - LLVMContext &Ctx = getModule()->getContext(); - Expected> ModuleOrErr = - getOwningLazyBitcodeModule(std::move(*BCBuf), Ctx); - - if (!ModuleOrErr) { - handleAllErrors(ModuleOrErr.takeError(), [&](ErrorInfoBase &EIB) { - Diags.Report(diag::err_cannot_open_file) << F.Filename << EIB.message(); - }); - LinkModules.clear(); - return true; - } - LinkModules.push_back({std::move(ModuleOrErr.get()), F.PropagateAttrs, - F.Internalize, F.LinkFlags}); - } - - return false; // success -} - // Links each entry in LinkModules into our module. Returns true on error. bool BackendConsumer::LinkInModules(llvm::Module *M, bool ShouldLinkFiles) { for (auto &LM : LinkModules) { @@ -362,7 +329,7 @@ void BackendConsumer::HandleTranslationUnit(ASTContext &C) { } // Link each LinkModule into our module. - if (LinkInModules(getModule())) + if (!CodeGenOpts.LinkBitcodePostopt && LinkInModules(getModule())) return; for (auto &F : getModule()->functions()) { @@ -1232,7 +1199,7 @@ void CodeGenAction::ExecuteAction() { std::move(LinkModules), *VMContext, nullptr); // Link in each pending link module. - if (Result.LinkInModules(&*TheModule)) + if (!CodeGenOpts.LinkBitcodePostopt && Result.LinkInModules(&*TheModule)) return; // PR44896: Force DiscardValueNames as false. DiscardValueNames cannot be diff --git a/clang/lib/CodeGen/LinkInModulesPass.cpp b/clang/lib/CodeGen/LinkInModulesPass.cpp index 929539cc8f33..c3831aae13b6 100644 --- a/clang/lib/CodeGen/LinkInModulesPass.cpp +++ b/clang/lib/CodeGen/LinkInModulesPass.cpp @@ -28,12 +28,8 @@ PreservedAnalyses LinkInModulesPass::run(Module &M, ModuleAnalysisManager &AM) { if (!BC) return PreservedAnalyses::all(); - // Re-load bitcode modules from files - if (BC->ReloadModules(&M)) - report_fatal_error("Bitcode module re-loading failed, aborted!"); - if (BC->LinkInModules(&M, ShouldLinkFiles)) - report_fatal_error("Bitcode module re-linking failed, aborted!"); + report_fatal_error("Bitcode module postopt linking failed, aborted!"); - return PreservedAnalyses::all(); + return PreservedAnalyses::none(); } diff --git a/clang/test/CodeGen/linking-bitcode-postopt.cpp b/clang/test/CodeGen/linking-bitcode-postopt.cpp new file mode 100644 index 000000000000..a0486ed0c9a8 --- /dev/null +++ b/clang/test/CodeGen/linking-bitcode-postopt.cpp @@ -0,0 +1,31 @@ +// REQUIRES: amdgpu-registered-target + +// Test that -mlink-bitcode-postopt correctly enables LinkInModulesPass + +// RUN: %clang_cc1 -triple amdgcn-- -emit-llvm-bc -o /dev/null \ +// RUN: -mllvm -print-pipeline-passes \ +// RUN: %s 2>&1 | FileCheck --check-prefixes=DEFAULT %s + +// DEFAULT-NOT: LinkInModulesPass + +// RUN: %clang_cc1 -triple amdgcn-- -emit-llvm-bc -o /dev/null \ +// RUN: -mllvm -print-pipeline-passes \ +// RUN: -mlink-builtin-bitcode-postopt \ +// RUN: %s 2>&1 | FileCheck --check-prefixes=OPTION-POSITIVE %s + +// OPTION-POSITIVE: LinkInModulesPass + +// RUN: %clang_cc1 -triple amdgcn-- -emit-llvm-bc -o /dev/null \ +// RUN: -mllvm -print-pipeline-passes \ +// RUN: -mno-link-builtin-bitcode-postopt \ +// RUN: %s 2>&1 | FileCheck --check-prefixes=OPTION-NEGATIVE %s + +// OPTION-NEGATIVE-NOT: LinkInModulesPass + +// RUN: %clang_cc1 -triple amdgcn-- -emit-llvm-bc -o /dev/null \ +// RUN: -mllvm -print-pipeline-passes \ +// RUN: -mlink-builtin-bitcode-postopt \ +// RUN: -mno-link-builtin-bitcode-postopt \ +// RUN: %s 2>&1 | FileCheck --check-prefixes=OPTION-POSITIVE-NEGATIVE %s + +// OPTION-POSITIVE-NEGATIVE-NOT: LinkInModulesPass -- GitLab From a55127281b2ed5f24f848b9e5c70870ad170bc3f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 8 May 2024 13:43:27 +0100 Subject: [PATCH 040/328] [CostModel][X86] getGSVectorCost - add cost kind support Don't just assume gather/scatter non-throughput costs are 1 - latency and sizelatency (#uops) costs will be high, and codesize (#instructions) needs to account splitting. --- .../lib/Target/X86/X86TargetTransformInfo.cpp | 31 ++-- .../X86/masked-intrinsic-codesize.ll | 38 ++--- .../CostModel/X86/masked-intrinsic-latency.ll | 132 +++++++++--------- .../X86/masked-intrinsic-sizelatency.ll | 132 +++++++++--------- 4 files changed, 167 insertions(+), 166 deletions(-) diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 2257370912bd..6b7cddc6d72e 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -5828,14 +5828,17 @@ InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Alignment, AddressSpace); } + // If we didn't split, this will be a single gather/scatter instruction. + if (CostKind == TTI::TCK_CodeSize) + return 1; + // The gather / scatter cost is given by Intel architects. It is a rough // number since we are looking at one instruction in a time. - const int GSOverhead = (Opcode == Instruction::Load) - ? getGatherOverhead() - : getScatterOverhead(); + const int GSOverhead = (Opcode == Instruction::Load) ? getGatherOverhead() + : getScatterOverhead(); return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), MaybeAlign(Alignment), AddressSpace, - TTI::TCK_RecipThroughput); + CostKind); } /// Return the cost of full scalarization of gather / scatter operation. @@ -5892,19 +5895,17 @@ InstructionCost X86TTIImpl::getGatherScatterOpCost( unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I = nullptr) { - if (CostKind != TTI::TCK_RecipThroughput) { - if ((Opcode == Instruction::Load && - isLegalMaskedGather(SrcVTy, Align(Alignment)) && - !forceScalarizeMaskedGather(cast(SrcVTy), - Align(Alignment))) || - (Opcode == Instruction::Store && - isLegalMaskedScatter(SrcVTy, Align(Alignment)) && - !forceScalarizeMaskedScatter(cast(SrcVTy), - Align(Alignment)))) - return 1; + if (CostKind != TTI::TCK_RecipThroughput && + ((Opcode == Instruction::Load && + (!isLegalMaskedGather(SrcVTy, Align(Alignment)) || + forceScalarizeMaskedGather(cast(SrcVTy), + Align(Alignment)))) || + (Opcode == Instruction::Store && + (!isLegalMaskedScatter(SrcVTy, Align(Alignment)) || + forceScalarizeMaskedScatter(cast(SrcVTy), + Align(Alignment)))))) return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, Alignment, CostKind, I); - } assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); PointerType *PtrTy = dyn_cast(Ptr->getType()); diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll index 320774175944..1e5c02afc2b3 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll @@ -840,20 +840,20 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKL-LABEL: 'masked_gather' -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 139 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) @@ -871,7 +871,7 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) @@ -879,7 +879,7 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; KNL-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) @@ -898,7 +898,7 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) @@ -906,7 +906,7 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) @@ -1094,7 +1094,7 @@ define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m ; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; KNL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) @@ -1102,7 +1102,7 @@ define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m ; KNL-NEXT: Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; KNL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) @@ -1121,7 +1121,7 @@ define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) @@ -1129,7 +1129,7 @@ define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) @@ -1909,7 +1909,7 @@ define <16 x float> @test_gather_16f32_const_mask(ptr %base, <16 x i32> %ind) { ; SKL-LABEL: 'test_gather_16f32_const_mask' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX512-LABEL: 'test_gather_16f32_const_mask' @@ -1953,7 +1953,7 @@ define <16 x float> @test_gather_16f32_var_mask(ptr %base, <16 x i32> %ind, <16 ; SKL-LABEL: 'test_gather_16f32_var_mask' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX512-LABEL: 'test_gather_16f32_var_mask' @@ -1997,13 +1997,13 @@ define <16 x float> @test_gather_16f32_ra_var_mask(<16 x ptr> %ptrs, <16 x i32> ; SKL-LABEL: 'test_gather_16f32_ra_var_mask' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX512-LABEL: 'test_gather_16f32_ra_var_mask' ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; %sext_ind = sext <16 x i32> %ind to <16 x i64> @@ -2051,7 +2051,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX512-LABEL: 'test_gather_16f32_const_mask2' diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll index 781a000149e4..14dc561edc34 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll @@ -840,22 +840,22 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKL-LABEL: 'masked_gather' -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 139 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) @@ -867,20 +867,20 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; KNL-LABEL: 'masked_gather' -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 175 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) @@ -894,21 +894,21 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKX-LABEL: 'masked_gather' -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 175 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 87 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) @@ -1090,20 +1090,20 @@ define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; KNL-LABEL: 'masked_scatter' -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; KNL-NEXT: Cost Model: Found an estimated cost of 175 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) @@ -1117,21 +1117,21 @@ define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKX-LABEL: 'masked_scatter' -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; SKX-NEXT: Cost Model: Found an estimated cost of 175 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) ; SKX-NEXT: Cost Model: Found an estimated cost of 87 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) @@ -1804,7 +1804,7 @@ define <2 x double> @test_gather_2f64(<2 x ptr> %ptrs, <2 x i1> %mask, <2 x doub ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; SKL-LABEL: 'test_gather_2f64' -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; AVX512-LABEL: 'test_gather_2f64' @@ -1833,7 +1833,7 @@ define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %s ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKL-LABEL: 'test_gather_4i32' -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; KNL-LABEL: 'test_gather_4i32' @@ -1841,7 +1841,7 @@ define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %s ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKX-LABEL: 'test_gather_4i32' -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) @@ -1866,7 +1866,7 @@ define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKL-LABEL: 'test_gather_4i32_const_mask' -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; KNL-LABEL: 'test_gather_4i32_const_mask' @@ -1874,7 +1874,7 @@ define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKX-LABEL: 'test_gather_4i32_const_mask' -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) @@ -1909,13 +1909,13 @@ define <16 x float> @test_gather_16f32_const_mask(ptr %base, <16 x i32> %ind) { ; SKL-LABEL: 'test_gather_16f32_const_mask' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX512-LABEL: 'test_gather_16f32_const_mask' ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; AVX512-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; %sext_ind = sext <16 x i32> %ind to <16 x i64> @@ -1953,13 +1953,13 @@ define <16 x float> @test_gather_16f32_var_mask(ptr %base, <16 x i32> %ind, <16 ; SKL-LABEL: 'test_gather_16f32_var_mask' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX512-LABEL: 'test_gather_16f32_var_mask' ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX512-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; %sext_ind = sext <16 x i32> %ind to <16 x i64> @@ -1997,13 +1997,13 @@ define <16 x float> @test_gather_16f32_ra_var_mask(<16 x ptr> %ptrs, <16 x i32> ; SKL-LABEL: 'test_gather_16f32_ra_var_mask' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX512-LABEL: 'test_gather_16f32_ra_var_mask' ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX512-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; %sext_ind = sext <16 x i32> %ind to <16 x i64> @@ -2051,7 +2051,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX512-LABEL: 'test_gather_16f32_const_mask2' @@ -2059,7 +2059,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; AVX512-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 @@ -2118,7 +2118,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; AVX512-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 @@ -2144,7 +2144,7 @@ define void @test_scatter_8i32(<8 x i32>%a1, <8 x ptr> %ptr, <8 x i1>%mask) { ; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX512-LABEL: 'test_scatter_8i32' -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) +; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) @@ -2169,7 +2169,7 @@ define void @test_scatter_4i32(<4 x i32>%a1, <4 x ptr> %ptr, <4 x i1>%mask) { ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SKX-LABEL: 'test_scatter_4i32' -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) @@ -2204,7 +2204,7 @@ define <4 x float> @test_gather_4f32(ptr %ptr, <4 x i32> %ind, <4 x i1>%mask) { ; SKL-LABEL: 'test_gather_4f32' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; KNL-LABEL: 'test_gather_4f32' @@ -2216,7 +2216,7 @@ define <4 x float> @test_gather_4f32(ptr %ptr, <4 x i32> %ind, <4 x i1>%mask) { ; SKX-LABEL: 'test_gather_4f32' ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SKX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; %sext_ind = sext <4 x i32> %ind to <4 x i64> @@ -2254,7 +2254,7 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; SKL-LABEL: 'test_gather_4f32_const_mask' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; KNL-LABEL: 'test_gather_4f32_const_mask' @@ -2266,7 +2266,7 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; SKX-LABEL: 'test_gather_4f32_const_mask' ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SKX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; %sext_ind = sext <4 x i32> %ind to <4 x i64> diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll index 6d8b344c0002..a030068dfaf5 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll @@ -840,22 +840,22 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKL-LABEL: 'masked_gather' -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 139 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) @@ -867,20 +867,20 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; KNL-LABEL: 'masked_gather' -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 175 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) @@ -894,21 +894,21 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKX-LABEL: 'masked_gather' -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 175 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 87 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) @@ -1090,20 +1090,20 @@ define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; KNL-LABEL: 'masked_scatter' -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; KNL-NEXT: Cost Model: Found an estimated cost of 175 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) @@ -1117,21 +1117,21 @@ define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKX-LABEL: 'masked_scatter' -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; SKX-NEXT: Cost Model: Found an estimated cost of 175 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) ; SKX-NEXT: Cost Model: Found an estimated cost of 87 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) @@ -1804,7 +1804,7 @@ define <2 x double> @test_gather_2f64(<2 x ptr> %ptrs, <2 x i1> %mask, <2 x doub ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; SKL-LABEL: 'test_gather_2f64' -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; AVX512-LABEL: 'test_gather_2f64' @@ -1833,7 +1833,7 @@ define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %s ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKL-LABEL: 'test_gather_4i32' -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; KNL-LABEL: 'test_gather_4i32' @@ -1841,7 +1841,7 @@ define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %s ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKX-LABEL: 'test_gather_4i32' -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) @@ -1866,7 +1866,7 @@ define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKL-LABEL: 'test_gather_4i32_const_mask' -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; KNL-LABEL: 'test_gather_4i32_const_mask' @@ -1874,7 +1874,7 @@ define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKX-LABEL: 'test_gather_4i32_const_mask' -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) @@ -1909,13 +1909,13 @@ define <16 x float> @test_gather_16f32_const_mask(ptr %base, <16 x i32> %ind) { ; SKL-LABEL: 'test_gather_16f32_const_mask' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX512-LABEL: 'test_gather_16f32_const_mask' ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; AVX512-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; %sext_ind = sext <16 x i32> %ind to <16 x i64> @@ -1953,13 +1953,13 @@ define <16 x float> @test_gather_16f32_var_mask(ptr %base, <16 x i32> %ind, <16 ; SKL-LABEL: 'test_gather_16f32_var_mask' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX512-LABEL: 'test_gather_16f32_var_mask' ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX512-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; %sext_ind = sext <16 x i32> %ind to <16 x i64> @@ -1997,13 +1997,13 @@ define <16 x float> @test_gather_16f32_ra_var_mask(<16 x ptr> %ptrs, <16 x i32> ; SKL-LABEL: 'test_gather_16f32_ra_var_mask' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX512-LABEL: 'test_gather_16f32_ra_var_mask' ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX512-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; %sext_ind = sext <16 x i32> %ind to <16 x i64> @@ -2051,7 +2051,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX512-LABEL: 'test_gather_16f32_const_mask2' @@ -2059,7 +2059,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; AVX512-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 @@ -2118,7 +2118,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; AVX512-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 @@ -2144,7 +2144,7 @@ define void @test_scatter_8i32(<8 x i32>%a1, <8 x ptr> %ptr, <8 x i1>%mask) { ; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX512-LABEL: 'test_scatter_8i32' -; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) +; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) @@ -2169,7 +2169,7 @@ define void @test_scatter_4i32(<4 x i32>%a1, <4 x ptr> %ptr, <4 x i1>%mask) { ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SKX-LABEL: 'test_scatter_4i32' -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) @@ -2204,7 +2204,7 @@ define <4 x float> @test_gather_4f32(ptr %ptr, <4 x i32> %ind, <4 x i1>%mask) { ; SKL-LABEL: 'test_gather_4f32' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; KNL-LABEL: 'test_gather_4f32' @@ -2216,7 +2216,7 @@ define <4 x float> @test_gather_4f32(ptr %ptr, <4 x i32> %ind, <4 x i1>%mask) { ; SKX-LABEL: 'test_gather_4f32' ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SKX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; %sext_ind = sext <4 x i32> %ind to <4 x i64> @@ -2254,7 +2254,7 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; SKL-LABEL: 'test_gather_4f32_const_mask' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; KNL-LABEL: 'test_gather_4f32_const_mask' @@ -2266,7 +2266,7 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; SKX-LABEL: 'test_gather_4f32_const_mask' ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SKX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; %sext_ind = sext <4 x i32> %ind to <4 x i64> -- GitLab From 29b7eb8400f48fe7d8de3cb3741584c329ec597c Mon Sep 17 00:00:00 2001 From: Juergen Ributzka Date: Wed, 8 May 2024 08:58:55 -0700 Subject: [PATCH 041/328] [llvm][stackmaps] Include pristine registers for liveness computation. (#90529) Users of stackmaps and patchpoints need to add all pristine registers to the spill set, even so they don't need to be all preserved. This fixes the liveness computation for stackmaps to include pristine registers. This fixes rdar://21228337. --- llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp | 3 +- .../test/CodeGen/AArch64/stackmap-liveness.ll | 80 +++++++++++- llvm/test/CodeGen/X86/stackmap-liveness.ll | 115 +++++++++++++++--- 3 files changed, 175 insertions(+), 23 deletions(-) diff --git a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp index 778ac1f5701c..687acd90b405 100644 --- a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp +++ b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp @@ -126,8 +126,7 @@ bool StackMapLiveness::calculateLiveness(MachineFunction &MF) { for (auto &MBB : MF) { LLVM_DEBUG(dbgs() << "****** BB " << MBB.getName() << " ******\n"); LiveRegs.init(*TRI); - // FIXME: This should probably be addLiveOuts(). - LiveRegs.addLiveOutsNoPristines(MBB); + LiveRegs.addLiveOuts(MBB); bool HasStackMap = false; // Reverse iterate over all instructions and add the current live register // set to an instruction if we encounter a patchpoint instruction. diff --git a/llvm/test/CodeGen/AArch64/stackmap-liveness.ll b/llvm/test/CodeGen/AArch64/stackmap-liveness.ll index e1f9ffe42a77..c19c2623e322 100644 --- a/llvm/test/CodeGen/AArch64/stackmap-liveness.ll +++ b/llvm/test/CodeGen/AArch64/stackmap-liveness.ll @@ -27,16 +27,88 @@ define i64 @stackmap_liveness(i1 %c) { ; Padding ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .short 0 -; Num LiveOut Entries: 1 -; CHECK-NEXT: .short 2 -; LiveOut Entry 0: X0 +; Num LiveOut Entries: 20 +; CHECK-NEXT: .short 20 +; LiveOut Entry 1: X0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .byte 8 -; LiveOut Entry 1: SP +; LiveOut Entry 2: +; CHECK-NEXT: .short 19 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 3: +; CHECK-NEXT: .short 20 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 4: +; CHECK-NEXT: .short 21 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 5: +; CHECK-NEXT: .short 22 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 6: +; CHECK-NEXT: .short 23 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 7: +; CHECK-NEXT: .short 24 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 8: +; CHECK-NEXT: .short 25 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 9: +; CHECK-NEXT: .short 26 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 10: +; CHECK-NEXT: .short 27 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 11: +; CHECK-NEXT: .short 28 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 12: SP ; CHECK-NEXT: .short 31 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .byte 8 +; LiveOut Entry 13: +; CHECK-NEXT: .short 72 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 14: +; CHECK-NEXT: .short 73 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 15: +; CHECK-NEXT: .short 74 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 16: +; CHECK-NEXT: .short 75 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 17: +; CHECK-NEXT: .short 76 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 18: +; CHECK-NEXT: .short 77 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 19: +; CHECK-NEXT: .short 78 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 20: +; CHECK-NEXT: .short 79 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 ; Align ; CHECK-NEXT: .p2align 3 %1 = select i1 %c, i64 1, i64 2 diff --git a/llvm/test/CodeGen/X86/stackmap-liveness.ll b/llvm/test/CodeGen/X86/stackmap-liveness.ll index 798eab9249df..10a8f950baeb 100644 --- a/llvm/test/CodeGen/X86/stackmap-liveness.ll +++ b/llvm/test/CodeGen/X86/stackmap-liveness.ll @@ -46,9 +46,29 @@ entry: ; Padding ; PATCH-NEXT: .p2align 3 ; PATCH-NEXT: .short 0 -; Num LiveOut Entries: 1 -; PATCH-NEXT: .short 1 -; LiveOut Entry 1: %ymm2 (16 bytes) --> %xmm2 +; Num LiveOut Entries: 6 +; PATCH-NEXT: .short 6 +; LiveOut Entry 1: +; PATCH-NEXT: .short 3 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 2: +; PATCH-NEXT: .short 12 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 3: +; PATCH-NEXT: .short 13 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 4: +; PATCH-NEXT: .short 14 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 5: +; PATCH-NEXT: .short 15 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 6: %ymm2 (16 bytes) --> %xmm2 ; PATCH-NEXT: .short 19 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 16 @@ -79,25 +99,46 @@ entry: ; Padding ; PATCH-NEXT: .p2align 3 ; PATCH-NEXT: .short 0 -; Num LiveOut Entries: 5 -; PATCH-NEXT: .short 5 +; Num LiveOut Entries: 10 +; PATCH-NEXT: .short 10 + ; LiveOut Entry 1: %rax (1 bytes) --> %al or %ah ; PATCH-NEXT: .short 0 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 1 -; LiveOut Entry 2: %r8 (8 bytes) +; LiveOut Entry 2: +; PATCH-NEXT: .short 3 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 3: %r8 (8 bytes) ; PATCH-NEXT: .short 8 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 8 -; LiveOut Entry 3: %ymm0 (32 bytes) +; LiveOut Entry 4: +; PATCH-NEXT: .short 12 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 5: +; PATCH-NEXT: .short 13 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 6: +; PATCH-NEXT: .short 14 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 7: +; PATCH-NEXT: .short 15 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 8: %ymm0 (32 bytes) ; PATCH-NEXT: .short 17 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 32 -; LiveOut Entry 4: %ymm1 (32 bytes) +; LiveOut Entry 9: %ymm1 (32 bytes) ; PATCH-NEXT: .short 18 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 32 -; LiveOut Entry 5: %ymm2 (16 bytes) --> %xmm2 +; LiveOut Entry 10: %ymm2 (16 bytes) --> %xmm2 ; PATCH-NEXT: .short 19 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 16 @@ -125,13 +166,33 @@ entry: ; Padding ; PATCH-NEXT: .p2align 3 ; PATCH-NEXT: .short 0 -; Num LiveOut Entries: 2 -; PATCH-NEXT: .short 2 -; LiveOut Entry 1: %rsp (8 bytes) +; Num LiveOut Entries: 7 +; PATCH-NEXT: .short 7 +; LiveOut Entry 1: +; PATCH-NEXT: .short 3 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 2: %rsp (8 bytes) ; PATCH-NEXT: .short 7 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 8 -; LiveOut Entry 2: %ymm2 (16 bytes) --> %xmm2 +; LiveOut Entry 3: +; PATCH-NEXT: .short 12 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 4: +; PATCH-NEXT: .short 13 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 5: +; PATCH-NEXT: .short 14 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 6: +; PATCH-NEXT: .short 15 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 7: %ymm2 (16 bytes) --> %xmm2 ; PATCH-NEXT: .short 19 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 16 @@ -164,13 +225,33 @@ entry: ; Padding ; PATCH-NEXT: .p2align 3 ; PATCH-NEXT: .short 0 -; Num LiveOut Entries: 2 -; PATCH-NEXT: .short 2 -; LiveOut Entry 1: %rsp (8 bytes) +; Num LiveOut Entries: 7 +; PATCH-NEXT: .short 7 +; LiveOut Entry 1: +; PATCH-NEXT: .short 3 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 2: %rsp (8 bytes) ; PATCH-NEXT: .short 7 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 8 -; LiveOut Entry 2: %ymm2 (16 bytes) --> %xmm2 +; LiveOut Entry 3: +; PATCH-NEXT: .short 12 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 4: +; PATCH-NEXT: .short 13 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 5: +; PATCH-NEXT: .short 14 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 6: +; PATCH-NEXT: .short 15 +; PATCH-NEXT: .byte 0 +; PATCH-NEXT: .byte 8 +; LiveOut Entry 7: %ymm2 (16 bytes) --> %xmm2 ; PATCH-NEXT: .short 19 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 16 -- GitLab From 9263318f9da22e6632f1aae3e85717ed88fde64f Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Wed, 8 May 2024 12:01:22 -0400 Subject: [PATCH 042/328] Revise the modules document for clarity (#90237) The intention isn't to add or change the information provided, but to improve clarity through some grammar fixes, improvements to the markdown, and so forth. --- clang/docs/StandardCPlusPlusModules.rst | 1215 +++++++++++------------ 1 file changed, 604 insertions(+), 611 deletions(-) diff --git a/clang/docs/StandardCPlusPlusModules.rst b/clang/docs/StandardCPlusPlusModules.rst index ee57fb5da648..1c3c4d319c0e 100644 --- a/clang/docs/StandardCPlusPlusModules.rst +++ b/clang/docs/StandardCPlusPlusModules.rst @@ -8,109 +8,92 @@ Standard C++ Modules Introduction ============ -The term ``modules`` has a lot of meanings. For the users of Clang, modules may -refer to ``Objective-C Modules``, ``Clang C++ Modules`` (or ``Clang Header Modules``, -etc.) or ``Standard C++ Modules``. The implementation of all these kinds of modules in Clang -has a lot of shared code, but from the perspective of users, their semantics and -command line interfaces are very different. This document focuses on -an introduction of how to use standard C++ modules in Clang. - -There is already a detailed document about `Clang modules `_, it -should be helpful to read `Clang modules `_ if you want to know -more about the general idea of modules. Since standard C++ modules have different semantics -(and work flows) from `Clang modules`, this page describes the background and use of -Clang with standard C++ modules. - -Modules exist in two forms in the C++ Language Specification. They can refer to -either "Named Modules" or to "Header Units". This document covers both forms. +The term ``module`` is ambiguous, as it is used to mean multiple things in +Clang. For Clang users, a module may refer to an ``Objective-C Module``, +`Clang Module `_ (also called a ``Clang Header Module``) or a +``C++20 Module`` (or a ``Standard C++ Module``). The implementation of all +these kinds of modules in Clang shares a lot of code, but from the perspective +of users their semantics and command line interfaces are very different. This +document is an introduction to the use of C++20 modules in Clang. In the +remainder of this document, the term ``module`` will refer to Standard C++20 +modules and the term ``Clang module`` will refer to the Clang Modules +extension. + +In terms of the C++ Standard, modules consist of two components: "Named +Modules" or "Header Units". This document covers both. Standard C++ Named modules ========================== -This document was intended to be a manual first and foremost, however, we consider it helpful to -introduce some language background here for readers who are not familiar with -the new language feature. This document is not intended to be a language -tutorial; it will only introduce necessary concepts about the -structure and building of the project. +In order to better understand the compiler's behavior, it is helpful to +understand some terms and definitions for readers who are not familiar with the +C++ feature. This document is not a tutorial on C++; it only introduces +necessary concepts to better understand use of modules in a project. Background and terminology -------------------------- -Modules -~~~~~~~ - -In this document, the term ``Modules``/``modules`` refers to standard C++ modules -feature if it is not decorated by ``Clang``. - -Clang Modules -~~~~~~~~~~~~~ - -In this document, the term ``Clang Modules``/``Clang modules`` refer to Clang -c++ modules extension. These are also known as ``Clang header modules``, -``Clang module map modules`` or ``Clang c++ modules``. - Module and module unit ~~~~~~~~~~~~~~~~~~~~~~ -A module consists of one or more module units. A module unit is a special -translation unit. Every module unit must have a module declaration. The syntax -of the module declaration is: +A module consists of one or more module units. A module unit is a special kind +of translation unit. A module unit should almost always start with a module +declaration. The syntax of the module declaration is: .. code-block:: c++ [export] module module_name[:partition_name]; -Terms enclosed in ``[]`` are optional. The syntax of ``module_name`` and ``partition_name`` -in regex form corresponds to ``[a-zA-Z_][a-zA-Z_0-9\.]*``. In particular, a literal dot ``.`` -in the name has no semantic meaning (e.g. implying a hierarchy). +Terms enclosed in ``[]`` are optional. ``module_name`` and ``partition_name`` +follow the rules for a C++ identifier, except that they may contain one or more +period (``.``) characters. Note that a ``.`` in the name has no semantic +meaning and does not imply any hierarchy. -In this document, module units are classified into: +In this document, module units are classified as: -* Primary module interface unit. - -* Module implementation unit. - -* Module interface partition unit. - -* Internal module partition unit. +* Primary module interface unit +* Module implementation unit +* Module partition interface unit +* Internal module partition unit A primary module interface unit is a module unit whose module declaration is -``export module module_name;``. The ``module_name`` here denotes the name of the +``export module module_name;`` where ``module_name`` denotes the name of the module. A module should have one and only one primary module interface unit. A module implementation unit is a module unit whose module declaration is -``module module_name;``. A module could have multiple module implementation -units with the same declaration. +``module module_name;``. Multiple module implementation units can be declared +in the same module. -A module interface partition unit is a module unit whose module declaration is +A module partition interface unit is a module unit whose module declaration is ``export module module_name:partition_name;``. The ``partition_name`` should be unique within any given module. -An internal module partition unit is a module unit whose module declaration -is ``module module_name:partition_name;``. The ``partition_name`` should be -unique within any given module. +An internal module partition unit is a module unit whose module +declaration is ``module module_name:partition_name;``. The ``partition_name`` +should be unique within any given module. -In this document, we use the following umbrella terms: +In this document, we use the following terms: * A ``module interface unit`` refers to either a ``primary module interface unit`` - or a ``module interface partition unit``. + or a ``module partition interface unit``. -* An ``importable module unit`` refers to either a ``module interface unit`` - or a ``internal module partition unit``. +* An ``importable module unit`` refers to either a ``module interface unit`` or + an ``internal module partition unit``. -* A ``module partition unit`` refers to either a ``module interface partition unit`` - or a ``internal module partition unit``. +* A ``module partition unit`` refers to either a ``module partition interface unit`` + or an ``internal module partition unit``. -Built Module Interface file -~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Built Module Interface +~~~~~~~~~~~~~~~~~~~~~~ -A ``Built Module Interface file`` stands for the precompiled result of an importable module unit. -It is also called the acronym ``BMI`` generally. +A ``Built Module Interface`` (or ``BMI``) is the precompiled result of an +importable module unit. Global module fragment ~~~~~~~~~~~~~~~~~~~~~~ -In a module unit, the section from ``module;`` to the module declaration is called the global module fragment. +The ``global module fragment`` (or ``GMF``) is the code between the ``module;`` +and the module declaration within a module unit. How to build projects using modules @@ -138,7 +121,7 @@ Let's see a "hello world" example that uses modules. return 0; } -Then we type: +Then, on the command line, invoke Clang like: .. code-block:: console @@ -148,9 +131,9 @@ Then we type: Hello World! In this example, we make and use a simple module ``Hello`` which contains only a -primary module interface unit ``Hello.cppm``. +primary module interface unit named ``Hello.cppm``. -Then let's see a little bit more complex "hello world" example which uses the 4 kinds of module units. +A more complex "hello world" example which uses the 4 kinds of module units is: .. code-block:: c++ @@ -192,7 +175,7 @@ Then let's see a little bit more complex "hello world" example which uses the 4 return 0; } -Then we are able to compile the example by the following command: +Then, back on the command line, invoke Clang with: .. code-block:: console @@ -216,51 +199,57 @@ We explain the options in the following sections. How to enable standard C++ modules ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Currently, standard C++ modules are enabled automatically -if the language standard is ``-std=c++20`` or newer. +Standard C++ modules are enabled automatically when the language standard mode +is ``-std=c++20`` or newer. How to produce a BMI ~~~~~~~~~~~~~~~~~~~~ -We can generate a BMI for an importable module unit by either ``--precompile`` -or ``-fmodule-output`` flags. +To generate a BMI for an importable module unit, use either the ``--precompile`` +or ``-fmodule-output`` command line options. -The ``--precompile`` option generates the BMI as the output of the compilation and the output path -can be specified using the ``-o`` option. +The ``--precompile`` option generates the BMI as the output of the compilation +with the output path specified using the ``-o`` option. -The ``-fmodule-output`` option generates the BMI as a by-product of the compilation. -If ``-fmodule-output=`` is specified, the BMI will be emitted the specified location. Then if -``-fmodule-output`` and ``-c`` are specified, the BMI will be emitted in the directory of the -output file with the name of the input file with the new extension ``.pcm``. Otherwise, the BMI -will be emitted in the working directory with the name of the input file with the new extension +The ``-fmodule-output`` option generates the BMI as a by-product of the +compilation. If ``-fmodule-output=`` is specified, the BMI will be emitted to +the specified location. If ``-fmodule-output`` and ``-c`` are specified, the +BMI will be emitted in the directory of the output file with the name of the +input file with the extension ``.pcm``. Otherwise, the BMI will be emitted in +the working directory with the name of the input file with the extension ``.pcm``. -The style to generate BMIs by ``--precompile`` is called two-phase compilation since it takes -2 steps to compile a source file to an object file. The style to generate BMIs by ``-fmodule-output`` -is called one-phase compilation respectively. The one-phase compilation model is simpler -for build systems to implement and the two-phase compilation has the potential to compile faster due -to higher parallelism. As an example, if there are two module units A and B, and B depends on A, the -one-phase compilation model would need to compile them serially, whereas the two-phase compilation -model may be able to compile them simultaneously if the compilation from A.pcm to A.o takes a long -time. - -File name requirement -~~~~~~~~~~~~~~~~~~~~~ - -The file name of an ``importable module unit`` should end with ``.cppm`` -(or ``.ccm``, ``.cxxm``, ``.c++m``). The file name of a ``module implementation unit`` -should end with ``.cpp`` (or ``.cc``, ``.cxx``, ``.c++``). - -The file name of BMIs should end with ``.pcm``. -The file name of the BMI of a ``primary module interface unit`` should be ``module_name.pcm``. -The file name of BMIs of ``module partition unit`` should be ``module_name-partition_name.pcm``. - -If the file names use different extensions, Clang may fail to build the module. -For example, if the filename of an ``importable module unit`` ends with ``.cpp`` instead of ``.cppm``, -then we can't generate a BMI for the ``importable module unit`` by ``--precompile`` option -since ``--precompile`` option now would only run preprocessor, which is equal to `-E` now. -If we want the filename of an ``importable module unit`` ends with other suffixes instead of ``.cppm``, -we could put ``-x c++-module`` in front of the file. For example, +Generating BMIs with ``--precompile`` is referred to as two-phase compilation +because it takes two steps to compile a source file to an object file. +Generating BMIs with ``-fmodule-output`` is called one-phase compilation. The +one-phase compilation model is simpler for build systems to implement while the +two-phase compilation has the potential to compile faster due to higher +parallelism. As an example, if there are two module units ``A`` and ``B``, and +``B`` depends on ``A``, the one-phase compilation model needs to compile them +serially, whereas the two-phase compilation model is able to be compiled as +soon as ``A.pcm`` is available, and thus can be compiled simultaneously as the +``A.pcm`` to ``A.o`` compilation step. + +File name requirements +~~~~~~~~~~~~~~~~~~~~~~ + +By convention, ``importable module unit`` files should use ``.cppm`` (or +``.ccm``, ``.cxxm``, or ``.c++m``) as a file extension. +``Module implementation unit`` files should use ``.cpp`` (or ``.cc``, ``.cxx``, +or ``.c++``) as a file extension. + +A BMI should use ``.pcm`` as a file extension. The file name of the BMI for a +``primary module interface unit`` should be ``module_name.pcm``. The file name +of a BMI for a ``module partition unit`` should be +``module_name-partition_name.pcm``. + +Clang may fail to build the module if different extensions are used. For +example, if the filename of an ``importable module unit`` ends with ``.cpp`` +instead of ``.cppm``, then Clang cannot generate a BMI for the +``importable module unit`` with the ``--precompile`` option because the +``--precompile`` option would only run the preprocessor (``-E``). If using a +different extension than the conventional one for an ``importable module unit`` +you can specify ``-x c++-module`` before the file. For example, .. code-block:: c++ @@ -279,8 +268,9 @@ we could put ``-x c++-module`` in front of the file. For example, return 0; } -Now the filename of the ``module interface`` ends with ``.cpp`` instead of ``.cppm``, -we can't compile them by the original command lines. But we are still able to do it by: +In this example, the extension used by the ``module interface`` is ``.cpp`` +instead of ``.cppm``, so it cannot be compiled like the previous example, but +it can be compiled with: .. code-block:: console @@ -289,12 +279,12 @@ we can't compile them by the original command lines. But we are still able to do $ ./Hello.out Hello World! -Module name requirement -~~~~~~~~~~~~~~~~~~~~~~~ +Module name requirements +~~~~~~~~~~~~~~~~~~~~~~~~ -[module.unit]p1 says: +.. -.. code-block:: text + [module.unit]p1: All module-names either beginning with an identifier consisting of std followed by zero or more digits or containing a reserved identifier ([lex.name]) are reserved and shall not @@ -302,7 +292,7 @@ Module name requirement module-name is a reserved identifier, the module name is reserved for use by C++ implementations; otherwise it is reserved for future standardization. -So all of the following name is not valid by default: +Therefore, none of the following names are valid by default: .. code-block:: text @@ -312,75 +302,74 @@ So all of the following name is not valid by default: __test // and so on ... -If you still want to use the reserved module names for any reason, use -``-Wno-reserved-module-identifier`` to suppress the warning. +Using a reserved module name is strongly discouraged, but +``-Wno-reserved-module-identifier`` can be used to suppress the warning. -How to specify the dependent BMIs -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Specifying dependent BMIs +~~~~~~~~~~~~~~~~~~~~~~~~~ -There are 3 methods to specify the dependent BMIs: +There are 3 ways to specify a dependent BMI: -* (1) ``-fprebuilt-module-path=``. -* (2) ``-fmodule-file=`` (Deprecated). -* (3) ``-fmodule-file==``. +1. ``-fprebuilt-module-path=``. +2. ``-fmodule-file=`` (Deprecated). +3. ``-fmodule-file==``. -The option ``-fprebuilt-module-path`` tells the compiler the path where to search for dependent BMIs. -It may be used multiple times just like ``-I`` for specifying paths for header files. The look up rule here is: +The ``-fprebuilt-module-path`` option specifies the path to search for +dependent BMIs. Multiple paths may be specified, similar to using ``-I`` to +specify a search path for header files. When importing a module ``M``, the +compiler looks for ``M.pcm`` in the directories specified by +``-fprebuilt-module-path``. Similarly, when importing a partition module unit +``M:P``, the compiler looks for ``M-P.pcm`` in the directories specified by +``-fprebuilt-module-path``. -* (1) When we import module M. The compiler would look up M.pcm in the directories specified - by ``-fprebuilt-module-path``. -* (2) When we import partition module unit M:P. The compiler would look up M-P.pcm in the - directories specified by ``-fprebuilt-module-path``. - -The option ``-fmodule-file=`` tells the compiler to load the specified BMI directly. -The option ``-fmodule-file==`` tells the compiler to load the specified BMI -for the module specified by ```` when necessary. The main difference is that +The ``-fmodule-file=`` option causes the compiler to load the +specified BMI directly. The ``-fmodule-file==`` +option causes the compiler to load the specified BMI for the module specified +by ```` when necessary. The main difference is that ``-fmodule-file=`` will load the BMI eagerly, whereas -``-fmodule-file==`` will only load the BMI lazily, which is similar -with ``-fprebuilt-module-path``. The option ``-fmodule-file=`` for named modules is deprecated -and is planning to be removed in future versions. +``-fmodule-file==`` will only load the BMI lazily, +as will ``-fprebuilt-module-path``. The ``-fmodule-file=`` option +for named modules is deprecated and will be removed in a future version of +Clang. -In case all ``-fprebuilt-module-path=``, ``-fmodule-file=`` and -``-fmodule-file==`` exist, the ``-fmodule-file=`` option -takes highest precedence and ``-fmodule-file==`` will take the second -highest precedence. +When these options are specified in the same invocation of the compiler, the +``-fmodule-file=`` option takes precedence over +``-fmodule-file==``, which takes precedence over +``-fprebuilt-module-path=``. -We need to specify all the dependent (directly and indirectly) BMIs. -See https://github.com/llvm/llvm-project/issues/62707 for detail. +Note: all dependant BMIs must be specified explicitly, either directly or +indirectly dependent BMIs explicitly. See +https://github.com/llvm/llvm-project/issues/62707 for details. -When we compile a ``module implementation unit``, we must specify the BMI of the corresponding -``primary module interface unit``. -Since the language specification says a module implementation unit implicitly imports -the primary module interface unit. +When compiling a ``module implementation unit``, the BMI of the corresponding +``primary module interface unit`` must be specified because a module +implementation unit implicitly imports the primary module interface unit. [module.unit]p8 A module-declaration that contains neither an export-keyword nor a module-partition implicitly imports the primary module interface unit of the module as if by a module-import-declaration. -All of the 3 options ``-fprebuilt-module-path=``, ``-fmodule-file=`` -and ``-fmodule-file==`` may occur multiple times. -For example, the command line to compile ``M.cppm`` in -the above example could be rewritten into: +The ``-fprebuilt-module-path=``, ``-fmodule-file=``, +and ``-fmodule-file==`` options may be specified +multiple times. For example, the command line to compile ``M.cppm`` in +the previous example could be rewritten as: .. code-block:: console $ clang++ -std=c++20 M.cppm --precompile -fmodule-file=M:interface_part=M-interface_part.pcm -fmodule-file=M:impl_part=M-impl_part.pcm -o M.pcm When there are multiple ``-fmodule-file==`` options for the same -````, the last ``-fmodule-file==`` will override the previous -``-fmodule-file==`` options. - -``-fprebuilt-module-path`` is more convenient and ``-fmodule-file`` is faster since -it saves time for file lookup. +````, the last ``-fmodule-file==`` overrides the +previous ``-fmodule-file==`` option. Remember that module units still have an object counterpart to the BMI ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -It is easy to forget to compile BMIs at first since we may envision module interfaces like headers. -However, this is not true. -Module units are translation units. We need to compile them to object files -and link the object files like the example shows. +While module interfaces resemble traditional header files, they still require +compilation. Module units are translation units, and need to be compiled to +object files, which then need to be linked together as the following examples +show. For example, the traditional compilation processes for headers are like: @@ -400,24 +389,27 @@ And the compilation process for module units are like: mod1.cppm -> clang++ mod1.cppm ... -> mod1.pcm --,--> clang++ mod1.pcm ... -> mod1.o -+ src2.cpp ----------------------------------------+> clang++ src2.cpp -------> src2.o -' -As the diagrams show, we need to compile the BMI from module units to object files and link the object files. -(But we can't do this for the BMI from header units. See the later section for the definition of header units) +As the diagrams show, we need to compile the BMI from module units to object +files and then link the object files. (However, this cannot be done for the BMI +from header units. See the section on :ref:`header units ` for +more details. -If we want to create a module library, we can't just ship the BMIs in an archive. -We must compile these BMIs(``*.pcm``) into object files(``*.o``) and add those object files to the archive instead. +BMIs cannot be shipped in an archive to create a module library. Instead, the +BMIs(``*.pcm``) are compiled into object files(``*.o``) and those object files +are added to the archive instead. -Consistency Requirement -~~~~~~~~~~~~~~~~~~~~~~~ +Consistency Requirements +~~~~~~~~~~~~~~~~~~~~~~~~ -If we envision modules as a cache to speed up compilation, then - as with other caching techniques - -it is important to keep cache consistency. -So **currently** Clang will do very strict check for consistency. +Modules can be viewed as a kind of cache to speed up compilation. Thus, like +other caching techniques, it is important to maintain cache consistency which +is why Clang does very strict checking for consistency. Options consistency ^^^^^^^^^^^^^^^^^^^ -The language option of module units and their non-module-unit users should be consistent. -The following example is not allowed: +Compiler options related to the language dialect for a module unit and its +non-module-unit uses need to be consistent. Consider the following example: .. code-block:: c++ @@ -432,9 +424,8 @@ The following example is not allowed: $ clang++ -std=c++20 M.cppm --precompile -o M.pcm $ clang++ -std=c++23 Use.cpp -fprebuilt-module-path=. -The compiler would reject the example due to the inconsistent language options. -Not all options are language options. -For example, the following example is allowed: +Clang rejects the example due to the inconsistent language standard modes. Not +all compiler options are language dialect options, though. For example: .. code-block:: console @@ -444,9 +435,12 @@ For example, the following example is allowed: # Inconsistent debugging level. $ clang++ -std=c++20 -g Use.cpp -fprebuilt-module-path=. -Although the two examples have inconsistent optimization and debugging level, both of them are accepted. +Although the optimization and debugging levels are inconsistent, these +compilations are accepted because the compiler options do not impact the +language dialect. -Note that **currently** the compiler doesn't consider inconsistent macro definition a problem. For example: +Note that the compiler **currently** doesn't reject inconsistent macro +definitions (this may change in the future). For example: .. code-block:: console @@ -454,43 +448,43 @@ Note that **currently** the compiler doesn't consider inconsistent macro definit # Inconsistent optimization level. $ clang++ -std=c++20 -O3 -DNDEBUG Use.cpp -fprebuilt-module-path=. -Currently Clang would accept the above example. But it may produce surprising results if the -debugging code depends on consistent use of ``NDEBUG`` also in other translation units. +Currently, Clang accepts the above example, though it may produce surprising +results if the debugging code depends on consistent use of ``NDEBUG`` in other +translation units. -Definitions consistency -^^^^^^^^^^^^^^^^^^^^^^^ +Object definition consistency +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The C++ language requires that declarations of the same entity in different +translation units have the same definition, which is known as the One +Definition Rule (ODR). Without modules, the compiler cannot perform strong ODR +violation checking because it only sees one translation unit at a time. With +the use of modules, the compiler can perform checks for ODR violations across +translation units. -The C++ language defines that same declarations in different translation units should have -the same definition, as known as ODR (One Definition Rule). Prior to modules, the translation -units don't dependent on each other and the compiler itself can't perform a strong -ODR violation check. With the introduction of modules, now the compiler have -the chance to perform ODR violations with language semantics across translation units. - -However, in the practice, we found the existing ODR checking mechanism is not stable -enough. Many people suffers from the false positive ODR violation diagnostics, AKA, -the compiler are complaining two identical declarations have different definitions -incorrectly. Also the true positive ODR violations are rarely reported. -Also we learned that MSVC don't perform ODR check for declarations in the global module -fragment. - -So in order to get better user experience, save the time checking ODR and keep consistent -behavior with MSVC, we disabled the ODR check for the declarations in the global module -fragment by default. Users who want more strict check can still use the -``-Xclang -fno-skip-odr-check-in-gmf`` flag to get the ODR check enabled. It is also -encouraged to report issues if users find false positive ODR violations or false negative ODR -violations with the flag enabled. +However, the current ODR checking mechanisms are not perfect. There are a +significant number of false positive ODR violation diagnostics, where the +compiler incorrectly diagnoses two identical declarations as having different +definitions. Further, true positive ODR violations are not always reported. + +To give a better user experience, improve compilation performance, and for +consistency with MSVC, ODR checking of declarations in the global module +fragment is disabled by default. These checks can be enabled by specifying +``-Xclang -fno-skip-odr-check-in-gmf`` when compiling. If the check is enabled +and you encounter incorrect or missing diagnostics, please report them via the +`community issue tracker `_. ABI Impacts ----------- -This section describes the new ABI changes brought by modules. - -Only Itanium C++ ABI related change are mentioned +This section describes the new ABI changes brought by modules. Only changes to +the Itanium C++ ABI are covered. -Mangling Names -~~~~~~~~~~~~~~ +Name Mangling +~~~~~~~~~~~~~ -The declarations in a module unit which are not in the global module fragment have new linkage names. +The declarations in a module unit which are not in the global module fragment +have new linkage names. For example, @@ -501,22 +495,24 @@ For example, export int foo(); } -The linkage name of ``NS::foo()`` would be ``_ZN2NSW1M3fooEv``. -This couldn't be demangled by previous versions of the debugger or demangler. -As of LLVM 15.x, users can utilize ``llvm-cxxfilt`` to demangle this: +The linkage name of ``NS::foo()`` is ``_ZN2NSW1M3fooEv``. This couldn't be +demangled by previous versions of the debugger or demangler. As of LLVM 15.x, +``llvm-cxxfilt`` can be used to demangle this: .. code-block:: console $ llvm-cxxfilt _ZN2NSW1M3fooEv + NS::foo@M() -The result would be ``NS::foo@M()``, which reads as ``NS::foo()`` in module ``M``. +The result should be read as ``NS::foo()`` in module ``M``. -The ABI implies that we can't declare something in a module unit and define it in a non-module unit (or vice-versa), -as this would result in linking errors. +The ABI implies that something cannot be declared in a module unit and defined +in a non-module unit (or vice-versa), as this would result in linking errors. -If we still want to implement declarations within the compatible ABI in module unit, -we can use the language-linkage specifier. Since the declarations in the language-linkage specifier -is attached to the global module fragments. For example: +Despite this, it is possible to implement declarations with a compatible ABI in +a module unit by using a language linkage specifier because the declarations in +the language linkage specifier are attached to the global module fragment. For +example: .. code-block:: c++ @@ -530,43 +526,47 @@ Now the linkage name of ``NS::foo()`` will be ``_ZN2NS3fooEv``. Module Initializers ~~~~~~~~~~~~~~~~~~~ -All the importable module units are required to emit an initializer function. -The initializer function should contain calls to importing modules first and -all the dynamic-initializers in the current module unit then. +All importable module units are required to emit an initializer function to +handle the dynamic initialization of non-inline variables in the module unit. +The importable module unit has to emit the initializer even if there is no +dynamic initialization; otherwise, the importer may call a nonexistent +function. The initializer function emits calls to imported modules first +followed by calls to all to of the dynamic initializers in the current module +unit. -Translation units explicitly or implicitly importing named modules must call -the initializer functions of the imported named modules within the sequence of -the dynamic-initializers in the TU. Initializations of entities at namespace -scope are appearance-ordered. This (recursively) extends into imported modules -at the point of appearance of the import declaration. +Translation units that explicitly or implicitly import a named module must call +the initializer functions of the imported named module within the sequence of +the dynamic initializers in the translation unit. Initializations of entities +at namespace scope are appearance-ordered. This (recursively) extends to +imported modules at the point of appearance of the import declaration. -It is allowed to omit calls to importing modules if it is known empty. - -It is allowed to omit calls to importing modules for which is known to be called. +If the imported module is known to be empty, the call to its initializer may be +omitted. Additionally, if the imported module is known to have already been +imported, the call to its initializer may be omitted. Reduced BMI ----------- -To support the 2 phase compilation model, Clang chose to put everything needed to -produce an object into the BMI. But every consumer of the BMI, except itself, doesn't -need such informations. It makes the BMI to larger and so may introduce unnecessary -dependencies into the BMI. To mitigate the problem, we decided to reduce the information -contained in the BMI. - -To be clear, we call the default BMI as Full BMI and the new introduced BMI as Reduced -BMI. +To support the two-phase compilation model, Clang puts everything needed to +produce an object into the BMI. However, other consumers of the BMI generally +don't need that information. This makes the BMI larger and may introduce +unnecessary dependencies for the BMI. To mitigate the problem, Clang has a +compiler option to reduce the information contained in the BMI. These two +formats are known as Full BMI and Reduced BMI, respectively. -Users can use ``-fexperimental-modules-reduced-bmi`` flag to enable the Reduced BMI. +Users can use the ``-fexperimental-modules-reduced-bmi`` option to produce a +Reduced BMI. -For one phase compilation model (CMake implements this model), with -``-fexperimental-modules-reduced-bmi``, the generated BMI will be Reduced BMI automatically. -(The output path of the BMI is specified by ``-fmodule-output=`` as usual one phase -compilation model). +For the one-phase compilation model (CMake implements this model), with +``-fexperimental-modules-reduced-bmi``, the generated BMI will be a Reduced +BMI automatically. (The output path of the BMI is specified by +``-fmodule-output=`` as usual with the one-phase compilation model). -It is still possible to support Reduced BMI in two phase compilation model. With -``-fexperimental-modules-reduced-bmi``, ``--precompile`` and ``-fmodule-output=`` specified, -the generated BMI specified by ``-o`` will be full BMI and the BMI specified by -``-fmodule-output=`` will be Reduced BMI. The dependency graph may be: +It is also possible to produce a Reduced BMI with the two-phase compilation +model. When ``-fexperimental-modules-reduced-bmi``, ``--precompile``, and +``-fmodule-output=`` are specified, the generated BMI specified by ``-o`` will +be a full BMI and the BMI specified by ``-fmodule-output=`` will be a Reduced +BMI. The dependency graph in this case would look like: .. code-block:: none @@ -577,15 +577,16 @@ the generated BMI specified by ``-o`` will be full BMI and the BMI specified by -> ... -> consumer_n.cpp -We don't emit diagnostics if ``-fexperimental-modules-reduced-bmi`` is used with a non-module -unit. This design helps the end users of one phase compilation model to perform experiments -early without asking for the help of build systems. The users of build systems which supports -two phase compilation model still need helps from build systems. +Clang does not emit diagnostics when ``-fexperimental-modules-reduced-bmi`` is +used with a non-module unit. This design permits users of the one-phase +compilation model to try using reduced BMIs without needing to modify the build +system. The two-phase compilation module requires build system support. -Within Reduced BMI, we won't write unreachable entities from GMF, definitions of non-inline -functions and non-inline variables. This may not be a transparent change. -`[module.global.frag]ex2 `_ may be a good -example: +In a Reduced BMI, Clang does not emit unreachable entities from the global +module fragment, or definitions of non-inline functions and non-inline +variables. This may not be a transparent change. + +Consider the following example: .. code-block:: c++ @@ -633,22 +634,23 @@ example: // module M's interface, so is discarded int c = use_h(); // OK -In the above example, the function definition of ``N::g`` is elided from the Reduced -BMI of ``M.cppm``. Then the use of ``use_g`` in ``M-impl.cpp`` fails -to instantiate. For such issues, users can add references to ``N::g`` in the module purview -of ``M.cppm`` to make sure it is reachable, e.g., ``using N::g;``. +In the above example, the function definition of ``N::g`` is elided from the +Reduced BMI of ``M.cppm``. Then the use of ``use_g`` in ``M-impl.cpp`` +fails to instantiate. For such issues, users can add references to ``N::g`` in +the `module purview `_ of ``M.cppm`` to +ensure it is reachable, e.g. ``using N::g;``. -We think the Reduced BMI is the correct direction. But given it is a drastic change, -we'd like to make it experimental first to avoid breaking existing users. The roadmap -of Reduced BMI may be: +Support for Reduced BMIs is still experimental, but it may become the default +in the future. The expected roadmap for Reduced BMIs as of Clang 19.x is: -1. ``-fexperimental-modules-reduced-bmi`` is opt in for 1~2 releases. The period depends -on testing feedbacks. -2. We would announce Reduced BMI is not experimental and introduce ``-fmodules-reduced-bmi``. -and suggest users to enable this mode. This may takes 1~2 releases too. -3. Finally we will enable this by default. When that time comes, the term BMI will refer to -the reduced BMI today and the Full BMI will only be meaningful to build systems which -loves to support two phase compilations. +1. ``-fexperimental-modules-reduced-bmi`` is opt-in for 1~2 releases. The period depends + on user feedback and may be extended. +2. Announce that Reduced BMIs are no longer experimental and introduce + ``-fmodules-reduced-bmi`` as a new option, and recommend use of the new + option. This transition is expected to take 1~2 additional releases as well. +3. Finally, ``-fmodules-reduced-bmi`` will be the default. When that time + comes, the term BMI will refer to the Reduced BMI and the Full BMI will only + be meaningful to build systems which elect to support two-phase compilation. Performance Tips ---------------- @@ -656,13 +658,11 @@ Performance Tips Reduce duplications ~~~~~~~~~~~~~~~~~~~ -While it is legal to have duplicated declarations in the global module fragments -of different module units, it is not free for clang to deal with the duplicated -declarations. In other word, for a translation unit, it will compile slower if the -translation unit itself and its importing module units contains a lot duplicated -declarations. - -For example, +While it is valid to have duplicated declarations in the global module fragments +of different module units, it is not free for Clang to deal with the duplicated +declarations. A translation unit will compile more slowly if there is a lot of +duplicated declarations between the translation unit and modules it imports. +For example: .. code-block:: c++ @@ -698,9 +698,9 @@ For example, import M; ... // use declarations from module M. -When ``big.header.h`` is big enough and there are a lot of partitions, -the compilation of ``use.cpp`` may be slower than -the following style significantly: +When ``big.header.h`` is big enough and there are a lot of partitions, the +compilation of ``use.cpp`` may be significantly slower than the following +approach: .. code-block:: c++ @@ -738,22 +738,21 @@ the following style significantly: import M; ... // use declarations from module M. -The key part of the tip is to reduce the duplications from the text includes. - -Ideas for converting to modules -------------------------------- +Reducing the duplication from textual includes is what improves compile-time +performance. -For new libraries, we encourage them to use modules completely from day one if possible. -This will be pretty helpful to make the whole ecosystems to get ready. +Transitioning to modules +------------------------ -For many existing libraries, it may be a breaking change to refactor themselves -into modules completely. So that many existing libraries need to provide headers and module -interfaces for a while to not break existing users. -Here we provide some ideas to ease the transition process for existing libraries. -**Note that the this section is only about helping ideas instead of requirement from clang**. +It is best for new code and libraries to use modules from the start if +possible. However, it may be a breaking change for existing code or libraries +to switch to modules. As a result, many existing libraries need to provide +both headers and module interfaces for a while to not break existing users. -Let's start with the case that there is no dependency or no dependent libraries providing -modules for your library. +This section suggests some suggestions on how to ease the transition process +for existing libraries. **Note that this information is only intended as +guidance, rather than as requirements to use modules in Clang.** It presumes +the project is starting with no module-based dependencies. ABI non-breaking styles ~~~~~~~~~~~~~~~~~~~~~~~ @@ -776,9 +775,9 @@ export-using style using decl_n; } -As the example shows, you need to include all the headers containing declarations needs -to be exported and `using` such declarations in an `export` block. Then, basically, -we're done. +This example shows how to include all the headers containing declarations which +need to be exported, and uses `using` declarations in an `export` block to +produce the module interface. export extern-C++ style ^^^^^^^^^^^^^^^^^^^^^^^ @@ -799,7 +798,7 @@ export extern-C++ style #include "header_n.h" } -Then in your headers (from ``header_1.h`` to ``header_n.h``), you need to define the macro: +Headers (from ``header_1.h`` to ``header_n.h``) need to define the macro: .. code-block:: c++ @@ -809,9 +808,10 @@ Then in your headers (from ``header_1.h`` to ``header_n.h``), you need to define #define EXPORT #endif -And you should put ``EXPORT`` to the beginning of the declarations you want to export. +and put ``EXPORT`` on the declarations you want to export. -Also it is suggested to refactor your headers to include thirdparty headers conditionally: +Also, it is recommended to refactor headers to include third-party headers +conditionally: .. code-block:: c++ @@ -823,26 +823,25 @@ Also it is suggested to refactor your headers to include thirdparty headers cond ... -This may be helpful to get better diagnostic messages if you forgot to update your module -interface unit file during maintaining. +This can be helpful because it gives better diagnostic messages if the module +interface unit is not properly updated when modifying code. -The reasoning for the practice is that the declarations in the language linkage are considered -to be attached to the global module. So the ABI of your library in the modular version -wouldn't change. +This approach works because the declarations with language linkage are attached +to the global module. Thus, the ABI of the modular form of the library does not +change. -While this style looks not as convenient as the export-using style, it is easier to convert -to other styles. +While this style is more involved than the export-using style, it makes it +easier to further refactor the library to other styles. ABI breaking style ~~~~~~~~~~~~~~~~~~ -The term ``ABI breaking`` sounds terrifying generally. But you may want it here if you want -to force your users to introduce your library in a consistent way. E.g., they either include -your headers all the way or import your modules all the way. -The style prevents the users to include your headers and import your modules at the same time -in the same repo. +The term ``ABI breaking`` may sound like a bad approach. However, this style +forces consumers of the library use it in a consistent way. e.g., either always +include headers for the library or always import modules. The style prevents +the ability to mix includes and imports for the library. -The pattern for ABI breaking style is similar with export extern-C++ style. +The pattern for ABI breaking style is similar to the export extern-C++ style. .. code-block:: c++ @@ -865,7 +864,7 @@ The pattern for ABI breaking style is similar with export extern-C++ style. ... #include "source_n.cpp" #else // the number of .cpp files in your project are a lot - // Using all the declarations from thirdparty libraries which are + // Using all the declarations from third-party libraries which are // used in the .cpp files. namespace third_party_namespace { using third_party_decl_used_in_cpp_1; @@ -875,11 +874,11 @@ The pattern for ABI breaking style is similar with export extern-C++ style. } #endif -(And add `EXPORT` and conditional include to the headers as suggested in the export -extern-C++ style section) +(And add `EXPORT` and conditional include to the headers as suggested in the +export extern-C++ style section.) -Remember that the ABI get changed and we need to compile our source files into the -new ABI format. This is the job of the additional part of the interface unit: +The ABI with modules is different and thus we need to compile the source files +into the new ABI. This is done by an additional part of the interface unit: .. code-block:: c++ @@ -890,7 +889,7 @@ new ABI format. This is the job of the additional part of the interface unit: ... #include "source_n.cpp" #else // the number of .cpp files in your project are a lot - // Using all the declarations from thirdparty libraries which are + // Using all the declarations from third-party libraries which are // used in the .cpp files. namespace third_party_namespace { using third_party_decl_used_in_cpp_1; @@ -900,16 +899,17 @@ new ABI format. This is the job of the additional part of the interface unit: } #endif -In case the number of your source files are small, we may put everything in the private -module fragment directly. (it is suggested to add conditional include to the source -files too). But it will make the compilation of the module interface unit to be slow -when the number of the source files are not small enough. +If the number of source files is small, everything can be put in the private +module fragment directly (it is recommended to add conditional includes to the +source files as well). However, compile time performance will be bad if there +are a lot of source files to compile. -**Note that the private module fragment can only be in the primary module interface unit -and the primary module interface unit containing private module fragment should be the only -module unit of the corresponding module.** +**Note that the private module fragment can only be in the primary module +interface unit and the primary module interface unit containing the private +module fragment should be the only module unit of the corresponding module.** -In that case, you need to convert your source files (.cpp files) to module implementation units: +In this case, source files (.cpp files) must be converted to module +implementation units: .. code-block:: c++ @@ -925,45 +925,40 @@ In that case, you need to convert your source files (.cpp files) to module imple // Following off should be unchanged. ... -The module implementation unit will import the primary module implicitly. -We don't include any headers in the module implementation units -here since we want to avoid duplicated declarations between translation units. -This is the reason why we add non-exported using declarations from the third -party libraries in the primary module interface unit. - -And if you provide your library as ``libyour_library.so``, you probably need to -provide a modular one ``libyour_library_modules.so`` since you changed the ABI. - -What if there are headers only inclued by the source files -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +The module implementation unit will import the primary module implicitly. Do +not include any headers in the module implementation units as it avoids +duplicated declarations between translation units. This is why non-exported +using declarations should be added from third-party libraries in the primary +module interface unit. -The above practice may be problematic if there are headers only included by the source -files. If you're using private module fragment, you may solve the issue by including them -in the private module fragment. While it is OK to solve it by including the implementation -headers in the module purview if you're using implementation module units, it may be -suboptimal since the primary module interface units now containing entities not belongs -to the interface. +If the library is provided as ``libyour_library.so``, a modular library (e.g., +``libyour_library_modules.so``) may also need to be provided for ABI +compatibility. -If you're a perfectionist, maybe you can improve it by introducing internal module partition unit. +What if there are headers only included by the source files +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The internal module partition unit is an importable module unit which is internal -to the module itself. The concept just meets the headers only included by the source files. +The above practice may be problematic if there are headers only included by the +source files. When using a private module fragment, this issue may be solved by +including those headers in the private module fragment. While it is OK to solve +it by including the implementation headers in the module purview when using +implementation module units, it may be suboptimal because the primary module +interface units now contain entities that do not belong to the interface. -We don't show code snippet since it may be too verbose or not good or not general. -But it may not be too hard if you can understand the points of the section. +This can potentially be improved by introducing a module partition +implementation unit. An internal module partition unit is an importable +module unit which is internal to the module itself. Providing a header to skip parsing redundant headers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -It is a problem for clang to handle redeclarations between translation units. -Also there is a long standing issue in clang (`problematic include after import `_). -But even if the issue get fixed in clang someday, the users may still get slower compilation speed -and larger BMI size. So it is suggested to not include headers after importing the corresponding -library. - -However, it is not easy for users if your library are included by other dependencies. - -So the users may have to write codes like: +Many redeclarations shared between translation units causes Clang to have +slower compile-time performance. Further, there are known issues with +`include after import `_. +Even when that issue is resolved, users may still get slower compilation speed +and larger BMIs. For these reasons, it is recommended to not include headers +after importing the corresponding module. However, it is not always easy if the +library is included by other dependencies, as in: .. code-block:: c++ @@ -977,9 +972,9 @@ or import your_library; #include "third_party/A.h" // #include "your_library/a_header.h" -For such cases, we suggest the libraries providing modules and the headers at the same time -to provide a header to skip parsing all the headers in your libraries. So the users can -import your library as the following style to skip redundant handling: +For such cases, it is best if the library providing both module and header +interfaces also provides a header which skips parsing so that the library can +be imported with the following approach that skips redundant redeclarations: .. code-block:: c++ @@ -987,9 +982,9 @@ import your library as the following style to skip redundant handling: #include "your_library_imported.h" #include "third_party/A.h" // #include "your_library/a_header.h" but got skipped -The implementation of ``your_library_imported.h`` can be a set of controlling macros or -an overall controlling macro if you're using `#pragma once`. So you can convert your -headers to: +The implementation of ``your_library_imported.h`` can be a set of controlling +macros or an overall controlling macro if using `#pragma once`. Then headers +can be refactored to: .. code-block:: c++ @@ -998,25 +993,24 @@ headers to: ... #endif -If the modules imported by your library provides such headers too, remember to add them to -your ``your_library_imported.h`` too. +If the modules imported by the library provide such headers, remember to add +them to ``your_library_imported.h`` too. Importing modules ~~~~~~~~~~~~~~~~~ -When there are dependent libraries providing modules, we suggest you to import that in -your module. - -Most of the existing libraries would fall into this catagory once the std module gets available. +When there are dependent libraries providing modules, they should be imported +in your module as well. Many existing libraries will fall into this category +once the ``std`` module is more widely available. All dependent libraries providing modules ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Life gets easier if all the dependent libraries providing modules. +Of course, most of the complexity disappears if all the dependent libraries +provide modules. -You need to convert your headers to include thirdparty headers conditionally. - -Then for export-using style: +Headers need to be converted to include third-party headers conditionally. Then, +for the export-using style: .. code-block:: c++ @@ -1035,7 +1029,7 @@ Then for export-using style: using decl_n; } -For export extern-C++ style: +or, for the export extern-C++ style: .. code-block:: c++ @@ -1049,7 +1043,7 @@ For export extern-C++ style: #include "header_n.h" } -For ABI breaking style, +or, for the ABI-breaking style, .. code-block:: c++ @@ -1069,35 +1063,39 @@ For ABI breaking style, #include "source_n.cpp" #endif -We don't need the non-exported using declarations if we're using implementation module -units now. We can import thirdparty modules directly in the implementation module -units. +Non-exported ``using`` declarations are unnecessary if using implementation +module units. Instead, third-party modules can be imported directly in +implementation module units. Partial dependent libraries providing modules ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -In this case, we have to mix the use of ``include`` and ``import`` in the module of our -library. The key point here is still to remove duplicated declarations in translation -units as much as possible. If the imported modules provide headers to skip parsing their -headers, we should include that after the including. If the imported modules don't provide -the headers, we can make it ourselves if we still want to optimize it. - -Known Problems --------------- - -The following describes issues in the current implementation of modules. -Please see https://github.com/llvm/llvm-project/labels/clang%3Amodules for more issues -or file a new issue if you don't find an existing one. -If you're going to create a new issue for standard C++ modules, -please start the title with ``[C++20] [Modules]`` (or ``[C++23] [Modules]``, etc) -and add the label ``clang:modules`` (if you have permissions for that). - -For higher level support for proposals, you could visit https://clang.llvm.org/cxx_status.html. - -Including headers after import is problematic -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +If the library has to mix the use of ``include`` and ``import`` in its module, +the primary goal is still the removal of duplicated declarations in translation +units as much as possible. If the imported modules provide headers to skip +parsing their headers, those should be included after the import. If the +imported modules don't provide such a header, one can be made manually for +improved compile time performance. + +Known Issues +------------ + +The following describes issues in the current implementation of modules. Please +see +`the issues list for modules `_ +for a list of issues or to file a new issue if you don't find an existing one. +When creating a new issue for standard C++ modules, please start the title with +``[C++20] [Modules]`` (or ``[C++23] [Modules]``, etc) and add the label +``clang:modules`` if possible. + +A high-level overview of support for standards features, including modules, can +be found on the `C++ Feature Status `_ +page. + +Including headers after import is not well-supported +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -For example, the following example can be accept: +The following example is accepted: .. code-block:: c++ @@ -1110,8 +1108,8 @@ For example, the following example can be accept: return 0; } -but it will get rejected if we reverse the order of ``#include `` and -``import foo;``: +but if the order of ``#include `` and ``import foo;`` is reversed, +then the code is currently rejected: .. code-block:: c++ @@ -1126,33 +1124,31 @@ but it will get rejected if we reverse the order of ``#include `` and Both of the above examples should be accepted. -This is a limitation in the implementation. In the first example, -the compiler will see and parse first then the compiler will see the import. -So the ODR Checking and declarations merging will happen in the deserializer. -In the second example, the compiler will see the import first and the include second. -As a result, the ODR Checking and declarations merging will happen in the semantic analyzer. +This is a limitation of the implementation. In the first example, the compiler +will see and parse ```` first then it will see the ``import``. In +this case, ODR checking and declaration merging will happen in the +deserializer. In the second example, the compiler will see the ``import`` first +and the ``#include`` second which results in ODR checking and declarations +merging happening in the semantic analyzer. This is due to a divergence in the +implementation path. This is tracked by +`#61465 `_. -So there is divergence in the implementation path. It might be understandable that why -the orders matter here in the case. -(Note that "understandable" is different from "makes sense"). - -This is tracked in: https://github.com/llvm/llvm-project/issues/61465 - -Ignored PreferredName Attribute -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Due to a tricky problem, when Clang writes BMIs, Clang will ignore the ``preferred_name`` attribute, if any. -This implies that the ``preferred_name`` wouldn't show in debugger or dumping. +Ignored ``preferred_name`` Attribute +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -This is tracked in: https://github.com/llvm/llvm-project/issues/56490 +When Clang writes BMIs, it will ignore the ``preferred_name`` attribute on +declarations which use it. Thus, the preferred name will not be displayed in +the debugger as expected. This is tracked by +`#56490 `_. Don't emit macros about module declaration ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -This is covered by P1857R3. We mention it again here since users may abuse it before we implement it. +This is covered by `P1857R3 `_. It is mentioned here +because we want users to be aware that we don't yet implement it. -Someone may want to write code which could be compiled both by modules or non-modules. -A direct idea would be use macros like: +A direct approach to write code that can be compiled by both modules and +non-module builds may look like: .. code-block:: c++ @@ -1162,39 +1158,37 @@ A direct idea would be use macros like: IMPORT header_name EXPORT ... -So this file could be triggered like a module unit or a non-module unit depending on the definition -of some macros. -However, this kind of usage is forbidden by P1857R3 but we haven't implemented P1857R3 yet. -This means that is possible to write illegal modules code now, and obviously this will stop working -once P1857R3 is implemented. -A simple suggestion would be "Don't play macro tricks with module declarations". +The intent of this is that this file can be compiled like a module unit or a +non-module unit depending on the definition of some macros. However, this usage +is forbidden by P1857R3 which is not yet implemented in Clang. This means that +is possible to write invalid modules which will no longer be accepted once +P1857R3 is implemented. This is tracked by +`#56917 `_. + +Until then, it is recommended not to mix macros with module declarations. -This is tracked in: https://github.com/llvm/llvm-project/issues/56917 In consistent filename suffix requirement for importable module units ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Currently, clang requires the file name of an ``importable module unit`` should end with ``.cppm`` -(or ``.ccm``, ``.cxxm``, ``.c++m``). However, the behavior is inconsistent with other compilers. - -This is tracked in: https://github.com/llvm/llvm-project/issues/57416 - -clang-cl is not compatible with the standard C++ modules -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Now we can't use the `/clang:-fmodule-file` or `/clang:-fprebuilt-module-path` to specify -the BMI within ``clang-cl.exe``. +Currently, Clang requires the file name of an ``importable module unit`` to +have ``.cppm`` (or ``.ccm``, ``.cxxm``, ``.c++m``) as the file extension. +However, the behavior is inconsistent with other compilers. This is tracked by +`#57416 `_. -This is tracked in: https://github.com/llvm/llvm-project/issues/64118 +clang-cl is not compatible with standard C++ modules +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -false positive ODR violation diagnostic due to using inconsistent qualified but the same type -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +``/clang:-fmodule-file`` and ``/clang:-fprebuilt-module-path`` cannot be used +to specify the BMI with ``clang-cl.exe``. This is tracked by +`#64118 `_. -ODR violation is a pretty common issue when using modules. -Sometimes the program violated the One Definition Rule actually. -But sometimes it shows the compiler gives false positive diagnostics. +Incorrect ODR violation diagnostics +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -One often reported example is: +ODR violations are a common issue when using modules. Clang sometimes produces +false-positive diagnostics or fails to produce true-positive diagnostics of the +One Definition Rule. One often-reported example is: .. code-block:: c++ @@ -1222,51 +1216,49 @@ One often reported example is: export module repro; export import :part; -Currently the compiler complains about the inconsistent definition of `fun()` in -2 module units. This is incorrect. Since both definitions of `fun()` has the same -spelling and `T` refers to the same type entity finally. So the program should be -fine. - -This is tracked in https://github.com/llvm/llvm-project/issues/78850. +Currently the compiler incorrectly diagnoses the inconsistent definition of +``fun()`` in two module units. Because both definitions of ``fun()`` have the +same spelling and ``T`` refers to the same type entity, there is no ODR +violation. This is tracked by +`#78850 `_. Using TU-local entity in other units ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Module units are translation units. So the entities which should only be local to the -module unit itself shouldn't be used by other units in any means. +Module units are translation units, so the entities which should be local to +the module unit itself should never be used by other units. -In the language side, to address the idea formally, the language specification defines -the concept of ``TU-local`` and ``exposure`` in +The C++ standard defines the concept of ``TU-local`` and ``exposure`` in `basic.link/p14 `_, `basic.link/p15 `_, `basic.link/p16 `_, -`basic.link/p17 `_ and +`basic.link/p17 `_, and `basic.link/p18 `_. -However, the compiler doesn't support these 2 ideas formally. -This results in unclear and confusing diagnostic messages. -And it is worse that the compiler may import TU-local entities to other units without any -diagnostics. +However, Clang doesn't formally support these two concepts. This results in +unclear or confusing diagnostic messages. Further, Clang may import +``TU-local`` entities to other units without any diagnostics. This is tracked +by `#78173 `_. -This is tracked in https://github.com/llvm/llvm-project/issues/78173. +.. _header-units: Header Units ============ -How to build projects using header unit ---------------------------------------- +How to build projects using header units +---------------------------------------- .. warning:: - The user interfaces of header units is highly experimental. There are still - many unanswered question about how tools should interact with header units. - The user interfaces described here may change after we have progress on how - tools should support for header units. + The support for header units, including related command line options, is + experimental. There are still many unanswered question about how tools + should interact with header units. The details described here may change in + the future. Quick Start ~~~~~~~~~~~ -For the following example, +The following example: .. code-block:: c++ @@ -1275,7 +1267,7 @@ For the following example, std::cout << "Hello World.\n"; } -we could compile it as +could be compiled with: .. code-block:: console @@ -1285,14 +1277,14 @@ we could compile it as How to produce BMIs ~~~~~~~~~~~~~~~~~~~ -Similar to named modules, we could use ``--precompile`` to produce the BMI. -But we need to specify that the input file is a header by ``-xc++-system-header`` or ``-xc++-user-header``. +Similar to named modules, ``--precompile`` can be used to produce a BMI. +However, that requires specifying that the input file is a header by using +``-xc++-system-header`` or ``-xc++-user-header``. -Also we could use `-fmodule-header={user,system}` option to produce the BMI for header units -which has suffix like `.h` or `.hh`. -The value of `-fmodule-header` means the user search path or the system search path. -The default value for `-fmodule-header` is `user`. -For example, +The ``-fmodule-header={user,system}`` option can also be used to produce a BMI +for header units which have a file extension like `.h` or `.hh`. The argument to +``-fmodule-header`` specifies either the user search path or the system search +path. The default value for ``-fmodule-header`` is ``user``. For example: .. code-block:: c++ @@ -1308,16 +1300,16 @@ For example, Hello(); } -We could compile it as: +could be compiled with: .. code-block:: console $ clang++ -std=c++20 -fmodule-header foo.h -o foo.pcm $ clang++ -std=c++20 -fmodule-file=foo.pcm use.cpp -For headers which don't have a suffix, we need to pass ``-xc++-header`` -(or ``-xc++-system-header`` or ``-xc++-user-header``) to mark it as a header. -For example, +For headers which do not have a file extension, ``-xc++-header`` (or +``-xc++-system-header``, ``-xc++-user-header``) must be used to specify the +file as a header. For example: .. code-block:: c++ @@ -1332,23 +1324,25 @@ For example, $ clang++ -std=c++20 -fmodule-header=system -xc++-header iostream -o iostream.pcm $ clang++ -std=c++20 -fmodule-file=iostream.pcm use.cpp -How to specify the dependent BMIs -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +How to specify dependent BMIs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -We could use ``-fmodule-file`` to specify the BMIs, and this option may occur multiple times as well. +``-fmodule-file`` can be used to specify a dependent BMI (or multiple times for +more than one dependent BMI). -With the existing implementation ``-fprebuilt-module-path`` cannot be used for header units -(since they are nominally anonymous). -For header units, use ``-fmodule-file`` to include the relevant PCM file for each header unit. +With the existing implementation, ``-fprebuilt-module-path`` cannot be used for +header units (because they are nominally anonymous). For header units, use +``-fmodule-file`` to include the relevant PCM file for each header unit. -This is expect to be solved in future editions of the compiler either by the tooling finding and specifying -the -fmodule-file or by the use of a module-mapper that understands how to map the header name to their PCMs. +This is expect to be solved in a future version of Clang either by the compiler +finding and specifying ``-fmodule-file`` automatically, or by the use of a +module-mapper that understands how to map the header name to their PCMs. -Don't compile the BMI -~~~~~~~~~~~~~~~~~~~~~ +Compiling a header unit to an object file +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Another difference with modules is that we can't compile the BMI from a header unit. -For example: +A header unit cannot be compiled to an object file due to the semantics of +header units. For example: .. code-block:: console @@ -1356,15 +1350,13 @@ For example: # This is not allowed! $ clang++ iostream.pcm -c -o iostream.o -It makes sense due to the semantics of header units, which are just like headers. - Include translation ~~~~~~~~~~~~~~~~~~~ -The C++ spec allows the vendors to convert ``#include header-name`` to ``import header-name;`` when possible. -Currently, Clang would do this translation for the ``#include`` in the global module fragment. - -For example, the following two examples are the same: +The C++ standard allows vendors to convert ``#include header-name`` to +``import header-name;`` when possible. Currently, Clang does this translation +for the ``#include`` in the global module fragment. For example, the following +example: .. code-block:: c++ @@ -1375,7 +1367,7 @@ For example, the following two examples are the same: std::cout << "Hello.\n"; } -with the following one: +is the same as this example: .. code-block:: c++ @@ -1391,17 +1383,17 @@ with the following one: $ clang++ -std=c++20 -xc++-system-header --precompile iostream -o iostream.pcm $ clang++ -std=c++20 -fmodule-file=iostream.pcm --precompile M.cppm -o M.cpp -In the latter example, the Clang could find the BMI for the ```` -so it would try to replace the ``#include `` to ``import ;`` automatically. +In the latter example, Clang can find the BMI for ```` and so it +tries to replace the ``#include `` with ``import ;`` +automatically. -Relationships between Clang modules ------------------------------------ +Differences between Clang modules and header units +-------------------------------------------------- -Header units have pretty similar semantics with Clang modules. -The semantics of both of them are like headers. - -In fact, we could even "mimic" the sytle of header units by Clang modules: +Header units have similar semantics to Clang modules. The semantics of both are +like headers. Therefore, header units can be mimicked by Clang modules as in +the following example: .. code-block:: c++ @@ -1414,46 +1406,45 @@ In fact, we could even "mimic" the sytle of header units by Clang modules: $ clang++ -std=c++20 -fimplicit-modules -fmodule-map-file=.modulemap main.cpp -It would be simpler if we are using libcxx: +This example is simplified when using libc++: .. code-block:: console $ clang++ -std=c++20 main.cpp -fimplicit-modules -fimplicit-module-maps -Since there is already one -`module map `_ -in the source of libcxx. - -Then immediately leads to the question: why don't we implement header units through Clang header modules? +because libc++ already supplies a +`module map `_. -The main reason for this is that Clang modules have more semantics like hierarchy or -wrapping multiple headers together as a big module. -However, these things are not part of Standard C++ Header units, -and we want to avoid the impression that these additional semantics get interpreted as Standard C++ behavior. +This raises the question: why are header units not implemented through Clang +modules? -Another reason is that there are proposals to introduce module mappers to the C++ standard -(for example, https://wg21.link/p1184r2). -If we decide to reuse Clang's modulemap, we may get in trouble once we need to introduce another module mapper. +This is primarily because Clang modules have more hierarchical semantics when +wrapping multiple headers together as one module, which is not supported by +Standard C++ Header units. We want to avoid the impression that these +additional semantics get interpreted as Standard C++ behavior. -So the final answer for why we don't reuse the interface of Clang modules for header units is that -there are some differences between header units and Clang modules and that ignoring those -differences now would likely become a problem in the future. +Another reason is that there are proposals to introduce module mappers to the +C++ standard (for example, https://wg21.link/p1184r2). Reusing Clang's +``modulemap`` may be more difficult if we need to introduce another module +mapper. -Discover Dependencies -===================== +Discovering Dependencies +======================== -Prior to modules, all the translation units can be compiled parallelly. -But it is not true for the module units. The presence of module units requires -us to compile the translation units in a (topological) order. +Without use of modules, all the translation units in a project can be compiled +in parallel. However, the presence of module units requires compiling the +translation units in a topological order. -The clang-scan-deps scanner implemented -`P1689 paper `_ -to describe the order. Only named modules are supported now. +The ``clang-scan-deps`` tool can extract dependency information and produce a +JSON file conforming to the specification described in +`P1689 `_. +Only named modules are supported currently. -We need a compilation database to use clang-scan-deps. See +A compilation database is needed when using ``clang-scan-deps``. See `JSON Compilation Database Format Specification `_ -for example. Note that the ``output`` entry is necessary for clang-scan-deps -to scan P1689 format. Here is an example: +for more information about compilation databases. Note that the ``output`` +JSON attribute is necessary for ``clang-scan-deps`` to scan using the P1689 +format. For example: .. code-block:: c++ @@ -1533,13 +1524,13 @@ And here is the compilation database: } ] -And we can get the dependency information in P1689 format by: +To get the dependency information in P1689 format, use: .. code-block:: console $ clang-scan-deps -format=p1689 -compilation-database P1689.json -And we will get: +to get: .. code-block:: text @@ -1619,14 +1610,14 @@ And we will get: See the P1689 paper for the meaning of the fields. -And if the user want a finer-grained control for any reason, e.g., to scan the generated source files, -the user can choose to get the dependency information per file. For example: +Getting dependency information per file with finer-grained control (such as +scanning generated source files) is possible. For example: .. code-block:: console $ clang-scan-deps -format=p1689 -- /clang++ -std=c++20 impl_part.cppm -c -o impl_part.o -And we'll get: +will produce: .. code-block:: text @@ -1652,22 +1643,23 @@ And we'll get: "version": 1 } -In this way, we can pass the single command line options after the ``--``. -Then clang-scan-deps will extract the necessary information from the options. -Note that we need to specify the path to the compiler executable instead of saying -``clang++`` simply. +Individual command line options can be specified after ``--``. +``clang-scan-deps`` will extract the necessary information from the specified +options. Note that the path to the compiler executable needs to be specified +explicitly instead of using ``clang++`` directly. -The users may want the scanner to get the transitional dependency information for headers. -Otherwise, the users have to scan twice for the project, once for headers and once for modules. -To address the requirement, clang-scan-deps will recognize the specified preprocessor options -in the given command line and generate the corresponding dependency information. For example, +Users may want the scanner to get the transitional dependency information for +headers. Otherwise, the project has to be scanned twice, once for headers and +once for modules. To address this, ``clang-scan-deps`` will recognize the +specified preprocessor options in the given command line and generate the +corresponding dependency information. For example: .. code-block:: console $ clang-scan-deps -format=p1689 -- ../bin/clang++ -std=c++20 impl_part.cppm -c -o impl_part.o -MD -MT impl_part.ddi -MF impl_part.dep $ cat impl_part.dep -We will get: +will produce: .. code-block:: text @@ -1679,41 +1671,41 @@ We will get: /usr/include/bits/types/__locale_t.h \ ... -When clang-scan-deps detects ``-MF`` option, clang-scan-deps will try to write the +When ``clang-scan-deps`` detects the ``-MF`` option, it will try to write the dependency information for headers to the file specified by ``-MF``. Possible Issues: Failed to find system headers ---------------------------------------------- -In case the users encounter errors like ``fatal error: 'stddef.h' file not found``, -probably the specified ``/clang++`` refers to a symlink -instead a real binary. There are 4 potential solutions to the problem: - -* (1) End users can resolve the issue by pointing the specified compiler executable to - the real binary instead of the symlink. -* (2) End users can invoke ``/clang++ -print-resource-dir`` - to get the corresponding resource directory for your compiler and add that directory - to the include search paths manually in the build scripts. -* (3) Build systems that use a compilation database as the input for clang-scan-deps - scanner, the build system can add the flag ``--resource-dir-recipe invoke-compiler`` to - the clang-scan-deps scanner to calculate the resources directory dynamically. - The calculation happens only once for a unique ``/clang++``. -* (4) For build systems that invokes the clang-scan-deps scanner per file, repeatedly - calculating the resource directory may be inefficient. In such cases, the build - system can cache the resource directory by itself and pass ``-resource-dir `` - explicitly in the command line options: +If encountering an error like ``fatal error: 'stddef.h' file not found``, +the specified ``/clang++`` probably refers to a +symlink instead a real binary. There are four potential solutions to the +problem: -.. code-block:: console +1. Point the specified compiler executable to the real binary instead of the + symlink. +2. Invoke ``/clang++ -print-resource-dir`` to get + the corresponding resource directory for your compiler and add that + directory to the include search paths manually in the build scripts. +3. For build systems that use a compilation database as the input for + ``clang-scan-deps``, the build system can add the + ``--resource-dir-recipe invoke-compiler`` option when executing + ``clang-scan-deps`` to calculate the resource directory dynamically. + The calculation happens only once for a unique ``/clang++``. +4. For build systems that invoke ``clang-scan-deps`` per file, repeatedly + calculating the resource directory may be inefficient. In such cases, the + build system can cache the resource directory and specify + ``-resource-dir `` explicitly, as in: + + .. code-block:: console - $ clang-scan-deps -format=p1689 -- /clang++ -std=c++20 -resource-dir mod.cppm -c -o mod.o + $ clang-scan-deps -format=p1689 -- /clang++ -std=c++20 -resource-dir mod.cppm -c -o mod.o Import modules with clang-repl ============================== -We're able to import C++20 named modules with clang-repl. - -Let's start with a simple example: +``clang-repl`` supports importing C++20 named modules. For example: .. code-block:: c++ @@ -1723,7 +1715,7 @@ Let's start with a simple example: return "Hello Interpreter for Modules!"; } -We still need to compile the named module in ahead. +The named module still needs to be compiled ahead of time. .. code-block:: console @@ -1731,10 +1723,9 @@ We still need to compile the named module in ahead. $ clang++ M.pcm -c -o M.o $ clang++ -shared M.o -o libM.so -Note that we need to compile the module unit into a dynamic library so that the clang-repl -can load the object files of the module units. - -Then we are able to import module ``M`` in clang-repl. +Note that the module unit needs to be compiled as a dynamic library so that +``clang-repl`` can load the object files of the module units. Then it is +possible to import module ``M`` in clang-repl. .. code-block:: console @@ -1753,17 +1744,18 @@ Possible Questions How modules speed up compilation -------------------------------- -A classic theory for the reason why modules speed up the compilation is: -if there are ``n`` headers and ``m`` source files and each header is included by each source file, -then the complexity of the compilation is ``O(n*m)``; -But if there are ``n`` module interfaces and ``m`` source files, the complexity of the compilation is -``O(n+m)``. So, using modules would be a big win when scaling. -In a simpler word, we could get rid of many redundant compilations by using modules. +A classic theory for the reason why modules speed up the compilation is: if +there are ``n`` headers and ``m`` source files and each header is included by +each source file, then the complexity of the compilation is ``O(n*m)``. +However, if there are ``n`` module interfaces and ``m`` source files, the +complexity of the compilation is ``O(n+m)``. Therefore, using modules would be +a significant improvement at scale. More simply, use of modules causes many of +the redundant compilations to no longer be necessary. -Roughly, this theory is correct. But the problem is that it is too rough. -The behavior depends on the optimization level, as we will illustrate below. +While this is accurate at a high level, this depends greatly on the +optimization level, as illustrated below. -First is ``O0``. The compilation process is described in the following graph. +First is ``-O0``. The compilation process is described in the following graph. .. code-block:: none @@ -1771,13 +1763,13 @@ First is ``O0``. The compilation process is described in the following graph. │ │ │ │ └---parsing----sema----codegen--┴----- transformations ---- codegen ----┴---- codegen --┘ - ┌---------------------------------------------------------------------------------------┐ + ├---------------------------------------------------------------------------------------┐ | │ | source file │ | │ └---------------------------------------------------------------------------------------┘ - ┌--------┐ + ├--------┐ │ │ │imported│ │ │ @@ -1785,18 +1777,17 @@ First is ``O0``. The compilation process is described in the following graph. │ │ └--------┘ -Here we can see that the source file (could be a non-module unit or a module unit) would get processed by the -whole pipeline. -But the imported code would only get involved in semantic analysis, which is mainly about name lookup, -overload resolution and template instantiation. -All of these processes are fast relative to the whole compilation process. -More importantly, the imported code only needs to be processed once in frontend code generation, -as well as the whole middle end and backend. -So we could get a big win for the compilation time in O0. +In this case, the source file (which could be a non-module unit or a module +unit) would get processed by the entire pipeline. However, the imported code +would only get involved in semantic analysis, which, for the most part, is name +lookup, overload resolution, and template instantiation. All of these processes +are fast relative to the whole compilation process. More importantly, the +imported code only needs to be processed once during frontend code generation, +as well as the whole middle end and backend. So we could get a big win for the +compilation time in ``-O0``. -But with optimizations, things are different: - -(we omit ``code generation`` part for each end due to the limited space) +But with optimizations, things are different (the ``code generation`` part for +each end is omitted due to limited space): .. code-block:: none @@ -1804,12 +1795,12 @@ But with optimizations, things are different: │ │ │ │ └--- parsing ---- sema -----┴--- optimizations --- IPO ---- optimizations---┴--- optimizations -┘ - ┌-----------------------------------------------------------------------------------------------┐ + ├-----------------------------------------------------------------------------------------------┐ │ │ │ source file │ │ │ └-----------------------------------------------------------------------------------------------┘ - ┌---------------------------------------┐ + ├---------------------------------------┐ │ │ │ │ │ imported code │ @@ -1817,27 +1808,29 @@ But with optimizations, things are different: │ │ └---------------------------------------┘ -It would be very unfortunate if we end up with worse performance after using modules. -The main concern is that when we compile a source file, the compiler needs to see the function body -of imported module units so that it can perform IPO (InterProcedural Optimization, primarily inlining -in practice) to optimize functions in current source file with the help of the information provided by -the imported module units. -In other words, the imported code would be processed again and again in importee units -by optimizations (including IPO itself). -The optimizations before IPO and the IPO itself are the most time-consuming part in whole compilation process. -So from this perspective, we might not be able to get the improvements described in the theory. -But we could still save the time for optimizations after IPO and the whole backend. - -Overall, at ``O0`` the implementations of functions defined in a module will not impact module users, -but at higher optimization levels the definitions of such functions are provided to user compilations for the -purposes of optimization (but definitions of these functions are still not included in the use's object file)- -this means the build speedup at higher optimization levels may be lower than expected given ``O0`` experience, -but does provide by more optimization opportunities. +It would be very unfortunate if we end up with worse performance when using +modules. The main concern is that when a source file is compiled, the compiler +needs to see the body of imported module units so that it can perform IPO +(InterProcedural Optimization, primarily inlining in practice) to optimize +functions in the current source file with the help of the information provided +by the imported module units. In other words, the imported code would be +processed again and again in importee units by optimizations (including IPO +itself). The optimizations before IPO and IPO itself are the most time-consuming +part in whole compilation process. So from this perspective, it might not be +possible to get the compile time improvements described, but there could be +time savings for optimizations after IPO and the whole backend. + +Overall, at ``-O0`` the implementations of functions defined in a module will +not impact module users, but at higher optimization levels the definitions of +such functions are provided to user compilations for the purposes of +optimization (but definitions of these functions are still not included in the +use's object file). This means the build speedup at higher optimization levels +may be lower than expected given ``-O0`` experience, but does provide more +optimization opportunities. Interoperability with Clang Modules ----------------------------------- -We **wish** to support clang modules and standard c++ modules at the same time, -but the mixed using form is not well used/tested yet. - -Please file new github issues as you find interoperability problems. +We **wish** to support Clang modules and standard C++ modules at the same time, +but the mixing them together is not well used/tested yet. Please file new +GitHub issues as you find interoperability problems. -- GitLab From 2ceb1291ef3ddb87cb58030cd61d965f4030338f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 8 May 2024 16:51:45 +0100 Subject: [PATCH 043/328] [X86] Add canScaleShuffleElements helper. NFC. Returns true if the shuffle mask can be rescaled to the requested number of elements. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 3ae68c438aa7..126577a4d59e 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -3738,6 +3738,11 @@ static bool scaleShuffleElements(ArrayRef Mask, unsigned NumDstElts, return false; } +static bool canScaleShuffleElements(ArrayRef Mask, unsigned NumDstElts) { + SmallVector ScaledMask; + return scaleShuffleElements(Mask, NumDstElts, ScaledMask); +} + /// Returns true if Elt is a constant zero or a floating point constant +0.0. bool X86::isZeroNode(SDValue Elt) { return isNullConstant(Elt) || isNullFPConstant(Elt); @@ -46684,14 +46689,14 @@ static SDValue combineSetCCMOVMSK(SDValue EFLAGS, X86::CondCode &CC, // To address this, we check that we can scale the shuffle mask to MOVMSK // element width (this will ensure "high" elements match). Its slightly overly // conservative, but fine for an edge case fold. - SmallVector ShuffleMask, ScaledMaskUnused; + SmallVector ShuffleMask; SmallVector ShuffleInputs; if (NumElts <= CmpBits && getTargetShuffleInputs(peekThroughBitcasts(Vec), ShuffleInputs, ShuffleMask, DAG) && ShuffleInputs.size() == 1 && isCompletePermute(ShuffleMask) && ShuffleInputs[0].getValueSizeInBits() == VecVT.getSizeInBits() && - scaleShuffleElements(ShuffleMask, NumElts, ScaledMaskUnused)) { + canScaleShuffleElements(ShuffleMask, NumElts)) { SDLoc DL(EFLAGS); SDValue Result = DAG.getBitcast(VecVT, ShuffleInputs[0]); Result = DAG.getNode(X86ISD::MOVMSK, DL, MVT::i32, Result); -- GitLab From a6171900a446c85c3b53a4a9deba16b746f9f77f Mon Sep 17 00:00:00 2001 From: Harald van Dijk Date: Wed, 8 May 2024 17:02:25 +0100 Subject: [PATCH 044/328] [RemoveDIs] Change remapDbgVariableRecord to remapDbgRecord (#91456) We need to remap any DbgRecord, not just DbgVariableRecords. This is the followup to #91447. Co-authored-by: PietroGhg --- .../llvm/Transforms/Utils/ValueMapper.h | 34 ++++++++--------- .../Transforms/Scalar/SimpleLoopUnswitch.cpp | 5 +-- llvm/lib/Transforms/Utils/CloneFunction.cpp | 17 ++++----- .../Transforms/Utils/LoopRotationUtils.cpp | 10 ++--- .../Transforms/Utils/LoopUnrollRuntime.cpp | 5 +-- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 9 ++--- llvm/lib/Transforms/Utils/ValueMapper.cpp | 10 ++--- .../Transforms/Utils/CloningTest.cpp | 37 +++++++++++++++++++ 8 files changed, 78 insertions(+), 49 deletions(-) diff --git a/llvm/include/llvm/Transforms/Utils/ValueMapper.h b/llvm/include/llvm/Transforms/Utils/ValueMapper.h index 54e3e62dc3af..743cfeb7ef3f 100644 --- a/llvm/include/llvm/Transforms/Utils/ValueMapper.h +++ b/llvm/include/llvm/Transforms/Utils/ValueMapper.h @@ -180,9 +180,8 @@ public: Constant *mapConstant(const Constant &C); void remapInstruction(Instruction &I); - void remapDbgVariableRecord(Module *M, DbgVariableRecord &V); - void remapDbgVariableRecordRange(Module *M, - iterator_range Range); + void remapDbgRecord(Module *M, DbgRecord &V); + void remapDbgRecordRange(Module *M, iterator_range Range); void remapFunction(Function &F); void remapGlobalObjectMetadata(GlobalObject &GO); @@ -268,26 +267,25 @@ inline void RemapInstruction(Instruction *I, ValueToValueMapTy &VM, ValueMapper(VM, Flags, TypeMapper, Materializer).remapInstruction(*I); } -/// Remap the Values used in the DbgVariableRecord \a V using the value map \a +/// Remap the Values used in the DbgRecord \a DR using the value map \a /// VM. -inline void RemapDbgVariableRecord(Module *M, DbgVariableRecord *V, - ValueToValueMapTy &VM, - RemapFlags Flags = RF_None, - ValueMapTypeRemapper *TypeMapper = nullptr, - ValueMaterializer *Materializer = nullptr) { - ValueMapper(VM, Flags, TypeMapper, Materializer) - .remapDbgVariableRecord(M, *V); +inline void RemapDbgRecord(Module *M, DbgRecord *DR, ValueToValueMapTy &VM, + RemapFlags Flags = RF_None, + ValueMapTypeRemapper *TypeMapper = nullptr, + ValueMaterializer *Materializer = nullptr) { + ValueMapper(VM, Flags, TypeMapper, Materializer).remapDbgRecord(M, *DR); } -/// Remap the Values used in the DbgVariableRecord \a V using the value map \a +/// Remap the Values used in the DbgRecords \a Range using the value map \a /// VM. -inline void -RemapDbgVariableRecordRange(Module *M, iterator_range Range, - ValueToValueMapTy &VM, RemapFlags Flags = RF_None, - ValueMapTypeRemapper *TypeMapper = nullptr, - ValueMaterializer *Materializer = nullptr) { +inline void RemapDbgRecordRange(Module *M, + iterator_range Range, + ValueToValueMapTy &VM, + RemapFlags Flags = RF_None, + ValueMapTypeRemapper *TypeMapper = nullptr, + ValueMaterializer *Materializer = nullptr) { ValueMapper(VM, Flags, TypeMapper, Materializer) - .remapDbgVariableRecordRange(M, Range); + .remapDbgRecordRange(M, Range); } /// Remap the operands, metadata, arguments, and instructions of a function. diff --git a/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp b/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp index d763b1ee0aa1..002ed381a4fd 100644 --- a/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp +++ b/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp @@ -1261,9 +1261,8 @@ static BasicBlock *buildClonedLoopBlocks( Module *M = ClonedPH->getParent()->getParent(); for (auto *ClonedBB : NewBlocks) for (Instruction &I : *ClonedBB) { - RemapDbgVariableRecordRange(M, I.getDbgRecordRange(), VMap, - RF_NoModuleLevelChanges | - RF_IgnoreMissingLocals); + RemapDbgRecordRange(M, I.getDbgRecordRange(), VMap, + RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); RemapInstruction(&I, VMap, RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); if (auto *II = dyn_cast(&I)) diff --git a/llvm/lib/Transforms/Utils/CloneFunction.cpp b/llvm/lib/Transforms/Utils/CloneFunction.cpp index 6a3b3faac77d..981183682b8b 100644 --- a/llvm/lib/Transforms/Utils/CloneFunction.cpp +++ b/llvm/lib/Transforms/Utils/CloneFunction.cpp @@ -278,8 +278,8 @@ void llvm::CloneFunctionInto(Function *NewFunc, const Function *OldFunc, // attached debug-info records. for (Instruction &II : *BB) { RemapInstruction(&II, VMap, RemapFlag, TypeMapper, Materializer); - RemapDbgVariableRecordRange(II.getModule(), II.getDbgRecordRange(), VMap, - RemapFlag, TypeMapper, Materializer); + RemapDbgRecordRange(II.getModule(), II.getDbgRecordRange(), VMap, + RemapFlag, TypeMapper, Materializer); } // Only update !llvm.dbg.cu for DifferentModule (not CloneModule). In the @@ -867,10 +867,10 @@ void llvm::CloneAndPruneIntoFromInst(Function *NewFunc, const Function *OldFunc, Function::iterator Begin = cast(VMap[StartingBB])->getIterator(); for (BasicBlock &BB : make_range(Begin, NewFunc->end())) { for (Instruction &I : BB) { - RemapDbgVariableRecordRange(I.getModule(), I.getDbgRecordRange(), VMap, - ModuleLevelChanges ? RF_None - : RF_NoModuleLevelChanges, - TypeMapper, Materializer); + RemapDbgRecordRange(I.getModule(), I.getDbgRecordRange(), VMap, + ModuleLevelChanges ? RF_None + : RF_NoModuleLevelChanges, + TypeMapper, Materializer); } } @@ -969,9 +969,8 @@ void llvm::remapInstructionsInBlocks(ArrayRef Blocks, // Rewrite the code to refer to itself. for (auto *BB : Blocks) { for (auto &Inst : *BB) { - RemapDbgVariableRecordRange( - Inst.getModule(), Inst.getDbgRecordRange(), VMap, - RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); + RemapDbgRecordRange(Inst.getModule(), Inst.getDbgRecordRange(), VMap, + RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); RemapInstruction(&Inst, VMap, RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); } diff --git a/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp b/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp index 5cd96412a322..08ba65d9483e 100644 --- a/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp +++ b/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp @@ -639,9 +639,8 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { !NextDbgInsts.empty()) { auto DbgValueRange = LoopEntryBranch->cloneDebugInfoFrom(Inst, NextDbgInsts.begin()); - RemapDbgVariableRecordRange(M, DbgValueRange, ValueMap, - RF_NoModuleLevelChanges | - RF_IgnoreMissingLocals); + RemapDbgRecordRange(M, DbgValueRange, ValueMap, + RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); // Erase anything we've seen before. for (DbgVariableRecord &DVR : make_early_inc_range(filterDbgVars(DbgValueRange))) @@ -666,9 +665,8 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { if (LoopEntryBranch->getParent()->IsNewDbgInfoFormat && !NextDbgInsts.empty()) { auto Range = C->cloneDebugInfoFrom(Inst, NextDbgInsts.begin()); - RemapDbgVariableRecordRange(M, Range, ValueMap, - RF_NoModuleLevelChanges | - RF_IgnoreMissingLocals); + RemapDbgRecordRange(M, Range, ValueMap, + RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); NextDbgInsts = DbgMarker::getEmptyDbgRecordRange(); // Erase anything we've seen before. for (DbgVariableRecord &DVR : diff --git a/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp b/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp index 2d5b5f967ffb..e1af02829c1d 100644 --- a/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp +++ b/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp @@ -917,9 +917,8 @@ bool llvm::UnrollRuntimeLoopRemainder( for (Instruction &I : *BB) { RemapInstruction(&I, VMap, RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); - RemapDbgVariableRecordRange(M, I.getDbgRecordRange(), VMap, - RF_NoModuleLevelChanges | - RF_IgnoreMissingLocals); + RemapDbgRecordRange(M, I.getDbgRecordRange(), VMap, + RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); } } diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index 5a44a11ecfd2..23a896c59bf6 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -1124,9 +1124,8 @@ static void CloneInstructionsIntoPredecessorBlockAndUpdateSSAUses( NewBonusInst->insertInto(PredBlock, PTI->getIterator()); auto Range = NewBonusInst->cloneDebugInfoFrom(&BonusInst); - RemapDbgVariableRecordRange(NewBonusInst->getModule(), Range, VMap, - RF_NoModuleLevelChanges | - RF_IgnoreMissingLocals); + RemapDbgRecordRange(NewBonusInst->getModule(), Range, VMap, + RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); if (isa(BonusInst)) continue; @@ -3860,8 +3859,8 @@ static bool performBranchToCommonDestFolding(BranchInst *BI, BranchInst *PBI, PredBlock->getTerminator()->cloneDebugInfoFrom(BB->getTerminator()); for (DbgVariableRecord &DVR : filterDbgVars(PredBlock->getTerminator()->getDbgRecordRange())) { - RemapDbgVariableRecord(M, &DVR, VMap, - RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); + RemapDbgRecord(M, &DVR, VMap, + RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); } } diff --git a/llvm/lib/Transforms/Utils/ValueMapper.cpp b/llvm/lib/Transforms/Utils/ValueMapper.cpp index 1c877ee937fb..1696e9c72673 100644 --- a/llvm/lib/Transforms/Utils/ValueMapper.cpp +++ b/llvm/lib/Transforms/Utils/ValueMapper.cpp @@ -1236,14 +1236,14 @@ void ValueMapper::remapInstruction(Instruction &I) { FlushingMapper(pImpl)->remapInstruction(&I); } -void ValueMapper::remapDbgVariableRecord(Module *M, DbgVariableRecord &V) { - FlushingMapper(pImpl)->remapDbgRecord(V); +void ValueMapper::remapDbgRecord(Module *M, DbgRecord &DR) { + FlushingMapper(pImpl)->remapDbgRecord(DR); } -void ValueMapper::remapDbgVariableRecordRange( +void ValueMapper::remapDbgRecordRange( Module *M, iterator_range Range) { - for (DbgVariableRecord &DVR : filterDbgVars(Range)) { - remapDbgVariableRecord(M, DVR); + for (DbgRecord &DR : Range) { + remapDbgRecord(M, DR); } } diff --git a/llvm/unittests/Transforms/Utils/CloningTest.cpp b/llvm/unittests/Transforms/Utils/CloningTest.cpp index 6f4e860d6046..1d0d56a2099c 100644 --- a/llvm/unittests/Transforms/Utils/CloningTest.cpp +++ b/llvm/unittests/Transforms/Utils/CloningTest.cpp @@ -1122,4 +1122,41 @@ TEST_F(CloneModule, IFunc) { EXPECT_EQ("resolver", Resolver->getName()); EXPECT_EQ(GlobalValue::PrivateLinkage, Resolver->getLinkage()); } + +TEST_F(CloneModule, CloneDbgLabel) { + LLVMContext Context; + + std::unique_ptr M = parseIR(Context, + R"M( +define void @noop(ptr nocapture noundef writeonly align 4 %dst) local_unnamed_addr !dbg !3 { +entry: + %call = tail call spir_func i64 @foo(i32 noundef 0) + #dbg_label(!11, !12) + store i64 %call, ptr %dst, align 4 + ret void +} + +declare i64 @foo(i32 noundef) local_unnamed_addr + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 19.0.0git", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug) +!1 = !DIFile(filename: "", directory: "foo") +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = distinct !DISubprogram(name: "noop", scope: !4, file: !4, line: 17, type: !5, scopeLine: 17, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !9) +!4 = !DIFile(filename: "file", directory: "foo") +!5 = !DISubroutineType(types: !6) +!6 = !{null, !7} +!7 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !8, size: 64) +!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!9 = !{} +!11 = !DILabel(scope: !3, name: "foo", file: !4, line: 23) +!12 = !DILocation(line: 23, scope: !3) +)M"); + + ASSERT_FALSE(verifyModule(*M, &errs())); + auto NewM = llvm::CloneModule(*M); + EXPECT_FALSE(verifyModule(*NewM, &errs())); } +} // namespace -- GitLab From 5636eb89bd69f9c55f4e4aeafaa8c04aa99e5c84 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 8 May 2024 17:05:33 +0100 Subject: [PATCH 045/328] [X86] combineBlendOfPermutes - allow whole-lane permutation on AVX1 targets. dd4bf22b9380e797362fac1415a1796da338b2db fixed #91433 but meant we couldn't use vperm2f128 to permute entire 128-bit lanes - if the new 256-bit permutation mask can be scaled to 2x128-bit elements, then we can still fold. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 7 +++++-- llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll | 3 +-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 126577a4d59e..0410cc33ca33 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -40161,9 +40161,12 @@ combineBlendOfPermutes(MVT VT, SDValue N0, SDValue N1, ArrayRef BlendMask, return SDValue(); } - // Don't introduce lane-crossing permutes without AVX2. + // Don't introduce lane-crossing permutes without AVX2, unless it can be + // widened to a lane permute (vperm2f128). if (VT.is256BitVector() && !Subtarget.hasAVX2() && - isLaneCrossingShuffleMask(128, VT.getScalarSizeInBits(), NewPermuteMask)) + isLaneCrossingShuffleMask(128, VT.getScalarSizeInBits(), + NewPermuteMask) && + !canScaleShuffleElements(NewPermuteMask, 2)) return SDValue(); SDValue NewBlend = diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll index 0c65f756f296..81ce14132c87 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll @@ -308,9 +308,8 @@ define <4 x float> @combine_vpermilvar_4f32_as_insertps(<4 x float> %a0) { define <8 x i32> @combine_blend_of_permutes_v8i32(<4 x i64> %a0, <4 x i64> %a1) { ; AVX1-LABEL: combine_blend_of_permutes_v8i32: ; AVX1: # %bb.0: +; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1] -; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm1[2,3,0,1] -; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3,4],ymm0[5,6],ymm1[7] ; AVX1-NEXT: ret{{[l|q]}} ; ; AVX2-LABEL: combine_blend_of_permutes_v8i32: -- GitLab From 6d8901488f160dd92aea5b98fcc21c7fa7c1cbe6 Mon Sep 17 00:00:00 2001 From: "S. Bharadwaj Yadavalli" Date: Wed, 8 May 2024 12:20:41 -0400 Subject: [PATCH 046/328] [DXIL] Set DXIL Version in DXIL target triple based on shader model version (#91407) This change set restores commit 080978dd2067d0c9ea7e229aa7696c2480d89ef1 that was reverted to address ASAN failures and includes a fix for the ASAN failures. Following is the description of the change: An earlier commit provided a way to decouple DXIL version from Shader Model version by representing the DXIL version as `SubArch` in the DXIL Target Triple and adding corresponding valid DXIL Arch types. This change constructs DXIL target triple with DXIL version that is deduced from Shader Model version specified in the following scenarios: 1. When compilation target profile is specified: For e.g., DXIL target triple `dxilv1.8-unknown-shader6.8-library` is constructed when `-T lib_6_8` is specified. 2. When DXIL target triple without DXIL version is specified: For e.g., DXIL target triple `dxilv1.8-pc-shadermodel6.8-library` is constructed when `-mtriple=dxil-pc-shadermodel6.8-library` is specified. Updated relevant HLSL tests that check for target triple. --- clang/lib/Basic/Targets.cpp | 2 +- clang/lib/Driver/ToolChains/HLSL.cpp | 44 +++++++++- clang/test/CodeGenHLSL/basic-target.c | 2 +- clang/test/Driver/dxc_dxv_path.hlsl | 6 +- .../enable_16bit_types_validation.hlsl | 4 +- clang/unittests/Driver/DXCModeTest.cpp | 22 ++--- llvm/include/llvm/TargetParser/Triple.h | 1 + llvm/lib/IR/Verifier.cpp | 4 +- llvm/lib/TargetParser/Triple.cpp | 86 +++++++++++++++++++ llvm/unittests/TargetParser/TripleTest.cpp | 16 ++++ 10 files changed, 166 insertions(+), 21 deletions(-) diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index e3283510c6aa..dc1792b3471e 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -760,7 +760,7 @@ using namespace clang::targets; TargetInfo * TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, const std::shared_ptr &Opts) { - llvm::Triple Triple(Opts->Triple); + llvm::Triple Triple(llvm::Triple::normalize(Opts->Triple)); // Construct the target std::unique_ptr Target = AllocateTarget(Triple, *Opts); diff --git a/clang/lib/Driver/ToolChains/HLSL.cpp b/clang/lib/Driver/ToolChains/HLSL.cpp index 558e4db46f81..8286e3be2180 100644 --- a/clang/lib/Driver/ToolChains/HLSL.cpp +++ b/clang/lib/Driver/ToolChains/HLSL.cpp @@ -98,9 +98,49 @@ std::optional tryParseProfile(StringRef Profile) { else if (llvm::getAsUnsignedInteger(Parts[2], 0, Minor)) return std::nullopt; - // dxil-unknown-shadermodel-hull + // Determine DXIL version using the minor version number of Shader + // Model version specified in target profile. Prior to decoupling DXIL version + // numbering from that of Shader Model DXIL version 1.Y corresponds to SM 6.Y. + // E.g., dxilv1.Y-unknown-shadermodelX.Y-hull llvm::Triple T; - T.setArch(Triple::ArchType::dxil); + Triple::SubArchType SubArch = llvm::Triple::NoSubArch; + switch (Minor) { + case 0: + SubArch = llvm::Triple::DXILSubArch_v1_0; + break; + case 1: + SubArch = llvm::Triple::DXILSubArch_v1_1; + break; + case 2: + SubArch = llvm::Triple::DXILSubArch_v1_2; + break; + case 3: + SubArch = llvm::Triple::DXILSubArch_v1_3; + break; + case 4: + SubArch = llvm::Triple::DXILSubArch_v1_4; + break; + case 5: + SubArch = llvm::Triple::DXILSubArch_v1_5; + break; + case 6: + SubArch = llvm::Triple::DXILSubArch_v1_6; + break; + case 7: + SubArch = llvm::Triple::DXILSubArch_v1_7; + break; + case 8: + SubArch = llvm::Triple::DXILSubArch_v1_8; + break; + case OfflineLibMinor: + // Always consider minor version x as the latest supported DXIL version + SubArch = llvm::Triple::LatestDXILSubArch; + break; + default: + // No DXIL Version corresponding to specified Shader Model version found + return std::nullopt; + } + T.setArch(Triple::ArchType::dxil, SubArch); T.setOSName(Triple::getOSTypeName(Triple::OSType::ShaderModel).str() + VersionTuple(Major, Minor).getAsString()); T.setEnvironment(Kind); diff --git a/clang/test/CodeGenHLSL/basic-target.c b/clang/test/CodeGenHLSL/basic-target.c index 8db711c3f2a5..b97ebf90a7a1 100644 --- a/clang/test/CodeGenHLSL/basic-target.c +++ b/clang/test/CodeGenHLSL/basic-target.c @@ -7,4 +7,4 @@ // RUN: %clang -target dxil-pc-shadermodel6.0-geometry -S -emit-llvm -o - %s | FileCheck %s // CHECK: target datalayout = "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:32-f64:64-n8:16:32:64" -// CHECK: target triple = "dxil-pc-shadermodel6.0-{{[a-z]+}}" +// CHECK: target triple = "dxilv1.0-pc-shadermodel6.0-{{[a-z]+}}" diff --git a/clang/test/Driver/dxc_dxv_path.hlsl b/clang/test/Driver/dxc_dxv_path.hlsl index 3d8e90d0d919..4845de11d5b0 100644 --- a/clang/test/Driver/dxc_dxv_path.hlsl +++ b/clang/test/Driver/dxc_dxv_path.hlsl @@ -7,12 +7,12 @@ // DXV_PATH:dxv{{(.exe)?}}" "-" "-o" "-" // RUN: %clang_dxc -I test -Vd -Tlib_6_3 -### %s 2>&1 | FileCheck %s --check-prefix=VD -// VD:"-cc1"{{.*}}"-triple" "dxil-unknown-shadermodel6.3-library" +// VD:"-cc1"{{.*}}"-triple" "dxilv1.3-unknown-shadermodel6.3-library" // VD-NOT:dxv not found // RUN: %clang_dxc -Tlib_6_3 -ccc-print-bindings --dxv-path=%T -Fo %t.dxo %s 2>&1 | FileCheck %s --check-prefix=BINDINGS -// BINDINGS: "dxil-unknown-shadermodel6.3-library" - "clang", inputs: ["[[INPUT:.+]]"], output: "[[DXC:.+]].dxo" -// BINDINGS-NEXT: "dxil-unknown-shadermodel6.3-library" - "hlsl::Validator", inputs: ["[[DXC]].dxo"] +// BINDINGS: "dxilv1.3-unknown-shadermodel6.3-library" - "clang", inputs: ["[[INPUT:.+]]"], output: "[[DXC:.+]].dxo" +// BINDINGS-NEXT: "dxilv1.3-unknown-shadermodel6.3-library" - "hlsl::Validator", inputs: ["[[DXC]].dxo"] // RUN: %clang_dxc -Tlib_6_3 -ccc-print-phases --dxv-path=%T -Fo %t.dxc %s 2>&1 | FileCheck %s --check-prefix=PHASES diff --git a/clang/test/Options/enable_16bit_types_validation.hlsl b/clang/test/Options/enable_16bit_types_validation.hlsl index 89fe26790c52..bcb217e8982e 100644 --- a/clang/test/Options/enable_16bit_types_validation.hlsl +++ b/clang/test/Options/enable_16bit_types_validation.hlsl @@ -9,11 +9,11 @@ // HV_invalid_2017: error: '-enable-16bit-types' option requires target HLSL Version >= 2018 and shader model >= 6.2, but HLSL Version is 'hlsl2017' and shader model is '6.4' // TP_invalid: error: '-enable-16bit-types' option requires target HLSL Version >= 2018 and shader model >= 6.2, but HLSL Version is 'hlsl2021' and shader model is '6.0' -// valid_2021: "dxil-unknown-shadermodel6.4-library" +// valid_2021: "dxilv1.4-unknown-shadermodel6.4-library" // valid_2021-SAME: "-std=hlsl2021" // valid_2021-SAME: "-fnative-half-type" -// valid_2018: "dxil-unknown-shadermodel6.4-library" +// valid_2018: "dxilv1.4-unknown-shadermodel6.4-library" // valid_2018-SAME: "-std=hlsl2018" // valid_2018-SAME: "-fnative-half-type" diff --git a/clang/unittests/Driver/DXCModeTest.cpp b/clang/unittests/Driver/DXCModeTest.cpp index b3767c042edb..416723d498a2 100644 --- a/clang/unittests/Driver/DXCModeTest.cpp +++ b/clang/unittests/Driver/DXCModeTest.cpp @@ -68,25 +68,27 @@ TEST(DxcModeTest, TargetProfileValidation) { IntrusiveRefCntPtr DiagOpts = new DiagnosticOptions(); DiagnosticsEngine Diags(DiagID, &*DiagOpts, DiagConsumer); - validateTargetProfile("-Tvs_6_0", "dxil--shadermodel6.0-vertex", + validateTargetProfile("-Tvs_6_0", "dxilv1.0--shadermodel6.0-vertex", InMemoryFileSystem, Diags); - validateTargetProfile("-Ths_6_1", "dxil--shadermodel6.1-hull", + validateTargetProfile("-Ths_6_1", "dxilv1.1--shadermodel6.1-hull", InMemoryFileSystem, Diags); - validateTargetProfile("-Tds_6_2", "dxil--shadermodel6.2-domain", + validateTargetProfile("-Tds_6_2", "dxilv1.2--shadermodel6.2-domain", InMemoryFileSystem, Diags); - validateTargetProfile("-Tds_6_2", "dxil--shadermodel6.2-domain", + validateTargetProfile("-Tds_6_2", "dxilv1.2--shadermodel6.2-domain", InMemoryFileSystem, Diags); - validateTargetProfile("-Tgs_6_3", "dxil--shadermodel6.3-geometry", + validateTargetProfile("-Tgs_6_3", "dxilv1.3--shadermodel6.3-geometry", InMemoryFileSystem, Diags); - validateTargetProfile("-Tps_6_4", "dxil--shadermodel6.4-pixel", + validateTargetProfile("-Tps_6_4", "dxilv1.4--shadermodel6.4-pixel", InMemoryFileSystem, Diags); - validateTargetProfile("-Tcs_6_5", "dxil--shadermodel6.5-compute", + validateTargetProfile("-Tcs_6_5", "dxilv1.5--shadermodel6.5-compute", InMemoryFileSystem, Diags); - validateTargetProfile("-Tms_6_6", "dxil--shadermodel6.6-mesh", + validateTargetProfile("-Tms_6_6", "dxilv1.6--shadermodel6.6-mesh", InMemoryFileSystem, Diags); - validateTargetProfile("-Tas_6_7", "dxil--shadermodel6.7-amplification", + validateTargetProfile("-Tas_6_7", "dxilv1.7--shadermodel6.7-amplification", InMemoryFileSystem, Diags); - validateTargetProfile("-Tlib_6_x", "dxil--shadermodel6.15-library", + validateTargetProfile("-Tcs_6_8", "dxilv1.8--shadermodel6.8-compute", + InMemoryFileSystem, Diags); + validateTargetProfile("-Tlib_6_x", "dxilv1.8--shadermodel6.15-library", InMemoryFileSystem, Diags); // Invalid tests. diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h index 20cca5928782..8f9d99816931 100644 --- a/llvm/include/llvm/TargetParser/Triple.h +++ b/llvm/include/llvm/TargetParser/Triple.h @@ -176,6 +176,7 @@ public: DXILSubArch_v1_6, DXILSubArch_v1_7, DXILSubArch_v1_8, + LatestDXILSubArch = DXILSubArch_v1_8, }; enum VendorType { UnknownVendor, diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index aa8160d18edd..50f8d6ec8420 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -152,8 +152,8 @@ struct VerifierSupport { bool TreatBrokenDebugInfoAsError = true; explicit VerifierSupport(raw_ostream *OS, const Module &M) - : OS(OS), M(M), MST(&M), TT(M.getTargetTriple()), DL(M.getDataLayout()), - Context(M.getContext()) {} + : OS(OS), M(M), MST(&M), TT(Triple::normalize(M.getTargetTriple())), + DL(M.getDataLayout()), Context(M.getContext()) {} private: void Write(const Module *M) { diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp index 18ec60296810..ef40ccf36806 100644 --- a/llvm/lib/TargetParser/Triple.cpp +++ b/llvm/lib/TargetParser/Triple.cpp @@ -115,6 +115,31 @@ StringRef Triple::getArchName(ArchType Kind, SubArchType SubArch) { if (SubArch == AArch64SubArch_arm64e) return "arm64e"; break; + case Triple::dxil: + switch (SubArch) { + case Triple::NoSubArch: + case Triple::DXILSubArch_v1_0: + return "dxilv1.0"; + case Triple::DXILSubArch_v1_1: + return "dxilv1.1"; + case Triple::DXILSubArch_v1_2: + return "dxilv1.2"; + case Triple::DXILSubArch_v1_3: + return "dxilv1.3"; + case Triple::DXILSubArch_v1_4: + return "dxilv1.4"; + case Triple::DXILSubArch_v1_5: + return "dxilv1.5"; + case Triple::DXILSubArch_v1_6: + return "dxilv1.6"; + case Triple::DXILSubArch_v1_7: + return "dxilv1.7"; + case Triple::DXILSubArch_v1_8: + return "dxilv1.8"; + default: + break; + } + break; default: break; } @@ -1014,6 +1039,53 @@ Triple::Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine &OSStr, ObjectFormat = getDefaultFormat(*this); } +static VersionTuple parseVersionFromName(StringRef Name); + +static StringRef getDXILArchNameFromShaderModel(StringRef ShaderModelStr) { + VersionTuple Ver = + parseVersionFromName(ShaderModelStr.drop_front(strlen("shadermodel"))); + // Default DXIL minor version when Shader Model version is anything other + // than 6.[0...8] or 6.x (which translates to latest current SM version) + const unsigned SMMajor = 6; + if (!Ver.empty()) { + if (Ver.getMajor() == SMMajor) { + if (std::optional SMMinor = Ver.getMinor()) { + switch (*SMMinor) { + case 0: + return Triple::getArchName(Triple::dxil, Triple::DXILSubArch_v1_0); + case 1: + return Triple::getArchName(Triple::dxil, Triple::DXILSubArch_v1_1); + case 2: + return Triple::getArchName(Triple::dxil, Triple::DXILSubArch_v1_2); + case 3: + return Triple::getArchName(Triple::dxil, Triple::DXILSubArch_v1_3); + case 4: + return Triple::getArchName(Triple::dxil, Triple::DXILSubArch_v1_4); + case 5: + return Triple::getArchName(Triple::dxil, Triple::DXILSubArch_v1_5); + case 6: + return Triple::getArchName(Triple::dxil, Triple::DXILSubArch_v1_6); + case 7: + return Triple::getArchName(Triple::dxil, Triple::DXILSubArch_v1_7); + case 8: + return Triple::getArchName(Triple::dxil, Triple::DXILSubArch_v1_8); + default: + report_fatal_error("Unsupported Shader Model version", false); + } + } + } + } else { + // Special case: DXIL minor version is set to LatestCurrentDXILMinor for + // shadermodel6.x is + if (ShaderModelStr == "shadermodel6.x") { + return Triple::getArchName(Triple::dxil, Triple::LatestDXILSubArch); + } + } + // DXIL version corresponding to Shader Model version other than 6.Minor + // is 1.0 + return Triple::getArchName(Triple::dxil, Triple::DXILSubArch_v1_0); +} + std::string Triple::normalize(StringRef Str) { bool IsMinGW32 = false; bool IsCygwin = false; @@ -1206,6 +1278,20 @@ std::string Triple::normalize(StringRef Str) { } } + // Normalize DXIL triple if it does not include DXIL version number. + // Determine DXIL version number using the minor version number of Shader + // Model version specified in target triple, if any. Prior to decoupling DXIL + // version numbering from that of Shader Model DXIL version 1.Y corresponds to + // SM 6.Y. E.g., dxilv1.Y-unknown-shadermodelX.Y-hull + if (Components[0] == "dxil") { + if (Components.size() > 4) { + Components.resize(4); + } + // Add DXIL version only if shadermodel is specified in the triple + if (OS == Triple::ShaderModel) { + Components[0] = getDXILArchNameFromShaderModel(Components[2]); + } + } // Stick the corrected components back together to form the normalized string. return join(Components, "-"); } diff --git a/llvm/unittests/TargetParser/TripleTest.cpp b/llvm/unittests/TargetParser/TripleTest.cpp index 8e90ee6858f4..f93dc3671197 100644 --- a/llvm/unittests/TargetParser/TripleTest.cpp +++ b/llvm/unittests/TargetParser/TripleTest.cpp @@ -2533,4 +2533,20 @@ TEST(TripleTest, isArmMClass) { EXPECT_TRUE(T.isArmMClass()); } } + +TEST(TripleTest, DXILNormaizeWithVersion) { + EXPECT_EQ("dxilv1.0-unknown-shadermodel6.0", + Triple::normalize("dxilv1.0--shadermodel6.0")); + EXPECT_EQ("dxilv1.0-unknown-shadermodel6.0", + Triple::normalize("dxil--shadermodel6.0")); + EXPECT_EQ("dxilv1.1-unknown-shadermodel6.1-library", + Triple::normalize("dxil-shadermodel6.1-unknown-library")); + EXPECT_EQ("dxilv1.8-unknown-shadermodel6.x-unknown", + Triple::normalize("dxil-unknown-shadermodel6.x-unknown")); + EXPECT_EQ("dxilv1.8-unknown-shadermodel6.x-unknown", + Triple::normalize("dxil-unknown-shadermodel6.x-unknown")); + EXPECT_EQ("dxil-unknown-unknown-unknown", Triple::normalize("dxil---")); + EXPECT_EQ("dxilv1.0-pc-shadermodel5.0-compute", + Triple::normalize("dxil-shadermodel5.0-pc-compute")); +} } // end anonymous namespace -- GitLab From efad14954c9d5bdfaddaca948be6cd7e71a1d1b0 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Wed, 8 May 2024 09:22:30 -0700 Subject: [PATCH 047/328] [Support] Add end/error to decode[US]LEB128AndInc Follow-up to #85739 to encourage error checking. We make `end` mandatory and add decodeULEB128AndIncUnsafe to be used without `end`. Pull Request: https://github.com/llvm/llvm-project/pull/90006 --- llvm/include/llvm/Support/LEB128.h | 14 ++++++++++---- llvm/unittests/Support/LEB128Test.cpp | 25 ++++++++++++++++++++++++- llvm/utils/TableGen/DecoderEmitter.cpp | 16 ++++++++-------- 3 files changed, 42 insertions(+), 13 deletions(-) diff --git a/llvm/include/llvm/Support/LEB128.h b/llvm/include/llvm/Support/LEB128.h index c4e741549f3f..a15b73bc14dc 100644 --- a/llvm/include/llvm/Support/LEB128.h +++ b/llvm/include/llvm/Support/LEB128.h @@ -200,20 +200,26 @@ inline int64_t decodeSLEB128(const uint8_t *p, unsigned *n = nullptr, return Value; } -inline uint64_t decodeULEB128AndInc(const uint8_t *&p) { +inline uint64_t decodeULEB128AndInc(const uint8_t *&p, const uint8_t *end, + const char **error = nullptr) { unsigned n; - auto ret = decodeULEB128(p, &n); + auto ret = decodeULEB128(p, &n, end, error); p += n; return ret; } -inline int64_t decodeSLEB128AndInc(const uint8_t *&p) { +inline int64_t decodeSLEB128AndInc(const uint8_t *&p, const uint8_t *end, + const char **error = nullptr) { unsigned n; - auto ret = decodeSLEB128(p, &n); + auto ret = decodeSLEB128(p, &n, end, error); p += n; return ret; } +inline uint64_t decodeULEB128AndIncUnsafe(const uint8_t *&p) { + return decodeULEB128AndInc(p, nullptr); +} + /// Utility function to get the size of the ULEB128-encoded value. extern unsigned getULEB128Size(uint64_t Value); diff --git a/llvm/unittests/Support/LEB128Test.cpp b/llvm/unittests/Support/LEB128Test.cpp index 08b8c5573ce6..60f5ddd568ca 100644 --- a/llvm/unittests/Support/LEB128Test.cpp +++ b/llvm/unittests/Support/LEB128Test.cpp @@ -155,6 +155,12 @@ TEST(LEB128Test, DecodeInvalidULEB128) { EXPECT_NE(Error, nullptr); \ EXPECT_EQ(0ul, Actual); \ EXPECT_EQ(ERROR_OFFSET, ErrorOffset); \ + Value = reinterpret_cast(VALUE); \ + Error = nullptr; \ + Actual = decodeULEB128AndInc(Value, Value + strlen(VALUE), &Error); \ + EXPECT_NE(Error, nullptr); \ + EXPECT_EQ(0ul, Actual); \ + EXPECT_EQ(ERROR_OFFSET, Value - reinterpret_cast(VALUE)); \ } while (0) // Buffer overflow. @@ -224,6 +230,12 @@ TEST(LEB128Test, DecodeInvalidSLEB128) { EXPECT_NE(Error, nullptr); \ EXPECT_EQ(0ul, Actual); \ EXPECT_EQ(ERROR_OFFSET, ErrorOffset); \ + Value = reinterpret_cast(VALUE); \ + Error = nullptr; \ + Actual = decodeSLEB128AndInc(Value, Value + strlen(VALUE), &Error); \ + EXPECT_NE(Error, nullptr); \ + EXPECT_EQ(0ul, Actual); \ + EXPECT_EQ(ERROR_OFFSET, Value - reinterpret_cast(VALUE)); \ } while (0) // Buffer overflow. @@ -246,7 +258,7 @@ TEST(LEB128Test, DecodeAndInc) { #define EXPECT_LEB128(FUN, VALUE, SIZE) \ do { \ const uint8_t *V = reinterpret_cast(VALUE), *P = V; \ - auto Expected = FUN(P), Actual = FUN##AndInc(P); \ + auto Expected = FUN(P), Actual = FUN##AndInc(P, P + strlen(VALUE)); \ EXPECT_EQ(Actual, Expected); \ EXPECT_EQ(P - V, SIZE); \ } while (0) @@ -255,6 +267,17 @@ TEST(LEB128Test, DecodeAndInc) { EXPECT_LEB128(decodeSLEB128, "\x7f", 1); EXPECT_LEB128(decodeSLEB128, "\x80\x01", 2); #undef EXPECT_LEB128 + +#define EXPECT_LEB128(FUN, VALUE, SIZE) \ + do { \ + const uint8_t *V = reinterpret_cast(VALUE), *P = V; \ + auto Expected = FUN(P), Actual = FUN##AndIncUnsafe(P); \ + EXPECT_EQ(Actual, Expected); \ + EXPECT_EQ(P - V, SIZE); \ + } while (0) + EXPECT_LEB128(decodeULEB128, "\x7f", 1); + EXPECT_LEB128(decodeULEB128, "\x80\x01", 2); +#undef EXPECT_LEB128 } TEST(LEB128Test, SLEB128Size) { diff --git a/llvm/utils/TableGen/DecoderEmitter.cpp b/llvm/utils/TableGen/DecoderEmitter.cpp index 3bd7f432ff9a..c303322e63b4 100644 --- a/llvm/utils/TableGen/DecoderEmitter.cpp +++ b/llvm/utils/TableGen/DecoderEmitter.cpp @@ -2301,7 +2301,7 @@ static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI, } case MCD::OPC_CheckField: { // Decode the start value. - unsigned Start = decodeULEB128AndInc(++Ptr); + unsigned Start = decodeULEB128AndIncUnsafe(++Ptr); unsigned Len = *Ptr;)"; if (IsVarLenInst) OS << "\n makeUp(insn, Start + Len);"; @@ -2328,7 +2328,7 @@ static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI, } case MCD::OPC_CheckPredicate: { // Decode the Predicate Index value. - unsigned PIdx = decodeULEB128AndInc(++Ptr); + unsigned PIdx = decodeULEB128AndIncUnsafe(++Ptr); // NumToSkip is a plain 24-bit integer. unsigned NumToSkip = *Ptr++; NumToSkip |= (*Ptr++) << 8; @@ -2345,8 +2345,8 @@ static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI, } case MCD::OPC_Decode: { // Decode the Opcode value. - unsigned Opc = decodeULEB128AndInc(++Ptr); - unsigned DecodeIdx = decodeULEB128AndInc(Ptr); + unsigned Opc = decodeULEB128AndIncUnsafe(++Ptr); + unsigned DecodeIdx = decodeULEB128AndIncUnsafe(Ptr); MI.clear(); MI.setOpcode(Opc); @@ -2366,8 +2366,8 @@ static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI, } case MCD::OPC_TryDecode: { // Decode the Opcode value. - unsigned Opc = decodeULEB128AndInc(++Ptr); - unsigned DecodeIdx = decodeULEB128AndInc(Ptr); + unsigned Opc = decodeULEB128AndIncUnsafe(++Ptr); + unsigned DecodeIdx = decodeULEB128AndIncUnsafe(Ptr); // NumToSkip is a plain 24-bit integer. unsigned NumToSkip = *Ptr++; NumToSkip |= (*Ptr++) << 8; @@ -2399,8 +2399,8 @@ static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI, } case MCD::OPC_SoftFail: { // Decode the mask values. - uint64_t PositiveMask = decodeULEB128AndInc(++Ptr); - uint64_t NegativeMask = decodeULEB128AndInc(Ptr); + uint64_t PositiveMask = decodeULEB128AndIncUnsafe(++Ptr); + uint64_t NegativeMask = decodeULEB128AndIncUnsafe(Ptr); bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; if (Fail) S = MCDisassembler::SoftFail; -- GitLab From 8d9b15497d70ac782d7d01a2d606f9fec7e7f642 Mon Sep 17 00:00:00 2001 From: Justin Bogner Date: Wed, 8 May 2024 10:28:54 -0600 Subject: [PATCH 048/328] Fix unused private field warning (#91500) After 11a6799740f8 "[clang][CodeGen] Omit pre-opt link when post-opt is link requested (#85672)" I'm seeing a new warning: > BackendConsumer.h:37:22: error: private field 'FileMgr' is not used [-Werror,-Wunused-private-field] Remove the field since it's no longer used. --- clang/lib/CodeGen/BackendConsumer.h | 7 +++---- clang/lib/CodeGen/CodeGenAction.cpp | 19 ++++++++----------- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/clang/lib/CodeGen/BackendConsumer.h b/clang/lib/CodeGen/BackendConsumer.h index f9edbe901bb8..0fe9929dca2b 100644 --- a/clang/lib/CodeGen/BackendConsumer.h +++ b/clang/lib/CodeGen/BackendConsumer.h @@ -34,7 +34,6 @@ class BackendConsumer : public ASTConsumer { const CodeGenOptions &CodeGenOpts; const TargetOptions &TargetOpts; const LangOptions &LangOpts; - const FileManager &FileMgr; std::unique_ptr AsmOutStream; ASTContext *Context; IntrusiveRefCntPtr FS; @@ -76,7 +75,7 @@ public: const PreprocessorOptions &PPOpts, const CodeGenOptions &CodeGenOpts, const TargetOptions &TargetOpts, const LangOptions &LangOpts, - const FileManager &FileMgr, const std::string &InFile, + const std::string &InFile, SmallVector LinkModules, std::unique_ptr OS, llvm::LLVMContext &C, CoverageSourceInfo *CoverageInfo = nullptr); @@ -90,8 +89,8 @@ public: const PreprocessorOptions &PPOpts, const CodeGenOptions &CodeGenOpts, const TargetOptions &TargetOpts, const LangOptions &LangOpts, - const FileManager &FileMgr, llvm::Module *Module, - SmallVector LinkModules, llvm::LLVMContext &C, + llvm::Module *Module, SmallVector LinkModules, + llvm::LLVMContext &C, CoverageSourceInfo *CoverageInfo = nullptr); llvm::Module *getModule() const; diff --git a/clang/lib/CodeGen/CodeGenAction.cpp b/clang/lib/CodeGen/CodeGenAction.cpp index 0255f05b1f90..6d3efdb5ffe3 100644 --- a/clang/lib/CodeGen/CodeGenAction.cpp +++ b/clang/lib/CodeGen/CodeGenAction.cpp @@ -114,13 +114,12 @@ BackendConsumer::BackendConsumer( const HeaderSearchOptions &HeaderSearchOpts, const PreprocessorOptions &PPOpts, const CodeGenOptions &CodeGenOpts, const TargetOptions &TargetOpts, const LangOptions &LangOpts, - const FileManager &FileMgr, const std::string &InFile, - SmallVector LinkModules, + const std::string &InFile, SmallVector LinkModules, std::unique_ptr OS, LLVMContext &C, CoverageSourceInfo *CoverageInfo) : Diags(Diags), Action(Action), HeaderSearchOpts(HeaderSearchOpts), CodeGenOpts(CodeGenOpts), TargetOpts(TargetOpts), LangOpts(LangOpts), - FileMgr(FileMgr), AsmOutStream(std::move(OS)), Context(nullptr), FS(VFS), + AsmOutStream(std::move(OS)), Context(nullptr), FS(VFS), LLVMIRGeneration("irgen", "LLVM IR Generation Time"), LLVMIRGenerationRefCount(0), Gen(CreateLLVMCodeGen(Diags, InFile, std::move(VFS), HeaderSearchOpts, @@ -140,12 +139,11 @@ BackendConsumer::BackendConsumer( const HeaderSearchOptions &HeaderSearchOpts, const PreprocessorOptions &PPOpts, const CodeGenOptions &CodeGenOpts, const TargetOptions &TargetOpts, const LangOptions &LangOpts, - const FileManager &FileMgr, llvm::Module *Module, - SmallVector LinkModules, LLVMContext &C, - CoverageSourceInfo *CoverageInfo) + llvm::Module *Module, SmallVector LinkModules, + LLVMContext &C, CoverageSourceInfo *CoverageInfo) : Diags(Diags), Action(Action), HeaderSearchOpts(HeaderSearchOpts), CodeGenOpts(CodeGenOpts), TargetOpts(TargetOpts), LangOpts(LangOpts), - FileMgr(FileMgr), Context(nullptr), FS(VFS), + Context(nullptr), FS(VFS), LLVMIRGeneration("irgen", "LLVM IR Generation Time"), LLVMIRGenerationRefCount(0), Gen(CreateLLVMCodeGen(Diags, "", std::move(VFS), HeaderSearchOpts, PPOpts, @@ -1022,9 +1020,8 @@ CodeGenAction::CreateASTConsumer(CompilerInstance &CI, StringRef InFile) { std::unique_ptr Result(new BackendConsumer( BA, CI.getDiagnostics(), &CI.getVirtualFileSystem(), CI.getHeaderSearchOpts(), CI.getPreprocessorOpts(), CI.getCodeGenOpts(), - CI.getTargetOpts(), CI.getLangOpts(), CI.getFileManager(), - std::string(InFile), std::move(LinkModules), std::move(OS), *VMContext, - CoverageInfo)); + CI.getTargetOpts(), CI.getLangOpts(), std::string(InFile), + std::move(LinkModules), std::move(OS), *VMContext, CoverageInfo)); BEConsumer = Result.get(); // Enable generating macro debug info only when debug info is not disabled and @@ -1195,7 +1192,7 @@ void CodeGenAction::ExecuteAction() { BackendConsumer Result(BA, CI.getDiagnostics(), &CI.getVirtualFileSystem(), CI.getHeaderSearchOpts(), CI.getPreprocessorOpts(), CI.getCodeGenOpts(), CI.getTargetOpts(), - CI.getLangOpts(), CI.getFileManager(), TheModule.get(), + CI.getLangOpts(), TheModule.get(), std::move(LinkModules), *VMContext, nullptr); // Link in each pending link module. -- GitLab From b59461ac63aa1770a617f96bab31010442bd2090 Mon Sep 17 00:00:00 2001 From: Aleksandr Platonov Date: Wed, 8 May 2024 19:40:16 +0300 Subject: [PATCH 050/328] [ADT] Add back ability to compare StringSet (#91374) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit StringSet comparison was broken after moving from llvm::Optional to std::optional because std::nullopt_t is not equality-comparable. Without this patch a try to compare objects of StringSet type leads to compilation error: ``` llvm-project/llvm/include/llvm/ADT/StringMap.h:294:33: error: no match for ‘operator==’ (operand types are ‘std::nullopt_t’ and ‘std::nullopt_t’) 294 | if (!(KeyValue.getValue() == FindInRHS->getValue())) ``` --- llvm/include/llvm/ADT/StringMap.h | 6 ++++-- llvm/unittests/ADT/StringSetTest.cpp | 8 ++++++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/llvm/include/llvm/ADT/StringMap.h b/llvm/include/llvm/ADT/StringMap.h index 453d91349e35..daaf82654e09 100644 --- a/llvm/include/llvm/ADT/StringMap.h +++ b/llvm/include/llvm/ADT/StringMap.h @@ -291,8 +291,10 @@ public: if (FindInRHS == RHS.end()) return false; - if (!(KeyValue.getValue() == FindInRHS->getValue())) - return false; + if constexpr (!std::is_same_v) { + if (!(KeyValue.getValue() == FindInRHS->getValue())) + return false; + } } return true; diff --git a/llvm/unittests/ADT/StringSetTest.cpp b/llvm/unittests/ADT/StringSetTest.cpp index e3703f6f0150..a804c1f17d1c 100644 --- a/llvm/unittests/ADT/StringSetTest.cpp +++ b/llvm/unittests/ADT/StringSetTest.cpp @@ -73,4 +73,12 @@ TEST_F(StringSetTest, Contains) { EXPECT_FALSE(Set.contains("test")); } +TEST_F(StringSetTest, Equal) { + StringSet<> A = {"A"}; + StringSet<> B = {"B"}; + ASSERT_TRUE(A != B); + ASSERT_FALSE(A == B); + ASSERT_TRUE(A == A); +} + } // end anonymous namespace -- GitLab From 4298fc5eb5c483fb72db6fce062352087dfd0acf Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Wed, 8 May 2024 10:13:01 -0700 Subject: [PATCH 051/328] [RISCV] Move strength reduction of mul X, 3/5/9*2^N to combine (#89966) This moves our last major category tablegen driven multiply strength reduction into the post legalize combine framework. The one slightly tricky bit is making sure that we use a leading shl if we can form a slli.uw, and trailing shl otherwise. Having the trailing shl is critical for shNadd matching, and folding any following sext.w. As can be seen in the TD deltas, this allows us to kill off both the actual multiply patterns and the explicit add (mul X, C) Y patterns. The later are now handled by the generic shNadd matching code, with the exception of the THead only C=200 case because we don't (yet) have a multiply expansion with two shNadd + a shift. --------- Co-authored-by: Yingwei Zheng --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 25 ++++++- llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td | 29 -------- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 74 ------------------- llvm/test/CodeGen/RISCV/addimm-mulimm.ll | 9 ++- .../CodeGen/RISCV/rv64-legal-i32/rv64zba.ll | 6 +- llvm/test/CodeGen/RISCV/rv64zba.ll | 6 +- 6 files changed, 32 insertions(+), 117 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 3536eb4c0ba4..846768f6d631 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -13565,10 +13565,27 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG, if (MulAmt % Divisor != 0) continue; uint64_t MulAmt2 = MulAmt / Divisor; - // 3/5/9 * 2^N -> shXadd (sll X, C), (sll X, C) - // Matched in tablegen, avoid perturbing patterns. - if (isPowerOf2_64(MulAmt2)) - return SDValue(); + // 3/5/9 * 2^N -> shl (shXadd X, X), N + if (isPowerOf2_64(MulAmt2)) { + SDLoc DL(N); + SDValue X = N->getOperand(0); + // Put the shift first if we can fold a zext into the + // shift forming a slli.uw. + if (X.getOpcode() == ISD::AND && isa(X.getOperand(1)) && + X.getConstantOperandVal(1) == UINT64_C(0xffffffff)) { + SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, X, + DAG.getConstant(Log2_64(MulAmt2), DL, VT)); + return DAG.getNode(RISCVISD::SHL_ADD, DL, VT, Shl, + DAG.getConstant(Log2_64(Divisor - 1), DL, VT), Shl); + } + // Otherwise, put rhe shl second so that it can fold with following + // instructions (e.g. sext or add). + SDValue Mul359 = + DAG.getNode(RISCVISD::SHL_ADD, DL, VT, X, + DAG.getConstant(Log2_64(Divisor - 1), DL, VT), X); + return DAG.getNode(ISD::SHL, DL, VT, Mul359, + DAG.getConstant(Log2_64(MulAmt2), DL, VT)); + } // 3/5/9 * 3/5/9 -> shXadd (shYadd X, X), (shYadd X, X) if (MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9) { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td index b398c5e7fec2..bc14f165d962 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td @@ -549,40 +549,11 @@ def : Pat<(add_non_imm12 sh2add_op:$rs1, (XLenVT GPR:$rs2)), def : Pat<(add_non_imm12 sh3add_op:$rs1, (XLenVT GPR:$rs2)), (TH_ADDSL GPR:$rs2, sh3add_op:$rs1, 3)>; -def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 6)), GPR:$rs2), - (TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 1)), 1)>; -def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 10)), GPR:$rs2), - (TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 2)), 1)>; -def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 18)), GPR:$rs2), - (TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 3)), 1)>; -def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 12)), GPR:$rs2), - (TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 1)), 2)>; -def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 20)), GPR:$rs2), - (TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 2)), 2)>; -def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 36)), GPR:$rs2), - (TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 3)), 2)>; -def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 24)), GPR:$rs2), - (TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 1)), 3)>; -def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 40)), GPR:$rs2), - (TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 2)), 3)>; -def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2), - (TH_ADDSL GPR:$rs2, (XLenVT (TH_ADDSL GPR:$rs1, GPR:$rs1, 3)), 3)>; - def : Pat<(add (XLenVT GPR:$r), CSImm12MulBy4:$i), (TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), (SimmShiftRightBy2XForm CSImm12MulBy4:$i))), 2)>; def : Pat<(add (XLenVT GPR:$r), CSImm12MulBy8:$i), (TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), (SimmShiftRightBy3XForm CSImm12MulBy8:$i))), 3)>; -def : Pat<(mul (XLenVT GPR:$r), C3LeftShift:$i), - (SLLI (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 1)), - (TrailingZeros C3LeftShift:$i))>; -def : Pat<(mul (XLenVT GPR:$r), C5LeftShift:$i), - (SLLI (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)), - (TrailingZeros C5LeftShift:$i))>; -def : Pat<(mul (XLenVT GPR:$r), C9LeftShift:$i), - (SLLI (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 3)), - (TrailingZeros C9LeftShift:$i))>; - def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 200)), (SLLI (XLenVT (TH_ADDSL (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)), (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)), 2)), 3)>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td index ffe2b7e27120..8a0bbf6abd33 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -173,42 +173,6 @@ def BCLRIANDIMaskLow : SDNodeXFormgetValueType(0)); }]>; -def C3LeftShift : PatLeaf<(imm), [{ - uint64_t C = N->getZExtValue(); - return C > 3 && (C >> llvm::countr_zero(C)) == 3; -}]>; - -def C5LeftShift : PatLeaf<(imm), [{ - uint64_t C = N->getZExtValue(); - return C > 5 && (C >> llvm::countr_zero(C)) == 5; -}]>; - -def C9LeftShift : PatLeaf<(imm), [{ - uint64_t C = N->getZExtValue(); - return C > 9 && (C >> llvm::countr_zero(C)) == 9; -}]>; - -// Constant of the form (3 << C) where C is less than 32. -def C3LeftShiftUW : PatLeaf<(imm), [{ - uint64_t C = N->getZExtValue(); - unsigned Shift = llvm::countr_zero(C); - return 1 <= Shift && Shift < 32 && (C >> Shift) == 3; -}]>; - -// Constant of the form (5 << C) where C is less than 32. -def C5LeftShiftUW : PatLeaf<(imm), [{ - uint64_t C = N->getZExtValue(); - unsigned Shift = llvm::countr_zero(C); - return 1 <= Shift && Shift < 32 && (C >> Shift) == 5; -}]>; - -// Constant of the form (9 << C) where C is less than 32. -def C9LeftShiftUW : PatLeaf<(imm), [{ - uint64_t C = N->getZExtValue(); - unsigned Shift = llvm::countr_zero(C); - return 1 <= Shift && Shift < 32 && (C >> Shift) == 9; -}]>; - def CSImm12MulBy4 : PatLeaf<(imm), [{ if (!N->hasOneUse()) return false; @@ -693,25 +657,6 @@ foreach i = {1,2,3} in { (shxadd pat:$rs1, GPR:$rs2)>; } -def : Pat<(add_like (mul_oneuse GPR:$rs1, (XLenVT 6)), GPR:$rs2), - (SH1ADD (XLenVT (SH1ADD GPR:$rs1, GPR:$rs1)), GPR:$rs2)>; -def : Pat<(add_like (mul_oneuse GPR:$rs1, (XLenVT 10)), GPR:$rs2), - (SH1ADD (XLenVT (SH2ADD GPR:$rs1, GPR:$rs1)), GPR:$rs2)>; -def : Pat<(add_like (mul_oneuse GPR:$rs1, (XLenVT 18)), GPR:$rs2), - (SH1ADD (XLenVT (SH3ADD GPR:$rs1, GPR:$rs1)), GPR:$rs2)>; -def : Pat<(add_like (mul_oneuse GPR:$rs1, (XLenVT 12)), GPR:$rs2), - (SH2ADD (XLenVT (SH1ADD GPR:$rs1, GPR:$rs1)), GPR:$rs2)>; -def : Pat<(add_like (mul_oneuse GPR:$rs1, (XLenVT 20)), GPR:$rs2), - (SH2ADD (XLenVT (SH2ADD GPR:$rs1, GPR:$rs1)), GPR:$rs2)>; -def : Pat<(add_like (mul_oneuse GPR:$rs1, (XLenVT 36)), GPR:$rs2), - (SH2ADD (XLenVT (SH3ADD GPR:$rs1, GPR:$rs1)), GPR:$rs2)>; -def : Pat<(add_like (mul_oneuse GPR:$rs1, (XLenVT 24)), GPR:$rs2), - (SH3ADD (XLenVT (SH1ADD GPR:$rs1, GPR:$rs1)), GPR:$rs2)>; -def : Pat<(add_like (mul_oneuse GPR:$rs1, (XLenVT 40)), GPR:$rs2), - (SH3ADD (XLenVT (SH2ADD GPR:$rs1, GPR:$rs1)), GPR:$rs2)>; -def : Pat<(add_like (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2), - (SH3ADD (XLenVT (SH3ADD GPR:$rs1, GPR:$rs1)), GPR:$rs2)>; - def : Pat<(add_like (XLenVT GPR:$r), CSImm12MulBy4:$i), (SH2ADD (XLenVT (ADDI (XLenVT X0), (SimmShiftRightBy2XForm CSImm12MulBy4:$i))), GPR:$r)>; @@ -719,16 +664,6 @@ def : Pat<(add_like (XLenVT GPR:$r), CSImm12MulBy8:$i), (SH3ADD (XLenVT (ADDI (XLenVT X0), (SimmShiftRightBy3XForm CSImm12MulBy8:$i))), GPR:$r)>; -def : Pat<(mul (XLenVT GPR:$r), C3LeftShift:$i), - (SLLI (XLenVT (SH1ADD GPR:$r, GPR:$r)), - (TrailingZeros C3LeftShift:$i))>; -def : Pat<(mul (XLenVT GPR:$r), C5LeftShift:$i), - (SLLI (XLenVT (SH2ADD GPR:$r, GPR:$r)), - (TrailingZeros C5LeftShift:$i))>; -def : Pat<(mul (XLenVT GPR:$r), C9LeftShift:$i), - (SLLI (XLenVT (SH3ADD GPR:$r, GPR:$r)), - (TrailingZeros C9LeftShift:$i))>; - } // Predicates = [HasStdExtZba] let Predicates = [HasStdExtZba, IsRV64] in { @@ -780,15 +715,6 @@ def : Pat<(i64 (add_like_non_imm12 (and GPR:$rs1, 0x3FFFFFFFC), (XLenVT GPR:$rs2 def : Pat<(i64 (add_like_non_imm12 (and GPR:$rs1, 0x7FFFFFFF8), (XLenVT GPR:$rs2))), (SH3ADD_UW (XLenVT (SRLI GPR:$rs1, 3)), GPR:$rs2)>; -def : Pat<(i64 (mul (and_oneuse GPR:$r, 0xFFFFFFFF), C3LeftShiftUW:$i)), - (SH1ADD (XLenVT (SLLI_UW GPR:$r, (TrailingZeros C3LeftShiftUW:$i))), - (XLenVT (SLLI_UW GPR:$r, (TrailingZeros C3LeftShiftUW:$i))))>; -def : Pat<(i64 (mul (and_oneuse GPR:$r, 0xFFFFFFFF), C5LeftShiftUW:$i)), - (SH2ADD (XLenVT (SLLI_UW GPR:$r, (TrailingZeros C5LeftShiftUW:$i))), - (XLenVT (SLLI_UW GPR:$r, (TrailingZeros C5LeftShiftUW:$i))))>; -def : Pat<(i64 (mul (and_oneuse GPR:$r, 0xFFFFFFFF), C9LeftShiftUW:$i)), - (SH3ADD (XLenVT (SLLI_UW GPR:$r, (TrailingZeros C9LeftShiftUW:$i))), - (XLenVT (SLLI_UW GPR:$r, (TrailingZeros C9LeftShiftUW:$i))))>; } // Predicates = [HasStdExtZba, IsRV64] let Predicates = [HasStdExtZbcOrZbkc] in { diff --git a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll index 8fb251a75bd1..e2f7be2e6d7f 100644 --- a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll +++ b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll @@ -600,8 +600,9 @@ define i64 @add_mul_combine_infinite_loop(i64 %x) { ; RV32IMB-NEXT: sh3add a1, a1, a2 ; RV32IMB-NEXT: sh1add a0, a0, a0 ; RV32IMB-NEXT: slli a2, a0, 3 -; RV32IMB-NEXT: addi a0, a2, 2047 -; RV32IMB-NEXT: addi a0, a0, 1 +; RV32IMB-NEXT: li a3, 1 +; RV32IMB-NEXT: slli a3, a3, 11 +; RV32IMB-NEXT: sh3add a0, a0, a3 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 ; RV32IMB-NEXT: ret @@ -610,8 +611,8 @@ define i64 @add_mul_combine_infinite_loop(i64 %x) { ; RV64IMB: # %bb.0: ; RV64IMB-NEXT: addi a0, a0, 86 ; RV64IMB-NEXT: sh1add a0, a0, a0 -; RV64IMB-NEXT: li a1, -16 -; RV64IMB-NEXT: sh3add a0, a0, a1 +; RV64IMB-NEXT: slli a0, a0, 3 +; RV64IMB-NEXT: addi a0, a0, -16 ; RV64IMB-NEXT: ret %tmp0 = mul i64 %x, 24 %tmp1 = add i64 %tmp0, 2048 diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll index c3ae40124ba0..2db0d40b0ce5 100644 --- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll +++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll @@ -646,8 +646,8 @@ define i64 @zext_mul12884901888(i32 signext %a) { ; ; RV64ZBA-LABEL: zext_mul12884901888: ; RV64ZBA: # %bb.0: -; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: slli a0, a0, 32 +; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: ret %b = zext i32 %a to i64 %c = mul i64 %b, 12884901888 @@ -667,8 +667,8 @@ define i64 @zext_mul21474836480(i32 signext %a) { ; ; RV64ZBA-LABEL: zext_mul21474836480: ; RV64ZBA: # %bb.0: -; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: slli a0, a0, 32 +; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: ret %b = zext i32 %a to i64 %c = mul i64 %b, 21474836480 @@ -688,8 +688,8 @@ define i64 @zext_mul38654705664(i32 signext %a) { ; ; RV64ZBA-LABEL: zext_mul38654705664: ; RV64ZBA: # %bb.0: -; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: slli a0, a0, 32 +; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: ret %b = zext i32 %a to i64 %c = mul i64 %b, 38654705664 diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll index 817e2b7d0bd9..5931e0982a4a 100644 --- a/llvm/test/CodeGen/RISCV/rv64zba.ll +++ b/llvm/test/CodeGen/RISCV/rv64zba.ll @@ -865,8 +865,8 @@ define i64 @zext_mul12884901888(i32 signext %a) { ; ; RV64ZBA-LABEL: zext_mul12884901888: ; RV64ZBA: # %bb.0: -; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: slli a0, a0, 32 +; RV64ZBA-NEXT: sh1add a0, a0, a0 ; RV64ZBA-NEXT: ret %b = zext i32 %a to i64 %c = mul i64 %b, 12884901888 @@ -886,8 +886,8 @@ define i64 @zext_mul21474836480(i32 signext %a) { ; ; RV64ZBA-LABEL: zext_mul21474836480: ; RV64ZBA: # %bb.0: -; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: slli a0, a0, 32 +; RV64ZBA-NEXT: sh2add a0, a0, a0 ; RV64ZBA-NEXT: ret %b = zext i32 %a to i64 %c = mul i64 %b, 21474836480 @@ -907,8 +907,8 @@ define i64 @zext_mul38654705664(i32 signext %a) { ; ; RV64ZBA-LABEL: zext_mul38654705664: ; RV64ZBA: # %bb.0: -; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: slli a0, a0, 32 +; RV64ZBA-NEXT: sh3add a0, a0, a0 ; RV64ZBA-NEXT: ret %b = zext i32 %a to i64 %c = mul i64 %b, 38654705664 -- GitLab From a620697340671aea2b0c65449fcddf3c2e4d1917 Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Wed, 8 May 2024 10:14:51 -0700 Subject: [PATCH 052/328] [IR] Check callee param attributes as well in CallBase::getParamAttr() (#91394) These methods aren't used yet, but may be in the future. This keeps them in line with other methods like getFnAttr(). --- llvm/include/llvm/IR/InstrTypes.h | 12 ++++++-- llvm/lib/IR/Instructions.cpp | 16 ++++++++++ llvm/unittests/IR/AttributesTest.cpp | 46 ++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+), 2 deletions(-) diff --git a/llvm/include/llvm/IR/InstrTypes.h b/llvm/include/llvm/IR/InstrTypes.h index eaade9ce4755..9dd1bb455a71 100644 --- a/llvm/include/llvm/IR/InstrTypes.h +++ b/llvm/include/llvm/IR/InstrTypes.h @@ -1997,13 +1997,19 @@ public: /// Get the attribute of a given kind from a given arg Attribute getParamAttr(unsigned ArgNo, Attribute::AttrKind Kind) const { assert(ArgNo < arg_size() && "Out of bounds"); - return getAttributes().getParamAttr(ArgNo, Kind); + Attribute A = getAttributes().getParamAttr(ArgNo, Kind); + if (A.isValid()) + return A; + return getParamAttrOnCalledFunction(ArgNo, Kind); } /// Get the attribute of a given kind from a given arg Attribute getParamAttr(unsigned ArgNo, StringRef Kind) const { assert(ArgNo < arg_size() && "Out of bounds"); - return getAttributes().getParamAttr(ArgNo, Kind); + Attribute A = getAttributes().getParamAttr(ArgNo, Kind); + if (A.isValid()) + return A; + return getParamAttrOnCalledFunction(ArgNo, Kind); } /// Return true if the data operand at index \p i has the attribute \p @@ -2652,6 +2658,8 @@ private: return hasFnAttrOnCalledFunction(Kind); } template Attribute getFnAttrOnCalledFunction(AK Kind) const; + template + Attribute getParamAttrOnCalledFunction(unsigned ArgNo, AK Kind) const; /// Determine whether the return value has the given attribute. Supports /// Attribute::AttrKind and StringRef as \p AttrKind types. diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp index 7ad1ad4cddb7..32af58a43b68 100644 --- a/llvm/lib/IR/Instructions.cpp +++ b/llvm/lib/IR/Instructions.cpp @@ -500,6 +500,22 @@ template Attribute CallBase::getFnAttrOnCalledFunction(Attribute::AttrKind Kind) const; template Attribute CallBase::getFnAttrOnCalledFunction(StringRef Kind) const; +template +Attribute CallBase::getParamAttrOnCalledFunction(unsigned ArgNo, + AK Kind) const { + Value *V = getCalledOperand(); + + if (auto *F = dyn_cast(V)) + return F->getAttributes().getParamAttr(ArgNo, Kind); + + return Attribute(); +} +template Attribute +CallBase::getParamAttrOnCalledFunction(unsigned ArgNo, + Attribute::AttrKind Kind) const; +template Attribute CallBase::getParamAttrOnCalledFunction(unsigned ArgNo, + StringRef Kind) const; + void CallBase::getOperandBundlesAsDefs( SmallVectorImpl &Defs) const { for (unsigned i = 0, e = getNumOperandBundles(); i != e; ++i) diff --git a/llvm/unittests/IR/AttributesTest.cpp b/llvm/unittests/IR/AttributesTest.cpp index a7967593c2f9..da72fa14510c 100644 --- a/llvm/unittests/IR/AttributesTest.cpp +++ b/llvm/unittests/IR/AttributesTest.cpp @@ -340,4 +340,50 @@ TEST(Attributes, ConstantRangeAttributeCAPI) { } } +TEST(Attributes, CalleeAttributes) { + const char *IRString = R"IR( + declare void @f1(i32 %i) + declare void @f2(i32 range(i32 1, 2) %i) + + define void @g1(i32 %i) { + call void @f1(i32 %i) + ret void + } + define void @g2(i32 %i) { + call void @f2(i32 %i) + ret void + } + define void @g3(i32 %i) { + call void @f1(i32 range(i32 3, 4) %i) + ret void + } + define void @g4(i32 %i) { + call void @f2(i32 range(i32 3, 4) %i) + ret void + } + )IR"; + + SMDiagnostic Err; + LLVMContext Context; + std::unique_ptr M = parseAssemblyString(IRString, Err, Context); + ASSERT_TRUE(M); + + { + auto *I = cast(&M->getFunction("g1")->getEntryBlock().front()); + ASSERT_FALSE(I->getParamAttr(0, Attribute::Range).isValid()); + } + { + auto *I = cast(&M->getFunction("g2")->getEntryBlock().front()); + ASSERT_TRUE(I->getParamAttr(0, Attribute::Range).isValid()); + } + { + auto *I = cast(&M->getFunction("g3")->getEntryBlock().front()); + ASSERT_TRUE(I->getParamAttr(0, Attribute::Range).isValid()); + } + { + auto *I = cast(&M->getFunction("g4")->getEntryBlock().front()); + ASSERT_TRUE(I->getParamAttr(0, Attribute::Range).isValid()); + } +} + } // end anonymous namespace -- GitLab From 576838301d23bb779aa9c3f0cc3d086c46add44b Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Wed, 8 May 2024 10:15:27 -0700 Subject: [PATCH 053/328] [IR] Remove check for bitcast of called function in CallBase::has/getFnAttrOnCalledFunction (#91392) With opaque pointers, we shouldn't have bitcasts between function pointer types. --- llvm/lib/IR/Instructions.cpp | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp index 32af58a43b68..4b725610081c 100644 --- a/llvm/lib/IR/Instructions.cpp +++ b/llvm/lib/IR/Instructions.cpp @@ -454,24 +454,14 @@ bool CallBase::paramHasAttr(unsigned ArgNo, Attribute::AttrKind Kind) const { } bool CallBase::hasFnAttrOnCalledFunction(Attribute::AttrKind Kind) const { - Value *V = getCalledOperand(); - if (auto *CE = dyn_cast(V)) - if (CE->getOpcode() == BitCast) - V = CE->getOperand(0); - - if (auto *F = dyn_cast(V)) + if (auto *F = dyn_cast(getCalledOperand())) return F->getAttributes().hasFnAttr(Kind); return false; } bool CallBase::hasFnAttrOnCalledFunction(StringRef Kind) const { - Value *V = getCalledOperand(); - if (auto *CE = dyn_cast(V)) - if (CE->getOpcode() == BitCast) - V = CE->getOperand(0); - - if (auto *F = dyn_cast(V)) + if (auto *F = dyn_cast(getCalledOperand())) return F->getAttributes().hasFnAttr(Kind); return false; @@ -485,12 +475,7 @@ Attribute CallBase::getFnAttrOnCalledFunction(AK Kind) const { assert(Kind != Attribute::Memory && "Use getMemoryEffects() instead"); } - Value *V = getCalledOperand(); - if (auto *CE = dyn_cast(V)) - if (CE->getOpcode() == BitCast) - V = CE->getOperand(0); - - if (auto *F = dyn_cast(V)) + if (auto *F = dyn_cast(getCalledOperand())) return F->getAttributes().getFnAttr(Kind); return Attribute(); -- GitLab From 08011cf8453c7c9e87d135f063356b6764a91cbc Mon Sep 17 00:00:00 2001 From: XChy Date: Thu, 9 May 2024 01:15:49 +0800 Subject: [PATCH 054/328] [Docs][NFC] Use opaque ptr in the example (#91502) --- llvm/docs/MIRLangRef.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst index 52ff24daa7fb..e248a14636a8 100644 --- a/llvm/docs/MIRLangRef.rst +++ b/llvm/docs/MIRLangRef.rst @@ -168,11 +168,11 @@ Here is an example of a YAML document that contains an LLVM module: .. code-block:: llvm - define i32 @inc(i32* %x) { + define i32 @inc(ptr %x) { entry: - %0 = load i32, i32* %x + %0 = load i32, ptr %x %1 = add i32 %0, 1 - store i32 %1, i32* %x + store i32 %1, ptr %x ret i32 %1 } -- GitLab From 46435ac19e09039fb146fa6c12da0e640a66d435 Mon Sep 17 00:00:00 2001 From: Kristof Beyls Date: Wed, 8 May 2024 19:20:11 +0200 Subject: [PATCH 055/328] [NFC][BOLT] Remove dead code (SPTAllocatorsId) (#91477) It seems that SPTAllocatorsId is no longer used in FrameAnalysis, so let's remove it. It seems the use of SPTAllocatorsId was removed back in 2019, in commit cc8415406c7. --- bolt/include/bolt/Passes/FrameAnalysis.h | 4 ---- bolt/lib/Passes/FrameAnalysis.cpp | 5 ----- 2 files changed, 9 deletions(-) diff --git a/bolt/include/bolt/Passes/FrameAnalysis.h b/bolt/include/bolt/Passes/FrameAnalysis.h index 66246bd6647b..44b54d4ed45d 100644 --- a/bolt/include/bolt/Passes/FrameAnalysis.h +++ b/bolt/include/bolt/Passes/FrameAnalysis.h @@ -170,10 +170,6 @@ class FrameAnalysis { std::unique_ptr> SPTMap; - /// A vector that stores ids of the allocators that are used in SPT - /// computation - std::vector SPTAllocatorsId; - public: explicit FrameAnalysis(BinaryContext &BC, BinaryFunctionCallGraph &CG); diff --git a/bolt/lib/Passes/FrameAnalysis.cpp b/bolt/lib/Passes/FrameAnalysis.cpp index 7f1245e39f56..4ebfd8f158f7 100644 --- a/bolt/lib/Passes/FrameAnalysis.cpp +++ b/bolt/lib/Passes/FrameAnalysis.cpp @@ -561,11 +561,6 @@ FrameAnalysis::FrameAnalysis(BinaryContext &BC, BinaryFunctionCallGraph &CG) NamedRegionTimer T1("clearspt", "clear spt", "FA", "FA breakdown", opts::TimeFA); clearSPTMap(); - - // Clean up memory allocated for annotation values - if (!opts::NoThreads) - for (MCPlusBuilder::AllocatorIdTy Id : SPTAllocatorsId) - BC.MIB->freeValuesAllocator(Id); } } -- GitLab From bb6df0804ba0a0b0581aec4156138f5144dbcee2 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Wed, 8 May 2024 10:33:53 -0700 Subject: [PATCH 056/328] [llvm] Use StringRef::operator== instead of StringRef::equals (NFC) (#91441) I'm planning to remove StringRef::equals in favor of StringRef::operator==. - StringRef::operator==/!= outnumber StringRef::equals by a factor of 70 under llvm/ in terms of their usage. - The elimination of StringRef::equals brings StringRef closer to std::string_view, which has operator== but not equals. - S == "foo" is more readable than S.equals("foo"), especially for !Long.Expression.equals("str") vs Long.Expression != "str". --- llvm/include/llvm/ADT/SmallString.h | 2 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 2 +- .../RuntimeDyld/RuntimeDyldELF.cpp | 2 +- llvm/lib/FileCheck/FileCheck.cpp | 2 +- llvm/lib/FuzzMutate/FuzzerCLI.cpp | 6 ++-- llvm/lib/LTO/LTOModule.cpp | 2 +- llvm/lib/MC/MCAsmStreamer.cpp | 2 +- llvm/lib/MC/MCParser/AsmParser.cpp | 2 +- llvm/lib/MC/MCParser/DarwinAsmParser.cpp | 2 +- llvm/lib/MC/MCSymbolXCOFF.cpp | 4 +-- llvm/lib/Object/Archive.cpp | 4 +-- llvm/lib/Object/MachOObjectFile.cpp | 4 +-- llvm/lib/Object/OffloadBinary.cpp | 2 +- llvm/lib/ObjectYAML/COFFEmitter.cpp | 4 +-- llvm/lib/Passes/StandardInstrumentations.cpp | 3 +- llvm/lib/ProfileData/GCOV.cpp | 2 +- llvm/lib/ProfileData/InstrProf.cpp | 2 +- llvm/lib/ProfileData/MemProfReader.cpp | 6 ++-- llvm/lib/Support/VirtualFileSystem.cpp | 4 +-- llvm/lib/TargetParser/ARMTargetParser.cpp | 2 +- llvm/lib/TargetParser/Triple.cpp | 6 ++-- llvm/tools/dsymutil/DwarfLinkerForBinary.cpp | 2 +- llvm/tools/llvm-dwarfdump/Statistics.cpp | 2 +- llvm/tools/llvm-extract/llvm-extract.cpp | 2 +- llvm/tools/llvm-objdump/MachODump.cpp | 2 +- llvm/tools/llvm-xray/xray-graph-diff.cpp | 4 +-- .../yaml-numeric-parser-fuzzer.cpp | 2 +- llvm/unittests/ADT/StringRefTest.cpp | 6 ++-- llvm/unittests/IR/VerifierTest.cpp | 36 +++++++++---------- llvm/unittests/Support/MemoryBufferTest.cpp | 22 ++++++------ llvm/unittests/Support/YAMLIOTest.cpp | 8 ++--- .../TargetParser/CSKYTargetParserTest.cpp | 2 +- .../TargetParser/TargetParserTest.cpp | 4 +-- llvm/utils/TableGen/AsmMatcherEmitter.cpp | 2 +- 34 files changed, 79 insertions(+), 80 deletions(-) diff --git a/llvm/include/llvm/ADT/SmallString.h b/llvm/include/llvm/ADT/SmallString.h index a5b9eec50c82..be3193c6ef9b 100644 --- a/llvm/include/llvm/ADT/SmallString.h +++ b/llvm/include/llvm/ADT/SmallString.h @@ -89,7 +89,7 @@ public: /// Check for string equality. This is more efficient than compare() when /// the relative ordering of inequal strings isn't needed. - [[nodiscard]] bool equals(StringRef RHS) const { return str().equals(RHS); } + [[nodiscard]] bool equals(StringRef RHS) const { return str() == RHS; } /// Check for string equality, ignoring case. [[nodiscard]] bool equals_insensitive(StringRef RHS) const { diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp index 73fe63b5b8f6..be2381cd7d77 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -6896,7 +6896,7 @@ Error BitcodeReader::materialize(GlobalValue *GV) { MDString *MDS = cast(MD->getOperand(0)); StringRef ProfName = MDS->getString(); // Check consistency of !prof branch_weights metadata. - if (!ProfName.equals("branch_weights")) + if (ProfName != "branch_weights") continue; unsigned ExpectedNumOperands = 0; if (BranchInst *BI = dyn_cast(&I)) diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp index edeb563076fd..eaf8c35142de 100644 --- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp +++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp @@ -659,7 +659,7 @@ void RuntimeDyldELF::setMipsABI(const ObjectFile &Obj) { IsMipsO32ABI = AbiVariant & ELF::EF_MIPS_ABI_O32; IsMipsN32ABI = AbiVariant & ELF::EF_MIPS_ABI2; } - IsMipsN64ABI = Obj.getFileFormatName().equals("elf64-mips"); + IsMipsN64ABI = Obj.getFileFormatName() == "elf64-mips"; } // Return the .TOC. section and offset. diff --git a/llvm/lib/FileCheck/FileCheck.cpp b/llvm/lib/FileCheck/FileCheck.cpp index 8f80a69c4abd..1719f8ef2b43 100644 --- a/llvm/lib/FileCheck/FileCheck.cpp +++ b/llvm/lib/FileCheck/FileCheck.cpp @@ -374,7 +374,7 @@ Expected Pattern::parseNumericVariableDefinition( Expected> Pattern::parseNumericVariableUse( StringRef Name, bool IsPseudo, std::optional LineNumber, FileCheckPatternContext *Context, const SourceMgr &SM) { - if (IsPseudo && !Name.equals("@LINE")) + if (IsPseudo && Name != "@LINE") return ErrorDiagnostic::get( SM, Name, "invalid pseudo numeric variable '" + Name + "'"); diff --git a/llvm/lib/FuzzMutate/FuzzerCLI.cpp b/llvm/lib/FuzzMutate/FuzzerCLI.cpp index 58e4b74f4b22..504532865440 100644 --- a/llvm/lib/FuzzMutate/FuzzerCLI.cpp +++ b/llvm/lib/FuzzMutate/FuzzerCLI.cpp @@ -21,7 +21,7 @@ void llvm::parseFuzzerCLOpts(int ArgC, char *ArgV[]) { int I = 1; while (I < ArgC) - if (StringRef(ArgV[I++]).equals("-ignore_remaining_args=1")) + if (StringRef(ArgV[I++]) == "-ignore_remaining_args=1") break; while (I < ArgC) CLArgs.push_back(ArgV[I++]); @@ -39,7 +39,7 @@ void llvm::handleExecNameEncodedBEOpts(StringRef ExecName) { SmallVector Opts; NameAndArgs.second.split(Opts, '-'); for (StringRef Opt : Opts) { - if (Opt.equals("gisel")) { + if (Opt == "gisel") { Args.push_back("-global-isel"); // For now we default GlobalISel to -O0 Args.push_back("-O0"); @@ -151,7 +151,7 @@ int llvm::runFuzzerOnInputs(int ArgC, char *ArgV[], FuzzerTestFun TestOne, for (int I = 1; I < ArgC; ++I) { StringRef Arg(ArgV[I]); if (Arg.starts_with("-")) { - if (Arg.equals("-ignore_remaining_args=1")) + if (Arg == "-ignore_remaining_args=1") break; continue; } diff --git a/llvm/lib/LTO/LTOModule.cpp b/llvm/lib/LTO/LTOModule.cpp index f839fe944e18..eac78069f4d2 100644 --- a/llvm/lib/LTO/LTOModule.cpp +++ b/llvm/lib/LTO/LTOModule.cpp @@ -694,7 +694,7 @@ bool LTOModule::hasCtorDtor() const { if (auto *GV = dyn_cast_if_present(Sym)) { StringRef Name = GV->getName(); if (Name.consume_front("llvm.global_")) { - if (Name.equals("ctors") || Name.equals("dtors")) + if (Name == "ctors" || Name == "dtors") return true; } } diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp index 3dc70a401589..f257d0d9e83f 100644 --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -468,7 +468,7 @@ void MCAsmStreamer::emitRawComment(const Twine &T, bool TabPrefix) { void MCAsmStreamer::addExplicitComment(const Twine &T) { StringRef c = T.getSingleStringRef(); - if (c.equals(StringRef(MAI->getSeparatorString()))) + if (c == MAI->getSeparatorString()) return; if (c.starts_with(StringRef("//"))) { ExplicitCommentToEmit.append("\t"); diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp index 76a3e501f459..8d9acd54e879 100644 --- a/llvm/lib/MC/MCParser/AsmParser.cpp +++ b/llvm/lib/MC/MCParser/AsmParser.cpp @@ -4543,7 +4543,7 @@ bool AsmParser::parseDirectiveMacro(SMLoc DirectiveLoc) { // Emit an error if two (or more) named parameters share the same name for (const MCAsmMacroParameter& CurrParam : Parameters) - if (CurrParam.Name.equals(Parameter.Name)) + if (CurrParam.Name == Parameter.Name) return TokError("macro '" + Name + "' has multiple parameters" " named '" + Parameter.Name + "'"); diff --git a/llvm/lib/MC/MCParser/DarwinAsmParser.cpp b/llvm/lib/MC/MCParser/DarwinAsmParser.cpp index 3cd44e7195be..a97b72997ae3 100644 --- a/llvm/lib/MC/MCParser/DarwinAsmParser.cpp +++ b/llvm/lib/MC/MCParser/DarwinAsmParser.cpp @@ -705,7 +705,7 @@ bool DarwinAsmParser::parseDirectiveSection(StringRef, SMLoc) { .Case("__datacoal_nt", "__data") .Default(Section); - if (!Section.equals(NonCoalSection)) { + if (Section != NonCoalSection) { StringRef SectionVal(Loc.getPointer()); size_t B = SectionVal.find(',') + 1, E = SectionVal.find(',', B); SMLoc BLoc = SMLoc::getFromPointer(SectionVal.data() + B); diff --git a/llvm/lib/MC/MCSymbolXCOFF.cpp b/llvm/lib/MC/MCSymbolXCOFF.cpp index b4c96a1ffa23..599a3946a1ed 100644 --- a/llvm/lib/MC/MCSymbolXCOFF.cpp +++ b/llvm/lib/MC/MCSymbolXCOFF.cpp @@ -13,7 +13,7 @@ using namespace llvm; MCSectionXCOFF *MCSymbolXCOFF::getRepresentedCsect() const { assert(RepresentedCsect && "Trying to get csect representation of this symbol but none was set."); - assert(getSymbolTableName().equals(RepresentedCsect->getSymbolTableName()) && + assert(getSymbolTableName() == RepresentedCsect->getSymbolTableName() && "SymbolTableNames need to be the same for this symbol and its csect " "representation."); return RepresentedCsect; @@ -24,7 +24,7 @@ void MCSymbolXCOFF::setRepresentedCsect(MCSectionXCOFF *C) { assert((!RepresentedCsect || RepresentedCsect == C) && "Trying to set a csect that doesn't match the one that this symbol is " "already mapped to."); - assert(getSymbolTableName().equals(C->getSymbolTableName()) && + assert(getSymbolTableName() == C->getSymbolTableName() && "SymbolTableNames need to be the same for this symbol and its csect " "representation."); RepresentedCsect = C; diff --git a/llvm/lib/Object/Archive.cpp b/llvm/lib/Object/Archive.cpp index 6139d9996bda..e798bbdd16f1 100644 --- a/llvm/lib/Object/Archive.cpp +++ b/llvm/lib/Object/Archive.cpp @@ -269,11 +269,11 @@ Expected ArchiveMemberHeader::getName(uint64_t Size) const { return Name; // System libraries from the Windows SDK for Windows 11 contain this symbol. // It looks like a CFG guard: we just skip it for now. - if (Name.equals("//")) + if (Name == "//") return Name; // Some libraries (e.g., arm64rt.lib) from the Windows WDK // (version 10.0.22000.0) contain this undocumented special member. - if (Name.equals("//")) + if (Name == "//") return Name; // It's a long name. // Get the string table offset. diff --git a/llvm/lib/Object/MachOObjectFile.cpp b/llvm/lib/Object/MachOObjectFile.cpp index 1cfd0a069463..06186ad362aa 100644 --- a/llvm/lib/Object/MachOObjectFile.cpp +++ b/llvm/lib/Object/MachOObjectFile.cpp @@ -399,7 +399,7 @@ static Error parseSegmentLoadCommand( return malformedError("load command " + Twine(LoadCommandIndex) + " filesize field in " + CmdName + " greater than vmsize field"); - IsPageZeroSegment |= StringRef("__PAGEZERO").equals(S.segname); + IsPageZeroSegment |= StringRef("__PAGEZERO") == S.segname; } else return SegOrErr.takeError(); @@ -4364,7 +4364,7 @@ BindRebaseSegInfo::BindRebaseSegInfo(const object::MachOObjectFile *Obj) { Info.Size = Section.getSize(); Info.SegmentName = Obj->getSectionFinalSegmentName(Section.getRawDataRefImpl()); - if (!Info.SegmentName.equals(CurSegName)) { + if (Info.SegmentName != CurSegName) { ++CurSegIndex; CurSegName = Info.SegmentName; CurSegAddress = Info.Address; diff --git a/llvm/lib/Object/OffloadBinary.cpp b/llvm/lib/Object/OffloadBinary.cpp index 6e9f8bed513c..89dc12551494 100644 --- a/llvm/lib/Object/OffloadBinary.cpp +++ b/llvm/lib/Object/OffloadBinary.cpp @@ -359,7 +359,7 @@ bool object::areTargetsCompatible(const OffloadFile::TargetID &LHS, return false; // If the architecture is "all" we assume it is always compatible. - if (LHS.second.equals("generic") || RHS.second.equals("generic")) + if (LHS.second == "generic" || RHS.second == "generic") return true; // Only The AMDGPU target requires additional checks. diff --git a/llvm/lib/ObjectYAML/COFFEmitter.cpp b/llvm/lib/ObjectYAML/COFFEmitter.cpp index 7088223b9b67..bb46de4c6f57 100644 --- a/llvm/lib/ObjectYAML/COFFEmitter.cpp +++ b/llvm/lib/ObjectYAML/COFFEmitter.cpp @@ -359,9 +359,9 @@ static uint32_t initializeOptionalHeader(COFFParser &CP, uint16_t Magic, SizeOfInitializedData += S.Header.SizeOfRawData; if (S.Header.Characteristics & COFF::IMAGE_SCN_CNT_UNINITIALIZED_DATA) SizeOfUninitializedData += S.Header.SizeOfRawData; - if (S.Name.equals(".text")) + if (S.Name == ".text") Header->BaseOfCode = S.Header.VirtualAddress; // RVA - else if (S.Name.equals(".data")) + else if (S.Name == ".data") BaseOfData = S.Header.VirtualAddress; // RVA if (S.Header.VirtualAddress) SizeOfImage += alignTo(S.Header.VirtualSize, Header->SectionAlignment); diff --git a/llvm/lib/Passes/StandardInstrumentations.cpp b/llvm/lib/Passes/StandardInstrumentations.cpp index 79aff096fb08..c7adc7668b9a 100644 --- a/llvm/lib/Passes/StandardInstrumentations.cpp +++ b/llvm/lib/Passes/StandardInstrumentations.cpp @@ -822,8 +822,7 @@ PrintIRInstrumentation::PassRunDescriptor PrintIRInstrumentation::popPassRunDescriptor(StringRef PassID) { assert(!PassRunDescriptorStack.empty() && "empty PassRunDescriptorStack"); PassRunDescriptor Descriptor = PassRunDescriptorStack.pop_back_val(); - assert(Descriptor.PassID.equals(PassID) && - "malformed PassRunDescriptorStack"); + assert(Descriptor.PassID == PassID && "malformed PassRunDescriptorStack"); return Descriptor; } diff --git a/llvm/lib/ProfileData/GCOV.cpp b/llvm/lib/ProfileData/GCOV.cpp index ee61784abade..ecb12c045b5b 100644 --- a/llvm/lib/ProfileData/GCOV.cpp +++ b/llvm/lib/ProfileData/GCOV.cpp @@ -678,7 +678,7 @@ std::string Context::getCoveragePath(StringRef filename, return std::string(filename); std::string CoveragePath; - if (options.LongFileNames && !filename.equals(mainFilename)) + if (options.LongFileNames && filename != mainFilename) CoveragePath = mangleCoveragePath(mainFilename, options.PreservePaths) + "##"; CoveragePath += mangleCoveragePath(filename, options.PreservePaths); diff --git a/llvm/lib/ProfileData/InstrProf.cpp b/llvm/lib/ProfileData/InstrProf.cpp index f9ba80bd99c8..1e3ca47b3d5a 100644 --- a/llvm/lib/ProfileData/InstrProf.cpp +++ b/llvm/lib/ProfileData/InstrProf.cpp @@ -1283,7 +1283,7 @@ MDNode *mayHaveValueProfileOfKind(const Instruction &Inst, return nullptr; MDString *Tag = cast(MD->getOperand(0)); - if (!Tag || !Tag->getString().equals("VP")) + if (!Tag || Tag->getString() != "VP") return nullptr; // Now check kind: diff --git a/llvm/lib/ProfileData/MemProfReader.cpp b/llvm/lib/ProfileData/MemProfReader.cpp index b4d2c6f043f6..c25babac844a 100644 --- a/llvm/lib/ProfileData/MemProfReader.cpp +++ b/llvm/lib/ProfileData/MemProfReader.cpp @@ -164,9 +164,9 @@ bool isRuntimePath(const StringRef Path) { const StringRef Filename = llvm::sys::path::filename(Path); // This list should be updated in case new files with additional interceptors // are added to the memprof runtime. - return Filename.equals("memprof_malloc_linux.cpp") || - Filename.equals("memprof_interceptors.cpp") || - Filename.equals("memprof_new_delete.cpp"); + return Filename == "memprof_malloc_linux.cpp" || + Filename == "memprof_interceptors.cpp" || + Filename == "memprof_new_delete.cpp"; } std::string getBuildIdString(const SegmentEntry &Entry) { diff --git a/llvm/lib/Support/VirtualFileSystem.cpp b/llvm/lib/Support/VirtualFileSystem.cpp index 54b9c38f7609..fcefdef992be 100644 --- a/llvm/lib/Support/VirtualFileSystem.cpp +++ b/llvm/lib/Support/VirtualFileSystem.cpp @@ -1725,7 +1725,7 @@ public: RedirectingFileSystem::Entry *ParentEntry = nullptr) { if (!ParentEntry) { // Look for a existent root for (const auto &Root : FS->Roots) { - if (Name.equals(Root->getName())) { + if (Name == Root->getName()) { ParentEntry = Root.get(); return ParentEntry; } @@ -1736,7 +1736,7 @@ public: llvm::make_range(DE->contents_begin(), DE->contents_end())) { auto *DirContent = dyn_cast(Content.get()); - if (DirContent && Name.equals(Content->getName())) + if (DirContent && Name == Content->getName()) return DirContent; } } diff --git a/llvm/lib/TargetParser/ARMTargetParser.cpp b/llvm/lib/TargetParser/ARMTargetParser.cpp index 67f937ebc33f..9d9917d86a36 100644 --- a/llvm/lib/TargetParser/ARMTargetParser.cpp +++ b/llvm/lib/TargetParser/ARMTargetParser.cpp @@ -610,7 +610,7 @@ StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) { return StringRef(); StringRef CPU = llvm::ARM::getDefaultCPU(MArch); - if (!CPU.empty() && !CPU.equals("invalid")) + if (!CPU.empty() && CPU != "invalid") return CPU; // If no specific architecture version is requested, return the minimum CPU diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp index ef40ccf36806..f8269a51dc0b 100644 --- a/llvm/lib/TargetParser/Triple.cpp +++ b/llvm/lib/TargetParser/Triple.cpp @@ -373,14 +373,14 @@ StringRef Triple::getObjectFormatTypeName(ObjectFormatType Kind) { } static Triple::ArchType parseBPFArch(StringRef ArchName) { - if (ArchName.equals("bpf")) { + if (ArchName == "bpf") { if (sys::IsLittleEndianHost) return Triple::bpfel; else return Triple::bpfeb; - } else if (ArchName.equals("bpf_be") || ArchName.equals("bpfeb")) { + } else if (ArchName == "bpf_be" || ArchName == "bpfeb") { return Triple::bpfeb; - } else if (ArchName.equals("bpf_le") || ArchName.equals("bpfel")) { + } else if (ArchName == "bpf_le" || ArchName == "bpfel") { return Triple::bpfel; } else { return Triple::UnknownArch; diff --git a/llvm/tools/dsymutil/DwarfLinkerForBinary.cpp b/llvm/tools/dsymutil/DwarfLinkerForBinary.cpp index 7246ba45d5af..83473704398d 100644 --- a/llvm/tools/dsymutil/DwarfLinkerForBinary.cpp +++ b/llvm/tools/dsymutil/DwarfLinkerForBinary.cpp @@ -705,7 +705,7 @@ bool DwarfLinkerForBinary::linkImpl( } else { // Try and emit more helpful warnings by applying some heuristics. StringRef ObjFile = ContainerName; - bool IsClangModule = sys::path::extension(Path).equals(".pcm"); + bool IsClangModule = sys::path::extension(Path) == ".pcm"; bool IsArchive = ObjFile.ends_with(")"); if (IsClangModule) { diff --git a/llvm/tools/llvm-dwarfdump/Statistics.cpp b/llvm/tools/llvm-dwarfdump/Statistics.cpp index 96841c3c387b..1846f9265c75 100644 --- a/llvm/tools/llvm-dwarfdump/Statistics.cpp +++ b/llvm/tools/llvm-dwarfdump/Statistics.cpp @@ -229,7 +229,7 @@ static std::string constructDieID(DWARFDie Die, << Die.getName(DINameKind::LinkageName); // Prefix + Name is enough for local variables and parameters. - if (!Prefix.empty() && !Prefix.equals("g")) + if (!Prefix.empty() && Prefix != "g") return ID.str(); auto DeclFile = Die.findRecursively(dwarf::DW_AT_decl_file); diff --git a/llvm/tools/llvm-extract/llvm-extract.cpp b/llvm/tools/llvm-extract/llvm-extract.cpp index a879c203fc37..5915f92ea05c 100644 --- a/llvm/tools/llvm-extract/llvm-extract.cpp +++ b/llvm/tools/llvm-extract/llvm-extract.cpp @@ -357,7 +357,7 @@ int main(int argc, char **argv) { // The function has been materialized, so add its matching basic blocks // to the block extractor list, or fail if a name is not found. auto Res = llvm::find_if(*P.first, [&](const BasicBlock &BB) { - return BB.getName().equals(BBName); + return BB.getName() == BBName; }); if (Res == P.first->end()) { errs() << argv[0] << ": function " << P.first->getName() diff --git a/llvm/tools/llvm-objdump/MachODump.cpp b/llvm/tools/llvm-objdump/MachODump.cpp index 5e0d69a68d69..749f98820175 100644 --- a/llvm/tools/llvm-objdump/MachODump.cpp +++ b/llvm/tools/llvm-objdump/MachODump.cpp @@ -2148,7 +2148,7 @@ static void ProcessMachO(StringRef Name, MachOObjectFile *MachOOF, else consumeError(NameOrErr.takeError()); - if (SectName.equals("__text")) { + if (SectName == "__text") { DataRefImpl Ref = Section.getRawDataRefImpl(); StringRef SegName = MachOOF->getSectionFinalSegmentName(Ref); DisassembleMachO(FileName, MachOOF, SegName, SectName); diff --git a/llvm/tools/llvm-xray/xray-graph-diff.cpp b/llvm/tools/llvm-xray/xray-graph-diff.cpp index 899a6725a5d3..b5c63ab0a918 100644 --- a/llvm/tools/llvm-xray/xray-graph-diff.cpp +++ b/llvm/tools/llvm-xray/xray-graph-diff.cpp @@ -381,14 +381,14 @@ void GraphDiffRenderer::exportGraphAsDOT(raw_ostream &OS, StatType EdgeLabel, R"(color="{5}" labelfontcolor="{5}" penwidth={6}])" "\n", VertexNo[HeadId], VertexNo[TailId], - (HeadId.equals("")) ? static_cast("F0") : HeadId, + HeadId.empty() ? static_cast("F0") : HeadId, TailId, getLabel(E, EdgeLabel), getColor(E, G, H, EdgeColor), getLineWidth(E, EdgeColor)); } for (const auto &V : G.vertices()) { const auto &VertexId = V.first; - if (VertexId.equals("")) { + if (VertexId.empty()) { OS << formatv(R"(F{0} [label="F0"])" "\n", VertexNo[VertexId]); diff --git a/llvm/tools/llvm-yaml-numeric-parser-fuzzer/yaml-numeric-parser-fuzzer.cpp b/llvm/tools/llvm-yaml-numeric-parser-fuzzer/yaml-numeric-parser-fuzzer.cpp index c8370289963d..9a572c1e0600 100644 --- a/llvm/tools/llvm-yaml-numeric-parser-fuzzer/yaml-numeric-parser-fuzzer.cpp +++ b/llvm/tools/llvm-yaml-numeric-parser-fuzzer/yaml-numeric-parser-fuzzer.cpp @@ -18,7 +18,7 @@ inline bool isNumericRegex(llvm::StringRef S) { static llvm::Regex Float( "^[-+]?(\\.[0-9]+|[0-9]+(\\.[0-9]*)?)([eE][-+]?[0-9]+)?$"); - if (S.equals(".nan") || S.equals(".NaN") || S.equals(".NAN")) + if (S == ".nan" || S == ".NaN" || S == ".NAN") return true; if (Infinity.match(S)) diff --git a/llvm/unittests/ADT/StringRefTest.cpp b/llvm/unittests/ADT/StringRefTest.cpp index fa537e816fc8..b3c206a33696 100644 --- a/llvm/unittests/ADT/StringRefTest.cpp +++ b/llvm/unittests/ADT/StringRefTest.cpp @@ -998,7 +998,7 @@ TEST(StringRefTest, AllocatorCopy) { // allocator. StringRef StrEmpty = ""; StringRef StrEmptyc = StrEmpty.copy(Alloc); - EXPECT_TRUE(StrEmpty.equals(StrEmptyc)); + EXPECT_TRUE(StrEmpty == StrEmptyc); EXPECT_EQ(StrEmptyc.data(), nullptr); EXPECT_EQ(StrEmptyc.size(), 0u); EXPECT_EQ(Alloc.getTotalMemory(), 0u); @@ -1007,9 +1007,9 @@ TEST(StringRefTest, AllocatorCopy) { StringRef Str2 = "bye"; StringRef Str1c = Str1.copy(Alloc); StringRef Str2c = Str2.copy(Alloc); - EXPECT_TRUE(Str1.equals(Str1c)); + EXPECT_TRUE(Str1 == Str1c); EXPECT_NE(Str1.data(), Str1c.data()); - EXPECT_TRUE(Str2.equals(Str2c)); + EXPECT_TRUE(Str2 == Str2c); EXPECT_NE(Str2.data(), Str2c.data()); } diff --git a/llvm/unittests/IR/VerifierTest.cpp b/llvm/unittests/IR/VerifierTest.cpp index c8db7fb7ab84..d79b4f3d8a44 100644 --- a/llvm/unittests/IR/VerifierTest.cpp +++ b/llvm/unittests/IR/VerifierTest.cpp @@ -173,27 +173,27 @@ TEST(VerifierTest, CrossModuleRef) { std::string Error; raw_string_ostream ErrorOS(Error); EXPECT_TRUE(verifyModule(M2, &ErrorOS)); - EXPECT_TRUE(StringRef(ErrorOS.str()) - .equals("Global is referenced in a different module!\n" - "ptr @foo2\n" - "; ModuleID = 'M2'\n" - " %call = call i32 @foo2()\n" - "ptr @foo1\n" - "; ModuleID = 'M1'\n" - "Global is used by function in a different module\n" - "ptr @foo2\n" - "; ModuleID = 'M2'\n" - "ptr @foo3\n" - "; ModuleID = 'M3'\n")); + EXPECT_TRUE(StringRef(ErrorOS.str()) == + "Global is referenced in a different module!\n" + "ptr @foo2\n" + "; ModuleID = 'M2'\n" + " %call = call i32 @foo2()\n" + "ptr @foo1\n" + "; ModuleID = 'M1'\n" + "Global is used by function in a different module\n" + "ptr @foo2\n" + "; ModuleID = 'M2'\n" + "ptr @foo3\n" + "; ModuleID = 'M3'\n"); Error.clear(); EXPECT_TRUE(verifyModule(M1, &ErrorOS)); - EXPECT_TRUE(StringRef(ErrorOS.str()).equals( - "Referencing function in another module!\n" - " %call = call i32 @foo2()\n" - "; ModuleID = 'M1'\n" - "ptr @foo2\n" - "; ModuleID = 'M2'\n")); + EXPECT_TRUE(StringRef(ErrorOS.str()) == + "Referencing function in another module!\n" + " %call = call i32 @foo2()\n" + "; ModuleID = 'M1'\n" + "ptr @foo2\n" + "; ModuleID = 'M2'\n"); Error.clear(); EXPECT_TRUE(verifyModule(M3, &ErrorOS)); diff --git a/llvm/unittests/Support/MemoryBufferTest.cpp b/llvm/unittests/Support/MemoryBufferTest.cpp index cfee3e477d2e..4815e65c968d 100644 --- a/llvm/unittests/Support/MemoryBufferTest.cpp +++ b/llvm/unittests/Support/MemoryBufferTest.cpp @@ -317,13 +317,13 @@ TEST_F(MemoryBufferTest, slice) { EXPECT_EQ(0x4000UL, MB.get()->getBufferSize()); StringRef BufData = MB.get()->getBuffer(); - EXPECT_TRUE(BufData.substr(0x0000,8).equals("12345678")); - EXPECT_TRUE(BufData.substr(0x0FF8,8).equals("12345678")); - EXPECT_TRUE(BufData.substr(0x1000,8).equals("abcdefgh")); - EXPECT_TRUE(BufData.substr(0x2FF8,8).equals("abcdefgh")); - EXPECT_TRUE(BufData.substr(0x3000,8).equals("ABCDEFGH")); - EXPECT_TRUE(BufData.substr(0x3FF8,8).equals("ABCDEFGH")); - + EXPECT_TRUE(BufData.substr(0x0000, 8) == "12345678"); + EXPECT_TRUE(BufData.substr(0x0FF8, 8) == "12345678"); + EXPECT_TRUE(BufData.substr(0x1000, 8) == "abcdefgh"); + EXPECT_TRUE(BufData.substr(0x2FF8, 8) == "abcdefgh"); + EXPECT_TRUE(BufData.substr(0x3000, 8) == "ABCDEFGH"); + EXPECT_TRUE(BufData.substr(0x3FF8, 8) == "ABCDEFGH"); + // Try non-page aligned. ErrorOr MB2 = MemoryBuffer::getFileSlice(TestPath.str(), 0x3000, 0x0800); @@ -332,10 +332,10 @@ TEST_F(MemoryBufferTest, slice) { EXPECT_EQ(0x3000UL, MB2.get()->getBufferSize()); StringRef BufData2 = MB2.get()->getBuffer(); - EXPECT_TRUE(BufData2.substr(0x0000,8).equals("12345678")); - EXPECT_TRUE(BufData2.substr(0x17F8,8).equals("12345678")); - EXPECT_TRUE(BufData2.substr(0x1800,8).equals("abcdefgh")); - EXPECT_TRUE(BufData2.substr(0x2FF8,8).equals("abcdefgh")); + EXPECT_TRUE(BufData2.substr(0x0000, 8) == "12345678"); + EXPECT_TRUE(BufData2.substr(0x17F8, 8) == "12345678"); + EXPECT_TRUE(BufData2.substr(0x1800, 8) == "abcdefgh"); + EXPECT_TRUE(BufData2.substr(0x2FF8, 8) == "abcdefgh"); } TEST_F(MemoryBufferTest, writableSlice) { diff --git a/llvm/unittests/Support/YAMLIOTest.cpp b/llvm/unittests/Support/YAMLIOTest.cpp index 6ac0d1b412f0..9d40b62115a6 100644 --- a/llvm/unittests/Support/YAMLIOTest.cpp +++ b/llvm/unittests/Support/YAMLIOTest.cpp @@ -1389,10 +1389,10 @@ TEST(YAMLIO, TestReadWriteMyFlowSequence) { yin >> map2; EXPECT_FALSE(yin.error()); - EXPECT_TRUE(map2.name.equals("hello")); + EXPECT_TRUE(map2.name == "hello"); EXPECT_EQ(map2.strings.size(), 2UL); - EXPECT_TRUE(map2.strings[0].value.equals("one")); - EXPECT_TRUE(map2.strings[1].value.equals("two")); + EXPECT_TRUE(map2.strings[0].value == "one"); + EXPECT_TRUE(map2.strings[1].value == "two"); EXPECT_EQ(map2.single.size(), 1UL); EXPECT_EQ(1, map2.single[0]); EXPECT_EQ(map2.numbers.size(), 3UL); @@ -1436,7 +1436,7 @@ TEST(YAMLIO, TestReadWriteSequenceOfMyFlowSequence) { yin >> map2; EXPECT_FALSE(yin.error()); - EXPECT_TRUE(map2.name.equals("hello")); + EXPECT_TRUE(map2.name == "hello"); EXPECT_EQ(map2.sequenceOfNumbers.size(), 3UL); EXPECT_EQ(map2.sequenceOfNumbers[0].size(), 1UL); EXPECT_EQ(0, map2.sequenceOfNumbers[0][0]); diff --git a/llvm/unittests/TargetParser/CSKYTargetParserTest.cpp b/llvm/unittests/TargetParser/CSKYTargetParserTest.cpp index f28a2a33eb90..50e825c5f99f 100644 --- a/llvm/unittests/TargetParser/CSKYTargetParserTest.cpp +++ b/llvm/unittests/TargetParser/CSKYTargetParserTest.cpp @@ -1020,7 +1020,7 @@ TEST(TargetParserTest, testInvalidCSKYArch) { bool testCSKYArch(StringRef Arch, StringRef DefaultCPU) { CSKY::ArchKind AK = CSKY::parseArch(Arch); bool Result = (AK != CSKY::ArchKind::INVALID); - Result &= CSKY::getDefaultCPU(Arch).equals(DefaultCPU); + Result &= CSKY::getDefaultCPU(Arch) == DefaultCPU; return Result; } diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index cc098c264065..b61928bd8f98 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -572,8 +572,8 @@ bool testARMArch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch, unsigned ArchAttr) { ARM::ArchKind AK = ARM::parseArch(Arch); bool Result = (AK != ARM::ArchKind::INVALID); - Result &= ARM::getDefaultCPU(Arch).equals(DefaultCPU); - Result &= ARM::getSubArch(AK).equals(SubArch); + Result &= ARM::getDefaultCPU(Arch) == DefaultCPU; + Result &= ARM::getSubArch(AK) == SubArch; Result &= (ARM::getArchAttr(AK) == ArchAttr); return Result; } diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp index 53d49a2900a1..8e475f9153b0 100644 --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -3121,7 +3121,7 @@ static void emitMnemonicSpellChecker(raw_ostream &OS, CodeGenTarget &Target, OS << "\n"; OS << " StringRef T = I->getMnemonic();\n"; OS << " // Avoid recomputing the edit distance for the same string.\n"; - OS << " if (T.equals(Prev))\n"; + OS << " if (T == Prev)\n"; OS << " continue;\n"; OS << "\n"; OS << " Prev = T;\n"; -- GitLab From dabdec1001dc368373dd581cf72f37a440873ce3 Mon Sep 17 00:00:00 2001 From: Benoit Jacob Date: Wed, 8 May 2024 13:37:05 -0400 Subject: [PATCH 057/328] Fix `memref.expand_shape` verifier (#91501) Torch-mlir integration is currently blocked on `memref.expand_shape` verifier errors of the form ``` 'memref.expand_shape' op invalid output shape provided at pos 1 ``` The verifier code generating these errors was introduced in https://github.com/llvm/llvm-project/pull/91245. I have commented there why I believe it's incorrect. This PR has my suggested fix. Unfortunately, this does not seem to be directly testable on `memref` IR, because `static_output_shape` is not directly exposed in the custom assembly format. --- mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp | 11 +++++------ mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir | 2 +- mlir/test/Dialect/MemRef/ops.mlir | 7 ++++++- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp b/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp index 78201ae29cd9..c9a85919ec79 100644 --- a/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp +++ b/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp @@ -2356,12 +2356,11 @@ LogicalResult ExpandShapeOp::verify() { // Verify if provided output shapes are in agreement with output type. DenseI64ArrayAttr staticOutputShapes = getStaticOutputShapeAttr(); ArrayRef resShape = getResult().getType().getShape(); - unsigned staticShapeNum = 0; - - for (auto [pos, shape] : llvm::enumerate(resShape)) - if (!ShapedType::isDynamic(shape) && - shape != staticOutputShapes[staticShapeNum++]) - emitOpError("invalid output shape provided at pos ") << pos; + for (auto [pos, shape] : llvm::enumerate(resShape)) { + if (!ShapedType::isDynamic(shape) && shape != staticOutputShapes[pos]) { + return emitOpError("invalid output shape provided at pos ") << pos; + } + } return success(); } diff --git a/mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir b/mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir index 99b5f78b03fb..e49dff44ae0d 100644 --- a/mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir +++ b/mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir @@ -502,7 +502,7 @@ func.func @fold_dynamic_subview_with_memref_store_expand_shape(%arg0 : memref<16 // CHECK-SAME: (%[[ARG0:.*]]: memref<2048x16xf32>, %[[ARG1:.*]]: index, %[[ARG2:.*]]: index, %[[ARG3:.*]]: index, %[[ARG4:.*]]: index) func.func @fold_memref_alias_expand_shape_subview_load_store_dynamic_dim(%alloc: memref<2048x16xf32>, %c10: index, %c5: index, %c0: index, %sz0: index) { %subview = memref.subview %alloc[%c5, 0] [%c10, 16] [1, 1] : memref<2048x16xf32> to memref> - %expand_shape = memref.expand_shape %subview [[0], [1, 2, 3]] output_shape [1, 16, %sz0, 1] : memref> into memref> + %expand_shape = memref.expand_shape %subview [[0], [1, 2, 3]] output_shape [%sz0, 1, 8, 2] : memref> into memref> %dim = memref.dim %expand_shape, %c0 : memref> affine.for %arg6 = 0 to %dim step 64 { diff --git a/mlir/test/Dialect/MemRef/ops.mlir b/mlir/test/Dialect/MemRef/ops.mlir index 60fb0ffeee24..b60894377f22 100644 --- a/mlir/test/Dialect/MemRef/ops.mlir +++ b/mlir/test/Dialect/MemRef/ops.mlir @@ -203,7 +203,8 @@ func.func @expand_collapse_shape_dynamic(%arg0: memref, %arg3: memref>, %arg4: index, %arg5: index, - %arg6: index) { + %arg6: index, + %arg7: memref<4x?x4xf32>) { // CHECK: memref.collapse_shape {{.*}} {{\[}}[0, 1], [2]] // CHECK-SAME: memref into memref %0 = memref.collapse_shape %arg0 [[0, 1], [2]] : @@ -248,6 +249,10 @@ func.func @expand_collapse_shape_dynamic(%arg0: memref, // CHECK-SAME: memref> into memref %r3 = memref.expand_shape %3 [[0, 1]] output_shape [%arg6, 42] : memref> into memref + +// CHECK: memref.expand_shape {{.*}} {{\[}}[0, 1], [2], [3, 4]] + %4 = memref.expand_shape %arg7 [[0, 1], [2], [3, 4]] output_shape [2, 2, %arg4, 2, 2] + : memref<4x?x4xf32> into memref<2x2x?x2x2xf32> return } -- GitLab From fcfc15b7052a311b7a045e2c6bd26fb5d0b7122c Mon Sep 17 00:00:00 2001 From: Adrian Prantl Date: Wed, 8 May 2024 10:38:09 -0700 Subject: [PATCH 058/328] =?UTF-8?q?Add=20a=20dependency=20from=20lldb-sbap?= =?UTF-8?q?i-dwarf-enums=20as=20a=20dependency=20of=20libll=E2=80=A6=20(#9?= =?UTF-8?q?1511)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …db-resource-headers The Xcode build otherwise fails with ``` CMake Error in source/API/CMakeLists.txt: The custom command generating /Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-standalone/lldb-xcode-build/include/lldb/API/SBLanguages.h is attached to multiple targets: lldb-sbapi-dwarf-enums liblldb-resource-headers but none of these is a common dependency of the other(s). This is not allowed by the Xcode "new build system". CMake Generate step failed. Build files cannot be regenerated correctly. ``` --- lldb/cmake/modules/LLDBFramework.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lldb/cmake/modules/LLDBFramework.cmake b/lldb/cmake/modules/LLDBFramework.cmake index df2f8ddf54a3..dd8c36bba0e9 100644 --- a/lldb/cmake/modules/LLDBFramework.cmake +++ b/lldb/cmake/modules/LLDBFramework.cmake @@ -105,7 +105,7 @@ foreach(header endforeach() # Wrap output in a target, so lldb-framework can depend on it. -add_custom_target(liblldb-resource-headers DEPENDS ${lldb_staged_headers}) +add_custom_target(liblldb-resource-headers DEPENDS lldb-sbapi-dwarf-enums ${lldb_staged_headers}) set_target_properties(liblldb-resource-headers PROPERTIES FOLDER "lldb misc") add_dependencies(liblldb liblldb-resource-headers) -- GitLab From dbcfa2957d9f99de62fc86db12a857caf929583c Mon Sep 17 00:00:00 2001 From: Nicklas Boman Date: Wed, 8 May 2024 19:57:16 +0200 Subject: [PATCH 059/328] =?UTF-8?q?lldb=20create=20API=20folder=20if=20it?= =?UTF-8?q?=20does=20not=20exist,=20before=20creating=20SBLangua=E2=80=A6?= =?UTF-8?q?=20(#91128)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Create API folder if it does not exist, before creating SBLanguages.h --- lldb/scripts/generate-sbapi-dwarf-enum.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lldb/scripts/generate-sbapi-dwarf-enum.py b/lldb/scripts/generate-sbapi-dwarf-enum.py index 464eb2afff7d..f7a13e5efffe 100755 --- a/lldb/scripts/generate-sbapi-dwarf-enum.py +++ b/lldb/scripts/generate-sbapi-dwarf-enum.py @@ -2,6 +2,7 @@ import argparse import re +import os HEADER = """\ //===-- SBLanguages.h -----------------------------------------*- C++ -*-===// @@ -37,6 +38,9 @@ def emit_enum(input, output): with open(input, "r") as f: lines = f.readlines() + # Create output folder if it does not exist + os.makedirs(os.path.dirname(output), exist_ok=True) + # Write the output. with open(output, "w") as f: # Emit the header. -- GitLab From 42d99013bd6b7ed4a085e39c94ab86938d633f8a Mon Sep 17 00:00:00 2001 From: AdityaK Date: Wed, 8 May 2024 11:03:46 -0700 Subject: [PATCH 060/328] NFC: Add a comment indicating UpdateAnalysisInformation invalidates DFS Numbering (#91252) --- llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp index b9ed077b660d..462283c0bfe0 100644 --- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp +++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp @@ -1141,6 +1141,7 @@ BasicBlock *llvm::splitBlockBefore(BasicBlock *Old, BasicBlock::iterator SplitPt } /// Update DominatorTree, LoopInfo, and LCCSA analysis information. +/// Invalidates DFS Numbering when DTU or DT is provided. static void UpdateAnalysisInformation(BasicBlock *OldBB, BasicBlock *NewBB, ArrayRef Preds, DomTreeUpdater *DTU, DominatorTree *DT, -- GitLab From 10bdcf6b4cd37d017753b3821fbf8eb2ad924a1a Mon Sep 17 00:00:00 2001 From: Piotr Zegar Date: Wed, 8 May 2024 20:10:47 +0200 Subject: [PATCH 061/328] [clang-tidy] Handle implicit casts in hicpp-signed-bitwise for IgnorePositiveIntegerLiterals (#90621) Improved hicpp-signed-bitwise check by ignoring false positives involving positive integer literals behind implicit casts when IgnorePositiveIntegerLiterals is enabled. Closes #89367 --- clang-tools-extra/clang-tidy/hicpp/SignedBitwiseCheck.cpp | 5 +++-- clang-tools-extra/docs/ReleaseNotes.rst | 4 ++++ .../checkers/hicpp/signed-bitwise-integer-literals.cpp | 3 +++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/clang-tools-extra/clang-tidy/hicpp/SignedBitwiseCheck.cpp b/clang-tools-extra/clang-tidy/hicpp/SignedBitwiseCheck.cpp index 51cc26400f7f..bf09a6662d95 100644 --- a/clang-tools-extra/clang-tidy/hicpp/SignedBitwiseCheck.cpp +++ b/clang-tools-extra/clang-tidy/hicpp/SignedBitwiseCheck.cpp @@ -9,6 +9,7 @@ #include "SignedBitwiseCheck.h" #include "clang/AST/ASTContext.h" #include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/ASTMatchers/ASTMatchers.h" using namespace clang::ast_matchers; using namespace clang::ast_matchers::internal; @@ -29,8 +30,8 @@ void SignedBitwiseCheck::storeOptions(ClangTidyOptions::OptionMap &Opts) { void SignedBitwiseCheck::registerMatchers(MatchFinder *Finder) { const auto SignedIntegerOperand = (IgnorePositiveIntegerLiterals - ? expr(ignoringImpCasts(hasType(isSignedInteger())), - unless(integerLiteral())) + ? expr(ignoringImpCasts( + allOf(hasType(isSignedInteger()), unless(integerLiteral())))) : expr(ignoringImpCasts(hasType(isSignedInteger())))) .bind("signed-operand"); diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 5d6d0351362e..c4c9df27ee1e 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -259,6 +259,10 @@ Changes in existing checks - Improved :doc:`google-runtime-int ` check performance through optimizations. +- Improved :doc:`hicpp-signed-bitwise ` + check by ignoring false positives involving positive integer literals behind + implicit casts when `IgnorePositiveIntegerLiterals` is enabled. + - Improved :doc:`hicpp-ignored-remove-result ` check by ignoring other functions with same prefixes as the target specific functions. diff --git a/clang-tools-extra/test/clang-tidy/checkers/hicpp/signed-bitwise-integer-literals.cpp b/clang-tools-extra/test/clang-tidy/checkers/hicpp/signed-bitwise-integer-literals.cpp index edbb56f90cb0..aca7ae1fd76f 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/hicpp/signed-bitwise-integer-literals.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/hicpp/signed-bitwise-integer-literals.cpp @@ -11,6 +11,7 @@ void examples() { // CHECK-MESSAGES: :[[@LINE-1]]:19: warning: use of a signed integer operand with a binary bitwise operator unsigned URes2 = URes << 1; //Ok + unsigned URes3 = URes & 1; //Ok int IResult; IResult = 10 & 2; //Ok @@ -21,6 +22,8 @@ void examples() { IResult = Int << 1; // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: use of a signed integer operand with a binary bitwise operator IResult = ~0; //Ok + IResult = -1 & 1; + // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: use of a signed integer operand with a binary bitwise operator [hicpp-signed-bitwise] } enum EnumConstruction { -- GitLab From 37b6ba96dea54e7af3772d78c90bfb3fd61140f6 Mon Sep 17 00:00:00 2001 From: Piotr Zegar Date: Wed, 8 May 2024 20:11:10 +0200 Subject: [PATCH 062/328] [clang-tidy] Handle expr with side-effects in readability-static-accessed-through-instance (#90736) Improved readability-static-accessed-through-instance check to support expressions with side-effects. Originally calls to overloaded operator were ignored by check, in fear of possible side-effects. This change remove that restriction, and enables fix-its for expressions with side-effect via --fix-notes. Closes #75163 --- .../StaticAccessedThroughInstanceCheck.cpp | 37 +++++++++++------- clang-tools-extra/docs/ReleaseNotes.rst | 5 +++ .../static-accessed-through-instance.rst | 3 ++ .../static-accessed-through-instance.cpp | 38 +++++++++++++++---- 4 files changed, 62 insertions(+), 21 deletions(-) diff --git a/clang-tools-extra/clang-tidy/readability/StaticAccessedThroughInstanceCheck.cpp b/clang-tools-extra/clang-tidy/readability/StaticAccessedThroughInstanceCheck.cpp index 65356cc3929c..08adc7134cfe 100644 --- a/clang-tools-extra/clang-tidy/readability/StaticAccessedThroughInstanceCheck.cpp +++ b/clang-tools-extra/clang-tidy/readability/StaticAccessedThroughInstanceCheck.cpp @@ -59,10 +59,6 @@ void StaticAccessedThroughInstanceCheck::check( const Expr *BaseExpr = MemberExpression->getBase(); - // Do not warn for overloaded -> operators. - if (isa(BaseExpr)) - return; - const QualType BaseType = BaseExpr->getType()->isPointerType() ? BaseExpr->getType()->getPointeeType().getUnqualifiedType() @@ -89,17 +85,30 @@ void StaticAccessedThroughInstanceCheck::check( return; SourceLocation MemberExprStartLoc = MemberExpression->getBeginLoc(); - auto Diag = - diag(MemberExprStartLoc, "static member accessed through instance"); - - if (BaseExpr->HasSideEffects(*AstContext) || - getNameSpecifierNestingLevel(BaseType) > NameSpecifierNestingThreshold) - return; + auto CreateFix = [&] { + return FixItHint::CreateReplacement( + CharSourceRange::getCharRange(MemberExprStartLoc, + MemberExpression->getMemberLoc()), + BaseTypeName + "::"); + }; + + { + auto Diag = + diag(MemberExprStartLoc, "static member accessed through instance"); + + if (getNameSpecifierNestingLevel(BaseType) > NameSpecifierNestingThreshold) + return; + + if (!BaseExpr->HasSideEffects(*AstContext, + /* IncludePossibleEffects =*/true)) { + Diag << CreateFix(); + return; + } + } - Diag << FixItHint::CreateReplacement( - CharSourceRange::getCharRange(MemberExprStartLoc, - MemberExpression->getMemberLoc()), - BaseTypeName + "::"); + diag(MemberExprStartLoc, "member base expression may carry some side effects", + DiagnosticIDs::Level::Note) + << BaseExpr->getSourceRange() << CreateFix(); } } // namespace clang::tidy::readability diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index c4c9df27ee1e..5b7ea42c63d6 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -352,6 +352,11 @@ Changes in existing checks ` check to properly emit warnings for static data member with an in-class initializer. +- Improved :doc:`readability-static-accessed-through-instance + ` check to + support calls to overloaded operators as base expression and provide fixes to + expressions with side-effects. + - Improved :doc:`readability-static-definition-in-anonymous-namespace ` check by resolving fix-it overlaps in template code by disregarding implicit diff --git a/clang-tools-extra/docs/clang-tidy/checks/readability/static-accessed-through-instance.rst b/clang-tools-extra/docs/clang-tidy/checks/readability/static-accessed-through-instance.rst index 23d12f418366..ffb3738bf72c 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/readability/static-accessed-through-instance.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/readability/static-accessed-through-instance.rst @@ -35,3 +35,6 @@ is changed to: C::E1; C::E2; +The `--fix` commandline option provides default support for safe fixes, whereas +`--fix-notes` enables fixes that may replace expressions with side effects, +potentially altering the program's behavior. diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/static-accessed-through-instance.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/static-accessed-through-instance.cpp index 81c1cecf607f..202fe9be6d00 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/static-accessed-through-instance.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/static-accessed-through-instance.cpp @@ -1,4 +1,4 @@ -// RUN: %check_clang_tidy %s readability-static-accessed-through-instance %t -- -- -isystem %S/Inputs/static-accessed-through-instance +// RUN: %check_clang_tidy %s readability-static-accessed-through-instance %t -- --fix-notes -- -isystem %S/Inputs/static-accessed-through-instance #include <__clang_cuda_builtin_vars.h> enum OutEnum { @@ -47,7 +47,8 @@ C &f(int, int, int, int); void g() { f(1, 2, 3, 4).x; // CHECK-MESSAGES: :[[@LINE-1]]:3: warning: static member accessed through instance [readability-static-accessed-through-instance] - // CHECK-FIXES: {{^}} f(1, 2, 3, 4).x;{{$}} + // CHECK-MESSAGES: :[[@LINE-2]]:3: note: member base expression may carry some side effects + // CHECK-FIXES: {{^}} C::x;{{$}} } int i(int &); @@ -59,12 +60,14 @@ int k(bool); void f(C c) { j(i(h().x)); // CHECK-MESSAGES: :[[@LINE-1]]:7: warning: static member - // CHECK-FIXES: {{^}} j(i(h().x));{{$}} + // CHECK-MESSAGES: :[[@LINE-2]]:7: note: member base expression may carry some side effects + // CHECK-FIXES: {{^}} j(i(C::x));{{$}} // The execution of h() depends on the return value of a(). j(k(a() && h().x)); // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: static member - // CHECK-FIXES: {{^}} j(k(a() && h().x));{{$}} + // CHECK-MESSAGES: :[[@LINE-2]]:14: note: member base expression may carry some side effects + // CHECK-FIXES: {{^}} j(k(a() && C::x));{{$}} if ([c]() { c.ns(); @@ -72,7 +75,8 @@ void f(C c) { }().x == 15) ; // CHECK-MESSAGES: :[[@LINE-5]]:7: warning: static member - // CHECK-FIXES: {{^}} if ([c]() {{{$}} + // CHECK-MESSAGES: :[[@LINE-6]]:7: note: member base expression may carry some side effects + // CHECK-FIXES: {{^}} if (C::x == 15){{$}} } // Nested specifiers @@ -261,8 +265,11 @@ struct Qptr { }; int func(Qptr qp) { - qp->y = 10; // OK, the overloaded operator might have side-effects. - qp->K = 10; // + qp->y = 10; + qp->K = 10; + // CHECK-MESSAGES: :[[@LINE-1]]:3: warning: static member accessed through instance [readability-static-accessed-through-instance] + // CHECK-MESSAGES: :[[@LINE-2]]:3: note: member base expression may carry some side effects + // CHECK-FIXES: {{^}} Q::K = 10; } namespace { @@ -380,3 +387,20 @@ namespace PR51861 { // CHECK-FIXES: {{^}} PR51861::Foo::getBar();{{$}} } } + +namespace PR75163 { + struct Static { + static void call(); + }; + + struct Ptr { + Static* operator->(); + }; + + void test(Ptr& ptr) { + ptr->call(); + // CHECK-MESSAGES: :[[@LINE-1]]:5: warning: static member accessed through instance [readability-static-accessed-through-instance] + // CHECK-MESSAGES: :[[@LINE-2]]:5: note: member base expression may carry some side effects + // CHECK-FIXES: {{^}} PR75163::Static::call();{{$}} + } +} -- GitLab From 79921fbd5c6223ff7e6c75ed75974b4d16cad529 Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Wed, 8 May 2024 20:17:59 +0200 Subject: [PATCH 063/328] [libc++][CI] Reenables clang-tidy. (#90077) The patch does several things: - fixes module exports - disables clang-tidy with Clang-17 due to known issues - disabled clang-tidy on older libstdc++ versions since it lacks C++20 features used - fixes the CMake dependency The issue why clang-tidy was not used in the CI was the last issue; the plugin was not a dependency of the tests. Without a plugin the tests disable clang-tidy. This was noticed while investigating https://github.com/llvm/llvm-project/issues/89898 --- libcxx/modules/std/chrono.inc | 18 +++++++++----- libcxx/modules/std/ranges.inc | 7 +++--- libcxx/test/CMakeLists.txt | 6 +++++ libcxx/test/libcxx/clang_tidy.gen.py | 3 +++ .../tools/clang_tidy_checks/CMakeLists.txt | 24 +++++++++++++++++-- 5 files changed, 47 insertions(+), 11 deletions(-) diff --git a/libcxx/modules/std/chrono.inc b/libcxx/modules/std/chrono.inc index 1265e21dc54e..813322a1797f 100644 --- a/libcxx/modules/std/chrono.inc +++ b/libcxx/modules/std/chrono.inc @@ -190,10 +190,11 @@ export namespace std { using std::chrono::make12; using std::chrono::make24; -#if !defined(_LIBCPP_HAS_NO_TIME_ZONE_DATABASE) && !defined(_LIBCPP_HAS_NO_FILESYSTEM) && \ - !defined(_LIBCPP_HAS_NO_LOCALIZATION) +#ifdef _LIBCPP_ENABLE_EXPERIMENTAL + +# if !defined(_LIBCPP_HAS_NO_TIME_ZONE_DATABASE) && !defined(_LIBCPP_HAS_NO_FILESYSTEM) && \ + !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# ifdef _LIBCPP_ENABLE_EXPERIMENTAL // [time.zone.db], time zone database using std::chrono::tzdb; using std::chrono::tzdb_list; @@ -213,11 +214,16 @@ export namespace std { using std::chrono::ambiguous_local_time; using std::chrono::nonexistent_local_time; # endif // if 0 +# endif // !defined(_LIBCPP_HAS_NO_TIME_ZONE_DATABASE) && !defined(_LIBCPP_HAS_NO_FILESYSTEM) && + // !defined(_LIBCPP_HAS_NO_LOCALIZATION) // [time.zone.info], information classes using std::chrono::local_info; using std::chrono::sys_info; +# if !defined(_LIBCPP_HAS_NO_TIME_ZONE_DATABASE) && !defined(_LIBCPP_HAS_NO_FILESYSTEM) && \ + !defined(_LIBCPP_HAS_NO_LOCALIZATION) + # if 0 // [time.zone.timezone], class time_zone using std::chrono::choose; @@ -246,9 +252,9 @@ export namespace std { // [time.format], formatting using std::chrono::local_time_format; # endif -# endif // _LIBCPP_ENABLE_EXPERIMENTAL -#endif // !defined(_LIBCPP_HAS_NO_TIME_ZONE_DATABASE) && !defined(_LIBCPP_HAS_NO_FILESYSTEM) && - // !defined(_LIBCPP_HAS_NO_LOCALIZATION) +# endif // !defined(_LIBCPP_HAS_NO_TIME_ZONE_DATABASE) && !defined(_LIBCPP_HAS_NO_FILESYSTEM) && + // !defined(_LIBCPP_HAS_NO_LOCALIZATION) +#endif // _LIBCPP_ENABLE_EXPERIMENTAL } // namespace chrono diff --git a/libcxx/modules/std/ranges.inc b/libcxx/modules/std/ranges.inc index 80f31c79a1a4..f71efe948ede 100644 --- a/libcxx/modules/std/ranges.inc +++ b/libcxx/modules/std/ranges.inc @@ -138,9 +138,6 @@ export namespace std { } #endif // _LIBCPP_HAS_NO_LOCALIZATION -#if _LIBCPP_STD_VER >= 23 - // [range.adaptor.object], range adaptor objects - using std::ranges::range_adaptor_closure; // Note: This declaration not in the synopsis or explicitly in the wording. // However it is needed for the range adaptors. // [range.adaptor.object]/3 @@ -151,7 +148,11 @@ export namespace std { // involving an object of type cv D as an operand to the | operator is // undefined if overload resolution selects a program-defined operator| // function. + // This is used internally in C++20 mode. using std::ranges::operator|; +#if _LIBCPP_STD_VER >= 23 + // [range.adaptor.object], range adaptor objects + using std::ranges::range_adaptor_closure; #endif // [range.all], all view diff --git a/libcxx/test/CMakeLists.txt b/libcxx/test/CMakeLists.txt index e0d3a0dbc400..fd57aa9fe8b3 100644 --- a/libcxx/test/CMakeLists.txt +++ b/libcxx/test/CMakeLists.txt @@ -1,5 +1,11 @@ include(HandleLitArguments) add_subdirectory(tools) +# When the tools add clang-tidy support, the dependencies need to be updated. +# This cannot be done in the tools CMakeLists.txt since that does not update +# the status in this (a parent) directory. +if(TARGET cxx-tidy) + list(APPEND LIBCXX_TEST_DEPS cxx-tidy) +endif() # By default, libcxx and libcxxabi share a library directory. if (NOT LIBCXX_CXX_ABI_LIBRARY_PATH) diff --git a/libcxx/test/libcxx/clang_tidy.gen.py b/libcxx/test/libcxx/clang_tidy.gen.py index f29447d00655..76b9db2d5cb8 100644 --- a/libcxx/test/libcxx/clang_tidy.gen.py +++ b/libcxx/test/libcxx/clang_tidy.gen.py @@ -26,6 +26,9 @@ for header in public_headers: // The GCC compiler flags are not always compatible with clang-tidy. // UNSUPPORTED: gcc +// Clang 17 has false positives. +// UNSUPPORTED: clang-17 + {lit_header_restrictions.get(header, '')} // TODO: run clang-tidy with modules enabled once they are supported diff --git a/libcxx/test/tools/clang_tidy_checks/CMakeLists.txt b/libcxx/test/tools/clang_tidy_checks/CMakeLists.txt index 28eed6144583..28c1dbf8aca3 100644 --- a/libcxx/test/tools/clang_tidy_checks/CMakeLists.txt +++ b/libcxx/test/tools/clang_tidy_checks/CMakeLists.txt @@ -64,6 +64,28 @@ if(NOT HAS_CLANG_TIDY_HEADERS) "clang-tidy headers are not present.") return() endif() + +# The clangTidy plugin uses C++20, so ensure that we support C++20 when using libstdc++. +# This is required because some versions of libstdc++ used as a system library on build platforms +# we support do not support C++20 yet. +# Note it has not been tested whether version 11 works. +file(WRITE "${CMAKE_CURRENT_BINARY_DIR}/test.cpp" " +#include +#if defined(_GLIBCXX_RELEASE) && _GLIBCXX_RELEASE < 12 + # error The libstdc++ version is too old. +#endif +int main(){} +") +try_compile(HAS_NEWER_STANDARD_LIBRARY + "${CMAKE_CURRENT_BINARY_DIR}" + "${CMAKE_CURRENT_BINARY_DIR}/test.cpp" + LINK_LIBRARIES clangTidy) + +if(NOT HAS_NEWER_STANDARD_LIBRARY) + message(STATUS "Clang-tidy tests are disabled due to using " + "stdlibc++ older than version 12") + return() +endif() message(STATUS "Clang-tidy tests are enabled.") set(SOURCES @@ -88,5 +110,3 @@ set_target_properties(cxx-tidy PROPERTIES set_target_properties(cxx-tidy PROPERTIES LIBRARY_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}) set(CMAKE_SHARED_MODULE_SUFFIX_CXX .plugin) # Use a portable suffix to simplify how we can find it from Lit - -list(APPEND LIBCXX_TEST_DEPS cxx-tidy) -- GitLab From a6b623705b13b0f69c302ee7b36fe87f833ff193 Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Wed, 8 May 2024 15:01:58 -0400 Subject: [PATCH 064/328] [gn] port 2868e26d0a6f (PERL_EXECUTABLE) --- llvm/utils/gn/secondary/clang/test/BUILD.gn | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/utils/gn/secondary/clang/test/BUILD.gn b/llvm/utils/gn/secondary/clang/test/BUILD.gn index 4ed9352da9c9..11454e68ec91 100644 --- a/llvm/utils/gn/secondary/clang/test/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/test/BUILD.gn @@ -116,11 +116,13 @@ write_lit_config("lit_site_cfg") { "CMAKE_LIBRARY_OUTPUT_DIRECTORY=" + rebase_path("$root_out_dir/bin", dir), "LLVM_LIT_ERRC_MESSAGES=no such file or directory;is a directory;" + "invalid argument;permission denied", + "PERL_EXECUTABLE=" ] } else { extra_values += [ "CMAKE_LIBRARY_OUTPUT_DIRECTORY=" + rebase_path("$root_out_dir/lib", dir), "LLVM_LIT_ERRC_MESSAGES=", + "PERL_EXECUTABLE=/usr/bin/perl" ] } -- GitLab From db29f20fdd4f715553f663f21021330cb4497e00 Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Wed, 8 May 2024 12:02:18 -0700 Subject: [PATCH 065/328] [BOLT] Ignore returns in DataAggregator Returns are ignored in perf/pre-aggregated/fdata profile reader (see DataReader::convertBranchData). They are also omitted in YAMLProfileWriter by virtue of not having the profile attached to them in the reader, and YAMLProfileWriter converting the profile attached to BinaryFunctions. Thus, return profile is universally ignored across all profile types except BAT YAML. To make returns ignored for YAML produced in BAT mode, we can: 1) ignore them in YAMLProfileReader, 2) omit them from YAML profile in profile conversion/writing. The first option is prone to profile staleness issue, where the profiled binary doesn't match the one to be optimized, and thus returns in the profile can no longer be reliably detected (as we don't distinguish them from calls in the profile). The second option is robust to staleness but requires disassembling the branch source instruction. Test Plan: Updated bolt-address-translation-yaml.test Reviewers: rafaelauler, dcci, ayermolo, maksfb Reviewed By: maksfb Pull Request: https://github.com/llvm/llvm-project/pull/90807 --- bolt/include/bolt/Core/BinaryFunction.h | 2 ++ bolt/lib/Core/BinaryFunction.cpp | 15 +++++++++++++++ bolt/lib/Profile/DataAggregator.cpp | 13 +++++++++++++ bolt/test/X86/bolt-address-translation-yaml.test | 5 +++-- 4 files changed, 33 insertions(+), 2 deletions(-) diff --git a/bolt/include/bolt/Core/BinaryFunction.h b/bolt/include/bolt/Core/BinaryFunction.h index 26d2d01f8626..3c641581e247 100644 --- a/bolt/include/bolt/Core/BinaryFunction.h +++ b/bolt/include/bolt/Core/BinaryFunction.h @@ -930,6 +930,8 @@ public: return const_cast(this)->getInstructionAtOffset(Offset); } + std::optional disassembleInstructionAtOffset(uint64_t Offset) const; + /// Return offset for the first instruction. If there is data at the /// beginning of a function then offset of the first instruction could /// be different from 0 diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp index 1fa96dfaabde..de34421ebeb0 100644 --- a/bolt/lib/Core/BinaryFunction.cpp +++ b/bolt/lib/Core/BinaryFunction.cpp @@ -1167,6 +1167,21 @@ void BinaryFunction::handleAArch64IndirectCall(MCInst &Instruction, } } +std::optional +BinaryFunction::disassembleInstructionAtOffset(uint64_t Offset) const { + assert(CurrentState == State::Empty && "Function should not be disassembled"); + assert(Offset < MaxSize && "Invalid offset"); + ErrorOr> FunctionData = getData(); + assert(FunctionData && "Cannot get function as data"); + MCInst Instr; + uint64_t InstrSize = 0; + const uint64_t InstrAddress = getAddress() + Offset; + if (BC.DisAsm->getInstruction(Instr, InstrSize, FunctionData->slice(Offset), + InstrAddress, nulls())) + return Instr; + return std::nullopt; +} + Error BinaryFunction::disassemble() { NamedRegionTimer T("disassemble", "Disassemble function", "buildfuncs", "Build Binary Functions", opts::TimeBuild); diff --git a/bolt/lib/Profile/DataAggregator.cpp b/bolt/lib/Profile/DataAggregator.cpp index 5108392c824c..d02e4499014e 100644 --- a/bolt/lib/Profile/DataAggregator.cpp +++ b/bolt/lib/Profile/DataAggregator.cpp @@ -773,9 +773,19 @@ bool DataAggregator::doInterBranch(BinaryFunction *FromFunc, bool DataAggregator::doBranch(uint64_t From, uint64_t To, uint64_t Count, uint64_t Mispreds) { + bool IsReturn = false; auto handleAddress = [&](uint64_t &Addr, bool IsFrom) -> BinaryFunction * { if (BinaryFunction *Func = getBinaryFunctionContainingAddress(Addr)) { Addr -= Func->getAddress(); + if (IsFrom) { + auto checkReturn = [&](auto MaybeInst) { + IsReturn = MaybeInst && BC->MIB->isReturn(*MaybeInst); + }; + if (Func->hasInstructions()) + checkReturn(Func->getInstructionAtOffset(Addr)); + else + checkReturn(Func->disassembleInstructionAtOffset(Addr)); + } if (BAT) Addr = BAT->translate(Func->getAddress(), Addr, IsFrom); @@ -792,6 +802,9 @@ bool DataAggregator::doBranch(uint64_t From, uint64_t To, uint64_t Count, }; BinaryFunction *FromFunc = handleAddress(From, /*IsFrom=*/true); + // Ignore returns. + if (IsReturn) + return true; BinaryFunction *ToFunc = handleAddress(To, /*IsFrom=*/false); if (!FromFunc && !ToFunc) return false; diff --git a/bolt/test/X86/bolt-address-translation-yaml.test b/bolt/test/X86/bolt-address-translation-yaml.test index af24c3d84a0f..b3d8a8839450 100644 --- a/bolt/test/X86/bolt-address-translation-yaml.test +++ b/bolt/test/X86/bolt-address-translation-yaml.test @@ -13,7 +13,7 @@ RUN: llvm-bolt %t.exe -data %t.fdata -w %t.yaml-fdata -o /dev/null RUN: FileCheck --input-file %t.yaml-fdata --check-prefix YAML-BAT-CHECK %s # Test resulting YAML profile with the original binary (no-stale mode) -RUN: llvm-bolt %t.exe -data %t.yaml -o %t.null -dyno-stats \ +RUN: llvm-bolt %t.exe -data %t.yaml -o %t.null -dyno-stats 2>&1 \ RUN: | FileCheck --check-prefix CHECK-BOLT-YAML %s WRITE-BAT-CHECK: BOLT-INFO: Wrote 5 BAT maps @@ -63,7 +63,8 @@ YAML-BAT-CHECK-NEXT: blocks: YAML-BAT-CHECK: - bid: 1 YAML-BAT-CHECK-NEXT: insns: [[#]] YAML-BAT-CHECK-NEXT: hash: 0xD70DC695320E0010 -YAML-BAT-CHECK-NEXT: succ: {{.*}} { bid: 2, cnt: [[#]] } +YAML-BAT-CHECK-NEXT: succ: {{.*}} { bid: 2, cnt: [[#]] CHECK-BOLT-YAML: pre-processing profile using YAML profile reader CHECK-BOLT-YAML-NEXT: 5 out of 16 functions in the binary (31.2%) have non-empty execution profile +CHECK-BOLT-YAML-NOT: invalid (possibly stale) profile -- GitLab From 2f956a35edb61d250a52c4d883f368d060fae57c Mon Sep 17 00:00:00 2001 From: Artem Belevich Date: Wed, 8 May 2024 12:02:57 -0700 Subject: [PATCH 066/328] [CUDA] Mark CUDA-12.4 as supported and introduce ptx 8.4. (#91516) --- clang/docs/ReleaseNotes.rst | 1 + clang/include/clang/Basic/BuiltinsNVPTX.def | 5 ++++- clang/include/clang/Basic/Cuda.h | 3 ++- clang/lib/Basic/Cuda.cpp | 5 +++-- clang/lib/Driver/ToolChains/Cuda.cpp | 3 +++ llvm/lib/Target/NVPTX/NVPTX.td | 2 +- 6 files changed, 14 insertions(+), 5 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 0f9728c00e64..a3c8e4141ca5 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -798,6 +798,7 @@ CUDA/HIP Language Changes CUDA Support ^^^^^^^^^^^^ +- Clang now supports CUDA SDK up to 12.4 AIX Support ^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/BuiltinsNVPTX.def b/clang/include/clang/Basic/BuiltinsNVPTX.def index 8d3c5e69d55c..9e243d740ed7 100644 --- a/clang/include/clang/Basic/BuiltinsNVPTX.def +++ b/clang/include/clang/Basic/BuiltinsNVPTX.def @@ -61,7 +61,9 @@ #pragma push_macro("PTX81") #pragma push_macro("PTX82") #pragma push_macro("PTX83") -#define PTX83 "ptx83" +#pragma push_macro("PTX84") +#define PTX84 "ptx84" +#define PTX83 "ptx83|" PTX84 #define PTX82 "ptx82|" PTX83 #define PTX81 "ptx81|" PTX82 #define PTX80 "ptx80|" PTX81 @@ -1091,3 +1093,4 @@ TARGET_BUILTIN(__nvvm_getctarank_shared_cluster, "iv*3", "", AND(SM_90,PTX78)) #pragma pop_macro("PTX81") #pragma pop_macro("PTX82") #pragma pop_macro("PTX83") +#pragma pop_macro("PTX84") diff --git a/clang/include/clang/Basic/Cuda.h b/clang/include/clang/Basic/Cuda.h index ba0e4465a0f5..2d67c4181d12 100644 --- a/clang/include/clang/Basic/Cuda.h +++ b/clang/include/clang/Basic/Cuda.h @@ -41,9 +41,10 @@ enum class CudaVersion { CUDA_121, CUDA_122, CUDA_123, + CUDA_124, FULLY_SUPPORTED = CUDA_123, PARTIALLY_SUPPORTED = - CUDA_123, // Partially supported. Proceed with a warning. + CUDA_124, // Partially supported. Proceed with a warning. NEW = 10000, // Too new. Issue a warning, but allow using it. }; const char *CudaVersionToString(CudaVersion V); diff --git a/clang/lib/Basic/Cuda.cpp b/clang/lib/Basic/Cuda.cpp index 113483db5729..e8ce15eb0dec 100644 --- a/clang/lib/Basic/Cuda.cpp +++ b/clang/lib/Basic/Cuda.cpp @@ -14,7 +14,7 @@ struct CudaVersionMapEntry { }; #define CUDA_ENTRY(major, minor) \ { \ -#major "." #minor, CudaVersion::CUDA_##major##minor, \ + #major "." #minor, CudaVersion::CUDA_##major##minor, \ llvm::VersionTuple(major, minor) \ } @@ -41,6 +41,7 @@ static const CudaVersionMapEntry CudaNameVersionMap[] = { CUDA_ENTRY(12, 1), CUDA_ENTRY(12, 2), CUDA_ENTRY(12, 3), + CUDA_ENTRY(12, 4), {"", CudaVersion::NEW, llvm::VersionTuple(std::numeric_limits::max())}, {"unknown", CudaVersion::UNKNOWN, {}} // End of list tombstone. }; @@ -241,7 +242,7 @@ CudaVersion MaxVersionForCudaArch(CudaArch A) { } } -bool CudaFeatureEnabled(llvm::VersionTuple Version, CudaFeature Feature) { +bool CudaFeatureEnabled(llvm::VersionTuple Version, CudaFeature Feature) { return CudaFeatureEnabled(ToCudaVersion(Version), Feature); } diff --git a/clang/lib/Driver/ToolChains/Cuda.cpp b/clang/lib/Driver/ToolChains/Cuda.cpp index 6634e6d818b3..d5f93c9c830f 100644 --- a/clang/lib/Driver/ToolChains/Cuda.cpp +++ b/clang/lib/Driver/ToolChains/Cuda.cpp @@ -82,6 +82,8 @@ CudaVersion getCudaVersion(uint32_t raw_version) { return CudaVersion::CUDA_122; if (raw_version < 12040) return CudaVersion::CUDA_123; + if (raw_version < 12050) + return CudaVersion::CUDA_124; return CudaVersion::NEW; } @@ -688,6 +690,7 @@ void NVPTX::getNVPTXTargetFeatures(const Driver &D, const llvm::Triple &Triple, case CudaVersion::CUDA_##CUDA_VER: \ PtxFeature = "+ptx" #PTX_VER; \ break; + CASE_CUDA_VERSION(124, 84); CASE_CUDA_VERSION(123, 83); CASE_CUDA_VERSION(122, 82); CASE_CUDA_VERSION(121, 81); diff --git a/llvm/lib/Target/NVPTX/NVPTX.td b/llvm/lib/Target/NVPTX/NVPTX.td index 6aa98543e5e2..05457c71cd39 100644 --- a/llvm/lib/Target/NVPTX/NVPTX.td +++ b/llvm/lib/Target/NVPTX/NVPTX.td @@ -41,7 +41,7 @@ foreach sm = [20, 21, 30, 32, 35, 37, 50, 52, 53, def SM90a: FeatureSM<"90a", 901>; foreach version = [32, 40, 41, 42, 43, 50, 60, 61, 62, 63, 64, 65, - 70, 71, 72, 73, 74, 75, 76, 77, 78, 80, 81, 82, 83] in + 70, 71, 72, 73, 74, 75, 76, 77, 78, 80, 81, 82, 83, 84] in def PTX#version: FeaturePTX; //===----------------------------------------------------------------------===// -- GitLab From 7e35a9a0e77aad673a3054855761ee4afd2605c1 Mon Sep 17 00:00:00 2001 From: Max191 <44243577+Max191@users.noreply.github.com> Date: Wed, 8 May 2024 12:05:53 -0700 Subject: [PATCH 067/328] [mlir] Replace dynamic sizes in insert_slice of tensor.cast canonicalization (#91352) In some cases this pattern may ignore static information due to dynamic operands in the insert_slice sizes operands, e.g.: ``` %0 = tensor.cast %arg0 : tensor<1x?xf32> to tensor %1 = tensor.insert_slice %0 into %arg1[...] [%s0, %s1] [...] : tensor into tensor ``` Can be rewritten into: ``` %1 = tensor.insert_slice %arg0 into %arg1[...] [1, %s1] [...] : tensor<1x?xf32> into tensor ``` This PR updates the matching in the pattern to allow rewrites like this. --- mlir/include/mlir/IR/BuiltinTypes.h | 8 +++- mlir/lib/Dialect/Tensor/IR/TensorOps.cpp | 29 +++++++++++++-- mlir/lib/IR/BuiltinTypes.cpp | 24 ++++++------ mlir/test/Dialect/Tensor/canonicalize.mlir | 43 ++++++++++++++-------- 4 files changed, 73 insertions(+), 31 deletions(-) diff --git a/mlir/include/mlir/IR/BuiltinTypes.h b/mlir/include/mlir/IR/BuiltinTypes.h index 2361cf137123..5579b138668d 100644 --- a/mlir/include/mlir/IR/BuiltinTypes.h +++ b/mlir/include/mlir/IR/BuiltinTypes.h @@ -360,9 +360,15 @@ private: /// which dimensions must be kept when e.g. compute MemRef strides under /// rank-reducing operations. Return std::nullopt if reducedShape cannot be /// obtained by dropping only `1` entries in `originalShape`. +/// If `matchDynamic` is true, then dynamic dims in `originalShape` and +/// `reducedShape` will be considered matching with non-dynamic dims, unless +/// the non-dynamic dim is from `originalShape` and equal to 1. For example, +/// in ([1, 3, ?], [?, 5]), the mask would be {1, 0, 0}, since 3 and 5 will +/// match with the corresponding dynamic dims. std::optional> computeRankReductionMask(ArrayRef originalShape, - ArrayRef reducedShape); + ArrayRef reducedShape, + bool matchDynamic = false); /// Enum that captures information related to verifier error conditions on /// slice insert/extract type of ops. diff --git a/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp b/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp index 7a13f7a7d135..1f94397e823f 100644 --- a/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp +++ b/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp @@ -2713,15 +2713,38 @@ struct InsertSliceOpCastFolder final : public OpRewritePattern { auto dstType = llvm::dyn_cast(dst.getType()); if (!srcType || !dstType) return failure(); + + // The tensor.cast source could have additional static information not seen + // in the insert slice op static sizes, so we ignore dynamic dims when + // computing the rank reduction mask. + SmallVector staticSizes(insertSliceOp.getStaticSizes()); + auto rankReductionMask = computeRankReductionMask( + staticSizes, srcType.getShape(), /*matchDynamic=*/true); + if (!rankReductionMask.has_value()) + return failure(); + // Replace dimensions in the insert slice op with corresponding static dims + // from the cast source type. If the insert slice sizes have static dims + // that are not static in the tensor.cast source (i.e., when the cast op + // casts a dynamic dim to static), the dim should not be replaced, and the + // pattern will fail later in `verifyInsertSliceOp`. + SmallVector mixedSizes(insertSliceOp.getMixedSizes()); + int64_t rankReducedIdx = 0; + for (auto [idx, size] : enumerate(staticSizes)) { + if (!rankReductionMask.value().contains(idx) && + !srcType.isDynamicDim(rankReducedIdx)) { + mixedSizes[idx] = getAsIndexOpFoldResult( + rewriter.getContext(), srcType.getDimSize(rankReducedIdx)); + size = srcType.getDimSize(rankReducedIdx++); + } + } if (verifyInsertSliceOp(srcType, dstType, insertSliceOp.getStaticOffsets(), - insertSliceOp.getStaticSizes(), - insertSliceOp.getStaticStrides()) != + staticSizes, insertSliceOp.getStaticStrides()) != SliceVerificationResult::Success) return failure(); Operation *replacement = rewriter.create( insertSliceOp.getLoc(), src, dst, insertSliceOp.getMixedOffsets(), - insertSliceOp.getMixedSizes(), insertSliceOp.getMixedStrides()); + mixedSizes, insertSliceOp.getMixedStrides()); // In the parallel case there is no result and so nothing to cast. bool isParallelInsert = diff --git a/mlir/lib/IR/BuiltinTypes.cpp b/mlir/lib/IR/BuiltinTypes.cpp index a2738946de41..179797cb943a 100644 --- a/mlir/lib/IR/BuiltinTypes.cpp +++ b/mlir/lib/IR/BuiltinTypes.cpp @@ -408,24 +408,24 @@ unsigned BaseMemRefType::getMemorySpaceAsInt() const { // MemRefType //===----------------------------------------------------------------------===// -/// Given an `originalShape` and a `reducedShape` assumed to be a subset of -/// `originalShape` with some `1` entries erased, return the set of indices -/// that specifies which of the entries of `originalShape` are dropped to obtain -/// `reducedShape`. The returned mask can be applied as a projection to -/// `originalShape` to obtain the `reducedShape`. This mask is useful to track -/// which dimensions must be kept when e.g. compute MemRef strides under -/// rank-reducing operations. Return std::nullopt if reducedShape cannot be -/// obtained by dropping only `1` entries in `originalShape`. std::optional> mlir::computeRankReductionMask(ArrayRef originalShape, - ArrayRef reducedShape) { + ArrayRef reducedShape, + bool matchDynamic) { size_t originalRank = originalShape.size(), reducedRank = reducedShape.size(); llvm::SmallDenseSet unusedDims; unsigned reducedIdx = 0; for (unsigned originalIdx = 0; originalIdx < originalRank; ++originalIdx) { // Greedily insert `originalIdx` if match. - if (reducedIdx < reducedRank && - originalShape[originalIdx] == reducedShape[reducedIdx]) { + int64_t origSize = originalShape[originalIdx]; + // if `matchDynamic`, count dynamic dims as a match, unless `origSize` is 1. + if (matchDynamic && reducedIdx < reducedRank && origSize != 1 && + (ShapedType::isDynamic(reducedShape[reducedIdx]) || + ShapedType::isDynamic(origSize))) { + reducedIdx++; + continue; + } + if (reducedIdx < reducedRank && origSize == reducedShape[reducedIdx]) { reducedIdx++; continue; } @@ -433,7 +433,7 @@ mlir::computeRankReductionMask(ArrayRef originalShape, unusedDims.insert(originalIdx); // If no match on `originalIdx`, the `originalShape` at this dimension // must be 1, otherwise we bail. - if (originalShape[originalIdx] != 1) + if (origSize != 1) return std::nullopt; } // The whole reducedShape must be scanned, otherwise we bail. diff --git a/mlir/test/Dialect/Tensor/canonicalize.mlir b/mlir/test/Dialect/Tensor/canonicalize.mlir index 6177fe3c752c..8036d996d232 100644 --- a/mlir/test/Dialect/Tensor/canonicalize.mlir +++ b/mlir/test/Dialect/Tensor/canonicalize.mlir @@ -755,6 +755,34 @@ func.func @fold_dim_of_tensor.cast(%arg0 : tensor<4x?xf32>) -> (index, index) { // ----- +// CHECK-LABEL: func @insert_slice_cast +func.func @insert_slice_cast(%arg0 : tensor<1x?xf32>, %arg1 : tensor, %arg2 : index, %arg3 : index, %arg4 : index, %arg5 : index, %arg6 : index, %arg7 : index) -> tensor { + // CHECK-SAME: %[[ARG0:.*]]: tensor<1x?xf32> + %0 = tensor.cast %arg0 : tensor<1x?xf32> to tensor + // CHECK: %[[RES:.*]] = tensor.insert_slice %[[ARG0]] + // CHECK-SAME: [{{.*}}, {{.*}}] [1, {{.*}}] [{{.*}}, {{.*}}] + // CHECK-SAME: : tensor<1x?xf32> into tensor + %1 = tensor.insert_slice %0 into %arg1[%arg2, %arg3] [%arg4, %arg5] [%arg6, %arg7] : tensor into tensor + // CHECK: return %[[RES]] : tensor + return %1 : tensor +} + +// ----- + +// CHECK-LABEL: func @insert_slice_cast_no_fold +func.func @insert_slice_cast_no_fold(%arg0 : tensor<1x?xf32>, %arg1 : tensor, %arg2 : index, %arg3 : index, %arg4 : index, %arg5 : index, %arg6 : index, %arg7 : index) -> tensor { + %0 = tensor.cast %arg0 : tensor<1x?xf32> to tensor + // CHECK: %[[CAST:.*]] = tensor.cast + // CHECK: %[[RES:.*]] = tensor.insert_slice %[[CAST]] + // CHECK-SAME: [{{.*}}, {{.*}}] [{{.*}}, 5] [{{.*}}, {{.*}}] + // CHECK-SAME: : tensor into tensor + %1 = tensor.insert_slice %0 into %arg1[%arg2, %arg3] [%arg4, 5] [%arg6, %arg7] : tensor into tensor + // CHECK: return %[[RES]] : tensor + return %1 : tensor +} + +// ----- + // CHECK-LABEL: func @insert_tensor_cast_on_insert_slice_src( // CHECK-SAME: %[[arg0:.*]]: tensor, %[[arg1:.*]]: tensor // CHECK: %[[cast:.*]] = tensor.cast %[[arg0]] : tensor to tensor<64x5x64xf32> @@ -1890,21 +1918,6 @@ func.func @splat_dynamic_no_fold(%m: index) -> tensor<4x?xf32> { // ----- -// There was an issue in cast + insert_slice folding generating invalid ir. -// https://github.com/llvm/llvm-project/issues/53099 -// CHECK-LABEL: func @insert_slice_cast -func.func @insert_slice_cast(%arg0 : tensor<1x?xf32>, %arg1 : tensor, %arg2 : index, %arg3 : index, %arg4 : index, %arg5 : index, %arg6 : index, %arg7 : index) -> tensor { - // CHECK: %[[CAST:.*]] = tensor.cast %{{.*}} : tensor<1x?xf32> to tensor - %0 = tensor.cast %arg0 : tensor<1x?xf32> to tensor - // CHECK: %[[RES:.*]] = tensor.insert_slice %[[CAST]] - // CHECK-SAME: : tensor into tensor - %1 = tensor.insert_slice %0 into %arg1[%arg2, %arg3] [%arg4, %arg5] [%arg6, %arg7] : tensor into tensor - // CHECK: return %[[RES]] : tensor - return %1 : tensor -} - -// ----- - // CHECK-LABEL: func @cast_extract_slice func.func @cast_extract_slice(%arg0 : tensor<128x512xf32>, %s : index, %o : index) -> tensor<16x512xf32> { -- GitLab From 878c141adcd3a1ea47c4cc8429af5c8522678536 Mon Sep 17 00:00:00 2001 From: Lily Brown Date: Wed, 8 May 2024 12:07:37 -0700 Subject: [PATCH 068/328] [mlir-lsp] Add DiagnosticTag from LSP spec (#91396) Adds the [DiagnosticTag][diagtag] LSP construct to the LSP support headers. I also added a unit test file to validate that the `tags` array is omitted entirely if it's empty. The LSP spec requires that `Diagnostic::tags` be an array; in order to conform to that I used `std::vector`, as `SmallVector` doesn't have JSON decoding support (you can encode it to JSON, but not decode it from JSON). [diagtag]: https://microsoft.github.io/language-server-protocol/specifications/lsp/3.18/specification/#diagnosticTag --- .../mlir/Tools/lsp-server-support/Protocol.h | 13 +++++ .../lib/Tools/lsp-server-support/Protocol.cpp | 19 ++++++- .../Tools/lsp-server-support/CMakeLists.txt | 1 + .../Tools/lsp-server-support/Protocol.cpp | 51 +++++++++++++++++++ 4 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 mlir/unittests/Tools/lsp-server-support/Protocol.cpp diff --git a/mlir/include/mlir/Tools/lsp-server-support/Protocol.h b/mlir/include/mlir/Tools/lsp-server-support/Protocol.h index 839d82bb02b8..1d22b8a66774 100644 --- a/mlir/include/mlir/Tools/lsp-server-support/Protocol.h +++ b/mlir/include/mlir/Tools/lsp-server-support/Protocol.h @@ -677,6 +677,16 @@ enum class DiagnosticSeverity { Hint = 4 }; +enum class DiagnosticTag { + Unnecessary = 1, + Deprecated = 2, +}; + +/// Add support for JSON serialization. +llvm::json::Value toJSON(DiagnosticTag tag); +bool fromJSON(const llvm::json::Value &value, DiagnosticTag &result, + llvm::json::Path path); + struct Diagnostic { /// The source range where the message applies. Range range; @@ -696,6 +706,9 @@ struct Diagnostic { /// a scope collide all definitions can be marked via this property. std::optional> relatedInformation; + /// Additional metadata about the diagnostic. + std::vector tags; + /// The diagnostic's category. Can be omitted. /// An LSP extension that's used to send the name of the category over to the /// client. The category typically describes the compilation stage during diff --git a/mlir/lib/Tools/lsp-server-support/Protocol.cpp b/mlir/lib/Tools/lsp-server-support/Protocol.cpp index e110fdd97a38..188f5253c95c 100644 --- a/mlir/lib/Tools/lsp-server-support/Protocol.cpp +++ b/mlir/lib/Tools/lsp-server-support/Protocol.cpp @@ -646,6 +646,20 @@ llvm::json::Value mlir::lsp::toJSON(const DiagnosticRelatedInformation &info) { // Diagnostic //===----------------------------------------------------------------------===// +llvm::json::Value mlir::lsp::toJSON(DiagnosticTag tag) { + return static_cast(tag); +} + +bool mlir::lsp::fromJSON(const llvm::json::Value &value, DiagnosticTag &result, + llvm::json::Path path) { + if (std::optional i = value.getAsInteger()) { + result = (DiagnosticTag)*i; + return true; + } + + return false; +} + llvm::json::Value mlir::lsp::toJSON(const Diagnostic &diag) { llvm::json::Object result{ {"range", diag.range}, @@ -658,6 +672,8 @@ llvm::json::Value mlir::lsp::toJSON(const Diagnostic &diag) { result["source"] = diag.source; if (diag.relatedInformation) result["relatedInformation"] = *diag.relatedInformation; + if (!diag.tags.empty()) + result["tags"] = diag.tags; return std::move(result); } @@ -675,7 +691,8 @@ bool mlir::lsp::fromJSON(const llvm::json::Value &value, Diagnostic &result, mapOptOrNull(value, "category", result.category, path) && mapOptOrNull(value, "source", result.source, path) && mapOptOrNull(value, "relatedInformation", result.relatedInformation, - path); + path) && + mapOptOrNull(value, "tags", result.tags, path); } //===----------------------------------------------------------------------===// diff --git a/mlir/unittests/Tools/lsp-server-support/CMakeLists.txt b/mlir/unittests/Tools/lsp-server-support/CMakeLists.txt index 3aa8b9c4bc77..f777873ff7c6 100644 --- a/mlir/unittests/Tools/lsp-server-support/CMakeLists.txt +++ b/mlir/unittests/Tools/lsp-server-support/CMakeLists.txt @@ -1,4 +1,5 @@ add_mlir_unittest(MLIRLspServerSupportTests + Protocol.cpp Transport.cpp ) target_link_libraries(MLIRLspServerSupportTests diff --git a/mlir/unittests/Tools/lsp-server-support/Protocol.cpp b/mlir/unittests/Tools/lsp-server-support/Protocol.cpp new file mode 100644 index 000000000000..04d7b2fbb440 --- /dev/null +++ b/mlir/unittests/Tools/lsp-server-support/Protocol.cpp @@ -0,0 +1,51 @@ +//===- Protocol.cpp - LSP JSON protocol unit tests ------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "mlir/Tools/lsp-server-support/Protocol.h" + +#include "gtest/gtest.h" + +using namespace mlir; +using namespace mlir::lsp; +using namespace testing; + +namespace { + +TEST(ProtocolTest, DiagnosticTagPresent) { + Diagnostic diagnostic; + diagnostic.tags.push_back(DiagnosticTag::Unnecessary); + + llvm::json::Value json = toJSON(diagnostic); + const llvm::json::Object *o = json.getAsObject(); + const llvm::json::Array *v = o->get("tags")->getAsArray(); + EXPECT_EQ(*v, llvm::json::Array{1}); + + Diagnostic parsed; + llvm::json::Path::Root root = llvm::json::Path::Root(); + bool success = fromJSON(json, parsed, llvm::json::Path(root)); + EXPECT_TRUE(success); + ASSERT_EQ(parsed.tags.size(), (size_t)1); + EXPECT_EQ(parsed.tags.at(0), DiagnosticTag::Unnecessary); +} + +TEST(ProtocolTest, DiagnosticTagNotPresent) { + Diagnostic diagnostic; + + llvm::json::Value json = toJSON(diagnostic); + const llvm::json::Object *o = json.getAsObject(); + const llvm::json::Value *v = o->get("tags"); + EXPECT_EQ(v, nullptr); + + Diagnostic parsed; + llvm::json::Path::Root root = llvm::json::Path::Root(); + bool success = fromJSON(json, parsed, llvm::json::Path(root)); + EXPECT_TRUE(success); + EXPECT_TRUE(parsed.tags.empty()); +} + +} // namespace -- GitLab From 1464aee3767bf516633ce595ccd89a9cb50ae763 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Wed, 8 May 2024 20:16:44 +0100 Subject: [PATCH 069/328] [LAA] Add tests with non-constant backward deps with known min value. Add a set of tests with non-constant backward dependences, where the minimum value is known (via the start value of the outer AddRec). --- .../non-constant-distance-backward.ll | 258 ++++++++++++++++++ 1 file changed, 258 insertions(+) create mode 100644 llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll diff --git a/llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll b/llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll new file mode 100644 index 000000000000..5a95dcca1050 --- /dev/null +++ b/llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll @@ -0,0 +1,258 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes='print' -disable-output %s 2>&1 | FileCheck %s +; RUN: opt -passes='print' -disable-output -mtriple=arm64-apple-macosx %s 2>&1 | FileCheck %s +; RUN: opt -passes='print' -disable-output -mtriple=arm64-apple-macosx -mattr=+sve %s 2>&1 | FileCheck %s + +; REQUIRES: aarch64-registered-target + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +define void @backward_min_distance_8(ptr %A, i64 %N) { +; CHECK-LABEL: 'backward_min_distance_8' +; CHECK-NEXT: loop: +; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Check 0: +; CHECK-NEXT: Comparing group ([[GRP1:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv +; CHECK-NEXT: Against group ([[GRP2:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; CHECK-NEXT: Grouped accesses: +; CHECK-NEXT: Group [[GRP1]]: +; CHECK-NEXT: (Low: {(1 + %A),+,1}<%outer.header> High: {(257 + %A),+,1}<%outer.header>) +; CHECK-NEXT: Member: {{\{\{}}(1 + %A),+,1}<%outer.header>,+,1}<%loop> +; CHECK-NEXT: Group [[GRP2]]: +; CHECK-NEXT: (Low: %A High: (256 + %A)) +; CHECK-NEXT: Member: {%A,+,1}<%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; CHECK-NEXT: outer.header: +; CHECK-NEXT: Report: loop is not the innermost loop +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + br label %outer.header + +outer.header: + %outer.iv = phi i64 [ 1, %entry ], [ %outer.iv.next, %outer.latch ] + %gep.off = getelementptr inbounds i8, ptr %A, i64 %outer.iv + br label %loop + +loop: + %iv = phi i64 [ 0, %outer.header ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i8, ptr %A, i64 %iv + %l = load i8 , ptr %gep, align 4 + %add = add nsw i8 %l, 5 + %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv + store i8 %add, ptr %gep.off.iv, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %outer.latch, label %loop + +outer.latch: + %outer.iv.next = add nuw nsw i64 %outer.iv, 1 + %ec.2 = icmp eq i64 %outer.iv.next, %N + br i1 %ec.2, label %exit, label %outer.header + +exit: + ret void +} + +define void @backward_min_distance_120(ptr %A, i64 %N) { +; CHECK-LABEL: 'backward_min_distance_120' +; CHECK-NEXT: loop: +; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Check 0: +; CHECK-NEXT: Comparing group ([[GRP3:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv +; CHECK-NEXT: Against group ([[GRP4:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; CHECK-NEXT: Grouped accesses: +; CHECK-NEXT: Group [[GRP3]]: +; CHECK-NEXT: (Low: {(15 + %A),+,1}<%outer.header> High: {(271 + %A),+,1}<%outer.header>) +; CHECK-NEXT: Member: {{\{\{}}(15 + %A),+,1}<%outer.header>,+,1}<%loop> +; CHECK-NEXT: Group [[GRP4]]: +; CHECK-NEXT: (Low: %A High: (256 + %A)) +; CHECK-NEXT: Member: {%A,+,1}<%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; CHECK-NEXT: outer.header: +; CHECK-NEXT: Report: loop is not the innermost loop +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + br label %outer.header + +outer.header: + %outer.iv = phi i64 [ 15, %entry ], [ %outer.iv.next, %outer.latch ] + %gep.off = getelementptr inbounds i8, ptr %A, i64 %outer.iv + br label %loop + +loop: + %iv = phi i64 [ 0, %outer.header ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i8, ptr %A, i64 %iv + %l = load i8 , ptr %gep, align 4 + %add = add nsw i8 %l, 5 + %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv + store i8 %add, ptr %gep.off.iv, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %outer.latch, label %loop + +outer.latch: + %outer.iv.next = add nuw nsw i64 %outer.iv, 1 + %ec.2 = icmp eq i64 %outer.iv.next, %N + br i1 %ec.2, label %exit, label %outer.header + +exit: + ret void +} + + +declare void @llvm.assume(i1) +define void @backward_min_distance_128(ptr %A, i64 %N) { +; CHECK-LABEL: 'backward_min_distance_128' +; CHECK-NEXT: loop: +; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Check 0: +; CHECK-NEXT: Comparing group ([[GRP5:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv +; CHECK-NEXT: Against group ([[GRP6:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; CHECK-NEXT: Grouped accesses: +; CHECK-NEXT: Group [[GRP5]]: +; CHECK-NEXT: (Low: {(16 + %A),+,1}<%outer.header> High: {(272 + %A),+,1}<%outer.header>) +; CHECK-NEXT: Member: {{\{\{}}(16 + %A),+,1}<%outer.header>,+,1}<%loop> +; CHECK-NEXT: Group [[GRP6]]: +; CHECK-NEXT: (Low: %A High: (256 + %A)) +; CHECK-NEXT: Member: {%A,+,1}<%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; CHECK-NEXT: outer.header: +; CHECK-NEXT: Report: loop is not the innermost loop +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + br label %outer.header + +outer.header: + %outer.iv = phi i64 [ 16, %entry ], [ %outer.iv.next, %outer.latch ] + %gep.off = getelementptr inbounds i8, ptr %A, i64 %outer.iv + br label %loop + +loop: + %iv = phi i64 [ 0, %outer.header ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i8, ptr %A, i64 %iv + %l = load i8 , ptr %gep, align 4 + %add = add nsw i8 %l, 5 + %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv + store i8 %add, ptr %gep.off.iv, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %outer.latch, label %loop + +outer.latch: + %outer.iv.next = add nuw nsw i64 %outer.iv, 1 + %ec.2 = icmp eq i64 %outer.iv.next, %N + br i1 %ec.2, label %exit, label %outer.header + +exit: + ret void +} + +define void @backward_min_distance_256(ptr %A, i64 %N) { +; CHECK-LABEL: 'backward_min_distance_256' +; CHECK-NEXT: loop: +; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Check 0: +; CHECK-NEXT: Comparing group ([[GRP7:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv +; CHECK-NEXT: Against group ([[GRP8:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; CHECK-NEXT: Grouped accesses: +; CHECK-NEXT: Group [[GRP7]]: +; CHECK-NEXT: (Low: {(32 + %A),+,1}<%outer.header> High: {(288 + %A),+,1}<%outer.header>) +; CHECK-NEXT: Member: {{\{\{}}(32 + %A),+,1}<%outer.header>,+,1}<%loop> +; CHECK-NEXT: Group [[GRP8]]: +; CHECK-NEXT: (Low: %A High: (256 + %A)) +; CHECK-NEXT: Member: {%A,+,1}<%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; CHECK-NEXT: outer.header: +; CHECK-NEXT: Report: loop is not the innermost loop +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + br label %outer.header + +outer.header: + %outer.iv = phi i64 [ 32, %entry ], [ %outer.iv.next, %outer.latch ] + %gep.off = getelementptr inbounds i8, ptr %A, i64 %outer.iv + br label %loop + +loop: + %iv = phi i64 [ 0, %outer.header ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i8, ptr %A, i64 %iv + %l = load i8 , ptr %gep, align 4 + %add = add nsw i8 %l, 5 + %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv + store i8 %add, ptr %gep.off.iv, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %outer.latch, label %loop + +outer.latch: + %outer.iv.next = add nuw nsw i64 %outer.iv, 1 + %ec.2 = icmp eq i64 %outer.iv.next, %N + br i1 %ec.2, label %exit, label %outer.header + +exit: + ret void +} -- GitLab From 63c38ba64ebe079439e29acf43f24c33ecf44f4c Mon Sep 17 00:00:00 2001 From: Mariusz Borsa Date: Wed, 8 May 2024 12:23:25 -0700 Subject: [PATCH 070/328] [Sanitizers] Fix fake_test_gc not working on devices (#91284) The way the LIT RUN command is currently constructed ( %run not --crash %t ) causes the test failure on devices - since 'not' is a LLVM built command, not available on devices. Changing the command to read 'not --crash %run %t' fixes it, as 'not' now executes on the host running the test. rdar://115914588 Co-authored-by: Mariusz Borsa --- compiler-rt/test/asan/TestCases/Posix/fake_stack_gc.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler-rt/test/asan/TestCases/Posix/fake_stack_gc.cpp b/compiler-rt/test/asan/TestCases/Posix/fake_stack_gc.cpp index 524ca29f2fc5..8c368b9b1b94 100644 --- a/compiler-rt/test/asan/TestCases/Posix/fake_stack_gc.cpp +++ b/compiler-rt/test/asan/TestCases/Posix/fake_stack_gc.cpp @@ -1,4 +1,4 @@ -// RUN: %clangxx_asan -O0 -pthread %s -o %t && %env_asan_opts=use_sigaltstack=0 %run not --crash %t 2>&1 | FileCheck %s +// RUN: %clangxx_asan -O0 -pthread %s -o %t && %env_asan_opts=use_sigaltstack=0 not --crash %run %t 2>&1 | FileCheck %s // Check that fake stack does not discard frames on the main stack, when GC is // triggered from high alt stack. -- GitLab From 9047331f1b4a623332966d888f05bcd3381c8abe Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 8 May 2024 20:34:37 +0100 Subject: [PATCH 071/328] [AArch64] Add some additional add mul imm tests with multiple uses. NFC --- llvm/test/CodeGen/AArch64/addimm-mulimm.ll | 299 +++++++++++++++++++-- 1 file changed, 279 insertions(+), 20 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/addimm-mulimm.ll b/llvm/test/CodeGen/AArch64/addimm-mulimm.ll index cc6523d1bb1d..3618b14aa921 100644 --- a/llvm/test/CodeGen/AArch64/addimm-mulimm.ll +++ b/llvm/test/CodeGen/AArch64/addimm-mulimm.ll @@ -4,8 +4,8 @@ define i64 @addimm_mulimm_accept_00(i64 %a) { ; CHECK-LABEL: addimm_mulimm_accept_00: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #37 -; CHECK-NEXT: mov x9, #1147 +; CHECK-NEXT: mov w8, #37 // =0x25 +; CHECK-NEXT: mov x9, #1147 // =0x47b ; CHECK-NEXT: madd x0, x0, x8, x9 ; CHECK-NEXT: ret %tmp0 = add i64 %a, 31 @@ -16,8 +16,8 @@ define i64 @addimm_mulimm_accept_00(i64 %a) { define i64 @addimm_mulimm_accept_01(i64 %a) { ; CHECK-LABEL: addimm_mulimm_accept_01: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #37 -; CHECK-NEXT: mov x9, #-1147 +; CHECK-NEXT: mov w8, #37 // =0x25 +; CHECK-NEXT: mov x9, #-1147 // =0xfffffffffffffb85 ; CHECK-NEXT: madd x0, x0, x8, x9 ; CHECK-NEXT: ret %tmp0 = add i64 %a, -31 @@ -28,8 +28,8 @@ define i64 @addimm_mulimm_accept_01(i64 %a) { define signext i32 @addimm_mulimm_accept_02(i32 signext %a) { ; CHECK-LABEL: addimm_mulimm_accept_02: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #37 -; CHECK-NEXT: mov w9, #1147 +; CHECK-NEXT: mov w8, #37 // =0x25 +; CHECK-NEXT: mov w9, #1147 // =0x47b ; CHECK-NEXT: madd w0, w0, w8, w9 ; CHECK-NEXT: ret %tmp0 = add i32 %a, 31 @@ -40,8 +40,8 @@ define signext i32 @addimm_mulimm_accept_02(i32 signext %a) { define signext i32 @addimm_mulimm_accept_03(i32 signext %a) { ; CHECK-LABEL: addimm_mulimm_accept_03: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #37 -; CHECK-NEXT: mov w9, #-1147 +; CHECK-NEXT: mov w8, #37 // =0x25 +; CHECK-NEXT: mov w9, #-1147 // =0xfffffb85 ; CHECK-NEXT: madd w0, w0, w8, w9 ; CHECK-NEXT: ret %tmp0 = add i32 %a, -31 @@ -52,8 +52,8 @@ define signext i32 @addimm_mulimm_accept_03(i32 signext %a) { define i64 @addimm_mulimm_accept_10(i64 %a) { ; CHECK-LABEL: addimm_mulimm_accept_10: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #37 -; CHECK-NEXT: mov w9, #32888 +; CHECK-NEXT: mov w8, #37 // =0x25 +; CHECK-NEXT: mov w9, #32888 // =0x8078 ; CHECK-NEXT: movk w9, #17, lsl #16 ; CHECK-NEXT: madd x0, x0, x8, x9 ; CHECK-NEXT: ret @@ -65,8 +65,8 @@ define i64 @addimm_mulimm_accept_10(i64 %a) { define i64 @addimm_mulimm_accept_11(i64 %a) { ; CHECK-LABEL: addimm_mulimm_accept_11: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #37 -; CHECK-NEXT: mov x9, #-32888 +; CHECK-NEXT: mov w8, #37 // =0x25 +; CHECK-NEXT: mov x9, #-32888 // =0xffffffffffff7f88 ; CHECK-NEXT: movk x9, #65518, lsl #16 ; CHECK-NEXT: madd x0, x0, x8, x9 ; CHECK-NEXT: ret @@ -78,8 +78,8 @@ define i64 @addimm_mulimm_accept_11(i64 %a) { define signext i32 @addimm_mulimm_accept_12(i32 signext %a) { ; CHECK-LABEL: addimm_mulimm_accept_12: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #37 -; CHECK-NEXT: mov w9, #32888 +; CHECK-NEXT: mov w8, #37 // =0x25 +; CHECK-NEXT: mov w9, #32888 // =0x8078 ; CHECK-NEXT: movk w9, #17, lsl #16 ; CHECK-NEXT: madd w0, w0, w8, w9 ; CHECK-NEXT: ret @@ -91,8 +91,8 @@ define signext i32 @addimm_mulimm_accept_12(i32 signext %a) { define signext i32 @addimm_mulimm_accept_13(i32 signext %a) { ; CHECK-LABEL: addimm_mulimm_accept_13: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #37 -; CHECK-NEXT: mov w9, #32648 +; CHECK-NEXT: mov w8, #37 // =0x25 +; CHECK-NEXT: mov w9, #32648 // =0x7f88 ; CHECK-NEXT: movk w9, #65518, lsl #16 ; CHECK-NEXT: madd w0, w0, w8, w9 ; CHECK-NEXT: ret @@ -104,7 +104,7 @@ define signext i32 @addimm_mulimm_accept_13(i32 signext %a) { define i64 @addimm_mulimm_reject_00(i64 %a) { ; CHECK-LABEL: addimm_mulimm_reject_00: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #3700 +; CHECK-NEXT: mov w8, #3700 // =0xe74 ; CHECK-NEXT: add x9, x0, #3100 ; CHECK-NEXT: mul x0, x9, x8 ; CHECK-NEXT: ret @@ -116,7 +116,7 @@ define i64 @addimm_mulimm_reject_00(i64 %a) { define i64 @addimm_mulimm_reject_01(i64 %a) { ; CHECK-LABEL: addimm_mulimm_reject_01: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #3700 +; CHECK-NEXT: mov w8, #3700 // =0xe74 ; CHECK-NEXT: sub x9, x0, #3100 ; CHECK-NEXT: mul x0, x9, x8 ; CHECK-NEXT: ret @@ -128,7 +128,7 @@ define i64 @addimm_mulimm_reject_01(i64 %a) { define signext i32 @addimm_mulimm_reject_02(i32 signext %a) { ; CHECK-LABEL: addimm_mulimm_reject_02: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #3700 +; CHECK-NEXT: mov w8, #3700 // =0xe74 ; CHECK-NEXT: add w9, w0, #3100 ; CHECK-NEXT: mul w0, w9, w8 ; CHECK-NEXT: ret @@ -140,7 +140,7 @@ define signext i32 @addimm_mulimm_reject_02(i32 signext %a) { define signext i32 @addimm_mulimm_reject_03(i32 signext %a) { ; CHECK-LABEL: addimm_mulimm_reject_03: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #3700 +; CHECK-NEXT: mov w8, #3700 // =0xe74 ; CHECK-NEXT: sub w9, w0, #3100 ; CHECK-NEXT: mul w0, w9, w8 ; CHECK-NEXT: ret @@ -148,3 +148,262 @@ define signext i32 @addimm_mulimm_reject_03(i32 signext %a) { %tmp1 = mul i32 %tmp0, 3700 ret i32 %tmp1 } + +define signext i32 @addmuladd(i32 signext %a) { +; CHECK-LABEL: addmuladd: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: mov w9, #1300 // =0x514 +; CHECK-NEXT: madd w0, w0, w8, w9 +; CHECK-NEXT: ret + %tmp0 = add i32 %a, 4 + %tmp1 = mul i32 %tmp0, 324 + %tmp2 = add i32 %tmp1, 4 + ret i32 %tmp2 +} + +define signext i32 @addmuladd_multiuse(i32 signext %a) { +; CHECK-LABEL: addmuladd_multiuse: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: add w9, w0, #4 +; CHECK-NEXT: mov w10, #4 // =0x4 +; CHECK-NEXT: madd w8, w9, w8, w10 +; CHECK-NEXT: eor w0, w9, w8 +; CHECK-NEXT: ret + %tmp0 = add i32 %a, 4 + %tmp1 = mul i32 %tmp0, 324 + %tmp2 = add i32 %tmp1, 4 + %tmp3 = xor i32 %tmp0, %tmp2 + ret i32 %tmp3 +} + +define signext i32 @addmuladd_multiusemul(i32 signext %a) { +; CHECK-LABEL: addmuladd_multiusemul: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: mul w8, w0, w8 +; CHECK-NEXT: add w9, w8, #1296 +; CHECK-NEXT: add w8, w8, #1300 +; CHECK-NEXT: eor w0, w9, w8 +; CHECK-NEXT: ret + %tmp0 = add i32 %a, 4 + %tmp1 = mul i32 %tmp0, 324 + %tmp2 = add i32 %tmp1, 4 + %tmp3 = xor i32 %tmp1, %tmp2 + ret i32 %tmp3 +} + +define signext i32 @addmuladd_multiuse2(i32 signext %a) { +; CHECK-LABEL: addmuladd_multiuse2: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: add w9, w0, #4 +; CHECK-NEXT: mov w11, #4 // =0x4 +; CHECK-NEXT: lsl w10, w9, #2 +; CHECK-NEXT: madd w8, w9, w8, w11 +; CHECK-NEXT: add w9, w10, #4 +; CHECK-NEXT: eor w0, w8, w9 +; CHECK-NEXT: ret + %tmp0 = add i32 %a, 4 + %tmp1 = mul i32 %tmp0, 4 + %tmp2 = add i32 %tmp1, 4 + %tmp3 = mul i32 %tmp0, 324 + %tmp4 = add i32 %tmp3, 4 + %tmp5 = xor i32 %tmp4, %tmp2 + ret i32 %tmp5 +} + +define signext i32 @addaddmuladd(i32 signext %a, i32 %b) { +; CHECK-LABEL: addaddmuladd: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: madd w8, w0, w8, w1 +; CHECK-NEXT: add w0, w8, #1300 +; CHECK-NEXT: ret + %tmp0 = add i32 %a, 4 + %tmp1 = mul i32 %tmp0, 324 + %tmp2 = add i32 %tmp1, %b + %tmp3 = add i32 %tmp2, 4 + ret i32 %tmp3 +} + +define signext i32 @addaddmuladd_multiuse(i32 signext %a, i32 %b) { +; CHECK-LABEL: addaddmuladd_multiuse: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: add w9, w0, #4 +; CHECK-NEXT: madd w8, w9, w8, w1 +; CHECK-NEXT: add w8, w8, #4 +; CHECK-NEXT: eor w0, w9, w8 +; CHECK-NEXT: ret + %tmp0 = add i32 %a, 4 + %tmp1 = mul i32 %tmp0, 324 + %tmp2 = add i32 %tmp1, %b + %tmp3 = add i32 %tmp2, 4 + %tmp4 = xor i32 %tmp0, %tmp3 + ret i32 %tmp4 +} + +define signext i32 @addaddmuladd_multiuse2(i32 signext %a, i32 %b) { +; CHECK-LABEL: addaddmuladd_multiuse2: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: add w9, w0, #4 +; CHECK-NEXT: mov w10, #162 // =0xa2 +; CHECK-NEXT: madd w8, w9, w8, w1 +; CHECK-NEXT: madd w9, w9, w10, w1 +; CHECK-NEXT: add w8, w8, #4 +; CHECK-NEXT: add w9, w9, #4 +; CHECK-NEXT: eor w0, w9, w8 +; CHECK-NEXT: ret + %tmp0 = add i32 %a, 4 + %tmp1 = mul i32 %tmp0, 324 + %tmp2 = add i32 %tmp1, %b + %tmp3 = add i32 %tmp2, 4 + %tmp1b = mul i32 %tmp0, 162 + %tmp2b = add i32 %tmp1b, %b + %tmp3b = add i32 %tmp2b, 4 + %tmp4 = xor i32 %tmp3b, %tmp3 + ret i32 %tmp4 +} + +define <4 x i32> @addmuladd_vec(<4 x i32> %a) { +; CHECK-LABEL: addmuladd_vec: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: mov w9, #1300 // =0x514 +; CHECK-NEXT: dup v2.4s, w8 +; CHECK-NEXT: dup v1.4s, w9 +; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret + %tmp0 = add <4 x i32> %a, + %tmp1 = mul <4 x i32> %tmp0, + %tmp2 = add <4 x i32> %tmp1, + ret <4 x i32> %tmp2 +} + +define <4 x i32> @addmuladd_vec_multiuse(<4 x i32> %a) { +; CHECK-LABEL: addmuladd_vec_multiuse: +; CHECK: // %bb.0: +; CHECK-NEXT: movi v1.4s, #4 +; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: dup v2.4s, w8 +; CHECK-NEXT: add v0.4s, v0.4s, v1.4s +; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret + %tmp0 = add <4 x i32> %a, + %tmp1 = mul <4 x i32> %tmp0, + %tmp2 = add <4 x i32> %tmp1, + %tmp3 = xor <4 x i32> %tmp0, %tmp2 + ret <4 x i32> %tmp3 +} + +define void @addmuladd_gep(ptr %p, i64 %a) { +; CHECK-LABEL: addmuladd_gep: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #40 // =0x28 +; CHECK-NEXT: str wzr, [x0, #10]! +; CHECK-NEXT: madd x8, x1, x8, x0 +; CHECK-NEXT: str wzr, [x8, #20] +; CHECK-NEXT: ret + %q = getelementptr i8, ptr %p, i64 10 + %r = getelementptr [10 x [10 x i32]], ptr %q, i64 0, i64 %a, i64 5 + store i32 0, ptr %q + store i32 0, ptr %r + ret void +} + +define i32 @addmuladd_gep2(ptr %p, i32 %a) { +; CHECK-LABEL: addmuladd_gep2: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-NEXT: sxtw x8, w1 +; CHECK-NEXT: mov w9, #3240 // =0xca8 +; CHECK-NEXT: add x8, x8, #1 +; CHECK-NEXT: madd x9, x8, x9, x0 +; CHECK-NEXT: ldr w9, [x9, #20] +; CHECK-NEXT: tbnz w9, #31, .LBB22_2 +; CHECK-NEXT: // %bb.1: +; CHECK-NEXT: mov w0, wzr +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB22_2: // %then +; CHECK-NEXT: str x8, [x0] +; CHECK-NEXT: mov w0, #1 // =0x1 +; CHECK-NEXT: ret + %b = sext i32 %a to i64 + %c = add nsw i64 %b, 1 + %d = mul nsw i64 %c, 81 + %g = getelementptr [10 x [10 x i32]], ptr %p, i64 0, i64 %d, i64 5 + %l = load i32, ptr %g, align 4 + %cc = icmp slt i32 %l, 0 + br i1 %cc, label %then, label %else +then: + store i64 %c, ptr %p + ret i32 1 +else: + ret i32 0 +} + +define signext i32 @addmuladd_multiuse2_nsw(i32 signext %a) { +; CHECK-LABEL: addmuladd_multiuse2_nsw: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: add w9, w0, #4 +; CHECK-NEXT: mov w11, #4 // =0x4 +; CHECK-NEXT: lsl w10, w9, #2 +; CHECK-NEXT: madd w8, w9, w8, w11 +; CHECK-NEXT: add w9, w10, #4 +; CHECK-NEXT: eor w0, w8, w9 +; CHECK-NEXT: ret + %tmp0 = add nsw i32 %a, 4 + %tmp1 = mul nsw i32 %tmp0, 4 + %tmp2 = add nsw i32 %tmp1, 4 + %tmp3 = mul nsw i32 %tmp0, 324 + %tmp4 = add nsw i32 %tmp3, 4 + %tmp5 = xor i32 %tmp4, %tmp2 + ret i32 %tmp5 +} + +define signext i32 @addmuladd_multiuse2_nuw(i32 signext %a) { +; CHECK-LABEL: addmuladd_multiuse2_nuw: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: add w9, w0, #4 +; CHECK-NEXT: mov w11, #4 // =0x4 +; CHECK-NEXT: lsl w10, w9, #2 +; CHECK-NEXT: madd w8, w9, w8, w11 +; CHECK-NEXT: add w9, w10, #4 +; CHECK-NEXT: eor w0, w8, w9 +; CHECK-NEXT: ret + %tmp0 = add nuw i32 %a, 4 + %tmp1 = mul nuw i32 %tmp0, 4 + %tmp2 = add nuw i32 %tmp1, 4 + %tmp3 = mul nuw i32 %tmp0, 324 + %tmp4 = add nuw i32 %tmp3, 4 + %tmp5 = xor i32 %tmp4, %tmp2 + ret i32 %tmp5 +} + +define signext i32 @addmuladd_multiuse2_nswnuw(i32 signext %a) { +; CHECK-LABEL: addmuladd_multiuse2_nswnuw: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: add w9, w0, #4 +; CHECK-NEXT: mov w11, #4 // =0x4 +; CHECK-NEXT: lsl w10, w9, #2 +; CHECK-NEXT: madd w8, w9, w8, w11 +; CHECK-NEXT: add w9, w10, #4 +; CHECK-NEXT: eor w0, w8, w9 +; CHECK-NEXT: ret + %tmp0 = add nsw nuw i32 %a, 4 + %tmp1 = mul nsw nuw i32 %tmp0, 4 + %tmp2 = add nsw nuw i32 %tmp1, 4 + %tmp3 = mul nsw nuw i32 %tmp0, 324 + %tmp4 = add nsw nuw i32 %tmp3, 4 + %tmp5 = xor i32 %tmp4, %tmp2 + ret i32 %tmp5 +} + -- GitLab From 5526c8a7425350cff2cd9cafa1bf5f20753e7848 Mon Sep 17 00:00:00 2001 From: Thomas Raoux Date: Wed, 8 May 2024 12:35:15 -0700 Subject: [PATCH 072/328] [MLIR] Model llvm.inline_asm side_effects (#91507) Allow more cleanups on inline_asm ops modeling side effects based on the side_effect attributed. --- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 2 +- mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 13 +++++++++++++ mlir/test/Dialect/LLVMIR/canonicalize.mlir | 11 +++++++++++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td index 6655ce6f123e..4b91708ea1aa 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td @@ -1795,7 +1795,7 @@ def LLVM_FenceOp : LLVM_Op<"fence">, LLVM_MemOpPatterns { let hasVerifier = 1; } -def LLVM_InlineAsmOp : LLVM_Op<"inline_asm", []> { +def LLVM_InlineAsmOp : LLVM_Op<"inline_asm", [DeclareOpInterfaceMethods]> { let description = [{ The InlineAsmOp mirrors the underlying LLVM semantics with a notable exception: the embedded `asm_string` is not allowed to define or reference diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp index 7be493d5992c..7d33d05feb65 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp @@ -3034,6 +3034,19 @@ LogicalResult LinkerOptionsOp::verify() { return success(); } +//===----------------------------------------------------------------------===// +// InlineAsmOp +//===----------------------------------------------------------------------===// + +void InlineAsmOp::getEffects( + SmallVectorImpl> + &effects) { + if (getHasSideEffects()) { + effects.emplace_back(MemoryEffects::Write::get()); + effects.emplace_back(MemoryEffects::Read::get()); + } +} + //===----------------------------------------------------------------------===// // LLVMDialect initialization, type parsing, and registration. //===----------------------------------------------------------------------===// diff --git a/mlir/test/Dialect/LLVMIR/canonicalize.mlir b/mlir/test/Dialect/LLVMIR/canonicalize.mlir index 6b265bbbdbfb..15f960167cb5 100644 --- a/mlir/test/Dialect/LLVMIR/canonicalize.mlir +++ b/mlir/test/Dialect/LLVMIR/canonicalize.mlir @@ -248,3 +248,14 @@ llvm.func @volatile_load(%x : !llvm.ptr) { %3 = llvm.load %x atomic unordered { alignment = 1 } : !llvm.ptr -> i8 llvm.return } + +// ----- + +// CHECK-LABEL: func @inline_asm_side_effects +llvm.func @inline_asm_side_effects(%x : i32) { + // CHECK-NOT: llvm.inline_asm "pure inline asm" + llvm.inline_asm "pure inline asm", "r" %x : (i32) -> () + // CHECK: llvm.inline_asm has_side_effects "inline asm with side effects" + llvm.inline_asm has_side_effects "inline asm with side effects", "r" %x : (i32) -> () + llvm.return +} -- GitLab From e3938f4d71493673033f6190454e7e19d5411ea7 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Wed, 8 May 2024 14:36:58 -0500 Subject: [PATCH 073/328] [Offload] Detect native ELF machine from preprocessor (#91282) Summary: This gets the target's corresponding ELF value from the preprocessor. We use this to detect if a given ELF is compatible with the CPU offloading impolementation for OpenMP. Previously we used defitions from CMake, but this is easier for people to understand as there may be new users of this in the future. --- .../plugins-nextgen/common/include/Utils/ELF.h | 3 +++ offload/plugins-nextgen/common/src/Utils/ELF.cpp | 15 +++++++++++++++ offload/plugins-nextgen/host/CMakeLists.txt | 5 ----- offload/plugins-nextgen/host/src/rtl.cpp | 10 ++++------ 4 files changed, 22 insertions(+), 11 deletions(-) diff --git a/offload/plugins-nextgen/common/include/Utils/ELF.h b/offload/plugins-nextgen/common/include/Utils/ELF.h index 88c83d39b68c..f87e0a5ed02b 100644 --- a/offload/plugins-nextgen/common/include/Utils/ELF.h +++ b/offload/plugins-nextgen/common/include/Utils/ELF.h @@ -24,6 +24,9 @@ namespace elf { /// Returns true or false if the \p Buffer is an ELF file. bool isELF(llvm::StringRef Buffer); +/// Returns the ELF e_machine value of the current compilation target. +uint16_t getTargetMachine(); + /// Checks if the given \p Object is a valid ELF matching the e_machine value. llvm::Expected checkMachine(llvm::StringRef Object, uint16_t EMachine); diff --git a/offload/plugins-nextgen/common/src/Utils/ELF.cpp b/offload/plugins-nextgen/common/src/Utils/ELF.cpp index 2ae97f0f2589..90d6950b83e5 100644 --- a/offload/plugins-nextgen/common/src/Utils/ELF.cpp +++ b/offload/plugins-nextgen/common/src/Utils/ELF.cpp @@ -36,6 +36,21 @@ bool utils::elf::isELF(StringRef Buffer) { } } +uint16_t utils::elf::getTargetMachine() { +#if defined(__x86_64__) + return EM_X86_64; +#elif defined(__s390x__) + return EM_S390; +#elif defined(__aarch64__) + return EM_AARCH64; +#elif defined(__powerpc64__) + return EM_PPC64; +#else +#warning "Unknown ELF compilation target architecture" + return EM_NONE; +#endif +} + template static Expected checkMachineImpl(const object::ELFObjectFile &ELFObj, uint16_t EMachine) { diff --git a/offload/plugins-nextgen/host/CMakeLists.txt b/offload/plugins-nextgen/host/CMakeLists.txt index 48e591bc894e..1d000442c84d 100644 --- a/offload/plugins-nextgen/host/CMakeLists.txt +++ b/offload/plugins-nextgen/host/CMakeLists.txt @@ -52,27 +52,22 @@ endif() # Define the target specific triples and ELF machine values. if(CMAKE_SYSTEM_PROCESSOR MATCHES "ppc64le$") - target_compile_definitions(omptarget.rtl.host PRIVATE TARGET_ELF_ID=EM_PPC64) list(APPEND LIBOMPTARGET_SYSTEM_TARGETS "powerpc64le-ibm-linux-gnu" "powerpc64le-ibm-linux-gnu-LTO") set(LIBOMPTARGET_SYSTEM_TARGETS "${LIBOMPTARGET_SYSTEM_TARGETS}" PARENT_SCOPE) elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "ppc64$") - target_compile_definitions(omptarget.rtl.host PRIVATE TARGET_ELF_ID=EM_PPC64) list(APPEND LIBOMPTARGET_SYSTEM_TARGETS "powerpc64-ibm-linux-gnu" "powerpc64-ibm-linux-gnu-LTO") set(LIBOMPTARGET_SYSTEM_TARGETS "${LIBOMPTARGET_SYSTEM_TARGETS}" PARENT_SCOPE) elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64$") - target_compile_definitions(omptarget.rtl.host PRIVATE TARGET_ELF_ID=EM_X86_64) list(APPEND LIBOMPTARGET_SYSTEM_TARGETS "x86_64-pc-linux-gnu" "x86_64-pc-linux-gnu-LTO") set(LIBOMPTARGET_SYSTEM_TARGETS "${LIBOMPTARGET_SYSTEM_TARGETS}" PARENT_SCOPE) elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64$") - target_compile_definitions(omptarget.rtl.host PRIVATE TARGET_ELF_ID=EM_AARCH64) list(APPEND LIBOMPTARGET_SYSTEM_TARGETS "aarch64-unknown-linux-gnu" "aarch64-unknown-linux-gnu-LTO") set(LIBOMPTARGET_SYSTEM_TARGETS "${LIBOMPTARGET_SYSTEM_TARGETS}" PARENT_SCOPE) elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "s390x$") - target_compile_definitions(omptarget.rtl.host PRIVATE TARGET_ELF_ID=EM_S390) list(APPEND LIBOMPTARGET_SYSTEM_TARGETS "s390x-ibm-linux-gnu" "s390x-ibm-linux-gnu-LTO") set(LIBOMPTARGET_SYSTEM_TARGETS "${LIBOMPTARGET_SYSTEM_TARGETS}" PARENT_SCOPE) diff --git a/offload/plugins-nextgen/host/src/rtl.cpp b/offload/plugins-nextgen/host/src/rtl.cpp index c929db6c22d8..4bdcae3dd6a1 100644 --- a/offload/plugins-nextgen/host/src/rtl.cpp +++ b/offload/plugins-nextgen/host/src/rtl.cpp @@ -18,6 +18,7 @@ #include "Shared/Debug.h" #include "Shared/Environment.h" +#include "Utils/ELF.h" #include "GlobalHandler.h" #include "OpenMP/OMPT/Callback.h" @@ -44,11 +45,6 @@ // The number of devices in this plugin. #define NUM_DEVICES 4 -// The ELF ID should be defined at compile-time by the build system. -#ifndef TARGET_ELF_ID -#define TARGET_ELF_ID EM_NONE -#endif - namespace llvm { namespace omp { namespace target { @@ -416,7 +412,9 @@ struct GenELF64PluginTy final : public GenericPluginTy { } /// Get the ELF code to recognize the compatible binary images. - uint16_t getMagicElfBits() const override { return ELF::TARGET_ELF_ID; } + uint16_t getMagicElfBits() const override { + return utils::elf::getTargetMachine(); + } /// This plugin does not support exchanging data between two devices. bool isDataExchangable(int32_t SrcDeviceId, int32_t DstDeviceId) override { -- GitLab From 559accf365a6eb885c24cf15e14aea2eb8e66596 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 8 May 2024 12:53:31 -0700 Subject: [PATCH 074/328] [AMDGPU] Add VOP3_PACKED to V_PK_{MIN|MAX}IMUM_F16 profile (#91512) NFCI as far as I understand, added for consitency. --- llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index a7d63fdb2e04..71ce36647e45 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -110,8 +110,8 @@ defm V_PK_MAX_I16 : VOP3PInst<"v_pk_max_i16", VOP3P_Profile, umax>; let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in { -defm V_PK_MAXIMUM_F16 : VOP3PInst<"v_pk_maximum_f16", VOP3P_Profile, fmaximum>; -defm V_PK_MINIMUM_F16 : VOP3PInst<"v_pk_minimum_f16", VOP3P_Profile, fminimum>; +defm V_PK_MAXIMUM_F16 : VOP3PInst<"v_pk_maximum_f16", VOP3P_Profile, fmaximum>; +defm V_PK_MINIMUM_F16 : VOP3PInst<"v_pk_minimum_f16", VOP3P_Profile, fminimum>; } // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 } -- GitLab From b1da82ae3dba0982b3a9668ca895ddf4164fb3d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20Warzy=C5=84ski?= Date: Wed, 8 May 2024 21:06:03 +0100 Subject: [PATCH 075/328] [mlir][arith] Fix overflow bug in arith::CeilDivSIOp::fold (#90947) The folder for arith::CeilDivSIOp should only be applied when it can be guaranteed that no overflow would happen. The current implementation works fine when both dividends are positive and the only arithmetic operation is the division itself. However, in cases where either the dividend or divisor is negative (or both), the division is split into multiple arith operations, e.g.: `- ( -a / b)`. That's additional 2 operations on top of the actual division that can overflow - the folder should check all 3 ops for overflow. The current logic doesn't do that - it effectively only checks the last operation (i.e. the division). It breaks when using e.g. MININT values (e.g. -128 for 8-bit integers) - negating such values overflows. This PR makes sure that no folding happens if any of the intermediate arithmetic operations overflows. Fixes https://github.com/llvm/llvm-project/issues/89382 --- mlir/lib/Dialect/Arith/IR/ArithOps.cpp | 34 ++++++++++++++++------ mlir/test/Transforms/constant-fold.mlir | 38 +++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 9 deletions(-) diff --git a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp index 6f995b93bc3e..a1568d0ebba3 100644 --- a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp +++ b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp @@ -683,6 +683,8 @@ OpFoldResult arith::CeilDivSIOp::fold(FoldAdaptor adaptor) { return getLhs(); // Don't fold if it would overflow or if it requires a division by zero. + // TODO: This hook won't fold operations where a = MININT, because + // negating MININT overflows. This can be improved. bool overflowOrDiv0 = false; auto result = constFoldBinaryOp( adaptor.getOperands(), [&](APInt a, const APInt &b) { @@ -701,22 +703,36 @@ OpFoldResult arith::CeilDivSIOp::fold(FoldAdaptor adaptor) { // Both positive, return ceil(a, b). return signedCeilNonnegInputs(a, b, overflowOrDiv0); } + + // No folding happens if any of the intermediate arithmetic operations + // overflows. + bool overflowNegA = false; + bool overflowNegB = false; + bool overflowDiv = false; + bool overflowNegRes = false; if (!aGtZero && !bGtZero) { // Both negative, return ceil(-a, -b). - APInt posA = zero.ssub_ov(a, overflowOrDiv0); - APInt posB = zero.ssub_ov(b, overflowOrDiv0); - return signedCeilNonnegInputs(posA, posB, overflowOrDiv0); + APInt posA = zero.ssub_ov(a, overflowNegA); + APInt posB = zero.ssub_ov(b, overflowNegB); + APInt res = signedCeilNonnegInputs(posA, posB, overflowDiv); + overflowOrDiv0 = (overflowNegA || overflowNegB || overflowDiv); + return res; } if (!aGtZero && bGtZero) { // A is negative, b is positive, return - ( -a / b). - APInt posA = zero.ssub_ov(a, overflowOrDiv0); - APInt div = posA.sdiv_ov(b, overflowOrDiv0); - return zero.ssub_ov(div, overflowOrDiv0); + APInt posA = zero.ssub_ov(a, overflowNegA); + APInt div = posA.sdiv_ov(b, overflowDiv); + APInt res = zero.ssub_ov(div, overflowNegRes); + overflowOrDiv0 = (overflowNegA || overflowDiv || overflowNegRes); + return res; } // A is positive, b is negative, return - (a / -b). - APInt posB = zero.ssub_ov(b, overflowOrDiv0); - APInt div = a.sdiv_ov(posB, overflowOrDiv0); - return zero.ssub_ov(div, overflowOrDiv0); + APInt posB = zero.ssub_ov(b, overflowNegB); + APInt div = a.sdiv_ov(posB, overflowDiv); + APInt res = zero.ssub_ov(div, overflowNegRes); + + overflowOrDiv0 = (overflowNegB || overflowDiv || overflowNegRes); + return res; }); return overflowOrDiv0 ? Attribute() : result; diff --git a/mlir/test/Transforms/constant-fold.mlir b/mlir/test/Transforms/constant-fold.mlir index 253163f2af91..981757aed9b1 100644 --- a/mlir/test/Transforms/constant-fold.mlir +++ b/mlir/test/Transforms/constant-fold.mlir @@ -478,6 +478,44 @@ func.func @simple_arith.ceildivsi() -> (i32, i32, i32, i32, i32) { // ----- +// CHECK-LABEL: func @simple_arith.ceildivsi_overflow +func.func @simple_arith.ceildivsi_overflow() -> (i8, i16, i32) { + // The negative values below are MININTs for the corresponding bit-width. The + // folder will try to negate them (so that the division operates on two + // positive numbers), but that would cause overflow (negating MININT + // overflows). Hence folding should not happen and the original ceildivsi is + // preserved. + + // TODO: The folder should be able to fold the following by avoiding + // intermediate operations that overflow. + + // CHECK-DAG: %[[C_1:.*]] = arith.constant 7 : i8 + // CHECK-DAG: %[[MIN_I8:.*]] = arith.constant -128 : i8 + // CHECK-DAG: %[[C_2:.*]] = arith.constant 7 : i16 + // CHECK-DAG: %[[MIN_I16:.*]] = arith.constant -32768 : i16 + // CHECK-DAG: %[[C_3:.*]] = arith.constant 7 : i32 + // CHECK-DAG: %[[MIN_I32:.*]] = arith.constant -2147483648 : i32 + + // CHECK-NEXT: %[[CEILDIV_1:.*]] = arith.ceildivsi %[[MIN_I8]], %[[C_1]] : i8 + %0 = arith.constant 7 : i8 + %min_int_i8 = arith.constant -128 : i8 + %2 = arith.ceildivsi %min_int_i8, %0 : i8 + + // CHECK-NEXT: %[[CEILDIV_2:.*]] = arith.ceildivsi %[[MIN_I16]], %[[C_2]] : i16 + %3 = arith.constant 7 : i16 + %min_int_i16 = arith.constant -32768 : i16 + %5 = arith.ceildivsi %min_int_i16, %3 : i16 + + // CHECK-NEXT: %[[CEILDIV_2:.*]] = arith.ceildivsi %[[MIN_I32]], %[[C_3]] : i32 + %6 = arith.constant 7 : i32 + %min_int_i32 = arith.constant -2147483648 : i32 + %8 = arith.ceildivsi %min_int_i32, %6 : i32 + + return %2, %5, %8 : i8, i16, i32 +} + +// ----- + // CHECK-LABEL: func @simple_arith.ceildivui func.func @simple_arith.ceildivui() -> (i32, i32, i32, i32, i32) { // CHECK-DAG: [[C0:%.+]] = arith.constant 0 -- GitLab From b52160dbae268cc87cb8f6cdf75553ca095e26a9 Mon Sep 17 00:00:00 2001 From: Dave Lee Date: Wed, 8 May 2024 13:07:07 -0700 Subject: [PATCH 076/328] [lldb] Consult Language plugin in GetDisplayDemangledName (#90294) Give language plugins the opportunity to provide a language specific display name. This will be used in a follow up commit. The purpose of this change is to ultimately display breakpoint locations with a more human friendly demangling of Swift symbols. --- lldb/include/lldb/Target/Language.h | 4 ++++ lldb/source/Core/Mangled.cpp | 2 ++ 2 files changed, 6 insertions(+) diff --git a/lldb/include/lldb/Target/Language.h b/lldb/include/lldb/Target/Language.h index 67714e6fdf94..ff7c60bf68bf 100644 --- a/lldb/include/lldb/Target/Language.h +++ b/lldb/include/lldb/Target/Language.h @@ -281,6 +281,10 @@ public: return mangled.GetMangledName(); } + virtual ConstString GetDisplayDemangledName(Mangled mangled) const { + return mangled.GetDemangledName(); + } + virtual void GetExceptionResolverDescription(bool catch_on, bool throw_on, Stream &s); diff --git a/lldb/source/Core/Mangled.cpp b/lldb/source/Core/Mangled.cpp index b167c51fdce2..8efc4c639cca 100644 --- a/lldb/source/Core/Mangled.cpp +++ b/lldb/source/Core/Mangled.cpp @@ -310,6 +310,8 @@ ConstString Mangled::GetDemangledName() const { } ConstString Mangled::GetDisplayDemangledName() const { + if (Language *lang = Language::FindPlugin(GuessLanguage())) + return lang->GetDisplayDemangledName(*this); return GetDemangledName(); } -- GitLab From cec6665f2b7583223eb20519dfc3289011d1d2d7 Mon Sep 17 00:00:00 2001 From: Teresa Johnson Date: Wed, 8 May 2024 13:41:29 -0700 Subject: [PATCH 077/328] [MemProf] Optionally update hints on existing hot/cold new calls (#91047) If directed by an option, update hints on calls to new that already provide a hot/cold hint. --- .../lib/Transforms/Utils/SimplifyLibCalls.cpp | 137 +++++++++++--- .../InstCombine/simplify-libcalls-new.ll | 176 +++++++++++++++++- 2 files changed, 288 insertions(+), 25 deletions(-) diff --git a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp index 2e68a9c01898..174cc7a3c778 100644 --- a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp @@ -52,6 +52,10 @@ static cl::opt static cl::opt OptimizeHotColdNew("optimize-hot-cold-new", cl::Hidden, cl::init(false), cl::desc("Enable hot/cold operator new library calls")); +static cl::opt OptimizeExistingHotColdNew( + "optimize-existing-hot-cold-new", cl::Hidden, cl::init(false), + cl::desc( + "Enable optimization of existing hot/cold operator new library calls")); namespace { @@ -81,6 +85,10 @@ struct HotColdHintParser : public cl::parser { static cl::opt ColdNewHintValue( "cold-new-hint-value", cl::Hidden, cl::init(1), cl::desc("Value to pass to hot/cold operator new for cold allocation")); +static cl::opt + NotColdNewHintValue("notcold-new-hint-value", cl::Hidden, cl::init(128), + cl::desc("Value to pass to hot/cold operator new for " + "notcold (warm) allocation")); static cl::opt HotNewHintValue( "hot-new-hint-value", cl::Hidden, cl::init(254), cl::desc("Value to pass to hot/cold operator new for hot allocation")); @@ -1722,45 +1730,122 @@ Value *LibCallSimplifier::optimizeNew(CallInst *CI, IRBuilderBase &B, uint8_t HotCold; if (CI->getAttributes().getFnAttr("memprof").getValueAsString() == "cold") HotCold = ColdNewHintValue; + else if (CI->getAttributes().getFnAttr("memprof").getValueAsString() == + "notcold") + HotCold = NotColdNewHintValue; else if (CI->getAttributes().getFnAttr("memprof").getValueAsString() == "hot") HotCold = HotNewHintValue; else return nullptr; + // For calls that already pass a hot/cold hint, only update the hint if + // directed by OptimizeExistingHotColdNew. For other calls to new, add a hint + // if cold or hot, and leave as-is for default handling if "notcold" aka warm. + // Note that in cases where we decide it is "notcold", it might be slightly + // better to replace the hinted call with a non hinted call, to avoid the + // extra paramter and the if condition check of the hint value in the + // allocator. This can be considered in the future. switch (Func) { + case LibFunc_Znwm12__hot_cold_t: + if (OptimizeExistingHotColdNew) + return emitHotColdNew(CI->getArgOperand(0), B, TLI, + LibFunc_Znwm12__hot_cold_t, HotCold); + break; case LibFunc_Znwm: - return emitHotColdNew(CI->getArgOperand(0), B, TLI, - LibFunc_Znwm12__hot_cold_t, HotCold); + if (HotCold != NotColdNewHintValue) + return emitHotColdNew(CI->getArgOperand(0), B, TLI, + LibFunc_Znwm12__hot_cold_t, HotCold); + break; + case LibFunc_Znam12__hot_cold_t: + if (OptimizeExistingHotColdNew) + return emitHotColdNew(CI->getArgOperand(0), B, TLI, + LibFunc_Znam12__hot_cold_t, HotCold); + break; case LibFunc_Znam: - return emitHotColdNew(CI->getArgOperand(0), B, TLI, - LibFunc_Znam12__hot_cold_t, HotCold); + if (HotCold != NotColdNewHintValue) + return emitHotColdNew(CI->getArgOperand(0), B, TLI, + LibFunc_Znam12__hot_cold_t, HotCold); + break; + case LibFunc_ZnwmRKSt9nothrow_t12__hot_cold_t: + if (OptimizeExistingHotColdNew) + return emitHotColdNewNoThrow( + CI->getArgOperand(0), CI->getArgOperand(1), B, TLI, + LibFunc_ZnwmRKSt9nothrow_t12__hot_cold_t, HotCold); + break; case LibFunc_ZnwmRKSt9nothrow_t: - return emitHotColdNewNoThrow(CI->getArgOperand(0), CI->getArgOperand(1), B, - TLI, LibFunc_ZnwmRKSt9nothrow_t12__hot_cold_t, - HotCold); + if (HotCold != NotColdNewHintValue) + return emitHotColdNewNoThrow( + CI->getArgOperand(0), CI->getArgOperand(1), B, TLI, + LibFunc_ZnwmRKSt9nothrow_t12__hot_cold_t, HotCold); + break; + case LibFunc_ZnamRKSt9nothrow_t12__hot_cold_t: + if (OptimizeExistingHotColdNew) + return emitHotColdNewNoThrow( + CI->getArgOperand(0), CI->getArgOperand(1), B, TLI, + LibFunc_ZnamRKSt9nothrow_t12__hot_cold_t, HotCold); + break; case LibFunc_ZnamRKSt9nothrow_t: - return emitHotColdNewNoThrow(CI->getArgOperand(0), CI->getArgOperand(1), B, - TLI, LibFunc_ZnamRKSt9nothrow_t12__hot_cold_t, - HotCold); + if (HotCold != NotColdNewHintValue) + return emitHotColdNewNoThrow( + CI->getArgOperand(0), CI->getArgOperand(1), B, TLI, + LibFunc_ZnamRKSt9nothrow_t12__hot_cold_t, HotCold); + break; + case LibFunc_ZnwmSt11align_val_t12__hot_cold_t: + if (OptimizeExistingHotColdNew) + return emitHotColdNewAligned( + CI->getArgOperand(0), CI->getArgOperand(1), B, TLI, + LibFunc_ZnwmSt11align_val_t12__hot_cold_t, HotCold); + break; case LibFunc_ZnwmSt11align_val_t: - return emitHotColdNewAligned(CI->getArgOperand(0), CI->getArgOperand(1), B, - TLI, LibFunc_ZnwmSt11align_val_t12__hot_cold_t, - HotCold); + if (HotCold != NotColdNewHintValue) + return emitHotColdNewAligned( + CI->getArgOperand(0), CI->getArgOperand(1), B, TLI, + LibFunc_ZnwmSt11align_val_t12__hot_cold_t, HotCold); + break; + case LibFunc_ZnamSt11align_val_t12__hot_cold_t: + if (OptimizeExistingHotColdNew) + return emitHotColdNewAligned( + CI->getArgOperand(0), CI->getArgOperand(1), B, TLI, + LibFunc_ZnamSt11align_val_t12__hot_cold_t, HotCold); + break; case LibFunc_ZnamSt11align_val_t: - return emitHotColdNewAligned(CI->getArgOperand(0), CI->getArgOperand(1), B, - TLI, LibFunc_ZnamSt11align_val_t12__hot_cold_t, - HotCold); + if (HotCold != NotColdNewHintValue) + return emitHotColdNewAligned( + CI->getArgOperand(0), CI->getArgOperand(1), B, TLI, + LibFunc_ZnamSt11align_val_t12__hot_cold_t, HotCold); + break; + case LibFunc_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t: + if (OptimizeExistingHotColdNew) + return emitHotColdNewAlignedNoThrow( + CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), B, + TLI, LibFunc_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t, + HotCold); + break; case LibFunc_ZnwmSt11align_val_tRKSt9nothrow_t: - return emitHotColdNewAlignedNoThrow( - CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), B, - TLI, LibFunc_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t, HotCold); + if (HotCold != NotColdNewHintValue) + return emitHotColdNewAlignedNoThrow( + CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), B, + TLI, LibFunc_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t, + HotCold); + break; + case LibFunc_ZnamSt11align_val_tRKSt9nothrow_t12__hot_cold_t: + if (OptimizeExistingHotColdNew) + return emitHotColdNewAlignedNoThrow( + CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), B, + TLI, LibFunc_ZnamSt11align_val_tRKSt9nothrow_t12__hot_cold_t, + HotCold); + break; case LibFunc_ZnamSt11align_val_tRKSt9nothrow_t: - return emitHotColdNewAlignedNoThrow( - CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), B, - TLI, LibFunc_ZnamSt11align_val_tRKSt9nothrow_t12__hot_cold_t, HotCold); + if (HotCold != NotColdNewHintValue) + return emitHotColdNewAlignedNoThrow( + CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), B, + TLI, LibFunc_ZnamSt11align_val_tRKSt9nothrow_t12__hot_cold_t, + HotCold); + break; default: return nullptr; } + return nullptr; } //===----------------------------------------------------------------------===// @@ -3675,6 +3760,14 @@ Value *LibCallSimplifier::optimizeStringMemoryLibCall(CallInst *CI, case LibFunc_ZnamRKSt9nothrow_t: case LibFunc_ZnamSt11align_val_t: case LibFunc_ZnamSt11align_val_tRKSt9nothrow_t: + case LibFunc_Znwm12__hot_cold_t: + case LibFunc_ZnwmRKSt9nothrow_t12__hot_cold_t: + case LibFunc_ZnwmSt11align_val_t12__hot_cold_t: + case LibFunc_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t: + case LibFunc_Znam12__hot_cold_t: + case LibFunc_ZnamRKSt9nothrow_t12__hot_cold_t: + case LibFunc_ZnamSt11align_val_t12__hot_cold_t: + case LibFunc_ZnamSt11align_val_tRKSt9nothrow_t12__hot_cold_t: return optimizeNew(CI, Builder, Func); default: break; diff --git a/llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll b/llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll index 51debdf6643e..ecfafbc69797 100644 --- a/llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll +++ b/llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll @@ -1,13 +1,19 @@ ;; Test behavior of -optimize-hot-cold-new and related options. ;; Check that we don't get hot/cold new calls without enabling it explicitly. -; RUN: opt < %s -passes=instcombine -S | FileCheck %s --implicit-check-not=hot_cold_t +; RUN: opt < %s -passes=instcombine -S | FileCheck %s --check-prefix=OFF +; OFF-NOT: hot_cold_t +; OFF-LABEL: @new_hot_cold() ;; First check with the default cold and hot hint values (255 = -2). -; RUN: opt < %s -passes=instcombine -optimize-hot-cold-new -S | FileCheck %s --check-prefix=HOTCOLD -DCOLD=1 -DHOT=-2 +; RUN: opt < %s -passes=instcombine -optimize-hot-cold-new -S | FileCheck %s --check-prefix=HOTCOLD -DCOLD=1 -DHOT=-2 -DPREVHINTCOLD=7 -DPREVHINTNOTCOLD=7 -DPREVHINTHOT=7 ;; Next check with the non-default cold and hot hint values (200 =-56). -; RUN: opt < %s -passes=instcombine -optimize-hot-cold-new -cold-new-hint-value=5 -hot-new-hint-value=200 -S | FileCheck %s --check-prefix=HOTCOLD -DCOLD=5 -DHOT=-56 +; RUN: opt < %s -passes=instcombine -optimize-hot-cold-new -cold-new-hint-value=5 -hot-new-hint-value=200 -S | FileCheck %s --check-prefix=HOTCOLD -DCOLD=5 -DHOT=-56 -DPREVHINTCOLD=7 -DPREVHINTNOTCOLD=7 -DPREVHINTHOT=7 + +;; Try again with the non-default cold and hot hint values (200 =-56), and this +;; time specify that existing hints should be updated. +; RUN: opt < %s -passes=instcombine -optimize-hot-cold-new -cold-new-hint-value=5 -notcold-new-hint-value=100 -hot-new-hint-value=200 -optimize-existing-hot-cold-new -S | FileCheck %s --check-prefix=HOTCOLD -DCOLD=5 -DHOT=-56 -DPREVHINTCOLD=5 -DPREVHINTNOTCOLD=100 -DPREVHINTHOT=-56 ;; Make sure that values not in 0..255 are flagged with an error ; RUN: not opt < %s -passes=instcombine -optimize-hot-cold-new -cold-new-hint-value=256 -S 2>&1 | FileCheck %s --check-prefix=ERROR @@ -178,6 +184,162 @@ define void @array_new_align_nothrow() { ret void } +;; Check that operator new(unsigned long, __hot_cold_t) +;; optionally has its hint updated. +; HOTCOLD-LABEL: @new_hot_cold() +define void @new_hot_cold() { + ;; Attribute cold converted to __hot_cold_t cold value. + ; HOTCOLD: @_Znwm12__hot_cold_t(i64 10, i8 [[PREVHINTCOLD]]) + %call = call ptr @_Znwm12__hot_cold_t(i64 10, i8 7) #0 + call void @dummy(ptr %call) + ;; Attribute notcold converted to __hot_cold_t notcold value. + ; HOTCOLD: @_Znwm12__hot_cold_t(i64 10, i8 [[PREVHINTNOTCOLD]]) + %call1 = call ptr @_Znwm12__hot_cold_t(i64 10, i8 7) #1 + call void @dummy(ptr %call1) + ;; Attribute hot converted to __hot_cold_t hot value. + ; HOTCOLD: @_Znwm12__hot_cold_t(i64 10, i8 [[PREVHINTHOT]]) + %call2 = call ptr @_Znwm12__hot_cold_t(i64 10, i8 7) #2 + call void @dummy(ptr %call2) + ret void +} + +;; Check that operator new(unsigned long, std::align_val_t, __hot_cold_t) +;; optionally has its hint updated. +; HOTCOLD-LABEL: @new_align_hot_cold() +define void @new_align_hot_cold() { + ;; Attribute cold converted to __hot_cold_t cold value. + ; HOTCOLD: @_ZnwmSt11align_val_t12__hot_cold_t(i64 10, i64 8, i8 [[PREVHINTCOLD]]) + %call = call ptr @_ZnwmSt11align_val_t12__hot_cold_t(i64 10, i64 8, i8 7) #0 + call void @dummy(ptr %call) + ;; Attribute notcold converted to __hot_cold_t notcold value. + ; HOTCOLD: @_ZnwmSt11align_val_t12__hot_cold_t(i64 10, i64 8, i8 [[PREVHINTNOTCOLD]]) + %call1 = call ptr @_ZnwmSt11align_val_t12__hot_cold_t(i64 10, i64 8, i8 7) #1 + call void @dummy(ptr %call1) + ;; Attribute hot converted to __hot_cold_t hot value. + ; HOTCOLD: @_ZnwmSt11align_val_t12__hot_cold_t(i64 10, i64 8, i8 [[PREVHINTHOT]]) + %call2 = call ptr @_ZnwmSt11align_val_t12__hot_cold_t(i64 10, i64 8, i8 7) #2 + call void @dummy(ptr %call2) + ret void +} + +;; Check that operator new(unsigned long, const std::nothrow_t&, __hot_cold_t) +;; optionally has its hint updated. +; HOTCOLD-LABEL: @new_nothrow_hot_cold() +define void @new_nothrow_hot_cold() { + %nt = alloca i8 + ;; Attribute cold converted to __hot_cold_t cold value. + ; HOTCOLD: @_ZnwmRKSt9nothrow_t12__hot_cold_t(i64 10, ptr nonnull %nt, i8 [[PREVHINTCOLD]]) + %call = call ptr @_ZnwmRKSt9nothrow_t12__hot_cold_t(i64 10, ptr %nt, i8 7) #0 + call void @dummy(ptr %call) + ;; Attribute notcold converted to __hot_cold_t notcold value. + ; HOTCOLD: @_ZnwmRKSt9nothrow_t12__hot_cold_t(i64 10, ptr nonnull %nt, i8 [[PREVHINTNOTCOLD]]) + %call1 = call ptr @_ZnwmRKSt9nothrow_t12__hot_cold_t(i64 10, ptr %nt, i8 7) #1 + call void @dummy(ptr %call1) + ;; Attribute hot converted to __hot_cold_t hot value. + ; HOTCOLD: @_ZnwmRKSt9nothrow_t12__hot_cold_t(i64 10, ptr nonnull %nt, i8 [[PREVHINTHOT]]) + %call2 = call ptr @_ZnwmRKSt9nothrow_t12__hot_cold_t(i64 10, ptr %nt, i8 7) #2 + call void @dummy(ptr %call2) + ret void +} + +;; Check that operator new(unsigned long, std::align_val_t, const std::nothrow_t&, __hot_cold_t) +;; optionally has its hint updated. +; HOTCOLD-LABEL: @new_align_nothrow_hot_cold() +define void @new_align_nothrow_hot_cold() { + %nt = alloca i8 + ;; Attribute cold converted to __hot_cold_t cold value. + ; HOTCOLD: @_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 10, i64 8, ptr nonnull %nt, i8 [[PREVHINTCOLD]]) + %call = call ptr @_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 10, i64 8, ptr %nt, i8 7) #0 + call void @dummy(ptr %call) + ;; Attribute notcold converted to __hot_cold_t notcold value. + ; HOTCOLD: @_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 10, i64 8, ptr nonnull %nt, i8 [[PREVHINTNOTCOLD]]) + %call1 = call ptr @_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 10, i64 8, ptr %nt, i8 7) #1 + call void @dummy(ptr %call1) + ;; Attribute hot converted to __hot_cold_t hot value. + ; HOTCOLD: @_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 10, i64 8, ptr nonnull %nt, i8 [[PREVHINTHOT]]) + %call2 = call ptr @_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 10, i64 8, ptr %nt, i8 7) #2 + call void @dummy(ptr %call2) + ret void +} + +;; Check that operator new[](unsigned long, __hot_cold_t) +;; optionally has its hint updated. +; HOTCOLD-LABEL: @array_new_hot_cold() +define void @array_new_hot_cold() { + ;; Attribute cold converted to __hot_cold_t cold value. + ; HOTCOLD: @_Znam12__hot_cold_t(i64 10, i8 [[PREVHINTCOLD]]) + %call = call ptr @_Znam12__hot_cold_t(i64 10, i8 7) #0 + call void @dummy(ptr %call) + ;; Attribute notcold converted to __hot_cold_t notcold value. + ; HOTCOLD: @_Znam12__hot_cold_t(i64 10, i8 [[PREVHINTNOTCOLD]]) + %call1 = call ptr @_Znam12__hot_cold_t(i64 10, i8 7) #1 + call void @dummy(ptr %call1) + ;; Attribute hot converted to __hot_cold_t hot value. + ; HOTCOLD: @_Znam12__hot_cold_t(i64 10, i8 [[PREVHINTHOT]]) + %call2 = call ptr @_Znam12__hot_cold_t(i64 10, i8 7) #2 + call void @dummy(ptr %call2) + ret void +} + +;; Check that operator new[](unsigned long, std::align_val_t, __hot_cold_t) +;; optionally has its hint updated. +; HOTCOLD-LABEL: @array_new_align_hot_cold() +define void @array_new_align_hot_cold() { + ;; Attribute cold converted to __hot_cold_t cold value. + ; HOTCOLD: @_ZnamSt11align_val_t12__hot_cold_t(i64 10, i64 8, i8 [[PREVHINTCOLD]]) + %call = call ptr @_ZnamSt11align_val_t12__hot_cold_t(i64 10, i64 8, i8 7) #0 + call void @dummy(ptr %call) + ;; Attribute notcold converted to __hot_cold_t notcold value. + ; HOTCOLD: @_ZnamSt11align_val_t12__hot_cold_t(i64 10, i64 8, i8 [[PREVHINTNOTCOLD]]) + %call1 = call ptr @_ZnamSt11align_val_t12__hot_cold_t(i64 10, i64 8, i8 7) #1 + call void @dummy(ptr %call1) + ;; Attribute hot converted to __hot_cold_t hot value. + ; HOTCOLD: @_ZnamSt11align_val_t12__hot_cold_t(i64 10, i64 8, i8 [[PREVHINTHOT]]) + %call2 = call ptr @_ZnamSt11align_val_t12__hot_cold_t(i64 10, i64 8, i8 7) #2 + call void @dummy(ptr %call2) + ret void +} + +;; Check that operator new[](unsigned long, const std::nothrow_t&, __hot_cold_t) +;; optionally has its hint updated. +; HOTCOLD-LABEL: @array_new_nothrow_hot_cold() +define void @array_new_nothrow_hot_cold() { + %nt = alloca i8 + ;; Attribute cold converted to __hot_cold_t cold value. + ; HOTCOLD: @_ZnamRKSt9nothrow_t12__hot_cold_t(i64 10, ptr nonnull %nt, i8 [[PREVHINTCOLD]]) + %call = call ptr @_ZnamRKSt9nothrow_t12__hot_cold_t(i64 10, ptr %nt, i8 7) #0 + call void @dummy(ptr %call) + ;; Attribute notcold converted to __hot_cold_t notcold value. + ; HOTCOLD: @_ZnamRKSt9nothrow_t12__hot_cold_t(i64 10, ptr nonnull %nt, i8 [[PREVHINTNOTCOLD]]) + %call1 = call ptr @_ZnamRKSt9nothrow_t12__hot_cold_t(i64 10, ptr %nt, i8 7) #1 + call void @dummy(ptr %call1) + ;; Attribute hot converted to __hot_cold_t hot value. + ; HOTCOLD: @_ZnamRKSt9nothrow_t12__hot_cold_t(i64 10, ptr nonnull %nt, i8 [[PREVHINTHOT]]) + %call2 = call ptr @_ZnamRKSt9nothrow_t12__hot_cold_t(i64 10, ptr %nt, i8 7) #2 + call void @dummy(ptr %call2) + ret void +} + +;; Check that operator new[](unsigned long, std::align_val_t, const std::nothrow_t&, __hot_cold_t) +;; optionally has its hint updated. +; HOTCOLD-LABEL: @array_new_align_nothrow_hot_cold() +define void @array_new_align_nothrow_hot_cold() { + %nt = alloca i8 + ;; Attribute cold converted to __hot_cold_t cold value. + ; HOTCOLD: @_ZnamSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 10, i64 8, ptr nonnull %nt, i8 [[PREVHINTCOLD]]) + %call = call ptr @_ZnamSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 10, i64 8, ptr %nt, i8 7) #0 + call void @dummy(ptr %call) + ;; Attribute notcold converted to __hot_cold_t notcold value. + ; HOTCOLD: @_ZnamSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 10, i64 8, ptr nonnull %nt, i8 [[PREVHINTNOTCOLD]]) + %call1 = call ptr @_ZnamSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 10, i64 8, ptr %nt, i8 7) #1 + call void @dummy(ptr %call1) + ;; Attribute hot converted to __hot_cold_t hot value. + ; HOTCOLD: @_ZnamSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 10, i64 8, ptr nonnull %nt, i8 [[PREVHINTHOT]]) + %call2 = call ptr @_ZnamSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 10, i64 8, ptr %nt, i8 7) #2 + call void @dummy(ptr %call2) + ret void +} + ;; So that instcombine doesn't optimize out the call. declare void @dummy(ptr) @@ -189,6 +351,14 @@ declare ptr @_Znam(i64) declare ptr @_ZnamSt11align_val_t(i64, i64) declare ptr @_ZnamRKSt9nothrow_t(i64, ptr) declare ptr @_ZnamSt11align_val_tRKSt9nothrow_t(i64, i64, ptr) +declare ptr @_Znwm12__hot_cold_t(i64, i8) +declare ptr @_ZnwmSt11align_val_t12__hot_cold_t(i64, i64, i8) +declare ptr @_ZnwmRKSt9nothrow_t12__hot_cold_t(i64, ptr, i8) +declare ptr @_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64, i64, ptr, i8) +declare ptr @_Znam12__hot_cold_t(i64, i8) +declare ptr @_ZnamSt11align_val_t12__hot_cold_t(i64, i64, i8) +declare ptr @_ZnamRKSt9nothrow_t12__hot_cold_t(i64, ptr, i8) +declare ptr @_ZnamSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64, i64, ptr, i8) attributes #0 = { builtin allocsize(0) "memprof"="cold" } attributes #1 = { builtin allocsize(0) "memprof"="notcold" } -- GitLab From 965f3ca3dc5464892e283e176bf058ae04d8b654 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 8 May 2024 21:58:59 +0100 Subject: [PATCH 078/328] [GISel] Fold bitreverse(shl/srl(bitreverse(x),y)) -> srl/shl(x,y) (#91355) Sibling patch to #89897 --- .../include/llvm/Target/GlobalISel/Combine.td | 26 +++- .../GlobalISel/combine-bitreverse-shift.ll | 132 +++++------------- 2 files changed, 59 insertions(+), 99 deletions(-) diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td index d0e125390347..98d266c8c0b4 100644 --- a/llvm/include/llvm/Target/GlobalISel/Combine.td +++ b/llvm/include/llvm/Target/GlobalISel/Combine.td @@ -325,6 +325,28 @@ def reduce_shl_of_extend : GICombineRule< [{ return Helper.matchCombineShlOfExtend(*${mi}, ${matchinfo}); }]), (apply [{ Helper.applyCombineShlOfExtend(*${mi}, ${matchinfo}); }])>; +// Combine bitreverse(shl (bitreverse x), y)) -> (lshr x, y) +def bitreverse_shl : GICombineRule< + (defs root:$d), + (match (G_BITREVERSE $rev, $val), + (G_SHL $src, $rev, $amt):$mi, + (G_BITREVERSE $d, $src), + [{ return Helper.isLegalOrBeforeLegalizer({TargetOpcode::G_LSHR, + {MRI.getType(${val}.getReg()), + MRI.getType(${amt}.getReg())}}); }]), + (apply (G_LSHR $d, $val, $amt))>; + +// Combine bitreverse(lshr (bitreverse x), y)) -> (shl x, y) +def bitreverse_lshr : GICombineRule< + (defs root:$d, build_fn_matchinfo:$matchinfo), + (match (G_BITREVERSE $rev, $val), + (G_LSHR $src, $rev, $amt):$mi, + (G_BITREVERSE $d, $src), + [{ return Helper.isLegalOrBeforeLegalizer({TargetOpcode::G_SHL, + {MRI.getType(${val}.getReg()), + MRI.getType(${amt}.getReg())}}); }]), + (apply (G_SHL $d, $val, $amt))>; + // Combine (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) // Combine (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) def commute_shift : GICombineRule< @@ -1645,6 +1667,8 @@ def width_reduction_combines : GICombineGroup<[reduce_shl_of_extend, def phi_combines : GICombineGroup<[extend_through_phis]>; +def bitreverse_shift : GICombineGroup<[bitreverse_shl, bitreverse_lshr]>; + def select_combines : GICombineGroup<[select_undef_cmp, select_constant_cmp, match_selects]>; @@ -1674,7 +1698,7 @@ def all_combines : GICombineGroup<[trivial_combines, vector_ops_combines, unmerge_zext_to_zext, merge_unmerge, trunc_ext_fold, trunc_shift, const_combines, xor_of_and_with_same_reg, ptr_add_with_zero, shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine, - div_rem_to_divrem, funnel_shift_combines, commute_shift, + div_rem_to_divrem, funnel_shift_combines, bitreverse_shift, commute_shift, form_bitfield_extract, constant_fold_binops, constant_fold_fma, constant_fold_cast_op, fabs_fneg_fold, intdiv_combines, mulh_combines, redundant_neg_operands, diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-bitreverse-shift.ll b/llvm/test/CodeGen/AArch64/GlobalISel/combine-bitreverse-shift.ll index 3ce94e2c40a9..b9fbe2379a42 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-bitreverse-shift.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-bitreverse-shift.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefixes=SDAG -; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel | FileCheck %s --check-prefixes=GISEL +; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s +; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel | FileCheck %s ; These tests can be optimised ; fold (bitreverse(srl (bitreverse c), x)) -> (shl c, x) @@ -12,19 +12,10 @@ declare i32 @llvm.bitreverse.i32(i32) declare i64 @llvm.bitreverse.i64(i64) define i8 @test_bitreverse_srli_bitreverse_i8(i8 %a) nounwind { -; SDAG-LABEL: test_bitreverse_srli_bitreverse_i8: -; SDAG: // %bb.0: -; SDAG-NEXT: lsl w0, w0, #3 -; SDAG-NEXT: ret -; -; GISEL-LABEL: test_bitreverse_srli_bitreverse_i8: -; GISEL: // %bb.0: -; GISEL-NEXT: rbit w8, w0 -; GISEL-NEXT: lsr w8, w8, #24 -; GISEL-NEXT: lsr w8, w8, #3 -; GISEL-NEXT: rbit w8, w8 -; GISEL-NEXT: lsr w0, w8, #24 -; GISEL-NEXT: ret +; CHECK-LABEL: test_bitreverse_srli_bitreverse_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: lsl w0, w0, #3 +; CHECK-NEXT: ret %1 = call i8 @llvm.bitreverse.i8(i8 %a) %2 = lshr i8 %1, 3 %3 = call i8 @llvm.bitreverse.i8(i8 %2) @@ -32,19 +23,10 @@ define i8 @test_bitreverse_srli_bitreverse_i8(i8 %a) nounwind { } define i16 @test_bitreverse_srli_bitreverse_i16(i16 %a) nounwind { -; SDAG-LABEL: test_bitreverse_srli_bitreverse_i16: -; SDAG: // %bb.0: -; SDAG-NEXT: lsl w0, w0, #7 -; SDAG-NEXT: ret -; -; GISEL-LABEL: test_bitreverse_srli_bitreverse_i16: -; GISEL: // %bb.0: -; GISEL-NEXT: rbit w8, w0 -; GISEL-NEXT: lsr w8, w8, #16 -; GISEL-NEXT: lsr w8, w8, #7 -; GISEL-NEXT: rbit w8, w8 -; GISEL-NEXT: lsr w0, w8, #16 -; GISEL-NEXT: ret +; CHECK-LABEL: test_bitreverse_srli_bitreverse_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: lsl w0, w0, #7 +; CHECK-NEXT: ret %1 = call i16 @llvm.bitreverse.i16(i16 %a) %2 = lshr i16 %1, 7 %3 = call i16 @llvm.bitreverse.i16(i16 %2) @@ -52,17 +34,10 @@ define i16 @test_bitreverse_srli_bitreverse_i16(i16 %a) nounwind { } define i32 @test_bitreverse_srli_bitreverse_i32(i32 %a) nounwind { -; SDAG-LABEL: test_bitreverse_srli_bitreverse_i32: -; SDAG: // %bb.0: -; SDAG-NEXT: lsl w0, w0, #15 -; SDAG-NEXT: ret -; -; GISEL-LABEL: test_bitreverse_srli_bitreverse_i32: -; GISEL: // %bb.0: -; GISEL-NEXT: rbit w8, w0 -; GISEL-NEXT: lsr w8, w8, #15 -; GISEL-NEXT: rbit w0, w8 -; GISEL-NEXT: ret +; CHECK-LABEL: test_bitreverse_srli_bitreverse_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: lsl w0, w0, #15 +; CHECK-NEXT: ret %1 = call i32 @llvm.bitreverse.i32(i32 %a) %2 = lshr i32 %1, 15 %3 = call i32 @llvm.bitreverse.i32(i32 %2) @@ -70,17 +45,10 @@ define i32 @test_bitreverse_srli_bitreverse_i32(i32 %a) nounwind { } define i64 @test_bitreverse_srli_bitreverse_i64(i64 %a) nounwind { -; SDAG-LABEL: test_bitreverse_srli_bitreverse_i64: -; SDAG: // %bb.0: -; SDAG-NEXT: lsl x0, x0, #33 -; SDAG-NEXT: ret -; -; GISEL-LABEL: test_bitreverse_srli_bitreverse_i64: -; GISEL: // %bb.0: -; GISEL-NEXT: rbit x8, x0 -; GISEL-NEXT: lsr x8, x8, #33 -; GISEL-NEXT: rbit x0, x8 -; GISEL-NEXT: ret +; CHECK-LABEL: test_bitreverse_srli_bitreverse_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: lsl x0, x0, #33 +; CHECK-NEXT: ret %1 = call i64 @llvm.bitreverse.i64(i64 %a) %2 = lshr i64 %1, 33 %3 = call i64 @llvm.bitreverse.i64(i64 %2) @@ -88,19 +56,10 @@ define i64 @test_bitreverse_srli_bitreverse_i64(i64 %a) nounwind { } define i8 @test_bitreverse_shli_bitreverse_i8(i8 %a) nounwind { -; SDAG-LABEL: test_bitreverse_shli_bitreverse_i8: -; SDAG: // %bb.0: -; SDAG-NEXT: ubfx w0, w0, #3, #5 -; SDAG-NEXT: ret -; -; GISEL-LABEL: test_bitreverse_shli_bitreverse_i8: -; GISEL: // %bb.0: -; GISEL-NEXT: rbit w8, w0 -; GISEL-NEXT: lsr w8, w8, #24 -; GISEL-NEXT: lsl w8, w8, #3 -; GISEL-NEXT: rbit w8, w8 -; GISEL-NEXT: lsr w0, w8, #24 -; GISEL-NEXT: ret +; CHECK-LABEL: test_bitreverse_shli_bitreverse_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ubfx w0, w0, #3, #5 +; CHECK-NEXT: ret %1 = call i8 @llvm.bitreverse.i8(i8 %a) %2 = shl i8 %1, 3 %3 = call i8 @llvm.bitreverse.i8(i8 %2) @@ -108,19 +67,10 @@ define i8 @test_bitreverse_shli_bitreverse_i8(i8 %a) nounwind { } define i16 @test_bitreverse_shli_bitreverse_i16(i16 %a) nounwind { -; SDAG-LABEL: test_bitreverse_shli_bitreverse_i16: -; SDAG: // %bb.0: -; SDAG-NEXT: ubfx w0, w0, #7, #9 -; SDAG-NEXT: ret -; -; GISEL-LABEL: test_bitreverse_shli_bitreverse_i16: -; GISEL: // %bb.0: -; GISEL-NEXT: rbit w8, w0 -; GISEL-NEXT: lsr w8, w8, #16 -; GISEL-NEXT: lsl w8, w8, #7 -; GISEL-NEXT: rbit w8, w8 -; GISEL-NEXT: lsr w0, w8, #16 -; GISEL-NEXT: ret +; CHECK-LABEL: test_bitreverse_shli_bitreverse_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ubfx w0, w0, #7, #9 +; CHECK-NEXT: ret %1 = call i16 @llvm.bitreverse.i16(i16 %a) %2 = shl i16 %1, 7 %3 = call i16 @llvm.bitreverse.i16(i16 %2) @@ -128,17 +78,10 @@ define i16 @test_bitreverse_shli_bitreverse_i16(i16 %a) nounwind { } define i32 @test_bitreverse_shli_bitreverse_i32(i32 %a) nounwind { -; SDAG-LABEL: test_bitreverse_shli_bitreverse_i32: -; SDAG: // %bb.0: -; SDAG-NEXT: lsr w0, w0, #15 -; SDAG-NEXT: ret -; -; GISEL-LABEL: test_bitreverse_shli_bitreverse_i32: -; GISEL: // %bb.0: -; GISEL-NEXT: rbit w8, w0 -; GISEL-NEXT: lsl w8, w8, #15 -; GISEL-NEXT: rbit w0, w8 -; GISEL-NEXT: ret +; CHECK-LABEL: test_bitreverse_shli_bitreverse_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: lsr w0, w0, #15 +; CHECK-NEXT: ret %1 = call i32 @llvm.bitreverse.i32(i32 %a) %2 = shl i32 %1, 15 %3 = call i32 @llvm.bitreverse.i32(i32 %2) @@ -146,17 +89,10 @@ define i32 @test_bitreverse_shli_bitreverse_i32(i32 %a) nounwind { } define i64 @test_bitreverse_shli_bitreverse_i64(i64 %a) nounwind { -; SDAG-LABEL: test_bitreverse_shli_bitreverse_i64: -; SDAG: // %bb.0: -; SDAG-NEXT: lsr x0, x0, #33 -; SDAG-NEXT: ret -; -; GISEL-LABEL: test_bitreverse_shli_bitreverse_i64: -; GISEL: // %bb.0: -; GISEL-NEXT: rbit x8, x0 -; GISEL-NEXT: lsl x8, x8, #33 -; GISEL-NEXT: rbit x0, x8 -; GISEL-NEXT: ret +; CHECK-LABEL: test_bitreverse_shli_bitreverse_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: lsr x0, x0, #33 +; CHECK-NEXT: ret %1 = call i64 @llvm.bitreverse.i64(i64 %a) %2 = shl i64 %1, 33 %3 = call i64 @llvm.bitreverse.i64(i64 %2) -- GitLab From fcf945f4edbad1f2d82df067c2826baa6165dd3e Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 8 May 2024 22:11:18 +0100 Subject: [PATCH 079/328] [DAG] Fold add(mul(add(A, CA), CM), CB) -> add(mul(A, CM), CM*CA+CB) (#90860) This is useful when the inner add has multiple uses, and so cannot be canonicalized by pushing the constants down through the mul. This patch adds patterns for both `add(mul(add(A, CA), CM), CB)` and with an extra add `add(add(mul(add(A, CA), CM), B) CB)` as the second can come up when lowering geps. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 60 +++++++++++++++++ llvm/test/CodeGen/AArch64/addimm-mulimm.ll | 67 +++++++++---------- 2 files changed, 91 insertions(+), 36 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index e835bd950a7b..4589d201d620 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2838,6 +2838,66 @@ SDValue DAGCombiner::visitADDLike(SDNode *N) { return DAG.getNode(ISD::ADD, DL, VT, Not, N0.getOperand(0)); } + // Fold add(mul(add(A, CA), CM), CB) -> add(mul(A, CM), CM*CA+CB). + // This can help if the inner add has multiple uses. + APInt CM, CA; + if (ConstantSDNode *CB = dyn_cast(N1)) { + if (VT.getScalarSizeInBits() <= 64) { + if (sd_match(N0, m_OneUse(m_Mul(m_Add(m_Value(A), m_ConstInt(CA)), + m_ConstInt(CM)))) && + TLI.isLegalAddImmediate( + (CA * CM + CB->getAPIntValue()).getSExtValue())) { + SDNodeFlags Flags; + // If all the inputs are nuw, the outputs can be nuw. If all the input + // are _also_ nsw the outputs can be too. + if (N->getFlags().hasNoUnsignedWrap() && + N0->getFlags().hasNoUnsignedWrap() && + N0.getOperand(0)->getFlags().hasNoUnsignedWrap()) { + Flags.setNoUnsignedWrap(true); + if (N->getFlags().hasNoSignedWrap() && + N0->getFlags().hasNoSignedWrap() && + N0.getOperand(0)->getFlags().hasNoSignedWrap()) + Flags.setNoSignedWrap(true); + } + SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N1), VT, A, + DAG.getConstant(CM, DL, VT), Flags); + return DAG.getNode( + ISD::ADD, DL, VT, Mul, + DAG.getConstant(CA * CM + CB->getAPIntValue(), DL, VT), Flags); + } + // Also look in case there is an intermediate add. + if (sd_match(N0, m_OneUse(m_Add( + m_OneUse(m_Mul(m_Add(m_Value(A), m_ConstInt(CA)), + m_ConstInt(CM))), + m_Value(B)))) && + TLI.isLegalAddImmediate( + (CA * CM + CB->getAPIntValue()).getSExtValue())) { + SDNodeFlags Flags; + // If all the inputs are nuw, the outputs can be nuw. If all the input + // are _also_ nsw the outputs can be too. + SDValue OMul = + N0.getOperand(0) == B ? N0.getOperand(1) : N0.getOperand(0); + if (N->getFlags().hasNoUnsignedWrap() && + N0->getFlags().hasNoUnsignedWrap() && + OMul->getFlags().hasNoUnsignedWrap() && + OMul.getOperand(0)->getFlags().hasNoUnsignedWrap()) { + Flags.setNoUnsignedWrap(true); + if (N->getFlags().hasNoSignedWrap() && + N0->getFlags().hasNoSignedWrap() && + OMul->getFlags().hasNoSignedWrap() && + OMul.getOperand(0)->getFlags().hasNoSignedWrap()) + Flags.setNoSignedWrap(true); + } + SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N1), VT, A, + DAG.getConstant(CM, DL, VT), Flags); + SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N1), VT, Mul, B, Flags); + return DAG.getNode( + ISD::ADD, DL, VT, Add, + DAG.getConstant(CA * CM + CB->getAPIntValue(), DL, VT), Flags); + } + } + } + if (SDValue Combined = visitADDLikeCommutative(N0, N1, N)) return Combined; diff --git a/llvm/test/CodeGen/AArch64/addimm-mulimm.ll b/llvm/test/CodeGen/AArch64/addimm-mulimm.ll index 3618b14aa921..6636813eb250 100644 --- a/llvm/test/CodeGen/AArch64/addimm-mulimm.ll +++ b/llvm/test/CodeGen/AArch64/addimm-mulimm.ll @@ -166,9 +166,9 @@ define signext i32 @addmuladd_multiuse(i32 signext %a) { ; CHECK-LABEL: addmuladd_multiuse: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #324 // =0x144 +; CHECK-NEXT: mov w9, #1300 // =0x514 +; CHECK-NEXT: madd w8, w0, w8, w9 ; CHECK-NEXT: add w9, w0, #4 -; CHECK-NEXT: mov w10, #4 // =0x4 -; CHECK-NEXT: madd w8, w9, w8, w10 ; CHECK-NEXT: eor w0, w9, w8 ; CHECK-NEXT: ret %tmp0 = add i32 %a, 4 @@ -198,11 +198,10 @@ define signext i32 @addmuladd_multiuse2(i32 signext %a) { ; CHECK-LABEL: addmuladd_multiuse2: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #324 // =0x144 -; CHECK-NEXT: add w9, w0, #4 -; CHECK-NEXT: mov w11, #4 // =0x4 -; CHECK-NEXT: lsl w10, w9, #2 -; CHECK-NEXT: madd w8, w9, w8, w11 -; CHECK-NEXT: add w9, w10, #4 +; CHECK-NEXT: lsl w9, w0, #2 +; CHECK-NEXT: mov w10, #1300 // =0x514 +; CHECK-NEXT: madd w8, w0, w8, w10 +; CHECK-NEXT: add w9, w9, #20 ; CHECK-NEXT: eor w0, w8, w9 ; CHECK-NEXT: ret %tmp0 = add i32 %a, 4 @@ -233,8 +232,8 @@ define signext i32 @addaddmuladd_multiuse(i32 signext %a, i32 %b) { ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #324 // =0x144 ; CHECK-NEXT: add w9, w0, #4 -; CHECK-NEXT: madd w8, w9, w8, w1 -; CHECK-NEXT: add w8, w8, #4 +; CHECK-NEXT: madd w8, w0, w8, w1 +; CHECK-NEXT: add w8, w8, #1300 ; CHECK-NEXT: eor w0, w9, w8 ; CHECK-NEXT: ret %tmp0 = add i32 %a, 4 @@ -249,12 +248,11 @@ define signext i32 @addaddmuladd_multiuse2(i32 signext %a, i32 %b) { ; CHECK-LABEL: addaddmuladd_multiuse2: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #324 // =0x144 -; CHECK-NEXT: add w9, w0, #4 -; CHECK-NEXT: mov w10, #162 // =0xa2 -; CHECK-NEXT: madd w8, w9, w8, w1 -; CHECK-NEXT: madd w9, w9, w10, w1 -; CHECK-NEXT: add w8, w8, #4 -; CHECK-NEXT: add w9, w9, #4 +; CHECK-NEXT: mov w9, #162 // =0xa2 +; CHECK-NEXT: madd w8, w0, w8, w1 +; CHECK-NEXT: madd w9, w0, w9, w1 +; CHECK-NEXT: add w8, w8, #1300 +; CHECK-NEXT: add w9, w9, #652 ; CHECK-NEXT: eor w0, w9, w8 ; CHECK-NEXT: ret %tmp0 = add i32 %a, 4 @@ -319,17 +317,17 @@ define void @addmuladd_gep(ptr %p, i64 %a) { define i32 @addmuladd_gep2(ptr %p, i32 %a) { ; CHECK-LABEL: addmuladd_gep2: ; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #3240 // =0xca8 ; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: sxtw x8, w1 -; CHECK-NEXT: mov w9, #3240 // =0xca8 -; CHECK-NEXT: add x8, x8, #1 -; CHECK-NEXT: madd x9, x8, x9, x0 -; CHECK-NEXT: ldr w9, [x9, #20] -; CHECK-NEXT: tbnz w9, #31, .LBB22_2 +; CHECK-NEXT: smaddl x8, w1, w8, x0 +; CHECK-NEXT: ldr w8, [x8, #3260] +; CHECK-NEXT: tbnz w8, #31, .LBB22_2 ; CHECK-NEXT: // %bb.1: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB22_2: // %then +; CHECK-NEXT: sxtw x8, w1 +; CHECK-NEXT: add x8, x8, #1 ; CHECK-NEXT: str x8, [x0] ; CHECK-NEXT: mov w0, #1 // =0x1 ; CHECK-NEXT: ret @@ -351,11 +349,10 @@ define signext i32 @addmuladd_multiuse2_nsw(i32 signext %a) { ; CHECK-LABEL: addmuladd_multiuse2_nsw: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #324 // =0x144 -; CHECK-NEXT: add w9, w0, #4 -; CHECK-NEXT: mov w11, #4 // =0x4 -; CHECK-NEXT: lsl w10, w9, #2 -; CHECK-NEXT: madd w8, w9, w8, w11 -; CHECK-NEXT: add w9, w10, #4 +; CHECK-NEXT: lsl w9, w0, #2 +; CHECK-NEXT: mov w10, #1300 // =0x514 +; CHECK-NEXT: madd w8, w0, w8, w10 +; CHECK-NEXT: add w9, w9, #20 ; CHECK-NEXT: eor w0, w8, w9 ; CHECK-NEXT: ret %tmp0 = add nsw i32 %a, 4 @@ -371,11 +368,10 @@ define signext i32 @addmuladd_multiuse2_nuw(i32 signext %a) { ; CHECK-LABEL: addmuladd_multiuse2_nuw: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #324 // =0x144 -; CHECK-NEXT: add w9, w0, #4 -; CHECK-NEXT: mov w11, #4 // =0x4 -; CHECK-NEXT: lsl w10, w9, #2 -; CHECK-NEXT: madd w8, w9, w8, w11 -; CHECK-NEXT: add w9, w10, #4 +; CHECK-NEXT: lsl w9, w0, #2 +; CHECK-NEXT: mov w10, #1300 // =0x514 +; CHECK-NEXT: madd w8, w0, w8, w10 +; CHECK-NEXT: add w9, w9, #20 ; CHECK-NEXT: eor w0, w8, w9 ; CHECK-NEXT: ret %tmp0 = add nuw i32 %a, 4 @@ -391,11 +387,10 @@ define signext i32 @addmuladd_multiuse2_nswnuw(i32 signext %a) { ; CHECK-LABEL: addmuladd_multiuse2_nswnuw: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #324 // =0x144 -; CHECK-NEXT: add w9, w0, #4 -; CHECK-NEXT: mov w11, #4 // =0x4 -; CHECK-NEXT: lsl w10, w9, #2 -; CHECK-NEXT: madd w8, w9, w8, w11 -; CHECK-NEXT: add w9, w10, #4 +; CHECK-NEXT: lsl w9, w0, #2 +; CHECK-NEXT: mov w10, #1300 // =0x514 +; CHECK-NEXT: madd w8, w0, w8, w10 +; CHECK-NEXT: add w9, w9, #20 ; CHECK-NEXT: eor w0, w8, w9 ; CHECK-NEXT: ret %tmp0 = add nsw nuw i32 %a, 4 -- GitLab From e37bd6c68b50a556ff0e9261cf9eba64afa06bf9 Mon Sep 17 00:00:00 2001 From: lntue <35648136+lntue@users.noreply.github.com> Date: Wed, 8 May 2024 17:32:05 -0400 Subject: [PATCH 080/328] [libc][fenv] Add missing FE_* definitions for some environment. (#91519) --- libc/hdr/fenv_macros.h | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/libc/hdr/fenv_macros.h b/libc/hdr/fenv_macros.h index 041fca5f224b..a2e4462ef02d 100644 --- a/libc/hdr/fenv_macros.h +++ b/libc/hdr/fenv_macros.h @@ -17,10 +17,51 @@ #include +// In some environment, FE_ALL_EXCEPT is set to 0 and the remaining exceptions +// FE_* are missing. +#if (FE_ALL_EXCEPT == 0) +#ifndef FE_DIVBYZERO +#define FE_DIVBYZERO 0 +#endif // FE_DIVBYZERO + +#ifndef FE_INEXACT +#define FE_INEXACT 0 +#endif // FE_INEXACT + +#ifndef FE_INVALID +#define FE_INVALID 0 +#endif // FE_INVALID + +#ifndef FE_OVERFLOW +#define FE_OVERFLOW 0 +#endif // FE_OVERFLOW + +#ifndef FE_UNDERFLOW +#define FE_UNDERFLOW 0 +#endif // FE_UNDERFLOW +#else // If this is not provided by the system, define it for use internally. #ifndef __FE_DENORM #define __FE_DENORM (1 << 6) #endif +#endif + +// Rounding mode macros might be missing. +#ifndef FE_DOWNWARD +#define FE_DOWNWARD 0x400 +#endif // FE_DOWNWARD + +#ifndef FE_TONEAREST +#define FE_TONEAREST 0 +#endif // FE_TONEAREST + +#ifndef FE_TOWARDZERO +#define FE_TOWARDZERO 0xC00 +#endif // FE_TOWARDZERO + +#ifndef FE_UPWARD +#define FE_UPWARD 0x800 +#endif // FE_UPWARD #endif // LLVM_LIBC_FULL_BUILD -- GitLab From 7ec8a333b5fdf1ee78426fe3557c330aa920aa5f Mon Sep 17 00:00:00 2001 From: Dave Lee Date: Wed, 8 May 2024 15:07:14 -0700 Subject: [PATCH 081/328] [lldb] Display breakpoint locations using display name (#90297) Adds a `show_function_display_name` parameter to `SymbolContext::DumpStopContext`. This parameter defaults to false, but `BreakpointLocation::GetDescription` sets it to true. This is NFC in mainline lldb, and will be used to modify how Swift breakpoint locations are printed. --- lldb/include/lldb/Symbol/SymbolContext.h | 1 + lldb/source/Breakpoint/BreakpointLocation.cpp | 2 +- lldb/source/Core/Address.cpp | 5 +++-- lldb/source/Symbol/SymbolContext.cpp | 13 +++++++++++-- 4 files changed, 16 insertions(+), 5 deletions(-) diff --git a/lldb/include/lldb/Symbol/SymbolContext.h b/lldb/include/lldb/Symbol/SymbolContext.h index bd33a71b46ca..0bc707070f85 100644 --- a/lldb/include/lldb/Symbol/SymbolContext.h +++ b/lldb/include/lldb/Symbol/SymbolContext.h @@ -158,6 +158,7 @@ public: Stream *s, ExecutionContextScope *exe_scope, const Address &so_addr, bool show_fullpaths, bool show_module, bool show_inlined_frames, bool show_function_arguments, bool show_function_name, + bool show_function_display_name = false, std::optional settings = std::nullopt) const; /// Get the address range contained within a symbol context. diff --git a/lldb/source/Breakpoint/BreakpointLocation.cpp b/lldb/source/Breakpoint/BreakpointLocation.cpp index b48ec1398d63..41911fad41c6 100644 --- a/lldb/source/Breakpoint/BreakpointLocation.cpp +++ b/lldb/source/Breakpoint/BreakpointLocation.cpp @@ -507,7 +507,7 @@ void BreakpointLocation::GetDescription(Stream *s, else s->PutCString("where = "); sc.DumpStopContext(s, m_owner.GetTarget().GetProcessSP().get(), m_address, - false, true, false, true, true); + false, true, false, true, true, true); } else { if (sc.module_sp) { s->EOL(); diff --git a/lldb/source/Core/Address.cpp b/lldb/source/Core/Address.cpp index b23398883fa5..5a4751bd5256 100644 --- a/lldb/source/Core/Address.cpp +++ b/lldb/source/Core/Address.cpp @@ -645,7 +645,8 @@ bool Address::Dump(Stream *s, ExecutionContextScope *exe_scope, DumpStyle style, pointer_sc.symbol != nullptr) { s->PutCString(": "); pointer_sc.DumpStopContext(s, exe_scope, so_addr, true, false, - false, true, true, settings); + false, true, true, false, + settings); } } } @@ -685,7 +686,7 @@ bool Address::Dump(Stream *s, ExecutionContextScope *exe_scope, DumpStyle style, sc.DumpStopContext(s, exe_scope, *this, show_fullpaths, show_module, show_inlined_frames, show_function_arguments, show_function_name, - settings); + false, settings); } else { // We found a symbol but it was in a different section so it // isn't the symbol we should be showing, just show the section diff --git a/lldb/source/Symbol/SymbolContext.cpp b/lldb/source/Symbol/SymbolContext.cpp index f368896fbad4..8f26e41d1920 100644 --- a/lldb/source/Symbol/SymbolContext.cpp +++ b/lldb/source/Symbol/SymbolContext.cpp @@ -73,6 +73,7 @@ bool SymbolContext::DumpStopContext( Stream *s, ExecutionContextScope *exe_scope, const Address &addr, bool show_fullpaths, bool show_module, bool show_inlined_frames, bool show_function_arguments, bool show_function_name, + bool show_function_display_name, std::optional settings) const { bool dumped_something = false; if (show_module && module_sp) { @@ -93,6 +94,8 @@ bool SymbolContext::DumpStopContext( ConstString name; if (!show_function_arguments) name = function->GetNameNoArguments(); + if (!name && show_function_display_name) + name = function->GetDisplayName(); if (!name) name = function->GetName(); if (name) @@ -146,7 +149,8 @@ bool SymbolContext::DumpStopContext( const bool show_function_name = true; return inline_parent_sc.DumpStopContext( s, exe_scope, inline_parent_addr, show_fullpaths, show_module, - show_inlined_frames, show_function_arguments, show_function_name); + show_inlined_frames, show_function_arguments, show_function_name, + show_function_display_name); } } else { if (line_entry.IsValid()) { @@ -164,7 +168,12 @@ bool SymbolContext::DumpStopContext( dumped_something = true; if (symbol->GetType() == eSymbolTypeTrampoline) s->PutCString("symbol stub for: "); - s->PutCStringColorHighlighted(symbol->GetName().GetStringRef(), settings); + ConstString name; + if (show_function_display_name) + name = symbol->GetDisplayName(); + if (!name) + name = symbol->GetName(); + s->PutCStringColorHighlighted(name.GetStringRef(), settings); } if (addr.IsValid() && symbol->ValueIsAddress()) { -- GitLab From 1610eaad39ad882f006f32c29771862a610f8314 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Wed, 8 May 2024 15:12:48 -0700 Subject: [PATCH 082/328] [memprof] Make Version2 officially available (#91541) --- llvm/include/llvm/ProfileData/MemProf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/include/llvm/ProfileData/MemProf.h b/llvm/include/llvm/ProfileData/MemProf.h index 4274f2a6849b..3ef6ca8586fb 100644 --- a/llvm/include/llvm/ProfileData/MemProf.h +++ b/llvm/include/llvm/ProfileData/MemProf.h @@ -26,7 +26,7 @@ enum IndexedVersion : uint64_t { Version0 = 0, // Version 1: Added a version field to the header. Version1 = 1, - // Version 2: Added a call stack table. Under development. + // Version 2: Added a call stack table. Version2 = 2, }; -- GitLab From 64f4ceb09ec3559368dd775330184b5259531cd3 Mon Sep 17 00:00:00 2001 From: Mingming Liu Date: Wed, 8 May 2024 15:48:40 -0700 Subject: [PATCH 083/328] [Inline][PGO] After inline, update InvokeInst profile counts in caller and cloned callee (#83809) A related change is https://reviews.llvm.org/D133121, which correctly preserves both branch weights and value profiles for invoke instruction. * If the branch weight of the `invokeinst` specifies taken / not-taken branches, there is no scale. --- llvm/include/llvm/IR/Instructions.h | 3 ++ llvm/lib/IR/Instructions.cpp | 12 ++++++ llvm/lib/IR/ProfDataUtils.cpp | 20 ++++++++++ llvm/lib/Transforms/Utils/InlineFunction.cpp | 11 +++++- .../Transforms/Inline/update_invoke_prof.ll | 38 ++++++++++++++----- 5 files changed, 72 insertions(+), 12 deletions(-) diff --git a/llvm/include/llvm/IR/Instructions.h b/llvm/include/llvm/IR/Instructions.h index d7ec3c16bec2..0f7b215b80fd 100644 --- a/llvm/include/llvm/IR/Instructions.h +++ b/llvm/include/llvm/IR/Instructions.h @@ -4370,6 +4370,9 @@ public: unsigned getNumSuccessors() const { return 2; } + /// Updates profile metadata by scaling it by \p S / \p T. + void updateProfWeight(uint64_t S, uint64_t T); + // Methods for support type inquiry through isa, cast, and dyn_cast: static bool classof(const Instruction *I) { return (I->getOpcode() == Instruction::Invoke); diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp index 4b725610081c..c31d399b01d1 100644 --- a/llvm/lib/IR/Instructions.cpp +++ b/llvm/lib/IR/Instructions.cpp @@ -927,6 +927,18 @@ LandingPadInst *InvokeInst::getLandingPadInst() const { return cast(getUnwindDest()->getFirstNonPHI()); } +void InvokeInst::updateProfWeight(uint64_t S, uint64_t T) { + if (T == 0) { + LLVM_DEBUG(dbgs() << "Attempting to update profile weights will result in " + "div by 0. Ignoring. Likely the function " + << getParent()->getParent()->getName() + << " has 0 entry count, and contains call instructions " + "with non-zero prof info."); + return; + } + scaleProfData(*this, S, T); +} + //===----------------------------------------------------------------------===// // CallBrInst Implementation //===----------------------------------------------------------------------===// diff --git a/llvm/lib/IR/ProfDataUtils.cpp b/llvm/lib/IR/ProfDataUtils.cpp index 3d72418593a7..51e78dc5e6c0 100644 --- a/llvm/lib/IR/ProfDataUtils.cpp +++ b/llvm/lib/IR/ProfDataUtils.cpp @@ -46,6 +46,9 @@ constexpr unsigned WeightsIdx = 1; // the minimum number of operands for MD_prof nodes with branch weights constexpr unsigned MinBWOps = 3; +// the minimum number of operands for MD_prof nodes with value profiles +constexpr unsigned MinVPOps = 5; + // We may want to add support for other MD_prof types, so provide an abstraction // for checking the metadata type. bool isTargetMD(const MDNode *ProfData, const char *Name, unsigned MinOps) { @@ -97,11 +100,25 @@ bool isBranchWeightMD(const MDNode *ProfileData) { return isTargetMD(ProfileData, "branch_weights", MinBWOps); } +bool isValueProfileMD(const MDNode *ProfileData) { + return isTargetMD(ProfileData, "VP", MinVPOps); +} + bool hasBranchWeightMD(const Instruction &I) { auto *ProfileData = I.getMetadata(LLVMContext::MD_prof); return isBranchWeightMD(ProfileData); } +bool hasCountTypeMD(const Instruction &I) { + auto *ProfileData = I.getMetadata(LLVMContext::MD_prof); + // Value profiles record count-type information. + if (isValueProfileMD(ProfileData)) + return true; + // Conservatively assume non CallBase instruction only get taken/not-taken + // branch probability, so not interpret them as count. + return isa(I) && !isBranchWeightMD(ProfileData); +} + bool hasValidBranchWeightMD(const Instruction &I) { return getValidBranchWeightMDNode(I); } @@ -212,6 +229,9 @@ void scaleProfData(Instruction &I, uint64_t S, uint64_t T) { ProfDataName->getString() != "VP")) return; + if (!hasCountTypeMD(I)) + return; + LLVMContext &C = I.getContext(); MDBuilder MDB(C); diff --git a/llvm/lib/Transforms/Utils/InlineFunction.cpp b/llvm/lib/Transforms/Utils/InlineFunction.cpp index 1aae561d8817..48bb76eb85e3 100644 --- a/llvm/lib/Transforms/Utils/InlineFunction.cpp +++ b/llvm/lib/Transforms/Utils/InlineFunction.cpp @@ -1982,10 +1982,14 @@ void llvm::updateProfileCallee( // During inlining ? if (VMap) { uint64_t CloneEntryCount = PriorEntryCount - NewEntryCount; - for (auto Entry : *VMap) + for (auto Entry : *VMap) { if (isa(Entry.first)) if (auto *CI = dyn_cast_or_null(Entry.second)) CI->updateProfWeight(CloneEntryCount, PriorEntryCount); + if (isa(Entry.first)) + if (auto *II = dyn_cast_or_null(Entry.second)) + II->updateProfWeight(CloneEntryCount, PriorEntryCount); + } } if (EntryDelta) { @@ -1994,9 +1998,12 @@ void llvm::updateProfileCallee( for (BasicBlock &BB : *Callee) // No need to update the callsite if it is pruned during inlining. if (!VMap || VMap->count(&BB)) - for (Instruction &I : BB) + for (Instruction &I : BB) { if (CallInst *CI = dyn_cast(&I)) CI->updateProfWeight(NewEntryCount, PriorEntryCount); + if (InvokeInst *II = dyn_cast(&I)) + II->updateProfWeight(NewEntryCount, PriorEntryCount); + } } } diff --git a/llvm/test/Transforms/Inline/update_invoke_prof.ll b/llvm/test/Transforms/Inline/update_invoke_prof.ll index 5f09c7cf8fe0..f6b86dfe5bb1 100644 --- a/llvm/test/Transforms/Inline/update_invoke_prof.ll +++ b/llvm/test/Transforms/Inline/update_invoke_prof.ll @@ -1,22 +1,31 @@ -; A pre-commit test to show that branch weights and value profiles associated with invoke are not updated. +; Test that branch weights and value profiles associated with invoke are updated +; in both caller and callee after inline, but invoke instructions with taken or +; not taken branch probabilities are not updated. ; RUN: opt < %s -passes='require,cgscc(inline)' -S | FileCheck %s declare i32 @__gxx_personality_v0(...) define void @caller(ptr %func) personality ptr @__gxx_personality_v0 !prof !15 { call void @callee(ptr %func), !prof !16 + ret void } -declare void @inner_callee(ptr %func) +declare void @callee1(ptr %func) + +declare void @callee2(ptr %func) define void @callee(ptr %func) personality ptr @__gxx_personality_v0 !prof !17 { invoke void %func() to label %next unwind label %lpad, !prof !18 next: - invoke void @inner_callee(ptr %func) - to label %ret unwind label %lpad, !prof !19 + invoke void @callee1(ptr %func) + to label %cont unwind label %lpad, !prof !19 + +cont: + invoke void @callee2(ptr %func) + to label %ret unwind label %lpad, !prof !20 lpad: %exn = landingpad {ptr, i32} @@ -47,18 +56,27 @@ ret: !17 = !{!"function_entry_count", i32 1500} !18 = !{!"VP", i32 0, i64 1500, i64 123, i64 900, i64 456, i64 600} !19 = !{!"branch_weights", i32 1500} +!20 = !{!"branch_weights", i32 1234, i32 5678} ; CHECK-LABEL: @caller( ; CHECK: invoke void %func( ; CHECK-NEXT: {{.*}} !prof ![[PROF1:[0-9]+]] -; CHECK: invoke void @inner_callee( +; CHECK: invoke void @callee1( ; CHECK-NEXT: {{.*}} !prof ![[PROF2:[0-9]+]] +; CHECK: invoke void @callee2( +; CHECK-NEXT: {{.*}} !prof ![[PROF3:[0-9]+]] ; CHECK-LABL: @callee( ; CHECK: invoke void %func( -; CHECK-NEXT: {{.*}} !prof ![[PROF1]] -; CHECK: invoke void @inner_callee( -; CHECK-NEXT: {{.*}} !prof ![[PROF2]] +; CHECK-NEXT: {{.*}} !prof ![[PROF4:[0-9]+]] +; CHECK: invoke void @callee1( +; CHECK-NEXT: {{.*}} !prof ![[PROF5:[0-9]+]] +; CHECK: invoke void @callee2( +; CHECK-NEXT: {{.*}} !prof ![[PROF3]] + -; CHECK: ![[PROF1]] = !{!"VP", i32 0, i64 1500, i64 123, i64 900, i64 456, i64 600} -; CHECK: ![[PROF2]] = !{!"branch_weights", i32 1500} +; CHECK: ![[PROF1]] = !{!"VP", i32 0, i64 1000, i64 123, i64 600, i64 456, i64 400} +; CHECK: ![[PROF2]] = !{!"branch_weights", i32 1000} +; CHECK: ![[PROF3]] = !{!"branch_weights", i32 1234, i32 5678} +; CHECK: ![[PROF4]] = !{!"VP", i32 0, i64 500, i64 123, i64 300, i64 456, i64 200} +; CHECK: ![[PROF5]] = !{!"branch_weights", i32 500} -- GitLab From 99052c4bdf9593a2e648f2c99cabaab36580898c Mon Sep 17 00:00:00 2001 From: Augusto Noronha Date: Wed, 8 May 2024 15:51:46 -0700 Subject: [PATCH 084/328] [gardening][DebugInfo][NFC] Improve comment on HashingDISubprogram test (#91543) --- llvm/unittests/IR/DebugInfoTest.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/unittests/IR/DebugInfoTest.cpp b/llvm/unittests/IR/DebugInfoTest.cpp index 8847a5759ad9..cac8acbe15a7 100644 --- a/llvm/unittests/IR/DebugInfoTest.cpp +++ b/llvm/unittests/IR/DebugInfoTest.cpp @@ -1195,8 +1195,9 @@ TEST(MetadataTest, DbgVariableRecordConversionRoutines) { UseNewDbgInfoFormat = OldDbgValueMode; } -// Test that the hashing function for DISubprograms produce the same result -// after replacing the temporary scope. +// Test that the hashing function for DISubprograms representing methods produce +// the same result after replacing their scope (the type containing the +// subprogram) from a temporary DIType with the permanent one. TEST(DIBuilder, HashingDISubprogram) { LLVMContext Ctx; std::unique_ptr M = std::make_unique("MyModule", Ctx); -- GitLab From 2fb377432134b12c3522b1ba8fa35ac4d0f14e1d Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Wed, 8 May 2024 22:55:37 +0000 Subject: [PATCH 085/328] Revert "[SLP]Fix PR91467: Look through scalar cast, when trying to cast to another type." This reverts commit 2475efa91d8b4fa8f1a2d16052cb6d14be7d5dc6. Causes crashes, see comments on https://github.com/llvm/llvm-project/commit/2475efa91d8b4fa8f1a2d16052cb6d14be7d5dc6. --- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 6 +----- .../SLPVectorizer/AArch64/gather-with-minbith-user.ll | 9 ++++++++- .../SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll | 7 ++++++- .../SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll | 3 ++- 4 files changed, 17 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index cc9219ca02cf..98561f9ca044 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -11419,12 +11419,8 @@ Value *BoUpSLP::gather(ArrayRef VL, Value *Root, Type *ScalarTy) { if (Scalar->getType() != Ty) { assert(Scalar->getType()->isIntegerTy() && Ty->isIntegerTy() && "Expected integer types only."); - Value *V = Scalar; - if (auto *CI = dyn_cast(Scalar); - isa_and_nonnull(CI)) - V = CI->getOperand(0); Scalar = Builder.CreateIntCast( - V, Ty, !isKnownNonNegative(Scalar, SimplifyQuery(*DL))); + Scalar, Ty, !isKnownNonNegative(Scalar, SimplifyQuery(*DL))); } Vec = Builder.CreateInsertElement(Vec, Scalar, Builder.getInt32(Pos)); diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll index 3ebe920d1734..76bb882171b1 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll @@ -5,7 +5,14 @@ define void @h() { ; CHECK-LABEL: define void @h() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16 -; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 2 +; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 0 to i1 +; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i1> , i1 [[TMP6]], i32 4 +; CHECK-NEXT: [[TMP1:%.*]] = sub <8 x i1> [[TMP0]], zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = add <8 x i1> [[TMP0]], zeroinitializer +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP2]], <8 x i32> +; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i1> [[TMP3]], zeroinitializer +; CHECK-NEXT: [[TMP4:%.*]] = zext <8 x i1> [[TMP5]] to <8 x i16> +; CHECK-NEXT: store <8 x i16> [[TMP4]], ptr [[ARRAYIDX2]], align 2 ; CHECK-NEXT: ret void ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll index 6404cf4a2cd1..2ab6e919c23b 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll @@ -5,7 +5,12 @@ define void @h() { ; CHECK-LABEL: define void @h() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16 -; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 2 +; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 0 to i1 +; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i1> , i1 [[TMP0]], i32 4 +; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i1> zeroinitializer, [[TMP1]] +; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i1> zeroinitializer, [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = zext <8 x i1> [[TMP3]] to <8 x i16> +; CHECK-NEXT: store <8 x i16> [[TMP4]], ptr [[ARRAYIDX2]], align 2 ; CHECK-NEXT: ret void ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll index 3c8e98485ffc..1bb87bf6205f 100644 --- a/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll +++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll @@ -4,9 +4,10 @@ define void @test(ptr %a, i8 %0, i16 %b.promoted.i) { ; CHECK-LABEL: define void @test( ; CHECK-SAME: ptr [[A:%.*]], i8 [[TMP0:%.*]], i16 [[B_PROMOTED_I:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP0]] to i128 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[B_PROMOTED_I]], i32 0 ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP0]] to i16 +; CHECK-NEXT: [[TMP5:%.*]] = trunc i128 [[TMP2]] to i16 ; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i16> poison, i16 [[TMP5]], i32 0 ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i16> [[TMP6]], <4 x i16> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP4]], [[TMP7]] -- GitLab From c0b5a96ac44a70bdc0b138e117e3fea1b49189f5 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 8 May 2024 15:55:10 -0700 Subject: [PATCH 086/328] [RISCV] Add tests where we could use Zbs instructions in constant materialization. NFC --- llvm/test/CodeGen/RISCV/imm.ll | 116 +++++++++++++++ llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll | 137 ++++++++++++++++++ 2 files changed, 253 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll index 9e356a93526c..6456401dbb86 100644 --- a/llvm/test/CodeGen/RISCV/imm.ll +++ b/llvm/test/CodeGen/RISCV/imm.ll @@ -3994,3 +3994,119 @@ define i64 @imm64_same_lo_hi_negative() nounwind { ; RV64-REMAT-NEXT: ret ret i64 9259542123273814144 ; 0x8080808080808080 } + +define i64 @imm64_0x8000080000000() { +; RV32I-LABEL: imm64_0x8000080000000: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a0, 524288 +; RV32I-NEXT: lui a1, 128 +; RV32I-NEXT: ret +; +; RV64I-LABEL: imm64_0x8000080000000: +; RV64I: # %bb.0: +; RV64I-NEXT: lui a0, 256 +; RV64I-NEXT: addiw a0, a0, 1 +; RV64I-NEXT: slli a0, a0, 31 +; RV64I-NEXT: ret +; +; RV64IZBA-LABEL: imm64_0x8000080000000: +; RV64IZBA: # %bb.0: +; RV64IZBA-NEXT: lui a0, 256 +; RV64IZBA-NEXT: addiw a0, a0, 1 +; RV64IZBA-NEXT: slli a0, a0, 31 +; RV64IZBA-NEXT: ret +; +; RV64IZBB-LABEL: imm64_0x8000080000000: +; RV64IZBB: # %bb.0: +; RV64IZBB-NEXT: lui a0, 256 +; RV64IZBB-NEXT: addiw a0, a0, 1 +; RV64IZBB-NEXT: slli a0, a0, 31 +; RV64IZBB-NEXT: ret +; +; RV64IZBS-LABEL: imm64_0x8000080000000: +; RV64IZBS: # %bb.0: +; RV64IZBS-NEXT: lui a0, 256 +; RV64IZBS-NEXT: addiw a0, a0, 1 +; RV64IZBS-NEXT: slli a0, a0, 31 +; RV64IZBS-NEXT: ret +; +; RV64IXTHEADBB-LABEL: imm64_0x8000080000000: +; RV64IXTHEADBB: # %bb.0: +; RV64IXTHEADBB-NEXT: lui a0, 256 +; RV64IXTHEADBB-NEXT: addiw a0, a0, 1 +; RV64IXTHEADBB-NEXT: slli a0, a0, 31 +; RV64IXTHEADBB-NEXT: ret +; +; RV32-REMAT-LABEL: imm64_0x8000080000000: +; RV32-REMAT: # %bb.0: +; RV32-REMAT-NEXT: lui a0, 524288 +; RV32-REMAT-NEXT: lui a1, 128 +; RV32-REMAT-NEXT: ret +; +; RV64-REMAT-LABEL: imm64_0x8000080000000: +; RV64-REMAT: # %bb.0: +; RV64-REMAT-NEXT: lui a0, 256 +; RV64-REMAT-NEXT: addiw a0, a0, 1 +; RV64-REMAT-NEXT: slli a0, a0, 31 +; RV64-REMAT-NEXT: ret + ret i64 2251801961168896 ; 0x8000080000000 +} + +define i64 @imm64_0x10000100000000() { +; RV32I-LABEL: imm64_0x10000100000000: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a1, 256 +; RV32I-NEXT: addi a1, a1, 1 +; RV32I-NEXT: li a0, 0 +; RV32I-NEXT: ret +; +; RV64I-LABEL: imm64_0x10000100000000: +; RV64I: # %bb.0: +; RV64I-NEXT: lui a0, 256 +; RV64I-NEXT: addi a0, a0, 1 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: ret +; +; RV64IZBA-LABEL: imm64_0x10000100000000: +; RV64IZBA: # %bb.0: +; RV64IZBA-NEXT: lui a0, 256 +; RV64IZBA-NEXT: addi a0, a0, 1 +; RV64IZBA-NEXT: slli a0, a0, 32 +; RV64IZBA-NEXT: ret +; +; RV64IZBB-LABEL: imm64_0x10000100000000: +; RV64IZBB: # %bb.0: +; RV64IZBB-NEXT: lui a0, 256 +; RV64IZBB-NEXT: addi a0, a0, 1 +; RV64IZBB-NEXT: slli a0, a0, 32 +; RV64IZBB-NEXT: ret +; +; RV64IZBS-LABEL: imm64_0x10000100000000: +; RV64IZBS: # %bb.0: +; RV64IZBS-NEXT: lui a0, 256 +; RV64IZBS-NEXT: addi a0, a0, 1 +; RV64IZBS-NEXT: slli a0, a0, 32 +; RV64IZBS-NEXT: ret +; +; RV64IXTHEADBB-LABEL: imm64_0x10000100000000: +; RV64IXTHEADBB: # %bb.0: +; RV64IXTHEADBB-NEXT: lui a0, 256 +; RV64IXTHEADBB-NEXT: addi a0, a0, 1 +; RV64IXTHEADBB-NEXT: slli a0, a0, 32 +; RV64IXTHEADBB-NEXT: ret +; +; RV32-REMAT-LABEL: imm64_0x10000100000000: +; RV32-REMAT: # %bb.0: +; RV32-REMAT-NEXT: lui a1, 256 +; RV32-REMAT-NEXT: addi a1, a1, 1 +; RV32-REMAT-NEXT: li a0, 0 +; RV32-REMAT-NEXT: ret +; +; RV64-REMAT-LABEL: imm64_0x10000100000000: +; RV64-REMAT: # %bb.0: +; RV64-REMAT-NEXT: lui a0, 256 +; RV64-REMAT-NEXT: addi a0, a0, 1 +; RV64-REMAT-NEXT: slli a0, a0, 32 +; RV64-REMAT-NEXT: ret + ret i64 4503603922337792 ; 0x10000100000000 +} diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll index 0ef17ca964db..c5bb7289e448 100644 --- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll +++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll @@ -2562,3 +2562,140 @@ define i64 @imm64_same_lo_hi_optsize() nounwind optsize { ; RV64IXTHEADBB-NEXT: ret ret i64 1157442765409226768 ; 0x0101010101010101 } +; Hi and lo are the same and also negative. +define i64 @imm64_same_lo_hi_negative() nounwind { +; RV64-NOPOOL-LABEL: imm64_same_lo_hi_negative: +; RV64-NOPOOL: # %bb.0: +; RV64-NOPOOL-NEXT: lui a0, 983297 +; RV64-NOPOOL-NEXT: slli a0, a0, 4 +; RV64-NOPOOL-NEXT: addi a0, a0, 257 +; RV64-NOPOOL-NEXT: slli a0, a0, 16 +; RV64-NOPOOL-NEXT: addi a0, a0, 257 +; RV64-NOPOOL-NEXT: slli a0, a0, 15 +; RV64-NOPOOL-NEXT: addi a0, a0, 128 +; RV64-NOPOOL-NEXT: ret +; +; RV64I-POOL-LABEL: imm64_same_lo_hi_negative: +; RV64I-POOL: # %bb.0: +; RV64I-POOL-NEXT: lui a0, %hi(.LCPI65_0) +; RV64I-POOL-NEXT: ld a0, %lo(.LCPI65_0)(a0) +; RV64I-POOL-NEXT: ret +; +; RV64IZBA-LABEL: imm64_same_lo_hi_negative: +; RV64IZBA: # %bb.0: +; RV64IZBA-NEXT: lui a0, 526344 +; RV64IZBA-NEXT: addi a0, a0, 128 +; RV64IZBA-NEXT: slli a1, a0, 32 +; RV64IZBA-NEXT: add.uw a0, a0, a1 +; RV64IZBA-NEXT: ret +; +; RV64IZBB-LABEL: imm64_same_lo_hi_negative: +; RV64IZBB: # %bb.0: +; RV64IZBB-NEXT: lui a0, 983297 +; RV64IZBB-NEXT: slli a0, a0, 4 +; RV64IZBB-NEXT: addi a0, a0, 257 +; RV64IZBB-NEXT: slli a0, a0, 16 +; RV64IZBB-NEXT: addi a0, a0, 257 +; RV64IZBB-NEXT: slli a0, a0, 15 +; RV64IZBB-NEXT: addi a0, a0, 128 +; RV64IZBB-NEXT: ret +; +; RV64IZBS-LABEL: imm64_same_lo_hi_negative: +; RV64IZBS: # %bb.0: +; RV64IZBS-NEXT: lui a0, 983297 +; RV64IZBS-NEXT: slli a0, a0, 4 +; RV64IZBS-NEXT: addi a0, a0, 257 +; RV64IZBS-NEXT: slli a0, a0, 16 +; RV64IZBS-NEXT: addi a0, a0, 257 +; RV64IZBS-NEXT: slli a0, a0, 15 +; RV64IZBS-NEXT: addi a0, a0, 128 +; RV64IZBS-NEXT: ret +; +; RV64IXTHEADBB-LABEL: imm64_same_lo_hi_negative: +; RV64IXTHEADBB: # %bb.0: +; RV64IXTHEADBB-NEXT: lui a0, 983297 +; RV64IXTHEADBB-NEXT: slli a0, a0, 4 +; RV64IXTHEADBB-NEXT: addi a0, a0, 257 +; RV64IXTHEADBB-NEXT: slli a0, a0, 16 +; RV64IXTHEADBB-NEXT: addi a0, a0, 257 +; RV64IXTHEADBB-NEXT: slli a0, a0, 15 +; RV64IXTHEADBB-NEXT: addi a0, a0, 128 +; RV64IXTHEADBB-NEXT: ret + ret i64 9259542123273814144 ; 0x8080808080808080 +} + +define i64 @imm64_0x8000080000000() { +; RV64I-LABEL: imm64_0x8000080000000: +; RV64I: # %bb.0: +; RV64I-NEXT: lui a0, 256 +; RV64I-NEXT: addiw a0, a0, 1 +; RV64I-NEXT: slli a0, a0, 31 +; RV64I-NEXT: ret +; +; RV64IZBA-LABEL: imm64_0x8000080000000: +; RV64IZBA: # %bb.0: +; RV64IZBA-NEXT: lui a0, 256 +; RV64IZBA-NEXT: addiw a0, a0, 1 +; RV64IZBA-NEXT: slli a0, a0, 31 +; RV64IZBA-NEXT: ret +; +; RV64IZBB-LABEL: imm64_0x8000080000000: +; RV64IZBB: # %bb.0: +; RV64IZBB-NEXT: lui a0, 256 +; RV64IZBB-NEXT: addiw a0, a0, 1 +; RV64IZBB-NEXT: slli a0, a0, 31 +; RV64IZBB-NEXT: ret +; +; RV64IZBS-LABEL: imm64_0x8000080000000: +; RV64IZBS: # %bb.0: +; RV64IZBS-NEXT: lui a0, 256 +; RV64IZBS-NEXT: addiw a0, a0, 1 +; RV64IZBS-NEXT: slli a0, a0, 31 +; RV64IZBS-NEXT: ret +; +; RV64IXTHEADBB-LABEL: imm64_0x8000080000000: +; RV64IXTHEADBB: # %bb.0: +; RV64IXTHEADBB-NEXT: lui a0, 256 +; RV64IXTHEADBB-NEXT: addiw a0, a0, 1 +; RV64IXTHEADBB-NEXT: slli a0, a0, 31 +; RV64IXTHEADBB-NEXT: ret + ret i64 2251801961168896 ; 0x8000080000000 +} + +define i64 @imm64_0x10000100000000() { +; RV64I-LABEL: imm64_0x10000100000000: +; RV64I: # %bb.0: +; RV64I-NEXT: lui a0, 256 +; RV64I-NEXT: addi a0, a0, 1 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: ret +; +; RV64IZBA-LABEL: imm64_0x10000100000000: +; RV64IZBA: # %bb.0: +; RV64IZBA-NEXT: lui a0, 256 +; RV64IZBA-NEXT: addi a0, a0, 1 +; RV64IZBA-NEXT: slli a0, a0, 32 +; RV64IZBA-NEXT: ret +; +; RV64IZBB-LABEL: imm64_0x10000100000000: +; RV64IZBB: # %bb.0: +; RV64IZBB-NEXT: lui a0, 256 +; RV64IZBB-NEXT: addi a0, a0, 1 +; RV64IZBB-NEXT: slli a0, a0, 32 +; RV64IZBB-NEXT: ret +; +; RV64IZBS-LABEL: imm64_0x10000100000000: +; RV64IZBS: # %bb.0: +; RV64IZBS-NEXT: lui a0, 256 +; RV64IZBS-NEXT: addi a0, a0, 1 +; RV64IZBS-NEXT: slli a0, a0, 32 +; RV64IZBS-NEXT: ret +; +; RV64IXTHEADBB-LABEL: imm64_0x10000100000000: +; RV64IXTHEADBB: # %bb.0: +; RV64IXTHEADBB-NEXT: lui a0, 256 +; RV64IXTHEADBB-NEXT: addi a0, a0, 1 +; RV64IXTHEADBB-NEXT: slli a0, a0, 32 +; RV64IXTHEADBB-NEXT: ret + ret i64 4503603922337792 ; 0x10000100000000 +} -- GitLab From 36d8b37dfaa95b8b4e21cb8269fefb62e1f59c2f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 8 May 2024 16:20:05 -0700 Subject: [PATCH 087/328] [RISCV] Add another missed Zbs constant materialization test. NFC This can be LI+BCLRI+BCLRI. --- llvm/test/CodeGen/RISCV/imm.ll | 67 +++++++++++++++++++ llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll | 43 ++++++++++++ 2 files changed, 110 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll index 6456401dbb86..0dc5c7ceb500 100644 --- a/llvm/test/CodeGen/RISCV/imm.ll +++ b/llvm/test/CodeGen/RISCV/imm.ll @@ -4110,3 +4110,70 @@ define i64 @imm64_0x10000100000000() { ; RV64-REMAT-NEXT: ret ret i64 4503603922337792 ; 0x10000100000000 } + +define i64 @imm64_0xFF7FFFFF7FFFFFFE() { +; RV32I-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a0, 524288 +; RV32I-NEXT: addi a0, a0, -1 +; RV32I-NEXT: lui a1, 1046528 +; RV32I-NEXT: addi a1, a1, -1 +; RV32I-NEXT: ret +; +; RV64I-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV64I: # %bb.0: +; RV64I-NEXT: lui a0, 1044480 +; RV64I-NEXT: addiw a0, a0, -1 +; RV64I-NEXT: slli a0, a0, 31 +; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: ret +; +; RV64IZBA-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV64IZBA: # %bb.0: +; RV64IZBA-NEXT: lui a0, 1044480 +; RV64IZBA-NEXT: addiw a0, a0, -1 +; RV64IZBA-NEXT: slli a0, a0, 31 +; RV64IZBA-NEXT: addi a0, a0, -1 +; RV64IZBA-NEXT: ret +; +; RV64IZBB-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV64IZBB: # %bb.0: +; RV64IZBB-NEXT: lui a0, 1044480 +; RV64IZBB-NEXT: addiw a0, a0, -1 +; RV64IZBB-NEXT: slli a0, a0, 31 +; RV64IZBB-NEXT: addi a0, a0, -1 +; RV64IZBB-NEXT: ret +; +; RV64IZBS-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV64IZBS: # %bb.0: +; RV64IZBS-NEXT: lui a0, 1044480 +; RV64IZBS-NEXT: addiw a0, a0, -1 +; RV64IZBS-NEXT: slli a0, a0, 31 +; RV64IZBS-NEXT: addi a0, a0, -1 +; RV64IZBS-NEXT: ret +; +; RV64IXTHEADBB-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV64IXTHEADBB: # %bb.0: +; RV64IXTHEADBB-NEXT: lui a0, 1044480 +; RV64IXTHEADBB-NEXT: addiw a0, a0, -1 +; RV64IXTHEADBB-NEXT: slli a0, a0, 31 +; RV64IXTHEADBB-NEXT: addi a0, a0, -1 +; RV64IXTHEADBB-NEXT: ret +; +; RV32-REMAT-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV32-REMAT: # %bb.0: +; RV32-REMAT-NEXT: lui a0, 524288 +; RV32-REMAT-NEXT: addi a0, a0, -1 +; RV32-REMAT-NEXT: lui a1, 1046528 +; RV32-REMAT-NEXT: addi a1, a1, -1 +; RV32-REMAT-NEXT: ret +; +; RV64-REMAT-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV64-REMAT: # %bb.0: +; RV64-REMAT-NEXT: lui a0, 1044480 +; RV64-REMAT-NEXT: addiw a0, a0, -1 +; RV64-REMAT-NEXT: slli a0, a0, 31 +; RV64-REMAT-NEXT: addi a0, a0, -1 +; RV64-REMAT-NEXT: ret + ret i64 -36028799166447617 ; 0xFF7FFFFF7FFFFFFE +} diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll index c5bb7289e448..bac4bb9ce6f1 100644 --- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll +++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll @@ -2699,3 +2699,46 @@ define i64 @imm64_0x10000100000000() { ; RV64IXTHEADBB-NEXT: ret ret i64 4503603922337792 ; 0x10000100000000 } + +define i64 @imm64_0xFF7FFFFF7FFFFFFE() { +; RV64I-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV64I: # %bb.0: +; RV64I-NEXT: lui a0, 1044480 +; RV64I-NEXT: addiw a0, a0, -1 +; RV64I-NEXT: slli a0, a0, 31 +; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: ret +; +; RV64IZBA-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV64IZBA: # %bb.0: +; RV64IZBA-NEXT: lui a0, 1044480 +; RV64IZBA-NEXT: addiw a0, a0, -1 +; RV64IZBA-NEXT: slli a0, a0, 31 +; RV64IZBA-NEXT: addi a0, a0, -1 +; RV64IZBA-NEXT: ret +; +; RV64IZBB-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV64IZBB: # %bb.0: +; RV64IZBB-NEXT: lui a0, 1044480 +; RV64IZBB-NEXT: addiw a0, a0, -1 +; RV64IZBB-NEXT: slli a0, a0, 31 +; RV64IZBB-NEXT: addi a0, a0, -1 +; RV64IZBB-NEXT: ret +; +; RV64IZBS-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV64IZBS: # %bb.0: +; RV64IZBS-NEXT: lui a0, 1044480 +; RV64IZBS-NEXT: addiw a0, a0, -1 +; RV64IZBS-NEXT: slli a0, a0, 31 +; RV64IZBS-NEXT: addi a0, a0, -1 +; RV64IZBS-NEXT: ret +; +; RV64IXTHEADBB-LABEL: imm64_0xFF7FFFFF7FFFFFFE: +; RV64IXTHEADBB: # %bb.0: +; RV64IXTHEADBB-NEXT: lui a0, 1044480 +; RV64IXTHEADBB-NEXT: addiw a0, a0, -1 +; RV64IXTHEADBB-NEXT: slli a0, a0, 31 +; RV64IXTHEADBB-NEXT: addi a0, a0, -1 +; RV64IXTHEADBB-NEXT: ret + ret i64 -36028799166447617 ; 0xFF7FFFFF7FFFFFFE +} -- GitLab From 1710c8cf0f8def4984893e9dd646579de5528d95 Mon Sep 17 00:00:00 2001 From: Slava Zakharin Date: Wed, 8 May 2024 16:48:14 -0700 Subject: [PATCH 088/328] [flang] Lowering changes for assigning dummy_scope to hlfir.declare. (#90989) The lowering produces fir.dummy_scope operation if the current function has dummy arguments. Each hlfir.declare generated for a dummy argument is then using the result of fir.dummy_scope as its dummy_scope operand. This is only done for HLFIR. I was not able to find a reliable way to identify dummy symbols in `genDeclareSymbol`, so I added a set of registered dummy symbols that is alive during the variables instantiation for the current function. The set is initialized during the mapping of the dummy argument symbols to their MLIR values. It is reset right after all variables are instantiated - this is done to avoid generating hlfir.declare operations with dummy_scope for the clones of the dummy symbols (e.g. this happens with OpenMP privatization). If this can be done in a cleaner way, please advise. --- flang/include/flang/Lower/AbstractConverter.h | 12 ++ .../flang/Optimizer/Builder/HLFIRTools.h | 1 + .../include/flang/Optimizer/HLFIR/HLFIROps.td | 1 + flang/lib/Lower/Bridge.cpp | 73 +++++++++++-- flang/lib/Lower/ConvertArrayConstructor.cpp | 2 +- flang/lib/Lower/ConvertExprToHLFIR.cpp | 3 +- flang/lib/Lower/ConvertVariable.cpp | 20 +++- flang/lib/Lower/OpenACC.cpp | 22 ++-- flang/lib/Lower/OpenMP/ClauseProcessor.cpp | 12 +- flang/lib/Optimizer/Builder/HLFIRTools.cpp | 19 ++-- .../Optimizer/Builder/TemporaryStorage.cpp | 3 +- flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp | 4 +- .../HLFIR/Transforms/BufferizeHLFIR.cpp | 15 +-- flang/test/Fir/dispatch.f90 | 2 +- flang/test/HLFIR/assumed-type-actual-args.f90 | 30 +++-- .../assumed_shape_with_value_keyword.f90 | 20 ++-- flang/test/HLFIR/boxchar_emboxing.f90 | 4 +- flang/test/HLFIR/c_ptr_byvalue.f90 | 3 +- flang/test/HLFIR/call_with_poly_dummy.f90 | 3 +- flang/test/HLFIR/optional_dummy.f90 | 2 +- .../order_assignments/where-scheduling.f90 | 10 +- flang/test/Lower/CUDA/cuda-data-attribute.cuf | 8 +- .../HLFIR/actual_target_for_dummy_pointer.f90 | 22 ++-- .../allocatable-and-pointer-status-change.f90 | 12 +- .../Lower/HLFIR/allocatables-and-pointers.f90 | 18 +-- .../HLFIR/array-ctor-as-elemental-nested.f90 | 4 +- .../Lower/HLFIR/array-ctor-as-elemental.f90 | 11 +- .../HLFIR/array-ctor-as-inlined-temp.f90 | 12 +- flang/test/Lower/HLFIR/array-ctor-index.f90 | 8 +- .../Lower/HLFIR/assignment-intrinsics.f90 | 46 ++++---- .../HLFIR/assumed-rank-iface-alloc-ptr.f90 | 10 +- flang/test/Lower/HLFIR/assumed-rank-iface.f90 | 18 +-- flang/test/Lower/HLFIR/binary-ops.f90 | 84 +++++++------- .../test/Lower/HLFIR/bindc-value-derived.f90 | 4 +- .../call-sequence-associated-descriptors.f90 | 16 +-- .../test/Lower/HLFIR/calls-assumed-shape.f90 | 14 +-- .../Lower/HLFIR/calls-constant-expr-arg.f90 | 4 +- flang/test/Lower/HLFIR/calls-f77.f90 | 14 +-- flang/test/Lower/HLFIR/calls-optional.f90 | 14 +-- .../Lower/HLFIR/calls-percent-val-ref.f90 | 12 +- .../HLFIR/calls-poly-to-assumed-type.f90 | 2 +- flang/test/Lower/HLFIR/char_extremum.f03 | 40 +++---- flang/test/Lower/HLFIR/charconvert.f90 | 8 +- .../Lower/HLFIR/convert-mbox-to-value.f90 | 16 +-- .../Lower/HLFIR/convert-variable-block.f90 | 2 +- flang/test/Lower/HLFIR/convert-variable.f90 | 20 ++-- flang/test/Lower/HLFIR/cray-pointers.f90 | 10 +- flang/test/Lower/HLFIR/custom-intrinsic.f90 | 103 +++++++++--------- .../Lower/HLFIR/designators-component-ref.f90 | 8 +- flang/test/Lower/HLFIR/designators.f90 | 42 +++---- flang/test/Lower/HLFIR/dot_product.f90 | 4 +- .../test/Lower/HLFIR/elemental-array-ops.f90 | 12 +- .../HLFIR/elemental-polymorphic-merge.f90 | 8 +- .../HLFIR/elemental-user-procedure-ref.f90 | 6 +- flang/test/Lower/HLFIR/expr-addr.f90 | 2 +- flang/test/Lower/HLFIR/expr-box.f90 | 2 +- flang/test/Lower/HLFIR/expr-value.f90 | 2 +- .../ignore-rank-unlimited-polymorphic.f90 | 10 +- .../Lower/HLFIR/implicit-type-conversion.f90 | 28 ++--- .../intentout-allocatable-components.f90 | 4 +- .../test/Lower/HLFIR/internal-procedures.f90 | 2 +- .../HLFIR/intrinsic-dynamically-optional.f90 | 4 +- flang/test/Lower/HLFIR/issue80884.f90 | 4 +- flang/test/Lower/HLFIR/maxloc.f90 | 11 +- flang/test/Lower/HLFIR/minloc.f90 | 11 +- flang/test/Lower/HLFIR/procedure-pointer.f90 | 6 +- .../test/Lower/HLFIR/statement-functions.f90 | 2 +- .../Lower/HLFIR/structure-constructor.f90 | 16 +-- flang/test/Lower/HLFIR/transformational.f90 | 2 +- flang/test/Lower/HLFIR/transpose.f90 | 10 +- flang/test/Lower/HLFIR/unary-ops.f90 | 12 +- .../Lower/HLFIR/user-defined-assignment.f90 | 38 +++---- .../Lower/HLFIR/vector-subscript-as-value.f90 | 6 +- .../Intrinsics/associated-proc-pointers.f90 | 12 +- .../test/Lower/Intrinsics/c_f_procpointer.f90 | 8 +- .../Intrinsics/c_funloc-proc-pointers.f90 | 4 +- flang/test/Lower/Intrinsics/c_ptr_eq_ne.f90 | 8 +- .../execute_command_line-optional.f90 | 11 +- .../Lower/Intrinsics/execute_command_line.f90 | 16 +-- flang/test/Lower/Intrinsics/ieee_logb.f90 | 2 +- flang/test/Lower/Intrinsics/product.f90 | 2 +- flang/test/Lower/Intrinsics/signal.f90 | 2 +- flang/test/Lower/Intrinsics/sizeof.f90 | 4 +- flang/test/Lower/Intrinsics/sum.f90 | 2 +- .../test/Lower/Intrinsics/system-optional.f90 | 5 +- flang/test/Lower/Intrinsics/system.f90 | 10 +- .../Lower/OpenACC/acc-atomic-update-array.f90 | 18 +-- flang/test/Lower/OpenACC/acc-bounds.f90 | 12 +- flang/test/Lower/OpenACC/acc-declare.f90 | 18 +-- flang/test/Lower/OpenACC/acc-loop-exit.f90 | 6 +- flang/test/Lower/OpenACC/acc-private.f90 | 10 +- flang/test/Lower/OpenACC/acc-reduction.f90 | 10 +- .../Lower/OpenMP/allocatable-array-bounds.f90 | 2 +- flang/test/Lower/OpenMP/array-bounds.f90 | 4 +- flang/test/Lower/OpenMP/flush.f90 | 14 +-- .../parallel-firstprivate-clause-scalar.f90 | 42 +++---- .../parallel-lastprivate-clause-scalar.f90 | 18 +-- .../OpenMP/parallel-private-clause-fixes.f90 | 6 +- .../OpenMP/parallel-private-clause-str.f90 | 4 +- .../test/Lower/OpenMP/parallel-reduction3.f90 | 2 +- .../OpenMP/parallel-wsloop-firstpriv.f90 | 6 +- flang/test/Lower/OpenMP/parallel-wsloop.f90 | 22 ++-- flang/test/Lower/OpenMP/sections.f90 | 2 +- flang/test/Lower/OpenMP/simd.f90 | 14 +-- flang/test/Lower/OpenMP/single.f90 | 12 +- flang/test/Lower/OpenMP/target.f90 | 4 +- .../wsloop-reduction-array-assumed-shape.f90 | 2 +- .../OpenMP/wsloop-reduction-iand-byref.f90 | 2 +- .../Lower/OpenMP/wsloop-reduction-iand.f90 | 2 +- .../OpenMP/wsloop-reduction-ieor-byref.f90 | 2 +- .../Lower/OpenMP/wsloop-reduction-ieor.f90 | 2 +- .../OpenMP/wsloop-reduction-ior-byref.f90 | 2 +- .../Lower/OpenMP/wsloop-reduction-ior.f90 | 2 +- .../wsloop-reduction-logical-and-byref.f90 | 6 +- .../OpenMP/wsloop-reduction-logical-and.f90 | 6 +- .../wsloop-reduction-logical-eqv-byref.f90 | 6 +- .../OpenMP/wsloop-reduction-logical-eqv.f90 | 6 +- .../wsloop-reduction-logical-neqv-byref.f90 | 6 +- .../OpenMP/wsloop-reduction-logical-neqv.f90 | 6 +- .../wsloop-reduction-logical-or-byref.f90 | 6 +- .../OpenMP/wsloop-reduction-logical-or.f90 | 6 +- .../OpenMP/wsloop-reduction-max-byref.f90 | 4 +- .../wsloop-reduction-max-hlfir-byref.f90 | 2 +- .../OpenMP/wsloop-reduction-max-hlfir.f90 | 2 +- .../Lower/OpenMP/wsloop-reduction-max.f90 | 4 +- .../OpenMP/wsloop-reduction-min-byref.f90 | 4 +- .../Lower/OpenMP/wsloop-reduction-min.f90 | 4 +- flang/test/Lower/allocatable-polymorphic.f90 | 6 +- flang/test/Lower/array-expression.f90 | 2 +- flang/test/Lower/character-substrings.f90 | 4 +- flang/test/Lower/charconvert.f90 | 8 +- flang/test/Lower/dispatch.f90 | 30 ++--- flang/test/Lower/do_loop.f90 | 1 + flang/test/Lower/pointer-references.f90 | 2 +- flang/test/Lower/polymorphic.f90 | 2 +- flang/test/Lower/select-type.f90 | 2 +- .../structure-constructors-alloc-comp.f90 | 6 +- 137 files changed, 806 insertions(+), 696 deletions(-) diff --git a/flang/include/flang/Lower/AbstractConverter.h b/flang/include/flang/Lower/AbstractConverter.h index 1cb6bcb1f5d2..0bc68de6938d 100644 --- a/flang/include/flang/Lower/AbstractConverter.h +++ b/flang/include/flang/Lower/AbstractConverter.h @@ -219,6 +219,18 @@ public: /// function. virtual void bindHostAssocTuple(mlir::Value val) = 0; + /// Returns fir.dummy_scope operation's result value to be used + /// as dummy_scope operand of hlfir.declare operations for the dummy + /// arguments of this function. + virtual mlir::Value dummyArgsScopeValue() const = 0; + + /// Returns true if the given symbol is a dummy argument of this function. + /// Note that it returns false for all the symbols after all the variables + /// are instantiated for this function, i.e. it can only be used reliably + /// during the instatiation of the variables. + virtual bool + isRegisteredDummySymbol(Fortran::semantics::SymbolRef symRef) const = 0; + //===--------------------------------------------------------------------===// // Types //===--------------------------------------------------------------------===// diff --git a/flang/include/flang/Optimizer/Builder/HLFIRTools.h b/flang/include/flang/Optimizer/Builder/HLFIRTools.h index cf7df38b1cdf..6cc8e71b3b18 100644 --- a/flang/include/flang/Optimizer/Builder/HLFIRTools.h +++ b/flang/include/flang/Optimizer/Builder/HLFIRTools.h @@ -238,6 +238,7 @@ fir::FortranVariableOpInterface genDeclare(mlir::Location loc, fir::FirOpBuilder &builder, const fir::ExtendedValue &exv, llvm::StringRef name, fir::FortranVariableFlagsAttr flags, + mlir::Value dummyScope = nullptr, fir::CUDADataAttributeAttr cudaAttr = {}); /// Generate an hlfir.associate to build a variable from an expression value. diff --git a/flang/include/flang/Optimizer/HLFIR/HLFIROps.td b/flang/include/flang/Optimizer/HLFIR/HLFIROps.td index ee3c26800ae3..9558a6832972 100644 --- a/flang/include/flang/Optimizer/HLFIR/HLFIROps.td +++ b/flang/include/flang/Optimizer/HLFIR/HLFIROps.td @@ -104,6 +104,7 @@ def hlfir_DeclareOp : hlfir_Op<"declare", [AttrSizedOperandSegments, let builders = [ OpBuilder<(ins "mlir::Value":$memref, "llvm::StringRef":$uniq_name, CArg<"mlir::Value", "{}">:$shape, CArg<"mlir::ValueRange", "{}">:$typeparams, + CArg<"mlir::Value", "{}">:$dummy_scope, CArg<"fir::FortranVariableFlagsAttr", "{}">:$fortran_attrs, CArg<"fir::CUDADataAttributeAttr", "{}">:$cuda_attr)>]; diff --git a/flang/lib/Lower/Bridge.cpp b/flang/lib/Lower/Bridge.cpp index b0fc26332651..4902886712e9 100644 --- a/flang/lib/Lower/Bridge.cpp +++ b/flang/lib/Lower/Bridge.cpp @@ -900,6 +900,16 @@ public: hostAssocTuple = val; } + mlir::Value dummyArgsScopeValue() const override final { + return dummyArgsScope; + } + + bool isRegisteredDummySymbol( + Fortran::semantics::SymbolRef symRef) const override final { + auto *sym = &*symRef; + return registeredDummySymbols.contains(sym); + } + void registerTypeInfo(mlir::Location loc, Fortran::lower::SymbolRef typeInfoSym, const Fortran::semantics::DerivedTypeSpec &typeSpec, @@ -1145,10 +1155,11 @@ private: /// yet. The final mapping will be done using this pre-mapping in /// Fortran::lower::mapSymbolAttributes. bool mapBlockArgToDummyOrResult(const Fortran::semantics::SymbolRef sym, - mlir::Value val, bool forced = false) { - if (!forced && lookupSymbol(sym)) - return false; - localSymbols.addSymbol(sym, val, forced); + mlir::Value val, bool isResult) { + localSymbols.addSymbol(sym, val); + if (!isResult) + registerDummySymbol(sym); + return true; } @@ -4559,7 +4570,7 @@ private: const Fortran::lower::CalleeInterface &callee) { assert(builder && "require a builder object at this point"); using PassBy = Fortran::lower::CalleeInterface::PassEntityBy; - auto mapPassedEntity = [&](const auto arg) { + auto mapPassedEntity = [&](const auto arg, bool isResult = false) { if (arg.passBy == PassBy::AddressAndLength) { if (callee.characterize().IsBindC()) return; @@ -4569,10 +4580,11 @@ private: fir::factory::CharacterExprHelper charHelp{*builder, loc}; mlir::Value box = charHelp.createEmboxChar(arg.firArgument, arg.firLength); - mapBlockArgToDummyOrResult(arg.entity->get(), box); + mapBlockArgToDummyOrResult(arg.entity->get(), box, isResult); } else { if (arg.entity.has_value()) { - mapBlockArgToDummyOrResult(arg.entity->get(), arg.firArgument); + mapBlockArgToDummyOrResult(arg.entity->get(), arg.firArgument, + isResult); } else { assert(funit.parentHasTupleHostAssoc() && "expect tuple argument"); } @@ -4581,15 +4593,19 @@ private: for (const Fortran::lower::CalleeInterface::PassedEntity &arg : callee.getPassedArguments()) mapPassedEntity(arg); + if (lowerToHighLevelFIR() && !callee.getPassedArguments().empty()) { + mlir::Value scopeOp = builder->create(toLocation()); + setDummyArgsScope(scopeOp); + } if (std::optional passedResult = callee.getPassedResult()) { - mapPassedEntity(*passedResult); + mapPassedEntity(*passedResult, /*isResult=*/true); // FIXME: need to make sure things are OK here. addSymbol may not be OK if (funit.primaryResult && passedResult->entity->get() != *funit.primaryResult) mapBlockArgToDummyOrResult( - *funit.primaryResult, - getSymbolAddress(passedResult->entity->get())); + *funit.primaryResult, getSymbolAddress(passedResult->entity->get()), + /*isResult=*/true); } } @@ -4766,7 +4782,8 @@ private: Fortran::lower::StatementContext stmtCtx; if (std::optional passedResult = callee.getPassedResult()) { - mapBlockArgToDummyOrResult(altResult.getSymbol(), resultArg.getAddr()); + mapBlockArgToDummyOrResult(altResult.getSymbol(), resultArg.getAddr(), + /*isResult=*/true); Fortran::lower::mapSymbolAttributes(*this, altResult, localSymbols, stmtCtx); } else { @@ -4810,6 +4827,11 @@ private: if (!funit.getHostAssoc().empty()) funit.getHostAssoc().hostProcedureBindings(*this, localSymbols); + // Unregister all dummy symbols, so that their cloning (e.g. for OpenMP + // privatization) does not create the cloned hlfir.declare operations + // with dummy_scope operands. + resetRegisteredDummySymbols(); + // Create most function blocks in advance. createEmptyBlocks(funit.evaluationList); @@ -4929,6 +4951,8 @@ private: hostAssocTuple = mlir::Value{}; localSymbols.clear(); blockId = 0; + dummyArgsScope = mlir::Value{}; + resetRegisteredDummySymbols(); } /// Helper to generate GlobalOps when the builder is not positioned in any @@ -4957,6 +4981,7 @@ private: delete builder; builder = nullptr; localSymbols.clear(); + resetRegisteredDummySymbols(); } /// Instantiate the data from a BLOCK DATA unit. @@ -5374,6 +5399,23 @@ private: globalOmpRequiresSymbol); } + /// Record fir.dummy_scope operation for this function. + /// It will be used to set dummy_scope operand of the hlfir.declare + /// operations. + void setDummyArgsScope(mlir::Value val) { + assert(!dummyArgsScope && val); + dummyArgsScope = val; + } + + /// Record the given symbol as a dummy argument of this function. + void registerDummySymbol(Fortran::semantics::SymbolRef symRef) { + auto *sym = &*symRef; + registeredDummySymbols.insert(sym); + } + + /// Reset all registered dummy symbols. + void resetRegisteredDummySymbols() { registeredDummySymbols.clear(); } + //===--------------------------------------------------------------------===// Fortran::lower::LoweringBridge &bridge; @@ -5400,6 +5442,15 @@ private: /// Tuple of host associated variables mlir::Value hostAssocTuple; + /// Value of fir.dummy_scope operation for this function. + mlir::Value dummyArgsScope; + + /// A set of dummy argument symbols for this function. + /// The set is only preserved during the instatiation + /// of variables for this function. + llvm::SmallPtrSet + registeredDummySymbols; + /// A map of unique names for constant expressions. /// The names are used for representing the constant expressions /// with global constant initialized objects. diff --git a/flang/lib/Lower/ConvertArrayConstructor.cpp b/flang/lib/Lower/ConvertArrayConstructor.cpp index a5b5838fe6b6..341fad9a5e43 100644 --- a/flang/lib/Lower/ConvertArrayConstructor.cpp +++ b/flang/lib/Lower/ConvertArrayConstructor.cpp @@ -318,7 +318,7 @@ public: mlir::Value shape = builder.genShape(loc, extents); declare = builder.create( loc, tempStorage, tempName, shape, lengths, - fir::FortranVariableFlagsAttr{}); + /*dummy_scope=*/nullptr, fir::FortranVariableFlagsAttr{}); initialBoxValue = builder.createBox(loc, boxType, declare->getOriginalBase(), shape, /*slice=*/mlir::Value{}, lengths, /*tdesc=*/{}); diff --git a/flang/lib/Lower/ConvertExprToHLFIR.cpp b/flang/lib/Lower/ConvertExprToHLFIR.cpp index 93bdf650f9ff..3c305955520e 100644 --- a/flang/lib/Lower/ConvertExprToHLFIR.cpp +++ b/flang/lib/Lower/ConvertExprToHLFIR.cpp @@ -1676,7 +1676,8 @@ private: mlir::Value storagePtr = builder.createTemporary(loc, recTy); auto varOp = hlfir::EntityWithAttributes{builder.create( loc, storagePtr, "ctor.temp", /*shape=*/nullptr, - /*typeparams=*/mlir::ValueRange{}, fir::FortranVariableFlagsAttr{})}; + /*typeparams=*/mlir::ValueRange{}, /*dummy_scope=*/nullptr, + fir::FortranVariableFlagsAttr{})}; // Initialize any components that need initialization. mlir::Value box = builder.createBox(loc, fir::ExtendedValue{varOp}); diff --git a/flang/lib/Lower/ConvertVariable.cpp b/flang/lib/Lower/ConvertVariable.cpp index f31fbab41028..5ddd8a6a9d41 100644 --- a/flang/lib/Lower/ConvertVariable.cpp +++ b/flang/lib/Lower/ConvertVariable.cpp @@ -1683,7 +1683,8 @@ static void genDeclareSymbol(Fortran::lower::AbstractConverter &converter, // Declare a local pointer variable. auto newBase = builder.create( - loc, boxAlloc, name, /*shape=*/nullptr, lenParams, attributes); + loc, boxAlloc, name, /*shape=*/nullptr, lenParams, + /*dummy_scope=*/nullptr, attributes); mlir::Value nullAddr = builder.createNullConstant( loc, llvm::cast(ptrBoxType).getEleTy()); @@ -1710,8 +1711,12 @@ static void genDeclareSymbol(Fortran::lower::AbstractConverter &converter, symMap.addVariableDefinition(sym, newBase, force); return; } + mlir::Value dummyScope; + if (converter.isRegisteredDummySymbol(sym)) + dummyScope = converter.dummyArgsScopeValue(); auto newBase = builder.create( - loc, base, name, shapeOrShift, lenParams, attributes, cudaAttr); + loc, base, name, shapeOrShift, lenParams, dummyScope, attributes, + cudaAttr); symMap.addVariableDefinition(sym, newBase, force); return; } @@ -1761,8 +1766,11 @@ void Fortran::lower::genDeclareSymbol( Fortran::lower::translateSymbolCUDADataAttribute(builder.getContext(), sym.GetUltimate()); auto name = converter.mangleName(sym); - hlfir::EntityWithAttributes declare = - hlfir::genDeclare(loc, builder, exv, name, attributes, cudaAttr); + mlir::Value dummyScope; + if (converter.isRegisteredDummySymbol(sym)) + dummyScope = converter.dummyArgsScopeValue(); + hlfir::EntityWithAttributes declare = hlfir::genDeclare( + loc, builder, exv, name, attributes, dummyScope, cudaAttr); symMap.addVariableDefinition(sym, declare.getIfVariableInterface(), force); return; } @@ -2022,7 +2030,9 @@ void Fortran::lower::mapSymbolAttributes( fir::factory::genMutableBoxRead( builder, loc, fir::factory::createTempMutableBox(builder, loc, ty, {}, {}, - isPolymorphic))); + isPolymorphic)), + fir::FortranVariableFlagsEnum::None, + converter.isRegisteredDummySymbol(sym)); return true; } return false; diff --git a/flang/lib/Lower/OpenACC.cpp b/flang/lib/Lower/OpenACC.cpp index eae2afc760e6..b02e7be75d20 100644 --- a/flang/lib/Lower/OpenACC.cpp +++ b/flang/lib/Lower/OpenACC.cpp @@ -425,7 +425,8 @@ static void genPrivateLikeInitRegion(mlir::OpBuilder &builder, RecipeOp recipe, auto alloca = builder.create(loc, refTy.getEleTy()); auto declareOp = builder.create( loc, alloca, accPrivateInitName, /*shape=*/nullptr, - llvm::ArrayRef{}, fir::FortranVariableFlagsAttr{}); + llvm::ArrayRef{}, /*dummy_scope=*/nullptr, + fir::FortranVariableFlagsAttr{}); retVal = declareOp.getBase(); } else if (auto seqTy = mlir::dyn_cast_or_null( refTy.getEleTy())) { @@ -446,7 +447,8 @@ static void genPrivateLikeInitRegion(mlir::OpBuilder &builder, RecipeOp recipe, loc, seqTy, /*typeparams=*/mlir::ValueRange{}, extents); auto declareOp = builder.create( loc, alloca, accPrivateInitName, shape, - llvm::ArrayRef{}, fir::FortranVariableFlagsAttr{}); + llvm::ArrayRef{}, /*dummy_scope=*/nullptr, + fir::FortranVariableFlagsAttr{}); retVal = declareOp.getBase(); } } @@ -666,10 +668,12 @@ mlir::acc::FirstprivateRecipeOp Fortran::lower::createOrGetFirstprivateRecipe( auto leftDeclOp = builder.create( loc, recipe.getCopyRegion().getArgument(0), llvm::StringRef{}, shape, - llvm::ArrayRef{}, fir::FortranVariableFlagsAttr{}); + llvm::ArrayRef{}, /*dummy_scope=*/nullptr, + fir::FortranVariableFlagsAttr{}); auto rightDeclOp = builder.create( loc, recipe.getCopyRegion().getArgument(1), llvm::StringRef{}, shape, - llvm::ArrayRef{}, fir::FortranVariableFlagsAttr{}); + llvm::ArrayRef{}, /*dummy_scope=*/nullptr, + fir::FortranVariableFlagsAttr{}); hlfir::DesignateOp::Subscripts triplets = getSubscriptsFromArgs(recipe.getCopyRegion().getArguments()); @@ -975,7 +979,8 @@ static mlir::Value genReductionInitRegion(fir::FirOpBuilder &builder, mlir::Value alloca = builder.create(loc, ty); auto declareOp = builder.create( loc, alloca, accReductionInitName, /*shape=*/nullptr, - llvm::ArrayRef{}, fir::FortranVariableFlagsAttr{}); + llvm::ArrayRef{}, /*dummy_scope=*/nullptr, + fir::FortranVariableFlagsAttr{}); builder.create(loc, builder.createConvert(loc, ty, initValue), declareOp.getBase()); return declareOp.getBase(); @@ -991,7 +996,8 @@ static mlir::Value genReductionInitRegion(fir::FirOpBuilder &builder, loc, seqTy, /*typeparams=*/mlir::ValueRange{}, extents); auto declareOp = builder.create( loc, alloca, accReductionInitName, shape, - llvm::ArrayRef{}, fir::FortranVariableFlagsAttr{}); + llvm::ArrayRef{}, /*dummy_scope=*/nullptr, + fir::FortranVariableFlagsAttr{}); mlir::Type idxTy = builder.getIndexType(); mlir::Type refTy = fir::ReferenceType::get(seqTy.getEleTy()); llvm::SmallVector loops; @@ -1143,10 +1149,10 @@ static void genCombiner(fir::FirOpBuilder &builder, mlir::Location loc, recipe.getCombinerRegion().getArguments()); auto v1DeclareOp = builder.create( loc, value1, llvm::StringRef{}, shape, llvm::ArrayRef{}, - fir::FortranVariableFlagsAttr{}); + /*dummy_scope=*/nullptr, fir::FortranVariableFlagsAttr{}); auto v2DeclareOp = builder.create( loc, value2, llvm::StringRef{}, shape, llvm::ArrayRef{}, - fir::FortranVariableFlagsAttr{}); + /*dummy_scope=*/nullptr, fir::FortranVariableFlagsAttr{}); hlfir::DesignateOp::Subscripts triplets = getTripletsFromArgs(recipe); llvm::SmallVector lenParamsLeft; diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp index bb83e8d5e788..b7198c951c8f 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp @@ -657,12 +657,12 @@ createCopyFunc(mlir::Location loc, Fortran::lower::AbstractConverter &converter, builder.createIntegerConstant(loc, builder.getIndexType(), extent)); shape = builder.create(loc, extents); } - auto declDst = builder.create(loc, funcOp.getArgument(0), - copyFuncName + "_dst", shape, - typeparams, attrs); - auto declSrc = builder.create(loc, funcOp.getArgument(1), - copyFuncName + "_src", shape, - typeparams, attrs); + auto declDst = builder.create( + loc, funcOp.getArgument(0), copyFuncName + "_dst", shape, typeparams, + /*dummy_scope=*/nullptr, attrs); + auto declSrc = builder.create( + loc, funcOp.getArgument(1), copyFuncName + "_src", shape, typeparams, + /*dummy_scope=*/nullptr, attrs); converter.copyVar(loc, declDst.getBase(), declSrc.getBase()); builder.create(loc); return funcOp; diff --git a/flang/lib/Optimizer/Builder/HLFIRTools.cpp b/flang/lib/Optimizer/Builder/HLFIRTools.cpp index b32c3e50647e..8fdab2a57181 100644 --- a/flang/lib/Optimizer/Builder/HLFIRTools.cpp +++ b/flang/lib/Optimizer/Builder/HLFIRTools.cpp @@ -198,7 +198,7 @@ mlir::Value hlfir::Entity::getFirBase() const { fir::FortranVariableOpInterface hlfir::genDeclare(mlir::Location loc, fir::FirOpBuilder &builder, const fir::ExtendedValue &exv, llvm::StringRef name, - fir::FortranVariableFlagsAttr flags, + fir::FortranVariableFlagsAttr flags, mlir::Value dummyScope, fir::CUDADataAttributeAttr cudaAttr) { mlir::Value base = fir::getBase(exv); @@ -229,7 +229,7 @@ hlfir::genDeclare(mlir::Location loc, fir::FirOpBuilder &builder, }, [](const auto &) {}); auto declareOp = builder.create( - loc, base, name, shapeOrShift, lenParams, flags, cudaAttr); + loc, base, name, shapeOrShift, lenParams, dummyScope, flags, cudaAttr); return mlir::cast(declareOp.getOperation()); } @@ -1096,8 +1096,9 @@ hlfir::createTempFromMold(mlir::Location loc, fir::FirOpBuilder &builder, /*shape=*/std::nullopt, lenParams); isHeapAlloc = builder.createBool(loc, false); } - auto declareOp = builder.create(loc, alloc, tmpName, shape, - lenParams, declAttrs); + auto declareOp = + builder.create(loc, alloc, tmpName, shape, lenParams, + /*dummy_scope=*/nullptr, declAttrs); if (mold.isPolymorphic()) { int rank = mold.getRank(); // TODO: should probably read rank from the mold. @@ -1134,8 +1135,9 @@ hlfir::Entity hlfir::createStackTempFromMold(mlir::Location loc, alloc = builder.createTemporary(loc, mold.getFortranElementType(), tmpName, /*shape=*/std::nullopt, lenParams); } - auto declareOp = builder.create(loc, alloc, tmpName, shape, - lenParams, declAttrs); + auto declareOp = + builder.create(loc, alloc, tmpName, shape, lenParams, + /*dummy_scope=*/nullptr, declAttrs); return hlfir::Entity{declareOp.getBase()}; } @@ -1153,7 +1155,7 @@ hlfir::convertCharacterKind(mlir::Location loc, fir::FirOpBuilder &builder, return hlfir::EntityWithAttributes{builder.create( loc, res.getAddr(), ".temp.kindconvert", /*shape=*/nullptr, /*typeparams=*/mlir::ValueRange{res.getLen()}, - fir::FortranVariableFlagsAttr{})}; + /*dummy_scope=*/nullptr, fir::FortranVariableFlagsAttr{})}; } std::pair> @@ -1225,7 +1227,8 @@ hlfir::genTypeAndKindConvert(mlir::Location loc, fir::FirOpBuilder &builder, builder.create(loc, shapeShiftType, lbAndExtents); auto declareOp = builder.create( loc, associate.getFirBase(), *associate.getUniqName(), shapeShift, - associate.getTypeparams(), /*flags=*/fir::FortranVariableFlagsAttr{}); + associate.getTypeparams(), /*dummy_scope=*/nullptr, + /*flags=*/fir::FortranVariableFlagsAttr{}); hlfir::Entity castWithLbounds = mlir::cast(declareOp.getOperation()); fir::FirOpBuilder *bldr = &builder; diff --git a/flang/lib/Optimizer/Builder/TemporaryStorage.cpp b/flang/lib/Optimizer/Builder/TemporaryStorage.cpp index dbc285ce9e22..d34dad52c28b 100644 --- a/flang/lib/Optimizer/Builder/TemporaryStorage.cpp +++ b/flang/lib/Optimizer/Builder/TemporaryStorage.cpp @@ -83,7 +83,8 @@ fir::factory::HomogeneousScalarStack::HomogeneousScalarStack( mlir::Value shape = builder.genShape(loc, extents); temp = builder .create(loc, tempStorage, tempName, shape, - lengths, fir::FortranVariableFlagsAttr{}) + lengths, /*dummy_scope=*/nullptr, + fir::FortranVariableFlagsAttr{}) .getBase(); } diff --git a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp index 4b586ad1d3a4..c232ae165d4c 100644 --- a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp +++ b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp @@ -125,6 +125,7 @@ void hlfir::DeclareOp::build(mlir::OpBuilder &builder, mlir::OperationState &result, mlir::Value memref, llvm::StringRef uniq_name, mlir::Value shape, mlir::ValueRange typeparams, + mlir::Value dummy_scope, fir::FortranVariableFlagsAttr fortran_attrs, fir::CUDADataAttributeAttr cuda_attr) { auto nameAttr = builder.getStringAttr(uniq_name); @@ -133,8 +134,7 @@ void hlfir::DeclareOp::build(mlir::OpBuilder &builder, mlir::Type hlfirVariableType = getHLFIRVariableType(inputType, hasExplicitLbs); build(builder, result, {hlfirVariableType, inputType}, memref, shape, - typeparams, /*dummy_scope=*/nullptr, nameAttr, fortran_attrs, - cuda_attr); + typeparams, dummy_scope, nameAttr, fortran_attrs, cuda_attr); } mlir::LogicalResult hlfir::DeclareOp::verify() { diff --git a/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp b/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp index d4e4835ee726..76b42c57277b 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp @@ -122,9 +122,10 @@ createArrayTemp(mlir::Location loc, fir::FirOpBuilder &builder, fir::FortranVariableFlagsAttr::get( builder.getContext(), fir::FortranVariableFlagsEnum::allocatable); - auto declareOp = builder.create(loc, alloc, tmpName, - /*shape=*/nullptr, - lenParams, declAttrs); + auto declareOp = + builder.create(loc, alloc, tmpName, + /*shape=*/nullptr, lenParams, + /*dummy_scope=*/nullptr, declAttrs); int rank = extents.size(); fir::runtime::genAllocatableApplyMold(builder, loc, alloc, @@ -152,9 +153,9 @@ createArrayTemp(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Value allocmem = builder.createHeapTemporary(loc, sequenceType, tmpName, extents, lenParams); - auto declareOp = - builder.create(loc, allocmem, tmpName, shape, lenParams, - fir::FortranVariableFlagsAttr{}); + auto declareOp = builder.create( + loc, allocmem, tmpName, shape, lenParams, + /*dummy_scope=*/nullptr, fir::FortranVariableFlagsAttr{}); mlir::Value trueVal = builder.createBool(loc, true); return {hlfir::Entity{declareOp.getBase()}, trueVal}; } @@ -331,7 +332,7 @@ struct SetLengthOpConversion /*shape=*/std::nullopt, lenParams); auto declareOp = builder.create( loc, alloca, tmpName, /*shape=*/mlir::Value{}, lenParams, - fir::FortranVariableFlagsAttr{}); + /*dummy_scope=*/nullptr, fir::FortranVariableFlagsAttr{}); hlfir::Entity temp{declareOp.getBase()}; // Assign string value to the created temp. builder.create(loc, string, temp, diff --git a/flang/test/Fir/dispatch.f90 b/flang/test/Fir/dispatch.f90 index 1479d611b986..fc935217defa 100644 --- a/flang/test/Fir/dispatch.f90 +++ b/flang/test/Fir/dispatch.f90 @@ -184,7 +184,7 @@ end ! CHECK-LABEL: func.func @_QMdispatch1Pdisplay_class( ! CHECK-SAME: %[[ARG:.*]]: [[CLASS:!fir.class<.*>>]] -! CHECK: %[[ARG_DECL:.*]]:2 = hlfir.declare %[[ARG]] {uniq_name = "_QMdispatch1Fdisplay_classEp"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[ARG_DECL:.*]]:2 = hlfir.declare %[[ARG]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMdispatch1Fdisplay_classEp"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! Check dynamic dispatch equal to `call p%display2()` with binding index = 2. ! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG_DECL]]#0 : ([[CLASS]]) -> !fir.tdesc diff --git a/flang/test/HLFIR/assumed-type-actual-args.f90 b/flang/test/HLFIR/assumed-type-actual-args.f90 index dbdfc1785ce9..7ce1067d7acd 100644 --- a/flang/test/HLFIR/assumed-type-actual-args.f90 +++ b/flang/test/HLFIR/assumed-type-actual-args.f90 @@ -104,30 +104,34 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest1( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest1Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFtest1Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: fir.call @_QPs1(%[[VAL_1]]#1) fastmath : (!fir.ref) -> () ! CHECK: return ! CHECK: } ! CHECK-LABEL: func.func @_QPtest2( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> {fir.bindc_name = "x"}) { +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope ! CHECK: %[[VAL_1:.*]] = arith.constant -1 : index ! CHECK: %[[VAL_2:.*]] = fir.shape %[[VAL_1]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_2]]) {uniq_name = "_QFtest2Ex"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_2]]) dummy_scope %[[DSCOPE]] {uniq_name = "_QFtest2Ex"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) ! CHECK: fir.call @_QPs2(%[[VAL_3]]#1) fastmath : (!fir.ref>) -> () ! CHECK: return ! CHECK: } ! CHECK-LABEL: func.func @_QPtest3( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest3Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFtest3Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: fir.call @_QPs3(%[[VAL_1]]#0) fastmath : (!fir.box>) -> () ! CHECK: return ! CHECK: } ! CHECK-LABEL: func.func @_QPtest4( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest4Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFtest4Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]]:2 = hlfir.copy_in %[[VAL_1]]#0 : (!fir.box>) -> (!fir.box>, i1) ! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_2]]#0 : (!fir.box>) -> !fir.ref> ! CHECK: fir.call @_QPs4(%[[VAL_3]]) fastmath : (!fir.ref>) -> () @@ -137,7 +141,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest3b( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest3bEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %[[DSCOPE]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest3bEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = fir.is_present %[[VAL_1]]#0 : (!fir.box>) -> i1 ! CHECK: %[[VAL_3:.*]]:4 = fir.if %[[VAL_2]] -> (!fir.box>, !fir.box>, i1, !fir.box>) { ! CHECK: %[[VAL_4:.*]]:2 = hlfir.copy_in %[[VAL_1]]#0 : (!fir.box>) -> (!fir.box>, i1) @@ -156,7 +161,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest4b( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest4bEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %[[DSCOPE]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest4bEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = fir.is_present %[[VAL_1]]#0 : (!fir.box>) -> i1 ! CHECK: %[[VAL_3:.*]]:4 = fir.if %[[VAL_2]] -> (!fir.ref>, !fir.box>, i1, !fir.box>) { ! CHECK: %[[VAL_4:.*]]:2 = hlfir.copy_in %[[VAL_1]]#0 : (!fir.box>) -> (!fir.box>, i1) @@ -176,7 +182,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest4c( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous, fir.optional}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest4cEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %[[DSCOPE]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest4cEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = fir.is_present %[[VAL_1]]#0 : (!fir.box>) -> i1 ! CHECK: %[[VAL_3:.*]] = fir.if %[[VAL_2]] -> (!fir.ref>) { ! CHECK: %[[VAL_4:.*]] = fir.box_addr %[[VAL_1]]#1 : (!fir.box>) -> !fir.ref> @@ -191,7 +198,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest4d( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest4dEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %[[DSCOPE]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest4dEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]]#1 : (!fir.box>) -> !fir.ref> ! CHECK: fir.call @_QPs4d(%[[VAL_2]]) fastmath : (!fir.ref>) -> () ! CHECK: return @@ -199,7 +207,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest5( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest5Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFtest5Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]]#0 : (!fir.box>) -> !fir.box> ! CHECK: fir.call @_QPs5(%[[VAL_2]]) fastmath : (!fir.box>) -> () ! CHECK: return @@ -207,7 +216,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest5b( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest5bEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %[[DSCOPE]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest5bEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = fir.is_present %[[VAL_1]]#0 : (!fir.box>) -> i1 ! CHECK: %[[VAL_3:.*]]:4 = fir.if %[[VAL_2]] -> (!fir.box>, !fir.box>, i1, !fir.box>) { ! CHECK: %[[VAL_4:.*]]:2 = hlfir.copy_in %[[VAL_1]]#0 : (!fir.box>) -> (!fir.box>, i1) diff --git a/flang/test/HLFIR/assumed_shape_with_value_keyword.f90 b/flang/test/HLFIR/assumed_shape_with_value_keyword.f90 index b5080d9bedca..da3dff16382c 100644 --- a/flang/test/HLFIR/assumed_shape_with_value_keyword.f90 +++ b/flang/test/HLFIR/assumed_shape_with_value_keyword.f90 @@ -9,7 +9,7 @@ end ! CHECK-LABEL: func.func @_QPtest_integer_value1( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_integer_value1Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_integer_value1Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_1:.*]]:2 = hlfir.copy_in %[[VAL_0]]#0 : (!fir.box>) -> (!fir.box>, i1) ! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]]#0 : (!fir.box>) -> !fir.ref> ! CHECK: fir.call @_QPinternal_call1(%[[VAL_2]]) fastmath : (!fir.ref>) -> () @@ -23,7 +23,7 @@ subroutine test_integer_value2(x) end ! CHECK-LABEL: func.func @_QPtest_integer_value2( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_integer_value2Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_integer_value2Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_1:.*]]:2 = hlfir.copy_in %[[VAL_0]]#0 : (!fir.box>) -> (!fir.box>, i1) ! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]]#0 : (!fir.box>) -> !fir.ref> ! CHECK: fir.call @_QPinternal_call2(%[[VAL_2]]) fastmath : (!fir.ref>) -> () @@ -37,7 +37,7 @@ subroutine test_real_value1(x) end ! CHECK-LABEL: func.func @_QPtest_real_value1( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_real_value1Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_real_value1Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_1:.*]]:2 = hlfir.copy_in %[[VAL_0]]#0 : (!fir.box>) -> (!fir.box>, i1) ! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]]#0 : (!fir.box>) -> !fir.ref> ! CHECK: fir.call @_QPinternal_call3(%[[VAL_2]]) fastmath : (!fir.ref>) -> () @@ -51,7 +51,7 @@ subroutine test_real_value2(x) end ! CHECK-LABEL: func.func @_QPtest_real_value2( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_real_value2Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_real_value2Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_1:.*]]:2 = hlfir.copy_in %[[VAL_0]]#0 : (!fir.box>) -> (!fir.box>, i1) ! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]]#0 : (!fir.box>) -> !fir.ref> ! CHECK: fir.call @_QPinternal_call4(%[[VAL_2]]) fastmath : (!fir.ref>) -> () @@ -65,7 +65,7 @@ subroutine test_complex_value1(x) end ! CHECK-LABEL: func.func @_QPtest_complex_value1( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_complex_value1Ex"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_complex_value1Ex"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_1:.*]]:2 = hlfir.copy_in %[[VAL_0]]#0 : (!fir.box>>) -> (!fir.box>>, i1) ! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]]#0 : (!fir.box>>) -> !fir.ref>> ! CHECK: fir.call @_QPinternal_call5(%[[VAL_2]]) fastmath : (!fir.ref>>) -> () @@ -79,7 +79,7 @@ subroutine test_complex_value2(x) end ! CHECK-LABEL: func.func @_QPtest_complex_value2( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_complex_value2Ex"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_complex_value2Ex"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_1:.*]]:2 = hlfir.copy_in %[[VAL_0]]#0 : (!fir.box>>) -> (!fir.box>>, i1) ! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]]#0 : (!fir.box>>) -> !fir.ref>> ! CHECK: fir.call @_QPinternal_call6(%[[VAL_2]]) fastmath : (!fir.ref>>) -> () @@ -95,7 +95,7 @@ subroutine test_optional1(x) end ! CHECK-LABEL: func.func @_QPtest_optional1( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { -! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_optional1Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_optional1Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_1:.*]] = fir.is_present %[[VAL_0]]#1 : (!fir.box>) -> i1 ! CHECK: fir.if %[[VAL_1:.*]] { ! CHECK: %[[VAL_2:.*]]:2 = hlfir.copy_in %[[VAL_0]]#0 : (!fir.box>) -> (!fir.box>, i1) @@ -115,7 +115,7 @@ subroutine test_optional2(x) end ! CHECK-LABEL: func.func @_QPtest_optional2( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { -! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_optional2Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_optional2Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_1:.*]] = fir.is_present %[[VAL_0]]#1 : (!fir.box>) -> i1 ! CHECK: fir.if %[[VAL_1:.*]] { ! CHECK: %[[VAL_2:.*]]:2 = hlfir.copy_in %[[VAL_0]]#0 : (!fir.box>) -> (!fir.box>, i1) @@ -135,7 +135,7 @@ subroutine test_optional3(x) end ! CHECK-LABEL: func.func @_QPtest_optional3( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { -! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_optional3Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_optional3Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_1:.*]] = fir.is_present %[[VAL_0]]#1 : (!fir.box>) -> i1 ! CHECK: cf.cond_br %[[VAL_1]], ^bb1, ^bb2 ! CHECK: b1: // pred: ^bb0 @@ -146,4 +146,4 @@ end ! CHECK: fir.unreachable ! CHECK: b2: // pred: ^bb0 ! CHECK: return -! CHECK: } \ No newline at end of file +! CHECK: } diff --git a/flang/test/HLFIR/boxchar_emboxing.f90 b/flang/test/HLFIR/boxchar_emboxing.f90 index fbc41bbea72d..c25a5c283e36 100644 --- a/flang/test/HLFIR/boxchar_emboxing.f90 +++ b/flang/test/HLFIR/boxchar_emboxing.f90 @@ -2,7 +2,7 @@ ! CHECK-LABEL: func.func @_QPtest1( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.class {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest1Ex"} : (!fir.class) -> (!fir.class, !fir.class) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest1Ex"} : (!fir.class, !fir.dscope) -> (!fir.class, !fir.class) ! CHECK: fir.select_type %[[VAL_1]]#1 : !fir.class [#fir.type_is>, ^bb1, unit, ^bb2] ! CHECK: ^bb1: ! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]]#1 : (!fir.class) -> !fir.ref> @@ -44,7 +44,7 @@ end subroutine test1 ! CHECK-LABEL: func.func @_QPtest2( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.class> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest2Ex"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest2Ex"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: fir.select_type %[[VAL_1]]#1 : !fir.class> [#fir.type_is>, ^bb1, unit, ^bb2] ! CHECK: ^bb1: ! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]]#1 : (!fir.class>) -> !fir.box>> diff --git a/flang/test/HLFIR/c_ptr_byvalue.f90 b/flang/test/HLFIR/c_ptr_byvalue.f90 index 45e17c0ff630..377c9fccbee3 100644 --- a/flang/test/HLFIR/c_ptr_byvalue.f90 +++ b/flang/test/HLFIR/c_ptr_byvalue.f90 @@ -22,7 +22,8 @@ end ! CHECK-LABEL: func.func @_QPtest2( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> {fir.bindc_name = "cptr"}) { -! CHECK: %[[VAL_97:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest2Ecptr"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK: %[[VAL_97:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFtest2Ecptr"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_98:.*]] = fir.field_index __address, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}> ! CHECK: %[[VAL_99:.*]] = fir.coordinate_of %[[VAL_97]]#0, %[[VAL_98]] : (!fir.ref>, !fir.field) -> !fir.ref ! CHECK: %[[VAL_100:.*]] = fir.load %[[VAL_99]] : !fir.ref diff --git a/flang/test/HLFIR/call_with_poly_dummy.f90 b/flang/test/HLFIR/call_with_poly_dummy.f90 index 00a795c5b1fb..93cd410428f7 100644 --- a/flang/test/HLFIR/call_with_poly_dummy.f90 +++ b/flang/test/HLFIR/call_with_poly_dummy.f90 @@ -22,7 +22,8 @@ end subroutine test1 ! CHECK-LABEL: func.func @_QPtest2( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest2Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFtest2Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref ! CHECK: %[[VAL_3:.*]] = arith.constant 0.000000e+00 : f32 ! CHECK: %[[VAL_4:.*]] = arith.cmpf oeq, %[[VAL_2]], %[[VAL_3]] {{.*}} : f32 diff --git a/flang/test/HLFIR/optional_dummy.f90 b/flang/test/HLFIR/optional_dummy.f90 index 0f1a8d5b9c39..8534a414eaaf 100644 --- a/flang/test/HLFIR/optional_dummy.f90 +++ b/flang/test/HLFIR/optional_dummy.f90 @@ -5,7 +5,7 @@ ! CHECK-LABEL: func.func @_QPtest( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "ext_buf", fir.contiguous, fir.optional}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtestEext_buf"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtestEext_buf"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = fir.is_present %[[VAL_1]]#1 : (!fir.box>) -> i1 ! CHECK: cf.cond_br %[[VAL_2]], ^bb1, ^bb2 ! CHECK: ^bb1: diff --git a/flang/test/HLFIR/order_assignments/where-scheduling.f90 b/flang/test/HLFIR/order_assignments/where-scheduling.f90 index 0f79058a6ae9..d3665d234a71 100644 --- a/flang/test/HLFIR/order_assignments/where-scheduling.f90 +++ b/flang/test/HLFIR/order_assignments/where-scheduling.f90 @@ -134,7 +134,7 @@ end subroutine !CHECK-NEXT: run 1 save : where/mask !CHECK-NEXT: run 2 evaluate: where/region_assign1 !CHECK-LABEL: ------------ scheduling where in _QPonly_once ------------ -!CHECK-NEXT: unknown effect: %9 = fir.call @llvm.stacksave.p0() fastmath : () -> !fir.ref +!CHECK-NEXT: unknown effect: %{{[0-9]+}} = fir.call @llvm.stacksave.p0() fastmath : () -> !fir.ref !CHECK-NEXT: run 1 save (w): where/mask !CHECK-NEXT: run 2 evaluate: where/region_assign1 !CHECK-NEXT: run 3 evaluate: where/region_assign2 @@ -172,12 +172,12 @@ end subroutine !CHECK-NEXT: run 1 save : forall/where1/region_assign1/rhs !CHECK-NEXT: run 2 evaluate: forall/where1/region_assign1 !CHECK-LABEL: ------------ scheduling where in _QFno_need_to_make_lhs_tempPinternal ------------ -!CHECK-NEXT: conflict: R/W: %7 = fir.load %6 : !fir.llvm_ptr> W:%13 = fir.load %12 : !fir.ref>> +!CHECK-NEXT: conflict: R/W: %{{[0-9]+}} = fir.load %{{[0-9]+}} : !fir.llvm_ptr> W:%{{[0-9]+}} = fir.load %{{[0-9]+}} : !fir.ref>> !CHECK-NEXT: run 1 save : where/mask !CHECK-NEXT: run 2 evaluate: where/region_assign1 !CHECK-NEXT: ------------ scheduling where in _QPwhere_construct_unknown_conflict ------------ !CHECK-NEXT: unknown effect: %{{.*}} = fir.call @_QPf() fastmath : () -> f32 -!CHECK-NEXT: conflict: R/W: %{{.*}} = hlfir.declare %{{.*}} {uniq_name = "_QFwhere_construct_unknown_conflictEmask"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) W: +!CHECK-NEXT: conflict: R/W: %{{.*}} = hlfir.declare %{{.*}} {uniq_name = "_QFwhere_construct_unknown_conflictEmask"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) W: !CHECK-NEXT: run 1 save : where/mask !CHECK-NEXT: unknown effect: %{{.*}} = fir.call @_QPf() fastmath : () -> f32 !CHECK-NEXT: run 2 save (w): where/region_assign1/rhs @@ -185,9 +185,9 @@ end subroutine !CHECK-NEXT: ------------ scheduling where in _QPelsewhere_construct_unknown_conflict ------------ !CHECK-NEXT: run 1 evaluate: where/region_assign1 !CHECK-NEXT: unknown effect: %{{.*}} = fir.call @_QPf() fastmath : () -> f32 -!CHECK-NEXT: conflict: R/W: %{{.*}} = hlfir.declare %{{.*}} {uniq_name = "_QFelsewhere_construct_unknown_conflictEmask1"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) W: +!CHECK-NEXT: conflict: R/W: %{{.*}} = hlfir.declare %{{.*}} {uniq_name = "_QFelsewhere_construct_unknown_conflictEmask1"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) W: !CHECK-NEXT: run 2 save : where/mask -!CHECK-NEXT: conflict: R/W: %{{.*}} = hlfir.declare %{{.*}} {uniq_name = "_QFelsewhere_construct_unknown_conflictEmask2"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) W: +!CHECK-NEXT: conflict: R/W: %{{.*}} = hlfir.declare %{{.*}} {uniq_name = "_QFelsewhere_construct_unknown_conflictEmask2"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) W: !CHECK-NEXT: run 2 save : where/elsewhere1/mask !CHECK-NEXT: unknown effect: %{{.*}} = fir.call @_QPf() fastmath : () -> f32 !CHECK-NEXT: run 3 save (w): where/elsewhere1/region_assign1/rhs diff --git a/flang/test/Lower/CUDA/cuda-data-attribute.cuf b/flang/test/Lower/CUDA/cuda-data-attribute.cuf index 2688d220d8bb..3eb42a6a5d40 100644 --- a/flang/test/Lower/CUDA/cuda-data-attribute.cuf +++ b/flang/test/Lower/CUDA/cuda-data-attribute.cuf @@ -39,28 +39,28 @@ subroutine dummy_arg_device(dd) end subroutine ! CHECK-LABEL: func.func @_QMcuda_varPdummy_arg_device( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref {fir.bindc_name = "dd", fir.cuda_attr = #fir.cuda}) { -! CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] {cuda_attr = #fir.cuda, uniq_name = "_QMcuda_varFdummy_arg_deviceEdd"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {cuda_attr = #fir.cuda, uniq_name = "_QMcuda_varFdummy_arg_deviceEdd"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) subroutine dummy_arg_managed(dm) real, allocatable, managed :: dm end subroutine ! CHECK-LABEL: func.func @_QMcuda_varPdummy_arg_managed( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>> {fir.bindc_name = "dm", fir.cuda_attr = #fir.cuda}) { -! CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] {cuda_attr = #fir.cuda, fortran_attrs = #fir.var_attrs, uniq_name = "_QMcuda_varFdummy_arg_managedEdm"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {cuda_attr = #fir.cuda, fortran_attrs = #fir.var_attrs, uniq_name = "_QMcuda_varFdummy_arg_managedEdm"} : (!fir.ref>>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) subroutine dummy_arg_pinned(dp) real, allocatable, pinned :: dp end subroutine ! CHECK-LABEL: func.func @_QMcuda_varPdummy_arg_pinned( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>> {fir.bindc_name = "dp", fir.cuda_attr = #fir.cuda}) { -! CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] {cuda_attr = #fir.cuda, fortran_attrs = #fir.var_attrs, uniq_name = "_QMcuda_varFdummy_arg_pinnedEdp"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {cuda_attr = #fir.cuda, fortran_attrs = #fir.var_attrs, uniq_name = "_QMcuda_varFdummy_arg_pinnedEdp"} : (!fir.ref>>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) subroutine dummy_arg_unified(du) real, unified :: du end subroutine ! CHECK-LABEL: func.func @_QMcuda_varPdummy_arg_unified( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref {fir.bindc_name = "du", fir.cuda_attr = #fir.cuda}) -! CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] {cuda_attr = #fir.cuda, uniq_name = "_QMcuda_varFdummy_arg_unifiedEdu"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {cuda_attr = #fir.cuda, uniq_name = "_QMcuda_varFdummy_arg_unifiedEdu"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) subroutine cuda_alloc_free(n) integer :: n diff --git a/flang/test/Lower/HLFIR/actual_target_for_dummy_pointer.f90 b/flang/test/Lower/HLFIR/actual_target_for_dummy_pointer.f90 index 129aa49b811d..e6c247205c39 100644 --- a/flang/test/Lower/HLFIR/actual_target_for_dummy_pointer.f90 +++ b/flang/test/Lower/HLFIR/actual_target_for_dummy_pointer.f90 @@ -50,7 +50,7 @@ end subroutine integer_assumed_shape_array ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "i", fir.target}) { ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.class>> ! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.box>> -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFinteger_assumed_shape_arrayEi"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFinteger_assumed_shape_arrayEi"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_4:.*]] = fir.rebox %[[VAL_3]]#1 : (!fir.box>) -> !fir.box>> ! CHECK: fir.store %[[VAL_4]] to %[[VAL_2]] : !fir.ref>>> ! CHECK: fir.call @_QPinteger_assumed_shape_array_callee(%[[VAL_2]]) fastmath : (!fir.ref>>>) -> () @@ -159,8 +159,8 @@ end subroutine char_assumed_shape_array ! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.box>>> ! CHECK: %[[VAL_7:.*]] = fir.alloca !fir.box>>> ! CHECK: %[[VAL_8:.*]] = arith.constant 2 : index -! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_8]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFchar_assumed_shape_arrayEa1"} : (!fir.box>>, index) -> (!fir.box>>, !fir.box>>) -! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFchar_assumed_shape_arrayEa2"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_8]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFchar_assumed_shape_arrayEa1"} : (!fir.box>>, index, !fir.dscope) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFchar_assumed_shape_arrayEa2"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_11:.*]] = fir.rebox %[[VAL_9]]#1 : (!fir.box>>) -> !fir.box>>> ! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref>>>> ! CHECK: fir.call @_QPchar_assumed_shape_array_explicit_len_callee(%[[VAL_7]]) fastmath : (!fir.ref>>>>) -> () @@ -220,7 +220,7 @@ end subroutine char_explicit_shape_array ! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]]#0 : (!fir.ref>) -> !fir.ref>> ! CHECK: %[[VAL_14:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_15:.*]] = fir.shape %[[VAL_14]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_16:.*]]:2 = hlfir.declare %[[VAL_13]](%[[VAL_15]]) typeparams %[[VAL_12]]#1 {fortran_attrs = #fir.var_attrs, uniq_name = "_QFchar_explicit_shape_arrayEa2"} : (!fir.ref>>, !fir.shape<1>, index) -> (!fir.box>>, !fir.ref>>) +! CHECK: %[[VAL_16:.*]]:2 = hlfir.declare %[[VAL_13]](%[[VAL_15]]) typeparams %[[VAL_12]]#1 dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFchar_explicit_shape_arrayEa2"} : (!fir.ref>>, !fir.shape<1>, index, !fir.dscope) -> (!fir.box>>, !fir.ref>>) ! CHECK: %[[VAL_17:.*]] = fir.shape %[[VAL_8]] : (index) -> !fir.shape<1> ! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]]#1 : (!fir.ref>>) -> !fir.ref>> ! CHECK: %[[VAL_19:.*]] = fir.embox %[[VAL_18]](%[[VAL_17]]) : (!fir.ref>>, !fir.shape<1>) -> !fir.box>>> @@ -317,7 +317,7 @@ end subroutine type_assumed_shape_array ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.class>> ! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.class>>> ! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.box>>> -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtype_assumed_shape_arrayEt"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtype_assumed_shape_arrayEt"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_5:.*]] = fir.rebox %[[VAL_4]]#1 : (!fir.box>>) -> !fir.box>>> ! CHECK: fir.store %[[VAL_5]] to %[[VAL_3]] : !fir.ref>>>> ! CHECK: fir.call @_QPtype_assumed_shape_array_callee(%[[VAL_3]]) fastmath : (!fir.ref>>>>) -> () @@ -400,7 +400,7 @@ end subroutine class_scalar ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.class> ! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.class>> ! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.box>> -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFclass_scalarEt"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFclass_scalarEt"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: %[[VAL_5:.*]] = fir.rebox %[[VAL_4]]#1 : (!fir.class>) -> !fir.box>> ! CHECK: fir.store %[[VAL_5]] to %[[VAL_3]] : !fir.ref>>> ! CHECK: fir.call @_QPclass_scalar_callee(%[[VAL_3]]) fastmath : (!fir.ref>>>) -> () @@ -439,7 +439,7 @@ end subroutine class_assumed_shape_array ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.class>> ! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.class>>> ! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.box>>> -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFclass_assumed_shape_arrayEt"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFclass_assumed_shape_arrayEt"} : (!fir.class>>, !fir.dscope) -> (!fir.class>>, !fir.class>>) ! CHECK: %[[VAL_5:.*]] = fir.rebox %[[VAL_4]]#1 : (!fir.class>>) -> !fir.box>>> ! CHECK: fir.store %[[VAL_5]] to %[[VAL_3]] : !fir.ref>>>> ! CHECK: fir.call @_QPclass_assumed_shape_array_callee(%[[VAL_3]]) fastmath : (!fir.ref>>>>) -> () @@ -478,7 +478,7 @@ end subroutine class_explicit_shape_array ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.class>> ! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.class>>> ! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.box>>> -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFclass_explicit_shape_arrayEt"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFclass_explicit_shape_arrayEt"} : (!fir.class>>, !fir.dscope) -> (!fir.class>>, !fir.class>>) ! CHECK: %[[VAL_5:.*]] = fir.rebox %[[VAL_4]]#1 : (!fir.class>>) -> !fir.box>>> ! CHECK: fir.store %[[VAL_5]] to %[[VAL_3]] : !fir.ref>>>> ! CHECK: fir.call @_QPclass_explicit_shape_array_callee(%[[VAL_3]]) fastmath : (!fir.ref>>>>) -> () @@ -505,7 +505,7 @@ end subroutine uclass_scalar ! CHECK-LABEL: func.func @_QPuclass_scalar( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.class {fir.bindc_name = "t", fir.target}) { ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.class> -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFuclass_scalarEt"} : (!fir.class) -> (!fir.class, !fir.class) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFuclass_scalarEt"} : (!fir.class, !fir.dscope) -> (!fir.class, !fir.class) ! CHECK: %[[VAL_3:.*]] = fir.rebox %[[VAL_2]]#1 : (!fir.class) -> !fir.class> ! CHECK: fir.store %[[VAL_3]] to %[[VAL_1]] : !fir.ref>> ! CHECK: fir.call @_QPuclass_scalar_uclass_callee(%[[VAL_1]]) fastmath : (!fir.ref>>) -> () @@ -526,7 +526,7 @@ end subroutine uclass_assumed_shape_array ! CHECK-LABEL: func.func @_QPuclass_assumed_shape_array( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.class> {fir.bindc_name = "t", fir.target}) { ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.class>> -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFuclass_assumed_shape_arrayEt"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFuclass_assumed_shape_arrayEt"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: %[[VAL_3:.*]] = fir.rebox %[[VAL_2]]#1 : (!fir.class>) -> !fir.class>> ! CHECK: fir.store %[[VAL_3]] to %[[VAL_1]] : !fir.ref>>> ! CHECK: fir.call @_QPuclass_assumed_shape_array_uclass_callee(%[[VAL_1]]) fastmath : (!fir.ref>>>) -> () @@ -547,7 +547,7 @@ end subroutine uclass_explicit_shape_array ! CHECK-LABEL: func.func @_QPuclass_explicit_shape_array( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.class> {fir.bindc_name = "t", fir.target}) { ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.class>> -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFuclass_explicit_shape_arrayEt"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFuclass_explicit_shape_arrayEt"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: %[[VAL_3:.*]] = fir.rebox %[[VAL_2]]#1 : (!fir.class>) -> !fir.class>> ! CHECK: fir.store %[[VAL_3]] to %[[VAL_1]] : !fir.ref>>> ! CHECK: fir.call @_QPuclass_explicit_shape_array_uclass_callee(%[[VAL_1]]) fastmath : (!fir.ref>>>) -> () diff --git a/flang/test/Lower/HLFIR/allocatable-and-pointer-status-change.f90 b/flang/test/Lower/HLFIR/allocatable-and-pointer-status-change.f90 index f5ae6592faa4..328fb778eaf8 100644 --- a/flang/test/Lower/HLFIR/allocatable-and-pointer-status-change.f90 +++ b/flang/test/Lower/HLFIR/allocatable-and-pointer-status-change.f90 @@ -5,7 +5,7 @@ subroutine allocation(x) character(*), allocatable :: x(:) ! CHECK-LABEL: func.func @_QPallocation( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] typeparams %[[VAL_2:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, {{.*}}Ex +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] typeparams %[[VAL_2:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, {{.*}}Ex deallocate(x) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#1 : !fir.ref>>>> ! CHECK: %[[VAL_5:.*]] = fir.box_addr %[[VAL_4]] : (!fir.box>>>) -> !fir.heap>> @@ -30,8 +30,8 @@ subroutine pointer_assignment(p, ziel) real, pointer :: p(:) real, target :: ziel(42:) ! CHECK-LABEL: func.func @_QPpointer_assignment( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, {{.*}}Ep -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]](%[[VAL_5:[a-z0-9]*]]) {fortran_attrs = #fir.var_attrs, {{.*}}Eziel +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, {{.*}}Ep +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]](%[[VAL_5:[a-z0-9]*]]) dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, {{.*}}Eziel p => ziel ! CHECK: %[[VAL_7:.*]] = fir.shift %[[VAL_4:.*]] : (index) -> !fir.shift<1> ! CHECK: %[[VAL_8:.*]] = fir.rebox %[[VAL_6]]#1(%[[VAL_7]]) : (!fir.box>, !fir.shift<1>) -> !fir.box>> @@ -46,8 +46,8 @@ subroutine pointer_remapping(p, ziel) real, pointer :: p(:, :) real, target :: ziel(10, 20, 30) ! CHECK-LABEL: func.func @_QPpointer_remapping( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, {{.*}}Ep -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]](%[[VAL_6:[a-z0-9]*]]) {fortran_attrs = #fir.var_attrs, {{.*}}Eziel +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, {{.*}}Ep +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]](%[[VAL_6:[a-z0-9]*]]) dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, {{.*}}Eziel p(2:7, 3:102) => ziel ! CHECK: %[[VAL_8:.*]] = arith.constant 2 : i64 ! CHECK: %[[VAL_9:.*]] = arith.constant 7 : i64 @@ -101,7 +101,7 @@ subroutine ptr_comp_assign(x, ziel) x(9_8)%p => ziel ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]](%[[VAL_6:[a-z0-9]*]]) {fortran_attrs = #fir.var_attrs, {{.*}}Eziel +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]](%[[VAL_6:[a-z0-9]*]]) dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, {{.*}}Eziel ! CHECK: %[[VAL_8:.*]] = arith.constant 9 : index ! CHECK: %[[VAL_9:.*]] = hlfir.designate %[[VAL_4]]#0 (%[[VAL_8]]) : (!fir.ref>>}>>>, index) -> !fir.ref>>}>> ! CHECK: %[[VAL_10:.*]] = hlfir.designate %[[VAL_9]]{"p"} {fortran_attrs = #fir.var_attrs} : (!fir.ref>>}>>) -> !fir.ref>>> diff --git a/flang/test/Lower/HLFIR/allocatables-and-pointers.f90 b/flang/test/Lower/HLFIR/allocatables-and-pointers.f90 index ad6b2cf932e3..eb278508eba2 100644 --- a/flang/test/Lower/HLFIR/allocatables-and-pointers.f90 +++ b/flang/test/Lower/HLFIR/allocatables-and-pointers.f90 @@ -15,7 +15,7 @@ subroutine passing_allocatable(x) call takes_array(x) end subroutine ! CHECK-LABEL: func.func @_QPpassing_allocatable( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} ! CHECK: fir.call @_QPtakes_allocatable(%[[VAL_1]]#0) {{.*}} : (!fir.ref>>>) -> () ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_2]] : (!fir.box>>) -> !fir.heap> @@ -34,7 +34,7 @@ subroutine passing_pointer(x) end subroutine ! CHECK-LABEL: func.func @_QPpassing_pointer( ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.box>> -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} ! CHECK: fir.call @_QPtakes_pointer(%[[VAL_2]]#0) {{.*}} : (!fir.ref>>>) -> () ! CHECK: %[[VAL_3:.*]] = fir.zero_bits !fir.ptr> ! CHECK: %[[VAL_4:.*]] = arith.constant 0 : index @@ -53,7 +53,7 @@ subroutine passing_contiguous_pointer(x) call takes_array(x) end subroutine ! CHECK-LABEL: func.func @_QPpassing_contiguous_pointer( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_2]] : (!fir.box>>) -> !fir.ptr> ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ptr>) -> !fir.ref> @@ -66,7 +66,7 @@ subroutine character_allocatable_cst_len(x) end subroutine ! CHECK-LABEL: func.func @_QPcharacter_allocatable_cst_len( ! CHECK: %[[VAL_1:.*]] = arith.constant 10 : index -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] typeparams %[[VAL_1:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] typeparams %[[VAL_1:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref>>> ! CHECK: %[[VAL_4:.*]] = fir.box_addr %[[VAL_3]] : (!fir.box>>) -> !fir.heap> ! CHECK: %[[VAL_5:.*]] = arith.constant 10 : index @@ -87,12 +87,12 @@ subroutine character_allocatable_dyn_len(x, l) call takes_char(x//"hello") end subroutine ! CHECK-LABEL: func.func @_QPcharacter_allocatable_dyn_len( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]] {uniq_name = {{.*}}El"} +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {uniq_name = {{.*}}El"} ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref ! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 ! CHECK: %[[VAL_5:.*]] = arith.cmpi sgt, %[[VAL_3]], %[[VAL_4]] : i64 ! CHECK: %[[VAL_6:.*]] = arith.select %[[VAL_5]], %[[VAL_3]], %[[VAL_4]] : i64 -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] typeparams %[[VAL_6:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] typeparams %[[VAL_6:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} ! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref>>> ! CHECK: %[[VAL_9:.*]] = fir.box_addr %[[VAL_8]] : (!fir.box>>) -> !fir.heap> ! CHECK: %[[VAL_10:.*]] = fir.emboxchar %[[VAL_9]], %[[VAL_6]] : (!fir.heap>, i64) -> !fir.boxchar<1> @@ -110,7 +110,7 @@ subroutine print_allocatable(x) print *, x end subroutine ! CHECK-LABEL: func.func @_QPprint_allocatable( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_1]]#1 : !fir.ref>>> ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (!fir.box>>) -> !fir.box ! CHECK: %[[VAL_9:.*]] = fir.call @_FortranAioOutputDescriptor(%{{.*}}, %[[VAL_8]]) @@ -120,7 +120,7 @@ subroutine print_pointer(x) print *, x end subroutine ! CHECK-LABEL: func.func @_QPprint_pointer( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_1]]#1 : !fir.ref>>> ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (!fir.box>>) -> !fir.box ! CHECK: %[[VAL_9:.*]] = fir.call @_FortranAioOutputDescriptor(%{{.*}}, %[[VAL_8]]) @@ -130,7 +130,7 @@ subroutine elemental_expr(x) call takes_array_2(x+42) end subroutine ! CHECK-LABEL: func.func @_QPelemental_expr( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = {{.*}}Ex"} ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]] = arith.constant 42 : i32 ! CHECK: %[[VAL_4:.*]] = arith.constant 0 : index diff --git a/flang/test/Lower/HLFIR/array-ctor-as-elemental-nested.f90 b/flang/test/Lower/HLFIR/array-ctor-as-elemental-nested.f90 index f3f5653a7c48..a30c6c6e4a22 100644 --- a/flang/test/Lower/HLFIR/array-ctor-as-elemental-nested.f90 +++ b/flang/test/Lower/HLFIR/array-ctor-as-elemental-nested.f90 @@ -9,14 +9,14 @@ ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "h1"}) { ! CHECK: %[[VAL_2:.*]] = arith.constant 2 : index ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_2]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_3]]) {uniq_name = "_QFtestEh1"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_3]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFtestEh1"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = fir.alloca i32 {bindc_name = "k", uniq_name = "_QFtestEk"} ! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_5]] {uniq_name = "_QFtestEk"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_7:.*]] = fir.alloca i32 {bindc_name = "l", uniq_name = "_QFtestEl"} ! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare %[[VAL_7]] {uniq_name = "_QFtestEl"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_9:.*]] = fir.address_of(@_QFtestECn) : !fir.ref ! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_9]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtestECn"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_11:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtestEpi"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_11:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtestEpi"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_12:.*]] = arith.constant 2 : index ! CHECK: %[[VAL_13:.*]] = fir.shape %[[VAL_12]] : (index) -> !fir.shape<1> ! CHECK: %[[VAL_14:.*]] = hlfir.elemental %[[VAL_13]] unordered : (!fir.shape<1>) -> !hlfir.expr<2xf32> { diff --git a/flang/test/Lower/HLFIR/array-ctor-as-elemental.f90 b/flang/test/Lower/HLFIR/array-ctor-as-elemental.f90 index 7cbc052ea709..277e2683c64f 100644 --- a/flang/test/Lower/HLFIR/array-ctor-as-elemental.f90 +++ b/flang/test/Lower/HLFIR/array-ctor-as-elemental.f90 @@ -7,7 +7,7 @@ subroutine test_as_simple_elemental(n) end subroutine ! CHECK-LABEL: func.func @_QPtest_as_simple_elemental( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "n"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_as_simple_elementalEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_as_simple_elementalEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = arith.constant 4 : index ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_2]] : (index) -> !fir.shape<1> ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i64 @@ -41,9 +41,10 @@ end subroutine ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "lb"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "ub"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref {fir.bindc_name = "stride"}) { -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_as_strided_elementalElb"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_2]] {uniq_name = "_QFtest_as_strided_elementalEstride"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest_as_strided_elementalEub"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFtest_as_strided_elementalElb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_2]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFtest_as_strided_elementalEstride"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFtest_as_strided_elementalEub"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i64 ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref @@ -91,7 +92,7 @@ subroutine test_as_elemental_with_pure_call(n) end subroutine ! CHECK-LABEL: func.func @_QPtest_as_elemental_with_pure_call( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "n"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_as_elemental_with_pure_callEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_as_elemental_with_pure_callEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = arith.constant 4 : index ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_2]] : (index) -> !fir.shape<1> ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i64 diff --git a/flang/test/Lower/HLFIR/array-ctor-as-inlined-temp.f90 b/flang/test/Lower/HLFIR/array-ctor-as-inlined-temp.f90 index 1fc882015108..a7c2faa410fb 100644 --- a/flang/test/Lower/HLFIR/array-ctor-as-inlined-temp.f90 +++ b/flang/test/Lower/HLFIR/array-ctor-as-inlined-temp.f90 @@ -116,7 +116,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest_implied_do( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "n"}) { ! CHECK: %[[VAL_1:.*]] = fir.alloca index -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_implied_doEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_implied_doEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = arith.constant 0 : i64 ! CHECK: %[[VAL_4:.*]] = arith.constant 2 : i64 ! CHECK: %[[VAL_5:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref @@ -178,9 +178,9 @@ end subroutine ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "ub"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref {fir.bindc_name = "stride"}) { ! CHECK: %[[VAL_3:.*]] = fir.alloca index -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_strided_implied_doElb"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_2]] {uniq_name = "_QFtest_strided_implied_doEstride"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest_strided_implied_doEub"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_strided_implied_doElb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_strided_implied_doEstride"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_strided_implied_doEub"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_7:.*]] = arith.constant 0 : i64 ! CHECK: %[[VAL_8:.*]] = arith.constant 2 : i64 ! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref @@ -241,8 +241,8 @@ end subroutine ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "n"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "m"}) { ! CHECK: %[[VAL_2:.*]] = fir.alloca index -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest_nested_implied_doEm"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_nested_implied_doEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_nested_implied_doEm"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_nested_implied_doEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_5:.*]] = arith.constant 0 : i64 ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i64 ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref diff --git a/flang/test/Lower/HLFIR/array-ctor-index.f90 b/flang/test/Lower/HLFIR/array-ctor-index.f90 index 83eb2cd3a408..f0c7cf620e9a 100644 --- a/flang/test/Lower/HLFIR/array-ctor-index.f90 +++ b/flang/test/Lower/HLFIR/array-ctor-index.f90 @@ -8,7 +8,7 @@ function test1(k) end function test1 ! CHECK-LABEL: func.func @_QPtest1( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "k"}) -> !fir.array<4xi8> { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest1Ek"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest1Ek"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = arith.constant 4 : index ! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.array<4xi8> {bindc_name = "test1", uniq_name = "_QFtest1Etest1"} ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_2]] : (index) -> !fir.shape<1> @@ -58,7 +58,7 @@ function test2(k) end function test2 ! CHECK-LABEL: func.func @_QPtest2( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "k"}) -> !fir.array<4xi16> { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest2Ek"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest2Ek"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = arith.constant 4 : index ! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.array<4xi16> {bindc_name = "test2", uniq_name = "_QFtest2Etest2"} ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_2]] : (index) -> !fir.shape<1> @@ -108,7 +108,7 @@ function test3(k) end function test3 ! CHECK-LABEL: func.func @_QPtest3( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "k"}) -> !fir.array<4xi32> { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest3Ek"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest3Ek"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = arith.constant 4 : index ! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.array<4xi32> {bindc_name = "test3", uniq_name = "_QFtest3Etest3"} ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_2]] : (index) -> !fir.shape<1> @@ -158,7 +158,7 @@ function test4(k) end function test4 ! CHECK-LABEL: func.func @_QPtest4( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "k"}) -> !fir.array<4xi64> { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest4Ek"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest4Ek"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = arith.constant 4 : index ! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.array<4xi64> {bindc_name = "test4", uniq_name = "_QFtest4Etest4"} ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_2]] : (index) -> !fir.shape<1> diff --git a/flang/test/Lower/HLFIR/assignment-intrinsics.f90 b/flang/test/Lower/HLFIR/assignment-intrinsics.f90 index 984395d8f90d..544815e88140 100644 --- a/flang/test/Lower/HLFIR/assignment-intrinsics.f90 +++ b/flang/test/Lower/HLFIR/assignment-intrinsics.f90 @@ -10,8 +10,8 @@ subroutine scalar_int(x, y) x = y end subroutine ! CHECK-LABEL: func.func @_QPscalar_int( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_intEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_intEx"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_intEy"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 ! CHECK: hlfir.assign %[[VAL_4]] to %[[VAL_2]]#0 : i32, !fir.ref @@ -20,8 +20,8 @@ subroutine scalar_logical(x, y) x = y end subroutine ! CHECK-LABEL: func.func @_QPscalar_logical( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_logicalEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_logicalEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_logicalEx"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_logicalEy"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 ! CHECK: hlfir.assign %[[VAL_4]] to %[[VAL_2]]#0 : !fir.logical<4>, !fir.ref> @@ -30,8 +30,8 @@ subroutine scalar_real(x, y) x = y end subroutine ! CHECK-LABEL: func.func @_QPscalar_real( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_realEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_realEx"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_realEy"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 ! CHECK: hlfir.assign %[[VAL_4]] to %[[VAL_2]]#0 : f32, !fir.ref @@ -40,8 +40,8 @@ subroutine scalar_complex(x, y) x = y end subroutine ! CHECK-LABEL: func.func @_QPscalar_complex( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_complexEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_complexEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_complexEx"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_complexEy"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 ! CHECK: hlfir.assign %[[VAL_4]] to %[[VAL_2]]#0 : !fir.complex<4>, !fir.ref> @@ -50,8 +50,8 @@ subroutine scalar_character(x, y) x = y end subroutine ! CHECK-LABEL: func.func @_QPscalar_character( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_characterEx"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_characterEy"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_characterEx"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_characterEy"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: hlfir.assign %[[VAL_5]]#0 to %[[VAL_3]]#0 : !fir.boxchar<1>, !fir.boxchar<1> ! ----------------------------------------------------------------------------- @@ -63,7 +63,7 @@ subroutine scalar_int_2(x) x = 42 end subroutine ! CHECK-LABEL: func.func @_QPscalar_int_2( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_int_2Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_int_2Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = arith.constant 42 : i32 ! CHECK: hlfir.assign %[[VAL_2]] to %[[VAL_1]]#0 : i32, !fir.ref @@ -72,7 +72,7 @@ subroutine scalar_logical_2(x) x = .true. end subroutine ! CHECK-LABEL: func.func @_QPscalar_logical_2( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_logical_2Ex"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_logical_2Ex"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_2:.*]] = arith.constant true ! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_3]] to %[[VAL_1]]#0 : !fir.logical<4>, !fir.ref> @@ -82,7 +82,7 @@ subroutine scalar_real_2(x) x = 3.14 end subroutine ! CHECK-LABEL: func.func @_QPscalar_real_2( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_real_2Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_real_2Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = arith.constant 3.140000e+00 : f32 ! CHECK: hlfir.assign %[[VAL_2]] to %[[VAL_1]]#0 : f32, !fir.ref @@ -91,7 +91,7 @@ subroutine scalar_complex_2(x) x = (1., -1.) end subroutine ! CHECK-LABEL: func.func @_QPscalar_complex_2( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_complex_2Ex"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_complex_2Ex"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_2:.*]] = arith.constant 1.000000e+00 : f32 ! CHECK: %[[VAL_3:.*]] = arith.constant -1.000000e+00 : f32 ! CHECK: %[[VAL_4:.*]] = fir.undefined !fir.complex<4> @@ -104,7 +104,7 @@ subroutine scalar_character_2(x) x = "hello" end subroutine ! CHECK-LABEL: func.func @_QPscalar_character_2( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_character_2Ex"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFscalar_character_2Ex"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare {{.*}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QQclX68656C6C6F"} : (!fir.ref>, index) -> (!fir.ref>, !fir.ref>) ! CHECK: hlfir.assign %[[VAL_5]]#0 to %[[VAL_2]]#0 : !fir.ref>, !fir.boxchar<1> @@ -117,8 +117,8 @@ subroutine array(x, y) x = y end subroutine ! CHECK-LABEL: func.func @_QParray( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarrayEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarrayEy"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarrayEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarrayEy"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: hlfir.assign %[[VAL_5]]#0 to %[[VAL_2]]#0 : !fir.ref>, !fir.box> subroutine array_lbs(x, y) @@ -126,8 +126,8 @@ subroutine array_lbs(x, y) x = y end subroutine ! CHECK-LABEL: func.func @_QParray_lbs( -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarray_lbsEx"} : (!fir.ref>>, !fir.shapeshift<1>) -> (!fir.box>>, !fir.ref>>) -! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarray_lbsEy"} : (!fir.ref>>, !fir.shapeshift<1>) -> (!fir.box>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarray_lbsEx"} : (!fir.ref>>, !fir.shapeshift<1>, !fir.dscope) -> (!fir.box>>, !fir.ref>>) +! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarray_lbsEy"} : (!fir.ref>>, !fir.shapeshift<1>, !fir.dscope) -> (!fir.box>>, !fir.ref>>) ! CHECK: hlfir.assign %[[VAL_9]]#0 to %[[VAL_5]]#0 : !fir.box>>, !fir.box>> @@ -136,8 +136,8 @@ subroutine array_character(x, y) x = y end subroutine ! CHECK-LABEL: func.func @_QParray_character( -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarray_characterEx"} : (!fir.ref>>, !fir.shape<1>, index) -> (!fir.box>>, !fir.ref>>) -! CHECK: %[[VAL_11:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarray_characterEy"} : (!fir.ref>>, !fir.shape<1>, index) -> (!fir.box>>, !fir.ref>>) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarray_characterEx"} : (!fir.ref>>, !fir.shape<1>, index, !fir.dscope) -> (!fir.box>>, !fir.ref>>) +! CHECK: %[[VAL_11:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarray_characterEy"} : (!fir.ref>>, !fir.shape<1>, index, !fir.dscope) -> (!fir.box>>, !fir.ref>>) ! CHECK: hlfir.assign %[[VAL_11]]#0 to %[[VAL_6]]#0 : !fir.box>>, !fir.box>> subroutine array_pointer(x, y) @@ -160,8 +160,8 @@ subroutine array_scalar(x, y) x = y end subroutine ! CHECK-LABEL: func.func @_QParray_scalar( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarray_scalarEx"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarray_scalarEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarray_scalarEx"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFarray_scalarEy"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_5]]#0 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : i32, !fir.ref> diff --git a/flang/test/Lower/HLFIR/assumed-rank-iface-alloc-ptr.f90 b/flang/test/Lower/HLFIR/assumed-rank-iface-alloc-ptr.f90 index 1bb5c001ece8..fb1385f87f1b 100644 --- a/flang/test/Lower/HLFIR/assumed-rank-iface-alloc-ptr.f90 +++ b/flang/test/Lower/HLFIR/assumed-rank-iface-alloc-ptr.f90 @@ -23,7 +23,7 @@ subroutine scalar_alloc_to_assumed_rank(x) end subroutine ! CHECK-LABEL: func.func @_QPscalar_alloc_to_assumed_rank( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFscalar_alloc_to_assumed_rankEx"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFscalar_alloc_to_assumed_rankEx"} : (!fir.ref>>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]]#0 : (!fir.ref>>) -> !fir.ref>>> ! CHECK: fir.call @_QPalloc_assumed_rank(%[[VAL_2]]) fastmath : (!fir.ref>>>) -> () @@ -34,7 +34,7 @@ subroutine r2_alloc_to_assumed_rank(x) end subroutine ! CHECK-LABEL: func.func @_QPr2_alloc_to_assumed_rank( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFr2_alloc_to_assumed_rankEx"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFr2_alloc_to_assumed_rankEx"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]]#0 : (!fir.ref>>>) -> !fir.ref>>> ! CHECK: fir.call @_QPalloc_assumed_rank(%[[VAL_2]]) fastmath : (!fir.ref>>>) -> () @@ -45,7 +45,7 @@ subroutine scalar_pointer_to_assumed_rank(x) end subroutine ! CHECK-LABEL: func.func @_QPscalar_pointer_to_assumed_rank( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFscalar_pointer_to_assumed_rankEx"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFscalar_pointer_to_assumed_rankEx"} : (!fir.ref>>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]]#0 : (!fir.ref>>) -> !fir.ref>>> ! CHECK: fir.call @_QPpointer_assumed_rank(%[[VAL_2]]) fastmath : (!fir.ref>>>) -> () @@ -56,7 +56,7 @@ subroutine r2_pointer_to_assumed_rank(x) end subroutine ! CHECK-LABEL: func.func @_QPr2_pointer_to_assumed_rank( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFr2_pointer_to_assumed_rankEx"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFr2_pointer_to_assumed_rankEx"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]]#0 : (!fir.ref>>>) -> !fir.ref>>> ! CHECK: fir.call @_QPpointer_assumed_rank(%[[VAL_2]]) fastmath : (!fir.ref>>>) -> () @@ -68,7 +68,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPr2_target_to_pointer_assumed_rank( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.target}) { ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.box>> -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFr2_target_to_pointer_assumed_rankEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFr2_target_to_pointer_assumed_rankEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_3:.*]] = fir.rebox %[[VAL_2]]#1 : (!fir.box>) -> !fir.box>> ! CHECK: fir.store %[[VAL_3]] to %[[VAL_1]] : !fir.ref>>> ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_1]] : (!fir.ref>>>) -> !fir.ref>>> diff --git a/flang/test/Lower/HLFIR/assumed-rank-iface.f90 b/flang/test/Lower/HLFIR/assumed-rank-iface.f90 index 155ce8fb55f2..2d1d941238b1 100644 --- a/flang/test/Lower/HLFIR/assumed-rank-iface.f90 +++ b/flang/test/Lower/HLFIR/assumed-rank-iface.f90 @@ -23,7 +23,7 @@ subroutine int_scalar_to_assumed_rank(x) end subroutine ! CHECK-LABEL: func.func @_QPint_scalar_to_assumed_rank( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFint_scalar_to_assumed_rankEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFint_scalar_to_assumed_rankEx"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = fir.embox %[[VAL_1]]#0 : (!fir.ref) -> !fir.box ! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.box) -> !fir.box> ! CHECK: fir.call @_QPint_assumed_rank(%[[VAL_3]]) fastmath : (!fir.box>) -> () @@ -35,7 +35,7 @@ subroutine int_scalar_to_assumed_rank_bindc(x) end subroutine ! CHECK-LABEL: func.func @_QPint_scalar_to_assumed_rank_bindc( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFint_scalar_to_assumed_rank_bindcEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFint_scalar_to_assumed_rank_bindcEx"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = fir.embox %[[VAL_1]]#0 : (!fir.ref) -> !fir.box ! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.box) -> !fir.box> ! CHECK: fir.call @int_assumed_rank_bindc(%[[VAL_3]]) fastmath : (!fir.box>) -> () @@ -49,7 +49,7 @@ end subroutine ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> {fir.bindc_name = "x"}) { ! CHECK: %[[VAL_1:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_2:.*]] = fir.shape %[[VAL_1]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_2]]) {uniq_name = "_QFint_r1_to_assumed_rankEx"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_2]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFint_r1_to_assumed_rankEx"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = fir.embox %[[VAL_3]]#0(%[[VAL_2]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> ! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (!fir.box>) -> !fir.box> ! CHECK: fir.call @_QPint_assumed_rank(%[[VAL_5]]) fastmath : (!fir.box>) -> () @@ -66,7 +66,7 @@ end subroutine ! CHECK: %[[VAL_3:.*]] = arith.constant 4 : index ! CHECK: %[[VAL_4:.*]] = arith.constant 5 : index ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_1]], %[[VAL_2]], %[[VAL_3]], %[[VAL_4]] : (index, index, index, index) -> !fir.shape<4> -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_5]]) {uniq_name = "_QFint_r4_to_assumed_rankEx"} : (!fir.ref>, !fir.shape<4>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_5]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFint_r4_to_assumed_rankEx"} : (!fir.ref>, !fir.shape<4>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.ref>, !fir.shape<4>) -> !fir.box> ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (!fir.box>) -> !fir.box> ! CHECK: fir.call @_QPint_assumed_rank(%[[VAL_8]]) fastmath : (!fir.box>) -> () @@ -78,7 +78,7 @@ subroutine int_assumed_shape_to_assumed_rank(x) end subroutine ! CHECK-LABEL: func.func @_QPint_assumed_shape_to_assumed_rank( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFint_assumed_shape_to_assumed_rankEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFint_assumed_shape_to_assumed_rankEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]]#0 : (!fir.box>) -> !fir.box> ! CHECK: fir.call @_QPint_assumed_rank(%[[VAL_2]]) fastmath : (!fir.box>) -> () @@ -89,7 +89,7 @@ subroutine int_assumed_shape_to_assumed_rank_bindc(x) end subroutine ! CHECK-LABEL: func.func @_QPint_assumed_shape_to_assumed_rank_bindc( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFint_assumed_shape_to_assumed_rank_bindcEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFint_assumed_shape_to_assumed_rank_bindcEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_3:.*]] = fir.shift %[[VAL_2]], %[[VAL_2]] : (index, index) -> !fir.shift<2> ! CHECK: %[[VAL_4:.*]] = fir.rebox %[[VAL_1]]#0(%[[VAL_3]]) : (!fir.box>, !fir.shift<2>) -> !fir.box> @@ -103,7 +103,7 @@ subroutine int_allocatable_to_assumed_rank(x) end subroutine ! CHECK-LABEL: func.func @_QPint_allocatable_to_assumed_rank( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFint_allocatable_to_assumed_rankEx"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFint_allocatable_to_assumed_rankEx"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]] = fir.rebox %[[VAL_2]] : (!fir.box>>) -> !fir.box> ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.box>) -> !fir.box> @@ -116,7 +116,7 @@ subroutine int_allocatable_to_assumed_rank_opt(x) end subroutine ! CHECK-LABEL: func.func @_QPint_allocatable_to_assumed_rank_opt( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFint_allocatable_to_assumed_rank_optEx"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFint_allocatable_to_assumed_rank_optEx"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#1 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_2]] : (!fir.box>>) -> !fir.heap> ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.heap>) -> i64 @@ -147,6 +147,6 @@ end subroutine ! CHECK: %[[VAL_5:.*]] = arith.select %[[VAL_4]], %[[VAL_2]], %[[VAL_3]] : index ! CHECK: %[[VAL_6:.*]] = arith.constant -1 : index ! CHECK: %[[VAL_7:.*]] = fir.shape %[[VAL_5]], %[[VAL_6]] : (index, index) -> !fir.shape<2> -! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_7]]) {uniq_name = "_QFint_r2_assumed_size_to_assumed_rankEx"} : (!fir.ref>, !fir.shape<2>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_7]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFint_r2_assumed_size_to_assumed_rankEx"} : (!fir.ref>, !fir.shape<2>, !fir.dscope) -> (!fir.box>, !fir.ref>) ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]]#0 : (!fir.box>) -> !fir.box> ! CHECK: fir.call @_QPint_assumed_rank(%[[VAL_9]]) fastmath : (!fir.box>) -> () diff --git a/flang/test/Lower/HLFIR/binary-ops.f90 b/flang/test/Lower/HLFIR/binary-ops.f90 index e0af9258cda3..912cea0f5e0e 100644 --- a/flang/test/Lower/HLFIR/binary-ops.f90 +++ b/flang/test/Lower/HLFIR/binary-ops.f90 @@ -6,8 +6,8 @@ subroutine int_add(x, y, z) x = y + z end subroutine ! CHECK-LABEL: func.func @_QPint_add( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = arith.addi %[[VAL_6]], %[[VAL_7]] : i32 @@ -17,8 +17,8 @@ subroutine real_add(x, y, z) x = y + z end subroutine ! CHECK-LABEL: func.func @_QPreal_add( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = arith.addf %[[VAL_6]], %[[VAL_7]] fastmath : f32 @@ -28,8 +28,8 @@ subroutine complex_add(x, y, z) x = y + z end subroutine ! CHECK-LABEL: func.func @_QPcomplex_add( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref> ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref> ! CHECK: %[[VAL_8:.*]] = fir.addc %[[VAL_6]], %[[VAL_7]] {fastmath = #arith.fastmath} : !fir.complex<4> @@ -39,8 +39,8 @@ subroutine int_sub(x, y, z) x = y - z end subroutine ! CHECK-LABEL: func.func @_QPint_sub( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = arith.subi %[[VAL_6]], %[[VAL_7]] : i32 @@ -50,8 +50,8 @@ subroutine real_sub(x, y, z) x = y - z end subroutine ! CHECK-LABEL: func.func @_QPreal_sub( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = arith.subf %[[VAL_6]], %[[VAL_7]] fastmath : f32 @@ -61,8 +61,8 @@ subroutine complex_sub(x, y, z) x = y - z end subroutine ! CHECK-LABEL: func.func @_QPcomplex_sub( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref> ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref> ! CHECK: %[[VAL_8:.*]] = fir.subc %[[VAL_6]], %[[VAL_7]] {fastmath = #arith.fastmath} : !fir.complex<4> @@ -72,8 +72,8 @@ subroutine int_mul(x, y, z) x = y * z end subroutine ! CHECK-LABEL: func.func @_QPint_mul( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = arith.muli %[[VAL_6]], %[[VAL_7]] : i32 @@ -83,8 +83,8 @@ subroutine real_mul(x, y, z) x = y * z end subroutine ! CHECK-LABEL: func.func @_QPreal_mul( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = arith.mulf %[[VAL_6]], %[[VAL_7]] fastmath : f32 @@ -94,8 +94,8 @@ subroutine complex_mul(x, y, z) x = y * z end subroutine ! CHECK-LABEL: func.func @_QPcomplex_mul( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref> ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref> ! CHECK: %[[VAL_8:.*]] = fir.mulc %[[VAL_6]], %[[VAL_7]] {fastmath = #arith.fastmath} : !fir.complex<4> @@ -105,8 +105,8 @@ subroutine int_div(x, y, z) x = y / z end subroutine ! CHECK-LABEL: func.func @_QPint_div( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = arith.divsi %[[VAL_6]], %[[VAL_7]] : i32 @@ -116,8 +116,8 @@ subroutine real_div(x, y, z) x = y / z end subroutine ! CHECK-LABEL: func.func @_QPreal_div( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = arith.divf %[[VAL_6]], %[[VAL_7]] fastmath : f32 @@ -127,8 +127,8 @@ subroutine complex_div(x, y, z) x = y / z end subroutine ! CHECK-LABEL: func.func @_QPcomplex_div( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref> ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref> ! CHECK: %[[VAL_8:.*]] = fir.extract_value %[[VAL_6]], [0 : index] : (!fir.complex<4>) -> f32 @@ -142,8 +142,8 @@ subroutine int_power(x, y, z) x = y**z end subroutine ! CHECK-LABEL: func.func @_QPint_power( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = math.ipowi %[[VAL_6]], %[[VAL_7]] : i32 @@ -153,8 +153,8 @@ subroutine real_power(x, y, z) x = y**z end subroutine ! CHECK-LABEL: func.func @_QPreal_power( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = math.powf %[[VAL_6]], %[[VAL_7]] fastmath : f32 @@ -164,8 +164,8 @@ subroutine complex_power(x, y, z) x = y**z end subroutine ! CHECK-LABEL: func.func @_QPcomplex_power( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref> ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref> ! CHECK: %[[VAL_8:.*]] = fir.call @cpowf(%[[VAL_6]], %[[VAL_7]]) fastmath : (!fir.complex<4>, !fir.complex<4>) -> !fir.complex<4> @@ -177,8 +177,8 @@ subroutine real_to_int_power(x, y, z) x = y**z end subroutine ! CHECK-LABEL: func.func @_QPreal_to_int_power( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = math.fpowi %[[VAL_6]], %[[VAL_7]] fastmath : f32, i32 @@ -189,8 +189,8 @@ subroutine complex_to_int_power(x, y, z) x = y**z end subroutine ! CHECK-LABEL: func.func @_QPcomplex_to_int_power( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref> ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = fir.call @_FortranAcpowi(%[[VAL_6]], %[[VAL_7]]) fastmath : (!fir.complex<4>, i32) -> !fir.complex<4> @@ -203,7 +203,7 @@ subroutine extremum(c, n, l) n = len(c, 8) end subroutine ! CHECK-LABEL: func.func @_QPextremum( -! CHECK: hlfir.declare {{.*}}c +! CHECK: hlfir.declare {{.*}}c"} ! CHECK: %[[VAL_11:.*]] = arith.constant 0 : i64 ! CHECK: %[[VAL_12:.*]] = fir.load %{{.*}} : !fir.ref ! CHECK: %[[VAL_13:.*]] = arith.cmpi sgt, %[[VAL_11]], %[[VAL_12]] : i64 @@ -281,8 +281,8 @@ subroutine cmp_char(l, x, y) l = x .eq. y end subroutine ! CHECK-LABEL: func.func @_QPcmp_char( -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}} typeparams %[[VAL_4:.*]]#1 {uniq_name = "_QFcmp_charEx"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %{{.*}} typeparams %[[VAL_6:.*]]#1 {uniq_name = "_QFcmp_charEy"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}} typeparams %[[VAL_4:.*]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFcmp_charEx"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %{{.*}} typeparams %[[VAL_6:.*]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFcmp_charEy"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_5]]#1 : (!fir.ref>) -> !fir.ref ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_7]]#1 : (!fir.ref>) -> !fir.ref ! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_4]]#1 : (index) -> i64 @@ -296,8 +296,8 @@ subroutine logical_and(x, y, z) x = y.and.z end subroutine ! CHECK-LABEL: func.func @_QPlogical_and( -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %{{.*}}z"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref> ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref> ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_6]] : (!fir.logical<4>) -> i1 @@ -331,8 +331,8 @@ subroutine cmplx_ctor(z, x, y) z = cmplx(x, y) end subroutine ! CHECK-LABEL: func.func @_QPcmplx_ctor( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}}y"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_8:.*]] = fir.undefined !fir.complex<4> @@ -345,7 +345,7 @@ subroutine cmplx_ctor_2(z, x) z = cmplx(x, 1._8, kind=8) end subroutine ! CHECK-LABEL: func.func @_QPcmplx_ctor_2( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref ! CHECK: %[[VAL_5:.*]] = arith.constant 1.000000e+00 : f64 ! CHECK: %[[VAL_6:.*]] = fir.undefined !fir.complex<8> diff --git a/flang/test/Lower/HLFIR/bindc-value-derived.f90 b/flang/test/Lower/HLFIR/bindc-value-derived.f90 index 671e6d45b9a9..7103d54c3e3d 100644 --- a/flang/test/Lower/HLFIR/bindc-value-derived.f90 +++ b/flang/test/Lower/HLFIR/bindc-value-derived.f90 @@ -17,7 +17,7 @@ contains ! CHECK-SAME: %[[VAL_0:.*]]: !fir.type<_QMbindc_byvalTt{i:i32}> {fir.bindc_name = "x"}) attributes {fir.bindc_name = "test"} { ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.type<_QMbindc_byvalTt{i:i32}> ! CHECK: fir.store %[[VAL_0]] to %[[VAL_1]] : !fir.ref> -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMbindc_byvalFtestEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMbindc_byvalFtestEx"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_3:.*]] = hlfir.designate %[[VAL_2]]#0{"i"} : (!fir.ref>) -> !fir.ref ! CHECK: fir.call @_QPuse_it(%[[VAL_3]]) fastmath : (!fir.ref) -> () ! CHECK: return @@ -29,7 +29,7 @@ contains end subroutine ! CHECK-LABEL: func.func @_QMbindc_byvalPcall_it( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QMbindc_byvalFcall_itEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMbindc_byvalFcall_itEx"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#1 : !fir.ref> ! CHECK: fir.call @test(%[[VAL_2]]) fastmath : (!fir.type<_QMbindc_byvalTt{i:i32}>) -> () ! CHECK: return diff --git a/flang/test/Lower/HLFIR/call-sequence-associated-descriptors.f90 b/flang/test/Lower/HLFIR/call-sequence-associated-descriptors.f90 index 7a2ea5cc14b6..bad647bb3ac9 100644 --- a/flang/test/Lower/HLFIR/call-sequence-associated-descriptors.f90 +++ b/flang/test/Lower/HLFIR/call-sequence-associated-descriptors.f90 @@ -23,7 +23,7 @@ contains call takes_char(x, 100) end subroutine ! CHECK-LABEL: func.func @_QMbindc_seq_assocPtest_char_1( -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_2:.*]](%[[VAL_5:.*]]) typeparams %[[VAL_1:.*]]#1 {uniq_name = "_QMbindc_seq_assocFtest_char_1Ex"} : (!fir.ref>>, !fir.shape<2>, index) -> (!fir.box>>, !fir.ref>>) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_2:.*]](%[[VAL_5:.*]]) typeparams %[[VAL_1:.*]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QMbindc_seq_assocFtest_char_1Ex"} : (!fir.ref>>, !fir.shape<2>, index, !fir.dscope) -> (!fir.box>>, !fir.ref>>) ! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_9:.*]] = fir.shift %[[VAL_8]], %[[VAL_8]] : (index, index) -> !fir.shift<2> @@ -56,7 +56,7 @@ contains call takes_char(x, 100) end subroutine ! CHECK-LABEL: func.func @_QMbindc_seq_assocPtest_char_copy_in_copy_out( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:.*]] {uniq_name = "_QMbindc_seq_assocFtest_char_copy_in_copy_outEx"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:.*]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMbindc_seq_assocFtest_char_copy_in_copy_outEx"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_2:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_3:.*]]:2 = hlfir.copy_in %[[VAL_1]]#0 : (!fir.box>>) -> (!fir.box>>, i1) ! CHECK: %[[VAL_4:.*]] = arith.constant 0 : index @@ -91,7 +91,7 @@ contains call takes_char_assumed_size(x) end subroutine ! CHECK-LABEL: func.func @_QMbindc_seq_assocPtest_char_assumed_size( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:.*]] {uniq_name = "_QMbindc_seq_assocFtest_char_assumed_sizeEx"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:.*]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMbindc_seq_assocFtest_char_assumed_sizeEx"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_2:.*]]:2 = hlfir.copy_in %[[VAL_1]]#0 : (!fir.box>>) -> (!fir.box>>, i1) ! CHECK: %[[VAL_3:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_4:.*]] = fir.shift %[[VAL_3]], %[[VAL_3]] : (index, index) -> !fir.shift<2> @@ -123,7 +123,7 @@ contains call takes_optional_char(x, 100) end subroutine ! CHECK-LABEL: func.func @_QMbindc_seq_assocPtest_optional_char( -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_2:.*]](%[[VAL_5:.*]]) typeparams %[[VAL_1:.*]]#1 {fortran_attrs = #fir.var_attrs, uniq_name = "_QMbindc_seq_assocFtest_optional_charEx"} : (!fir.ref>>, !fir.shape<2>, index) -> (!fir.box>>, !fir.ref>>) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_2:.*]](%[[VAL_5:.*]]) typeparams %[[VAL_1:.*]]#1 dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMbindc_seq_assocFtest_optional_charEx"} : (!fir.ref>>, !fir.shape<2>, index, !fir.dscope) -> (!fir.box>>, !fir.ref>>) ! CHECK: %[[VAL_7:.*]] = fir.is_present %[[VAL_6]]#0 : (!fir.box>>) -> i1 ! CHECK: %[[VAL_8:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_9:.*]] = fir.if %[[VAL_7]] -> (!fir.box>>) { @@ -186,7 +186,7 @@ contains end subroutine ! CHECK-LABEL: func.func @_QMpoly_seq_assocPtest_poly_1( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.class> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:.*]] {uniq_name = "_QMpoly_seq_assocFtest_poly_1Ex"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:.*]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMpoly_seq_assocFtest_poly_1Ex"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: %[[VAL_2:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_3:.*]]:3 = hlfir.associate %[[VAL_2]] {adapt.valuebyref} : (i32) -> (!fir.ref, !fir.ref, i1) ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]]#1 {uniq_name = "_QMpoly_seq_assocFtakes_polyEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) @@ -214,7 +214,7 @@ contains call takes_poly(x, 100) end subroutine ! CHECK-LABEL: func.func @_QMpoly_seq_assocPtest_poly_copy_in_copy_out( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:.*]] {uniq_name = "_QMpoly_seq_assocFtest_poly_copy_in_copy_outEx"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:.*]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMpoly_seq_assocFtest_poly_copy_in_copy_outEx"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: %[[VAL_2:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_3:.*]]:2 = hlfir.copy_in %[[VAL_1]]#0 : (!fir.class>) -> (!fir.class>, i1) ! CHECK: %[[VAL_4:.*]]:3 = hlfir.associate %[[VAL_2]] {adapt.valuebyref} : (i32) -> (!fir.ref, !fir.ref, i1) @@ -244,7 +244,7 @@ contains call takes_poly_assumed_size(x) end subroutine ! CHECK-LABEL: func.func @_QMpoly_seq_assocPtest_poly_assumed_size( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:.*]] {uniq_name = "_QMpoly_seq_assocFtest_poly_assumed_sizeEx"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:.*]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMpoly_seq_assocFtest_poly_assumed_sizeEx"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: %[[VAL_2:.*]]:2 = hlfir.copy_in %[[VAL_1]]#0 : (!fir.class>) -> (!fir.class>, i1) ! CHECK: %[[VAL_3:.*]] = arith.constant 10 : i64 ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i64 @@ -271,7 +271,7 @@ contains call takes_optional_poly(x, 100) end subroutine ! CHECK-LABEL: func.func @_QMpoly_seq_assocPtest_optional_poly( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:.*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpoly_seq_assocFtest_optional_polyEx"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:.*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpoly_seq_assocFtest_optional_polyEx"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: %[[VAL_2:.*]] = fir.is_present %[[VAL_1]]#0 : (!fir.class>) -> i1 ! CHECK: %[[VAL_3:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_4:.*]] = fir.if %[[VAL_2]] -> (!fir.class>) { diff --git a/flang/test/Lower/HLFIR/calls-assumed-shape.f90 b/flang/test/Lower/HLFIR/calls-assumed-shape.f90 index a2094f1f1f0e..cfe607a69102 100644 --- a/flang/test/Lower/HLFIR/calls-assumed-shape.f90 +++ b/flang/test/Lower/HLFIR/calls-assumed-shape.f90 @@ -12,7 +12,7 @@ subroutine test_assumed_to_assumed(x) call takes_assumed(x) end subroutine ! CHECK-LABEL: func.func @_QPtest_assumed_to_assumed( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {uniq_name = "_QFtest_assumed_to_assumedEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_assumed_to_assumedEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: fir.call @_QPtakes_assumed(%[[VAL_1]]#0) {{.*}} : (!fir.box>) -> () subroutine test_ptr_to_assumed(p) @@ -25,7 +25,7 @@ subroutine test_ptr_to_assumed(p) call takes_assumed(p) end subroutine ! CHECK-LABEL: func.func @_QPtest_ptr_to_assumed( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_ptr_to_assumedEp"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_ptr_to_assumedEp"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]] = fir.rebox %[[VAL_2]] : (!fir.box>>) -> !fir.box> ! CHECK: fir.call @_QPtakes_assumed(%[[VAL_3]]) {{.*}} : (!fir.box>) -> () @@ -40,7 +40,7 @@ subroutine test_ptr_to_contiguous_assumed(p) call takes_contiguous_assumed(p) end subroutine ! CHECK-LABEL: func.func @_QPtest_ptr_to_contiguous_assumed( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_ptr_to_contiguous_assumedEp"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_ptr_to_contiguous_assumedEp"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]]:2 = hlfir.copy_in %[[VAL_2]] : (!fir.box>>) -> (!fir.box>>, i1) ! CHECK: %[[VAL_4:.*]] = fir.rebox %[[VAL_3]]#0 : (!fir.box>>) -> !fir.box> @@ -57,7 +57,7 @@ subroutine test_ptr_to_contiguous_assumed_classstar(p) call takes_contiguous_assumed_classstar(p) end subroutine ! CHECK-LABEL: func.func @_QPtest_ptr_to_contiguous_assumed_classstar( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_ptr_to_contiguous_assumed_classstarEp"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_ptr_to_contiguous_assumed_classstarEp"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]]:2 = hlfir.copy_in %[[VAL_2]] : (!fir.box>>) -> (!fir.box>>, i1) ! CHECK: %[[VAL_4:.*]] = fir.rebox %[[VAL_3]]#0 : (!fir.box>>) -> !fir.class> @@ -74,7 +74,7 @@ subroutine test_ptr_to_assumed_typestar(p) call takes_assumed_typestar(p) end subroutine ! CHECK-LABEL: func.func @_QPtest_ptr_to_assumed_typestar( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_ptr_to_assumed_typestarEp"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_ptr_to_assumed_typestarEp"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]] = fir.rebox %[[VAL_2]] : (!fir.box>>) -> !fir.box> ! CHECK: fir.call @_QPtakes_assumed_typestar(%[[VAL_3]]) {{.*}} : (!fir.box>) -> () @@ -94,7 +94,7 @@ end subroutine ! CHECK: %[[VAL_2:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_4:.*]] = arith.constant 20 : index ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_4]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_3]](%[[VAL_5:[a-z0-9]*]]) typeparams %[[VAL_2:[a-z0-9]*]] {uniq_name = "_QFtest_explicit_char_to_boxEe"} : (!fir.ref>>, !fir.shape<1>, index) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_3]](%[[VAL_5:[a-z0-9]*]]) typeparams %[[VAL_2:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_explicit_char_to_boxEe"} : (!fir.ref>>, !fir.shape<1>, index, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.ref>>, !fir.shape<1>) -> !fir.box>> ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (!fir.box>>) -> !fir.box>> ! CHECK: fir.call @_QPtakes_assumed_character(%[[VAL_8]]) {{.*}} : (!fir.box>>) -> () @@ -109,7 +109,7 @@ subroutine test_explicit_by_val(x) call takes_explicit_by_value(x) end subroutine ! CHECK-LABEL: func.func @_QPtest_explicit_by_val( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]](%[[VAL_2:[a-z0-9]*]]) {uniq_name = "_QFtest_explicit_by_valEx"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]](%[[VAL_2:[a-z0-9]*]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_explicit_by_valEx"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = hlfir.as_expr %[[VAL_3]]#0 : (!fir.ref>) -> !hlfir.expr<10xf32> ! CHECK: %[[VAL_5:.*]]:3 = hlfir.associate %[[VAL_4]](%[[VAL_2]]) {adapt.valuebyref} : (!hlfir.expr<10xf32>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>, i1) ! CHECK: fir.call @_QPtakes_explicit_by_value(%[[VAL_5]]#1) {{.*}} : (!fir.ref>) -> () diff --git a/flang/test/Lower/HLFIR/calls-constant-expr-arg.f90 b/flang/test/Lower/HLFIR/calls-constant-expr-arg.f90 index cfe8cf726045..7c8faf4fca8f 100644 --- a/flang/test/Lower/HLFIR/calls-constant-expr-arg.f90 +++ b/flang/test/Lower/HLFIR/calls-constant-expr-arg.f90 @@ -18,7 +18,7 @@ end subroutine sub ! CHECK-LABEL: func.func @_QPsub( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> {fir.bindc_name = "i"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "n"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFsubEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFsubEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (i32) -> i64 ! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (i64) -> index @@ -26,7 +26,7 @@ end subroutine sub ! CHECK: %[[VAL_7:.*]] = arith.cmpi sgt, %[[VAL_5]], %[[VAL_6]] : index ! CHECK: %[[VAL_8:.*]] = arith.select %[[VAL_7]], %[[VAL_5]], %[[VAL_6]] : index ! CHECK: %[[VAL_9:.*]] = fir.shape %[[VAL_8]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_9]]) {uniq_name = "_QFsubEi"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_9]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsubEi"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) ! CHECK: %[[VAL_11:.*]] = arith.constant 3 : index ! CHECK: %[[VAL_12:.*]] = arith.constant 2 : index ! CHECK: %[[VAL_13:.*]] = arith.constant 0 : index diff --git a/flang/test/Lower/HLFIR/calls-f77.f90 b/flang/test/Lower/HLFIR/calls-f77.f90 index cefe379a45d3..a970deb056f5 100644 --- a/flang/test/Lower/HLFIR/calls-f77.f90 +++ b/flang/test/Lower/HLFIR/calls-f77.f90 @@ -18,7 +18,7 @@ subroutine call_int_arg_var(n) end subroutine ! CHECK-LABEL: func.func @_QPcall_int_arg_var( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFcall_int_arg_varEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFcall_int_arg_varEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: fir.call @_QPtake_i4(%[[VAL_1]]#1) fastmath : (!fir.ref) -> () subroutine call_int_arg_expr() @@ -45,7 +45,7 @@ subroutine call_real_arg_var(x) end subroutine ! CHECK-LABEL: func.func @_QPcall_real_arg_var( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFcall_real_arg_varEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFcall_real_arg_varEx"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: fir.call @_QPtake_r4(%[[VAL_1]]#1) fastmath : (!fir.ref) -> () subroutine call_logical_arg_var(x) @@ -54,7 +54,7 @@ subroutine call_logical_arg_var(x) end subroutine ! CHECK-LABEL: func.func @_QPcall_logical_arg_var( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFcall_logical_arg_varEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFcall_logical_arg_varEx"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: fir.call @_QPtake_l4(%[[VAL_1]]#1) fastmath : (!fir.ref>) -> () subroutine call_logical_arg_expr() @@ -84,7 +84,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPcall_char_arg_var( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.boxchar<1> ! CHECK: %[[VAL_1:.*]]:2 = fir.unboxchar %[[VAL_0]] : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]]#0 typeparams %[[VAL_1]]#1 {uniq_name = "_QFcall_char_arg_varEx"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]]#0 typeparams %[[VAL_1]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFcall_char_arg_varEx"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: fir.call @_QPtake_c(%[[VAL_2]]#0) fastmath : (!fir.boxchar<1>) -> () subroutine call_char_arg_var_expr(x) @@ -94,7 +94,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPcall_char_arg_var_expr( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.boxchar<1> ! CHECK: %[[VAL_1:.*]]:2 = fir.unboxchar %[[VAL_0]] : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]]#0 typeparams %[[VAL_1]]#1 {uniq_name = "_QFcall_char_arg_var_exprEx"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]]#0 typeparams %[[VAL_1]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFcall_char_arg_var_exprEx"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_3:.*]] = arith.addi %[[VAL_1]]#1, %[[VAL_1]]#1 : index ! CHECK: %[[VAL_4:.*]] = hlfir.concat %[[VAL_2]]#0, %[[VAL_2]]#0 len %[[VAL_3]] : (!fir.boxchar<1>, !fir.boxchar<1>, index) -> !hlfir.expr> ! CHECK: %[[VAL_5:.*]]:3 = hlfir.associate %[[VAL_4]] typeparams %[[VAL_3]] {adapt.valuebyref} : (!hlfir.expr>, index) -> (!fir.boxchar<1>, !fir.ref>, i1) @@ -110,7 +110,7 @@ end subroutine ! CHECK: %[[VAL_1:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_2:.*]] = arith.constant 20 : index ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_1]], %[[VAL_2]] : (index, index) -> !fir.shape<2> -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_3]]) {uniq_name = "_QFcall_arg_array_varEn"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_3]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFcall_arg_array_varEn"} : (!fir.ref>, !fir.shape<2>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: fir.call @_QPtake_arr(%[[VAL_4]]#1) fastmath : (!fir.ref>) -> () subroutine call_arg_array_2(n) @@ -119,7 +119,7 @@ subroutine call_arg_array_2(n) end subroutine ! CHECK-LABEL: func.func @_QPcall_arg_array_2( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFcall_arg_array_2En"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFcall_arg_array_2En"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]]#1 : (!fir.box>) -> !fir.ref> ! CHECK: fir.call @_QPtake_arr_2(%[[VAL_2]]) fastmath : (!fir.ref>) -> () diff --git a/flang/test/Lower/HLFIR/calls-optional.f90 b/flang/test/Lower/HLFIR/calls-optional.f90 index df9519a24fb7..1ada5b198aed 100644 --- a/flang/test/Lower/HLFIR/calls-optional.f90 +++ b/flang/test/Lower/HLFIR/calls-optional.f90 @@ -14,7 +14,7 @@ subroutine optional_copy_in_out(x) call takes_optional_explicit(x) end subroutine ! CHECK-LABEL: func.func @_QPoptional_copy_in_out( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFoptional_copy_in_outEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFoptional_copy_in_outEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = fir.is_present %[[VAL_1]]#0 : (!fir.box>) -> i1 ! CHECK: %[[VAL_3:.*]]:4 = fir.if %[[VAL_2]] -> (!fir.ref>, !fir.box>, i1, !fir.box>) { ! CHECK: %[[VAL_4:.*]]:2 = hlfir.copy_in %[[VAL_1]]#0 : (!fir.box>) -> (!fir.box>, i1) @@ -40,7 +40,7 @@ subroutine optional_value_copy(x) call takes_optional_explicit_value(x) end subroutine ! CHECK-LABEL: func.func @_QPoptional_value_copy( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]](%[[VAL_2:[a-z0-9]*]]) {fortran_attrs = #fir.var_attrs, uniq_name = "_QFoptional_value_copyEx"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]](%[[VAL_2:[a-z0-9]*]]) dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFoptional_value_copyEx"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = fir.is_present %[[VAL_3]]#0 : (!fir.ref>) -> i1 ! CHECK: %[[VAL_5:.*]]:3 = fir.if %[[VAL_4]] -> (!fir.ref>, !fir.ref>, i1) { ! CHECK: %[[VAL_6:.*]] = hlfir.as_expr %[[VAL_3]]#0 : (!fir.ref>) -> !hlfir.expr<100xf32> @@ -66,8 +66,8 @@ subroutine elem_pointer_to_optional(x, y) call elem_takes_two_optional(x, y) end subroutine ! CHECK-LABEL: func.func @_QPelem_pointer_to_optional( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {uniq_name = "_QFelem_pointer_to_optionalEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFelem_pointer_to_optionalEy"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFelem_pointer_to_optionalEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFelem_pointer_to_optionalEy"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#1 : !fir.ref>>> ! CHECK: %[[VAL_5:.*]] = fir.box_addr %[[VAL_4]] : (!fir.box>>) -> !fir.ptr> ! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5]] : (!fir.ptr>) -> i64 @@ -105,7 +105,7 @@ subroutine optional_cannot_be_absent_optional(x) call elem_takes_one_optional(x) end subroutine ! CHECK-LABEL: func.func @_QPoptional_cannot_be_absent_optional( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFoptional_cannot_be_absent_optionalEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFoptional_cannot_be_absent_optionalEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_3:.*]]:3 = fir.box_dims %[[VAL_1]]#0, %[[VAL_2]] : (!fir.box>, index) -> (index, index, index) ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : index @@ -125,8 +125,8 @@ subroutine optional_elem_poly(x, y) call elem_optional_poly(x, y) end subroutine ! CHECK-LABEL: func.func @_QPoptional_elem_poly( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {uniq_name = "_QFoptional_elem_polyEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFoptional_elem_polyEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFoptional_elem_polyEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFoptional_elem_polyEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_4:.*]] = fir.is_present %[[VAL_3]]#0 : (!fir.box>) -> i1 ! CHECK: %[[VAL_5:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_6:.*]]:3 = fir.box_dims %[[VAL_2]]#0, %[[VAL_5]] : (!fir.box>, index) -> (index, index, index) diff --git a/flang/test/Lower/HLFIR/calls-percent-val-ref.f90 b/flang/test/Lower/HLFIR/calls-percent-val-ref.f90 index c6acc42455f1..c8724e6d7bee 100644 --- a/flang/test/Lower/HLFIR/calls-percent-val-ref.f90 +++ b/flang/test/Lower/HLFIR/calls-percent-val-ref.f90 @@ -7,7 +7,7 @@ subroutine test_val_1(x) end subroutine ! CHECK-LABEL: func.func @_QPtest_val_1( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_val_1Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_val_1Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref ! CHECK: fir.call @_QPval1(%[[VAL_2]]) fastmath : (i32) -> () @@ -17,7 +17,7 @@ subroutine test_val_2(x) end subroutine ! CHECK-LABEL: func.func @_QPtest_val_2( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_val_2Ex"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_val_2Ex"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_2]] : (!fir.box>>) -> !fir.heap> ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]] : !fir.heap> @@ -32,7 +32,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest_ref_char( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.boxchar<1> {fir.bindc_name = "x"}) { ! CHECK: %[[VAL_1:.*]]:2 = fir.unboxchar %[[VAL_0]] : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]]#0 typeparams %[[VAL_1]]#1 {uniq_name = "_QFtest_ref_charEx"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]]#0 typeparams %[[VAL_1]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_ref_charEx"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_3:.*]]:2 = fir.unboxchar %[[VAL_2]]#0 : (!fir.boxchar<1>) -> (!fir.ref>, index) ! CHECK: fir.call @_QPref_char(%[[VAL_3]]#0) fastmath : (!fir.ref>) -> () @@ -42,7 +42,7 @@ subroutine test_ref_1(x) end subroutine ! CHECK-LABEL: func.func @_QPtest_ref_1( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_ref_1Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_ref_1Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: fir.call @_QPref1(%[[VAL_1]]#1) fastmath : (!fir.ref) -> () subroutine test_ref_2(x) @@ -51,7 +51,7 @@ subroutine test_ref_2(x) end subroutine ! CHECK-LABEL: func.func @_QPtest_ref_2( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_ref_2Ex"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_ref_2Ex"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_2]] : (!fir.box>>) -> !fir.ptr> ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ptr>) -> !fir.ref> @@ -63,7 +63,7 @@ subroutine test_skip_copy_in_out(x) end subroutine ! CHECK-LABEL: func.func @_QPtest_skip_copy_in_out( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_skip_copy_in_outEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_skip_copy_in_outEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]]#1 : (!fir.box>) -> !fir.ref> ! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> i64 ! CHECK: fir.call @_QPval3(%[[VAL_3]]) fastmath : (i64) -> () diff --git a/flang/test/Lower/HLFIR/calls-poly-to-assumed-type.f90 b/flang/test/Lower/HLFIR/calls-poly-to-assumed-type.f90 index b14f1bb1f443..05885e729f93 100644 --- a/flang/test/Lower/HLFIR/calls-poly-to-assumed-type.f90 +++ b/flang/test/Lower/HLFIR/calls-poly-to-assumed-type.f90 @@ -12,7 +12,7 @@ subroutine pass_poly_to_assumed_type_assumed_size(x) call assumed_type_assumed_size(x) end subroutine ! CHECK-LABEL: func.func @_QPpass_poly_to_assumed_type_assumed_size( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFpass_poly_to_assumed_type_assumed_sizeEx"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFpass_poly_to_assumed_type_assumed_sizeEx"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: %[[VAL_2:.*]]:2 = hlfir.copy_in %[[VAL_1]]#0 : (!fir.class>) -> (!fir.class>, i1) ! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_2]]#0 : (!fir.class>) -> !fir.ref> ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ref>) -> !fir.ref> diff --git a/flang/test/Lower/HLFIR/char_extremum.f03 b/flang/test/Lower/HLFIR/char_extremum.f03 index cc7b80184935..4996128a3753 100644 --- a/flang/test/Lower/HLFIR/char_extremum.f03 +++ b/flang/test/Lower/HLFIR/char_extremum.f03 @@ -8,11 +8,11 @@ end subroutine ! CHECK-LABEL: func.func @_QPmax1 ! CHECK: %[[VAL_0:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %{{.*}} : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_1:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_1:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_2:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %{{.*}} : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_3:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_3:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_4:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %{{.*}} : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_5:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_4]]#0 typeparams %[[VAL_4]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_5:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_4]]#0 typeparams %[[VAL_4]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_6:[a-zA-Z0-9_]*]] = hlfir.char_extremum max, %[[VAL_3]]#0, %[[VAL_5]]#0 : (!fir.boxchar<1>, !fir.boxchar<1>) -> !hlfir.expr> ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_1]]#0 : !hlfir.expr>, !fir.boxchar<1> ! CHECK: hlfir.destroy %[[VAL_6]] : !hlfir.expr> @@ -23,11 +23,11 @@ subroutine min1(c1, c2, c3) end subroutine ! CHECK-LABEL: func.func @_QPmin1 ! CHECK: %[[VAL_0:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %{{.*}} : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_1:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_1:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_2:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %{{.*}} : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_3:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_3:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_4:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %{{.*}} : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_5:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_4]]#0 typeparams %[[VAL_4]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_5:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_4]]#0 typeparams %[[VAL_4]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_6:[a-zA-Z0-9_]*]] = hlfir.char_extremum min, %[[VAL_3]]#0, %[[VAL_5]]#0 : (!fir.boxchar<1>, !fir.boxchar<1>) -> !hlfir.expr> ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_1]]#0 : !hlfir.expr>, !fir.boxchar<1> ! CHECK: hlfir.destroy %[[VAL_6]] : !hlfir.expr> @@ -43,19 +43,19 @@ end subroutine ! CHECK: %[[VAL_1:[a-zA-Z0-9_]*]] = fir.convert %[[VAL_0]]#0 : (!fir.ref>) -> !fir.ref>> ! CHECK: %[[VAL_C100:[a-zA-Z0-9_]*]] = arith.constant 100 : index ! CHECK: %[[VAL_2:[a-zA-Z0-9_]*]] = fir.shape %[[VAL_C100]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_3:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_2]]) typeparams %[[VAL_0]]#1 {{.*}} : (!fir.ref>>, !fir.shape<1>, index) -> (!fir.box>>, !fir.ref>>) +! CHECK: %[[VAL_3:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_2]]) typeparams %[[VAL_0]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>>, !fir.shape<1>, index, !fir.dscope) -> (!fir.box>>, !fir.ref>>) ! CHECK: %[[VAL_4:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %{{.*}} : (!fir.boxchar<1>) -> (!fir.ref>, index) ! CHECK: %[[VAL_5:[a-zA-Z0-9_]*]] = fir.convert %[[VAL_4]]#0 : (!fir.ref>) -> !fir.ref>> ! CHECK: %[[VAL_C10:[a-zA-Z0-9_]*]] = arith.constant 10 : index ! CHECK: %[[VAL_C100_0:[a-zA-Z0-9_]*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:[a-zA-Z0-9_]*]] = fir.shape %[[VAL_C100_0]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_5]](%[[VAL_6]]) typeparams %[[VAL_C10]] {{.*}} : (!fir.ref>>, !fir.shape<1>, index) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_5]](%[[VAL_6]]) typeparams %[[VAL_C10]] dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>>, !fir.shape<1>, index, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %{{.*}} : (!fir.boxchar<1>) -> (!fir.ref>, index) ! CHECK: %[[VAL_9:[a-zA-Z0-9_]*]] = fir.convert %[[VAL_8]]#0 : (!fir.ref>) -> !fir.ref>> ! CHECK: %[[VAL_C20:[a-zA-Z0-9_]*]] = arith.constant 20 : index ! CHECK: %[[VAL_C100_1:[a-zA-Z0-9_]*]] = arith.constant 100 : index ! CHECK: %[[VAL_10:[a-zA-Z0-9_]*]] = fir.shape %[[VAL_C100_1]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_11:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_9]](%[[VAL_10]]) typeparams %[[VAL_C20]] {{.*}} : (!fir.ref>>, !fir.shape<1>, index) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_11:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_9]](%[[VAL_10]]) typeparams %[[VAL_C20]] dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>>, !fir.shape<1>, index, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_C1:[a-zA-Z0-9_]*]] = arith.constant 1 : index ! CHECK: %[[VAL_12:[a-zA-Z0-9_]*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_C1]]) typeparams %[[VAL_C10]] : (!fir.ref>>, index, index) -> !fir.ref> ! CHECK: %[[VAL_C1_2:[a-zA-Z0-9_]*]] = arith.constant 1 : index @@ -76,19 +76,19 @@ end subroutine ! CHECK: %[[VAL_1:[a-zA-Z0-9_]*]] = fir.convert %[[VAL_0]]#0 : (!fir.ref>) -> !fir.ref>> ! CHECK: %[[VAL_C100:[a-zA-Z0-9_]*]] = arith.constant 100 : index ! CHECK: %[[VAL_2:[a-zA-Z0-9_]*]] = fir.shape %[[VAL_C100]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_3:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_2]]) typeparams %[[VAL_0]]#1 {{.*}} : (!fir.ref>>, !fir.shape<1>, index) -> (!fir.box>>, !fir.ref>>) +! CHECK: %[[VAL_3:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_2]]) typeparams %[[VAL_0]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>>, !fir.shape<1>, index, !fir.dscope) -> (!fir.box>>, !fir.ref>>) ! CHECK: %[[VAL_4:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %arg1 : (!fir.boxchar<1>) -> (!fir.ref>, index) ! CHECK: %[[VAL_5:[a-zA-Z0-9_]*]] = fir.convert %[[VAL_4]]#0 : (!fir.ref>) -> !fir.ref>> ! CHECK: %[[VAL_C10:[a-zA-Z0-9_]*]] = arith.constant 10 : index ! CHECK: %[[VAL_C100_0:[a-zA-Z0-9_]*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:[a-zA-Z0-9_]*]] = fir.shape %[[VAL_C100_0]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_5]](%[[VAL_6]]) typeparams %[[VAL_C10]] {{.*}} : (!fir.ref>>, !fir.shape<1>, index) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_5]](%[[VAL_6]]) typeparams %[[VAL_C10]] dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>>, !fir.shape<1>, index, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %arg2 : (!fir.boxchar<1>) -> (!fir.ref>, index) ! CHECK: %[[VAL_C9:[a-zA-Z0-9_]*]] = fir.convert %[[VAL_8]]#0 : (!fir.ref>) -> !fir.ref>> ! CHECK: %[[VAL_C20:[a-zA-Z0-9_]*]] = arith.constant 20 : index ! CHECK: %[[VAL_C100_1:[a-zA-Z0-9_]*]] = arith.constant 100 : index ! CHECK: %[[VAL_10:[a-zA-Z0-9_]*]] = fir.shape %[[VAL_C100_1]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_11:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_C9]](%[[VAL_10]]) typeparams %[[VAL_C20]] {{.*}} : (!fir.ref>>, !fir.shape<1>, index) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_11:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_C9]](%[[VAL_10]]) typeparams %[[VAL_C20]] dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>>, !fir.shape<1>, index, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_C1:[a-zA-Z0-9_]*]] = arith.constant 1 : index ! CHECK: %[[VAL_12:[a-zA-Z0-9_]*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_C1]]) typeparams %[[VAL_C10]] : (!fir.ref>>, index, index) -> !fir.ref> ! CHECK: %[[VAL_C1_2:[a-zA-Z0-9_]*]] = arith.constant 1 : index @@ -105,13 +105,13 @@ subroutine max3(c1, c2, c3, c4) end subroutine ! CHECK-LABEL: func.func @_QPmax3 ! CHECK: %[[VAL_0:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %arg0 : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_1:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_1:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_2:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %arg1 : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_3:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_3:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_4:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %arg2 : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_5:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_4]]#0 typeparams %[[VAL_4]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_5:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_4]]#0 typeparams %[[VAL_4]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_6:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %arg3 : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_7:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_6]]#0 typeparams %[[VAL_6]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_7:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_6]]#0 typeparams %[[VAL_6]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_8:[a-zA-Z0-9_]*]] = hlfir.char_extremum max, %[[VAL_3]]#0, %[[VAL_5]]#0, %[[VAL_7]]#0 : (!fir.boxchar<1>, !fir.boxchar<1>, !fir.boxchar<1>) -> !hlfir.expr> ! CHECK: hlfir.assign %[[VAL_8]] to %[[VAL_1]]#0 : !hlfir.expr>, !fir.boxchar<1> ! CHECK: hlfir.destroy %[[VAL_8]] : !hlfir.expr> @@ -122,13 +122,13 @@ subroutine min3(c1, c2, c3, c4) end subroutine ! CHECK-LABEL: func.func @_QPmin3 ! CHECK: %[[VAL_0:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %arg0 : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_1:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_1:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_2:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %arg1 : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_3:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_3:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_4:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %arg2 : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_5:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_4]]#0 typeparams %[[VAL_4]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_5:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_4]]#0 typeparams %[[VAL_4]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_6:[a-zA-Z0-9_]*]]:2 = fir.unboxchar %arg3 : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_7:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_6]]#0 typeparams %[[VAL_6]]#1 {{.*}} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_7:[a-zA-Z0-9_]*]]:2 = hlfir.declare %[[VAL_6]]#0 typeparams %[[VAL_6]]#1 dummy_scope %{{[0-9]+}} {{.*}} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_8:[a-zA-Z0-9_]*]] = hlfir.char_extremum min, %[[VAL_3]]#0, %[[VAL_5]]#0, %[[VAL_7]]#0 : (!fir.boxchar<1>, !fir.boxchar<1>, !fir.boxchar<1>) -> !hlfir.expr> ! CHECK: hlfir.assign %[[VAL_8]] to %[[VAL_1]]#0 : !hlfir.expr>, !fir.boxchar<1> ! CHECK: hlfir.destroy %[[VAL_8]] : !hlfir.expr> diff --git a/flang/test/Lower/HLFIR/charconvert.f90 b/flang/test/Lower/HLFIR/charconvert.f90 index 117fdc0d3ad4..45b0f356617a 100644 --- a/flang/test/Lower/HLFIR/charconvert.f90 +++ b/flang/test/Lower/HLFIR/charconvert.f90 @@ -13,7 +13,7 @@ subroutine charconvert1(c,n) end subroutine charconvert1 ! CHECK-LABEL: func.func @_QPcharconvert1 -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFcharconvert1Ec"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFcharconvert1Ec"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: ^bb0(%[[ARG2:.*]]: index): ! CHECK: %[[VAL_37:.*]] = fir.box_elesize %[[VAL_2]]#1 : (!fir.box>>) -> index ! CHECK: %[[C4_4:.*]] = arith.constant 4 : index @@ -36,7 +36,7 @@ end subroutine charconvert2 ! CHECK: %[[C1:.*]] = arith.constant 1 : index ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.char<4> {bindc_name = "cx", uniq_name = "_QFcharconvert2Ecx"} ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] typeparams %[[C1]] {uniq_name = "_QFcharconvert2Ecx"} : (!fir.ref>, index) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFcharconvert2Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFcharconvert2Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref ! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (i32) -> i64 ! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5]] : (i64) -> i8 @@ -58,9 +58,9 @@ end subroutine ! CHECK-LABEL: func.func @_QPcharconvert3 ! CHECK-SAME: %[[ARG0:.*]]: !fir.boxchar<1> {{.*}}, %[[ARG1:.*]]: !fir.boxchar<4> ! CHECK: %[[VAL_0:.*]]:2 = fir.unboxchar %[[ARG0]] : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 {uniq_name = "_QFcharconvert3Ec"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFcharconvert3Ec"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_2:.*]]:2 = fir.unboxchar %[[ARG1]] : (!fir.boxchar<4>) -> (!fir.ref>, index) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 {uniq_name = "_QFcharconvert3Ec4"} : (!fir.ref>, index) -> (!fir.boxchar<4>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFcharconvert3Ec4"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<4>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = arith.addi %[[VAL_0]]#1, %[[VAL_0]]#1 : index ! CHECK: %[[VAL_5:.*]] = hlfir.concat %[[VAL_1]]#0, %[[VAL_1]]#0 len %[[VAL_4]] : (!fir.boxchar<1>, !fir.boxchar<1>, index) -> !hlfir.expr> ! CHECK: %[[VAL_7:.*]]:3 = hlfir.associate %[[VAL_5]] typeparams %[[VAL_4]] {adapt.valuebyref} : (!hlfir.expr>, index) -> (!fir.boxchar<1>, !fir.ref>, i1) diff --git a/flang/test/Lower/HLFIR/convert-mbox-to-value.f90 b/flang/test/Lower/HLFIR/convert-mbox-to-value.f90 index b9d55d3fde4f..ef9c12102a56 100644 --- a/flang/test/Lower/HLFIR/convert-mbox-to-value.f90 +++ b/flang/test/Lower/HLFIR/convert-mbox-to-value.f90 @@ -7,7 +7,7 @@ subroutine test_int_allocatable(a) end subroutine test_int_allocatable ! CHECK-LABEL: func.func @_QPtest_int_allocatable( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "a"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_int_allocatableEa"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_int_allocatableEa"} : (!fir.ref>>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_2:.*]] = arith.constant 6 : i32 ! CHECK: %[[VAL_3:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref> ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ref>) -> !fir.ref @@ -27,7 +27,7 @@ subroutine test_int_pointer(p) end subroutine test_int_pointer ! CHECK-LABEL: func.func @_QPtest_int_pointer( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "p"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_int_pointerEp"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_int_pointerEp"} : (!fir.ref>>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_2:.*]] = arith.constant 6 : i32 ! CHECK: %[[VAL_3:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref> ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ref>) -> !fir.ref @@ -49,7 +49,7 @@ end subroutine test_char_allocatable ! CHECK-LABEL: func.func @_QPtest_char_allocatable( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "a"}) { ! CHECK: %[[VAL_1:.*]] = arith.constant 11 : index -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_char_allocatableEa"} : (!fir.ref>>>, index) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_char_allocatableEa"} : (!fir.ref>>>, index, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFtest_char_allocatableEi"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFtest_char_allocatableEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_5:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref>>> @@ -86,7 +86,7 @@ end subroutine test_char_pointer ! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFtest_char_pointerEi"} ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest_char_pointerEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = arith.constant 11 : index -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_3]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_char_pointerEp"} : (!fir.ref>>>, index) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_3]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_char_pointerEp"} : (!fir.ref>>>, index, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_5:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref>>> ! CHECK: %[[VAL_6:.*]] = fir.box_addr %[[VAL_5]] : (!fir.box>>) -> !fir.ptr> ! CHECK: %[[VAL_3B:.*]] = arith.constant 11 : index @@ -120,7 +120,7 @@ end subroutine test_dyn_char_allocatable ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "a"}) { ! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> ! CHECK: %[[VAL_2:.*]] = fir.box_elesize %[[VAL_1]] : (!fir.box>>) -> index -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_2]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_dyn_char_allocatableEa"} : (!fir.ref>>>, index) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_2]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_dyn_char_allocatableEa"} : (!fir.ref>>>, index, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_4:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFtest_dyn_char_allocatableEi"} ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_4]] {uniq_name = "_QFtest_dyn_char_allocatableEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref>>> @@ -157,7 +157,7 @@ end subroutine test_dyn_char_pointer ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest_dyn_char_pointerEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> ! CHECK: %[[VAL_4:.*]] = fir.box_elesize %[[VAL_3]] : (!fir.box>>) -> index -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_4]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_dyn_char_pointerEp"} : (!fir.ref>>>, index) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_4]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_dyn_char_pointerEp"} : (!fir.ref>>>, index, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref>>> ! CHECK: %[[VAL_7:.*]] = fir.box_addr %[[VAL_6]] : (!fir.box>>) -> !fir.ptr> ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : index @@ -201,7 +201,7 @@ end subroutine test_derived_allocatable ! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]] : (!fir.heap>) -> !fir.class>> ! CHECK: fir.store %[[VAL_7]] to %[[VAL_5]] : !fir.ref>>> ! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare %[[VAL_5]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_derived_allocatableEa2"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) -! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_derived_allocatableEl"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_derived_allocatableEl"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_10:.*]] = fir.alloca !fir.class>> {bindc_name = "r", uniq_name = "_QFtest_derived_allocatableEr"} ! CHECK: %[[VAL_11:.*]] = fir.zero_bits !fir.heap> ! CHECK: %[[VAL_12:.*]] = fir.embox %[[VAL_11]] : (!fir.heap>) -> !fir.class>> @@ -241,7 +241,7 @@ end subroutine test_derived_pointer ! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]] : (!fir.heap>) -> !fir.class>> ! CHECK: fir.store %[[VAL_7]] to %[[VAL_5]] : !fir.ref>>> ! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare %[[VAL_5]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_derived_pointerEa2"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) -! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_derived_pointerEl"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_derived_pointerEl"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_10:.*]] = fir.alloca !fir.class>> {bindc_name = "r", uniq_name = "_QFtest_derived_pointerEr"} ! CHECK: %[[VAL_11:.*]] = fir.zero_bits !fir.heap> ! CHECK: %[[VAL_12:.*]] = fir.embox %[[VAL_11]] : (!fir.heap>) -> !fir.class>> diff --git a/flang/test/Lower/HLFIR/convert-variable-block.f90 b/flang/test/Lower/HLFIR/convert-variable-block.f90 index 30f8eacaaed1..dad6bc14fbdb 100644 --- a/flang/test/Lower/HLFIR/convert-variable-block.f90 +++ b/flang/test/Lower/HLFIR/convert-variable-block.f90 @@ -12,7 +12,7 @@ subroutine test(n) end subroutine ! CHECK-LABEL: func.func @_QPtest( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "n"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtestEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtestEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: fir.call @_QPbefore_block() {{.*}}: () -> () ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (i64) -> index diff --git a/flang/test/Lower/HLFIR/convert-variable.f90 b/flang/test/Lower/HLFIR/convert-variable.f90 index e7487ef870d1..7acb1be578b9 100644 --- a/flang/test/Lower/HLFIR/convert-variable.f90 +++ b/flang/test/Lower/HLFIR/convert-variable.f90 @@ -6,7 +6,7 @@ subroutine scalar_numeric(x) end subroutine ! CHECK-LABEL: func.func @_QPscalar_numeric( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref -! CHECK: %[[VAL_1:.*]] = hlfir.declare %[[VAL_0]] {uniq_name = "_QFscalar_numericEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]] = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFscalar_numericEx"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) subroutine scalar_character(c) character(*) :: c @@ -14,7 +14,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPscalar_character( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.boxchar<1> ! CHECK: %[[VAL_1:.*]]:2 = fir.unboxchar %[[VAL_0]] : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_2:.*]] = hlfir.declare %[[VAL_1]]#0 typeparams %[[VAL_1]]#1 {uniq_name = "_QFscalar_characterEc"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_2:.*]] = hlfir.declare %[[VAL_1]]#0 typeparams %[[VAL_1]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFscalar_characterEc"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) subroutine scalar_character_cst_len(c) character(10) :: c @@ -24,7 +24,7 @@ end subroutine ! CHECK: %[[VAL_1:.*]]:2 = fir.unboxchar %[[VAL_0]] : (!fir.boxchar<1>) -> (!fir.ref>, index) ! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_1]]#0 : (!fir.ref>) -> !fir.ref> ! CHECK: %[[VAL_2:.*]] = arith.constant 10 : index -! CHECK: %[[VAL_4:.*]] = hlfir.declare %[[VAL_3]] typeparams %[[VAL_2]] {uniq_name = "_QFscalar_character_cst_lenEc"} : (!fir.ref>, index) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]] = hlfir.declare %[[VAL_3]] typeparams %[[VAL_2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFscalar_character_cst_lenEc"} : (!fir.ref>, index, !fir.dscope) -> (!fir.ref>, !fir.ref>) subroutine array_numeric(x) integer :: x(10, 20) @@ -34,7 +34,7 @@ end subroutine ! CHECK: %[[VAL_1:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_2:.*]] = arith.constant 20 : index ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_1]], %[[VAL_2]] : (index, index) -> !fir.shape<2> -! CHECK: %[[VAL_4:.*]] = hlfir.declare %[[VAL_0]](%[[VAL_3]]) {uniq_name = "_QFarray_numericEx"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]] = hlfir.declare %[[VAL_0]](%[[VAL_3]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFarray_numericEx"} : (!fir.ref>, !fir.shape<2>, !fir.dscope) -> (!fir.ref>, !fir.ref>) subroutine array_numeric_lbounds(x) @@ -47,7 +47,7 @@ end subroutine ! CHECK: %[[VAL_3:.*]] = arith.constant -2 : index ! CHECK: %[[VAL_4:.*]] = arith.constant 23 : index ! CHECK: %[[VAL_5:.*]] = fir.shape_shift %[[VAL_1]], %[[VAL_2]], %[[VAL_3]], %[[VAL_4]] : (index, index, index, index) -> !fir.shapeshift<2> -! CHECK: %[[VAL_6:.*]] = hlfir.declare %[[VAL_0]](%[[VAL_5]]) {uniq_name = "_QFarray_numeric_lboundsEx"} : (!fir.ref>, !fir.shapeshift<2>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[VAL_6:.*]] = hlfir.declare %[[VAL_0]](%[[VAL_5]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFarray_numeric_lboundsEx"} : (!fir.ref>, !fir.shapeshift<2>, !fir.dscope) -> (!fir.box>, !fir.ref>) subroutine array_character(c) character(*) :: c(50) @@ -58,14 +58,14 @@ end subroutine ! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]]#0 : (!fir.ref>) -> !fir.ref>> ! CHECK: %[[VAL_3:.*]] = arith.constant 50 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]] = hlfir.declare %[[VAL_2]](%[[VAL_4]]) typeparams %[[VAL_1]]#1 {uniq_name = "_QFarray_characterEc"} : (!fir.ref>>, !fir.shape<1>, index) -> (!fir.box>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]] = hlfir.declare %[[VAL_2]](%[[VAL_4]]) typeparams %[[VAL_1]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFarray_characterEc"} : (!fir.ref>>, !fir.shape<1>, index, !fir.dscope) -> (!fir.box>>, !fir.ref>>) subroutine scalar_numeric_attributes(x) integer, optional, target, intent(in) :: x end subroutine ! CHECK-LABEL: func.func @_QPscalar_numeric_attributes( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref -! CHECK: %[[VAL_1:.*]] = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFscalar_numeric_attributesEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]] = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFscalar_numeric_attributesEx"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) subroutine scalar_numeric_attributes_2(x) real(16), value :: x(100) @@ -74,21 +74,21 @@ end subroutine ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> ! CHECK: %[[VAL_1:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_2:.*]] = fir.shape %[[VAL_1]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_3:.*]] = hlfir.declare %[[VAL_0]](%[[VAL_2]]) {fortran_attrs = #fir.var_attrs, uniq_name = "_QFscalar_numeric_attributes_2Ex"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]] = hlfir.declare %[[VAL_0]](%[[VAL_2]]) dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFscalar_numeric_attributes_2Ex"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) subroutine scalar_numeric_attributes_3(x) real, intent(in) :: x end subroutine ! CHECK-LABEL: func.func @_QPscalar_numeric_attributes_3( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref -! CHECK: %[[VAL_1:.*]] = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFscalar_numeric_attributes_3Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]] = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFscalar_numeric_attributes_3Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) subroutine scalar_numeric_attributes_4(x) logical(8), intent(out) :: x end subroutine ! CHECK-LABEL: func.func @_QPscalar_numeric_attributes_4( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> -! CHECK: %[[VAL_1:.*]] = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFscalar_numeric_attributes_4Ex"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_1:.*]] = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFscalar_numeric_attributes_4Ex"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) subroutine scalar_numeric_parameter() integer, parameter :: p = 42 diff --git a/flang/test/Lower/HLFIR/cray-pointers.f90 b/flang/test/Lower/HLFIR/cray-pointers.f90 index d969aa5d747a..ae903c8b44be 100644 --- a/flang/test/Lower/HLFIR/cray-pointers.f90 +++ b/flang/test/Lower/HLFIR/cray-pointers.f90 @@ -62,8 +62,8 @@ end subroutine test3 ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "cp"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "n"}) { ! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.box>>> -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest3En"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest3Ecp"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest3En"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest3Ecp"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_5:.*]] = arith.constant 11 : index ! CHECK: %[[VAL_8:.*]] = arith.constant 11 : index ! CHECK: %[[VAL_24:.*]] = fir.shape_shift %{{.*}}, %{{.*}} : (index, index) -> !fir.shapeshift<1> @@ -88,7 +88,7 @@ end subroutine test4 ! CHECK-LABEL: func.func @_QPtest4( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "n"}) { ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.box>> -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest4En"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest4En"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca i64 {bindc_name = "cp", uniq_name = "_QFtest4Ecp"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFtest4Ecp"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_5:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref @@ -153,7 +153,7 @@ end subroutine test6 ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "n"}) { ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.box>> ! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.box>>> -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest6En"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest6En"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.alloca i64 {bindc_name = "cp", uniq_name = "_QFtest6Ecp"} ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_4]] {uniq_name = "_QFtest6Ecp"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref @@ -379,7 +379,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest_craypointer_capture( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "n"}) { ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.box>> -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_craypointer_captureEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_craypointer_captureEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca i64 {bindc_name = "cray_pointer", uniq_name = "_QFtest_craypointer_captureEcray_pointer"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFtest_craypointer_captureEcray_pointer"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_5:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref diff --git a/flang/test/Lower/HLFIR/custom-intrinsic.f90 b/flang/test/Lower/HLFIR/custom-intrinsic.f90 index cf91ea332cdc..f4af94cfee2f 100644 --- a/flang/test/Lower/HLFIR/custom-intrinsic.f90 +++ b/flang/test/Lower/HLFIR/custom-intrinsic.f90 @@ -7,8 +7,9 @@ end function ! CHECK-LABEL: func.func @_QPmax_simple( ! CHECK-SAME: %[[A_ARG:.*]]: !fir.ref {fir.bindc_name = "a"} ! CHECK-SAME: %[[B_ARG:.*]]: !fir.ref {fir.bindc_name = "b"} -! CHECK-NEXT: %[[A_DECL:.*]]:2 = hlfir.declare %[[A_ARG]] {uniq_name = "_QFmax_simpleEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK-NEXT: %[[B_DECL:.*]]:2 = hlfir.declare %[[B_ARG]] {uniq_name = "_QFmax_simpleEb"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK-NEXT: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK-NEXT: %[[A_DECL:.*]]:2 = hlfir.declare %[[A_ARG]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFmax_simpleEa"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK-NEXT: %[[B_DECL:.*]]:2 = hlfir.declare %[[B_ARG]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFmax_simpleEb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK-NEXT: %[[RES_ALLOC:.*]] = fir.alloca i32 {bindc_name = "max_simple", uniq_name = "_QFmax_simpleEmax_simple"} ! CHECK-NEXT: %[[RES_DECL:.*]]:2 = hlfir.declare %[[RES_ALLOC]] {uniq_name = "_QFmax_simpleEmax_simple"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK-NEXT: %[[A_LD:.*]] = fir.load %[[A_DECL]]#0 : !fir.ref @@ -29,9 +30,9 @@ end function ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "a"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "b"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref {fir.bindc_name = "c", fir.optional}) -> i32 { -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFmax_dynamic_optional_scalarEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmax_dynamic_optional_scalarEb"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_2]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmax_dynamic_optional_scalarEc"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmax_dynamic_optional_scalarEa"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmax_dynamic_optional_scalarEb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_2]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmax_dynamic_optional_scalarEc"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.alloca i32 {bindc_name = "max_dynamic_optional_scalar", uniq_name = "_QFmax_dynamic_optional_scalarEmax_dynamic_optional_scalar"} ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = "_QFmax_dynamic_optional_scalarEmax_dynamic_optional_scalar"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref @@ -62,10 +63,10 @@ end function ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "b"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref {fir.bindc_name = "c", fir.optional}, ! CHECK-SAME: %[[VAL_3:.*]]: !fir.ref {fir.bindc_name = "d", fir.optional}) -> i32 { -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFmax_dynamic_optional_scalar2Ea"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmax_dynamic_optional_scalar2Eb"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_2]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmax_dynamic_optional_scalar2Ec"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_3]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmax_dynamic_optional_scalar2Ed"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmax_dynamic_optional_scalar2Ea"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmax_dynamic_optional_scalar2Eb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_2]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmax_dynamic_optional_scalar2Ec"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_3]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmax_dynamic_optional_scalar2Ed"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_8:.*]] = fir.alloca i32 {bindc_name = "max_dynamic_optional_scalar2", uniq_name = "_QFmax_dynamic_optional_scalar2Emax_dynamic_optional_scalar2"} ! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_8]] {uniq_name = "_QFmax_dynamic_optional_scalar2Emax_dynamic_optional_scalar2"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref @@ -104,10 +105,10 @@ end function ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "b"}) -> !fir.array<42xi32> { ! CHECK: %[[VAL_2:.*]] = arith.constant 42 : index ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_2]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_3]]) {uniq_name = "_QFmax_arrayEa"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_3]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmax_arrayEa"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 42 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_6]]) {uniq_name = "_QFmax_arrayEb"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmax_arrayEb"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_8:.*]] = arith.constant 42 : index ! CHECK: %[[VAL_9:.*]] = fir.alloca !fir.array<42xi32> {bindc_name = "max_array", uniq_name = "_QFmax_arrayEmax_array"} ! CHECK: %[[VAL_10:.*]] = fir.shape %[[VAL_8]] : (index) -> !fir.shape<1> @@ -137,13 +138,13 @@ end function ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "a"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "b"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref> {fir.bindc_name = "c", fir.optional}) -> !fir.array<10xi32> { -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFmax_dynamic_optional_arrayEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmax_dynamic_optional_arrayEa"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_4]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = "_QFmax_dynamic_optional_arrayEb"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmax_dynamic_optional_arrayEb"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_7:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_8:.*]] = fir.shape %[[VAL_7]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_2]](%[[VAL_8]]) {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmax_dynamic_optional_arrayEc"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_2]](%[[VAL_8]]) dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmax_dynamic_optional_arrayEc"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_10:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_11:.*]] = fir.alloca !fir.array<10xi32> {bindc_name = "max_dynamic_optional_array", uniq_name = "_QFmax_dynamic_optional_arrayEmax_dynamic_optional_array"} ! CHECK: %[[VAL_12:.*]] = fir.shape %[[VAL_10]] : (index) -> !fir.shape<1> @@ -180,8 +181,8 @@ end function ! CHECK-LABEL: func.func @_QPmin_simple( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "a"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "b"}) -> i32 { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFmin_simpleEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmin_simpleEb"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmin_simpleEa"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmin_simpleEb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.alloca i32 {bindc_name = "min_simple", uniq_name = "_QFmin_simpleEmin_simple"} ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_4]] {uniq_name = "_QFmin_simpleEmin_simple"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref @@ -202,9 +203,9 @@ end function ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "a"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "b"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref {fir.bindc_name = "c", fir.optional}) -> i32 { -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFmin_dynamic_optional_scalarEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmin_dynamic_optional_scalarEb"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_2]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmin_dynamic_optional_scalarEc"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmin_dynamic_optional_scalarEa"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmin_dynamic_optional_scalarEb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_2]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmin_dynamic_optional_scalarEc"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.alloca i32 {bindc_name = "min_dynamic_optional_scalar", uniq_name = "_QFmin_dynamic_optional_scalarEmin_dynamic_optional_scalar"} ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = "_QFmin_dynamic_optional_scalarEmin_dynamic_optional_scalar"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref @@ -235,10 +236,10 @@ end function ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "b"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref {fir.bindc_name = "c", fir.optional}, ! CHECK-SAME: %[[VAL_3:.*]]: !fir.ref {fir.bindc_name = "d", fir.optional}) -> i32 { -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFmin_dynamic_optional_scalar2Ea"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmin_dynamic_optional_scalar2Eb"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_2]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmin_dynamic_optional_scalar2Ec"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_3]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmin_dynamic_optional_scalar2Ed"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmin_dynamic_optional_scalar2Ea"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmin_dynamic_optional_scalar2Eb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_2]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmin_dynamic_optional_scalar2Ec"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_3]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmin_dynamic_optional_scalar2Ed"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_8:.*]] = fir.alloca i32 {bindc_name = "min_dynamic_optional_scalar2", uniq_name = "_QFmin_dynamic_optional_scalar2Emin_dynamic_optional_scalar2"} ! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_8]] {uniq_name = "_QFmin_dynamic_optional_scalar2Emin_dynamic_optional_scalar2"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref @@ -277,10 +278,10 @@ end function ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "b"}) -> !fir.array<42xi32> { ! CHECK: %[[VAL_2:.*]] = arith.constant 42 : index ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_2]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_3]]) {uniq_name = "_QFmin_arrayEa"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_3]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmin_arrayEa"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 42 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_6]]) {uniq_name = "_QFmin_arrayEb"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmin_arrayEb"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_8:.*]] = arith.constant 42 : index ! CHECK: %[[VAL_9:.*]] = fir.alloca !fir.array<42xi32> {bindc_name = "min_array", uniq_name = "_QFmin_arrayEmin_array"} ! CHECK: %[[VAL_10:.*]] = fir.shape %[[VAL_8]] : (index) -> !fir.shape<1> @@ -310,13 +311,13 @@ end function ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "a"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "b"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref> {fir.bindc_name = "c", fir.optional}) -> !fir.array<10xi32> { -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFmin_dynamic_optional_arrayEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmin_dynamic_optional_arrayEa"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_4]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = "_QFmin_dynamic_optional_arrayEb"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmin_dynamic_optional_arrayEb"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_7:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_8:.*]] = fir.shape %[[VAL_7]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_2]](%[[VAL_8]]) {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmin_dynamic_optional_arrayEc"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_2]](%[[VAL_8]]) dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFmin_dynamic_optional_arrayEc"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_10:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_11:.*]] = fir.alloca !fir.array<10xi32> {bindc_name = "min_dynamic_optional_array", uniq_name = "_QFmin_dynamic_optional_arrayEmin_dynamic_optional_array"} ! CHECK: %[[VAL_12:.*]] = fir.shape %[[VAL_10]] : (index) -> !fir.shape<1> @@ -355,7 +356,7 @@ end function ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "pointer"}) -> !fir.logical<4> { ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.logical<4> {bindc_name = "associated_simple", uniq_name = "_QFassociated_simpleEassociated_simple"} ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFassociated_simpleEassociated_simple"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_simpleEpointer"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_simpleEpointer"} : (!fir.ref>>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#1 : !fir.ref>> ! CHECK: %[[VAL_5:.*]] = fir.box_addr %[[VAL_4]] : (!fir.box>) -> !fir.ptr ! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5]] : (!fir.ptr) -> i64 @@ -378,8 +379,8 @@ end function ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "target", fir.target}) -> !fir.logical<4> { ! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "associated_target", uniq_name = "_QFassociated_targetEassociated_target"} ! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_2]] {uniq_name = "_QFassociated_targetEassociated_target"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_targetEpointer"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_targetEtarget"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_targetEpointer"} : (!fir.ref>>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_targetEtarget"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_6:.*]] = fir.embox %[[VAL_5]]#1 : (!fir.ref) -> !fir.box ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_4]]#1 : !fir.ref>> ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (!fir.box>) -> !fir.box @@ -402,8 +403,8 @@ end function ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref>> {fir.bindc_name = "target"}) -> !fir.logical<4> { ! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "associated_pointer", uniq_name = "_QFassociated_pointerEassociated_pointer"} ! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_2]] {uniq_name = "_QFassociated_pointerEassociated_pointer"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_pointerEpointer"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_pointerEtarget"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_pointerEpointer"} : (!fir.ref>>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_pointerEtarget"} : (!fir.ref>>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_5]]#1 : !fir.ref>> ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_4]]#1 : !fir.ref>> ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (!fir.box>) -> !fir.box @@ -426,8 +427,8 @@ end function ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref>>> {fir.bindc_name = "target"}) -> !fir.logical<4> { ! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "associated_array", uniq_name = "_QFassociated_arrayEassociated_array"} ! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_2]] {uniq_name = "_QFassociated_arrayEassociated_array"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_arrayEpointer"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_arrayEtarget"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_arrayEpointer"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFassociated_arrayEtarget"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_5]]#1 : !fir.ref>>> ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_4]]#1 : !fir.ref>>> ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (!fir.box>>) -> !fir.box @@ -447,11 +448,11 @@ end function ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "i"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "shift"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref {fir.bindc_name = "size"}) -> i32 { -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFishftc_simpleEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFishftc_simpleEi"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.alloca i32 {bindc_name = "ishftc_simple", uniq_name = "_QFishftc_simpleEishftc_simple"} ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_4]] {uniq_name = "_QFishftc_simpleEishftc_simple"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFishftc_simpleEshift"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_2]] {uniq_name = "_QFishftc_simpleEsize"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFishftc_simpleEshift"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFishftc_simpleEsize"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref ! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref ! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref @@ -498,11 +499,11 @@ end function ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "i"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "shift"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref {fir.bindc_name = "size", fir.optional}) -> i32 { -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFishftc_dynamically_optional_scalarEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFishftc_dynamically_optional_scalarEi"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.alloca i32 {bindc_name = "ishftc_dynamically_optional_scalar", uniq_name = "_QFishftc_dynamically_optional_scalarEishftc_dynamically_optional_scalar"} ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_4]] {uniq_name = "_QFishftc_dynamically_optional_scalarEishftc_dynamically_optional_scalar"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFishftc_dynamically_optional_scalarEshift"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_2]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFishftc_dynamically_optional_scalarEsize"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFishftc_dynamically_optional_scalarEshift"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_2]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFishftc_dynamically_optional_scalarEsize"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref ! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref ! CHECK: %[[VAL_10:.*]] = fir.is_present %[[VAL_7]]#0 : (!fir.ref) -> i1 @@ -557,17 +558,17 @@ end function ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref> {fir.bindc_name = "size"}) -> !fir.array<42xi32> { ! CHECK: %[[VAL_3:.*]] = arith.constant 42 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) {uniq_name = "_QFishftc_arrayEi"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFishftc_arrayEi"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_6:.*]] = arith.constant 42 : index ! CHECK: %[[VAL_7:.*]] = fir.alloca !fir.array<42xi32> {bindc_name = "ishftc_array", uniq_name = "_QFishftc_arrayEishftc_array"} ! CHECK: %[[VAL_8:.*]] = fir.shape %[[VAL_6]] : (index) -> !fir.shape<1> ! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_7]](%[[VAL_8]]) {uniq_name = "_QFishftc_arrayEishftc_array"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_10:.*]] = arith.constant 42 : index ! CHECK: %[[VAL_11:.*]] = fir.shape %[[VAL_10]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_11]]) {uniq_name = "_QFishftc_arrayEshift"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_11]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFishftc_arrayEshift"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_13:.*]] = arith.constant 42 : index ! CHECK: %[[VAL_14:.*]] = fir.shape %[[VAL_13]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_15:.*]]:2 = hlfir.declare %[[VAL_2]](%[[VAL_14]]) {uniq_name = "_QFishftc_arrayEsize"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_15:.*]]:2 = hlfir.declare %[[VAL_2]](%[[VAL_14]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFishftc_arrayEsize"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_16:.*]] = hlfir.elemental %[[VAL_4]] unordered : (!fir.shape<1>) -> !hlfir.expr<42xi32> { ! CHECK: ^bb0(%[[VAL_17:.*]]: index): ! CHECK: %[[VAL_18:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_17]]) : (!fir.ref>, index) -> !fir.ref @@ -624,13 +625,13 @@ end function ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref {fir.bindc_name = "size", fir.optional}) -> !fir.array<42xi32> { ! CHECK: %[[VAL_3:.*]] = arith.constant 42 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) {uniq_name = "_QFishftc_dynamically_optional_arrayEi"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFishftc_dynamically_optional_arrayEi"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_6:.*]] = arith.constant 42 : index ! CHECK: %[[VAL_7:.*]] = fir.alloca !fir.array<42xi32> {bindc_name = "ishftc_dynamically_optional_array", uniq_name = "_QFishftc_dynamically_optional_arrayEishftc_dynamically_optional_array"} ! CHECK: %[[VAL_8:.*]] = fir.shape %[[VAL_6]] : (index) -> !fir.shape<1> ! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_7]](%[[VAL_8]]) {uniq_name = "_QFishftc_dynamically_optional_arrayEishftc_dynamically_optional_array"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFishftc_dynamically_optional_arrayEshift"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_11:.*]]:2 = hlfir.declare %[[VAL_2]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFishftc_dynamically_optional_arrayEsize"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFishftc_dynamically_optional_arrayEshift"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_11:.*]]:2 = hlfir.declare %[[VAL_2]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFishftc_dynamically_optional_arrayEsize"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_12:.*]] = fir.is_present %[[VAL_11]]#0 : (!fir.ref) -> i1 ! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_10]]#0 : !fir.ref ! CHECK: %[[VAL_14:.*]] = hlfir.elemental %[[VAL_4]] unordered : (!fir.shape<1>) -> !hlfir.expr<42xi32> { @@ -698,9 +699,9 @@ end subroutine ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "a"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref>>> {fir.bindc_name = "b"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref>>> {fir.bindc_name = "c"}) { -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFallocatables_testEa"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFallocatables_testEb"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_2]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFallocatables_testEc"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFallocatables_testEa"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFallocatables_testEb"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_2]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFallocatables_testEc"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_6:.*]] = fir.address_of(@_QFallocatables_testECnx) : !fir.ref ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFallocatables_testECnx"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_8:.*]] = fir.address_of(@_QFallocatables_testECny) : !fir.ref @@ -840,4 +841,4 @@ end subroutine ! CHECK: hlfir.assign %[[VAL_136:.*]] to %[[VAL_5]]#0 realloc : !hlfir.expr, !fir.ref>>> ! CHECK: hlfir.destroy %[[VAL_136]] : !hlfir.expr ! CHECK: return -! CHECK: } \ No newline at end of file +! CHECK: } diff --git a/flang/test/Lower/HLFIR/designators-component-ref.f90 b/flang/test/Lower/HLFIR/designators-component-ref.f90 index 392eda66fd03..69cc7d2e5aa6 100644 --- a/flang/test/Lower/HLFIR/designators-component-ref.f90 +++ b/flang/test/Lower/HLFIR/designators-component-ref.f90 @@ -340,7 +340,7 @@ subroutine test_scalar_array_complex_chain(a) type(t_complex) :: a print *, a%array_comp%im ! CHECK-LABEL: func.func @_QPtest_scalar_array_complex_chain( -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_scalar_array_complex_chainEa"} : (!fir.ref>}>>) -> (!fir.ref>}>>, !fir.ref>}>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_scalar_array_complex_chainEa"} : (!fir.ref>}>>, !fir.dscope) -> (!fir.ref>}>>, !fir.ref>}>>) ! CHECK: %[[VAL_7:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_8:.*]] = arith.constant 20 : index ! CHECK: %[[VAL_9:.*]] = arith.constant 2 : index @@ -379,13 +379,13 @@ end subroutine test_poly_array_vector_subscript ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>>> {fir.bindc_name = "p"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "v"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref> {fir.bindc_name = "r"}) { -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_poly_array_vector_subscriptEp"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_poly_array_vector_subscriptEp"} : (!fir.ref>>>>, !fir.dscope) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK: %[[VAL_4:.*]] = arith.constant 3 : index ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_4]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_2]](%[[VAL_5]]) {uniq_name = "_QFtest_poly_array_vector_subscriptEr"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_2]](%[[VAL_5]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_poly_array_vector_subscriptEr"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_7:.*]] = arith.constant 3 : index ! CHECK: %[[VAL_8:.*]] = fir.shape %[[VAL_7]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_8]]) {uniq_name = "_QFtest_poly_array_vector_subscriptEv"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_8]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_poly_array_vector_subscriptEv"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref>>>> ! CHECK: %[[VAL_11:.*]] = hlfir.elemental %[[VAL_8]] unordered : (!fir.shape<1>) -> !hlfir.expr<3xi64> { ! CHECK: ^bb0(%[[VAL_12:.*]]: index): diff --git a/flang/test/Lower/HLFIR/designators.f90 b/flang/test/Lower/HLFIR/designators.f90 index de1ec6e5b3cf..09753d06cc27 100644 --- a/flang/test/Lower/HLFIR/designators.f90 +++ b/flang/test/Lower/HLFIR/designators.f90 @@ -7,8 +7,8 @@ subroutine array_ref(x, n) print *, x(n) end subroutine ! CHECK-LABEL: func.func @_QParray_ref( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFarray_refEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFarray_refEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFarray_refEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFarray_refEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref ! CHECK: %[[VAL_10:.*]] = hlfir.designate %[[VAL_3]]#0 (%[[VAL_9]]) : (!fir.box>, i64) -> !fir.ref @@ -17,8 +17,8 @@ subroutine char_array_ref(x, n) print *, x(10) end subroutine ! CHECK-LABEL: func.func @_QPchar_array_ref( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFchar_array_refEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFchar_array_refEx"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFchar_array_refEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFchar_array_refEx"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_9:.*]] = fir.box_elesize %[[VAL_3]]#1 : (!fir.box>>) -> index ! CHECK: %[[VAL_10:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_11:.*]] = hlfir.designate %[[VAL_3]]#0 (%[[VAL_10]]) typeparams %[[VAL_9]] : (!fir.box>>, index, index) -> !fir.boxchar<1> @@ -28,9 +28,9 @@ subroutine char_array_ref_cst_len(x, n) print *, x(10) end subroutine ! CHECK-LABEL: func.func @_QPchar_array_ref_cst_len( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFchar_array_ref_cst_lenEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFchar_array_ref_cst_lenEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = arith.constant 5 : index -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}} typeparams %[[VAL_3]] {uniq_name = "_QFchar_array_ref_cst_lenEx"} : (!fir.box>>, index) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}} typeparams %[[VAL_3]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFchar_array_ref_cst_lenEx"} : (!fir.box>>, index, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_10:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_11:.*]] = hlfir.designate %[[VAL_4]]#0 (%[[VAL_10]]) typeparams %[[VAL_3]] : (!fir.box>>, index, index) -> !fir.ref> @@ -41,7 +41,7 @@ end subroutine ! CHECK-LABEL: func.func @_QParray_section( ! CHECK: %[[VAL_1:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_2:.*]] = fir.shape %[[VAL_1]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}(%[[VAL_2]]) {uniq_name = "_QFarray_sectionEx"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}(%[[VAL_2]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFarray_sectionEx"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_9:.*]] = arith.constant 2 : index ! CHECK: %[[VAL_10:.*]] = arith.constant 8 : index ! CHECK: %[[VAL_11:.*]] = arith.constant 3 : index @@ -55,8 +55,8 @@ subroutine array_section_2(x, n) print *, x(n::3) end subroutine ! CHECK-LABEL: func.func @_QParray_section_2( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFarray_section_2En"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFarray_section_2Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFarray_section_2En"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFarray_section_2Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref ! CHECK: %[[VAL_10:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_11:.*]]:3 = fir.box_dims %[[VAL_3]]#1, %[[VAL_10]] : (!fir.box>, index) -> (index, index, index) @@ -76,8 +76,8 @@ subroutine char_array_section(x, n) print *, x(::3) end subroutine ! CHECK-LABEL: func.func @_QPchar_array_section( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFchar_array_sectionEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFchar_array_sectionEx"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFchar_array_sectionEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFchar_array_sectionEx"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_9:.*]] = fir.box_elesize %[[VAL_3]]#1 : (!fir.box>>) -> index ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : index ! CHECK: %[[VAL_11:.*]] = arith.constant 0 : index @@ -97,9 +97,9 @@ subroutine char_array_section_cst_len(x, n) print *, x(::3) end subroutine ! CHECK-LABEL: func.func @_QPchar_array_section_cst_len( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFchar_array_section_cst_lenEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFchar_array_section_cst_lenEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = arith.constant 5 : index -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}} typeparams %[[VAL_3]] {uniq_name = "_QFchar_array_section_cst_lenEx"} : (!fir.box>>, index) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}} typeparams %[[VAL_3]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFchar_array_section_cst_lenEx"} : (!fir.box>>, index, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : index ! CHECK: %[[VAL_11:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_12:.*]]:3 = fir.box_dims %[[VAL_4]]#1, %[[VAL_11]] : (!fir.box>>, index) -> (index, index, index) @@ -120,7 +120,7 @@ subroutine complex_imag_ref(x) print *, x%im end subroutine ! CHECK-LABEL: func.func @_QPcomplex_imag_ref( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFcomplex_imag_refEx"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFcomplex_imag_refEx"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_4:.*]]#1 : (index) -> !fir.shape<1> ! CHECK: %[[VAL_5:.*]] = hlfir.designate %[[VAL_2]]#0 imag shape %[[VAL_3]] : (!fir.box>>, !fir.shape<1>) -> !fir.box> @@ -129,7 +129,7 @@ subroutine complex_real_ref(x) print *, x%re end subroutine ! CHECK-LABEL: func.func @_QPcomplex_real_ref( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFcomplex_real_refEx"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFcomplex_real_refEx"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_4:.*]]#1 : (index) -> !fir.shape<1> ! CHECK: %[[VAL_5:.*]] = hlfir.designate %[[VAL_2]]#0 real shape %[[VAL_3]] : (!fir.box>>, !fir.shape<1>) -> !fir.box> @@ -139,11 +139,11 @@ subroutine complex_individual_ref(x, n) print *, x(n)%im end subroutine ! CHECK-LABEL: func.func @_QPcomplex_individual_ref( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFcomplex_individual_refEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFcomplex_individual_refEx"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFcomplex_individual_refEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFcomplex_individual_refEx"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref ! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (i32) -> i64 -! CHECK: %[[VAL_6:.*]] = hlfir.designate %1#0 (%[[VAL_5]]) imag : (!fir.box>>, i64) -> !fir.ref +! CHECK: %[[VAL_6:.*]] = hlfir.designate %{{[0-9]+}}#0 (%[[VAL_5]]) imag : (!fir.box>>, i64) -> !fir.ref subroutine complex_slice_ref(x, start, end) complex :: x(:) @@ -151,9 +151,9 @@ subroutine complex_slice_ref(x, start, end) print *, x(start:end)%re end subroutine ! CHECK-LABEL: func.func @_QPcomplex_slice_ref( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFcomplex_slice_refEend"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFcomplex_slice_refEstart"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %arg0 {uniq_name = "_QFcomplex_slice_refEx"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFcomplex_slice_refEend"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFcomplex_slice_refEstart"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %arg0 dummy_scope %{{[0-9]+}} {uniq_name = "_QFcomplex_slice_refEx"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_5:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref ! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5]] : (i32) -> i64 ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref diff --git a/flang/test/Lower/HLFIR/dot_product.f90 b/flang/test/Lower/HLFIR/dot_product.f90 index 890dc4abca49..2d3ee97b7e40 100644 --- a/flang/test/Lower/HLFIR/dot_product.f90 +++ b/flang/test/Lower/HLFIR/dot_product.f90 @@ -72,10 +72,10 @@ endsubroutine ! CHECK-NEXT: } ! CHECK-LABEL: func.func @_QPdot_product5 -! CHECK: %[[LHS:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFdot_product5Elhs"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[LHS:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFdot_product5Elhs"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[C3:.*]] = arith.constant 3 : index ! CHECK: %[[RHS_SHAPE:.*]] = fir.shape %[[C3]] : (index) -> !fir.shape<1> -! CHECK: %[[RHS:.*]]:2 = hlfir.declare %{{.*}}(%[[RHS_SHAPE]]) {uniq_name = "_QFdot_product5Erhs"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[RHS:.*]]:2 = hlfir.declare %{{.*}}(%[[RHS_SHAPE]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFdot_product5Erhs"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: {{.*}} = hlfir.dot_product %[[LHS]]#0 %[[RHS]]#0 {fastmath = #arith.fastmath} : (!fir.box>, !fir.ref>) -> i32 subroutine dot_product5(lhs, rhs, res) integer :: lhs(:), rhs(3) diff --git a/flang/test/Lower/HLFIR/elemental-array-ops.f90 b/flang/test/Lower/HLFIR/elemental-array-ops.f90 index 9778adeb6179..80801fdde0d7 100644 --- a/flang/test/Lower/HLFIR/elemental-array-ops.f90 +++ b/flang/test/Lower/HLFIR/elemental-array-ops.f90 @@ -166,9 +166,9 @@ end subroutine char_return ! CHECK: fir.store %[[VAL_7]] to %[[VAL_3]] : !fir.ref>>>> ! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare %[[VAL_3]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFchar_returnEl"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK: %[[VAL_9:.*]] = arith.constant 3 : index -! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_9]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFchar_returnEx"} : (!fir.box>>, index) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_9]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFchar_returnEx"} : (!fir.box>>, index, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_11:.*]] = arith.constant 3 : index -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_1]] typeparams %[[VAL_11]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFchar_returnEy"} : (!fir.box>>, index) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_1]] typeparams %[[VAL_11]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFchar_returnEy"} : (!fir.box>>, index, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_13:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_14:.*]]:3 = fir.box_dims %[[VAL_12]]#0, %[[VAL_13]] : (!fir.box>>, index) -> (index, index, index) ! CHECK: %[[VAL_15:.*]] = fir.shape %[[VAL_14]]#1 : (index) -> !fir.shape<1> @@ -225,8 +225,8 @@ end subroutine polymorphic_parenthesis ! CHECK-LABEL: func.func @_QPpolymorphic_parenthesis( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>>> {fir.bindc_name = "x"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.class>> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFpolymorphic_parenthesisEx"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFpolymorphic_parenthesisEy"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFpolymorphic_parenthesisEx"} : (!fir.ref>>>>, !fir.dscope) -> (!fir.ref>>>>, !fir.ref>>>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFpolymorphic_parenthesisEy"} : (!fir.class>>, !fir.dscope) -> (!fir.class>>, !fir.class>>) ! CHECK: %[[VAL_4:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_5:.*]]:3 = fir.box_dims %[[VAL_3]]#0, %[[VAL_4]] : (!fir.class>>, index) -> (index, index, index) ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]]#1 : (index) -> !fir.shape<1> @@ -249,8 +249,8 @@ end subroutine unlimited_polymorphic_parenthesis ! CHECK-LABEL: func.func @_QPunlimited_polymorphic_parenthesis( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.class> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFunlimited_polymorphic_parenthesisEx"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFunlimited_polymorphic_parenthesisEy"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFunlimited_polymorphic_parenthesisEx"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFunlimited_polymorphic_parenthesisEy"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: %[[VAL_4:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_5:.*]]:3 = fir.box_dims %[[VAL_3]]#0, %[[VAL_4]] : (!fir.class>, index) -> (index, index, index) ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]]#1 : (index) -> !fir.shape<1> diff --git a/flang/test/Lower/HLFIR/elemental-polymorphic-merge.f90 b/flang/test/Lower/HLFIR/elemental-polymorphic-merge.f90 index eb93099b3890..36762d47100c 100644 --- a/flang/test/Lower/HLFIR/elemental-polymorphic-merge.f90 +++ b/flang/test/Lower/HLFIR/elemental-polymorphic-merge.f90 @@ -14,10 +14,10 @@ end subroutine test_polymorphic_merge ! CHECK-SAME: %[[VAL_1:.*]]: !fir.class>> {fir.bindc_name = "y"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref>>>> {fir.bindc_name = "r"}, ! CHECK-SAME: %[[VAL_3:.*]]: !fir.box>> {fir.bindc_name = "m"}) { -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFtest_polymorphic_mergeEm"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_2]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_polymorphic_mergeEr"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_polymorphic_mergeEx"} : (!fir.class>) -> (!fir.class>, !fir.class>) -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_polymorphic_mergeEy"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_polymorphic_mergeEm"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_2]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_polymorphic_mergeEr"} : (!fir.ref>>>>, !fir.dscope) -> (!fir.ref>>>>, !fir.ref>>>>) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_polymorphic_mergeEx"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_polymorphic_mergeEy"} : (!fir.class>>, !fir.dscope) -> (!fir.class>>, !fir.class>>) ! CHECK: %[[VAL_8:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_9:.*]]:3 = fir.box_dims %[[VAL_7]]#0, %[[VAL_8]] : (!fir.class>>, index) -> (index, index, index) ! CHECK: %[[VAL_10:.*]] = fir.shape %[[VAL_9]]#1 : (index) -> !fir.shape<1> diff --git a/flang/test/Lower/HLFIR/elemental-user-procedure-ref.f90 b/flang/test/Lower/HLFIR/elemental-user-procedure-ref.f90 index d015ba3b0707..aea23d8d9467 100644 --- a/flang/test/Lower/HLFIR/elemental-user-procedure-ref.f90 +++ b/flang/test/Lower/HLFIR/elemental-user-procedure-ref.f90 @@ -111,7 +111,7 @@ end subroutine ! CHECK: %[[VAL_1:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_2:.*]] = arith.constant 20 : index ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_1]], %[[VAL_2]] : (index, index) -> !fir.shape<2> -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_3]]) {uniq_name = "_QFimpure_elementalEx"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_3]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFimpure_elementalEx"} : (!fir.ref>, !fir.shape<2>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 1 : index ! CHECK: fir.do_loop %[[VAL_6:.*]] = %[[VAL_5]] to %[[VAL_2]] step %[[VAL_5]] { ! CHECK: fir.do_loop %[[VAL_7:.*]] = %[[VAL_5]] to %[[VAL_1]] step %[[VAL_5]] { @@ -136,7 +136,7 @@ end subroutine ! CHECK: %[[VAL_1:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_2:.*]] = arith.constant 20 : index ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_1]], %[[VAL_2]] : (index, index) -> !fir.shape<2> -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_3]]) {uniq_name = "_QFordered_elementalEx"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_3]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFordered_elementalEx"} : (!fir.ref>, !fir.shape<2>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 1 : index ! CHECK: fir.do_loop %[[VAL_6:.*]] = %[[VAL_5]] to %[[VAL_2]] step %[[VAL_5]] { ! CHECK: fir.do_loop %[[VAL_7:.*]] = %[[VAL_5]] to %[[VAL_1]] step %[[VAL_5]] { @@ -161,7 +161,7 @@ end subroutine ! CHECK: %[[VAL_1:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_2:.*]] = arith.constant 20 : index ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_1]], %[[VAL_2]] : (index, index) -> !fir.shape<2> -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_3]]) {uniq_name = "_QFimpure_elemental_arg_evalEx"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_3]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFimpure_elemental_arg_evalEx"} : (!fir.ref>, !fir.shape<2>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = hlfir.elemental %[[VAL_3]] unordered : (!fir.shape<2>) -> !hlfir.expr<10x20xf32> { ! CHECK: ^bb0(%[[VAL_6:.*]]: index, %[[VAL_7:.*]]: index): ! CHECK: %[[VAL_8:.*]] = hlfir.designate %[[VAL_4]]#0 (%[[VAL_6]], %[[VAL_7]]) : (!fir.ref>, index, index) -> !fir.ref diff --git a/flang/test/Lower/HLFIR/expr-addr.f90 b/flang/test/Lower/HLFIR/expr-addr.f90 index 876aad8925d7..917a68d59910 100644 --- a/flang/test/Lower/HLFIR/expr-addr.f90 +++ b/flang/test/Lower/HLFIR/expr-addr.f90 @@ -6,7 +6,7 @@ subroutine foo(x) integer :: x read (*,*) x - ! CHECK: %[[x:.]]:2 = hlfir.declare %[[arg0]] {uniq_name = "_QFfooEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[x:.]]:2 = hlfir.declare %[[arg0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfooEx"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[x_cast:.*]] = fir.convert %[[x]]#1 : (!fir.ref) -> !fir.ref ! CHECK: fir.call @_FortranAioInputInteger(%{{.*}}, %[[x_cast]], %{{.*}}) {{.*}}: (!fir.ref, !fir.ref, i32) -> i1 end subroutine diff --git a/flang/test/Lower/HLFIR/expr-box.f90 b/flang/test/Lower/HLFIR/expr-box.f90 index e7ab006751a0..f0de381c7457 100644 --- a/flang/test/Lower/HLFIR/expr-box.f90 +++ b/flang/test/Lower/HLFIR/expr-box.f90 @@ -9,7 +9,7 @@ subroutine foo(x) ! CHECK-DAG: %[[VAL_3:.*]] = arith.constant 21 : index ! CHECK-DAG: %[[VAL_4:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_5:.*]] = fir.shape_shift %[[VAL_3]], %[[VAL_4]] : (index, index) -> !fir.shapeshift<1> -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_5]]) {uniq_name = "_QFfooEx"} : (!fir.ref>, !fir.shapeshift<1>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_5]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFfooEx"} : (!fir.ref>, !fir.shapeshift<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) ! CHECK: fir.embox %[[VAL_6]]#1(%[[VAL_5]]) : (!fir.ref>, !fir.shapeshift<1>) -> !fir.box> end subroutine diff --git a/flang/test/Lower/HLFIR/expr-value.f90 b/flang/test/Lower/HLFIR/expr-value.f90 index cd2f42533c27..c692ec72bf7e 100644 --- a/flang/test/Lower/HLFIR/expr-value.f90 +++ b/flang/test/Lower/HLFIR/expr-value.f90 @@ -11,7 +11,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPfoo_designator( ! CHECK-SAME: %[[arg0:.*]]: !fir.ref subroutine foo_designator(n) - !CHECK: %[[n:.*]]:2 = hlfir.declare %[[arg0]] {uniq_name = "_QFfoo_designatorEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) + !CHECK: %[[n:.*]]:2 = hlfir.declare %[[arg0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfoo_designatorEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) print *, n ! CHECK: %[[nval:.*]] = fir.load %[[n]]#0 : !fir.ref ! CHECK: fir.call @_FortranAioOutputInteger32(%{{.*}}, %[[nval]]) {{.*}}: (!fir.ref, i32) -> i1 diff --git a/flang/test/Lower/HLFIR/ignore-rank-unlimited-polymorphic.f90 b/flang/test/Lower/HLFIR/ignore-rank-unlimited-polymorphic.f90 index 43986c8198b9..c2118432a981 100644 --- a/flang/test/Lower/HLFIR/ignore-rank-unlimited-polymorphic.f90 +++ b/flang/test/Lower/HLFIR/ignore-rank-unlimited-polymorphic.f90 @@ -49,7 +49,7 @@ subroutine test_logical_assumed_shape_array(x) end subroutine test_logical_assumed_shape_array ! CHECK-LABEL: func.func @_QPtest_logical_assumed_shape_array( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_logical_assumed_shape_arrayEx"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_logical_assumed_shape_arrayEx"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_2:.*]] = fir.rebox %[[VAL_1]]#0 : (!fir.box>>) -> !fir.class> ! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.class>) -> !fir.class ! CHECK: fir.call @_QPcallee(%[[VAL_3]]) fastmath : (!fir.class) -> () @@ -63,7 +63,7 @@ subroutine test_real_2d_pointer(x) end subroutine test_real_2d_pointer ! CHECK-LABEL: func.func @_QPtest_real_2d_pointer( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_real_2d_pointerEx"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_real_2d_pointerEx"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]] = fir.rebox %[[VAL_2]] : (!fir.box>>) -> !fir.class> ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.class>) -> !fir.class @@ -78,7 +78,7 @@ subroutine test_up_assumed_shape_1d_array(x) end subroutine test_up_assumed_shape_1d_array ! CHECK-LABEL: func.func @_QPtest_up_assumed_shape_1d_array( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.class> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_up_assumed_shape_1d_arrayEx"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_up_assumed_shape_1d_arrayEx"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]]#0 : (!fir.class>) -> !fir.class ! CHECK: fir.call @_QPcallee(%[[VAL_2]]) fastmath : (!fir.class) -> () ! CHECK: return @@ -115,7 +115,7 @@ subroutine test_up_allocatable_2d_array(x) end subroutine test_up_allocatable_2d_array ! CHECK-LABEL: func.func @_QPtest_up_allocatable_2d_array( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_up_allocatable_2d_arrayEx"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_up_allocatable_2d_arrayEx"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]] = fir.rebox %[[VAL_2]] : (!fir.class>>) -> !fir.class> ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.class>) -> !fir.class @@ -130,7 +130,7 @@ subroutine test_up_pointer_1d_array(x) end subroutine test_up_pointer_1d_array ! CHECK-LABEL: func.func @_QPtest_up_pointer_1d_array( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_up_pointer_1d_arrayEx"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_up_pointer_1d_arrayEx"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> ! CHECK: %[[VAL_3:.*]] = fir.rebox %[[VAL_2]] : (!fir.class>>) -> !fir.class> ! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.class>) -> !fir.class diff --git a/flang/test/Lower/HLFIR/implicit-type-conversion.f90 b/flang/test/Lower/HLFIR/implicit-type-conversion.f90 index ec0fb6e3bb12..dc2d111a8f7f 100644 --- a/flang/test/Lower/HLFIR/implicit-type-conversion.f90 +++ b/flang/test/Lower/HLFIR/implicit-type-conversion.f90 @@ -3,8 +3,8 @@ ! CHECK-LABEL: func.func @_QPtest1( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "x"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest1Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest1Ey"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest1Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest1Ey"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref> ! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (!fir.logical<4>) -> i32 ! CHECK: hlfir.assign %[[VAL_5]] to %[[VAL_2]]#0 : i32, !fir.ref @@ -19,8 +19,8 @@ end subroutine test1 ! CHECK-LABEL: func.func @_QPtest2( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "x"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest2Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest2Ey"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest2Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest2Ey"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref ! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (i32) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_5]] to %[[VAL_3]]#0 : !fir.logical<4>, !fir.ref> @@ -35,8 +35,8 @@ end subroutine test2 ! CHECK-LABEL: func.func @_QPtest3( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> {fir.bindc_name = "x"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest3Ex"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest3Ey"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest3Ex"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest3Ey"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref ! CHECK: %[[VAL_5:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_6:.*]] = arith.cmpi eq, %[[VAL_4]], %[[VAL_5]] : i32 @@ -54,8 +54,8 @@ end subroutine test3 ! CHECK-LABEL: func.func @_QPtest4( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "x"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest4Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest4Ey"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest4Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest4Ey"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref ! CHECK: %[[VAL_5:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_6:.*]] = arith.cmpi eq, %[[VAL_4]], %[[VAL_5]] : i32 @@ -73,8 +73,8 @@ end subroutine test4 ! CHECK-LABEL: func.func @_QPtest5( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest5Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest5Ey"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest5Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest5Ey"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref> ! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (!fir.logical<4>) -> i32 ! CHECK: hlfir.assign %[[VAL_5]] to %[[VAL_2]]#0 : i32, !fir.box> @@ -89,8 +89,8 @@ end subroutine test5 ! CHECK-LABEL: func.func @_QPtest6( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.box>> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest6Ex"} : (!fir.box>) -> (!fir.box>, !fir.box>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest6Ey"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest6Ex"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest6Ey"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %[[VAL_4:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_5:.*]]:3 = fir.box_dims %[[VAL_3]]#0, %[[VAL_4]] : (!fir.box>>, index) -> (index, index, index) ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]]#1 : (index) -> !fir.shape<1> @@ -114,8 +114,8 @@ end subroutine test6 ! CHECK-LABEL: func.func @_QPtest7( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box>> {fir.bindc_name = "x"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.box> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest7Ex"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest7Ey"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest7Ex"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest7Ey"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_4:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_5:.*]]:3 = fir.box_dims %[[VAL_3]]#0, %[[VAL_4]] : (!fir.box>, index) -> (index, index, index) ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]]#1 : (index) -> !fir.shape<1> diff --git a/flang/test/Lower/HLFIR/intentout-allocatable-components.f90 b/flang/test/Lower/HLFIR/intentout-allocatable-components.f90 index 797e4c89ae23..9d4bedbd9be6 100644 --- a/flang/test/Lower/HLFIR/intentout-allocatable-components.f90 +++ b/flang/test/Lower/HLFIR/intentout-allocatable-components.f90 @@ -10,7 +10,7 @@ subroutine test_intentout_component_deallocate(a) end subroutine ! CHECK-LABEL: func.func @_QPtest_intentout_component_deallocate( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>}>> -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_intentout_component_deallocateEa"} +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_intentout_component_deallocateEa"} ! CHECK: %[[VAL_2:.*]] = fir.embox %[[VAL_1]]#1 : (!fir.ref>}>>) -> !fir.box>}>> ! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.box>}>>) -> !fir.box ! CHECK: %[[VAL_4:.*]] = fir.call @_FortranADestroy(%[[VAL_3]]) fastmath : (!fir.box) -> none @@ -23,7 +23,7 @@ subroutine test_intentout_optional_component_deallocate(a) end subroutine ! CHECK-LABEL: func.func @_QPtest_intentout_optional_component_deallocate( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>}>> -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_intentout_optional_component_deallocateEa"} +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_intentout_optional_component_deallocateEa"} ! CHECK: %[[VAL_2:.*]] = fir.is_present %[[VAL_1]]#1 : (!fir.ref>}>>) -> i1 ! CHECK: fir.if %[[VAL_2]] { ! CHECK: %[[VAL_3:.*]] = fir.embox %[[VAL_1]]#1 : (!fir.ref>}>>) -> !fir.box>}>> diff --git a/flang/test/Lower/HLFIR/internal-procedures.f90 b/flang/test/Lower/HLFIR/internal-procedures.f90 index 3c4439911809..f0df1a7f6e64 100644 --- a/flang/test/Lower/HLFIR/internal-procedures.f90 +++ b/flang/test/Lower/HLFIR/internal-procedures.f90 @@ -64,7 +64,7 @@ contains end subroutine ! CHECK-LABEL: func.func @_QPtest_proc_pointer( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>>) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointerEp"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointerEp"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) ! CHECK: %[[VAL_2:.*]] = fir.alloca tuple ()>>> ! CHECK: %[[VAL_3:.*]] = arith.constant 0 : i32 ! CHECK: %[[VAL_4:.*]] = fir.coordinate_of %[[VAL_2]], %[[VAL_3]] : (!fir.ref ()>>>>, i32) -> !fir.llvm_ptr ()>>> diff --git a/flang/test/Lower/HLFIR/intrinsic-dynamically-optional.f90 b/flang/test/Lower/HLFIR/intrinsic-dynamically-optional.f90 index 39671d7931a1..d1969049828c 100644 --- a/flang/test/Lower/HLFIR/intrinsic-dynamically-optional.f90 +++ b/flang/test/Lower/HLFIR/intrinsic-dynamically-optional.f90 @@ -166,10 +166,10 @@ end function ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "imaginary", fir.optional}) -> !fir.array<3x!fir.complex<4>> { ! CHECK: %[[VAL_2:.*]] = arith.constant 3 : index ! CHECK: %[[VAL_3:.*]] = fir.shape %[[VAL_2]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_3]]) {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_elemental_optional_as_valueEimaginary"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_3]]) dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_elemental_optional_as_valueEimaginary"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 3 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFtest_elemental_optional_as_valueEreal"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_elemental_optional_as_valueEreal"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_8:.*]] = arith.constant 3 : index ! CHECK: %[[VAL_9:.*]] = fir.alloca !fir.array<3x!fir.complex<4>> {bindc_name = "test_elemental_optional_as_value", uniq_name = "_QFtest_elemental_optional_as_valueEtest_elemental_optional_as_value"} ! CHECK: %[[VAL_10:.*]] = fir.shape %[[VAL_8]] : (index) -> !fir.shape<1> diff --git a/flang/test/Lower/HLFIR/issue80884.f90 b/flang/test/Lower/HLFIR/issue80884.f90 index 2a7792b6004c..725ed1982975 100644 --- a/flang/test/Lower/HLFIR/issue80884.f90 +++ b/flang/test/Lower/HLFIR/issue80884.f90 @@ -12,8 +12,8 @@ subroutine issue80884(p, targ) p(1:100) => targ%array end subroutine ! CHECK-LABEL: func.func @_QPissue80884( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFissue80884Ep"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFissue80884Etarg"} : (!fir.ref}>}>>) -> (!fir.ref}>}>>, !fir.ref}>}>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %{{.*}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFissue80884Ep"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFissue80884Etarg"} : (!fir.ref}>}>>, !fir.dscope) -> (!fir.ref}>}>>, !fir.ref}>}>>) ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i64 ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i64 ! CHECK: %[[VAL_6:.*]] = hlfir.designate %[[VAL_3]]#0{"t0"} : (!fir.ref}>}>>) -> !fir.ref}>> diff --git a/flang/test/Lower/HLFIR/maxloc.f90 b/flang/test/Lower/HLFIR/maxloc.f90 index ea3cce92ae90..166a1b9db172 100644 --- a/flang/test/Lower/HLFIR/maxloc.f90 +++ b/flang/test/Lower/HLFIR/maxloc.f90 @@ -357,11 +357,12 @@ subroutine scalar_dim1(a, d, m, b, s) end subroutine ! CHECK-LABEL: func.func @_QPscalar_dim1( ! CHECK: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.ref {fir.bindc_name = "d"}, %[[ARG2:.*]]: !fir.box>> {fir.bindc_name = "m"}, %[[ARG3:.*]]: !fir.ref> {fir.bindc_name = "b"}, %[[ARG4:.*]]: !fir.box> {fir.bindc_name = "s"}) { -! CHECK-NEXT: %[[V0:.*]]:2 = hlfir.declare %[[ARG0]] -! CHECK-NEXT: %[[V1:.*]]:2 = hlfir.declare %[[ARG3]] -! CHECK-NEXT: %[[V2:.*]]:2 = hlfir.declare %[[ARG1]] -! CHECK-NEXT: %[[V3:.*]]:2 = hlfir.declare %[[ARG2]] -! CHECK-NEXT: %[[V4:.*]]:2 = hlfir.declare %[[ARG4]] +! CHECK-NEXT: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK-NEXT: %[[V0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %[[DSCOPE]] +! CHECK-NEXT: %[[V1:.*]]:2 = hlfir.declare %[[ARG3]] dummy_scope %[[DSCOPE]] +! CHECK-NEXT: %[[V2:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %[[DSCOPE]] +! CHECK-NEXT: %[[V3:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %[[DSCOPE]] +! CHECK-NEXT: %[[V4:.*]]:2 = hlfir.declare %[[ARG4]] dummy_scope %[[DSCOPE]] ! CHECK-NEXT: %[[V5:.*]] = fir.load %[[V1]]#0 : !fir.ref> ! CHECK-NEXT: %[[V6:.*]] = fir.load %[[V2]]#0 : !fir.ref ! CHECK-NEXT: %[[V7:.*]] = hlfir.maxloc %[[V0]]#0 dim %[[V6]] mask %[[V3]]#0 back %[[V5]] {fastmath = #arith.fastmath} : (!fir.box>, i32, !fir.box>>, !fir.logical<4>) -> i16 diff --git a/flang/test/Lower/HLFIR/minloc.f90 b/flang/test/Lower/HLFIR/minloc.f90 index c27430689ee0..f835cf54b2a7 100644 --- a/flang/test/Lower/HLFIR/minloc.f90 +++ b/flang/test/Lower/HLFIR/minloc.f90 @@ -357,11 +357,12 @@ subroutine scalar_dim1(a, d, m, b, s) end subroutine ! CHECK-LABEL: func.func @_QPscalar_dim1( ! CHECK: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.ref {fir.bindc_name = "d"}, %[[ARG2:.*]]: !fir.box>> {fir.bindc_name = "m"}, %[[ARG3:.*]]: !fir.ref> {fir.bindc_name = "b"}, %[[ARG4:.*]]: !fir.box> {fir.bindc_name = "s"}) { -! CHECK-NEXT: %[[V0:.*]]:2 = hlfir.declare %[[ARG0]] -! CHECK-NEXT: %[[V1:.*]]:2 = hlfir.declare %[[ARG3]] -! CHECK-NEXT: %[[V2:.*]]:2 = hlfir.declare %[[ARG1]] -! CHECK-NEXT: %[[V3:.*]]:2 = hlfir.declare %[[ARG2]] -! CHECK-NEXT: %[[V4:.*]]:2 = hlfir.declare %[[ARG4]] +! CHECK-NEXT: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK-NEXT: %[[V0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %[[DSCOPE]] +! CHECK-NEXT: %[[V1:.*]]:2 = hlfir.declare %[[ARG3]] dummy_scope %[[DSCOPE]] +! CHECK-NEXT: %[[V2:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %[[DSCOPE]] +! CHECK-NEXT: %[[V3:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %[[DSCOPE]] +! CHECK-NEXT: %[[V4:.*]]:2 = hlfir.declare %[[ARG4]] dummy_scope %[[DSCOPE]] ! CHECK-NEXT: %[[V5:.*]] = fir.load %[[V1]]#0 : !fir.ref> ! CHECK-NEXT: %[[V6:.*]] = fir.load %[[V2]]#0 : !fir.ref ! CHECK-NEXT: %[[V7:.*]] = hlfir.minloc %[[V0]]#0 dim %[[V6]] mask %[[V3]]#0 back %[[V5]] {fastmath = #arith.fastmath} : (!fir.box>, i32, !fir.box>>, !fir.logical<4>) -> i16 diff --git a/flang/test/Lower/HLFIR/procedure-pointer.f90 b/flang/test/Lower/HLFIR/procedure-pointer.f90 index 28965b22de97..ce20f19322b4 100644 --- a/flang/test/Lower/HLFIR/procedure-pointer.f90 +++ b/flang/test/Lower/HLFIR/procedure-pointer.f90 @@ -186,10 +186,10 @@ end subroutine subroutine sub7(p1, p2) use m procedure(real_func), pointer :: p1 -! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %arg0 {fortran_attrs = #fir.var_attrs, uniq_name = "_QFsub7Ep1"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %arg0 dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFsub7Ep1"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) procedure(char_func), pointer :: p2 -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %arg1 {fortran_attrs = #fir.var_attrs, uniq_name = "_QFsub7Ep2"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %arg1 dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFsub7Ep2"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) call foo1(p1) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_0]]#0 : !fir.ref ()>> @@ -265,7 +265,7 @@ contains function reffunc(arg) result(pp) integer :: arg procedure(real_func), pointer :: pp -! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %arg0 {uniq_name = "_QFsub10FreffuncEarg"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_0:.*]]:2 = hlfir.declare %arg0 dummy_scope %{{[0-9]+}} {uniq_name = "_QFsub10FreffuncEarg"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.boxproc<(!fir.ref) -> f32> {bindc_name = "pp", uniq_name = "_QFsub10FreffuncEpp"} ! CHECK: %[[VAL_2:.*]] = fir.zero_bits (!fir.ref) -> f32 ! CHECK: %[[VAL_3:.*]] = fir.emboxproc %[[VAL_2]] : ((!fir.ref) -> f32) -> !fir.boxproc<(!fir.ref) -> f32> diff --git a/flang/test/Lower/HLFIR/statement-functions.f90 b/flang/test/Lower/HLFIR/statement-functions.f90 index d19b912e0fe2..4f91c947690c 100644 --- a/flang/test/Lower/HLFIR/statement-functions.f90 +++ b/flang/test/Lower/HLFIR/statement-functions.f90 @@ -43,7 +43,7 @@ subroutine char_test2(c) call test(stmt_func(c)) end subroutine ! CHECK-LABEL: func.func @_QPchar_test2( -! CHECK: %[[C:.*]]:2 = hlfir.declare %1 typeparams %c10 {uniq_name = "_QFchar_test2Ec"} : (!fir.ref>, index) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[C:.*]]:2 = hlfir.declare %{{.*}} typeparams %c10 dummy_scope %{{[0-9]+}} {uniq_name = "_QFchar_test2Ec"} : (!fir.ref>, index, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[CAST:.*]] = fir.convert %[[C]]#0 : (!fir.ref>) -> !fir.ref> ! CHECK: %[[C_STMT_FUNC:.*]]:2 = hlfir.declare %[[CAST]] typeparams %c5{{.*}} {uniq_name = "_QFchar_test2Fstmt_funcEc_stmt_func"} : (!fir.ref>, index) -> (!fir.ref>, !fir.ref>) ! CHECK: hlfir.concat %[[C_STMT_FUNC]]#0, %{{.*}} len %{{.*}} : (!fir.ref>, !fir.ref>, index) -> !hlfir.expr> diff --git a/flang/test/Lower/HLFIR/structure-constructor.f90 b/flang/test/Lower/HLFIR/structure-constructor.f90 index d02427d2ff67..41d08c14f5fa 100644 --- a/flang/test/Lower/HLFIR/structure-constructor.f90 +++ b/flang/test/Lower/HLFIR/structure-constructor.f90 @@ -43,7 +43,7 @@ end subroutine test1 ! CHECK: %[[VAL_4:.*]]:2 = fir.unboxchar %[[VAL_0]] : (!fir.boxchar<1>) -> (!fir.ref>, index) ! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]]#0 : (!fir.ref>) -> !fir.ref> ! CHECK: %[[VAL_6:.*]] = arith.constant 4 : index -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_5]] typeparams %[[VAL_6]] {uniq_name = "_QFtest1Ex"} : (!fir.ref>, index) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_5]] typeparams %[[VAL_6]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest1Ex"} : (!fir.ref>, index, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "ctor.temp"} : (!fir.ref}>>) -> (!fir.ref}>>, !fir.ref}>>) ! CHECK: %[[VAL_9:.*]] = fir.embox %[[VAL_8]]#0 : (!fir.ref}>>) -> !fir.box}>> ! CHECK: %[[VAL_10:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref> @@ -71,7 +71,7 @@ end subroutine test2 ! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_2]] {uniq_name = "_QFtest2Eres"} : (!fir.ref}>>) -> (!fir.ref}>>, !fir.ref}>>) ! CHECK: %[[VAL_4:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_4]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_5]]) {uniq_name = "_QFtest2Ex"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_5]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest2Ex"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "ctor.temp"} : (!fir.ref}>>) -> (!fir.ref}>>, !fir.ref}>>) ! CHECK: %[[VAL_8:.*]] = fir.embox %[[VAL_7]]#0 : (!fir.ref}>>) -> !fir.box}>> ! CHECK: %[[VAL_9:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref> @@ -104,7 +104,7 @@ end subroutine test3 ! CHECK: %[[VAL_7:.*]] = fir.convert %[[VAL_4]] : (!fir.box>>}>>) -> !fir.box ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_5]] : (!fir.ref>) -> !fir.ref ! CHECK: %[[VAL_9:.*]] = fir.call @_FortranAInitialize(%[[VAL_7]], %[[VAL_8]], %[[VAL_6]]) fastmath : (!fir.box, !fir.ref, i32) -> none -! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest3Ex"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest3Ex"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_11:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "ctor.temp"} : (!fir.ref>>}>>) -> (!fir.ref>>}>>, !fir.ref>>}>>) ! CHECK: %[[VAL_12:.*]] = fir.embox %[[VAL_11]]#0 : (!fir.ref>>}>>) -> !fir.box>>}>> ! CHECK: %[[VAL_13:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref> @@ -141,7 +141,7 @@ end subroutine test4 ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_5]] : (!fir.ref>) -> !fir.ref ! CHECK: %[[VAL_9:.*]] = fir.call @_FortranAInitialize(%[[VAL_7]], %[[VAL_8]], %[[VAL_6]]) fastmath : (!fir.box, !fir.ref, i32) -> none ! CHECK: %[[VAL_10:.*]] = arith.constant 2 : index -! CHECK: %[[VAL_11:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_10]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest4Ex"} : (!fir.ref>>>>, index) -> (!fir.ref>>>>, !fir.ref>>>>) +! CHECK: %[[VAL_11:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_10]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest4Ex"} : (!fir.ref>>>>, index, !fir.dscope) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "ctor.temp"} : (!fir.ref>>>}>>) -> (!fir.ref>>>}>>, !fir.ref>>>}>>) ! CHECK: %[[VAL_13:.*]] = fir.embox %[[VAL_12]]#0 : (!fir.ref>>>}>>) -> !fir.box>>>}>> ! CHECK: %[[VAL_14:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref> @@ -184,7 +184,7 @@ end subroutine test5 ! CHECK: %[[VAL_7:.*]] = fir.convert %[[VAL_4]] : (!fir.box>>>}>>>>}>>) -> !fir.box ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_5]] : (!fir.ref>) -> !fir.ref ! CHECK: %[[VAL_9:.*]] = fir.call @_FortranAInitialize(%[[VAL_7]], %[[VAL_8]], %[[VAL_6]]) fastmath : (!fir.box, !fir.ref, i32) -> none -! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest5Ex"} : (!fir.ref>>>}>>>>>) -> (!fir.ref>>>}>>>>>, !fir.ref>>>}>>>>>) +! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest5Ex"} : (!fir.ref>>>}>>>>>, !fir.dscope) -> (!fir.ref>>>}>>>>>, !fir.ref>>>}>>>>>) ! CHECK: %[[VAL_11:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "ctor.temp"} : (!fir.ref>>>}>>>>}>>) -> (!fir.ref>>>}>>>>}>>, !fir.ref>>>}>>>>}>>) ! CHECK: %[[VAL_12:.*]] = fir.embox %[[VAL_11]]#0 : (!fir.ref>>>}>>>>}>>) -> !fir.box>>>}>>>>}>> ! CHECK: %[[VAL_13:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref> @@ -226,7 +226,7 @@ end subroutine test6 ! CHECK: %[[VAL_7:.*]]:2 = fir.unboxchar %[[VAL_1]] : (!fir.boxchar<1>) -> (!fir.ref>, index) ! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]]#0 : (!fir.ref>) -> !fir.ref> ! CHECK: %[[VAL_9:.*]] = arith.constant 4 : index -! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_8]] typeparams %[[VAL_9]] {uniq_name = "_QFtest6Ec"} : (!fir.ref>, index) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_8]] typeparams %[[VAL_9]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest6Ec"} : (!fir.ref>, index, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_11:.*]] = fir.alloca !fir.type<_QMtypesTt6{t5:!fir.type<_QMtypesTt5{t5m:!fir.box>>>}>>>>}>,t6m:!fir.array<1x!fir.type<_QMtypesTt1{c:!fir.char<1,4>}>>}> {bindc_name = "res", uniq_name = "_QFtest6Eres"} ! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_11]] {uniq_name = "_QFtest6Eres"} : (!fir.ref>>>}>>>>}>,t6m:!fir.array<1x!fir.type<_QMtypesTt1{c:!fir.char<1,4>}>>}>>) -> (!fir.ref>>>}>>>>}>,t6m:!fir.array<1x!fir.type<_QMtypesTt1{c:!fir.char<1,4>}>>}>>, !fir.ref>>>}>>>>}>,t6m:!fir.array<1x!fir.type<_QMtypesTt1{c:!fir.char<1,4>}>>}>>) ! CHECK: %[[VAL_13:.*]] = fir.embox %[[VAL_12]]#1 : (!fir.ref>>>}>>>>}>,t6m:!fir.array<1x!fir.type<_QMtypesTt1{c:!fir.char<1,4>}>>}>>) -> !fir.box>>>}>>>>}>,t6m:!fir.array<1x!fir.type<_QMtypesTt1{c:!fir.char<1,4>}>>}>> @@ -235,7 +235,7 @@ end subroutine test6 ! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_13]] : (!fir.box>>>}>>>>}>,t6m:!fir.array<1x!fir.type<_QMtypesTt1{c:!fir.char<1,4>}>>}>>) -> !fir.box ! CHECK: %[[VAL_17:.*]] = fir.convert %[[VAL_14]] : (!fir.ref>) -> !fir.ref ! CHECK: %[[VAL_18:.*]] = fir.call @_FortranAInitialize(%[[VAL_16]], %[[VAL_17]], %[[VAL_15]]) fastmath : (!fir.box, !fir.ref, i32) -> none -! CHECK: %[[VAL_19:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest6Ex"} : (!fir.ref>>>}>>>>>) -> (!fir.ref>>>}>>>>>, !fir.ref>>>}>>>>>) +! CHECK: %[[VAL_19:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest6Ex"} : (!fir.ref>>>}>>>>>, !fir.dscope) -> (!fir.ref>>>}>>>>>, !fir.ref>>>}>>>>>) ! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = "ctor.temp"} : (!fir.ref>>>}>>>>}>,t6m:!fir.array<1x!fir.type<_QMtypesTt1{c:!fir.char<1,4>}>>}>>) -> (!fir.ref>>>}>>>>}>,t6m:!fir.array<1x!fir.type<_QMtypesTt1{c:!fir.char<1,4>}>>}>>, !fir.ref>>>}>>>>}>,t6m:!fir.array<1x!fir.type<_QMtypesTt1{c:!fir.char<1,4>}>>}>>) ! CHECK: %[[VAL_21:.*]] = fir.embox %[[VAL_20]]#0 : (!fir.ref>>>}>>>>}>,t6m:!fir.array<1x!fir.type<_QMtypesTt1{c:!fir.char<1,4>}>>}>>) -> !fir.box>>>}>>>>}>,t6m:!fir.array<1x!fir.type<_QMtypesTt1{c:!fir.char<1,4>}>>}>> ! CHECK: %[[VAL_22:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref> @@ -316,7 +316,7 @@ end subroutine test7 ! CHECK-LABEL: func.func @_QPtest7( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "n"}) { ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.type<_QMtypesTt7{c1:i32,c2:!fir.box>>}> -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest7En"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest7En"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.type<_QMtypesTt7{c1:i32,c2:!fir.box>>}> {bindc_name = "x", uniq_name = "_QFtest7Ex"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFtest7Ex"} : (!fir.ref>>}>>) -> (!fir.ref>>}>>, !fir.ref>>}>>) ! CHECK: %[[VAL_5:.*]] = fir.embox %[[VAL_4]]#1 : (!fir.ref>>}>>) -> !fir.box>>}>> diff --git a/flang/test/Lower/HLFIR/transformational.f90 b/flang/test/Lower/HLFIR/transformational.f90 index 5f1137277336..96cda5daaacb 100644 --- a/flang/test/Lower/HLFIR/transformational.f90 +++ b/flang/test/Lower/HLFIR/transformational.f90 @@ -16,7 +16,7 @@ subroutine test_transformational_implemented_with_runtime_allocation(x) end subroutine ! CHECK-LABEL: func.func @_QPtest_transformational_implemented_with_runtime_allocation( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {uniq_name = "_QFtest_transformational_implemented_with_runtime_allocationEx"} +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_transformational_implemented_with_runtime_allocationEx"} ! CHECK: %[[VAL_2:.*]] = hlfir.minloc %[[VAL_1]]#0 ! CHECK: %[[VAL_3:.*]] = hlfir.shape_of %[[VAL_2]] ! CHECK: %[[VAL_4:.*]]:3 = hlfir.associate %[[VAL_2]](%[[VAL_3]]) {adapt.valuebyref} diff --git a/flang/test/Lower/HLFIR/transpose.f90 b/flang/test/Lower/HLFIR/transpose.f90 index e37e83c7a501..6d8e337f1ac8 100644 --- a/flang/test/Lower/HLFIR/transpose.f90 +++ b/flang/test/Lower/HLFIR/transpose.f90 @@ -8,8 +8,8 @@ endsubroutine ! CHECK-LABEL: func.func @_QPtranspose1 ! CHECK: %[[M_ARG:.*]]: !fir.ref> ! CHECK: %[[RES_ARG:.*]]: !fir.ref> -! CHECK-DAG: %[[ARG:.*]]:2 = hlfir.declare %[[M_ARG]](%[[M_SHAPE:.*]]) {[[NAME:.*]]} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) -! CHECK-DAG: %[[RES:.*]]:2 = hlfir.declare %[[RES_ARG]](%[[RES_SHAPE:.*]]) {[[NAME2:.*]]} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) +! CHECK-DAG: %[[ARG:.*]]:2 = hlfir.declare %[[M_ARG]](%[[M_SHAPE:.*]]) dummy_scope %{{[0-9]+}} {[[NAME:.*]]} : (!fir.ref>, !fir.shape<2>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK-DAG: %[[RES:.*]]:2 = hlfir.declare %[[RES_ARG]](%[[RES_SHAPE:.*]]) dummy_scope %{{[0-9]+}} {[[NAME2:.*]]} : (!fir.ref>, !fir.shape<2>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[EXPR:.*]] = hlfir.transpose %[[ARG]]#0 : (!fir.ref>) -> !hlfir.expr<2x1xi32> ! CHECK-NEXT: hlfir.assign %[[EXPR]] to %[[RES]]#0 ! CHECK-NEXT: hlfir.destroy %[[EXPR]] @@ -38,7 +38,7 @@ endsubroutine ! CHECK: %[[M_ARG:.*]]: !fir.ref>>> ! CHECK: %[[RES_ARG:.*]]: !fir.ref> ! CHECK-DAG: %[[ARG:.*]]:2 = hlfir.declare %[[M_ARG]] -! CHECK-DAG: %[[RES:.*]]:2 = hlfir.declare %[[RES_ARG]](%[[RES_SHAPE:.*]]) {[[NAME2:.*]]} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) +! CHECK-DAG: %[[RES:.*]]:2 = hlfir.declare %[[RES_ARG]](%[[RES_SHAPE:.*]]) dummy_scope %{{[0-9]+}} {[[NAME2:.*]]} : (!fir.ref>, !fir.shape<2>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[ARG_LOADED:.*]] = fir.load %[[ARG]]#0 ! CHECK: %[[EXPR:.*]] = hlfir.transpose %[[ARG_LOADED]] : (!fir.box>>) -> !hlfir.expr ! CHECK-NEXT: hlfir.assign %[[EXPR]] to %[[RES]]#0 @@ -54,8 +54,8 @@ end subroutine test_polymorphic_result ! CHECK-LABEL: func.func @_QPtest_polymorphic_result( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "m"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref>>> {fir.bindc_name = "res"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_polymorphic_resultEm"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_polymorphic_resultEres"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_polymorphic_resultEm"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_polymorphic_resultEres"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref>>> ! CHECK: %[[VAL_5:.*]] = hlfir.transpose %[[VAL_4]] : (!fir.class>>) -> !hlfir.expr ! CHECK: hlfir.assign %[[VAL_5]] to %[[VAL_3]]#0 realloc : !hlfir.expr, !fir.ref>>> diff --git a/flang/test/Lower/HLFIR/unary-ops.f90 b/flang/test/Lower/HLFIR/unary-ops.f90 index db2c1ceefaa9..b04d6b4cf949 100644 --- a/flang/test/Lower/HLFIR/unary-ops.f90 +++ b/flang/test/Lower/HLFIR/unary-ops.f90 @@ -39,7 +39,7 @@ subroutine test_not(l, x) l = .not.x end subroutine ! CHECK-LABEL: func.func @_QPtest_not( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref> ! CHECK: %[[VAL_5:.*]] = arith.constant true ! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_4]] : (!fir.logical<4>) -> i1 @@ -50,7 +50,7 @@ subroutine test_negate_int(res, x) res = -x end subroutine ! CHECK-LABEL: func.func @_QPtest_negate_int( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref ! CHECK: %[[VAL_5:.*]] = arith.constant 0 : i32 ! CHECK: %[[VAL_6:.*]] = arith.subi %[[VAL_5]], %[[VAL_4]] : i32 @@ -60,7 +60,7 @@ subroutine test_negate_real(res, x) res = -x end subroutine ! CHECK-LABEL: func.func @_QPtest_negate_real( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref ! CHECK: %[[VAL_5:.*]] = arith.negf %[[VAL_4]] fastmath : f32 @@ -69,7 +69,7 @@ subroutine test_negate_complex(res, x) res = -x end subroutine ! CHECK-LABEL: func.func @_QPtest_negate_complex( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref> ! CHECK: %[[VAL_5:.*]] = fir.negc %[[VAL_4]] : !fir.complex<4> @@ -79,7 +79,7 @@ subroutine test_complex_component_real(res, x) res = real(x) end subroutine ! CHECK-LABEL: func.func @_QPtest_complex_component_real( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref> ! CHECK: %[[VAL_5:.*]] = fir.extract_value %[[VAL_4]], [0 : index] : (!fir.complex<4>) -> f32 @@ -89,6 +89,6 @@ subroutine test_complex_component_imag(res, x) res = aimag(x) end subroutine ! CHECK-LABEL: func.func @_QPtest_complex_component_imag( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}}x"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref> ! CHECK: %[[VAL_5:.*]] = fir.extract_value %[[VAL_4]], [1 : index] : (!fir.complex<4>) -> f32 diff --git a/flang/test/Lower/HLFIR/user-defined-assignment.f90 b/flang/test/Lower/HLFIR/user-defined-assignment.f90 index 6f887cb00de3..f0e24f11c5ab 100644 --- a/flang/test/Lower/HLFIR/user-defined-assignment.f90 +++ b/flang/test/Lower/HLFIR/user-defined-assignment.f90 @@ -35,8 +35,8 @@ end subroutine ! CHECK-LABEL: func.func @_QMuser_defPtest_user_defined_elemental_array( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "i"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.box>> {fir.bindc_name = "l"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QMuser_defFtest_user_defined_elemental_arrayEi"} : (!fir.box>) -> (!fir.box>, !fir.box>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QMuser_defFtest_user_defined_elemental_arrayEl"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_user_defined_elemental_arrayEi"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_user_defined_elemental_arrayEl"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: hlfir.region_assign { ! CHECK: hlfir.yield %[[VAL_3]]#0 : !fir.box>> ! CHECK: } to { @@ -53,8 +53,8 @@ end subroutine ! CHECK-LABEL: func.func @_QMuser_defPtest_user_defined_elemental_array_value( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box>> {fir.bindc_name = "z"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.box>> {fir.bindc_name = "l"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QMuser_defFtest_user_defined_elemental_array_valueEl"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QMuser_defFtest_user_defined_elemental_array_valueEz"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_user_defined_elemental_array_valueEl"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_user_defined_elemental_array_valueEz"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: hlfir.region_assign { ! CHECK: hlfir.yield %[[VAL_2]]#0 : !fir.box>> ! CHECK: } to { @@ -72,8 +72,8 @@ end subroutine ! CHECK-LABEL: func.func @_QMuser_defPtest_user_defined_scalar( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "i"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "l"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QMuser_defFtest_user_defined_scalarEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QMuser_defFtest_user_defined_scalarEl"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_user_defined_scalarEi"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_user_defined_scalarEl"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: hlfir.region_assign { ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref> ! CHECK: hlfir.yield %[[VAL_4]] : !fir.logical<4> @@ -91,7 +91,7 @@ subroutine test_non_elemental_array(x) end subroutine ! CHECK-LABEL: func.func @_QMuser_defPtest_non_elemental_array( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QMuser_defFtest_non_elemental_arrayEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_non_elemental_arrayEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: hlfir.region_assign { ! CHECK: %[[VAL_2:.*]] = arith.constant 4.200000e+01 : f32 ! CHECK: %[[VAL_3:.*]] = arith.constant 0 : index @@ -126,9 +126,9 @@ end subroutine ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "i"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.box>> {fir.bindc_name = "l"}, ! CHECK-SAME: %[[VAL_2:.*]]: !fir.box>> {fir.bindc_name = "l2"}) { -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QMuser_defFtest_where_user_def_assignmentEi"} : (!fir.box>) -> (!fir.box>, !fir.box>) -! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QMuser_defFtest_where_user_def_assignmentEl"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_2]] {uniq_name = "_QMuser_defFtest_where_user_def_assignmentEl2"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_where_user_def_assignmentEi"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_where_user_def_assignmentEl"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_where_user_def_assignmentEl2"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: hlfir.where { ! CHECK: hlfir.yield %[[VAL_4]]#0 : !fir.box>> ! CHECK: } do { @@ -171,11 +171,11 @@ end subroutine ! CHECK: %[[VAL_2:.*]] = arith.constant 20 : index ! CHECK: %[[VAL_3:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_2]], %[[VAL_3]] : (index, index) -> !fir.shape<2> -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) {uniq_name = "_QMuser_defFtest_forall_user_def_assignmentEi"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_forall_user_def_assignmentEi"} : (!fir.ref>, !fir.shape<2>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_6:.*]] = arith.constant 20 : index ! CHECK: %[[VAL_7:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_8:.*]] = fir.shape %[[VAL_6]], %[[VAL_7]] : (index, index) -> !fir.shape<2> -! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_8]]) {uniq_name = "_QMuser_defFtest_forall_user_def_assignmentEl"} : (!fir.ref>>, !fir.shape<2>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_8]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_forall_user_def_assignmentEl"} : (!fir.ref>>, !fir.shape<2>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 10 : i32 ! CHECK: hlfir.forall lb { @@ -218,11 +218,11 @@ end subroutine ! CHECK: %[[VAL_2:.*]] = arith.constant 20 : index ! CHECK: %[[VAL_3:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_2]], %[[VAL_3]] : (index, index) -> !fir.shape<2> -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_4]]) {uniq_name = "_QMuser_defFtest_forall_user_def_assignment_non_elemental_arrayEl"} : (!fir.ref>>, !fir.shape<2>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_4]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_forall_user_def_assignment_non_elemental_arrayEl"} : (!fir.ref>>, !fir.shape<2>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_6:.*]] = arith.constant 20 : index ! CHECK: %[[VAL_7:.*]] = arith.constant 10 : index ! CHECK: %[[VAL_8:.*]] = fir.shape %[[VAL_6]], %[[VAL_7]] : (index, index) -> !fir.shape<2> -! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_8]]) {uniq_name = "_QMuser_defFtest_forall_user_def_assignment_non_elemental_arrayEx"} : (!fir.ref>, !fir.shape<2>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_8]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_forall_user_def_assignment_non_elemental_arrayEx"} : (!fir.ref>, !fir.shape<2>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 10 : i32 ! CHECK: hlfir.forall lb { @@ -269,8 +269,8 @@ end subroutine ! CHECK-LABEL: func.func @_QMuser_defPtest_pointer( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "p"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMuser_defFtest_pointerEp"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QMuser_defFtest_pointerEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMuser_defFtest_pointerEp"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_pointerEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: hlfir.region_assign { ! CHECK: hlfir.yield %[[VAL_3]]#0 : !fir.box> ! CHECK: } to { @@ -287,8 +287,8 @@ end subroutine ! CHECK-LABEL: func.func @_QMuser_defPtest_allocatable( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "a"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMuser_defFtest_allocatableEa"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QMuser_defFtest_allocatableEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMuser_defFtest_allocatableEa"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMuser_defFtest_allocatableEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: hlfir.region_assign { ! CHECK: hlfir.yield %[[VAL_3]]#0 : !fir.box> ! CHECK: } to { @@ -313,7 +313,7 @@ end subroutine test_char_get_length ! CHECK-LABEL: func.func @_QPtest_char_get_length( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.boxchar<1> {fir.bindc_name = "ch"}) { ! CHECK: %[[VAL_1:.*]]:2 = fir.unboxchar %[[VAL_0]] : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]]#0 typeparams %[[VAL_1]]#1 {uniq_name = "_QFtest_char_get_lengthEch"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]]#0 typeparams %[[VAL_1]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_char_get_lengthEch"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFtest_char_get_lengthEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFtest_char_get_lengthEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: hlfir.region_assign { diff --git a/flang/test/Lower/HLFIR/vector-subscript-as-value.f90 b/flang/test/Lower/HLFIR/vector-subscript-as-value.f90 index ee8ded197c95..7161ee088b57 100644 --- a/flang/test/Lower/HLFIR/vector-subscript-as-value.f90 +++ b/flang/test/Lower/HLFIR/vector-subscript-as-value.f90 @@ -68,7 +68,7 @@ subroutine foo3(x, y) call bar2(x(1:8:2, 5, y)) end subroutine ! CHECK-LABEL: func.func @_QPfoo3( -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFfoo3Ex"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0:[a-z0-9]*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFfoo3Ex"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_3:.*]] = arith.constant 20 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_1:[a-z0-9]*]](%[[VAL_4:[a-z0-9]*]]) {{.*}}Ey @@ -196,8 +196,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest_passing_subscripted_poly( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.class> ! CHECK-SAME: %[[VAL_1:.*]]: !fir.box> -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest_passing_subscripted_polyEvector"} : (!fir.box>) -> (!fir.box>, !fir.box>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest_passing_subscripted_polyEx"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_passing_subscripted_polyEvector"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_passing_subscripted_polyEx"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: %[[VAL_4:.*]] = arith.constant 314 : index ! CHECK: %[[VAL_5:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_6:.*]]:3 = fir.box_dims %[[VAL_2]]#0, %[[VAL_5]] : (!fir.box>, index) -> (index, index, index) diff --git a/flang/test/Lower/Intrinsics/associated-proc-pointers.f90 b/flang/test/Lower/Intrinsics/associated-proc-pointers.f90 index 1772b9afdfc0..e07e61b7e597 100644 --- a/flang/test/Lower/Intrinsics/associated-proc-pointers.f90 +++ b/flang/test/Lower/Intrinsics/associated-proc-pointers.f90 @@ -9,7 +9,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest_proc_pointer_1( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>>, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.boxproc<() -> ()>) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointer_1Ep"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointer_1Ep"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_2]]#1 : !fir.ref ()>> ! CHECK: %[[VAL_4:.*]] = fir.box_addr %[[VAL_3]] : (!fir.boxproc<() -> ()>) -> (() -> ()) ! CHECK: %[[VAL_5:.*]] = fir.box_addr %[[VAL_1]] : (!fir.boxproc<() -> ()>) -> (() -> ()) @@ -28,8 +28,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest_proc_pointer_2( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>>, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref ()>>) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointer_2Ep"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointer_2Ep_target"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointer_2Ep"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointer_2Ep_target"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_2]]#1 : !fir.ref ()>> ! CHECK: %[[VAL_5:.*]] = fir.box_addr %[[VAL_4]] : (!fir.boxproc<() -> ()>) -> (() -> ()) ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_3]]#1 : !fir.ref ()>> @@ -50,7 +50,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest_proc_pointer_3( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>>, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.boxproc<() -> ()>) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointer_3Ep"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointer_3Ep"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_2]]#1 : !fir.ref ()>> ! CHECK: %[[VAL_4:.*]] = fir.box_addr %[[VAL_3]] : (!fir.boxproc<() -> ()>) -> (() -> ()) ! CHECK: %[[VAL_5:.*]] = fir.box_addr %[[VAL_1]] : (!fir.boxproc<() -> ()>) -> (() -> ()) @@ -69,7 +69,7 @@ subroutine test_proc_pointer_4(p) end subroutine ! CHECK-LABEL: func.func @_QPtest_proc_pointer_4( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>>) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointer_4Ep"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointer_4Ep"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) ! CHECK: %[[VAL_2:.*]] = fir.address_of(@_QPsome_external) : () -> () ! CHECK: %[[VAL_3:.*]] = fir.emboxproc %[[VAL_2]] : (() -> ()) -> !fir.boxproc<() -> ()> ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_1]]#1 : !fir.ref ()>> @@ -95,7 +95,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest_proc_pointer_5( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>>, ! CHECK-SAME: %[[VAL_1:.*]]: tuple ()>, i64> {fir.char_proc}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointer_5Ep"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointer_5Ep"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) ! CHECK: %[[VAL_3:.*]] = fir.extract_value %[[VAL_1]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> ! CHECK: %[[VAL_4:.*]] = fir.box_addr %[[VAL_3]] : (!fir.boxproc<() -> ()>) -> (() -> ()) ! CHECK: %[[VAL_5:.*]] = arith.constant 10 : i64 diff --git a/flang/test/Lower/Intrinsics/c_f_procpointer.f90 b/flang/test/Lower/Intrinsics/c_f_procpointer.f90 index f70a56c91b91..f8792e4c1be0 100644 --- a/flang/test/Lower/Intrinsics/c_f_procpointer.f90 +++ b/flang/test/Lower/Intrinsics/c_f_procpointer.f90 @@ -10,8 +10,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest_c_funloc( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>>, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "cptr"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest_c_funlocEcptr"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_funlocEfptr"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_c_funlocEcptr"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_funlocEfptr"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) ! CHECK: %[[VAL_4:.*]] = fir.field_index __address, !fir.type<_QM__fortran_builtinsT__builtin_c_funptr{__address:i64}> ! CHECK: %[[VAL_5:.*]] = fir.coordinate_of %[[VAL_2]]#1, %[[VAL_4]] : (!fir.ref>, !fir.field) -> !fir.ref ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_5]] : !fir.ref @@ -32,8 +32,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPtest_c_funloc_char( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>>, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref> {fir.bindc_name = "cptr"}) { -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFtest_c_funloc_charEcptr"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_funloc_charEfptr"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_c_funloc_charEcptr"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_funloc_charEfptr"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) ! CHECK: %[[VAL_4:.*]] = fir.field_index __address, !fir.type<_QM__fortran_builtinsT__builtin_c_funptr{__address:i64}> ! CHECK: %[[VAL_5:.*]] = fir.coordinate_of %[[VAL_2]]#1, %[[VAL_4]] : (!fir.ref>, !fir.field) -> !fir.ref ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_5]] : !fir.ref diff --git a/flang/test/Lower/Intrinsics/c_funloc-proc-pointers.f90 b/flang/test/Lower/Intrinsics/c_funloc-proc-pointers.f90 index c9578b17ac52..0f398a346d45 100644 --- a/flang/test/Lower/Intrinsics/c_funloc-proc-pointers.f90 +++ b/flang/test/Lower/Intrinsics/c_funloc-proc-pointers.f90 @@ -8,7 +8,7 @@ subroutine test_c_funloc(p) end subroutine ! CHECK-LABEL: func.func @_QPtest_c_funloc( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>>) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_funlocEp"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_funlocEp"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref ()>> ! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.type<_QM__fortran_builtinsT__builtin_c_funptr{__address:i64}> ! CHECK: %[[VAL_4:.*]] = fir.field_index __address, !fir.type<_QM__fortran_builtinsT__builtin_c_funptr{__address:i64}> @@ -28,7 +28,7 @@ subroutine test_c_funloc_char(p) end subroutine ! CHECK-LABEL: func.func @_QPtest_c_funloc_char( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>>) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_funloc_charEp"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_funloc_charEp"} : (!fir.ref ()>>, !fir.dscope) -> (!fir.ref ()>>, !fir.ref ()>>) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref ()>> ! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.type<_QM__fortran_builtinsT__builtin_c_funptr{__address:i64}> ! CHECK: %[[VAL_4:.*]] = fir.field_index __address, !fir.type<_QM__fortran_builtinsT__builtin_c_funptr{__address:i64}> diff --git a/flang/test/Lower/Intrinsics/c_ptr_eq_ne.f90 b/flang/test/Lower/Intrinsics/c_ptr_eq_ne.f90 index 38468739ead5..c6a2f186e4c1 100644 --- a/flang/test/Lower/Intrinsics/c_ptr_eq_ne.f90 +++ b/flang/test/Lower/Intrinsics/c_ptr_eq_ne.f90 @@ -10,8 +10,8 @@ end ! CHECK-LABEL: func.func @_QPtest_c_ptr_eq( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "ptr1"}, %[[ARG1:.*]]: !fir.ref> {fir.bindc_name = "ptr2"}) -> !fir.logical<4> { -! CHECK: %[[DECL_ARG0:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_ptr_eqEptr1"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[DECL_ARG1:.*]]:2 = hlfir.declare %[[ARG1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_ptr_eqEptr2"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[DECL_ARG0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_ptr_eqEptr1"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[DECL_ARG1:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_ptr_eqEptr2"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.logical<4> {bindc_name = "test_c_ptr_eq", uniq_name = "_QFtest_c_ptr_eqEtest_c_ptr_eq"} ! CHECK: %[[DECL_RET:.*]]:2 = hlfir.declare %[[ALLOCA]] {uniq_name = "_QFtest_c_ptr_eqEtest_c_ptr_eq"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[FIELD_ADDRESS:.*]] = fir.field_index __address, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}> @@ -37,8 +37,8 @@ end ! CHECK-LABEL: func.func @_QPtest_c_ptr_ne( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "ptr1"}, %[[ARG1:.*]]: !fir.ref> {fir.bindc_name = "ptr2"}) -> !fir.logical<4> { -! CHECK: %[[DECL_ARG0:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_ptr_neEptr1"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[DECL_ARG1:.*]]:2 = hlfir.declare %[[ARG1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_ptr_neEptr2"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[DECL_ARG0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_ptr_neEptr1"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[DECL_ARG1:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_c_ptr_neEptr2"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.logical<4> {bindc_name = "test_c_ptr_ne", uniq_name = "_QFtest_c_ptr_neEtest_c_ptr_ne"} ! CHECK: %[[DECL_RET:.*]]:2 = hlfir.declare %[[ALLOCA]] {uniq_name = "_QFtest_c_ptr_neEtest_c_ptr_ne"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[FIELD_ADDRESS:.*]] = fir.field_index __address, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}> diff --git a/flang/test/Lower/Intrinsics/execute_command_line-optional.f90 b/flang/test/Lower/Intrinsics/execute_command_line-optional.f90 index 0b75a20216af..e4f9a241197c 100644 --- a/flang/test/Lower/Intrinsics/execute_command_line-optional.f90 +++ b/flang/test/Lower/Intrinsics/execute_command_line-optional.f90 @@ -15,14 +15,15 @@ subroutine all_args_optional(command, isWait, exitVal, cmdVal, msg) ! CHECK-NEXT: %[[c14:.*]] = arith.constant 14 : i32 ! CHECK-NEXT: %true = arith.constant true ! CHECK-NEXT: %[[c0:.*]] = arith.constant 0 : i64 -! CHECK-NEXT: %[[cmdstatDeclare:.*]] = fir.declare %[[cmdstatArg]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEcmdval"} : (!fir.ref) -> !fir.ref +! CHECK-NEXT: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK-NEXT: %[[cmdstatDeclare:.*]] = fir.declare %[[cmdstatArg]] dummy_scope %[[DSCOPE]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEcmdval"} : (!fir.ref, !fir.dscope) -> !fir.ref ! CHECK-NEXT: %[[commandUnbox:.*]]:2 = fir.unboxchar %[[commandArg]] : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK-NEXT: %[[commandDeclare:.*]] = fir.declare %[[commandUnbox]]#0 typeparams %[[commandUnbox]]#1 {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEcommand"} : (!fir.ref>, index) -> !fir.ref> +! CHECK-NEXT: %[[commandDeclare:.*]] = fir.declare %[[commandUnbox]]#0 typeparams %[[commandUnbox]]#1 dummy_scope %[[DSCOPE]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEcommand"} : (!fir.ref>, index, !fir.dscope) -> !fir.ref> ! CHECK-NEXT: %[[commandBoxTemp:.*]] = fir.emboxchar %[[commandDeclare]], %[[commandUnbox]]#1 : (!fir.ref>, index) -> !fir.boxchar<1> -! CHECK-NEXT: %[[exitstatDeclare:.*]] = fir.declare %[[exitstatArg]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEexitval"} : (!fir.ref) -> !fir.ref -! CHECK-NEXT: %[[waitDeclare:.*]] = fir.declare %[[waitArg]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEiswait"} : (!fir.ref>) -> !fir.ref> +! CHECK-NEXT: %[[exitstatDeclare:.*]] = fir.declare %[[exitstatArg]] dummy_scope %[[DSCOPE]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEexitval"} : (!fir.ref, !fir.dscope) -> !fir.ref +! CHECK-NEXT: %[[waitDeclare:.*]] = fir.declare %[[waitArg]] dummy_scope %[[DSCOPE]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEiswait"} : (!fir.ref>, !fir.dscope) -> !fir.ref> ! CHECK-NEXT: %[[cmdmsgUnbox:.*]]:2 = fir.unboxchar %[[cmdmsgArg]] : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK-NEXT: %[[cmdmsgDeclare:.*]] = fir.declare %[[cmdmsgUnbox]]#0 typeparams %[[cmdmsgUnbox]]#1 {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEmsg"} : (!fir.ref>, index) -> !fir.ref> +! CHECK-NEXT: %[[cmdmsgDeclare:.*]] = fir.declare %[[cmdmsgUnbox]]#0 typeparams %[[cmdmsgUnbox]]#1 dummy_scope %[[DSCOPE]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_args_optionalEmsg"} : (!fir.ref>, index, !fir.dscope) -> !fir.ref> ! CHECK-NEXT: %[[cmdmsgBoxTemp:.*]] = fir.emboxchar %[[cmdmsgDeclare]], %[[cmdmsgUnbox]]#1 : (!fir.ref>, index) -> !fir.boxchar<1> ! CHECK-NEXT: %[[exitstatIsPresent:.*]] = fir.is_present %[[exitstatDeclare]] : (!fir.ref) -> i1 ! CHECK-NEXT: %[[cmdstatIsPresent:.*]] = fir.is_present %[[cmdstatDeclare]] : (!fir.ref) -> i1 diff --git a/flang/test/Lower/Intrinsics/execute_command_line.f90 b/flang/test/Lower/Intrinsics/execute_command_line.f90 index 8aacd34346b4..6bde50e807b2 100644 --- a/flang/test/Lower/Intrinsics/execute_command_line.f90 +++ b/flang/test/Lower/Intrinsics/execute_command_line.f90 @@ -15,15 +15,16 @@ call execute_command_line(command, isWait, exitVal, cmdVal, msg) ! CHECK-NEXT: %true = arith.constant true ! CHECK-NEXT: %[[c0:.*]] = arith.constant 0 : i64 ! CHECK-NEXT: %[[c30:.*]] = arith.constant 30 : index -! CHECK-NEXT: %[[cmdstatsDeclare:.*]] = fir.declare %[[cmdstatArg]] {uniq_name = "_QFall_argsEcmdval"} : (!fir.ref) -> !fir.ref +! CHECK-NEXT: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope +! CHECK-NEXT: %[[cmdstatsDeclare:.*]] = fir.declare %[[cmdstatArg]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFall_argsEcmdval"} : (!fir.ref, !fir.dscope) -> !fir.ref ! CHECK-NEXT: %[[commandUnbox:.*]]:2 = fir.unboxchar %[[commandArg]] : (!fir.boxchar<1>) -> (!fir.ref>, index) ! CHECK-NEXT: %[[commandCast:.*]] = fir.convert %[[commandUnbox]]#0 : (!fir.ref>) -> !fir.ref> -! CHECK-NEXT: %[[commandDeclare:.*]] = fir.declare %[[commandCast]] typeparams %[[c30]] {uniq_name = "_QFall_argsEcommand"} : (!fir.ref>, index) -> !fir.ref> -! CHECK-NEXT: %[[exitstatDeclare:.*]] = fir.declare %[[exitstatArg]] {uniq_name = "_QFall_argsEexitval"} : (!fir.ref) -> !fir.ref -! CHECK-NEXT: %[[waitDeclare:.*]] = fir.declare %[[waitArg]] {uniq_name = "_QFall_argsEiswait"} : (!fir.ref>) -> !fir.ref> +! CHECK-NEXT: %[[commandDeclare:.*]] = fir.declare %[[commandCast]] typeparams %[[c30]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFall_argsEcommand"} : (!fir.ref>, index, !fir.dscope) -> !fir.ref> +! CHECK-NEXT: %[[exitstatDeclare:.*]] = fir.declare %[[exitstatArg]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFall_argsEexitval"} : (!fir.ref, !fir.dscope) -> !fir.ref +! CHECK-NEXT: %[[waitDeclare:.*]] = fir.declare %[[waitArg]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFall_argsEiswait"} : (!fir.ref>, !fir.dscope) -> !fir.ref> ! CHECK-NEXT: %[[cmdmsgUnbox:.*]]:2 = fir.unboxchar %[[cmdmsgArg]] : (!fir.boxchar<1>) -> (!fir.ref>, index) ! CHECK-NEXT: %[[cmdmsgCast:.*]] = fir.convert %[[cmdmsgUnbox]]#0 : (!fir.ref>) -> !fir.ref> -! CHECK-NEXT: %[[cmdmsgDeclare:.*]] = fir.declare %[[cmdmsgCast]] typeparams %[[c30]] {uniq_name = "_QFall_argsEmsg"} : (!fir.ref>, index) -> !fir.ref> +! CHECK-NEXT: %[[cmdmsgDeclare:.*]] = fir.declare %[[cmdmsgCast]] typeparams %[[c30]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFall_argsEmsg"} : (!fir.ref>, index, !fir.dscope) -> !fir.ref> ! CHECK-NEXT: %[[commandBox:.*]] = fir.embox %[[commandDeclare]] : (!fir.ref>) -> !fir.box> ! CHECK-NEXT: %[[exitstatBox:.*]] = fir.embox %[[exitstatDeclare]] : (!fir.ref) -> !fir.box ! CHECK-NEXT: %[[cmdstatBox:.*]] = fir.embox %[[cmdstatsDeclare]] : (!fir.ref) -> !fir.box @@ -50,12 +51,13 @@ end subroutine all_args subroutine only_command_default_wait_true(command) CHARACTER(30) :: command call execute_command_line(command) -! CHECK-NEXT: %[[c52:.*]] = arith.constant 52 : i32 +! CHECK-NEXT: %[[c52:.*]] = arith.constant 53 : i32 ! CHECK-NEXT: %true = arith.constant true ! CHECK-NEXT: %[[c30:.*]] = arith.constant 30 : index +! CHECK-NEXT: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope ! CHECK-NEXT: %[[commandUnbox:.*]]:2 = fir.unboxchar %[[cmdArg]] : (!fir.boxchar<1>) -> (!fir.ref>, index) ! CHECK-NEXT: %[[commandCast:.*]] = fir.convert %[[commandUnbox]]#0 : (!fir.ref>) -> !fir.ref> -! CHECK-NEXT: %[[commandDeclare:.*]] = fir.declare %[[commandCast]] typeparams %[[c30]] {uniq_name = "_QFonly_command_default_wait_trueEcommand"} : (!fir.ref>, index) -> !fir.ref> +! CHECK-NEXT: %[[commandDeclare:.*]] = fir.declare %[[commandCast]] typeparams %[[c30]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFonly_command_default_wait_trueEcommand"} : (!fir.ref>, index, !fir.dscope) -> !fir.ref> ! CHECK-NEXT: %[[commandBox:.*]] = fir.embox %[[commandDeclare]] : (!fir.ref>) -> !fir.box> ! CHECK-NEXT: %[[absent:.*]] = fir.absent !fir.box ! CHECK: %[[command:.*]] = fir.convert %[[commandBox]] : (!fir.box>) -> !fir.box diff --git a/flang/test/Lower/Intrinsics/ieee_logb.f90 b/flang/test/Lower/Intrinsics/ieee_logb.f90 index df15661d51b2..4195ac7af245 100644 --- a/flang/test/Lower/Intrinsics/ieee_logb.f90 +++ b/flang/test/Lower/Intrinsics/ieee_logb.f90 @@ -9,7 +9,7 @@ subroutine out(x) ! CHECK: %[[V_61:[0-9]+]] = fir.declare %[[V_60]] {uniq_name = "_QFoutEl"} : (!fir.ref>) -> !fir.ref> ! CHECK: %[[V_62:[0-9]+]] = fir.alloca f64 {bindc_name = "r", uniq_name = "_QFoutEr"} ! CHECK: %[[V_63:[0-9]+]] = fir.declare %[[V_62]] {uniq_name = "_QFoutEr"} : (!fir.ref) -> !fir.ref - ! CHECK: %[[V_64:[0-9]+]] = fir.declare %arg0 {uniq_name = "_QFoutEx"} : (!fir.ref) -> !fir.ref + ! CHECK: %[[V_64:[0-9]+]] = fir.declare %arg0 dummy_scope %{{[0-9]+}} {uniq_name = "_QFoutEx"} : (!fir.ref, !fir.dscope) -> !fir.ref real(k) :: x, r logical :: L diff --git a/flang/test/Lower/Intrinsics/product.f90 b/flang/test/Lower/Intrinsics/product.f90 index e7f7c0d39ee0..ddefa7a37184 100644 --- a/flang/test/Lower/Intrinsics/product.f90 +++ b/flang/test/Lower/Intrinsics/product.f90 @@ -58,7 +58,7 @@ product_test4 = product(x) ! CHECK-DAG: %[[a5:.*]] = fir.convert %[[arg0]] : (!fir.box>>) -> !fir.box ! CHECK-DAG: %[[a7:.*]] = fir.convert %[[c0]] : (index) -> i32 ! CHECK-DAG: %[[a8:.*]] = fir.convert %[[a2]] : (!fir.box) -> !fir.box -! CHECK: fir.call @_FortranACppProductComplex10(%[[a4]], %[[a5]], %{{.*}}, %{{.*}}, %[[a7]], %8) {{.*}}: (!fir.ref>, !fir.box, !fir.ref, i32, i32, !fir.box) -> () +! CHECK: fir.call @_FortranACppProductComplex10(%[[a4]], %[[a5]], %{{.*}}, %{{.*}}, %[[a7]], %{{[0-9]+}}) {{.*}}: (!fir.ref>, !fir.box, !fir.ref, i32, i32, !fir.box) -> () end ! CHECK-LABEL: func @_QPproduct_test_optional( diff --git a/flang/test/Lower/Intrinsics/signal.f90 b/flang/test/Lower/Intrinsics/signal.f90 index d6678000677e..5d20bb5c5c07 100644 --- a/flang/test/Lower/Intrinsics/signal.f90 +++ b/flang/test/Lower/Intrinsics/signal.f90 @@ -23,7 +23,7 @@ contains integer, optional, intent(out) :: optional_status ! CHECK: %[[VAL_1:.*]] = fir.alloca i32 -! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMmFsetup_signalsEoptional_status"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMmFsetup_signalsEoptional_status"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QMmFsetup_signalsEstat"} : (!fir.ref) -> (!fir.ref, !fir.ref) call signal(SIGFPE, handler) diff --git a/flang/test/Lower/Intrinsics/sizeof.f90 b/flang/test/Lower/Intrinsics/sizeof.f90 index e10cb79981a6..7e749f096112 100644 --- a/flang/test/Lower/Intrinsics/sizeof.f90 +++ b/flang/test/Lower/Intrinsics/sizeof.f90 @@ -6,7 +6,7 @@ integer(8) function test1(x) test1 = sizeof(x) end function ! CHECK-LABEL: func.func @_QPtest1( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFtest1Ex"} : (!fir.class) -> (!fir.class, !fir.class) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest1Ex"} : (!fir.class, !fir.dscope) -> (!fir.class, !fir.class) ! CHECK: %[[VAL_4:.*]] = fir.box_elesize %[[VAL_3]]#1 : (!fir.class) -> i64 ! CHECK: hlfir.assign %[[VAL_4]] to %{{.*}} : i64, !fir.ref @@ -15,7 +15,7 @@ integer(8) function test2(x) test2 = sizeof(x) end function ! CHECK-LABEL: func.func @_QPtest2( -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFtest2Ex"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest2Ex"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: %[[VAL_4:.*]] = fir.box_elesize %[[VAL_3]]#1 : (!fir.class>) -> i64 ! CHECK: %[[VAL_7:.*]] = fir.convert %[[VAL_3]]#1 : (!fir.class>) -> !fir.box ! CHECK: %[[VAL_9:.*]] = fir.call @_FortranASize(%[[VAL_7]], %{{.*}}, %{{.*}}) fastmath : (!fir.box, !fir.ref, i32) -> i64 diff --git a/flang/test/Lower/Intrinsics/sum.f90 b/flang/test/Lower/Intrinsics/sum.f90 index cafcc0828df8..696892d29126 100644 --- a/flang/test/Lower/Intrinsics/sum.f90 +++ b/flang/test/Lower/Intrinsics/sum.f90 @@ -58,7 +58,7 @@ sum_test4 = sum(x) ! CHECK-DAG: %[[a5:.*]] = fir.convert %[[arg0]] : (!fir.box>>) -> !fir.box ! CHECK-DAG: %[[a7:.*]] = fir.convert %[[c0]] : (index) -> i32 ! CHECK-DAG: %[[a8:.*]] = fir.convert %[[a2]] : (!fir.box) -> !fir.box -! CHECK: fir.call @_FortranACppSumComplex10(%[[a4]], %[[a5]], %{{.*}}, %{{.*}}, %[[a7]], %8) {{.*}}: (!fir.ref>, !fir.box, !fir.ref, i32, i32, !fir.box) -> () +! CHECK: fir.call @_FortranACppSumComplex10(%[[a4]], %[[a5]], %{{.*}}, %{{.*}}, %[[a7]], %{{[0-9]+}}) {{.*}}: (!fir.ref>, !fir.box, !fir.ref, i32, i32, !fir.box) -> () end ! CHECK-LABEL: func @_QPsum_test_optional( diff --git a/flang/test/Lower/Intrinsics/system-optional.f90 b/flang/test/Lower/Intrinsics/system-optional.f90 index 5047437c5c3c..8a2db132d672 100644 --- a/flang/test/Lower/Intrinsics/system-optional.f90 +++ b/flang/test/Lower/Intrinsics/system-optional.f90 @@ -9,9 +9,10 @@ INTEGER, OPTIONAL :: exitstat call system(command, exitstat) ! CHECK-NEXT: %[[cmdstatVal:.*]] = fir.alloca i16 +! CHECK-NEXT: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope ! CHECK-NEXT: %[[commandUnbox:.*]]:2 = fir.unboxchar %[[commandArg]] : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK-NEXT: %[[commandDeclare:.*]]:2 = hlfir.declare %[[commandUnbox]]#0 typeparams %[[commandUnbox]]#1 {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_argsEcommand"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) -! CHECK-NEXT: %[[exitstatDeclare:.*]]:2 = hlfir.declare %[[exitstatArg]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_argsEexitstat"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK-NEXT: %[[commandDeclare:.*]]:2 = hlfir.declare %[[commandUnbox]]#0 typeparams %[[commandUnbox]]#1 dummy_scope %[[DSCOPE]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_argsEcommand"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK-NEXT: %[[exitstatDeclare:.*]]:2 = hlfir.declare %[[exitstatArg]] dummy_scope %[[DSCOPE]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFall_argsEexitstat"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK-NEXT: %[[exitstatIsPresent:.*]] = fir.is_present %[[exitstatDeclare]]#0 : (!fir.ref) -> i1 ! CHECK-NEXT: %[[commandBox:.*]] = fir.embox %[[commandDeclare]]#1 typeparams %[[commandUnbox]]#1 : (!fir.ref>, index) -> !fir.box> ! CHECK-NEXT: %[[exitstatBox:.*]] = fir.embox %[[exitstatDeclare]]#1 : (!fir.ref) -> !fir.box diff --git a/flang/test/Lower/Intrinsics/system.f90 b/flang/test/Lower/Intrinsics/system.f90 index 0cafc0b2a9cf..4ce3c553891d 100644 --- a/flang/test/Lower/Intrinsics/system.f90 +++ b/flang/test/Lower/Intrinsics/system.f90 @@ -8,9 +8,10 @@ CHARACTER(*) :: command INTEGER :: exitstat call system(command, exitstat) ! CHECK-NEXT: %[[cmdstatVal:.*]] = fir.alloca i16 +! CHECK-NEXT: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope ! CHECK-NEXT: %[[commandUnbox:.*]]:2 = fir.unboxchar %[[commandArg]] : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK-NEXT: %[[commandDeclare:.*]]:2 = hlfir.declare %[[commandUnbox]]#0 typeparams %[[commandUnbox]]#1 {uniq_name = "_QFall_argsEcommand"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) -! CHECK-NEXT: %[[exitstatDeclare:.*]]:2 = hlfir.declare %[[exitstatArg]] {uniq_name = "_QFall_argsEexitstat"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK-NEXT: %[[commandDeclare:.*]]:2 = hlfir.declare %[[commandUnbox]]#0 typeparams %[[commandUnbox]]#1 dummy_scope %[[DSCOPE]] {uniq_name = "_QFall_argsEcommand"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK-NEXT: %[[exitstatDeclare:.*]]:2 = hlfir.declare %[[exitstatArg]] dummy_scope %[[DSCOPE]] {uniq_name = "_QFall_argsEexitstat"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK-NEXT: %[[commandBox:.*]] = fir.embox %[[commandDeclare]]#1 typeparams %[[commandUnbox]]#1 : (!fir.ref>, index) -> !fir.box> ! CHECK-NEXT: %[[exitstatBox:.*]] = fir.embox %[[exitstatDeclare]]#1 : (!fir.ref) -> !fir.box ! CHECK-NEXT: %[[true:.*]] = arith.constant true @@ -34,8 +35,9 @@ subroutine only_command(command) CHARACTER(*) :: command call system(command) ! CHECK-NEXT: %[[cmdstatVal:.*]] = fir.alloca i16 +! CHECK-NEXT: %[[DSCOPE:.*]] = fir.dummy_scope : !fir.dscope ! CHECK-NEXT: %[[commandUnbox:.*]]:2 = fir.unboxchar %arg0 : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK-NEXT: %[[commandDeclare:.*]]:2 = hlfir.declare %[[commandUnbox]]#0 typeparams %[[commandUnbox]]#1 {uniq_name = "_QFonly_commandEcommand"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK-NEXT: %[[commandDeclare:.*]]:2 = hlfir.declare %[[commandUnbox]]#0 typeparams %[[commandUnbox]]#1 dummy_scope %[[DSCOPE]] {uniq_name = "_QFonly_commandEcommand"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK-NEXT: %[[commandBox:.*]] = fir.embox %[[commandDeclare]]#1 typeparams %[[commandUnbox]]#1 : (!fir.ref>, index) -> !fir.box> ! CHECK-NEXT: %[[true:.*]] = arith.constant true ! CHECK-NEXT: %[[absentBox:.*]] = fir.absent !fir.box @@ -44,7 +46,7 @@ call system(command) ! CHECK-NEXT: fir.store %[[c0_i16]] to %[[cmdstatVal]] : !fir.ref ! CHECK-NEXT: %[[cmdstatBox:.*]] = fir.embox %[[cmdstatVal]] : (!fir.ref) -> !fir.box ! CHECK-NEXT: %[[absentBox2:.*]] = fir.absent !fir.box -! CHECK: %[[c35_i32:.*]] = arith.constant 35 : i32 +! CHECK: %[[c35_i32:.*]] = arith.constant {{[0-9]+}} : i32 ! CHECK-NEXT: %[[command:.*]] = fir.convert %[[commandBox]] : (!fir.box>) -> !fir.box ! CHECK-NEXT: %[[cmdstat:.*]] = fir.convert %[[cmdstatBox]] : (!fir.box) -> !fir.box ! CHECK: %[[VAL_12:.*]] = fir.call @_FortranAExecuteCommandLine(%[[command]], %[[true]], %[[absentBox]], %[[cmdstat]], %[[absentBox2]], %[[VAL_11:.*]], %[[c35_i32]]) fastmath : (!fir.box, i1, !fir.box, !fir.box, !fir.box, !fir.ref, i32) -> none diff --git a/flang/test/Lower/OpenACC/acc-atomic-update-array.f90 b/flang/test/Lower/OpenACC/acc-atomic-update-array.f90 index e36c39c830ec..eeb7ea299408 100644 --- a/flang/test/Lower/OpenACC/acc-atomic-update-array.f90 +++ b/flang/test/Lower/OpenACC/acc-atomic-update-array.f90 @@ -20,8 +20,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPatomic_update_array1( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "r"}, %[[ARG1:.*]]: !fir.ref {fir.bindc_name = "n"}, %[[ARG2:.*]]: !fir.ref {fir.bindc_name = "x"}) { -! CHECK: %[[DECL_ARG2:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFatomic_update_array1Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[DECL_ARG0:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {uniq_name = "_QFatomic_update_array1Er"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[DECL_ARG2:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFatomic_update_array1Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[DECL_ARG0:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {uniq_name = "_QFatomic_update_array1Er"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) ! CHECK: %[[ARRAY_REF:.*]] = hlfir.designate %[[DECL_ARG0]]#0 (%{{.*}}) : (!fir.box>, i64) -> !fir.ref ! CHECK: %[[LOAD_X:.*]] = fir.load %[[DECL_ARG2]]#0 : !fir.ref ! CHECK: acc.atomic.update %[[ARRAY_REF]] : !fir.ref { @@ -42,8 +42,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPatomic_read_array1( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "r"}, %[[ARG1:.*]]: !fir.ref {fir.bindc_name = "n"}, %[[ARG2:.*]]: !fir.ref {fir.bindc_name = "x"}) { -! CHECK: %[[DECL_X:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFatomic_read_array1Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[DECL_R:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {uniq_name = "_QFatomic_read_array1Er"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[DECL_X:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFatomic_read_array1Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[DECL_R:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {uniq_name = "_QFatomic_read_array1Er"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) ! CHECK: %[[DES:.*]] = hlfir.designate %[[DECL_R]]#0 (%{{.*}}) : (!fir.box>, i64) -> !fir.ref ! CHECK: acc.atomic.read %[[DECL_X]]#1 = %[[DES]] : !fir.ref, f32 @@ -58,8 +58,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPatomic_write_array1( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "r"}, %[[ARG1:.*]]: !fir.ref {fir.bindc_name = "n"}, %[[ARG2:.*]]: !fir.ref {fir.bindc_name = "x"}) { -! CHECK: %[[DECL_X:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFatomic_write_array1Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[DECL_R:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {uniq_name = "_QFatomic_write_array1Er"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[DECL_X:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFatomic_write_array1Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[DECL_R:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {uniq_name = "_QFatomic_write_array1Er"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) ! CHECK: %[[DES:.*]] = hlfir.designate %[[DECL_R]]#0 (%{{.*}}) : (!fir.box>, i64) -> !fir.ref ! CHECK: %[[LOAD:.*]] = fir.load %[[DES]] : !fir.ref ! CHECK: acc.atomic.write %[[DECL_X]]#1 = %[[LOAD]] : !fir.ref, f32 @@ -77,9 +77,9 @@ end subroutine ! CHECK-LABEL: func.func @_QPatomic_capture_array1( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "r"}, %[[ARG1:.*]]: !fir.ref {fir.bindc_name = "n"}, %[[ARG2:.*]]: !fir.ref {fir.bindc_name = "x"}, %[[ARG3:.*]]: !fir.ref {fir.bindc_name = "y"}) { -! CHECK: %[[DECL_X:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFatomic_capture_array1Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[DECL_Y:.*]]:2 = hlfir.declare %[[ARG3]] {uniq_name = "_QFatomic_capture_array1Ey"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[DECL_R:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {uniq_name = "_QFatomic_capture_array1Er"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[DECL_X:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFatomic_capture_array1Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[DECL_Y:.*]]:2 = hlfir.declare %[[ARG3]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFatomic_capture_array1Ey"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[DECL_R:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {uniq_name = "_QFatomic_capture_array1Er"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) ! CHECK: %[[R_I:.*]] = hlfir.designate %[[DECL_R]]#0 (%{{.*}}) : (!fir.box>, i64) -> !fir.ref ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL_X]]#0 : !fir.ref ! CHECK: acc.atomic.capture { diff --git a/flang/test/Lower/OpenACC/acc-bounds.f90 b/flang/test/Lower/OpenACC/acc-bounds.f90 index c275d4f1b1d5..a83de91a67ae 100644 --- a/flang/test/Lower/OpenACC/acc-bounds.f90 +++ b/flang/test/Lower/OpenACC/acc-bounds.f90 @@ -88,7 +88,7 @@ contains ! CHECK-LABEL: func.func @_QMopenacc_boundsPacc_undefined_extent( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "a"}) { -! CHECK: %[[DECL_ARG0:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {uniq_name = "_QMopenacc_boundsFacc_undefined_extentEa"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[DECL_ARG0:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {uniq_name = "_QMopenacc_boundsFacc_undefined_extentEa"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) ! CHECK: %[[DIMS0:.*]]:3 = fir.box_dims %[[DECL_ARG0]]#0, %c0{{.*}} : (!fir.box>, index) -> (index, index, index) ! CHECK: %[[UB:.*]] = arith.subi %[[DIMS0]]#1, %c1{{.*}} : index ! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%c0{{.*}} : index) upperbound(%[[UB]] : index) extent(%[[DIMS0]]#1 : index) stride(%[[DIMS0]]#2 : index) startIdx(%c1{{.*}} : index) {strideInBytes = true} @@ -105,7 +105,7 @@ contains ! CHECK-LABEL: func.func @_QMopenacc_boundsPacc_multi_strides( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "a"}) -! CHECK: %[[DECL_ARG0:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QMopenacc_boundsFacc_multi_stridesEa"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[DECL_ARG0:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMopenacc_boundsFacc_multi_stridesEa"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[BOX_DIMS0:.*]]:3 = fir.box_dims %[[DECL_ARG0]]#0, %c0{{.*}} : (!fir.box>, index) -> (index, index, index) ! CHECK: %[[BOUNDS0:.*]] = acc.bounds lowerbound(%{{.*}} : index) upperbound(%{{.*}} : index) extent(%[[BOX_DIMS0]]#1 : index) stride(%[[BOX_DIMS0]]#2 : index) startIdx(%{{.*}} : index) {strideInBytes = true} ! CHECK: %[[STRIDE1:.*]] = arith.muli %[[BOX_DIMS0]]#2, %[[BOX_DIMS0]]#1 : index @@ -126,7 +126,7 @@ contains ! CHECK-LABEL: func.func @_QMopenacc_boundsPacc_optional_data( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>> {fir.bindc_name = "a", fir.optional}) { -! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMopenacc_boundsFacc_optional_dataEa"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMopenacc_boundsFacc_optional_dataEa"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[IS_PRESENT:.*]] = fir.is_present %[[ARG0_DECL]]#1 : (!fir.ref>>>) -> i1 ! CHECK: %[[BOX:.*]] = fir.if %[[IS_PRESENT]] -> (!fir.box>>) { ! CHECK: %[[LOAD:.*]] = fir.load %[[ARG0_DECL]]#0 : !fir.ref>>> @@ -162,8 +162,8 @@ contains ! CHECK-LABEL: func.func @_QMopenacc_boundsPacc_optional_data2( ! CHECK-SAME: %[[A:.*]]: !fir.ref> {fir.bindc_name = "a", fir.optional}, %[[N:.*]]: !fir.ref {fir.bindc_name = "n"}) { -! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[A]](%{{.*}}) {fortran_attrs = #fir.var_attrs, uniq_name = "_QMopenacc_boundsFacc_optional_data2Ea"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) -! CHECK: %[[NO_CREATE:.*]] = acc.nocreate varPtr(%[[DECL_A]]#1 : !fir.ref>) bounds(%10) -> !fir.ref> {name = "a"} +! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[A]](%{{.*}}) dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMopenacc_boundsFacc_optional_data2Ea"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) +! CHECK: %[[NO_CREATE:.*]] = acc.nocreate varPtr(%[[DECL_A]]#1 : !fir.ref>) bounds(%{{[0-9]+}}) -> !fir.ref> {name = "a"} ! CHECK: acc.data dataOperands(%[[NO_CREATE]] : !fir.ref>) { subroutine acc_optional_data3(a, n) @@ -175,7 +175,7 @@ contains ! CHECK-LABEL: func.func @_QMopenacc_boundsPacc_optional_data3( ! CHECK-SAME: %[[A:.*]]: !fir.ref> {fir.bindc_name = "a", fir.optional}, %[[N:.*]]: !fir.ref {fir.bindc_name = "n"}) { -! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[A]](%{{.*}}) {fortran_attrs = #fir.var_attrs, uniq_name = "_QMopenacc_boundsFacc_optional_data3Ea"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[A]](%{{.*}}) dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMopenacc_boundsFacc_optional_data3Ea"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) ! CHECK: %[[PRES:.*]] = fir.is_present %[[DECL_A]]#1 : (!fir.ref>) -> i1 ! CHECK: %[[STRIDE:.*]] = fir.if %[[PRES]] -> (index) { ! CHECK: %[[DIMS:.*]]:3 = fir.box_dims %[[DECL_A]]#0, %c0{{.*}} : (!fir.box>, index) -> (index, index, index) diff --git a/flang/test/Lower/OpenACC/acc-declare.f90 b/flang/test/Lower/OpenACC/acc-declare.f90 index 5d3f9e3fe97e..ff1e756c20e1 100644 --- a/flang/test/Lower/OpenACC/acc-declare.f90 +++ b/flang/test/Lower/OpenACC/acc-declare.f90 @@ -62,7 +62,7 @@ module acc_declare ! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_present( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "a"}) ! CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index -! CHECK-DAG: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_presentEa"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK-DAG: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_presentEa"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%{{.*}} : index) upperbound(%{{.*}} : index) extent(%{{.*}} : index) stride(%{{.*}} : index) startIdx(%[[C1]] : index) ! CHECK: %[[PRESENT:.*]] = acc.present varPtr(%[[DECL]]#0 : !fir.ref>) bounds(%[[BOUND]]) -> !fir.ref> {name = "a"} ! CHECK: acc.declare_enter dataOperands(%[[PRESENT]] : !fir.ref>) @@ -119,7 +119,7 @@ module acc_declare ! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_deviceptr( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "a"}) { -! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_deviceptrEa"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_deviceptrEa"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[DEVICEPTR:.*]] = acc.deviceptr varPtr(%[[DECL]]#0 : !fir.ref>) bounds(%{{.*}}) -> !fir.ref> {name = "a"} ! CHECK: acc.declare_enter dataOperands(%[[DEVICEPTR]] : !fir.ref>) ! CHECK: %{{.*}}:2 = fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}} iter_args(%arg{{.*}} = %{{.*}}) -> (index, i32) @@ -135,7 +135,7 @@ module acc_declare ! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_link( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "a"}) -! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_linkEa"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_linkEa"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[LINK:.*]] = acc.declare_link varPtr(%[[DECL]]#0 : !fir.ref>) bounds(%{{.*}}) -> !fir.ref> {name = "a"} ! CHECK: acc.declare_enter dataOperands(%[[LINK]] : !fir.ref>) ! CHECK: %{{.*}}:2 = fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}} iter_args(%arg{{.*}} = %{{.*}}) -> (index, i32) @@ -151,7 +151,7 @@ module acc_declare ! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_device_resident( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "a"}) -! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_device_residentEa"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_device_residentEa"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[DEVICERES:.*]] = acc.declare_device_resident varPtr(%[[DECL]]#0 : !fir.ref>) bounds(%{{.*}}) -> !fir.ref> {name = "a"} ! CHECK: %[[TOKEN:.*]] = acc.declare_enter dataOperands(%[[DEVICERES]] : !fir.ref>) ! CHECK: %{{.*}}:2 = fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}} iter_args(%arg{{.*}} = %{{.*}}) -> (index, i32) @@ -220,12 +220,12 @@ module acc_declare ! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_in_func2(%arg0: !fir.ref {fir.bindc_name = "i"}) -> f32 { ! CHECK: %[[ALLOCA_A:.*]] = fir.alloca !fir.array<1024xf32> {bindc_name = "a", uniq_name = "_QMacc_declareFacc_declare_in_func2Ea"} ! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[ALLOCA_A]](%{{.*}}) {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_in_func2Ea"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[CREATE:.*]] = acc.create varPtr(%[[DECL_A]]#0 : !fir.ref>) bounds(%7) -> !fir.ref> {name = "a"} +! CHECK: %[[CREATE:.*]] = acc.create varPtr(%[[DECL_A]]#0 : !fir.ref>) bounds(%{{[0-9]+}}) -> !fir.ref> {name = "a"} ! CHECK: %[[TOKEN:.*]] = acc.declare_enter dataOperands(%[[CREATE]] : !fir.ref>) ! CHECK: cf.br ^bb1 ! CHECK: ^bb1: ! CHECK: acc.declare_exit token(%[[TOKEN]]) dataOperands(%[[CREATE]] : !fir.ref>) -! CHECK: acc.delete accPtr(%[[CREATE]] : !fir.ref>) bounds(%7) {dataClause = #acc, name = "a"} +! CHECK: acc.delete accPtr(%[[CREATE]] : !fir.ref>) bounds(%{{[0-9]+}}) {dataClause = #acc, name = "a"} ! CHECK: return %{{.*}} : f32 ! CHECK: } @@ -294,8 +294,8 @@ module acc_declare ! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_multiple_directive( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.ref> {fir.bindc_name = "b"}) { -! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_multiple_directiveEa"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[DECL_B:.*]]:2 = hlfir.declare %[[ARG1]](%{{.*}}) {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_multiple_directiveEb"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_multiple_directiveEa"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[DECL_B:.*]]:2 = hlfir.declare %[[ARG1]](%{{.*}}) dummy_scope %{{[0-9]+}} {acc.declare = #acc.declare, uniq_name = "_QMacc_declareFacc_declare_multiple_directiveEb"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[COPYIN:.*]] = acc.copyin varPtr(%[[DECL_A]]#0 : !fir.ref>) bounds(%{{.*}}) -> !fir.ref> {dataClause = #acc, name = "a"} ! CHECK: %[[CREATE:.*]] = acc.create varPtr(%[[DECL_B]]#0 : !fir.ref>) bounds(%{{.*}}) -> !fir.ref> {dataClause = #acc, name = "b"} ! CHECK: acc.declare_enter dataOperands(%[[COPYIN]], %[[CREATE]] : !fir.ref>, !fir.ref>) @@ -316,7 +316,7 @@ module acc_declare ! CHECK-LABEL: func.func @_QMacc_declarePacc_declare_array_section( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "a"}) { -! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QMacc_declareFacc_declare_array_sectionEa"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMacc_declareFacc_declare_array_sectionEa"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[DECL_A]]#0 {acc.declare = #acc.declare} : (!fir.box>) -> !fir.ref> ! CHECK: %[[COPYIN:.*]] = acc.copyin varPtr(%[[BOX_ADDR]] : !fir.ref>) bounds(%{{.*}}) -> !fir.ref> {dataClause = #acc, name = "a(1:10)"} ! CHECK: acc.declare_enter dataOperands(%[[COPYIN]] : !fir.ref>) diff --git a/flang/test/Lower/OpenACC/acc-loop-exit.f90 b/flang/test/Lower/OpenACC/acc-loop-exit.f90 index c1ea057af667..85394e4a5b74 100644 --- a/flang/test/Lower/OpenACC/acc-loop-exit.f90 +++ b/flang/test/Lower/OpenACC/acc-loop-exit.f90 @@ -14,9 +14,9 @@ subroutine sub1(x, a) end ! CHECK-LABEL: func.func @_QPsub1 -! CHECK: %[[A:.*]]:2 = hlfir.declare %arg1 {uniq_name = "_QFsub1Ea"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[I:.*]]:2 = hlfir.declare %2 {uniq_name = "_QFsub1Ei"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[I:.*]]:2 = hlfir.declare %6 {uniq_name = "_QFsub1Ei"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[A:.*]]:2 = hlfir.declare %arg1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFsub1Ea"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[I:.*]]:2 = hlfir.declare %{{[0-9]+}} {uniq_name = "_QFsub1Ei"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[I:.*]]:2 = hlfir.declare %{{[0-9]+}} {uniq_name = "_QFsub1Ei"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[EXIT_COND:.*]] = acc.loop ! CHECK: ^bb{{.*}}: ! CHECK: ^bb{{.*}}: diff --git a/flang/test/Lower/OpenACC/acc-private.f90 b/flang/test/Lower/OpenACC/acc-private.f90 index 4d9f84b1fa74..a299a7486c3b 100644 --- a/flang/test/Lower/OpenACC/acc-private.f90 +++ b/flang/test/Lower/OpenACC/acc-private.f90 @@ -271,7 +271,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPacc_private_assumed_shape( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "a"} -! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QFacc_private_assumed_shapeEa"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFacc_private_assumed_shapeEa"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: acc.parallel {{.*}} { ! CHECK: %[[ADDR:.*]] = fir.box_addr %[[DECL_A]]#0 : (!fir.box>) -> !fir.ref> ! CHECK: %[[PRIVATE:.*]] = acc.private varPtr(%[[ADDR]] : !fir.ref>) bounds(%{{.*}}) -> !fir.ref> {name = "a"} @@ -293,7 +293,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPacc_private_allocatable_array( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>> {fir.bindc_name = "a"} -! CHECK: %[[DECLA_A:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFacc_private_allocatable_arrayEa"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[DECLA_A:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFacc_private_allocatable_arrayEa"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: acc.parallel {{.*}} { ! CHECK: %[[BOX:.*]] = fir.load %[[DECLA_A]]#0 : !fir.ref>>> ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[BOX]] : (!fir.box>>) -> !fir.heap> @@ -313,7 +313,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPacc_private_pointer_array( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>> {fir.bindc_name = "a"}, %arg1: !fir.ref {fir.bindc_name = "n"}) { -! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %arg0 {fortran_attrs = #fir.var_attrs, uniq_name = "_QFacc_private_pointer_arrayEa"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %arg0 dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFacc_private_pointer_arrayEa"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: acc.parallel {{.*}} { ! CHECK: %[[BOX:.*]] = fir.load %[[DECLA_A]]#0 : !fir.ref>>> ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[BOX]] : (!fir.box>>) -> !fir.ptr> @@ -332,8 +332,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPacc_private_dynamic_extent( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.ref {fir.bindc_name = "n"}) { -! CHECK: %[[DECL_N:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFacc_private_dynamic_extentEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {uniq_name = "_QFacc_private_dynamic_extentEa"} : (!fir.ref>, !fir.shape<3>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[DECL_N:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFacc_private_dynamic_extentEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {uniq_name = "_QFacc_private_dynamic_extentEa"} : (!fir.ref>, !fir.shape<3>, !fir.dscope) -> (!fir.box>, !fir.ref>) ! CHECK: acc.parallel {{.*}} { ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[DECL_A]]#0 : (!fir.box>) -> !fir.ref> ! CHECK: %[[PRIV:.*]] = acc.private varPtr(%[[BOX_ADDR]] : !fir.ref>) bounds(%{{.*}}, %{{.*}}, %{{.*}}) -> !fir.ref> {name = "a"} diff --git a/flang/test/Lower/OpenACC/acc-reduction.f90 b/flang/test/Lower/OpenACC/acc-reduction.f90 index 6918bc1ec7d6..545c4f217577 100644 --- a/flang/test/Lower/OpenACC/acc-reduction.f90 +++ b/flang/test/Lower/OpenACC/acc-reduction.f90 @@ -1162,7 +1162,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPacc_reduction_add_dynamic_extent_add_with_section( ! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "a"}) -! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QFacc_reduction_add_dynamic_extent_add_with_sectionEa"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFacc_reduction_add_dynamic_extent_add_with_sectionEa"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%c1{{.*}} : index) upperbound(%c3{{.*}} : index) extent(%{{.*}}#1 : index) stride(%{{.*}}#2 : index) startIdx(%{{.*}} : index) {strideInBytes = true} ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[DECL]]#0 : (!fir.box>) -> !fir.ref> ! CHECK: %[[RED:.*]] = acc.reduction varPtr(%[[BOX_ADDR]] : !fir.ref>) bounds(%[[BOUND]]) -> !fir.ref> {name = "a(2:4)"} @@ -1176,11 +1176,11 @@ end subroutine ! CHECK-LABEL: func.func @_QPacc_reduction_add_allocatable( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>> {fir.bindc_name = "a"}) -! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFacc_reduction_add_allocatableEa"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFacc_reduction_add_allocatableEa"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[BOX:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> ! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%c0{{.*}} : index) upperbound(%{{.*}} : index) extent(%{{.*}}#1 : index) stride(%{{.*}}#2 : index) startIdx(%{{.*}}#0 : index) {strideInBytes = true} ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[BOX]] : (!fir.box>>) -> !fir.heap> -! CHECK: %[[RED:.*]] = acc.reduction varPtr(%[[BOX_ADDR]] : !fir.heap>) bounds(%6) -> !fir.heap> {name = "a"} +! CHECK: %[[RED:.*]] = acc.reduction varPtr(%[[BOX_ADDR]] : !fir.heap>) bounds(%{{[0-9]+}}) -> !fir.heap> {name = "a"} ! CHECK: acc.parallel reduction(@reduction_max_box_heap_Uxf32 -> %[[RED]] : !fir.heap>) subroutine acc_reduction_add_pointer_array(a) @@ -1191,7 +1191,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPacc_reduction_add_pointer_array( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>> {fir.bindc_name = "a"}) -! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFacc_reduction_add_pointer_arrayEa"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFacc_reduction_add_pointer_arrayEa"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[BOX:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> ! CHECK: %[[BOUND:.*]] = acc.bounds lowerbound(%c0{{.*}} : index) upperbound(%{{.*}} : index) extent(%{{.*}}#1 : index) stride(%{{.*}}#2 : index) startIdx(%{{.*}}#0 : index) {strideInBytes = true} ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[BOX]] : (!fir.box>>) -> !fir.ptr> @@ -1207,7 +1207,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPacc_reduction_max_dynamic_extent_max( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "a"}, %{{.*}}: !fir.ref {fir.bindc_name = "n"}) -! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {uniq_name = "_QFacc_reduction_max_dynamic_extent_maxEa"} : (!fir.ref>, !fir.shape<2>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[DECL_A:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} {uniq_name = "_QFacc_reduction_max_dynamic_extent_maxEa"} : (!fir.ref>, !fir.shape<2>, !fir.dscope) -> (!fir.box>, !fir.ref>) ! CHECK: %[[ADDR:.*]] = fir.box_addr %[[DECL_A]]#0 : (!fir.box>) -> !fir.ref> ! CHECK: %[[RED:.*]] = acc.reduction varPtr(%[[ADDR]] : !fir.ref>) bounds(%{{.*}}, %{{.*}}) -> !fir.ref> {name = "a"} ! CHECK: acc.parallel reduction(@reduction_max_box_UxUxf32 -> %[[RED]] : !fir.ref>) diff --git a/flang/test/Lower/OpenMP/allocatable-array-bounds.f90 b/flang/test/Lower/OpenMP/allocatable-array-bounds.f90 index aeb56a0427e3..14a50692bc60 100644 --- a/flang/test/Lower/OpenMP/allocatable-array-bounds.f90 +++ b/flang/test/Lower/OpenMP/allocatable-array-bounds.f90 @@ -64,7 +64,7 @@ module assumed_allocatable_array_routines !HOST-LABEL: func.func @_QMassumed_allocatable_array_routinesPassumed_shape_array( -!HOST: %[[DECLARE:.*]]:2 = hlfir.declare %[[ARG:.*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMassumed_allocatable_array_routinesFassumed_shape_arrayEarr_read_write"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +!HOST: %[[DECLARE:.*]]:2 = hlfir.declare %[[ARG:.*]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMassumed_allocatable_array_routinesFassumed_shape_arrayEarr_read_write"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) !HOST: %[[LOAD_1:.*]] = fir.load %[[DECLARE]]#0 : !fir.ref>>> !HOST: %[[LOAD_2:.*]] = fir.load %[[DECLARE]]#1 : !fir.ref>>> !HOST: %[[CONSTANT_1:.*]] = arith.constant 0 : index diff --git a/flang/test/Lower/OpenMP/array-bounds.f90 b/flang/test/Lower/OpenMP/array-bounds.f90 index 2c8a8999a2cc..8c9d8944bf33 100644 --- a/flang/test/Lower/OpenMP/array-bounds.f90 +++ b/flang/test/Lower/OpenMP/array-bounds.f90 @@ -41,7 +41,7 @@ module assumed_array_routines !HOST-LABEL: func.func @_QMassumed_array_routinesPassumed_shape_array( !HOST-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "arr_read_write"}) { !HOST: %[[INTERMEDIATE_ALLOCA:.*]] = fir.alloca !fir.box> -!HOST: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMassumed_array_routinesFassumed_shape_arrayEarr_read_write"} : (!fir.box>) -> (!fir.box>, !fir.box>) +!HOST: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMassumed_array_routinesFassumed_shape_arrayEarr_read_write"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) !HOST: %[[C0:.*]] = arith.constant 1 : index !HOST: %[[C1:.*]] = arith.constant 0 : index !HOST: %[[DIMS0:.*]]:3 = fir.box_dims %[[ARG0_DECL]]#0, %[[C1]] : (!fir.box>, index) -> (index, index, index) @@ -69,7 +69,7 @@ module assumed_array_routines !HOST-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "arr_read_write"}) { !HOST: %[[INTERMEDIATE_ALLOCA:.*]] = fir.alloca !fir.box> !HOST: %[[ARG0_SHAPE:.*]] = fir.shape %{{.*}} : (index) -> !fir.shape<1> -!HOST: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]](%[[ARG0_SHAPE]]) {fortran_attrs = #fir.var_attrs, uniq_name = "_QMassumed_array_routinesFassumed_size_arrayEarr_read_write"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) +!HOST: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]](%[[ARG0_SHAPE]]) dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMassumed_array_routinesFassumed_size_arrayEarr_read_write"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) !HOST: %[[ALLOCA:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QMassumed_array_routinesFassumed_size_arrayEi"} !HOST: %[[DIMS0:.*]]:3 = fir.box_dims %[[ARG0_DECL]]#0, %c0{{.*}} : (!fir.box>, index) -> (index, index, index) !HOST: %[[C4_1:.*]] = arith.subi %c4, %c1{{.*}} : index diff --git a/flang/test/Lower/OpenMP/flush.f90 b/flang/test/Lower/OpenMP/flush.f90 index ad2e3609ebef..8438fdba4ee4 100644 --- a/flang/test/Lower/OpenMP/flush.f90 +++ b/flang/test/Lower/OpenMP/flush.f90 @@ -7,9 +7,9 @@ subroutine flush_standalone(a, b, c) integer, intent(inout) :: a, b, c -!CHECK: %[[A:.*]]:2 = hlfir.declare %[[ARG_A]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFflush_standaloneEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[B:.*]]:2 = hlfir.declare %[[ARG_B]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFflush_standaloneEb"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[C:.*]]:2 = hlfir.declare %[[ARG_C]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFflush_standaloneEc"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[A:.*]]:2 = hlfir.declare %[[ARG_A]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFflush_standaloneEa"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[B:.*]]:2 = hlfir.declare %[[ARG_B]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFflush_standaloneEb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[C:.*]]:2 = hlfir.declare %[[ARG_C]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFflush_standaloneEc"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: omp.flush(%[[A]]#1, %[[B]]#1, %[[C]]#1 : !fir.ref, !fir.ref, !fir.ref) !CHECK: omp.flush !$omp flush(a,b,c) @@ -21,9 +21,9 @@ end subroutine flush_standalone !CHECK-SAME: %[[ARG_A:.*]]: !fir.ref {fir.bindc_name = "a"}, %[[ARG_B:.*]]: !fir.ref {fir.bindc_name = "b"}, %[[ARG_C:.*]]: !fir.ref {fir.bindc_name = "c"}) subroutine flush_parallel(a, b, c) integer, intent(inout) :: a, b, c -!CHECK: %[[A:.*]]:2 = hlfir.declare %[[ARG_A]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFflush_parallelEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[B:.*]]:2 = hlfir.declare %[[ARG_B]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFflush_parallelEb"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[C:.*]]:2 = hlfir.declare %[[ARG_C]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFflush_parallelEc"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[A:.*]]:2 = hlfir.declare %[[ARG_A]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFflush_parallelEa"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[B:.*]]:2 = hlfir.declare %[[ARG_B]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFflush_parallelEb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[C:.*]]:2 = hlfir.declare %[[ARG_C]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFflush_parallelEc"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !$omp parallel !CHECK: omp.parallel @@ -34,7 +34,7 @@ subroutine flush_parallel(a, b, c) !CHECK: %[[A_VAL:.*]] = fir.load %[[A]]#0 : !fir.ref !CHECK: %[[B_VAL:.*]] = fir.load %[[B]]#0 : !fir.ref -!CHECK: %[[C_VAL:.*]] = arith.addi %3, %4 : i32 +!CHECK: %[[C_VAL:.*]] = arith.addi %[[A_VAL]], %[[B_VAL]] : i32 !CHECK: hlfir.assign %[[C_VAL]] to %[[C]]#0 : i32, !fir.ref c = a + b diff --git a/flang/test/Lower/OpenMP/parallel-firstprivate-clause-scalar.f90 b/flang/test/Lower/OpenMP/parallel-firstprivate-clause-scalar.f90 index 6402f98a2add..93dcd4b74b00 100644 --- a/flang/test/Lower/OpenMP/parallel-firstprivate-clause-scalar.f90 +++ b/flang/test/Lower/OpenMP/parallel-firstprivate-clause-scalar.f90 @@ -4,8 +4,8 @@ ! RUN: bbc -fopenmp -emit-hlfir %s -o - | FileCheck %s --check-prefix=CHECK !CHECK-DAG: func @_QPfirstprivate_complex(%[[ARG1:.*]]: !fir.ref>{{.*}}, %[[ARG2:.*]]: !fir.ref>{{.*}}) { -!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFfirstprivate_complexEarg1"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFfirstprivate_complexEarg2"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_complexEarg1"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_complexEarg2"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) !CHECK: omp.parallel { !CHECK: %[[ARG1_PVT:.*]] = fir.alloca !fir.complex<4> {bindc_name = "arg1", pinned, uniq_name = "_QFfirstprivate_complexEarg1"} !CHECK: %[[ARG1_PVT_DECL:.*]]:2 = hlfir.declare %[[ARG1_PVT]] {uniq_name = "_QFfirstprivate_complexEarg1"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) @@ -30,12 +30,12 @@ subroutine firstprivate_complex(arg1, arg2) end subroutine !CHECK-DAG: func @_QPfirstprivate_integer(%[[ARG1:.*]]: !fir.ref{{.*}}, %[[ARG2:.*]]: !fir.ref{{.*}}, %[[ARG3:.*]]: !fir.ref{{.*}}, %[[ARG4:.*]]: !fir.ref{{.*}}, %[[ARG5:.*]]: !fir.ref{{.*}}, %[[ARG6:.*]]: !fir.ref{{.*}}) { -!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFfirstprivate_integerEarg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFfirstprivate_integerEarg2"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG3_DECL:.*]]:2 = hlfir.declare %[[ARG3]] {uniq_name = "_QFfirstprivate_integerEarg3"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG4_DECL:.*]]:2 = hlfir.declare %[[ARG4]] {uniq_name = "_QFfirstprivate_integerEarg4"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG5_DECL:.*]]:2 = hlfir.declare %[[ARG5]] {uniq_name = "_QFfirstprivate_integerEarg5"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG6_DECL:.*]]:2 = hlfir.declare %[[ARG6]] {uniq_name = "_QFfirstprivate_integerEarg6"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_integerEarg1"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_integerEarg2"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG3_DECL:.*]]:2 = hlfir.declare %[[ARG3]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_integerEarg3"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG4_DECL:.*]]:2 = hlfir.declare %[[ARG4]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_integerEarg4"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG5_DECL:.*]]:2 = hlfir.declare %[[ARG5]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_integerEarg5"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG6_DECL:.*]]:2 = hlfir.declare %[[ARG6]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_integerEarg6"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: omp.parallel { !CHECK: %[[ARG1_PVT:.*]] = fir.alloca i32 {bindc_name = "arg1", pinned, uniq_name = "_QFfirstprivate_integerEarg1"} !CHECK: %[[ARG1_PVT_DECL:.*]]:2 = hlfir.declare %[[ARG1_PVT]] {uniq_name = "_QFfirstprivate_integerEarg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) @@ -81,11 +81,11 @@ subroutine firstprivate_integer(arg1, arg2, arg3, arg4, arg5, arg6) end subroutine !CHECK-DAG: func @_QPfirstprivate_logical(%[[ARG1:.*]]: !fir.ref>{{.*}}, %[[ARG2:.*]]: !fir.ref>{{.*}}, %[[ARG3:.*]]: !fir.ref>{{.*}}, %[[ARG4:.*]]: !fir.ref>{{.*}}, %[[ARG5:.*]]: !fir.ref>{{.*}}) { -!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFfirstprivate_logicalEarg1"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFfirstprivate_logicalEarg2"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -!CHECK: %[[ARG3_DECL:.*]]:2 = hlfir.declare %[[ARG3]] {uniq_name = "_QFfirstprivate_logicalEarg3"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -!CHECK: %[[ARG4_DECL:.*]]:2 = hlfir.declare %[[ARG4]] {uniq_name = "_QFfirstprivate_logicalEarg4"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -!CHECK: %[[ARG5_DECL:.*]]:2 = hlfir.declare %[[ARG5]] {uniq_name = "_QFfirstprivate_logicalEarg5"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_logicalEarg1"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_logicalEarg2"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +!CHECK: %[[ARG3_DECL:.*]]:2 = hlfir.declare %[[ARG3]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_logicalEarg3"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +!CHECK: %[[ARG4_DECL:.*]]:2 = hlfir.declare %[[ARG4]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_logicalEarg4"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +!CHECK: %[[ARG5_DECL:.*]]:2 = hlfir.declare %[[ARG5]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_logicalEarg5"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) !CHECK: omp.parallel { !CHECK: %[[ARG1_PVT:.*]] = fir.alloca !fir.logical<4> {bindc_name = "arg1", pinned, uniq_name = "_QFfirstprivate_logicalEarg1"} !CHECK: %[[ARG1_PVT_DECL:.*]]:2 = hlfir.declare %[[ARG1_PVT]] {uniq_name = "_QFfirstprivate_logicalEarg1"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) @@ -125,12 +125,12 @@ subroutine firstprivate_logical(arg1, arg2, arg3, arg4, arg5) end subroutine !CHECK-DAG: func @_QPfirstprivate_real(%[[ARG1:.*]]: !fir.ref{{.*}}, %[[ARG2:.*]]: !fir.ref{{.*}}, %[[ARG3:.*]]: !fir.ref{{.*}}, %[[ARG4:.*]]: !fir.ref{{.*}}, %[[ARG5:.*]]: !fir.ref{{.*}}, %[[ARG6:.*]]: !fir.ref{{.*}}) { -!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFfirstprivate_realEarg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFfirstprivate_realEarg2"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG3_DECL:.*]]:2 = hlfir.declare %[[ARG3]] {uniq_name = "_QFfirstprivate_realEarg3"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG4_DECL:.*]]:2 = hlfir.declare %[[ARG4]] {uniq_name = "_QFfirstprivate_realEarg4"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG5_DECL:.*]]:2 = hlfir.declare %[[ARG5]] {uniq_name = "_QFfirstprivate_realEarg5"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG6_DECL:.*]]:2 = hlfir.declare %[[ARG6]] {uniq_name = "_QFfirstprivate_realEarg6"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_realEarg1"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_realEarg2"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG3_DECL:.*]]:2 = hlfir.declare %[[ARG3]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_realEarg3"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG4_DECL:.*]]:2 = hlfir.declare %[[ARG4]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_realEarg4"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG5_DECL:.*]]:2 = hlfir.declare %[[ARG5]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_realEarg5"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG6_DECL:.*]]:2 = hlfir.declare %[[ARG6]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivate_realEarg6"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: omp.parallel { !CHECK: %[[ARG1_PVT:.*]] = fir.alloca f32 {bindc_name = "arg1", pinned, uniq_name = "_QFfirstprivate_realEarg1"} !CHECK: %[[ARG1_PVT_DECL:.*]]:2 = hlfir.declare %[[ARG1_PVT]] {uniq_name = "_QFfirstprivate_realEarg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) @@ -177,8 +177,8 @@ end subroutine !CHECK-LABEL: func.func @_QPmultiple_firstprivate( !CHECK-SAME: %[[A_ADDR:.*]]: !fir.ref {fir.bindc_name = "a"}, !CHECK-SAME: %[[B_ADDR:.*]]: !fir.ref {fir.bindc_name = "b"}) { -!CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A_ADDR]] {uniq_name = "_QFmultiple_firstprivateEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[B_DECL:.*]]:2 = hlfir.declare %[[B_ADDR]] {uniq_name = "_QFmultiple_firstprivateEb"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A_ADDR]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmultiple_firstprivateEa"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[B_DECL:.*]]:2 = hlfir.declare %[[B_ADDR]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmultiple_firstprivateEb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: omp.parallel { !CHECK: %[[A_PRIV_ADDR:.*]] = fir.alloca i32 {bindc_name = "a", pinned, uniq_name = "_QFmultiple_firstprivateEa"} !CHECK: %[[A_PRIV_DECL:.*]]:2 = hlfir.declare %[[A_PRIV_ADDR]] {uniq_name = "_QFmultiple_firstprivateEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) diff --git a/flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90 b/flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90 index bb81e5eac62f..b7f11c8c722f 100644 --- a/flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90 +++ b/flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90 @@ -7,7 +7,7 @@ !CHECK-DAG: %[[ARG1_UNBOX:.*]]:2 = fir.unboxchar !CHECK-DAG: %[[FIVE:.*]] = arith.constant 5 : index !CHECK-DAG: %[[ARG1_REF:.*]] = fir.convert %[[ARG1_UNBOX]]#0 : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1_REF]] typeparams %[[FIVE]] {uniq_name = "_QFlastprivate_characterEarg1"} : (!fir.ref>, index) -> (!fir.ref>, !fir.ref>) +!CHECK-DAG: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1_REF]] typeparams %[[FIVE]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFlastprivate_characterEarg1"} : (!fir.ref>, index, !fir.dscope) -> (!fir.ref>, !fir.ref>) !CHECK: omp.parallel { !CHECK-DAG: %[[ARG1_PVT:.*]] = fir.alloca !fir.char<1,5> {bindc_name = "arg1", @@ -57,7 +57,7 @@ end do end subroutine !CHECK: func @_QPlastprivate_int(%[[ARG1:.*]]: !fir.ref {fir.bindc_name = "arg1"}) { -!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFlastprivate_intEarg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFlastprivate_intEarg1"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK-DAG: omp.parallel { !CHECK-DAG: %[[CLONE:.*]] = fir.alloca i32 {bindc_name = "arg1" !CHECK-DAG: %[[CLONE_DECL:.*]]:2 = hlfir.declare %[[CLONE]] {uniq_name = "_QFlastprivate_intEarg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) @@ -97,8 +97,8 @@ print *, arg1 end subroutine !CHECK: func.func @_QPmult_lastprivate_int(%[[ARG1:.*]]: !fir.ref {fir.bindc_name = "arg1"}, %[[ARG2:.*]]: !fir.ref {fir.bindc_name = "arg2"}) { -!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFmult_lastprivate_intEarg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFmult_lastprivate_intEarg2"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmult_lastprivate_intEarg1"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmult_lastprivate_intEarg2"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: omp.parallel { !CHECK-DAG: %[[CLONE1:.*]] = fir.alloca i32 {bindc_name = "arg1" !CHECK-DAG: %[[CLONE1_DECL:.*]]:2 = hlfir.declare %[[CLONE1]] {uniq_name = "_QFmult_lastprivate_intEarg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) @@ -142,8 +142,8 @@ print *, arg1, arg2 end subroutine !CHECK: func.func @_QPmult_lastprivate_int2(%[[ARG1:.*]]: !fir.ref {fir.bindc_name = "arg1"}, %[[ARG2:.*]]: !fir.ref {fir.bindc_name = "arg2"}) { -!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %arg0 {uniq_name = "_QFmult_lastprivate_int2Earg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %arg1 {uniq_name = "_QFmult_lastprivate_int2Earg2"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmult_lastprivate_int2Earg1"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmult_lastprivate_int2Earg2"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: omp.parallel { !CHECK-DAG: %[[CLONE1:.*]] = fir.alloca i32 {bindc_name = "arg1" !CHECK-DAG: %[[CLONE1_DECL:.*]]:2 = hlfir.declare %[[CLONE1]] {uniq_name = "_QFmult_lastprivate_int2Earg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) @@ -187,8 +187,8 @@ print *, arg1, arg2 end subroutine !CHECK: func.func @_QPfirstpriv_lastpriv_int(%[[ARG1:.*]]: !fir.ref {fir.bindc_name = "arg1"}, %[[ARG2:.*]]: !fir.ref {fir.bindc_name = "arg2"}) { -!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFfirstpriv_lastpriv_intEarg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFfirstpriv_lastpriv_intEarg2"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstpriv_lastpriv_intEarg1"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG2_DECL:.*]]:2 = hlfir.declare %[[ARG2]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstpriv_lastpriv_intEarg2"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: omp.parallel { ! Firstprivate update !CHECK: %[[CLONE1:.*]] = fir.alloca i32 {bindc_name = "arg1" @@ -235,7 +235,7 @@ print *, arg1, arg2 end subroutine !CHECK: func.func @_QPfirstpriv_lastpriv_int2(%[[ARG1:.*]]: !fir.ref {fir.bindc_name = "arg1"}) { -!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFfirstpriv_lastpriv_int2Earg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstpriv_lastpriv_int2Earg1"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: omp.parallel { ! Firstprivate update !CHECK: %[[CLONE1:.*]] = fir.alloca i32 {bindc_name = "arg1" diff --git a/flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90 b/flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90 index f8343338112c..d3843c8e241a 100644 --- a/flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90 +++ b/flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90 @@ -4,7 +4,7 @@ ! CHECK-LABEL: multiple_private_fix ! CHECK-SAME: %[[GAMA:.*]]: !fir.ref {fir.bindc_name = "gama"} -! CHECK-DAG: %[[GAMA_DECL:.*]]:2 = hlfir.declare %[[GAMA]] {uniq_name = "_QFmultiple_private_fixEgama"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK-DAG: %[[GAMA_DECL:.*]]:2 = hlfir.declare %[[GAMA]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFmultiple_private_fixEgama"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK-DAG: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFmultiple_private_fixEi"} ! CHECK-DAG: %[[I_DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFmultiple_private_fixEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK-DAG: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "j", uniq_name = "_QFmultiple_private_fixEj"} @@ -99,7 +99,7 @@ end subroutine ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "aaa"}) { ! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> ! CHECK: %[[VAL_2:.*]] = fir.box_elesize %[[VAL_1]] : (!fir.box>>) -> index -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_2]] {fortran_attrs = #{{.*}}, uniq_name = "_QFsub01Eaaa"} : (!fir.ref>>>, index) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_2]] dummy_scope %{{[0-9]+}} {fortran_attrs = #{{.*}}, uniq_name = "_QFsub01Eaaa"} : (!fir.ref>>>, index, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: omp.parallel { ! CHECK: %[[VAL_4:.*]] = fir.alloca !fir.box>> {bindc_name = "aaa", pinned, uniq_name = "_QFsub01Eaaa"} ! CHECK: %[[VAL_5:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref>>> @@ -148,7 +148,7 @@ end subroutine ! CHECK-LABEL: func.func @_QPsub02( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "bbb"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #{{.*}}, uniq_name = "_QFsub02Ebbb"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #{{.*}}, uniq_name = "_QFsub02Ebbb"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: omp.parallel { ! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.box>> {bindc_name = "bbb", pinned, uniq_name = "_QFsub02Ebbb"} ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> diff --git a/flang/test/Lower/OpenMP/parallel-private-clause-str.f90 b/flang/test/Lower/OpenMP/parallel-private-clause-str.f90 index 025e51e06617..19ea37c5339b 100644 --- a/flang/test/Lower/OpenMP/parallel-private-clause-str.f90 +++ b/flang/test/Lower/OpenMP/parallel-private-clause-str.f90 @@ -30,8 +30,8 @@ subroutine test_allocatable_string(n) !$omp end parallel end subroutine -!CHECK: func.func @_QPtest_allocatable_string_array(%{{.*}}: !fir.ref {fir.bindc_name = "n"}) { -!CHECK: %0:2 = hlfir.declare %arg0 {uniq_name = "_QFtest_allocatable_string_arrayEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: func.func @_QPtest_allocatable_string_array(%[[ARG0:.*]]: !fir.ref {fir.bindc_name = "n"}) { +!CHECK: %{{.*}} = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_allocatable_string_arrayEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: %[[C_BOX_REF:.*]] = fir.alloca !fir.box>>> {bindc_name = "c", uniq_name = "_QFtest_allocatable_string_arrayEc"} !CHECK: %[[C_BOX:.*]] = fir.embox %{{.*}}(%{{.*}}) typeparams %{{.*}} : (!fir.heap>>, !fir.shape<1>, i32) -> !fir.box>>> !CHECK: fir.store %[[C_BOX]] to %[[C_BOX_REF]] : !fir.ref>>>> diff --git a/flang/test/Lower/OpenMP/parallel-reduction3.f90 b/flang/test/Lower/OpenMP/parallel-reduction3.f90 index 2a4e338f255e..17d805c0d142 100644 --- a/flang/test/Lower/OpenMP/parallel-reduction3.f90 +++ b/flang/test/Lower/OpenMP/parallel-reduction3.f90 @@ -52,7 +52,7 @@ ! CHECK-LABEL: func.func @_QPs( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFsEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFsEx"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsEi"} ! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_2]] {uniq_name = "_QFsEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref diff --git a/flang/test/Lower/OpenMP/parallel-wsloop-firstpriv.f90 b/flang/test/Lower/OpenMP/parallel-wsloop-firstpriv.f90 index ac8b9f50f54e..c32eb2400a34 100644 --- a/flang/test/Lower/OpenMP/parallel-wsloop-firstpriv.f90 +++ b/flang/test/Lower/OpenMP/parallel-wsloop-firstpriv.f90 @@ -5,7 +5,7 @@ ! CHECK: func @_QPomp_do_firstprivate(%[[ARG0:.*]]: !fir.ref {fir.bindc_name = "a"}) subroutine omp_do_firstprivate(a) - ! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QFomp_do_firstprivateEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFomp_do_firstprivateEa"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) integer::a integer::n n = a+1 @@ -38,8 +38,8 @@ end subroutine omp_do_firstprivate ! CHECK: func @_QPomp_do_firstprivate2(%[[ARG0:.*]]: !fir.ref {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.ref {fir.bindc_name = "n"}) subroutine omp_do_firstprivate2(a, n) - ! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QFomp_do_firstprivate2Ea"} : (!fir.ref) -> (!fir.ref, !fir.ref) - ! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFomp_do_firstprivate2En"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFomp_do_firstprivate2Ea"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) + ! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFomp_do_firstprivate2En"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) integer::a integer::n n = a+1 diff --git a/flang/test/Lower/OpenMP/parallel-wsloop.f90 b/flang/test/Lower/OpenMP/parallel-wsloop.f90 index 602b3d1c05f0..5fa42da2269f 100644 --- a/flang/test/Lower/OpenMP/parallel-wsloop.f90 +++ b/flang/test/Lower/OpenMP/parallel-wsloop.f90 @@ -27,8 +27,8 @@ end subroutine ! CHECK-LABEL: func @_QPparallel_do_with_parallel_clauses ! CHECK-SAME: %[[COND_REF:.*]]: !fir.ref> {fir.bindc_name = "cond"}, %[[NT_REF:.*]]: !fir.ref {fir.bindc_name = "nt"} subroutine parallel_do_with_parallel_clauses(cond, nt) - ! CHECK: %[[COND_DECL:.*]]:2 = hlfir.declare %[[COND_REF]] {uniq_name = "_QFparallel_do_with_parallel_clausesEcond"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) - ! CHECK: %[[NT_DECL:.*]]:2 = hlfir.declare %[[NT_REF]] {uniq_name = "_QFparallel_do_with_parallel_clausesEnt"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[COND_DECL:.*]]:2 = hlfir.declare %[[COND_REF]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFparallel_do_with_parallel_clausesEcond"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) + ! CHECK: %[[NT_DECL:.*]]:2 = hlfir.declare %[[NT_REF]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFparallel_do_with_parallel_clausesEnt"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) logical :: cond integer :: nt integer :: i @@ -57,7 +57,7 @@ end subroutine ! CHECK-LABEL: func @_QPparallel_do_with_clauses ! CHECK-SAME: %[[NT_REF:.*]]: !fir.ref {fir.bindc_name = "nt"} subroutine parallel_do_with_clauses(nt) - ! CHECK: %[[NT_DECL:.*]]:2 = hlfir.declare %[[NT_REF]] {uniq_name = "_QFparallel_do_with_clausesEnt"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[NT_DECL:.*]]:2 = hlfir.declare %[[NT_REF]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFparallel_do_with_clausesEnt"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) integer :: nt integer :: i ! CHECK: %[[NT:.*]] = fir.load %[[NT_DECL]]#0 : !fir.ref @@ -88,8 +88,8 @@ end subroutine ! CHECK-LABEL: func @_QPparallel_do_with_privatisation_clauses ! CHECK-SAME: %[[COND_REF:.*]]: !fir.ref> {fir.bindc_name = "cond"}, %[[NT_REF:.*]]: !fir.ref {fir.bindc_name = "nt"} subroutine parallel_do_with_privatisation_clauses(cond,nt) - ! CHECK: %[[COND_DECL:.*]]:2 = hlfir.declare %[[COND_REF]] {uniq_name = "_QFparallel_do_with_privatisation_clausesEcond"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) - ! CHECK: %[[NT_DECL:.*]]:2 = hlfir.declare %[[NT_REF]] {uniq_name = "_QFparallel_do_with_privatisation_clausesEnt"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[COND_DECL:.*]]:2 = hlfir.declare %[[COND_REF]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFparallel_do_with_privatisation_clausesEcond"} : (!fir.ref>, !fir.dscope) -> (!fir.ref>, !fir.ref>) + ! CHECK: %[[NT_DECL:.*]]:2 = hlfir.declare %[[NT_REF]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFparallel_do_with_privatisation_clausesEnt"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) logical :: cond integer :: nt integer :: i @@ -145,7 +145,7 @@ end subroutine parallel_private_do ! CHECK-LABEL: func.func @_QPparallel_private_do( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> {fir.bindc_name = "cond"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "nt"}) { -! CHECK: %[[NT_DECL:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFparallel_private_doEnt"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[NT_DECL:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFparallel_private_doEnt"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: omp.parallel { ! CHECK: %[[I_PRIV:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} ! CHECK: %[[I_PRIV_DECL:.*]]:2 = hlfir.declare %[[I_PRIV]] {uniq_name = "_QFparallel_private_doEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) @@ -191,8 +191,8 @@ end subroutine omp_parallel_multiple_firstprivate_do ! CHECK-LABEL: func.func @_QPomp_parallel_multiple_firstprivate_do( ! CHECK-SAME: %[[A_ADDR:.*]]: !fir.ref {fir.bindc_name = "a"}, ! CHECK-SAME: %[[B_ADDR:.*]]: !fir.ref {fir.bindc_name = "b"}) { -! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A_ADDR]] {uniq_name = "_QFomp_parallel_multiple_firstprivate_doEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[B_DECL:.*]]:2 = hlfir.declare %[[B_ADDR]] {uniq_name = "_QFomp_parallel_multiple_firstprivate_doEb"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A_ADDR]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFomp_parallel_multiple_firstprivate_doEa"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[B_DECL:.*]]:2 = hlfir.declare %[[B_ADDR]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFomp_parallel_multiple_firstprivate_doEb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: omp.parallel { ! CHECK: %[[I_PRIV_ADDR:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} ! CHECK: %[[I_PRIV_DECL:.*]]:2 = hlfir.declare %[[I_PRIV_ADDR]] {uniq_name = "_QFomp_parallel_multiple_firstprivate_doEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) @@ -242,7 +242,7 @@ end subroutine parallel_do_private ! CHECK-LABEL: func.func @_QPparallel_do_private( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> {fir.bindc_name = "cond"}, ! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "nt"}) { -! CHECK: %[[NT_DECL:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFparallel_do_privateEnt"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[NT_DECL:.*]]:2 = hlfir.declare %[[VAL_1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFparallel_do_privateEnt"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: omp.parallel { ! CHECK: %[[I_PRIV_ADDR:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} ! CHECK: %[[I_PRIV_DECL:.*]]:2 = hlfir.declare %[[I_PRIV_ADDR]] {uniq_name = "_QFparallel_do_privateEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) @@ -288,8 +288,8 @@ end subroutine omp_parallel_do_multiple_firstprivate ! CHECK-LABEL: func.func @_QPomp_parallel_do_multiple_firstprivate( ! CHECK-SAME: %[[A_ADDR:.*]]: !fir.ref {fir.bindc_name = "a"}, ! CHECK-SAME: %[[B_ADDR:.*]]: !fir.ref {fir.bindc_name = "b"}) { -! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A_ADDR]] {uniq_name = "_QFomp_parallel_do_multiple_firstprivateEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[B_DECL:.*]]:2 = hlfir.declare %[[B_ADDR]] {uniq_name = "_QFomp_parallel_do_multiple_firstprivateEb"} : (!fir.ref) -> (!fir.ref, !fir.ref +! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A_ADDR]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFomp_parallel_do_multiple_firstprivateEa"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[B_DECL:.*]]:2 = hlfir.declare %[[B_ADDR]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFomp_parallel_do_multiple_firstprivateEb"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref ! CHECK: omp.parallel { ! CHECK: %[[I_PRIV_ADDR:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} ! CHECK: %[[I_PRIV_DECL:.*]]:2 = hlfir.declare %[[I_PRIV_ADDR]] {uniq_name = "_QFomp_parallel_do_multiple_firstprivateEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) diff --git a/flang/test/Lower/OpenMP/sections.f90 b/flang/test/Lower/OpenMP/sections.f90 index a93d6e34e374..bd76bd53e5a0 100644 --- a/flang/test/Lower/OpenMP/sections.f90 +++ b/flang/test/Lower/OpenMP/sections.f90 @@ -79,7 +79,7 @@ program sample end program sample !CHECK: func @_QPfirstprivate(%[[ARG:.*]]: !fir.ref {fir.bindc_name = "alpha"}) { -!CHECK: %[[ARG_DECL:.*]]:2 = hlfir.declare %[[ARG]] {uniq_name = "_QFfirstprivateEalpha"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[ARG_DECL:.*]]:2 = hlfir.declare %[[ARG]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFfirstprivateEalpha"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: %[[PRIVATE_ALPHA:.*]] = fir.alloca f32 {bindc_name = "alpha", pinned, uniq_name = "_QFfirstprivateEalpha"} !CHECK: %[[PRIVATE_ALPHA_DECL:.*]]:2 = hlfir.declare %[[PRIVATE_ALPHA]] {uniq_name = "_QFfirstprivateEalpha"} : (!fir.ref) -> (!fir.ref, !fir.ref) !CHECK: %[[TEMP:.*]] = fir.load %[[ARG_DECL]]#0 : !fir.ref diff --git a/flang/test/Lower/OpenMP/simd.f90 b/flang/test/Lower/OpenMP/simd.f90 index 8ec1a3cefb4a..223b248b7934 100644 --- a/flang/test/Lower/OpenMP/simd.f90 +++ b/flang/test/Lower/OpenMP/simd.f90 @@ -24,7 +24,7 @@ end subroutine !CHECK-LABEL: func @_QPsimd_with_if_clause subroutine simd_with_if_clause(n, threshold) - ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFsimd_with_if_clauseEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimd_with_if_clauseEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) integer :: i, n, threshold !$OMP SIMD IF( n .GE. threshold ) ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 @@ -44,7 +44,7 @@ end subroutine !CHECK-LABEL: func @_QPsimd_with_simdlen_clause subroutine simd_with_simdlen_clause(n, threshold) - ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFsimd_with_simdlen_clauseEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimd_with_simdlen_clauseEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) integer :: i, n, threshold !$OMP SIMD SIMDLEN(2) ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 @@ -63,7 +63,7 @@ end subroutine !CHECK-LABEL: func @_QPsimd_with_simdlen_clause_from_param subroutine simd_with_simdlen_clause_from_param(n, threshold) - ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFsimd_with_simdlen_clause_from_paramEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimd_with_simdlen_clause_from_paramEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) integer :: i, n, threshold integer, parameter :: simdlen = 2; !$OMP SIMD SIMDLEN(simdlen) @@ -83,7 +83,7 @@ end subroutine !CHECK-LABEL: func @_QPsimd_with_simdlen_clause_from_expr_from_param subroutine simd_with_simdlen_clause_from_expr_from_param(n, threshold) - ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFsimd_with_simdlen_clause_from_expr_from_paramEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimd_with_simdlen_clause_from_expr_from_paramEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) integer :: i, n, threshold integer, parameter :: simdlen = 2; !$OMP SIMD SIMDLEN(simdlen*2 + 2) @@ -103,7 +103,7 @@ end subroutine !CHECK-LABEL: func @_QPsimd_with_safelen_clause subroutine simd_with_safelen_clause(n, threshold) - ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFsimd_with_safelen_clauseEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimd_with_safelen_clauseEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) integer :: i, n, threshold !$OMP SIMD SAFELEN(2) ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 @@ -122,7 +122,7 @@ end subroutine !CHECK-LABEL: func @_QPsimd_with_safelen_clause_from_expr_from_param subroutine simd_with_safelen_clause_from_expr_from_param(n, threshold) - ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFsimd_with_safelen_clause_from_expr_from_paramEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimd_with_safelen_clause_from_expr_from_paramEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) integer :: i, n, threshold integer, parameter :: safelen = 2; !$OMP SIMD SAFELEN(safelen*2 + 2) @@ -142,7 +142,7 @@ end subroutine !CHECK-LABEL: func @_QPsimd_with_simdlen_safelen_clause subroutine simd_with_simdlen_safelen_clause(n, threshold) - ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFsimd_with_simdlen_safelen_clauseEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[ARG_N:.*]]:2 = hlfir.declare %{{.*}} dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimd_with_simdlen_safelen_clauseEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) integer :: i, n, threshold !$OMP SIMD SIMDLEN(1) SAFELEN(2) ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 diff --git a/flang/test/Lower/OpenMP/single.f90 b/flang/test/Lower/OpenMP/single.f90 index 10d537a0e18b..91f8a592909a 100644 --- a/flang/test/Lower/OpenMP/single.f90 +++ b/flang/test/Lower/OpenMP/single.f90 @@ -11,7 +11,7 @@ !CHECK-SAME: (%[[X:.*]]: !fir.ref {fir.bindc_name = "x"}) subroutine omp_single(x) integer, intent(inout) :: x - !CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFomp_singleEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) + !CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFomp_singleEx"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: omp.parallel !$omp parallel !CHECK: omp.single @@ -34,7 +34,7 @@ end subroutine omp_single !CHECK-SAME: (%[[X:.*]]: !fir.ref {fir.bindc_name = "x"}) subroutine omp_single_nowait(x) integer, intent(inout) :: x - !CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFomp_single_nowaitEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) + !CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFomp_single_nowaitEx"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: omp.parallel !$omp parallel !CHECK: omp.single nowait @@ -76,8 +76,8 @@ end subroutine single_allocate ! CHECK-LABEL: func.func @_QPsingle_privatization( ! CHECK-SAME: %[[X:.*]]: !fir.ref {fir.bindc_name = "x"}, ! CHECK-SAME: %[[Y:.*]]: !fir.ref {fir.bindc_name = "y"}) { -! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] {uniq_name = "_QFsingle_privatizationEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[Y]] {uniq_name = "_QFsingle_privatizationEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFsingle_privatizationEx"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[Y]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFsingle_privatizationEy"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: omp.single { ! CHECK: %[[X_PVT:.*]] = fir.alloca f32 {bindc_name = "x", pinned, uniq_name = "_QFsingle_privatizationEx"} ! CHECK: %[[X_PVT_DECL:.*]]:2 = hlfir.declare %[[X_PVT]] {uniq_name = "_QFsingle_privatizationEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) @@ -103,8 +103,8 @@ end subroutine ! CHECK-LABEL: func.func @_QPsingle_privatization2( ! CHECK-SAME: %[[X:.*]]: !fir.ref {fir.bindc_name = "x"}, ! CHECK-SAME: %[[Y:.*]]: !fir.ref {fir.bindc_name = "y"}) { -! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] {uniq_name = "_QFsingle_privatization2Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[Y]] {uniq_name = "_QFsingle_privatization2Ey"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFsingle_privatization2Ex"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) +! CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[Y]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFsingle_privatization2Ey"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! CHECK: omp.parallel { ! CHECK: omp.single { ! CHECK: %[[X_PVT:.*]] = fir.alloca f32 {bindc_name = "x", pinned, uniq_name = "_QFsingle_privatization2Ex"} diff --git a/flang/test/Lower/OpenMP/target.f90 b/flang/test/Lower/OpenMP/target.f90 index 44f77b5c3360..e3b3799e5e7a 100644 --- a/flang/test/Lower/OpenMP/target.f90 +++ b/flang/test/Lower/OpenMP/target.f90 @@ -444,7 +444,7 @@ end subroutine omp_target_implicit_nested !CHECK: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "n"}) { subroutine omp_target_implicit_bounds(n) !CHECK: %[[VAL_COPY:.*]] = fir.alloca i32 - !CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFomp_target_implicit_boundsEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) + !CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFomp_target_implicit_boundsEn"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) !CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref !CHECK: fir.store %[[VAL_2]] to %[[VAL_COPY]] : !fir.ref !CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (i32) -> i64 @@ -455,7 +455,7 @@ subroutine omp_target_implicit_bounds(n) !CHECK: %[[VAL_8:.*]] = fir.alloca !fir.array, %[[VAL_7]] {bindc_name = "a", uniq_name = "_QFomp_target_implicit_boundsEa"} !CHECK: %[[VAL_9:.*]] = fir.shape %[[VAL_7]] : (index) -> !fir.shape<1> !CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %[[VAL_8]](%[[VAL_9]]) {uniq_name = "_QFomp_target_implicit_boundsEa"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) - !CHECK: %[[DIMS0:.*]]:3 = fir.box_dims %9#0, %c0{{.*}} : (!fir.box>, index) -> (index, index, index) + !CHECK: %[[DIMS0:.*]]:3 = fir.box_dims %{{[0-9]+}}#0, %c0{{.*}} : (!fir.box>, index) -> (index, index, index) !CHECK: %[[UB:.*]] = arith.subi %[[DIMS0]]#1, %c1{{.*}} : index integer :: n diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90 index 6c9bc75b81d7..197800486c39 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90 @@ -75,7 +75,7 @@ end program ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "r"}) attributes {{.*}} { ! CHECK: %[[VAL_1:.*]] = fir.address_of(@_QFFreduceEi) : !fir.ref ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFFreduceEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = {{.*}}, uniq_name = "_QFFreduceEr"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {fortran_attrs = {{.*}}, uniq_name = "_QFFreduceEr"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: omp.parallel { ! CHECK: %[[VAL_4:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_4]] {uniq_name = "_QFFreduceEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-iand-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-iand-byref.f90 index 40280c56dad6..df07a9065331 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-iand-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-iand-byref.f90 @@ -26,7 +26,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_iandEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_iandEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_iandEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_iandEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_iandEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : i32, !fir.ref ! CHECK: omp.parallel { diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-iand.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-iand.f90 index 986892d3584f..ae771c692b98 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-iand.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-iand.f90 @@ -20,7 +20,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_iandEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_iandEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_iandEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_iandEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_iandEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : i32, !fir.ref ! CHECK: omp.parallel { diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-ieor-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-ieor-byref.f90 index ee33ce2f348d..50cec61b602b 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-ieor-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-ieor-byref.f90 @@ -22,7 +22,7 @@ !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_ieorEx"} !CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X_REF]] {uniq_name = "_QFreduction_ieorEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[Y_BOX]] {uniq_name = "_QFreduction_ieorEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +!CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[Y_BOX]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_ieorEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) !CHECK: omp.parallel diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-ieor.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-ieor.f90 index b362731b3371..d50f6b854f48 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-ieor.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-ieor.f90 @@ -13,7 +13,7 @@ !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_ieorEx"} !CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X_REF]] {uniq_name = "_QFreduction_ieorEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[Y_BOX]] {uniq_name = "_QFreduction_ieorEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +!CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[Y_BOX]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_ieorEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) !CHECK: omp.parallel diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-ior-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-ior-byref.f90 index 0052773bb5ad..d847bba89782 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-ior-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-ior-byref.f90 @@ -24,7 +24,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_iorEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_iorEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_iorEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_iorEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_iorEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : i32, !fir.ref ! CHECK: omp.parallel diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-ior.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-ior.f90 index f32be43b9b71..182f1eaeeeb7 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-ior.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-ior.f90 @@ -20,7 +20,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_iorEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_iorEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_iorEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_iorEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_iorEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : i32, !fir.ref ! CHECK: omp.parallel diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-and-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-and-byref.f90 index dfc018ed7c5a..69789e4c751e 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-and-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-and-byref.f90 @@ -32,7 +32,7 @@ ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -82,7 +82,7 @@ end subroutine simple_reduction ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -129,7 +129,7 @@ end subroutine ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmultiple_reductionsEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFmultiple_reductionsEx"} ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.logical<4> {bindc_name = "y", uniq_name = "_QFmultiple_reductionsEy"} diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-and.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-and.f90 index c529bd4755b6..078a463919e9 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-and.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-and.f90 @@ -26,7 +26,7 @@ ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -76,7 +76,7 @@ end subroutine simple_reduction ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -123,7 +123,7 @@ end subroutine ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmultiple_reductionsEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFmultiple_reductionsEx"} ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.logical<4> {bindc_name = "y", uniq_name = "_QFmultiple_reductionsEy"} diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv-byref.f90 index a54795a4446f..54175994ecd8 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv-byref.f90 @@ -32,7 +32,7 @@ ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -81,7 +81,7 @@ end subroutine ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -128,7 +128,7 @@ end subroutine ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmultiple_reductionsEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFmultiple_reductionsEx"} ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.logical<4> {bindc_name = "y", uniq_name = "_QFmultiple_reductionsEy"} diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv.f90 index 1021b5926b91..8204e88815f3 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv.f90 @@ -26,7 +26,7 @@ ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -75,7 +75,7 @@ end subroutine ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -122,7 +122,7 @@ end subroutine ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmultiple_reductionsEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFmultiple_reductionsEx"} ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.logical<4> {bindc_name = "y", uniq_name = "_QFmultiple_reductionsEy"} diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv-byref.f90 index 854cb19ecd75..c0a82476c7b1 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv-byref.f90 @@ -32,7 +32,7 @@ ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -82,7 +82,7 @@ end subroutine ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -131,7 +131,7 @@ end subroutine ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmultiple_reductionsEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFmultiple_reductionsEx"} ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.logical<4> {bindc_name = "y", uniq_name = "_QFmultiple_reductionsEy"} diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv.f90 index f5c84aaaf485..957de9b6741a 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv.f90 @@ -26,7 +26,7 @@ ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -76,7 +76,7 @@ end subroutine ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -125,7 +125,7 @@ end subroutine ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmultiple_reductionsEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFmultiple_reductionsEx"} ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.logical<4> {bindc_name = "y", uniq_name = "_QFmultiple_reductionsEy"} diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-or-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-or-byref.f90 index e268c6ff6cf5..0af9e0d5c9fd 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-or-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-or-byref.f90 @@ -31,7 +31,7 @@ ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -80,7 +80,7 @@ end subroutine ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -127,7 +127,7 @@ end subroutine ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmultiple_reductionsEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFmultiple_reductionsEx"} ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.logical<4> {bindc_name = "y", uniq_name = "_QFmultiple_reductionsEy"} diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-or.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-or.f90 index 26dc0c327aad..d77566b109e5 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-or.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-or.f90 @@ -26,7 +26,7 @@ ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reductionEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -75,7 +75,7 @@ end subroutine ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_6:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_6]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFsimple_reduction_switch_orderEy"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_8:.*]] = arith.constant true ! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.assign %[[VAL_9]] to %[[VAL_4]]#0 : !fir.logical<4>, !fir.ref> @@ -122,7 +122,7 @@ end subroutine ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFmultiple_reductionsEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = arith.constant 100 : index ! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_4]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QFmultiple_reductionsEw"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFmultiple_reductionsEx"} ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.logical<4> {bindc_name = "y", uniq_name = "_QFmultiple_reductionsEy"} diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90 index 95bdc98f18c2..11d039f9226c 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90 @@ -37,7 +37,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_max_intEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_max_intEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_max_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_max_intEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_max_intEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : i32, !fir.ref ! CHECK: omp.parallel { @@ -68,7 +68,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_max_realEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFreduction_max_realEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_max_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_max_realEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_max_realEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0.000000e+00 : f32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : f32, !fir.ref ! CHECK: omp.parallel { diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir-byref.f90 index 352888bb94f5..a352cb195c25 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir-byref.f90 @@ -24,7 +24,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_max_intEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_max_intEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_max_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_max_intEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_max_intEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : i32, !fir.ref ! CHECK: omp.parallel { diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir.f90 index f4caea5a269a..71631fb14592 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir.f90 @@ -20,7 +20,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_max_intEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_max_intEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_max_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_max_intEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_max_intEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : i32, !fir.ref ! CHECK: omp.parallel { diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-max.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-max.f90 index ff005f32487e..d4e827f3b7e2 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-max.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-max.f90 @@ -31,7 +31,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_max_intEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_max_intEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_max_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_max_intEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_max_intEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : i32, !fir.ref ! CHECK: omp.parallel { @@ -62,7 +62,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_max_realEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFreduction_max_realEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_max_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_max_realEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_max_realEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0.000000e+00 : f32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : f32, !fir.ref ! CHECK: omp.parallel { diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90 index 9787512ab078..d168b2a89295 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90 @@ -37,7 +37,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_min_intEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_min_intEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_min_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_min_intEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_min_intEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : i32, !fir.ref ! CHECK: omp.parallel { @@ -68,7 +68,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_min_realEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFreduction_min_realEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_min_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_min_realEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_min_realEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0.000000e+00 : f32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : f32, !fir.ref ! CHECK: omp.parallel { diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-min.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-min.f90 index 801ef99480a2..80c056b5e8c5 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-min.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-min.f90 @@ -31,7 +31,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_min_intEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_min_intEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_min_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_min_intEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_min_intEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : i32, !fir.ref ! CHECK: omp.parallel { @@ -62,7 +62,7 @@ ! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = "_QFreduction_min_realEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_3:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFreduction_min_realEx"} ! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {uniq_name = "_QFreduction_min_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFreduction_min_realEy"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QFreduction_min_realEy"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: %[[VAL_6:.*]] = arith.constant 0.000000e+00 : f32 ! CHECK: hlfir.assign %[[VAL_6]] to %[[VAL_4]]#0 : f32, !fir.ref ! CHECK: omp.parallel { diff --git a/flang/test/Lower/allocatable-polymorphic.f90 b/flang/test/Lower/allocatable-polymorphic.f90 index 10d7d957a257..e96945ef89e5 100644 --- a/flang/test/Lower/allocatable-polymorphic.f90 +++ b/flang/test/Lower/allocatable-polymorphic.f90 @@ -520,8 +520,8 @@ contains ! CHECK-LABEL: func.func @_QMpolyPtest_allocatable_up_from_up_mold( ! CHECK-SAME: %[[A:.*]]: !fir.ref>> {fir.bindc_name = "a"}, %[[B:.*]]: !fir.ref>> {fir.bindc_name = "b"}) { -! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatable_up_from_up_moldEa"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) -! CHECK: %[[B_DECL:.*]]:2 = hlfir.declare %[[B]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatable_up_from_up_moldEb"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatable_up_from_up_moldEa"} : (!fir.ref>>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[B_DECL:.*]]:2 = hlfir.declare %[[B]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatable_up_from_up_moldEb"} : (!fir.ref>>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[LOAD_B:.*]] = fir.load %[[B_DECL]]#1 : !fir.ref>> ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 ! CHECK: %[[A_BOX_NONE:.*]] = fir.convert %[[A_DECL]]#1 : (!fir.ref>>) -> !fir.ref> @@ -539,7 +539,7 @@ contains ! CHECK-LABEL: func.func @_QMpolyPtest_allocatable_up_from_mold_rank( ! CHECK-SAME: %[[A:.*]]: !fir.ref>>> {fir.bindc_name = "a"}) { ! CHECK: %[[VALUE_10:.*]] = fir.alloca i32 -! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatable_up_from_mold_rankEa"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatable_up_from_mold_rankEa"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[C10:.*]] = arith.constant 10 : i32 ! CHECK: fir.store %[[C10]] to %[[VALUE_10]] : !fir.ref ! CHECK: %[[EMBOX_10:.*]] = fir.embox %[[VALUE_10]] : (!fir.ref) -> !fir.box diff --git a/flang/test/Lower/array-expression.f90 b/flang/test/Lower/array-expression.f90 index 75789cd6952a..bdfbe6dd3509 100644 --- a/flang/test/Lower/array-expression.f90 +++ b/flang/test/Lower/array-expression.f90 @@ -991,7 +991,7 @@ end subroutine test19f ! CHECK: %[[VAL_24:.*]] = fir.array_load %[[VAL_5]](%[[VAL_22]]) {{\[}}%[[VAL_23]]] : (!fir.ref>>, !fir.shape<1>, !fir.slice<1>) -> !fir.array<140x!fir.char<2,13>> ! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_2]] : !fir.ref ! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i32) -> i64 -! CHECK: %[[char_temp:.*]] = fir.alloca !fir.char<4,?>(%16 : i64) {bindc_name = ".chrtmp"} +! CHECK: %[[char_temp:.*]] = fir.alloca !fir.char<4,?>(%{{[0-9]+}} : i64) {bindc_name = ".chrtmp"} ! CHECK: %[[VAL_27:.*]] = arith.constant 1 : index ! CHECK: %[[VAL_28:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_29:.*]] = arith.subi %[[VAL_13]], %[[VAL_27]] : index diff --git a/flang/test/Lower/character-substrings.f90 b/flang/test/Lower/character-substrings.f90 index 8e1a91a247d4..874f2944cff1 100644 --- a/flang/test/Lower/character-substrings.f90 +++ b/flang/test/Lower/character-substrings.f90 @@ -231,7 +231,7 @@ end subroutine array_substring_assignment ! CHECK: %[[c0:.*]] = arith.constant 0 : index ! CHECK: %[[sub:.*]] = arith.subi %[[VAL_1]], %[[VAL_4]] : index ! CHECK: %[[add:.*]] = arith.addi %[[sub]], %[[VAL_4]] : index -! CHECK: %[[div:.*]] = arith.divsi %4, %[[VAL_4]] : index +! CHECK: %[[div:.*]] = arith.divsi %{{[0-9]+}}, %[[VAL_4]] : index ! CHECK: %[[cmp:.*]] = arith.cmpi sgt, %[[div]], %[[c0]] : index ! CHECK: %[[select:.*]] = arith.select %[[cmp]], %[[div]], %[[c0]] : index ! CHECK: %[[VAL_6:.*]] = fir.array_load %[[VAL_0]](%[[VAL_3]]) {{\[}}%[[VAL_5]]] : (!fir.ref}>>>, !fir.shape<1>, !fir.slice<1>) -> !fir.array<8x!fir.char<1,7>> @@ -323,7 +323,7 @@ end subroutine array_substring_assignment2 ! CHECK: %[[c0:.*]] = arith.constant 0 : index ! CHECK: %[[sub:.*]] = arith.subi %[[VAL_2]], %[[VAL_6]] : index ! CHECK: %[[add:.*]] = arith.addi %[[sub]], %[[VAL_6]] : index -! CHECK: %[[div:.*]] = arith.divsi %4, %[[VAL_6]] : index +! CHECK: %[[div:.*]] = arith.divsi %[[add]], %[[VAL_6]] : index ! CHECK: %[[cmp:.*]] = arith.cmpi sgt, %[[div]], %[[c0]] : index ! CHECK: %[[select:.*]] = arith.select %[[cmp]], %[[div]], %[[c0]] : index ! CHECK: %[[VAL_8:.*]] = fir.array_load %[[VAL_0]](%[[VAL_5]]) {{\[}}%[[VAL_7]]] : (!fir.ref}>>>, !fir.shape<1>, !fir.slice<1>) -> !fir.array<8x!fir.char<1,7>> diff --git a/flang/test/Lower/charconvert.f90 b/flang/test/Lower/charconvert.f90 index c8ec254b6a54..e3f7f66b8476 100644 --- a/flang/test/Lower/charconvert.f90 +++ b/flang/test/Lower/charconvert.f90 @@ -14,17 +14,17 @@ end subroutine ! CHECK: func.func @_QPtest_c1_to_c4(%[[ARG0:.*]]: !fir.boxchar<4> {fir.bindc_name = "c4"}, %[[ARG1:.*]]: !fir.boxchar<1> {fir.bindc_name = "c1"}) { ! CHECK: %[[VAL_0:.*]]:2 = fir.unboxchar %[[ARG1]] : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 {uniq_name = "_QFtest_c1_to_c4Ec1"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_c1_to_c4Ec1"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_2:.*]]:2 = fir.unboxchar %[[ARG0]] : (!fir.boxchar<4>) -> (!fir.ref>, index) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 {uniq_name = "_QFtest_c1_to_c4Ec4"} : (!fir.ref>, index) -> (!fir.boxchar<4>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_c1_to_c4Ec4"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<4>, !fir.ref>) ! CHECK: %[[VAL_4:.*]] = fir.alloca !fir.char<4,?>(%[[VAL_0]]#1 : index) ! CHECK: fir.char_convert %[[VAL_1]]#1 for %[[VAL_0]]#1 to %[[VAL_4:.*]] : !fir.ref>, index, !fir.ref> ! CHECK: func.func @_QPtest_c4_to_c1(%[[ARG0:.*]]: !fir.boxchar<4> {fir.bindc_name = "c4"}, %[[ARG1:.*]]: !fir.boxchar<1> {fir.bindc_name = "c1"}) { ! CHECK: %[[VAL_0:.*]]:2 = fir.unboxchar %[[ARG1]] : (!fir.boxchar<1>) -> (!fir.ref>, index) -! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 {uniq_name = "_QFtest_c4_to_c1Ec1"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]]#0 typeparams %[[VAL_0]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_c4_to_c1Ec1"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: %[[VAL_2:.*]]:2 = fir.unboxchar %[[ARG0]] : (!fir.boxchar<4>) -> (!fir.ref>, index) -! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 {uniq_name = "_QFtest_c4_to_c1Ec4"} : (!fir.ref>, index) -> (!fir.boxchar<4>, !fir.ref>) +! CHECK: %[[VAL_3:.*]]:2 = hlfir.declare %[[VAL_2]]#0 typeparams %[[VAL_2]]#1 dummy_scope %{{[0-9]+}} {uniq_name = "_QFtest_c4_to_c1Ec4"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<4>, !fir.ref>) ! CHECK: %[[C4:.*]] = arith.constant 4 : index ! CHECK: %[[VAL_4:.*]] = arith.muli %[[VAL_2]]#1, %[[C4]] : index ! CHECK: %[[VAL_5:.*]] = fir.alloca !fir.char<1,?>(%[[VAL_4]] : index) diff --git a/flang/test/Lower/dispatch.f90 b/flang/test/Lower/dispatch.f90 index 60364076e633..02338065548d 100644 --- a/flang/test/Lower/dispatch.f90 +++ b/flang/test/Lower/dispatch.f90 @@ -151,7 +151,7 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch( ! CHECK-SAME: %[[P:.*]]: !fir.class> {fir.bindc_name = "p"}) { -! CHECK: %[[P_DECL:.*]]:2 = hlfir.declare %[[P]] {uniq_name = "_QMcall_dispatchFcheck_dispatchEp"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[P_DECL:.*]]:2 = hlfir.declare %[[P]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMcall_dispatchFcheck_dispatchEp"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) ! CHECK: fir.dispatch "tbp_nopass"(%[[P_DECL]]#1 : !fir.class>){{$}} ! CHECK: fir.dispatch "tbp_pass"(%[[P_DECL]]#0 : !fir.class>) (%[[P_DECL]]#0 : !fir.class>) {pass_arg_pos = 0 : i32} ! CHECK: fir.dispatch "tbp_pass_arg0"(%[[P_DECL]]#0 : !fir.class>) (%[[P_DECL]]#0 : !fir.class>) {pass_arg_pos = 0 : i32} @@ -176,8 +176,8 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_deferred( ! CHECK-SAME: %[[ARG0:.*]]: !fir.class> {fir.bindc_name = "a"}, ! CHECK-SAME: %[[ARG1:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_deferredEa"} : (!fir.class>) -> (!fir.class>, !fir.class>) -! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_deferredEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMcall_dispatchFcheck_dispatch_deferredEa"} : (!fir.class>, !fir.dscope) -> (!fir.class>, !fir.class>) +! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMcall_dispatchFcheck_dispatch_deferredEx"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) ! CHECK: fir.dispatch "nopassd"(%[[ARG0_DECL]]#1 : !fir.class>) (%[[ARG1_DECL]]#0 : !fir.box>) subroutine check_dispatch_scalar_allocatable(p) @@ -187,7 +187,7 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_scalar_allocatable( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>> {fir.bindc_name = "p"}) { -! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %arg0 {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_scalar_allocatableEp"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_scalar_allocatableEp"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[LOAD:.*]] = fir.load %[[ARG0_DECL]]#0 : !fir.ref>>> ! CHECK: %[[REBOX:.*]] = fir.rebox %[[LOAD]] : (!fir.class>>) -> !fir.class> ! CHECK: fir.dispatch "tbp_pass"(%[[REBOX]] : !fir.class>) (%[[REBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} @@ -199,7 +199,7 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_scalar_pointer( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>> {fir.bindc_name = "p"}) { -! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_scalar_pointerEp"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_scalar_pointerEp"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[LOAD:.*]] = fir.load %[[ARG0_DECL]]#0 : !fir.ref>>> ! CHECK: %[[REBOX:.*]] = fir.rebox %[[LOAD]] : (!fir.class>>) -> !fir.class> ! CHECK: fir.dispatch "tbp_pass"(%[[REBOX]] : !fir.class>) (%[[REBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} @@ -220,8 +220,8 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_static_array( ! CHECK-SAME: %[[ARG0:.*]]: !fir.class>> {fir.bindc_name = "p"}, ! CHECK-SAME: %[[ARG1:.*]]: !fir.ref>> {fir.bindc_name = "t"}) { -! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_static_arrayEp"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) -! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]](%{{.*}}) {uniq_name = "_QMcall_dispatchFcheck_dispatch_static_arrayEt"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMcall_dispatchFcheck_dispatch_static_arrayEp"} : (!fir.class>>, !fir.dscope) -> (!fir.class>>, !fir.class>>) +! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]](%{{.*}}) dummy_scope %{{[0-9]+}} {uniq_name = "_QMcall_dispatchFcheck_dispatch_static_arrayEt"} : (!fir.ref>>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>>, !fir.ref>>) ! CHECK: fir.do_loop {{.*}} { ! CHECK: %[[DESIGNATE:.*]] = hlfir.designate %[[ARG0_DECL]]#0 (%{{.*}}) : (!fir.class>>, i64) -> !fir.class> ! CHECK: fir.dispatch "tbp_pass"(%[[DESIGNATE]] : !fir.class>) (%[[DESIGNATE]] : !fir.class>) {pass_arg_pos = 0 : i32} @@ -248,8 +248,8 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_dynamic_array( ! CHECK-SAME: %[[ARG0:.*]]: !fir.class>> {fir.bindc_name = "p"}, ! CHECK-SAME: %[[ARG1:.*]]: !fir.box>> {fir.bindc_name = "t"}) { -! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_dynamic_arrayEp"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) -! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_dynamic_arrayEt"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMcall_dispatchFcheck_dispatch_dynamic_arrayEp"} : (!fir.class>>, !fir.dscope) -> (!fir.class>>, !fir.class>>) +! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMcall_dispatchFcheck_dispatch_dynamic_arrayEt"} : (!fir.box>>, !fir.dscope) -> (!fir.box>>, !fir.box>>) ! CHECK: %{{.*}} = fir.do_loop {{.*}} { ! CHECK: %[[DESIGNATE:.*]] = hlfir.designate %[[ARG0_DECL]]#0 (%{{.*}}) : (!fir.class>>, i64) -> !fir.class> ! CHECK: fir.dispatch "tbp_pass"(%[[DESIGNATE]] : !fir.class>) (%[[DESIGNATE]] : !fir.class>) {pass_arg_pos = 0 : i32} @@ -276,8 +276,8 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_allocatable_array( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>>> {fir.bindc_name = "p"}, ! CHECK-SAME: %[[ARG1:.*]]: !fir.ref>>>> {fir.bindc_name = "t"}) { -! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_allocatable_arrayEp"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) -! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_allocatable_arrayEt"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_allocatable_arrayEp"} : (!fir.ref>>>>, !fir.dscope) -> (!fir.ref>>>>, !fir.ref>>>>) +! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_allocatable_arrayEt"} : (!fir.ref>>>>, !fir.dscope) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK: %{{.*}} = fir.do_loop {{.*}} { ! CHECK: %[[LOAD_ARG0:.*]] = fir.load %[[ARG0_DECL]]#0 : !fir.ref>>>> ! CHECK: %[[DESIGNATE:.*]] = hlfir.designate %[[LOAD_ARG0]] (%{{.*}}) : (!fir.class>>>, i64) -> !fir.class> @@ -306,8 +306,8 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_pointer_array( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>>> {fir.bindc_name = "p"}, ! CHECK-SAME: %[[ARG1:.*]]: !fir.ref>>>> {fir.bindc_name = "t"}) { -! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_pointer_arrayEp"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) -! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_pointer_arrayEt"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_pointer_arrayEp"} : (!fir.ref>>>>, !fir.dscope) -> (!fir.ref>>>>, !fir.ref>>>>) +! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_pointer_arrayEt"} : (!fir.ref>>>>, !fir.dscope) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK: %{{.*}} = fir.do_loop {{.*}} { ! CHECK: %[[LOAD_ARG0:.*]] = fir.load %[[ARG0_DECL]]#0 : !fir.ref>>>> @@ -334,8 +334,8 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_dynamic_array_copy( ! CHECK-SAME: %[[ARG0:.*]]: !fir.class>> {fir.bindc_name = "p"}, ! CHECK-SAME: %[[ARG1:.*]]: !fir.class>> {fir.bindc_name = "o"}) { -! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_dynamic_array_copyEo"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) -! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_dynamic_array_copyEp"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) +! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMcall_dispatchFcheck_dispatch_dynamic_array_copyEo"} : (!fir.class>>, !fir.dscope) -> (!fir.class>>, !fir.class>>) +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMcall_dispatchFcheck_dispatch_dynamic_array_copyEp"} : (!fir.class>>, !fir.dscope) -> (!fir.class>>, !fir.class>>) ! CHECK: %{{.*}} = fir.do_loop {{.*}} { ! CHECK: %[[DESIGNATE0:.*]] = hlfir.designate %[[ARG0_DECL]]#0 (%{{.*}}) : (!fir.class>>, i64) -> !fir.class> diff --git a/flang/test/Lower/do_loop.f90 b/flang/test/Lower/do_loop.f90 index 4ace17342ade..d9c83658ee25 100644 --- a/flang/test/Lower/do_loop.f90 +++ b/flang/test/Lower/do_loop.f90 @@ -132,6 +132,7 @@ end subroutine ! CHECK-SAME: (%[[S_REF:.*]]: !fir.ref {fir.bindc_name = "s"}, %[[E_REF:.*]]: !fir.ref {fir.bindc_name = "e"}, %[[ST_REF:.*]]: !fir.ref {fir.bindc_name = "st"}) { subroutine loop_with_variable_step(s,e,st) integer :: s, e, st + ! CHECK: %[[I_REF:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFloop_with_variable_stepEi"} ! CHECK: %[[S:.*]] = fir.load %[[S_REF]] : !fir.ref ! CHECK: %[[S_CVT:.*]] = fir.convert %[[S]] : (i32) -> index ! CHECK: %[[E:.*]] = fir.load %[[E_REF]] : !fir.ref diff --git a/flang/test/Lower/pointer-references.f90 b/flang/test/Lower/pointer-references.f90 index ace64f9ec7ef..02394e7ec76b 100644 --- a/flang/test/Lower/pointer-references.f90 +++ b/flang/test/Lower/pointer-references.f90 @@ -34,7 +34,7 @@ subroutine char_ptr(p) ! CHECK: %[[count:.*]] = arith.muli %[[one]], %[[size]] : i64 ! CHECK: %[[dst:.*]] = fir.convert %[[addr]] : (!fir.ptr>) -> !fir.ref ! CHECK: %[[src:.*]] = fir.convert %[[str]] : (!fir.ref>) -> !fir.ref - ! CHECK: fir.call @llvm.memmove.p0.p0.i64(%[[dst]], %[[src]], %5, %false) {{.*}}: (!fir.ref, !fir.ref, i64, i1) -> () + ! CHECK: fir.call @llvm.memmove.p0.p0.i64(%[[dst]], %[[src]], %{{[0-9]+}}, %false) {{.*}}: (!fir.ref, !fir.ref, i64, i1) -> () p = "hello world!" ! CHECK: %[[boxload2:.*]] = fir.load %[[arg0]] diff --git a/flang/test/Lower/polymorphic.f90 b/flang/test/Lower/polymorphic.f90 index 70c1f768e389..14ec8a06a964 100644 --- a/flang/test/Lower/polymorphic.f90 +++ b/flang/test/Lower/polymorphic.f90 @@ -298,7 +298,7 @@ module polymorphic_test ! CHECK: %[[ZERO:.*]] = fir.zero_bits !fir.ptr> ! CHECK: fir.store %[[ZERO]] to %[[PTR]] : !fir.ref>> ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[ARG0]] : (!fir.class>) -> !fir.ref> -! CHECK: %[[CONVERT:.*]] = fir.convert %3 : (!fir.ref>) -> !fir.ptr> +! CHECK: %[[CONVERT:.*]] = fir.convert %{{[0-9]+}} : (!fir.ref>) -> !fir.ptr> ! CHECK: fir.store %[[CONVERT]] to %[[PTR]] : !fir.ref>> subroutine nullify_pointer_array(a) diff --git a/flang/test/Lower/select-type.f90 b/flang/test/Lower/select-type.f90 index 3243a813e9d5..e4ff2fef0efd 100644 --- a/flang/test/Lower/select-type.f90 +++ b/flang/test/Lower/select-type.f90 @@ -498,7 +498,7 @@ contains ! CHECK: fir.array_merge_store %[[ARRAY_LOAD]], %[[LOOP_RES]] to %[[BOX]] : !fir.array, !fir.array, !fir.box> ! CHECK: cf.br ^{{.*}} ! CHECK: ^bb{{.*}}: -! CHECK: %[[BOX:.*]] = fir.convert %0 : (!fir.class>) -> !fir.box>> +! CHECK: %[[BOX:.*]] = fir.convert %{{[0-9]+}} : (!fir.class>) -> !fir.box>> ! CHECK: cf.br ^bb{{.*}} ! CHECK: ^bb{{.*}}: ! CHECK: %[[EXACT_BOX:.*]] = fir.convert %[[SELECTOR]] : (!fir.class>) -> !fir.box>> diff --git a/flang/test/Lower/structure-constructors-alloc-comp.f90 b/flang/test/Lower/structure-constructors-alloc-comp.f90 index 5b56463303ba..5b1bca317c94 100644 --- a/flang/test/Lower/structure-constructors-alloc-comp.f90 +++ b/flang/test/Lower/structure-constructors-alloc-comp.f90 @@ -24,7 +24,7 @@ contains ! HLFIR-LABEL: func.func @_QMm_struct_ctorPtest_alloc1( ! HLFIR-SAME: %[[ARG_0:.*]]: !fir.ref {fir.bindc_name = "y"}) { ! HLFIR: %[[VAL_0:.*]] = fir.alloca !fir.type<_QMm_struct_ctorTt_alloc{x:f32,a:!fir.box>>}> -! HLFIR: %[[VAL_12:.*]]:2 = hlfir.declare %[[ARG_0]] {uniq_name = "_QMm_struct_ctorFtest_alloc1Ey"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! HLFIR: %[[VAL_12:.*]]:2 = hlfir.declare %[[ARG_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMm_struct_ctorFtest_alloc1Ey"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! HLFIR: %[[VAL_13:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "ctor.temp"} : (!fir.ref>>}>>) -> (!fir.ref>>}>>, !fir.ref>>}>>) ! HLFIR: %[[VAL_14:.*]] = fir.embox %[[VAL_13]]#0 : (!fir.ref>>}>>) -> !fir.box>>}>> ! HLFIR: %[[VAL_15:.*]] = fir.address_of(@_QQ{{.*}}) : !fir.ref> @@ -49,8 +49,8 @@ contains ! HLFIR: %[[VAL_0:.*]] = fir.alloca !fir.type<_QMm_struct_ctorTt_alloc{x:f32,a:!fir.box>>}> ! HLFIR: %[[CONS_6:.*]] = arith.constant 5 : index ! HLFIR: %[[VAL_12:.*]] = fir.shape %[[CONS_6]] : (index) -> !fir.shape<1> -! HLFIR: %[[VAL_13:.*]]:2 = hlfir.declare %[[ARG_1]](%[[VAL_12]]) {uniq_name = "_QMm_struct_ctorFtest_alloc2Eb"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) -! HLFIR: %[[VAL_14:.*]]:2 = hlfir.declare %[[ARG_0]] {uniq_name = "_QMm_struct_ctorFtest_alloc2Ey"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! HLFIR: %[[VAL_13:.*]]:2 = hlfir.declare %[[ARG_1]](%[[VAL_12]]) dummy_scope %{{[0-9]+}} {uniq_name = "_QMm_struct_ctorFtest_alloc2Eb"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) +! HLFIR: %[[VAL_14:.*]]:2 = hlfir.declare %[[ARG_0]] dummy_scope %{{[0-9]+}} {uniq_name = "_QMm_struct_ctorFtest_alloc2Ey"} : (!fir.ref, !fir.dscope) -> (!fir.ref, !fir.ref) ! HLFIR: %[[VAL_15:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "ctor.temp"} : (!fir.ref>>}>>) -> (!fir.ref>>}>>, !fir.ref>>}>>) ! HLFIR: %[[VAL_16:.*]] = fir.embox %[[VAL_15]]#0 : (!fir.ref>>}>>) -> !fir.box>>}>> ! HLFIR: %[[VAL_17:.*]] = fir.address_of(@_QQ{{.*}}) : !fir.ref> -- GitLab From 96568f3539d8a72432a03257a7a8ed2f36014b59 Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Wed, 8 May 2024 16:49:08 -0700 Subject: [PATCH 089/328] [llvm][ctx_profile] Add instrumentation lowering (#90821) This adds the instrumentation lowering pass. (Tracking Issue: #89287, RFC referenced there) --- llvm/docs/LangRef.rst | 48 ++- .../Instrumentation/PGOCtxProfLowering.h | 5 +- llvm/lib/Passes/PassBuilder.cpp | 1 + llvm/lib/Passes/PassBuilderPipelines.cpp | 5 + llvm/lib/Passes/PassRegistry.def | 1 + .../Instrumentation/PGOCtxProfLowering.cpp | 326 ++++++++++++++++++ .../ctx-instrumentation-invalid-roots.ll | 17 + .../PGOProfile/ctx-instrumentation.ll | 229 ++++++++++++ 8 files changed, 626 insertions(+), 6 deletions(-) create mode 100644 llvm/test/Transforms/PGOProfile/ctx-instrumentation-invalid-roots.ll diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index cc7094116b8b..6f5a4644ffc2 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -14111,6 +14111,25 @@ structures and the code to increment the appropriate value, in a format that can be written out by a compiler runtime and consumed via the ``llvm-profdata`` tool. +.. FIXME: write complete doc on contextual instrumentation and link from here +.. and from llvm.instrprof.callsite. + +The intrinsic is lowered differently for contextual profiling by the +``-ctx-instr-lower`` pass. Here: + +* the entry basic block increment counter is lowered as a call to compiler-rt, + to either ``__llvm_ctx_profile_start_context`` or + ``__llvm_ctx_profile_get_context``. Either returns a pointer to a context object + which contains a buffer into which counter increments can happen. Note that the + pointer value returned by compiler-rt may have its LSB set - counter increments + happen offset from the address with the LSB cleared. + +* all the other lowerings of ``llvm.instrprof.increment[.step]`` happen within + that context. + +* the context is assumed to be a local value to the function, and no concurrency + concerns need to be handled by LLVM. + '``llvm.instrprof.increment.step``' Intrinsic ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -14156,10 +14175,10 @@ Syntax: Overview: """"""""" -.. FIXME: detail when it's emitted once the support is added - The '``llvm.instrprof.callsite``' intrinsic should be emitted before a callsite -that's not to a "fake" callee (like another intrinsic or asm). +that's not to a "fake" callee (like another intrinsic or asm). It is used by +contextual profiling and has side-effects. Its lowering happens in IR, and +target-specific backends should never encounter it. Arguments: """""""""" @@ -14172,9 +14191,28 @@ The last argument is the called value of the callsite this intrinsic precedes. Semantics: """""""""" -.. FIXME: detail how when the lowering pass is added. -This is lowered by contextual profiling. +This is lowered by contextual profiling. In contextual profiling, functions get, +from compiler-rt, a pointer to a context object. The context object consists of +a buffer LLVM can use to perform counter increments (i.e. the lowering of +``llvm.instrprof.increment[.step]``. The address range following the counter +buffer, ```` x ``sizeof(ptr)`` - sized, is expected to contain +pointers to contexts of functions called from this function ("subcontexts"). +LLVM does not dereference into that memory region, just calculates GEPs. + +The lowering of ``llvm.instrprof.callsite`` consists of: + +* write to ``__llvm_ctx_profile_expected_callee`` the ```` value; + +* write to ``__llvm_ctx_profile_callsite`` the address into this function's + context of the ```` position into the subcontexts region. + + +``__llvm_ctx_profile_{expected_callee|callsite}`` are initialized by compiler-rt +and are TLS. They are both vectors of pointers of size 2. The index into each is +determined when the current function obtains the pointer to its context from +compiler-rt. The pointer's LSB gives the index. + '``llvm.instrprof.timestamp``' Intrinsic ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/llvm/include/llvm/Transforms/Instrumentation/PGOCtxProfLowering.h b/llvm/include/llvm/Transforms/Instrumentation/PGOCtxProfLowering.h index 38afa0c6fd32..5256aff56205 100644 --- a/llvm/include/llvm/Transforms/Instrumentation/PGOCtxProfLowering.h +++ b/llvm/include/llvm/Transforms/Instrumentation/PGOCtxProfLowering.h @@ -12,13 +12,16 @@ #ifndef LLVM_TRANSFORMS_INSTRUMENTATION_PGOCTXPROFLOWERING_H #define LLVM_TRANSFORMS_INSTRUMENTATION_PGOCTXPROFLOWERING_H +#include "llvm/IR/PassManager.h" namespace llvm { class Type; -class PGOCtxProfLoweringPass { +class PGOCtxProfLoweringPass : public PassInfoMixin { public: explicit PGOCtxProfLoweringPass() = default; static bool isContextualIRPGOEnabled(); + + PreservedAnalyses run(Module &M, ModuleAnalysisManager &MAM); }; } // namespace llvm #endif diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 51ddb73943b1..e4131706aba0 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -177,6 +177,7 @@ #include "llvm/Transforms/Instrumentation/LowerAllowCheckPass.h" #include "llvm/Transforms/Instrumentation/MemProfiler.h" #include "llvm/Transforms/Instrumentation/MemorySanitizer.h" +#include "llvm/Transforms/Instrumentation/PGOCtxProfLowering.h" #include "llvm/Transforms/Instrumentation/PGOForceFunctionAttrs.h" #include "llvm/Transforms/Instrumentation/PGOInstrumentation.h" #include "llvm/Transforms/Instrumentation/PoisonChecking.h" diff --git a/llvm/lib/Passes/PassBuilderPipelines.cpp b/llvm/lib/Passes/PassBuilderPipelines.cpp index 100889c0845b..1d7f0510450c 100644 --- a/llvm/lib/Passes/PassBuilderPipelines.cpp +++ b/llvm/lib/Passes/PassBuilderPipelines.cpp @@ -74,6 +74,7 @@ #include "llvm/Transforms/Instrumentation/InstrOrderFile.h" #include "llvm/Transforms/Instrumentation/InstrProfiling.h" #include "llvm/Transforms/Instrumentation/MemProfiler.h" +#include "llvm/Transforms/Instrumentation/PGOCtxProfLowering.h" #include "llvm/Transforms/Instrumentation/PGOForceFunctionAttrs.h" #include "llvm/Transforms/Instrumentation/PGOInstrumentation.h" #include "llvm/Transforms/Scalar/ADCE.h" @@ -834,6 +835,10 @@ void PassBuilder::addPGOInstrPasses(ModulePassManager &MPM, PTO.EagerlyInvalidateAnalyses)); } + if (PGOCtxProfLoweringPass::isContextualIRPGOEnabled()) { + MPM.addPass(PGOCtxProfLoweringPass()); + return; + } // Add the profile lowering pass. InstrProfOptions Options; if (!ProfileFile.empty()) diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 6864f307e56c..e5ce6cb7da64 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -77,6 +77,7 @@ MODULE_PASS("inliner-wrapper-no-mandatory-first", MODULE_PASS("insert-gcov-profiling", GCOVProfilerPass()) MODULE_PASS("instrorderfile", InstrOrderFilePass()) MODULE_PASS("instrprof", InstrProfilingLoweringPass()) +MODULE_PASS("ctx-instr-lower", PGOCtxProfLoweringPass()) MODULE_PASS("internalize", InternalizePass()) MODULE_PASS("invalidate", InvalidateAllAnalysesPass()) MODULE_PASS("iroutliner", IROutlinerPass()) diff --git a/llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp b/llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp index 9d6dd5ccb38b..76afa2f22461 100644 --- a/llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp +++ b/llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp @@ -8,10 +8,20 @@ // #include "llvm/Transforms/Instrumentation/PGOCtxProfLowering.h" +#include "llvm/Analysis/OptimizationRemarkEmitter.h" +#include "llvm/IR/Analysis.h" +#include "llvm/IR/DiagnosticInfo.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/Instructions.h" +#include "llvm/IR/IntrinsicInst.h" +#include "llvm/IR/PassManager.h" #include "llvm/Support/CommandLine.h" +#include using namespace llvm; +#define DEBUG_TYPE "ctx-instr-lower" + static cl::list ContextRoots( "profile-context-root", cl::Hidden, cl::desc( @@ -22,3 +32,319 @@ static cl::list ContextRoots( bool PGOCtxProfLoweringPass::isContextualIRPGOEnabled() { return !ContextRoots.empty(); } + +// the names of symbols we expect in compiler-rt. Using a namespace for +// readability. +namespace CompilerRtAPINames { +static auto StartCtx = "__llvm_ctx_profile_start_context"; +static auto ReleaseCtx = "__llvm_ctx_profile_release_context"; +static auto GetCtx = "__llvm_ctx_profile_get_context"; +static auto ExpectedCalleeTLS = "__llvm_ctx_profile_expected_callee"; +static auto CallsiteTLS = "__llvm_ctx_profile_callsite"; +} // namespace CompilerRtAPINames + +namespace { +// The lowering logic and state. +class CtxInstrumentationLowerer final { + Module &M; + ModuleAnalysisManager &MAM; + Type *ContextNodeTy = nullptr; + Type *ContextRootTy = nullptr; + + DenseMap ContextRootMap; + Function *StartCtx = nullptr; + Function *GetCtx = nullptr; + Function *ReleaseCtx = nullptr; + GlobalVariable *ExpectedCalleeTLS = nullptr; + GlobalVariable *CallsiteInfoTLS = nullptr; + +public: + CtxInstrumentationLowerer(Module &M, ModuleAnalysisManager &MAM); + // return true if lowering happened (i.e. a change was made) + bool lowerFunction(Function &F); +}; + +// llvm.instrprof.increment[.step] captures the total number of counters as one +// of its parameters, and llvm.instrprof.callsite captures the total number of +// callsites. Those values are the same for instances of those intrinsics in +// this function. Find the first instance of each and return them. +std::pair getNrCountersAndCallsites(const Function &F) { + uint32_t NrCounters = 0; + uint32_t NrCallsites = 0; + for (const auto &BB : F) { + for (const auto &I : BB) { + if (const auto *Incr = dyn_cast(&I)) { + uint32_t V = + static_cast(Incr->getNumCounters()->getZExtValue()); + assert((!NrCounters || V == NrCounters) && + "expected all llvm.instrprof.increment[.step] intrinsics to " + "have the same total nr of counters parameter"); + NrCounters = V; + } else if (const auto *CSIntr = dyn_cast(&I)) { + uint32_t V = + static_cast(CSIntr->getNumCounters()->getZExtValue()); + assert((!NrCallsites || V == NrCallsites) && + "expected all llvm.instrprof.callsite intrinsics to have the " + "same total nr of callsites parameter"); + NrCallsites = V; + } +#if NDEBUG + if (NrCounters && NrCallsites) + return std::make_pair(NrCounters, NrCallsites); +#endif + } + } + return {NrCounters, NrCallsites}; +} +} // namespace + +// set up tie-in with compiler-rt. +// NOTE!!! +// These have to match compiler-rt/lib/ctx_profile/CtxInstrProfiling.h +CtxInstrumentationLowerer::CtxInstrumentationLowerer(Module &M, + ModuleAnalysisManager &MAM) + : M(M), MAM(MAM) { + auto *PointerTy = PointerType::get(M.getContext(), 0); + auto *SanitizerMutexType = Type::getInt8Ty(M.getContext()); + auto *I32Ty = Type::getInt32Ty(M.getContext()); + auto *I64Ty = Type::getInt64Ty(M.getContext()); + + // The ContextRoot type + ContextRootTy = + StructType::get(M.getContext(), { + PointerTy, /*FirstNode*/ + PointerTy, /*FirstMemBlock*/ + PointerTy, /*CurrentMem*/ + SanitizerMutexType, /*Taken*/ + }); + // The Context header. + ContextNodeTy = StructType::get(M.getContext(), { + I64Ty, /*Guid*/ + PointerTy, /*Next*/ + I32Ty, /*NrCounters*/ + I32Ty, /*NrCallsites*/ + }); + + // Define a global for each entrypoint. We'll reuse the entrypoint's name as + // prefix. We assume the entrypoint names to be unique. + for (const auto &Fname : ContextRoots) { + if (const auto *F = M.getFunction(Fname)) { + if (F->isDeclaration()) + continue; + auto *G = M.getOrInsertGlobal(Fname + "_ctx_root", ContextRootTy); + cast(G)->setInitializer( + Constant::getNullValue(ContextRootTy)); + ContextRootMap.insert(std::make_pair(F, G)); + for (const auto &BB : *F) + for (const auto &I : BB) + if (const auto *CB = dyn_cast(&I)) + if (CB->isMustTailCall()) { + M.getContext().emitError( + "The function " + Fname + + " was indicated as a context root, but it features musttail " + "calls, which is not supported."); + } + } + } + + // Declare the functions we will call. + StartCtx = cast( + M.getOrInsertFunction( + CompilerRtAPINames::StartCtx, + FunctionType::get(ContextNodeTy->getPointerTo(), + {ContextRootTy->getPointerTo(), /*ContextRoot*/ + I64Ty, /*Guid*/ I32Ty, + /*NrCounters*/ I32Ty /*NrCallsites*/}, + false)) + .getCallee()); + GetCtx = cast( + M.getOrInsertFunction(CompilerRtAPINames::GetCtx, + FunctionType::get(ContextNodeTy->getPointerTo(), + {PointerTy, /*Callee*/ + I64Ty, /*Guid*/ + I32Ty, /*NrCounters*/ + I32Ty}, /*NrCallsites*/ + false)) + .getCallee()); + ReleaseCtx = cast( + M.getOrInsertFunction( + CompilerRtAPINames::ReleaseCtx, + FunctionType::get(Type::getVoidTy(M.getContext()), + { + ContextRootTy->getPointerTo(), /*ContextRoot*/ + }, + false)) + .getCallee()); + + // Declare the TLSes we will need to use. + CallsiteInfoTLS = + new GlobalVariable(M, PointerTy, false, GlobalValue::ExternalLinkage, + nullptr, CompilerRtAPINames::CallsiteTLS); + CallsiteInfoTLS->setThreadLocal(true); + CallsiteInfoTLS->setVisibility(llvm::GlobalValue::HiddenVisibility); + ExpectedCalleeTLS = + new GlobalVariable(M, PointerTy, false, GlobalValue::ExternalLinkage, + nullptr, CompilerRtAPINames::ExpectedCalleeTLS); + ExpectedCalleeTLS->setThreadLocal(true); + ExpectedCalleeTLS->setVisibility(llvm::GlobalValue::HiddenVisibility); +} + +PreservedAnalyses PGOCtxProfLoweringPass::run(Module &M, + ModuleAnalysisManager &MAM) { + CtxInstrumentationLowerer Lowerer(M, MAM); + bool Changed = false; + for (auto &F : M) + Changed |= Lowerer.lowerFunction(F); + return Changed ? PreservedAnalyses::none() : PreservedAnalyses::all(); +} + +bool CtxInstrumentationLowerer::lowerFunction(Function &F) { + if (F.isDeclaration()) + return false; + auto &FAM = MAM.getResult(M).getManager(); + auto &ORE = FAM.getResult(F); + + Value *Guid = nullptr; + auto [NrCounters, NrCallsites] = getNrCountersAndCallsites(F); + + Value *Context = nullptr; + Value *RealContext = nullptr; + + StructType *ThisContextType = nullptr; + Value *TheRootContext = nullptr; + Value *ExpectedCalleeTLSAddr = nullptr; + Value *CallsiteInfoTLSAddr = nullptr; + + auto &Head = F.getEntryBlock(); + for (auto &I : Head) { + // Find the increment intrinsic in the entry basic block. + if (auto *Mark = dyn_cast(&I)) { + assert(Mark->getIndex()->isZero()); + + IRBuilder<> Builder(Mark); + // FIXME(mtrofin): use InstrProfSymtab::getCanonicalName + Guid = Builder.getInt64(F.getGUID()); + // The type of the context of this function is now knowable since we have + // NrCallsites and NrCounters. We delcare it here because it's more + // convenient - we have the Builder. + ThisContextType = StructType::get( + F.getContext(), + {ContextNodeTy, ArrayType::get(Builder.getInt64Ty(), NrCounters), + ArrayType::get(Builder.getPtrTy(), NrCallsites)}); + // Figure out which way we obtain the context object for this function - + // if it's an entrypoint, then we call StartCtx, otherwise GetCtx. In the + // former case, we also set TheRootContext since we need to release it + // at the end (plus it can be used to know if we have an entrypoint or a + // regular function) + auto Iter = ContextRootMap.find(&F); + if (Iter != ContextRootMap.end()) { + TheRootContext = Iter->second; + Context = Builder.CreateCall(StartCtx, {TheRootContext, Guid, + Builder.getInt32(NrCounters), + Builder.getInt32(NrCallsites)}); + ORE.emit( + [&] { return OptimizationRemark(DEBUG_TYPE, "Entrypoint", &F); }); + } else { + Context = + Builder.CreateCall(GetCtx, {&F, Guid, Builder.getInt32(NrCounters), + Builder.getInt32(NrCallsites)}); + ORE.emit([&] { + return OptimizationRemark(DEBUG_TYPE, "RegularFunction", &F); + }); + } + // The context could be scratch. + auto *CtxAsInt = Builder.CreatePtrToInt(Context, Builder.getInt64Ty()); + if (NrCallsites > 0) { + // Figure out which index of the TLS 2-element buffers to use. + // Scratch context => we use index == 1. Real contexts => index == 0. + auto *Index = Builder.CreateAnd(CtxAsInt, Builder.getInt64(1)); + // The GEPs corresponding to that index, in the respective TLS. + ExpectedCalleeTLSAddr = Builder.CreateGEP( + Builder.getInt8Ty()->getPointerTo(), + Builder.CreateThreadLocalAddress(ExpectedCalleeTLS), {Index}); + CallsiteInfoTLSAddr = Builder.CreateGEP( + Builder.getInt32Ty(), + Builder.CreateThreadLocalAddress(CallsiteInfoTLS), {Index}); + } + // Because the context pointer may have LSB set (to indicate scratch), + // clear it for the value we use as base address for the counter vector. + // This way, if later we want to have "real" (not clobbered) buffers + // acting as scratch, the lowering (at least this part of it that deals + // with counters) stays the same. + RealContext = Builder.CreateIntToPtr( + Builder.CreateAnd(CtxAsInt, Builder.getInt64(-2)), + ThisContextType->getPointerTo()); + I.eraseFromParent(); + break; + } + } + if (!Context) { + ORE.emit([&] { + return OptimizationRemarkMissed(DEBUG_TYPE, "Skip", &F) + << "Function doesn't have instrumentation, skipping"; + }); + return false; + } + + bool ContextWasReleased = false; + for (auto &BB : F) { + for (auto &I : llvm::make_early_inc_range(BB)) { + if (auto *Instr = dyn_cast(&I)) { + IRBuilder<> Builder(Instr); + switch (Instr->getIntrinsicID()) { + case llvm::Intrinsic::instrprof_increment: + case llvm::Intrinsic::instrprof_increment_step: { + // Increments (or increment-steps) are just a typical load - increment + // - store in the RealContext. + auto *AsStep = cast(Instr); + auto *GEP = Builder.CreateGEP( + ThisContextType, RealContext, + {Builder.getInt32(0), Builder.getInt32(1), AsStep->getIndex()}); + Builder.CreateStore( + Builder.CreateAdd(Builder.CreateLoad(Builder.getInt64Ty(), GEP), + AsStep->getStep()), + GEP); + } break; + case llvm::Intrinsic::instrprof_callsite: + // callsite lowering: write the called value in the expected callee + // TLS we treat the TLS as volatile because of signal handlers and to + // avoid these being moved away from the callsite they decorate. + auto *CSIntrinsic = dyn_cast(Instr); + Builder.CreateStore(CSIntrinsic->getCallee(), ExpectedCalleeTLSAddr, + true); + // write the GEP of the slot in the sub-contexts portion of the + // context in TLS. Now, here, we use the actual Context value - as + // returned from compiler-rt - which may have the LSB set if the + // Context was scratch. Since the header of the context object and + // then the values are all 8-aligned (or, really, insofar as we care, + // they are even) - if the context is scratch (meaning, an odd value), + // so will the GEP. This is important because this is then visible to + // compiler-rt which will produce scratch contexts for callers that + // have a scratch context. + Builder.CreateStore( + Builder.CreateGEP(ThisContextType, Context, + {Builder.getInt32(0), Builder.getInt32(2), + CSIntrinsic->getIndex()}), + CallsiteInfoTLSAddr, true); + break; + } + I.eraseFromParent(); + } else if (TheRootContext && isa(I)) { + // Remember to release the context if we are an entrypoint. + IRBuilder<> Builder(&I); + Builder.CreateCall(ReleaseCtx, {TheRootContext}); + ContextWasReleased = true; + } + } + } + // FIXME: This would happen if the entrypoint tailcalls. A way to fix would be + // to disallow this, (so this then stays as an error), another is to detect + // that and then do a wrapper or disallow the tail call. This only affects + // instrumentation, when we want to detect the call graph. + if (TheRootContext && !ContextWasReleased) + F.getContext().emitError( + "[ctx_prof] An entrypoint was instrumented but it has no `ret` " + "instructions above which to release the context: " + + F.getName()); + return true; +} diff --git a/llvm/test/Transforms/PGOProfile/ctx-instrumentation-invalid-roots.ll b/llvm/test/Transforms/PGOProfile/ctx-instrumentation-invalid-roots.ll new file mode 100644 index 000000000000..99c7762a67df --- /dev/null +++ b/llvm/test/Transforms/PGOProfile/ctx-instrumentation-invalid-roots.ll @@ -0,0 +1,17 @@ +; RUN: not opt -passes=pgo-instr-gen,ctx-instr-lower -profile-context-root=good \ +; RUN: -profile-context-root=bad \ +; RUN: -S < %s 2>&1 | FileCheck %s + +declare void @foo() + +define void @good() { + call void @foo() + ret void +} + +define void @bad() { + musttail call void @foo() + ret void +} + +; CHECK: error: The function bad was indicated as a context root, but it features musttail calls, which is not supported. diff --git a/llvm/test/Transforms/PGOProfile/ctx-instrumentation.ll b/llvm/test/Transforms/PGOProfile/ctx-instrumentation.ll index 2ad95ab51cc6..56c7c7519f69 100644 --- a/llvm/test/Transforms/PGOProfile/ctx-instrumentation.ll +++ b/llvm/test/Transforms/PGOProfile/ctx-instrumentation.ll @@ -1,11 +1,31 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 4 ; RUN: opt -passes=pgo-instr-gen -profile-context-root=an_entrypoint \ ; RUN: -S < %s | FileCheck --check-prefix=INSTRUMENT %s +; RUN: opt -passes=pgo-instr-gen,ctx-instr-lower -profile-context-root=an_entrypoint \ +; RUN: -profile-context-root=another_entrypoint_no_callees \ +; RUN: -S < %s | FileCheck --check-prefix=LOWERING %s + declare void @bar() ;. ; INSTRUMENT: @__profn_foo = private constant [3 x i8] c"foo" +; INSTRUMENT: @__profn_an_entrypoint = private constant [13 x i8] c"an_entrypoint" +; INSTRUMENT: @__profn_another_entrypoint_no_callees = private constant [29 x i8] c"another_entrypoint_no_callees" +; INSTRUMENT: @__profn_simple = private constant [6 x i8] c"simple" +; INSTRUMENT: @__profn_no_callsites = private constant [12 x i8] c"no_callsites" +; INSTRUMENT: @__profn_no_counters = private constant [11 x i8] c"no_counters" +;. +; LOWERING: @__profn_foo = private constant [3 x i8] c"foo" +; LOWERING: @__profn_an_entrypoint = private constant [13 x i8] c"an_entrypoint" +; LOWERING: @__profn_another_entrypoint_no_callees = private constant [29 x i8] c"another_entrypoint_no_callees" +; LOWERING: @__profn_simple = private constant [6 x i8] c"simple" +; LOWERING: @__profn_no_callsites = private constant [12 x i8] c"no_callsites" +; LOWERING: @__profn_no_counters = private constant [11 x i8] c"no_counters" +; LOWERING: @an_entrypoint_ctx_root = global { ptr, ptr, ptr, i8 } zeroinitializer +; LOWERING: @another_entrypoint_no_callees_ctx_root = global { ptr, ptr, ptr, i8 } zeroinitializer +; LOWERING: @__llvm_ctx_profile_callsite = external hidden thread_local global ptr +; LOWERING: @__llvm_ctx_profile_expected_callee = external hidden thread_local global ptr ;. define void @foo(i32 %a, ptr %fct) { ; INSTRUMENT-LABEL: define void @foo( @@ -24,6 +44,38 @@ define void @foo(i32 %a, ptr %fct) { ; INSTRUMENT-NEXT: br label [[EXIT]] ; INSTRUMENT: exit: ; INSTRUMENT-NEXT: ret void +; +; LOWERING-LABEL: define void @foo( +; LOWERING-SAME: i32 [[A:%.*]], ptr [[FCT:%.*]]) { +; LOWERING-NEXT: [[TMP1:%.*]] = call ptr @__llvm_ctx_profile_get_context(ptr @foo, i64 6699318081062747564, i32 2, i32 2) +; LOWERING-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; LOWERING-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 1 +; LOWERING-NEXT: [[TMP4:%.*]] = call ptr @llvm.threadlocal.address.p0(ptr @__llvm_ctx_profile_expected_callee) +; LOWERING-NEXT: [[TMP5:%.*]] = getelementptr ptr, ptr [[TMP4]], i64 [[TMP3]] +; LOWERING-NEXT: [[TMP6:%.*]] = call ptr @llvm.threadlocal.address.p0(ptr @__llvm_ctx_profile_callsite) +; LOWERING-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i64 [[TMP3]] +; LOWERING-NEXT: [[TMP8:%.*]] = and i64 [[TMP2]], -2 +; LOWERING-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr +; LOWERING-NEXT: [[T:%.*]] = icmp eq i32 [[A]], 0 +; LOWERING-NEXT: br i1 [[T]], label [[YES:%.*]], label [[NO:%.*]] +; LOWERING: yes: +; LOWERING-NEXT: [[TMP10:%.*]] = getelementptr { { i64, ptr, i32, i32 }, [2 x i64], [2 x ptr] }, ptr [[TMP9]], i32 0, i32 1, i32 1 +; LOWERING-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 4 +; LOWERING-NEXT: [[TMP12:%.*]] = add i64 [[TMP11]], 1 +; LOWERING-NEXT: store i64 [[TMP12]], ptr [[TMP10]], align 4 +; LOWERING-NEXT: store volatile ptr [[FCT]], ptr [[TMP5]], align 8 +; LOWERING-NEXT: [[TMP13:%.*]] = getelementptr { { i64, ptr, i32, i32 }, [2 x i64], [2 x ptr] }, ptr [[TMP1]], i32 0, i32 2, i32 0 +; LOWERING-NEXT: store volatile ptr [[TMP13]], ptr [[TMP7]], align 8 +; LOWERING-NEXT: call void [[FCT]](i32 [[A]]) +; LOWERING-NEXT: br label [[EXIT:%.*]] +; LOWERING: no: +; LOWERING-NEXT: store volatile ptr @bar, ptr [[TMP5]], align 8 +; LOWERING-NEXT: [[TMP14:%.*]] = getelementptr { { i64, ptr, i32, i32 }, [2 x i64], [2 x ptr] }, ptr [[TMP1]], i32 0, i32 2, i32 1 +; LOWERING-NEXT: store volatile ptr [[TMP14]], ptr [[TMP7]], align 8 +; LOWERING-NEXT: call void @bar() +; LOWERING-NEXT: br label [[EXIT]] +; LOWERING: exit: +; LOWERING-NEXT: ret void ; %t = icmp eq i32 %a, 0 br i1 %t, label %yes, label %no @@ -36,6 +88,183 @@ no: exit: ret void } + +define void @an_entrypoint(i32 %a) { +; INSTRUMENT-LABEL: define void @an_entrypoint( +; INSTRUMENT-SAME: i32 [[A:%.*]]) { +; INSTRUMENT-NEXT: call void @llvm.instrprof.increment(ptr @__profn_an_entrypoint, i64 784007058953177093, i32 2, i32 0) +; INSTRUMENT-NEXT: [[T:%.*]] = icmp eq i32 [[A]], 0 +; INSTRUMENT-NEXT: br i1 [[T]], label [[YES:%.*]], label [[NO:%.*]] +; INSTRUMENT: yes: +; INSTRUMENT-NEXT: call void @llvm.instrprof.increment(ptr @__profn_an_entrypoint, i64 784007058953177093, i32 2, i32 1) +; INSTRUMENT-NEXT: call void @llvm.instrprof.callsite(ptr @__profn_an_entrypoint, i64 784007058953177093, i32 1, i32 0, ptr @foo) +; INSTRUMENT-NEXT: call void @foo(i32 1, ptr null) +; INSTRUMENT-NEXT: ret void +; INSTRUMENT: no: +; INSTRUMENT-NEXT: ret void +; +; LOWERING-LABEL: define void @an_entrypoint( +; LOWERING-SAME: i32 [[A:%.*]]) { +; LOWERING-NEXT: [[TMP1:%.*]] = call ptr @__llvm_ctx_profile_start_context(ptr @an_entrypoint_ctx_root, i64 4909520559318251808, i32 2, i32 1) +; LOWERING-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; LOWERING-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 1 +; LOWERING-NEXT: [[TMP4:%.*]] = call ptr @llvm.threadlocal.address.p0(ptr @__llvm_ctx_profile_expected_callee) +; LOWERING-NEXT: [[TMP5:%.*]] = getelementptr ptr, ptr [[TMP4]], i64 [[TMP3]] +; LOWERING-NEXT: [[TMP6:%.*]] = call ptr @llvm.threadlocal.address.p0(ptr @__llvm_ctx_profile_callsite) +; LOWERING-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i64 [[TMP3]] +; LOWERING-NEXT: [[TMP8:%.*]] = and i64 [[TMP2]], -2 +; LOWERING-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr +; LOWERING-NEXT: [[T:%.*]] = icmp eq i32 [[A]], 0 +; LOWERING-NEXT: br i1 [[T]], label [[YES:%.*]], label [[NO:%.*]] +; LOWERING: yes: +; LOWERING-NEXT: [[TMP10:%.*]] = getelementptr { { i64, ptr, i32, i32 }, [2 x i64], [1 x ptr] }, ptr [[TMP9]], i32 0, i32 1, i32 1 +; LOWERING-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 4 +; LOWERING-NEXT: [[TMP12:%.*]] = add i64 [[TMP11]], 1 +; LOWERING-NEXT: store i64 [[TMP12]], ptr [[TMP10]], align 4 +; LOWERING-NEXT: store volatile ptr @foo, ptr [[TMP5]], align 8 +; LOWERING-NEXT: [[TMP13:%.*]] = getelementptr { { i64, ptr, i32, i32 }, [2 x i64], [1 x ptr] }, ptr [[TMP1]], i32 0, i32 2, i32 0 +; LOWERING-NEXT: store volatile ptr [[TMP13]], ptr [[TMP7]], align 8 +; LOWERING-NEXT: call void @foo(i32 1, ptr null) +; LOWERING-NEXT: call void @__llvm_ctx_profile_release_context(ptr @an_entrypoint_ctx_root) +; LOWERING-NEXT: ret void +; LOWERING: no: +; LOWERING-NEXT: call void @__llvm_ctx_profile_release_context(ptr @an_entrypoint_ctx_root) +; LOWERING-NEXT: ret void +; + %t = icmp eq i32 %a, 0 + br i1 %t, label %yes, label %no + +yes: + call void @foo(i32 1, ptr null) + ret void +no: + ret void +} + +define void @another_entrypoint_no_callees(i32 %a) { +; INSTRUMENT-LABEL: define void @another_entrypoint_no_callees( +; INSTRUMENT-SAME: i32 [[A:%.*]]) { +; INSTRUMENT-NEXT: call void @llvm.instrprof.increment(ptr @__profn_another_entrypoint_no_callees, i64 784007058953177093, i32 2, i32 0) +; INSTRUMENT-NEXT: [[T:%.*]] = icmp eq i32 [[A]], 0 +; INSTRUMENT-NEXT: br i1 [[T]], label [[YES:%.*]], label [[NO:%.*]] +; INSTRUMENT: yes: +; INSTRUMENT-NEXT: call void @llvm.instrprof.increment(ptr @__profn_another_entrypoint_no_callees, i64 784007058953177093, i32 2, i32 1) +; INSTRUMENT-NEXT: ret void +; INSTRUMENT: no: +; INSTRUMENT-NEXT: ret void +; +; LOWERING-LABEL: define void @another_entrypoint_no_callees( +; LOWERING-SAME: i32 [[A:%.*]]) { +; LOWERING-NEXT: [[TMP1:%.*]] = call ptr @__llvm_ctx_profile_start_context(ptr @another_entrypoint_no_callees_ctx_root, i64 -6371873725078000974, i32 2, i32 0) +; LOWERING-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; LOWERING-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], -2 +; LOWERING-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; LOWERING-NEXT: [[T:%.*]] = icmp eq i32 [[A]], 0 +; LOWERING-NEXT: br i1 [[T]], label [[YES:%.*]], label [[NO:%.*]] +; LOWERING: yes: +; LOWERING-NEXT: [[TMP5:%.*]] = getelementptr { { i64, ptr, i32, i32 }, [2 x i64], [0 x ptr] }, ptr [[TMP4]], i32 0, i32 1, i32 1 +; LOWERING-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 4 +; LOWERING-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 1 +; LOWERING-NEXT: store i64 [[TMP7]], ptr [[TMP5]], align 4 +; LOWERING-NEXT: call void @__llvm_ctx_profile_release_context(ptr @another_entrypoint_no_callees_ctx_root) +; LOWERING-NEXT: ret void +; LOWERING: no: +; LOWERING-NEXT: call void @__llvm_ctx_profile_release_context(ptr @another_entrypoint_no_callees_ctx_root) +; LOWERING-NEXT: ret void +; + %t = icmp eq i32 %a, 0 + br i1 %t, label %yes, label %no + +yes: + ret void +no: + ret void +} + +define void @simple(i32 %a) { +; INSTRUMENT-LABEL: define void @simple( +; INSTRUMENT-SAME: i32 [[A:%.*]]) { +; INSTRUMENT-NEXT: call void @llvm.instrprof.increment(ptr @__profn_simple, i64 742261418966908927, i32 1, i32 0) +; INSTRUMENT-NEXT: ret void +; +; LOWERING-LABEL: define void @simple( +; LOWERING-SAME: i32 [[A:%.*]]) { +; LOWERING-NEXT: [[TMP1:%.*]] = call ptr @__llvm_ctx_profile_get_context(ptr @simple, i64 -3006003237940970099, i32 1, i32 0) +; LOWERING-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; LOWERING-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], -2 +; LOWERING-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; LOWERING-NEXT: ret void +; + ret void +} + + +define i32 @no_callsites(i32 %a) { +; INSTRUMENT-LABEL: define i32 @no_callsites( +; INSTRUMENT-SAME: i32 [[A:%.*]]) { +; INSTRUMENT-NEXT: call void @llvm.instrprof.increment(ptr @__profn_no_callsites, i64 784007058953177093, i32 2, i32 0) +; INSTRUMENT-NEXT: [[C:%.*]] = icmp eq i32 [[A]], 0 +; INSTRUMENT-NEXT: br i1 [[C]], label [[YES:%.*]], label [[NO:%.*]] +; INSTRUMENT: yes: +; INSTRUMENT-NEXT: call void @llvm.instrprof.increment(ptr @__profn_no_callsites, i64 784007058953177093, i32 2, i32 1) +; INSTRUMENT-NEXT: ret i32 1 +; INSTRUMENT: no: +; INSTRUMENT-NEXT: ret i32 0 +; +; LOWERING-LABEL: define i32 @no_callsites( +; LOWERING-SAME: i32 [[A:%.*]]) { +; LOWERING-NEXT: [[TMP1:%.*]] = call ptr @__llvm_ctx_profile_get_context(ptr @no_callsites, i64 5679753335911435902, i32 2, i32 0) +; LOWERING-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; LOWERING-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], -2 +; LOWERING-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; LOWERING-NEXT: [[C:%.*]] = icmp eq i32 [[A]], 0 +; LOWERING-NEXT: br i1 [[C]], label [[YES:%.*]], label [[NO:%.*]] +; LOWERING: yes: +; LOWERING-NEXT: [[TMP5:%.*]] = getelementptr { { i64, ptr, i32, i32 }, [2 x i64], [0 x ptr] }, ptr [[TMP4]], i32 0, i32 1, i32 1 +; LOWERING-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 4 +; LOWERING-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 1 +; LOWERING-NEXT: store i64 [[TMP7]], ptr [[TMP5]], align 4 +; LOWERING-NEXT: ret i32 1 +; LOWERING: no: +; LOWERING-NEXT: ret i32 0 +; + %c = icmp eq i32 %a, 0 + br i1 %c, label %yes, label %no +yes: + ret i32 1 +no: + ret i32 0 +} + +define void @no_counters() { +; INSTRUMENT-LABEL: define void @no_counters() { +; INSTRUMENT-NEXT: call void @llvm.instrprof.increment(ptr @__profn_no_counters, i64 742261418966908927, i32 1, i32 0) +; INSTRUMENT-NEXT: call void @llvm.instrprof.callsite(ptr @__profn_no_counters, i64 742261418966908927, i32 1, i32 0, ptr @bar) +; INSTRUMENT-NEXT: call void @bar() +; INSTRUMENT-NEXT: ret void +; +; LOWERING-LABEL: define void @no_counters() { +; LOWERING-NEXT: [[TMP1:%.*]] = call ptr @__llvm_ctx_profile_get_context(ptr @no_counters, i64 5458232184388660970, i32 1, i32 1) +; LOWERING-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; LOWERING-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 1 +; LOWERING-NEXT: [[TMP4:%.*]] = call ptr @llvm.threadlocal.address.p0(ptr @__llvm_ctx_profile_expected_callee) +; LOWERING-NEXT: [[TMP5:%.*]] = getelementptr ptr, ptr [[TMP4]], i64 [[TMP3]] +; LOWERING-NEXT: [[TMP6:%.*]] = call ptr @llvm.threadlocal.address.p0(ptr @__llvm_ctx_profile_callsite) +; LOWERING-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i64 [[TMP3]] +; LOWERING-NEXT: [[TMP8:%.*]] = and i64 [[TMP2]], -2 +; LOWERING-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr +; LOWERING-NEXT: store volatile ptr @bar, ptr [[TMP5]], align 8 +; LOWERING-NEXT: [[TMP10:%.*]] = getelementptr { { i64, ptr, i32, i32 }, [1 x i64], [1 x ptr] }, ptr [[TMP1]], i32 0, i32 2, i32 0 +; LOWERING-NEXT: store volatile ptr [[TMP10]], ptr [[TMP7]], align 8 +; LOWERING-NEXT: call void @bar() +; LOWERING-NEXT: ret void +; + call void @bar() + ret void +} ;. ; INSTRUMENT: attributes #[[ATTR0:[0-9]+]] = { nounwind } ;. +; LOWERING: attributes #[[ATTR0:[0-9]+]] = { nounwind } +; LOWERING: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +;. -- GitLab From 1aaab334c53d5c52ae337939e9c853e6e1061128 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 8 May 2024 17:22:18 -0700 Subject: [PATCH 090/328] [RISCV] Don't use std::vector for split extensions in RISCVISAInfo::parseArchString. NFC (#91538) We can use a SmallVector. Adjust the code so we check for empty strings in the loop instead of making a copy of the vector returned from StringRef::split. This overlaps with #91532 which also removed the std::vector, but that PR may be more controversial. --- llvm/lib/TargetParser/RISCVISAInfo.cpp | 49 ++++++++++---------------- 1 file changed, 18 insertions(+), 31 deletions(-) diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index 96590745b2eb..c553e330a878 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -500,24 +500,6 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) { return std::move(ISAInfo); } -static Error splitExtsByUnderscore(StringRef Exts, - std::vector &SplitExts) { - SmallVector Split; - if (Exts.empty()) - return Error::success(); - - Exts.split(Split, "_"); - - for (auto Ext : Split) { - if (Ext.empty()) - return createStringError(errc::invalid_argument, - "extension name missing after separator '_'"); - - SplitExts.push_back(Ext.str()); - } - return Error::success(); -} - static Error processMultiLetterExtension( StringRef RawExt, MapVector SplitExts; - if (auto E = splitExtsByUnderscore(Exts, SplitExts)) - return std::move(E); + SmallVector SplitExts; + // Only split if the string is not empty. Otherwise the split will push an + // empty string into the vector. + if (!Exts.empty()) + Exts.split(SplitExts, '_'); + + for (auto Ext : SplitExts) { + if (Ext.empty()) + return createStringError(errc::invalid_argument, + "extension name missing after separator '_'"); - for (auto &Ext : SplitExts) { - StringRef CurrExt = Ext; - while (!CurrExt.empty()) { - if (RISCVISAUtils::AllStdExts.contains(CurrExt.front())) { + do { + if (RISCVISAUtils::AllStdExts.contains(Ext.front())) { if (auto E = processSingleLetterExtension( - CurrExt, SeenExtMap, IgnoreUnknown, EnableExperimentalExtension, + Ext, SeenExtMap, IgnoreUnknown, EnableExperimentalExtension, ExperimentalExtensionVersionCheck)) return std::move(E); - } else if (CurrExt.front() == 'z' || CurrExt.front() == 's' || - CurrExt.front() == 'x') { + } else if (Ext.front() == 'z' || Ext.front() == 's' || + Ext.front() == 'x') { // Handle other types of extensions other than the standard // general purpose and standard user-level extensions. // Parse the ISA string containing non-standard user-level @@ -737,7 +724,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, // version number (major, minor) and are separated by a single // underscore '_'. We do not enforce a canonical order for them. if (auto E = processMultiLetterExtension( - CurrExt, SeenExtMap, IgnoreUnknown, EnableExperimentalExtension, + Ext, SeenExtMap, IgnoreUnknown, EnableExperimentalExtension, ExperimentalExtensionVersionCheck)) return std::move(E); // Multi-letter extension must be seperate following extension with @@ -747,9 +734,9 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, // FIXME: Could it be ignored by IgnoreUnknown? return createStringError(errc::invalid_argument, "invalid standard user-level extension '" + - Twine(CurrExt.front()) + "'"); + Twine(Ext.front()) + "'"); } - } + } while (!Ext.empty()); } // Check all Extensions are supported. -- GitLab From 409ff97aac00e5a677c90353b8b413c2bf46e28f Mon Sep 17 00:00:00 2001 From: AtariDreams Date: Wed, 8 May 2024 20:26:36 -0400 Subject: [PATCH 091/328] [InstCombine] Fix comment from #88193 (NFC) (#91427) It is inaccurate and needs to be corrected. --- llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp index 8847de366713..ba297111d945 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp @@ -1259,7 +1259,7 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) { match(Op1, m_SpecificIntAllowPoison(BitWidth - 1))) return new ZExtInst(Builder.CreateIsNotNeg(X, "isnotneg"), Ty); - // ((X << nuw Z) sub nuw Y) >>u exact Z --> X sub nuw (Y >>u exact Z), + // ((X << nuw Z) sub nuw Y) >>u exact Z --> X sub nuw (Y >>u exact Z) Value *Y; if (I.isExact() && match(Op0, m_OneUse(m_NUWSub(m_NUWShl(m_Value(X), m_Specific(Op1)), @@ -1279,7 +1279,7 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) { case Instruction::And: case Instruction::Or: case Instruction::Xor: - // And does not work here, and sub is handled separately. + // Sub is handled separately. return true; } }; -- GitLab From ba5170f430b027c6d290f57d7a5d7ba6ee2b265b Mon Sep 17 00:00:00 2001 From: AtariDreams Date: Wed, 8 May 2024 20:29:14 -0400 Subject: [PATCH 092/328] [InstCombine] Thwart complexity-based canonicalization in shl-add test (NFC) (#91413) Fixed test for #88193 --- llvm/test/Transforms/InstCombine/lshr.ll | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll index 563e669f9035..fa92c1c4b3be 100644 --- a/llvm/test/Transforms/InstCombine/lshr.ll +++ b/llvm/test/Transforms/InstCombine/lshr.ll @@ -397,12 +397,14 @@ define i32 @shl_add_lshr(i32 %x, i32 %c, i32 %y) { define i32 @shl_add_lshr_comm(i32 %x, i32 %c, i32 %y) { ; CHECK-LABEL: @shl_add_lshr_comm( -; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[Y:%.*]], [[C:%.*]] +; CHECK-NEXT: [[Y2:%.*]] = mul i32 [[Y:%.*]], [[Y]] +; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[Y2]], [[C:%.*]] ; CHECK-NEXT: [[LSHR:%.*]] = add nuw i32 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: ret i32 [[LSHR]] ; %shl = shl nuw i32 %x, %c - %add = add nuw i32 %y, %shl + %y2 = mul i32 %y, %y ; thwart complexity-based canonicalization + %add = add nuw i32 %y2, %shl %lshr = lshr i32 %add, %c ret i32 %lshr } -- GitLab From 62b5b61f436add042d8729dc9837d055613180d9 Mon Sep 17 00:00:00 2001 From: Krystian Stasiowski Date: Wed, 8 May 2024 20:49:59 -0400 Subject: [PATCH 093/328] [Clang][Sema] Fix lookup of dependent operator= outside of complete-class contexts (#91498) Fixes a crash caused by #90152. --- clang/lib/Sema/SemaLookup.cpp | 35 +++++++++++-------- clang/lib/Sema/SemaTemplate.cpp | 7 ++-- .../temp.res/temp.dep/temp.dep.type/p4.cpp | 13 +++++++ 3 files changed, 35 insertions(+), 20 deletions(-) diff --git a/clang/lib/Sema/SemaLookup.cpp b/clang/lib/Sema/SemaLookup.cpp index e63da5875d2c..e20de338ebb1 100644 --- a/clang/lib/Sema/SemaLookup.cpp +++ b/clang/lib/Sema/SemaLookup.cpp @@ -1267,6 +1267,20 @@ struct FindLocalExternScope { LookupResult &R; bool OldFindLocalExtern; }; + +/// Returns true if 'operator=' should be treated as a dependent name. +bool isDependentAssignmentOperator(DeclarationName Name, + DeclContext *LookupContext) { + const auto *LookupRecord = dyn_cast_if_present(LookupContext); + // If the lookup context is the current instantiation but we are outside a + // complete-class context, we will never find the implicitly declared + // copy/move assignment operators because they are declared at the closing '}' + // of the class specifier. In such cases, we treat 'operator=' like any other + // unqualified name because the results of name lookup in the template + // definition/instantiation context will always be the same. + return Name.getCXXOverloadedOperator() == OO_Equal && LookupRecord && + !LookupRecord->isBeingDefined() && LookupRecord->isDependentContext(); +} } // end anonymous namespace bool Sema::CppLookupName(LookupResult &R, Scope *S) { @@ -1275,13 +1289,6 @@ bool Sema::CppLookupName(LookupResult &R, Scope *S) { DeclarationName Name = R.getLookupName(); Sema::LookupNameKind NameKind = R.getLookupKind(); - // If this is the name of an implicitly-declared special member function, - // go through the scope stack to implicitly declare - if (isImplicitlyDeclaredMemberFunctionName(Name)) { - for (Scope *PreS = S; PreS; PreS = PreS->getParent()) - if (DeclContext *DC = PreS->getEntity()) - DeclareImplicitMemberFunctionsWithName(*this, Name, R.getNameLoc(), DC); - } // C++23 [temp.dep.general]p2: // The component name of an unqualified-id is dependent if // - it is a conversion-function-id whose conversion-type-id @@ -1299,9 +1306,8 @@ bool Sema::CppLookupName(LookupResult &R, Scope *S) { if (isImplicitlyDeclaredMemberFunctionName(Name)) { for (Scope *PreS = S; PreS; PreS = PreS->getParent()) if (DeclContext *DC = PreS->getEntity()) { - if (DC->isDependentContext() && isa(DC) && - Name.getCXXOverloadedOperator() == OO_Equal && - !R.isTemplateNameLookup()) { + if (!R.isTemplateNameLookup() && + isDependentAssignmentOperator(Name, DC)) { R.setNotFoundInCurrentInstantiation(); return false; } @@ -2472,8 +2478,6 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, } } QL(LookupCtx); - bool TemplateNameLookup = R.isTemplateNameLookup(); - CXXRecordDecl *LookupRec = dyn_cast(LookupCtx); if (!InUnqualifiedLookup && !R.isForRedeclaration()) { // C++23 [temp.dep.type]p5: // A qualified name is dependent if @@ -2486,13 +2490,14 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, if (DeclarationName Name = R.getLookupName(); (Name.getNameKind() == DeclarationName::CXXConversionFunctionName && Name.getCXXNameType()->isDependentType()) || - (Name.getCXXOverloadedOperator() == OO_Equal && LookupRec && - LookupRec->isDependentContext() && !TemplateNameLookup)) { + (!R.isTemplateNameLookup() && + isDependentAssignmentOperator(Name, LookupCtx))) { R.setNotFoundInCurrentInstantiation(); return false; } } + CXXRecordDecl *LookupRec = dyn_cast(LookupCtx); if (LookupDirect(*this, R, LookupCtx)) { R.resolveKind(); if (LookupRec) @@ -2604,7 +2609,7 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, // template, and if the name is used as a template-name, the // reference refers to the class template itself and not a // specialization thereof, and is not ambiguous. - if (TemplateNameLookup) + if (R.isTemplateNameLookup()) if (auto *TD = getAsTemplateNameDecl(ND)) ND = TD; diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index 7e57fa069672..480bc74c2001 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -726,7 +726,7 @@ Sema::ActOnDependentIdExpression(const CXXScopeSpec &SS, const DeclarationNameInfo &NameInfo, bool isAddressOfOperand, const TemplateArgumentListInfo *TemplateArgs) { - DeclContext *DC = getFunctionLevelDeclContext(); + QualType ThisType = getCurrentThisType(); // C++11 [expr.prim.general]p12: // An id-expression that denotes a non-static data member or non-static @@ -748,10 +748,7 @@ Sema::ActOnDependentIdExpression(const CXXScopeSpec &SS, IsEnum = isa_and_nonnull(NNS->getAsType()); if (!MightBeCxx11UnevalField && !isAddressOfOperand && !IsEnum && - isa(DC) && - cast(DC)->isImplicitObjectMemberFunction()) { - QualType ThisType = cast(DC)->getThisType().getNonReferenceType(); - + !ThisType.isNull()) { // Since the 'this' expression is synthesized, we don't need to // perform the double-lookup check. NamedDecl *FirstQualifierInScope = nullptr; diff --git a/clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/p4.cpp b/clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/p4.cpp index 46dd52f8c4c1..43053c18c507 100644 --- a/clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/p4.cpp +++ b/clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/p4.cpp @@ -471,6 +471,19 @@ namespace N3 { this->C::operator=(*this); } }; + + template + struct D { + auto not_instantiated() -> decltype(operator=(0)); // expected-error {{use of undeclared 'operator='}} + }; + + template + struct E { + auto instantiated(E& e) -> decltype(operator=(e)); // expected-error {{use of undeclared 'operator='}} + }; + + template struct E; // expected-note {{in instantiation of template class 'N3::E' requested here}} + } // namespace N3 namespace N4 { -- GitLab From 73a01448c733bf08443435927677d0ebd133615b Mon Sep 17 00:00:00 2001 From: Maksim Panchenko Date: Wed, 8 May 2024 17:56:44 -0700 Subject: [PATCH 094/328] [BOLT] Add test case for PIC fixed indirect jump (#91547) A compiler can generate a redundant indirection for a jump via a fixed jump table target. Add a test case that covers such pattern that covers PIC case. We already have non-PIC case detection. Currently XFAIL. --- .../X86/Inputs/jump-table-fixed-ref-pic.s | 35 +++++++++++++++++++ bolt/test/X86/jump-table-fixed-ref-pic.test | 9 +++++ 2 files changed, 44 insertions(+) create mode 100644 bolt/test/X86/Inputs/jump-table-fixed-ref-pic.s create mode 100644 bolt/test/X86/jump-table-fixed-ref-pic.test diff --git a/bolt/test/X86/Inputs/jump-table-fixed-ref-pic.s b/bolt/test/X86/Inputs/jump-table-fixed-ref-pic.s new file mode 100644 index 000000000000..66629a4880e6 --- /dev/null +++ b/bolt/test/X86/Inputs/jump-table-fixed-ref-pic.s @@ -0,0 +1,35 @@ + .globl main + .type main, %function +main: + .cfi_startproc + cmpq $0x3, %rdi + jae .L4 + cmpq $0x1, %rdi + jne .L4 + mov .Ljt_pic+8(%rip), %rax + lea .Ljt_pic(%rip), %rdx + add %rdx, %rax + jmpq *%rax +.L1: + movq $0x1, %rax + jmp .L5 +.L2: + movq $0x0, %rax + jmp .L5 +.L3: + movq $0x2, %rax + jmp .L5 +.L4: + mov $0x3, %rax +.L5: + retq + .cfi_endproc + + .section .rodata + .align 16 +.Ljt_pic: + .long .L1 - .Ljt_pic + .long .L2 - .Ljt_pic + .long .L3 - .Ljt_pic + .long .L4 - .Ljt_pic + diff --git a/bolt/test/X86/jump-table-fixed-ref-pic.test b/bolt/test/X86/jump-table-fixed-ref-pic.test new file mode 100644 index 000000000000..4195b97aac50 --- /dev/null +++ b/bolt/test/X86/jump-table-fixed-ref-pic.test @@ -0,0 +1,9 @@ +# Verify that BOLT detects fixed destination of indirect jump for PIC +# case. + +XFAIL: * + +RUN: %clang %cflags -no-pie %S/Inputs/jump-table-fixed-ref-pic.s -Wl,-q -o %t +RUN: llvm-bolt %t --relocs -o %t.null 2>&1 | FileCheck %s + +CHECK: BOLT-INFO: fixed indirect branch detected in main -- GitLab From 51f178d909d477bd269e0b434af1a7f9373d4e61 Mon Sep 17 00:00:00 2001 From: Artem Dergachev Date: Wed, 8 May 2024 18:00:59 -0700 Subject: [PATCH 095/328] [analyzer] MallocChecker: Recognize std::atomics in smart pointer suppression. (#90918) Fixes #90498. Same as 5337efc69cdd5 for atomic builtins, but for `std::atomic` this time. This is useful because even though the actual builtin atomic is still there, it may be buried beyond the inlining depth limit. Also add one popular custom smart pointer class name to the name-based heuristics, which isn't necessary to fix the bug but arguably a good idea regardless. --- .../StaticAnalyzer/Checkers/MallocChecker.cpp | 19 ++- .../Inputs/system-header-simulator-cxx.h | 7 ++ clang/test/Analysis/NewDelete-atomics.cpp | 116 ++++++++++++++++-- 3 files changed, 130 insertions(+), 12 deletions(-) diff --git a/clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp index dd204b62dcc0..ab89fb14046b 100644 --- a/clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp @@ -3451,7 +3451,7 @@ static bool isReferenceCountingPointerDestructor(const CXXDestructorDecl *DD) { if (N.contains_insensitive("ptr") || N.contains_insensitive("pointer")) { if (N.contains_insensitive("ref") || N.contains_insensitive("cnt") || N.contains_insensitive("intrusive") || - N.contains_insensitive("shared")) { + N.contains_insensitive("shared") || N.ends_with_insensitive("rc")) { return true; } } @@ -3483,13 +3483,24 @@ PathDiagnosticPieceRef MallocBugVisitor::VisitNode(const ExplodedNode *N, // original reference count is positive, we should not report use-after-frees // on objects deleted in such destructors. This can probably be improved // through better shared pointer modeling. - if (ReleaseDestructorLC) { + if (ReleaseDestructorLC && (ReleaseDestructorLC == CurrentLC || + ReleaseDestructorLC->isParentOf(CurrentLC))) { if (const auto *AE = dyn_cast(S)) { + // Check for manual use of atomic builtins. AtomicExpr::AtomicOp Op = AE->getOp(); if (Op == AtomicExpr::AO__c11_atomic_fetch_add || Op == AtomicExpr::AO__c11_atomic_fetch_sub) { - if (ReleaseDestructorLC == CurrentLC || - ReleaseDestructorLC->isParentOf(CurrentLC)) { + BR.markInvalid(getTag(), S); + } + } else if (const auto *CE = dyn_cast(S)) { + // Check for `std::atomic` and such. This covers both regular method calls + // and operator calls. + if (const auto *MD = + dyn_cast_or_null(CE->getDirectCallee())) { + const CXXRecordDecl *RD = MD->getParent(); + // A bit wobbly with ".contains()" because it may be like + // "__atomic_base" or something. + if (StringRef(RD->getNameAsString()).contains("atomic")) { BR.markInvalid(getTag(), S); } } diff --git a/clang/test/Analysis/Inputs/system-header-simulator-cxx.h b/clang/test/Analysis/Inputs/system-header-simulator-cxx.h index 1c2be322f83c..29326ec1f928 100644 --- a/clang/test/Analysis/Inputs/system-header-simulator-cxx.h +++ b/clang/test/Analysis/Inputs/system-header-simulator-cxx.h @@ -1260,6 +1260,13 @@ template< iterator end() const { return iterator(val + 1); } }; +template +class atomic { +public: + T operator++(); + T operator--(); +}; + namespace execution { class sequenced_policy {}; } diff --git a/clang/test/Analysis/NewDelete-atomics.cpp b/clang/test/Analysis/NewDelete-atomics.cpp index 54fce17ea7bd..1425acab7489 100644 --- a/clang/test/Analysis/NewDelete-atomics.cpp +++ b/clang/test/Analysis/NewDelete-atomics.cpp @@ -20,7 +20,7 @@ typedef enum memory_order { memory_order_seq_cst = __ATOMIC_SEQ_CST } memory_order; -class Obj { +class RawObj { int RefCnt; public: @@ -37,11 +37,27 @@ public: void foo(); }; +class StdAtomicObj { + std::atomic RefCnt; + +public: + int incRef() { + return ++RefCnt; + } + + int decRef() { + return --RefCnt; + } + + void foo(); +}; + +template class IntrusivePtr { - Obj *Ptr; + T *Ptr; public: - IntrusivePtr(Obj *Ptr) : Ptr(Ptr) { + IntrusivePtr(T *Ptr) : Ptr(Ptr) { Ptr->incRef(); } @@ -55,22 +71,106 @@ public: delete Ptr; } - Obj *getPtr() const { return Ptr; } // no-warning + T *getPtr() const { return Ptr; } // no-warning +}; + +// Also IntrusivePtr but let's dodge name-based heuristics. +template +class DifferentlyNamed { + T *Ptr; + +public: + DifferentlyNamed(T *Ptr) : Ptr(Ptr) { + Ptr->incRef(); + } + + DifferentlyNamed(const DifferentlyNamed &Other) : Ptr(Other.Ptr) { + Ptr->incRef(); + } + + ~DifferentlyNamed() { + // We should not take the path on which the object is deleted. + if (Ptr->decRef() == 1) + delete Ptr; + } + + T *getPtr() const { return Ptr; } // no-warning }; void testDestroyLocalRefPtr() { - IntrusivePtr p1(new Obj()); + IntrusivePtr p1(new RawObj()); + { + IntrusivePtr p2(p1); + } + + // p1 still maintains ownership. The object is not deleted. + p1.getPtr()->foo(); // no-warning +} + +void testDestroySymbolicRefPtr(const IntrusivePtr &p1) { + { + IntrusivePtr p2(p1); + } + + // p1 still maintains ownership. The object is not deleted. + p1.getPtr()->foo(); // no-warning +} + +void testDestroyLocalRefPtrWithAtomics() { + IntrusivePtr p1(new StdAtomicObj()); + { + IntrusivePtr p2(p1); + } + + // p1 still maintains ownership. The object is not deleted. + p1.getPtr()->foo(); // no-warning +} + + +void testDestroyLocalRefPtrWithAtomics(const IntrusivePtr &p1) { { - IntrusivePtr p2(p1); + IntrusivePtr p2(p1); } // p1 still maintains ownership. The object is not deleted. p1.getPtr()->foo(); // no-warning } -void testDestroySymbolicRefPtr(const IntrusivePtr &p1) { +void testDestroyLocalRefPtrDifferentlyNamed() { + DifferentlyNamed p1(new RawObj()); + { + DifferentlyNamed p2(p1); + } + + // p1 still maintains ownership. The object is not deleted. + p1.getPtr()->foo(); // no-warning +} + +void testDestroySymbolicRefPtrDifferentlyNamed( + const DifferentlyNamed &p1) { + { + DifferentlyNamed p2(p1); + } + + // p1 still maintains ownership. The object is not deleted. + p1.getPtr()->foo(); // no-warning +} + +void testDestroyLocalRefPtrWithAtomicsDifferentlyNamed() { + DifferentlyNamed p1(new StdAtomicObj()); + { + DifferentlyNamed p2(p1); + } + + // p1 still maintains ownership. The object is not deleted. + p1.getPtr()->foo(); // no-warning +} + + +void testDestroyLocalRefPtrWithAtomicsDifferentlyNamed( + const DifferentlyNamed &p1) { { - IntrusivePtr p2(p1); + DifferentlyNamed p2(p1); } // p1 still maintains ownership. The object is not deleted. -- GitLab From ea126aebdc9d8205016f355d85dbf1c15f2f4b28 Mon Sep 17 00:00:00 2001 From: "Felix (Ting Wang)" Date: Thu, 9 May 2024 09:50:36 +0800 Subject: [PATCH 096/328] [PowerPC] Tune AIX shared library TLS model at function level (#84132) Under some circumstance (library loaded with the main program), TLS initial-exec model can be applied to local-dynamic access(es). We could use some simple heuristic to decide the update at function level: * If there is equal or less than a number of TLS local-dynamic access(es) in the function, use TLS initial-exec model. (the threshold which default to 1 is controlled by hidden option) --- clang/include/clang/Driver/Options.td | 4 + clang/lib/Basic/Targets/PPC.cpp | 6 + clang/lib/Basic/Targets/PPC.h | 1 + llvm/lib/Target/PowerPC/PPC.td | 6 + llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 15 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 58 ++ llvm/lib/Target/PowerPC/PPCMCInstLower.cpp | 11 +- .../Target/PowerPC/PPCMachineFunctionInfo.h | 12 + llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 5 + ...b-tls-model-opt-small-local-dynamic-tls.ll | 74 +++ .../PowerPC/aix-shared-lib-tls-model-opt.ll | 627 ++++++++++++++++++ ...ix-shared-lib-tls-model-opt-IRattribute.ll | 21 + ...eck-aix-shared-lib-tls-model-opt-Option.ll | 22 + 13 files changed, 859 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/aix-shared-lib-tls-model-opt-small-local-dynamic-tls.ll create mode 100644 llvm/test/CodeGen/PowerPC/aix-shared-lib-tls-model-opt.ll create mode 100644 llvm/test/CodeGen/PowerPC/check-aix-shared-lib-tls-model-opt-IRattribute.ll create mode 100644 llvm/test/CodeGen/PowerPC/check-aix-shared-lib-tls-model-opt-Option.ll diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 322cc12af34a..142952897585 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -5077,6 +5077,10 @@ def maix_small_local_dynamic_tls : Flag<["-"], "maix-small-local-dynamic-tls">, "where the offset from the TLS base is encoded as an " "immediate operand (AIX 64-bit only). " "This access sequence is not used for variables larger than 32KB.">; +def maix_shared_lib_tls_model_opt : Flag<["-"], "maix-shared-lib-tls-model-opt">, + Group, + HelpText<"For shared library loaded with the main program, change local-dynamic access(es) " + "to initial-exec access(es) at the function level (AIX 64-bit only).">; def maix_struct_return : Flag<["-"], "maix-struct-return">, Group, Visibility<[ClangOption, CC1Option]>, HelpText<"Return all structs in memory (PPC32 only)">, diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index bad5259958a8..a1e5f20f7dbe 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -91,6 +91,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector &Features, IsISA3_1 = true; } else if (Feature == "+quadword-atomics") { HasQuadwordAtomics = true; + } else if (Feature == "+aix-shared-lib-tls-model-opt") { + HasAIXShLibTLSModelOpt = true; } // TODO: Finish this list and add an assert that we've handled them // all. @@ -580,6 +582,9 @@ bool PPCTargetInfo::initFeatureMap( Features["aix-small-local-exec-tls"] = false; Features["aix-small-local-dynamic-tls"] = false; + // Turn off TLS model opt by default. + Features["aix-shared-lib-tls-model-opt"] = false; + Features["spe"] = llvm::StringSwitch(CPU) .Case("8548", true) .Case("e500", true) @@ -722,6 +727,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const { .Case("isa-v30-instructions", IsISA3_0) .Case("isa-v31-instructions", IsISA3_1) .Case("quadword-atomics", HasQuadwordAtomics) + .Case("aix-shared-lib-tls-model-opt", HasAIXShLibTLSModelOpt) .Default(false); } diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h index 30059e418e69..496b6131d09b 100644 --- a/clang/lib/Basic/Targets/PPC.h +++ b/clang/lib/Basic/Targets/PPC.h @@ -81,6 +81,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { bool IsISA3_0 = false; bool IsISA3_1 = false; bool HasQuadwordAtomics = false; + bool HasAIXShLibTLSModelOpt = false; protected: std::string ABI; diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index b962ed28d720..639771ab9eab 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -338,6 +338,12 @@ def FeatureAIXLocalDynamicTLS : "true", "Produce a faster local-dynamic TLS sequence for this " "function for 64-bit AIX">; +def FeatureAIXSharedLibTLSModelOpt : + SubtargetFeature<"aix-shared-lib-tls-model-opt", + "HasAIXShLibTLSModelOpt", "true", + "Tune TLS model at function level in shared library loaded " + "with the main program (for 64-bit AIX only)">; + def FeaturePredictableSelectIsExpensive : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index a63824735490..ac48dc5af9d5 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -878,6 +878,15 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) { return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE; if (Model == TLSModel::InitialExec) return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE; + // On AIX, TLS model opt may have turned local-dynamic accesses into + // initial-exec accesses. + PPCFunctionInfo *FuncInfo = MF->getInfo(); + if (Model == TLSModel::LocalDynamic && + FuncInfo->isAIXFuncUseTLSIEForLD()) { + LLVM_DEBUG( + dbgs() << "Current function uses IE access for default LD vars.\n"); + return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE; + } llvm_unreachable("Only expecting local-exec or initial-exec accesses!"); } // For GD TLS access on AIX, we have two TOC entries for the symbol (one for @@ -2950,7 +2959,11 @@ void PPCAIXAsmPrinter::emitEndOfAsmFile(Module &M) { // Setup the csect for the current TC entry. If the variant kind is // VK_PPC_AIX_TLSGDM the entry represents the region handle, we create a // new symbol to prefix the name with a dot. - if (I.first.second == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM) { + // If TLS model opt is turned on, create a new symbol to prefix the name + // with a dot. + if (I.first.second == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM || + (Subtarget->hasAIXShLibTLSModelOpt() && + I.first.second == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLD)) { SmallString<128> Name; StringRef Prefix = "."; Name += Prefix; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index d27932f2915f..0a7483fc45b2 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -141,6 +141,11 @@ static cl::opt PPCGatherAllAliasesMaxDepth( "ppc-gather-alias-max-depth", cl::init(18), cl::Hidden, cl::desc("max depth when checking alias info in GatherAllAliases()")); +static cl::opt PPCAIXTLSModelOptUseIEForLDLimit( + "ppc-aix-shared-lib-tls-model-opt-limit", cl::init(1), cl::Hidden, + cl::desc("Set inclusive limit count of TLS local-dynamic access(es) in a " + "function to use initial-exec")); + STATISTIC(NumTailCalls, "Number of tail calls"); STATISTIC(NumSiblingCalls, "Number of sibling calls"); STATISTIC(ShufflesHandledWithVPERM, @@ -3362,6 +3367,54 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, return LowerGlobalTLSAddressLinux(Op, DAG); } +/// updateForAIXShLibTLSModelOpt - Helper to initialize TLS model opt settings, +/// and then apply the update. +static void updateForAIXShLibTLSModelOpt(TLSModel::Model &Model, + SelectionDAG &DAG, + const TargetMachine &TM) { + // Initialize TLS model opt setting lazily: + // (1) Use initial-exec for single TLS var references within current function. + // (2) Use local-dynamic for multiple TLS var references within current + // function. + PPCFunctionInfo *FuncInfo = + DAG.getMachineFunction().getInfo(); + if (!FuncInfo->isAIXFuncTLSModelOptInitDone()) { + SmallPtrSet TLSGV; + // Iterate over all instructions within current function, collect all TLS + // global variables (global variables taken as the first parameter to + // Intrinsic::threadlocal_address). + const Function &Func = DAG.getMachineFunction().getFunction(); + for (Function::const_iterator BI = Func.begin(), BE = Func.end(); BI != BE; + ++BI) + for (BasicBlock::const_iterator II = BI->begin(), IE = BI->end(); + II != IE; ++II) + if (II->getOpcode() == Instruction::Call) + if (const CallInst *CI = dyn_cast(&*II)) + if (Function *CF = CI->getCalledFunction()) + if (CF->isDeclaration() && + CF->getIntrinsicID() == Intrinsic::threadlocal_address) + if (const GlobalValue *GV = + dyn_cast(II->getOperand(0))) { + TLSModel::Model GVModel = TM.getTLSModel(GV); + if (GVModel == TLSModel::LocalDynamic) + TLSGV.insert(GV); + } + + unsigned TLSGVCnt = TLSGV.size(); + LLVM_DEBUG(dbgs() << format("LocalDynamic TLSGV count:%d\n", TLSGVCnt)); + if (TLSGVCnt <= PPCAIXTLSModelOptUseIEForLDLimit) + FuncInfo->setAIXFuncUseTLSIEForLD(); + FuncInfo->setAIXFuncTLSModelOptInitDone(); + } + + if (FuncInfo->isAIXFuncUseTLSIEForLD()) { + LLVM_DEBUG( + dbgs() << DAG.getMachineFunction().getName() + << " function is using the TLS-IE model for TLS-LD access.\n"); + Model = TLSModel::InitialExec; + } +} + SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op, SelectionDAG &DAG) const { GlobalAddressSDNode *GA = cast(Op); @@ -3374,6 +3427,11 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op, EVT PtrVT = getPointerTy(DAG.getDataLayout()); bool Is64Bit = Subtarget.isPPC64(); TLSModel::Model Model = getTargetMachine().getTLSModel(GV); + + // Apply update to the TLS model. + if (Subtarget.hasAIXShLibTLSModelOpt()) + updateForAIXShLibTLSModelOpt(Model, DAG, getTargetMachine()); + bool IsTLSLocalExecModel = Model == TLSModel::LocalExec; if (IsTLSLocalExecModel || Model == TLSModel::InitialExec) { diff --git a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp index c05bb37e58bf..31a261482358 100644 --- a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp +++ b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp @@ -13,6 +13,7 @@ #include "MCTargetDesc/PPCMCExpr.h" #include "PPC.h" +#include "PPCMachineFunctionInfo.h" #include "PPCSubtarget.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/Twine.h" @@ -81,6 +82,8 @@ static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol, } const TargetMachine &TM = Printer.TM; + const MachineInstr *MI = MO.getParent(); + const MachineFunction *MF = MI->getMF(); if (MO.getTargetFlags() == PPCII::MO_PLT) RefKind = MCSymbolRefExpr::VK_PLT; @@ -100,18 +103,22 @@ static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol, MO.getTargetFlags() == PPCII::MO_TLSLD_FLAG) { assert(MO.isGlobal() && "Only expecting a global MachineOperand here!"); TLSModel::Model Model = TM.getTLSModel(MO.getGlobal()); + const PPCFunctionInfo *FuncInfo = MF->getInfo(); // For the local-[exec|dynamic] TLS model, we may generate the offset from // the TLS base as an immediate operand (instead of using a TOC entry). Set // the relocation type in case the result is used for purposes other than a // TOC reference. In TOC reference cases, this result is discarded. if (Model == TLSModel::LocalExec) RefKind = MCSymbolRefExpr::VK_PPC_AIX_TLSLE; + else if (Model == TLSModel::LocalDynamic && + FuncInfo->isAIXFuncUseTLSIEForLD()) + // On AIX, TLS model opt may have turned local-dynamic accesses into + // initial-exec accesses. + RefKind = MCSymbolRefExpr::VK_PPC_AIX_TLSIE; else if (Model == TLSModel::LocalDynamic) RefKind = MCSymbolRefExpr::VK_PPC_AIX_TLSLD; } - const MachineInstr *MI = MO.getParent(); - const MachineFunction *MF = MI->getMF(); const Module *M = MF->getFunction().getParent(); const PPCSubtarget *Subtarget = &(MF->getSubtarget()); diff --git a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h index df655a3be951..b7d14da05ee2 100644 --- a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h +++ b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h @@ -150,6 +150,11 @@ private: /// to use SExt/ZExt flags in later optimization. std::vector> LiveInAttrs; + /// Flags for aix-shared-lib-tls-model-opt, will be lazily initialized for + /// each function. + bool AIXFuncUseTLSIEForLD = false; + bool AIXFuncTLSModelOptInitDone = false; + public: explicit PPCFunctionInfo(const Function &F, const TargetSubtargetInfo *STI); @@ -221,6 +226,13 @@ public: void setHasFastCall() { HasFastCall = true; } bool hasFastCall() const { return HasFastCall;} + void setAIXFuncTLSModelOptInitDone() { AIXFuncTLSModelOptInitDone = true; } + bool isAIXFuncTLSModelOptInitDone() const { + return AIXFuncTLSModelOptInitDone; + } + void setAIXFuncUseTLSIEForLD() { AIXFuncUseTLSIEForLD = true; } + bool isAIXFuncUseTLSIEForLD() const { return AIXFuncUseTLSIEForLD; } + int getVarArgsFrameIndex() const { return VarArgsFrameIndex; } void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp index d1722555f1fc..0628fbb26245 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -141,6 +141,11 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, "-data-sections.\n", false); } + + if (HasAIXShLibTLSModelOpt && (!TargetTriple.isOSAIX() || !IsPPC64)) + report_fatal_error("The aix-shared-lib-tls-model-opt attribute " + "is only supported on AIX in 64-bit mode.\n", + false); } bool PPCSubtarget::enableMachineScheduler() const { return true; } diff --git a/llvm/test/CodeGen/PowerPC/aix-shared-lib-tls-model-opt-small-local-dynamic-tls.ll b/llvm/test/CodeGen/PowerPC/aix-shared-lib-tls-model-opt-small-local-dynamic-tls.ll new file mode 100644 index 000000000000..cfb652ceeb8a --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-shared-lib-tls-model-opt-small-local-dynamic-tls.ll @@ -0,0 +1,74 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: -mattr=+aix-shared-lib-tls-model-opt --code-model=large < %s | FileCheck %s --check-prefixes=OPT +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: -mattr=+aix-small-local-dynamic-tls --code-model=large < %s | FileCheck %s --check-prefixes=SMALL +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: -mattr=+aix-shared-lib-tls-model-opt -mattr=+aix-small-local-dynamic-tls \ +; RUN: --code-model=large < %s | FileCheck %s --check-prefixes=BOTH + +@VarTLSLD1 = internal thread_local(localdynamic) global i32 42, align 4 + +define i32 @Single_LD(i32 %P, i32 %Q) { +; OPT-LABEL: Single_LD: +; OPT: # %bb.0: # %entry +; OPT-NEXT: and 4, 3, 4 +; OPT-NEXT: addis 3, L..C0@u(2) +; OPT-NEXT: ld 3, L..C0@l(3) +; OPT-NEXT: cmpwi 4, -1 +; OPT-NEXT: lwzx 3, 13, 3 +; OPT-NEXT: blr +; +; SMALL-LABEL: Single_LD: +; SMALL: # %bb.0: # %entry +; SMALL-NEXT: mflr 0 +; SMALL-NEXT: stdu 1, -48(1) +; SMALL-NEXT: and 6, 3, 4 +; SMALL-NEXT: addis 3, L..C0@u(2) +; SMALL-NEXT: std 0, 64(1) +; SMALL-NEXT: ld 3, L..C0@l(3) +; SMALL-NEXT: bla .__tls_get_mod[PR] +; SMALL-NEXT: cmpwi 6, -1 +; SMALL-NEXT: lwz 3, VarTLSLD1[TL]@ld(3) +; SMALL-NEXT: addi 1, 1, 48 +; SMALL-NEXT: ld 0, 16(1) +; SMALL-NEXT: mtlr 0 +; SMALL-NEXT: blr +; +; BOTH-LABEL: Single_LD: +; BOTH: # %bb.0: # %entry +; BOTH-NEXT: and 4, 3, 4 +; BOTH-NEXT: addis 3, L..C0@u(2) +; BOTH-NEXT: ld 3, L..C0@l(3) +; BOTH-NEXT: cmpwi 4, -1 +; BOTH-NEXT: lwzx 3, 13, 3 +; BOTH-NEXT: blr +entry: + %a = icmp slt i32 %P, 0 + %b = icmp slt i32 %Q, 0 + %c = and i1 %a, %b + %tls1 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @VarTLSLD1) + %load1 = load i32, ptr %tls1, align 4 + br i1 %c, label %bb1, label %return + +bb1: + %tls2 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @VarTLSLD1) + %load2 = load i32, ptr %tls2, align 4 + ret i32 %load2 + +return: + ret i32 %load1 +} + +; OPT-LABEL: .toc +; OPT-LABEL: L..C0: +; OPT-NEXT: .tc VarTLSLD1[TE],VarTLSLD1[TL]@ie + +; SMALL-LABEL: .toc +; SMALL-LABEL: L..C0: +; SMALL-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; SMALL-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" + +; BOTH-LABEL: .toc +; BOTH-LABEL: L..C0: +; BOTH-NEXT: .tc VarTLSLD1[TE],VarTLSLD1[TL]@ie diff --git a/llvm/test/CodeGen/PowerPC/aix-shared-lib-tls-model-opt.ll b/llvm/test/CodeGen/PowerPC/aix-shared-lib-tls-model-opt.ll new file mode 100644 index 000000000000..140377270d6d --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-shared-lib-tls-model-opt.ll @@ -0,0 +1,627 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: --code-model=small < %s | FileCheck %s --check-prefixes=DEFAULT_SMALL64 +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: --code-model=large < %s | FileCheck %s --check-prefixes=DEFAULT_LARGE64 +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: -mattr=+aix-shared-lib-tls-model-opt --code-model=small < %s | FileCheck %s --check-prefixes=TLS_MODEL_OPT_SMALL64 +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: -mattr=+aix-shared-lib-tls-model-opt --code-model=large < %s | FileCheck %s --check-prefixes=TLS_MODEL_OPT_LARGE64 +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: -mattr=+aix-shared-lib-tls-model-opt -ppc-aix-shared-lib-tls-model-opt-limit=2 \ +; RUN: --code-model=small < %s | FileCheck %s --check-prefixes=TLS_MODEL_OPT_LIMIT2_SMALL64 +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: -mattr=+aix-shared-lib-tls-model-opt -ppc-aix-shared-lib-tls-model-opt-limit=2 \ +; RUN: --code-model=large < %s | FileCheck %s --check-prefixes=TLS_MODEL_OPT_LIMIT2_LARGE64 +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: -mattr=+aix-shared-lib-tls-model-opt -ppc-aix-shared-lib-tls-model-opt-limit=3 \ +; RUN: --code-model=small < %s | FileCheck %s --check-prefixes=TLS_MODEL_OPT_LIMIT3_SMALL64 +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: -mattr=+aix-shared-lib-tls-model-opt -ppc-aix-shared-lib-tls-model-opt-limit=3 \ +; RUN: --code-model=large < %s | FileCheck %s --check-prefixes=TLS_MODEL_OPT_LIMIT3_LARGE64 + +@VarTLSLD1 = internal thread_local(localdynamic) global i32 42, align 4 +@VarTLSLD2 = internal thread_local(localdynamic) global i32 0, align 4 +@VarTLSLD3 = internal thread_local(localdynamic) global i32 0, align 4 + +; Tune function level TLS model settings: +; Use initial-exec when we have a function accessing only one TLS variable. +; Use local-dynamic when we have a function accessing a handful or more different TLS variables. + +define i32 @Single_LD(i32 %P, i32 %Q) { +; DEFAULT_SMALL64-LABEL: Single_LD: +; DEFAULT_SMALL64: # %bb.0: # %entry +; DEFAULT_SMALL64-NEXT: mflr 0 +; DEFAULT_SMALL64-NEXT: stdu 1, -48(1) +; DEFAULT_SMALL64-NEXT: and 6, 3, 4 +; DEFAULT_SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tlsldm) @"_$TLSML" +; DEFAULT_SMALL64-NEXT: std 0, 64(1) +; DEFAULT_SMALL64-NEXT: bla .__tls_get_mod[PR] +; DEFAULT_SMALL64-NEXT: ld 4, L..C1(2) # target-flags(ppc-tlsld) @VarTLSLD1 +; DEFAULT_SMALL64-NEXT: cmpwi 6, -1 +; DEFAULT_SMALL64-NEXT: lwzx 3, 3, 4 +; DEFAULT_SMALL64-NEXT: addi 1, 1, 48 +; DEFAULT_SMALL64-NEXT: ld 0, 16(1) +; DEFAULT_SMALL64-NEXT: mtlr 0 +; DEFAULT_SMALL64-NEXT: blr +; +; DEFAULT_LARGE64-LABEL: Single_LD: +; DEFAULT_LARGE64: # %bb.0: # %entry +; DEFAULT_LARGE64-NEXT: mflr 0 +; DEFAULT_LARGE64-NEXT: stdu 1, -48(1) +; DEFAULT_LARGE64-NEXT: and 6, 3, 4 +; DEFAULT_LARGE64-NEXT: addis 3, L..C0@u(2) +; DEFAULT_LARGE64-NEXT: addis 7, L..C1@u(2) +; DEFAULT_LARGE64-NEXT: ld 3, L..C0@l(3) +; DEFAULT_LARGE64-NEXT: std 0, 64(1) +; DEFAULT_LARGE64-NEXT: bla .__tls_get_mod[PR] +; DEFAULT_LARGE64-NEXT: ld 4, L..C1@l(7) +; DEFAULT_LARGE64-NEXT: lwzx 3, 3, 4 +; DEFAULT_LARGE64-NEXT: cmpwi 6, -1 +; DEFAULT_LARGE64-NEXT: addi 1, 1, 48 +; DEFAULT_LARGE64-NEXT: ld 0, 16(1) +; DEFAULT_LARGE64-NEXT: mtlr 0 +; DEFAULT_LARGE64-NEXT: blr +; +; TLS_MODEL_OPT_SMALL64-LABEL: Single_LD: +; TLS_MODEL_OPT_SMALL64: # %bb.0: # %entry +; TLS_MODEL_OPT_SMALL64-NEXT: and 4, 3, 4 +; TLS_MODEL_OPT_SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tprel) @VarTLSLD1 +; TLS_MODEL_OPT_SMALL64-NEXT: cmpwi 4, -1 +; TLS_MODEL_OPT_SMALL64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_SMALL64-NEXT: blr +; +; TLS_MODEL_OPT_LARGE64-LABEL: Single_LD: +; TLS_MODEL_OPT_LARGE64: # %bb.0: # %entry +; TLS_MODEL_OPT_LARGE64-NEXT: and 4, 3, 4 +; TLS_MODEL_OPT_LARGE64-NEXT: addis 3, L..C0@u(2) +; TLS_MODEL_OPT_LARGE64-NEXT: ld 3, L..C0@l(3) +; TLS_MODEL_OPT_LARGE64-NEXT: cmpwi 4, -1 +; TLS_MODEL_OPT_LARGE64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LARGE64-NEXT: blr +; +; TLS_MODEL_OPT_LIMIT2_SMALL64-LABEL: Single_LD: +; TLS_MODEL_OPT_LIMIT2_SMALL64: # %bb.0: # %entry +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: and 4, 3, 4 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tprel) @VarTLSLD1 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: cmpwi 4, -1 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: blr +; +; TLS_MODEL_OPT_LIMIT2_LARGE64-LABEL: Single_LD: +; TLS_MODEL_OPT_LIMIT2_LARGE64: # %bb.0: # %entry +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: and 4, 3, 4 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: addis 3, L..C0@u(2) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: ld 3, L..C0@l(3) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: cmpwi 4, -1 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: blr +; +; TLS_MODEL_OPT_LIMIT3_SMALL64-LABEL: Single_LD: +; TLS_MODEL_OPT_LIMIT3_SMALL64: # %bb.0: # %entry +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: and 4, 3, 4 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tprel) @VarTLSLD1 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: cmpwi 4, -1 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: blr +; +; TLS_MODEL_OPT_LIMIT3_LARGE64-LABEL: Single_LD: +; TLS_MODEL_OPT_LIMIT3_LARGE64: # %bb.0: # %entry +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: and 4, 3, 4 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: addis 3, L..C0@u(2) +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: ld 3, L..C0@l(3) +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: cmpwi 4, -1 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: blr +entry: + %a = icmp slt i32 %P, 0 + %b = icmp slt i32 %Q, 0 + %c = and i1 %a, %b + %tls1 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @VarTLSLD1) + %load1 = load i32, ptr %tls1, align 4 + br i1 %c, label %bb1, label %return + +bb1: + %tls2 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @VarTLSLD1) + %load2 = load i32, ptr %tls2, align 4 + ret i32 %load2 + +return: + ret i32 %load1 +} + +define i32 @Two_LDs(i32 %P, i32 %Q) { +; DEFAULT_SMALL64-LABEL: Two_LDs: +; DEFAULT_SMALL64: # %bb.0: # %entry +; DEFAULT_SMALL64-NEXT: mflr 0 +; DEFAULT_SMALL64-NEXT: stdu 1, -48(1) +; DEFAULT_SMALL64-NEXT: and 6, 3, 4 +; DEFAULT_SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tlsldm) @"_$TLSML" +; DEFAULT_SMALL64-NEXT: std 0, 64(1) +; DEFAULT_SMALL64-NEXT: bla .__tls_get_mod[PR] +; DEFAULT_SMALL64-NEXT: cmpwi 6, -1 +; DEFAULT_SMALL64-NEXT: bgt 0, L..BB1_2 +; DEFAULT_SMALL64-NEXT: # %bb.1: # %bb1 +; DEFAULT_SMALL64-NEXT: ld 4, L..C2(2) # target-flags(ppc-tlsld) @VarTLSLD2 +; DEFAULT_SMALL64-NEXT: lwzx 3, 3, 4 +; DEFAULT_SMALL64-NEXT: b L..BB1_3 +; DEFAULT_SMALL64-NEXT: L..BB1_2: # %return +; DEFAULT_SMALL64-NEXT: ld 4, L..C1(2) # target-flags(ppc-tlsld) @VarTLSLD1 +; DEFAULT_SMALL64-NEXT: lwzx 3, 3, 4 +; DEFAULT_SMALL64-NEXT: L..BB1_3: # %bb1 +; DEFAULT_SMALL64-NEXT: addi 1, 1, 48 +; DEFAULT_SMALL64-NEXT: ld 0, 16(1) +; DEFAULT_SMALL64-NEXT: mtlr 0 +; DEFAULT_SMALL64-NEXT: blr +; +; DEFAULT_LARGE64-LABEL: Two_LDs: +; DEFAULT_LARGE64: # %bb.0: # %entry +; DEFAULT_LARGE64-NEXT: mflr 0 +; DEFAULT_LARGE64-NEXT: stdu 1, -48(1) +; DEFAULT_LARGE64-NEXT: and 6, 3, 4 +; DEFAULT_LARGE64-NEXT: addis 3, L..C0@u(2) +; DEFAULT_LARGE64-NEXT: std 0, 64(1) +; DEFAULT_LARGE64-NEXT: ld 3, L..C0@l(3) +; DEFAULT_LARGE64-NEXT: bla .__tls_get_mod[PR] +; DEFAULT_LARGE64-NEXT: cmpwi 6, -1 +; DEFAULT_LARGE64-NEXT: bgt 0, L..BB1_2 +; DEFAULT_LARGE64-NEXT: # %bb.1: # %bb1 +; DEFAULT_LARGE64-NEXT: addis 4, L..C2@u(2) +; DEFAULT_LARGE64-NEXT: ld 4, L..C2@l(4) +; DEFAULT_LARGE64-NEXT: lwzx 3, 3, 4 +; DEFAULT_LARGE64-NEXT: b L..BB1_3 +; DEFAULT_LARGE64-NEXT: L..BB1_2: # %return +; DEFAULT_LARGE64-NEXT: addis 4, L..C1@u(2) +; DEFAULT_LARGE64-NEXT: ld 4, L..C1@l(4) +; DEFAULT_LARGE64-NEXT: lwzx 3, 3, 4 +; DEFAULT_LARGE64-NEXT: L..BB1_3: # %bb1 +; DEFAULT_LARGE64-NEXT: addi 1, 1, 48 +; DEFAULT_LARGE64-NEXT: ld 0, 16(1) +; DEFAULT_LARGE64-NEXT: mtlr 0 +; DEFAULT_LARGE64-NEXT: blr +; +; TLS_MODEL_OPT_SMALL64-LABEL: Two_LDs: +; TLS_MODEL_OPT_SMALL64: # %bb.0: # %entry +; TLS_MODEL_OPT_SMALL64-NEXT: mflr 0 +; TLS_MODEL_OPT_SMALL64-NEXT: stdu 1, -48(1) +; TLS_MODEL_OPT_SMALL64-NEXT: and 6, 3, 4 +; TLS_MODEL_OPT_SMALL64-NEXT: ld 3, L..C1(2) # target-flags(ppc-tlsldm) @"_$TLSML" +; TLS_MODEL_OPT_SMALL64-NEXT: std 0, 64(1) +; TLS_MODEL_OPT_SMALL64-NEXT: bla .__tls_get_mod[PR] +; TLS_MODEL_OPT_SMALL64-NEXT: cmpwi 6, -1 +; TLS_MODEL_OPT_SMALL64-NEXT: bgt 0, L..BB1_2 +; TLS_MODEL_OPT_SMALL64-NEXT: # %bb.1: # %bb1 +; TLS_MODEL_OPT_SMALL64-NEXT: ld 4, L..C2(2) # target-flags(ppc-tlsld) @VarTLSLD2 +; TLS_MODEL_OPT_SMALL64-NEXT: lwzx 3, 3, 4 +; TLS_MODEL_OPT_SMALL64-NEXT: b L..BB1_3 +; TLS_MODEL_OPT_SMALL64-NEXT: L..BB1_2: # %return +; TLS_MODEL_OPT_SMALL64-NEXT: ld 4, L..C3(2) # target-flags(ppc-tlsld) @VarTLSLD1 +; TLS_MODEL_OPT_SMALL64-NEXT: lwzx 3, 3, 4 +; TLS_MODEL_OPT_SMALL64-NEXT: L..BB1_3: # %bb1 +; TLS_MODEL_OPT_SMALL64-NEXT: addi 1, 1, 48 +; TLS_MODEL_OPT_SMALL64-NEXT: ld 0, 16(1) +; TLS_MODEL_OPT_SMALL64-NEXT: mtlr 0 +; TLS_MODEL_OPT_SMALL64-NEXT: blr +; +; TLS_MODEL_OPT_LARGE64-LABEL: Two_LDs: +; TLS_MODEL_OPT_LARGE64: # %bb.0: # %entry +; TLS_MODEL_OPT_LARGE64-NEXT: mflr 0 +; TLS_MODEL_OPT_LARGE64-NEXT: stdu 1, -48(1) +; TLS_MODEL_OPT_LARGE64-NEXT: and 6, 3, 4 +; TLS_MODEL_OPT_LARGE64-NEXT: addis 3, L..C1@u(2) +; TLS_MODEL_OPT_LARGE64-NEXT: std 0, 64(1) +; TLS_MODEL_OPT_LARGE64-NEXT: ld 3, L..C1@l(3) +; TLS_MODEL_OPT_LARGE64-NEXT: bla .__tls_get_mod[PR] +; TLS_MODEL_OPT_LARGE64-NEXT: cmpwi 6, -1 +; TLS_MODEL_OPT_LARGE64-NEXT: bgt 0, L..BB1_2 +; TLS_MODEL_OPT_LARGE64-NEXT: # %bb.1: # %bb1 +; TLS_MODEL_OPT_LARGE64-NEXT: addis 4, L..C2@u(2) +; TLS_MODEL_OPT_LARGE64-NEXT: ld 4, L..C2@l(4) +; TLS_MODEL_OPT_LARGE64-NEXT: lwzx 3, 3, 4 +; TLS_MODEL_OPT_LARGE64-NEXT: b L..BB1_3 +; TLS_MODEL_OPT_LARGE64-NEXT: L..BB1_2: # %return +; TLS_MODEL_OPT_LARGE64-NEXT: addis 4, L..C3@u(2) +; TLS_MODEL_OPT_LARGE64-NEXT: ld 4, L..C3@l(4) +; TLS_MODEL_OPT_LARGE64-NEXT: lwzx 3, 3, 4 +; TLS_MODEL_OPT_LARGE64-NEXT: L..BB1_3: # %bb1 +; TLS_MODEL_OPT_LARGE64-NEXT: addi 1, 1, 48 +; TLS_MODEL_OPT_LARGE64-NEXT: ld 0, 16(1) +; TLS_MODEL_OPT_LARGE64-NEXT: mtlr 0 +; TLS_MODEL_OPT_LARGE64-NEXT: blr +; +; TLS_MODEL_OPT_LIMIT2_SMALL64-LABEL: Two_LDs: +; TLS_MODEL_OPT_LIMIT2_SMALL64: # %bb.0: # %entry +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: and 3, 3, 4 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: cmpwi 3, -1 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: bgt 0, L..BB1_2 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: # %bb.1: # %bb1 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: ld 3, L..C1(2) # target-flags(ppc-tprel) @VarTLSLD2 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: blr +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: L..BB1_2: # %return +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tprel) @VarTLSLD1 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: blr +; +; TLS_MODEL_OPT_LIMIT2_LARGE64-LABEL: Two_LDs: +; TLS_MODEL_OPT_LIMIT2_LARGE64: # %bb.0: # %entry +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: and 3, 3, 4 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: cmpwi 3, -1 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: bgt 0, L..BB1_2 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: # %bb.1: # %bb1 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: addis 3, L..C1@u(2) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: ld 3, L..C1@l(3) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: blr +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: L..BB1_2: # %return +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: addis 3, L..C0@u(2) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: ld 3, L..C0@l(3) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: blr +; +; TLS_MODEL_OPT_LIMIT3_SMALL64-LABEL: Two_LDs: +; TLS_MODEL_OPT_LIMIT3_SMALL64: # %bb.0: # %entry +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: and 3, 3, 4 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: cmpwi 3, -1 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: bgt 0, L..BB1_2 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: # %bb.1: # %bb1 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: ld 3, L..C1(2) # target-flags(ppc-tprel) @VarTLSLD2 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: blr +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: L..BB1_2: # %return +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tprel) @VarTLSLD1 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: blr +; +; TLS_MODEL_OPT_LIMIT3_LARGE64-LABEL: Two_LDs: +; TLS_MODEL_OPT_LIMIT3_LARGE64: # %bb.0: # %entry +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: and 3, 3, 4 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: cmpwi 3, -1 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: bgt 0, L..BB1_2 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: # %bb.1: # %bb1 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: addis 3, L..C1@u(2) +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: ld 3, L..C1@l(3) +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: blr +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: L..BB1_2: # %return +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: addis 3, L..C0@u(2) +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: ld 3, L..C0@l(3) +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: blr +entry: + %a = icmp slt i32 %P, 0 + %b = icmp slt i32 %Q, 0 + %c = and i1 %a, %b + %tls1 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @VarTLSLD1) + %load1 = load i32, ptr %tls1, align 4 + br i1 %c, label %bb1, label %return + +bb1: + %tls2 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @VarTLSLD2) + %load2 = load i32, ptr %tls2, align 4 + ret i32 %load2 + +return: + ret i32 %load1 +} + +define i32 @Three_LDs(i32 %P, i32 %Q) { +; DEFAULT_SMALL64-LABEL: Three_LDs: +; DEFAULT_SMALL64: # %bb.0: # %entry +; DEFAULT_SMALL64-NEXT: mflr 0 +; DEFAULT_SMALL64-NEXT: stdu 1, -48(1) +; DEFAULT_SMALL64-NEXT: and 6, 3, 4 +; DEFAULT_SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tlsldm) @"_$TLSML" +; DEFAULT_SMALL64-NEXT: std 0, 64(1) +; DEFAULT_SMALL64-NEXT: bla .__tls_get_mod[PR] +; DEFAULT_SMALL64-NEXT: cmpwi 6, -1 +; DEFAULT_SMALL64-NEXT: bgt 0, L..BB2_2 +; DEFAULT_SMALL64-NEXT: # %bb.1: # %bb1 +; DEFAULT_SMALL64-NEXT: ld 4, L..C2(2) # target-flags(ppc-tlsld) @VarTLSLD2 +; DEFAULT_SMALL64-NEXT: ld 5, L..C3(2) # target-flags(ppc-tlsld) @VarTLSLD3 +; DEFAULT_SMALL64-NEXT: lwzx 4, 3, 4 +; DEFAULT_SMALL64-NEXT: lwzx 3, 3, 5 +; DEFAULT_SMALL64-NEXT: add 3, 4, 3 +; DEFAULT_SMALL64-NEXT: b L..BB2_3 +; DEFAULT_SMALL64-NEXT: L..BB2_2: # %return +; DEFAULT_SMALL64-NEXT: ld 4, L..C1(2) # target-flags(ppc-tlsld) @VarTLSLD1 +; DEFAULT_SMALL64-NEXT: lwzx 3, 3, 4 +; DEFAULT_SMALL64-NEXT: L..BB2_3: # %return +; DEFAULT_SMALL64-NEXT: addi 1, 1, 48 +; DEFAULT_SMALL64-NEXT: ld 0, 16(1) +; DEFAULT_SMALL64-NEXT: mtlr 0 +; DEFAULT_SMALL64-NEXT: blr +; +; DEFAULT_LARGE64-LABEL: Three_LDs: +; DEFAULT_LARGE64: # %bb.0: # %entry +; DEFAULT_LARGE64-NEXT: mflr 0 +; DEFAULT_LARGE64-NEXT: stdu 1, -48(1) +; DEFAULT_LARGE64-NEXT: and 6, 3, 4 +; DEFAULT_LARGE64-NEXT: addis 3, L..C0@u(2) +; DEFAULT_LARGE64-NEXT: std 0, 64(1) +; DEFAULT_LARGE64-NEXT: ld 3, L..C0@l(3) +; DEFAULT_LARGE64-NEXT: bla .__tls_get_mod[PR] +; DEFAULT_LARGE64-NEXT: cmpwi 6, -1 +; DEFAULT_LARGE64-NEXT: bgt 0, L..BB2_2 +; DEFAULT_LARGE64-NEXT: # %bb.1: # %bb1 +; DEFAULT_LARGE64-NEXT: addis 4, L..C2@u(2) +; DEFAULT_LARGE64-NEXT: addis 5, L..C3@u(2) +; DEFAULT_LARGE64-NEXT: ld 4, L..C2@l(4) +; DEFAULT_LARGE64-NEXT: ld 5, L..C3@l(5) +; DEFAULT_LARGE64-NEXT: lwzx 4, 3, 4 +; DEFAULT_LARGE64-NEXT: lwzx 3, 3, 5 +; DEFAULT_LARGE64-NEXT: add 3, 4, 3 +; DEFAULT_LARGE64-NEXT: b L..BB2_3 +; DEFAULT_LARGE64-NEXT: L..BB2_2: # %return +; DEFAULT_LARGE64-NEXT: addis 4, L..C1@u(2) +; DEFAULT_LARGE64-NEXT: ld 4, L..C1@l(4) +; DEFAULT_LARGE64-NEXT: lwzx 3, 3, 4 +; DEFAULT_LARGE64-NEXT: L..BB2_3: # %return +; DEFAULT_LARGE64-NEXT: addi 1, 1, 48 +; DEFAULT_LARGE64-NEXT: ld 0, 16(1) +; DEFAULT_LARGE64-NEXT: mtlr 0 +; DEFAULT_LARGE64-NEXT: blr +; +; TLS_MODEL_OPT_SMALL64-LABEL: Three_LDs: +; TLS_MODEL_OPT_SMALL64: # %bb.0: # %entry +; TLS_MODEL_OPT_SMALL64-NEXT: mflr 0 +; TLS_MODEL_OPT_SMALL64-NEXT: stdu 1, -48(1) +; TLS_MODEL_OPT_SMALL64-NEXT: and 6, 3, 4 +; TLS_MODEL_OPT_SMALL64-NEXT: ld 3, L..C1(2) # target-flags(ppc-tlsldm) @"_$TLSML" +; TLS_MODEL_OPT_SMALL64-NEXT: std 0, 64(1) +; TLS_MODEL_OPT_SMALL64-NEXT: bla .__tls_get_mod[PR] +; TLS_MODEL_OPT_SMALL64-NEXT: cmpwi 6, -1 +; TLS_MODEL_OPT_SMALL64-NEXT: bgt 0, L..BB2_2 +; TLS_MODEL_OPT_SMALL64-NEXT: # %bb.1: # %bb1 +; TLS_MODEL_OPT_SMALL64-NEXT: ld 4, L..C2(2) # target-flags(ppc-tlsld) @VarTLSLD2 +; TLS_MODEL_OPT_SMALL64-NEXT: ld 5, L..C4(2) # target-flags(ppc-tlsld) @VarTLSLD3 +; TLS_MODEL_OPT_SMALL64-NEXT: lwzx 4, 3, 4 +; TLS_MODEL_OPT_SMALL64-NEXT: lwzx 3, 3, 5 +; TLS_MODEL_OPT_SMALL64-NEXT: add 3, 4, 3 +; TLS_MODEL_OPT_SMALL64-NEXT: b L..BB2_3 +; TLS_MODEL_OPT_SMALL64-NEXT: L..BB2_2: # %return +; TLS_MODEL_OPT_SMALL64-NEXT: ld 4, L..C3(2) # target-flags(ppc-tlsld) @VarTLSLD1 +; TLS_MODEL_OPT_SMALL64-NEXT: lwzx 3, 3, 4 +; TLS_MODEL_OPT_SMALL64-NEXT: L..BB2_3: # %return +; TLS_MODEL_OPT_SMALL64-NEXT: addi 1, 1, 48 +; TLS_MODEL_OPT_SMALL64-NEXT: ld 0, 16(1) +; TLS_MODEL_OPT_SMALL64-NEXT: mtlr 0 +; TLS_MODEL_OPT_SMALL64-NEXT: blr +; +; TLS_MODEL_OPT_LARGE64-LABEL: Three_LDs: +; TLS_MODEL_OPT_LARGE64: # %bb.0: # %entry +; TLS_MODEL_OPT_LARGE64-NEXT: mflr 0 +; TLS_MODEL_OPT_LARGE64-NEXT: stdu 1, -48(1) +; TLS_MODEL_OPT_LARGE64-NEXT: and 6, 3, 4 +; TLS_MODEL_OPT_LARGE64-NEXT: addis 3, L..C1@u(2) +; TLS_MODEL_OPT_LARGE64-NEXT: std 0, 64(1) +; TLS_MODEL_OPT_LARGE64-NEXT: ld 3, L..C1@l(3) +; TLS_MODEL_OPT_LARGE64-NEXT: bla .__tls_get_mod[PR] +; TLS_MODEL_OPT_LARGE64-NEXT: cmpwi 6, -1 +; TLS_MODEL_OPT_LARGE64-NEXT: bgt 0, L..BB2_2 +; TLS_MODEL_OPT_LARGE64-NEXT: # %bb.1: # %bb1 +; TLS_MODEL_OPT_LARGE64-NEXT: addis 4, L..C2@u(2) +; TLS_MODEL_OPT_LARGE64-NEXT: addis 5, L..C4@u(2) +; TLS_MODEL_OPT_LARGE64-NEXT: ld 4, L..C2@l(4) +; TLS_MODEL_OPT_LARGE64-NEXT: ld 5, L..C4@l(5) +; TLS_MODEL_OPT_LARGE64-NEXT: lwzx 4, 3, 4 +; TLS_MODEL_OPT_LARGE64-NEXT: lwzx 3, 3, 5 +; TLS_MODEL_OPT_LARGE64-NEXT: add 3, 4, 3 +; TLS_MODEL_OPT_LARGE64-NEXT: b L..BB2_3 +; TLS_MODEL_OPT_LARGE64-NEXT: L..BB2_2: # %return +; TLS_MODEL_OPT_LARGE64-NEXT: addis 4, L..C3@u(2) +; TLS_MODEL_OPT_LARGE64-NEXT: ld 4, L..C3@l(4) +; TLS_MODEL_OPT_LARGE64-NEXT: lwzx 3, 3, 4 +; TLS_MODEL_OPT_LARGE64-NEXT: L..BB2_3: # %return +; TLS_MODEL_OPT_LARGE64-NEXT: addi 1, 1, 48 +; TLS_MODEL_OPT_LARGE64-NEXT: ld 0, 16(1) +; TLS_MODEL_OPT_LARGE64-NEXT: mtlr 0 +; TLS_MODEL_OPT_LARGE64-NEXT: blr +; +; TLS_MODEL_OPT_LIMIT2_SMALL64-LABEL: Three_LDs: +; TLS_MODEL_OPT_LIMIT2_SMALL64: # %bb.0: # %entry +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: mflr 0 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: stdu 1, -48(1) +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: and 6, 3, 4 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-tlsldm) @"_$TLSML" +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: std 0, 64(1) +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: bla .__tls_get_mod[PR] +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: cmpwi 6, -1 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: bgt 0, L..BB2_2 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: # %bb.1: # %bb1 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: ld 4, L..C3(2) # target-flags(ppc-tlsld) @VarTLSLD2 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: ld 5, L..C4(2) # target-flags(ppc-tlsld) @VarTLSLD3 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: lwzx 4, 3, 4 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: lwzx 3, 3, 5 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: add 3, 4, 3 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: b L..BB2_3 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: L..BB2_2: # %return +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: ld 4, L..C5(2) # target-flags(ppc-tlsld) @VarTLSLD1 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: lwzx 3, 3, 4 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: L..BB2_3: # %return +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: addi 1, 1, 48 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: ld 0, 16(1) +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: mtlr 0 +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: blr +; +; TLS_MODEL_OPT_LIMIT2_LARGE64-LABEL: Three_LDs: +; TLS_MODEL_OPT_LIMIT2_LARGE64: # %bb.0: # %entry +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: mflr 0 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: stdu 1, -48(1) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: and 6, 3, 4 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: addis 3, L..C2@u(2) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: std 0, 64(1) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: ld 3, L..C2@l(3) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: bla .__tls_get_mod[PR] +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: cmpwi 6, -1 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: bgt 0, L..BB2_2 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: # %bb.1: # %bb1 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: addis 4, L..C3@u(2) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: addis 5, L..C4@u(2) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: ld 4, L..C3@l(4) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: ld 5, L..C4@l(5) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: lwzx 4, 3, 4 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: lwzx 3, 3, 5 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: add 3, 4, 3 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: b L..BB2_3 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: L..BB2_2: # %return +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: addis 4, L..C5@u(2) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: ld 4, L..C5@l(4) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: lwzx 3, 3, 4 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: L..BB2_3: # %return +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: addi 1, 1, 48 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: ld 0, 16(1) +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: mtlr 0 +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: blr +; +; TLS_MODEL_OPT_LIMIT3_SMALL64-LABEL: Three_LDs: +; TLS_MODEL_OPT_LIMIT3_SMALL64: # %bb.0: # %entry +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: and 3, 3, 4 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: cmpwi 3, -1 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: bgt 0, L..BB2_2 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: # %bb.1: # %bb1 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: ld 3, L..C1(2) # target-flags(ppc-tprel) @VarTLSLD2 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: ld 4, L..C2(2) # target-flags(ppc-tprel) @VarTLSLD3 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: lwzx 4, 13, 4 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: add 3, 3, 4 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: blr +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: L..BB2_2: # %return +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tprel) @VarTLSLD1 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: blr +; +; TLS_MODEL_OPT_LIMIT3_LARGE64-LABEL: Three_LDs: +; TLS_MODEL_OPT_LIMIT3_LARGE64: # %bb.0: # %entry +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: and 3, 3, 4 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: cmpwi 3, -1 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: bgt 0, L..BB2_2 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: # %bb.1: # %bb1 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: addis 3, L..C1@u(2) +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: addis 4, L..C2@u(2) +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: ld 3, L..C1@l(3) +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: ld 4, L..C2@l(4) +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: lwzx 4, 13, 4 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: add 3, 3, 4 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: blr +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: L..BB2_2: # %return +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: addis 3, L..C0@u(2) +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: ld 3, L..C0@l(3) +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: lwzx 3, 13, 3 +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: blr +entry: + %a = icmp slt i32 %P, 0 + %b = icmp slt i32 %Q, 0 + %c = and i1 %a, %b + %tls1 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @VarTLSLD1) + %load1 = load i32, ptr %tls1, align 4 + br i1 %c, label %bb1, label %return + +bb1: + %tls2 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @VarTLSLD2) + %load2 = load i32, ptr %tls2, align 4 + %tls3 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @VarTLSLD3) + %load3 = load i32, ptr %tls3, align 4 + %sum = add i32 %load2, %load3 + ret i32 %sum + +return: + ret i32 %load1 +} + +declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) + +; DEFAULT_SMALL64-LABEL: .toc +; DEFAULT_SMALL64-LABEL: L..C0: +; DEFAULT_SMALL64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; DEFAULT_SMALL64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" +; DEFAULT_SMALL64-LABEL: L..C1: +; DEFAULT_SMALL64-NEXT: .tc VarTLSLD1[TC],VarTLSLD1[TL]@ld +; DEFAULT_SMALL64-LABEL: L..C2: +; DEFAULT_SMALL64-NEXT: .tc VarTLSLD2[TC],VarTLSLD2[UL]@ld +; DEFAULT_SMALL64-LABEL: L..C3: +; DEFAULT_SMALL64-NEXT: .tc VarTLSLD3[TC],VarTLSLD3[UL]@ld + +; DEFAULT_LARGE64-LABEL: .toc +; DEFAULT_LARGE64-LABEL: L..C0: +; DEFAULT_LARGE64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; DEFAULT_LARGE64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" +; DEFAULT_LARGE64-LABEL: L..C1: +; DEFAULT_LARGE64-NEXT: .tc VarTLSLD1[TE],VarTLSLD1[TL]@ld +; DEFAULT_LARGE64-LABEL: L..C2: +; DEFAULT_LARGE64-NEXT: .tc VarTLSLD2[TE],VarTLSLD2[UL]@ld +; DEFAULT_LARGE64-LABEL: L..C3: +; DEFAULT_LARGE64-NEXT: .tc VarTLSLD3[TE],VarTLSLD3[UL]@ld + +; TLS_MODEL_OPT_SMALL64-LABEL: .toc +; TLS_MODEL_OPT_SMALL64-LABEL: L..C0: +; TLS_MODEL_OPT_SMALL64-NEXT: .tc VarTLSLD1[TC],VarTLSLD1[TL]@ie +; TLS_MODEL_OPT_SMALL64-LABEL: L..C1: +; TLS_MODEL_OPT_SMALL64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; TLS_MODEL_OPT_SMALL64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" +; TLS_MODEL_OPT_SMALL64-LABEL: L..C2: +; TLS_MODEL_OPT_SMALL64-NEXT: .tc .VarTLSLD2[TC],VarTLSLD2[UL]@ld +; TLS_MODEL_OPT_SMALL64-LABEL: L..C3: +; TLS_MODEL_OPT_SMALL64-NEXT: .tc .VarTLSLD1[TC],VarTLSLD1[TL]@ld +; TLS_MODEL_OPT_SMALL64-LABEL: L..C4: +; TLS_MODEL_OPT_SMALL64-NEXT: .tc .VarTLSLD3[TC],VarTLSLD3[UL]@ld + +; TLS_MODEL_OPT_LARGE64-LABEL: .toc +; TLS_MODEL_OPT_LARGE64-LABEL: L..C0: +; TLS_MODEL_OPT_LARGE64-NEXT: .tc VarTLSLD1[TE],VarTLSLD1[TL]@ie +; TLS_MODEL_OPT_LARGE64-LABEL: L..C1: +; TLS_MODEL_OPT_LARGE64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; TLS_MODEL_OPT_LARGE64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" +; TLS_MODEL_OPT_LARGE64-LABEL: L..C2: +; TLS_MODEL_OPT_LARGE64-NEXT: .tc .VarTLSLD2[TE],VarTLSLD2[UL]@ld +; TLS_MODEL_OPT_LARGE64-LABEL: L..C3: +; TLS_MODEL_OPT_LARGE64-NEXT: .tc .VarTLSLD1[TE],VarTLSLD1[TL]@ld +; TLS_MODEL_OPT_LARGE64-LABEL: L..C4: +; TLS_MODEL_OPT_LARGE64-NEXT: .tc .VarTLSLD3[TE],VarTLSLD3[UL]@ld + +; TLS_MODEL_OPT_LIMIT2_SMALL64-LABEL: .toc +; TLS_MODEL_OPT_LIMIT2_SMALL64-LABEL: L..C0: +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: .tc VarTLSLD1[TC],VarTLSLD1[TL]@ie +; TLS_MODEL_OPT_LIMIT2_SMALL64-LABEL: L..C1: +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: .tc VarTLSLD2[TC],VarTLSLD2[UL]@ie +; TLS_MODEL_OPT_LIMIT2_SMALL64-LABEL: L..C2: +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" +; TLS_MODEL_OPT_LIMIT2_SMALL64-LABEL: L..C3: +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: .tc .VarTLSLD2[TC],VarTLSLD2[UL]@ld +; TLS_MODEL_OPT_LIMIT2_SMALL64-LABEL: L..C4: +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: .tc .VarTLSLD3[TC],VarTLSLD3[UL]@ld +; TLS_MODEL_OPT_LIMIT2_SMALL64-LABEL: L..C5: +; TLS_MODEL_OPT_LIMIT2_SMALL64-NEXT: .tc .VarTLSLD1[TC],VarTLSLD1[TL]@ld + +; TLS_MODEL_OPT_LIMIT2_LARGE64-LABEL: .toc +; TLS_MODEL_OPT_LIMIT2_LARGE64-LABEL: L..C0: +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: .tc VarTLSLD1[TE],VarTLSLD1[TL]@ie +; TLS_MODEL_OPT_LIMIT2_LARGE64-LABEL: L..C1: +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: .tc VarTLSLD2[TE],VarTLSLD2[UL]@ie +; TLS_MODEL_OPT_LIMIT2_LARGE64-LABEL: L..C2: +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" +; TLS_MODEL_OPT_LIMIT2_LARGE64-LABEL: L..C3: +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: .tc .VarTLSLD2[TE],VarTLSLD2[UL]@ld +; TLS_MODEL_OPT_LIMIT2_LARGE64-LABEL: L..C4: +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: .tc .VarTLSLD3[TE],VarTLSLD3[UL]@ld +; TLS_MODEL_OPT_LIMIT2_LARGE64-LABEL: L..C5: +; TLS_MODEL_OPT_LIMIT2_LARGE64-NEXT: .tc .VarTLSLD1[TE],VarTLSLD1[TL]@ld + +; TLS_MODEL_OPT_LIMIT3_SMALL64-LABEL: .toc +; TLS_MODEL_OPT_LIMIT3_SMALL64-LABEL: L..C0: +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: .tc VarTLSLD1[TC],VarTLSLD1[TL]@ie +; TLS_MODEL_OPT_LIMIT3_SMALL64-LABEL: L..C1: +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: .tc VarTLSLD2[TC],VarTLSLD2[UL]@ie +; TLS_MODEL_OPT_LIMIT3_SMALL64-LABEL: L..C2: +; TLS_MODEL_OPT_LIMIT3_SMALL64-NEXT: .tc VarTLSLD3[TC],VarTLSLD3[UL]@ie + +; TLS_MODEL_OPT_LIMIT3_LARGE64-LABEL: .toc +; TLS_MODEL_OPT_LIMIT3_LARGE64-LABEL: L..C0: +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: .tc VarTLSLD1[TE],VarTLSLD1[TL]@ie +; TLS_MODEL_OPT_LIMIT3_LARGE64-LABEL: L..C1: +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: .tc VarTLSLD2[TE],VarTLSLD2[UL]@ie +; TLS_MODEL_OPT_LIMIT3_LARGE64-LABEL: L..C2: +; TLS_MODEL_OPT_LIMIT3_LARGE64-NEXT: .tc VarTLSLD3[TE],VarTLSLD3[UL]@ie diff --git a/llvm/test/CodeGen/PowerPC/check-aix-shared-lib-tls-model-opt-IRattribute.ll b/llvm/test/CodeGen/PowerPC/check-aix-shared-lib-tls-model-opt-IRattribute.ll new file mode 100644 index 000000000000..15fac2d0c0ad --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/check-aix-shared-lib-tls-model-opt-IRattribute.ll @@ -0,0 +1,21 @@ +; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -ppc-asm-full-reg-names \ +; RUN: < %s | FileCheck %s +; RUN: not llc -mtriple powerpc-ibm-aix-xcoff -ppc-asm-full-reg-names \ +; RUN: < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOT-SUPPORTED +; RUN: not llc -mtriple powerpc64le-unknown-linux-gnu -ppc-asm-full-reg-names \ +; RUN: < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOT-SUPPORTED + +define dso_local signext i32 @testWithIRAttr() #0 { +entry: + ret i32 0 +} +; Check that the aix-shared-lib-tls-model-opt attribute is not supported on Linux and AIX (32-bit). +; CHECK-NOT-SUPPORTED: The aix-shared-lib-tls-model-opt attribute is only supported on AIX in 64-bit mode. + +; Make sure that the test was actually compiled successfully after using the +; aix-shared-lib-tls-model-opt attribute. +; CHECK-LABEL: testWithIRAttr: +; CHECK: li r3, 0 +; CHECK-NEXT: blr + +attributes #0 = { "target-features"="+aix-shared-lib-tls-model-opt" } diff --git a/llvm/test/CodeGen/PowerPC/check-aix-shared-lib-tls-model-opt-Option.ll b/llvm/test/CodeGen/PowerPC/check-aix-shared-lib-tls-model-opt-Option.ll new file mode 100644 index 000000000000..36f8bc78c77a --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/check-aix-shared-lib-tls-model-opt-Option.ll @@ -0,0 +1,22 @@ +; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mattr=+aix-shared-lib-tls-model-opt \ +; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s +; RUN: not llc -mtriple powerpc-ibm-aix-xcoff -mattr=+aix-shared-lib-tls-model-opt \ +; RUN: -ppc-asm-full-reg-names < %s 2>&1 | \ +; RUN: FileCheck %s --check-prefix=CHECK-NOT-SUPPORTED +; RUN: not llc -mtriple powerpc64le-unknown-linux-gnu -mattr=+aix-shared-lib-tls-model-opt \ +; RUN: -ppc-asm-full-reg-names < %s 2>&1 | \ +; RUN: FileCheck %s --check-prefix=CHECK-NOT-SUPPORTED + +define dso_local signext i32 @testNoIRAttr() { +entry: + ret i32 0 +} + +; Check that the aix-shared-lib-tls-model-opt attribute is not supported on Linux and AIX (32-bit). +; CHECK-NOT-SUPPORTED: The aix-shared-lib-tls-model-opt attribute is only supported on AIX in 64-bit mode. + +; Make sure that the test was actually compiled successfully after using the +; aix-shared-lib-tls-model-opt attribute. +; CHECK-LABEL: testNoIRAttr: +; CHECK: li r3, 0 +; CHECK-NEXT: blr -- GitLab From b910bebc300dafb30569cecc3017b446ea8eafa0 Mon Sep 17 00:00:00 2001 From: Zixu Wang <9819235+zixu-w@users.noreply.github.com> Date: Wed, 8 May 2024 18:53:15 -0700 Subject: [PATCH 097/328] [llvm][MachO] Fix integer truncation in rebase/bind parsing (#89337) `Count` and `Skip` should use `uint64_t` as they are encoded/decoded using 64-bit ULEB128. In `*_OPCODE_DO_*_ULEB_TIMES_SKIPPING_ULEB`, `Skip` could be encoded as a two's complement for moving `SegmentOffset` backwards. Having a 32-bit `Skip` truncates the encoded value and leads to a malformed `AdvanceAmount` and invalid `SegmentOffset` that extends past valid sections. --- llvm/include/llvm/Object/MachO.h | 15 +- llvm/lib/Object/MachOObjectFile.cpp | 20 +- .../Inputs/MachO/bind-negative-skip.yaml | 499 ++++++++++++++++++ .../test/Object/macho-bind-negative-skip.test | 17 + 4 files changed, 534 insertions(+), 17 deletions(-) create mode 100644 llvm/test/Object/Inputs/MachO/bind-negative-skip.yaml create mode 100644 llvm/test/Object/macho-bind-negative-skip.test diff --git a/llvm/include/llvm/Object/MachO.h b/llvm/include/llvm/Object/MachO.h index 24f9954584ed..35350df78f8d 100644 --- a/llvm/include/llvm/Object/MachO.h +++ b/llvm/include/llvm/Object/MachO.h @@ -134,9 +134,9 @@ public: BindRebaseSegInfo(const MachOObjectFile *Obj); // Used to check a Mach-O Bind or Rebase entry for errors when iterating. - const char* checkSegAndOffsets(int32_t SegIndex, uint64_t SegOffset, - uint8_t PointerSize, uint32_t Count=1, - uint32_t Skip=0); + const char *checkSegAndOffsets(int32_t SegIndex, uint64_t SegOffset, + uint8_t PointerSize, uint64_t Count = 1, + uint64_t Skip = 0); // Used with valid SegIndex/SegOffset values from checked entries. StringRef segmentName(int32_t SegIndex); StringRef sectionName(int32_t SegIndex, uint64_t SegOffset); @@ -576,8 +576,9 @@ public: // // This is used by MachOBindEntry::moveNext() to validate a MachOBindEntry. const char *BindEntryCheckSegAndOffsets(int32_t SegIndex, uint64_t SegOffset, - uint8_t PointerSize, uint32_t Count=1, - uint32_t Skip=0) const { + uint8_t PointerSize, + uint64_t Count = 1, + uint64_t Skip = 0) const { return BindRebaseSectionTable->checkSegAndOffsets(SegIndex, SegOffset, PointerSize, Count, Skip); } @@ -591,8 +592,8 @@ public: const char *RebaseEntryCheckSegAndOffsets(int32_t SegIndex, uint64_t SegOffset, uint8_t PointerSize, - uint32_t Count=1, - uint32_t Skip=0) const { + uint64_t Count = 1, + uint64_t Skip = 0) const { return BindRebaseSectionTable->checkSegAndOffsets(SegIndex, SegOffset, PointerSize, Count, Skip); } diff --git a/llvm/lib/Object/MachOObjectFile.cpp b/llvm/lib/Object/MachOObjectFile.cpp index 06186ad362aa..ef390ceca218 100644 --- a/llvm/lib/Object/MachOObjectFile.cpp +++ b/llvm/lib/Object/MachOObjectFile.cpp @@ -3515,7 +3515,7 @@ void MachORebaseEntry::moveNext() { uint8_t Byte = *Ptr++; uint8_t ImmValue = Byte & MachO::REBASE_IMMEDIATE_MASK; uint8_t Opcode = Byte & MachO::REBASE_OPCODE_MASK; - uint32_t Count, Skip; + uint64_t Count, Skip; const char *error = nullptr; switch (Opcode) { case MachO::REBASE_OPCODE_DONE: @@ -3854,7 +3854,7 @@ void MachOBindEntry::moveNext() { uint8_t Opcode = Byte & MachO::BIND_OPCODE_MASK; int8_t SignExtended; const uint8_t *SymStart; - uint32_t Count, Skip; + uint64_t Count, Skip; const char *error = nullptr; switch (Opcode) { case MachO::BIND_OPCODE_DONE: @@ -4384,18 +4384,18 @@ BindRebaseSegInfo::BindRebaseSegInfo(const object::MachOObjectFile *Obj) { // that fully contains a pointer at that location. Multiple fixups in a bind // (such as with the BIND_OPCODE_DO_BIND_ULEB_TIMES_SKIPPING_ULEB opcode) can // be tested via the Count and Skip parameters. -const char * BindRebaseSegInfo::checkSegAndOffsets(int32_t SegIndex, - uint64_t SegOffset, - uint8_t PointerSize, - uint32_t Count, - uint32_t Skip) { +const char *BindRebaseSegInfo::checkSegAndOffsets(int32_t SegIndex, + uint64_t SegOffset, + uint8_t PointerSize, + uint64_t Count, + uint64_t Skip) { if (SegIndex == -1) return "missing preceding *_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB"; if (SegIndex >= MaxSegIndex) return "bad segIndex (too large)"; - for (uint32_t i = 0; i < Count; ++i) { - uint32_t Start = SegOffset + i * (PointerSize + Skip); - uint32_t End = Start + PointerSize; + for (uint64_t i = 0; i < Count; ++i) { + uint64_t Start = SegOffset + i * (PointerSize + Skip); + uint64_t End = Start + PointerSize; bool Found = false; for (const SectionInfo &SI : Sections) { if (SI.SegmentIndex != SegIndex) diff --git a/llvm/test/Object/Inputs/MachO/bind-negative-skip.yaml b/llvm/test/Object/Inputs/MachO/bind-negative-skip.yaml new file mode 100644 index 000000000000..aef5664a798f --- /dev/null +++ b/llvm/test/Object/Inputs/MachO/bind-negative-skip.yaml @@ -0,0 +1,499 @@ +--- !mach-o +FileHeader: + magic: 0xFEEDFACF + cputype: 0x100000C + cpusubtype: 0x0 + filetype: 0x2 + ncmds: 17 + sizeofcmds: 1384 + flags: 0x200085 + reserved: 0x0 +LoadCommands: + - cmd: LC_SEGMENT_64 + cmdsize: 72 + segname: __PAGEZERO + vmaddr: 0 + vmsize: 4294967296 + fileoff: 0 + filesize: 0 + maxprot: 0 + initprot: 0 + nsects: 0 + flags: 0 + - cmd: LC_SEGMENT_64 + cmdsize: 472 + segname: __TEXT + vmaddr: 4294967296 + vmsize: 16384 + fileoff: 0 + filesize: 16384 + maxprot: 5 + initprot: 5 + nsects: 5 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x100003E58 + size: 228 + offset: 0x3E58 + align: 2 + reloff: 0x0 + nreloc: 0 + flags: 0x80000400 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: FF8300D1FD7B01A9FD430091E9030091080000B0080540F9280100F90000009000B03D9130000094E9030091080000B0080140F9280100F90000009000E03D9129000094280000B0080940F9E9030091280100F90000009000083E9122000094280000B0081140F9E9030091280100F90000009000243E911B000094280000B0081940F9E9030091280100F90000009000403E9114000094280000B0E80700F9082140F9E9030091280100F900000090005C3E910C000094E80740F9082140F9E9030091280100F90000009000783E910500009400008052FD7B41A9FF830091C0035FD6 + - sectname: __stubs + segname: __TEXT + addr: 0x100003F3C + size: 12 + offset: 0x3F3C + align: 2 + reloff: 0x0 + nreloc: 0 + flags: 0x80000408 + reserved1: 0x0 + reserved2: 0xC + reserved3: 0x0 + content: 300000B0100240F900021FD6 + - sectname: __stub_helper + segname: __TEXT + addr: 0x100003F48 + size: 36 + offset: 0x3F48 + align: 2 + reloff: 0x0 + nreloc: 0 + flags: 0x80000400 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: 310000B031220091F047BFA9100000B0100A40F900021FD650000018F9FFFF1700000000 + - sectname: __cstring + segname: __TEXT + addr: 0x100003F6C + size: 57 + offset: 0x3F6C + align: 0 + reloff: 0x0 + nreloc: 0 + flags: 0x2 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: 6D616C6C6F633A2025700A00667265653A2025700A00613A2025700A00623A2025700A00633A2025700A00643A2025700A00653A2025700A00 + - sectname: __unwind_info + segname: __TEXT + addr: 0x100003FA8 + size: 88 + offset: 0x3FA8 + align: 2 + reloff: 0x0 + nreloc: 0 + flags: 0x0 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: 010000001C000000000000001C000000000000001C00000002000000583E000040000000400000003C3F00000000000040000000000000000000000000000000030000000C00010010000100000000000000000400000000 + - cmd: LC_SEGMENT_64 + cmdsize: 152 + segname: __DATA_CONST + vmaddr: 4294983680 + vmsize: 16384 + fileoff: 16384 + filesize: 16384 + maxprot: 3 + initprot: 3 + nsects: 1 + flags: 16 + Sections: + - sectname: __got + segname: __DATA_CONST + addr: 0x100004000 + size: 24 + offset: 0x4000 + align: 3 + reloff: 0x0 + nreloc: 0 + flags: 0x6 + reserved1: 0x1 + reserved2: 0x0 + reserved3: 0x0 + content: '000000000000000000000000000000000000000000000000' + - cmd: LC_SEGMENT_64 + cmdsize: 232 + segname: __DATA + vmaddr: 4295000064 + vmsize: 16384 + fileoff: 32768 + filesize: 16384 + maxprot: 3 + initprot: 3 + nsects: 2 + flags: 0 + Sections: + - sectname: __la_symbol_ptr + segname: __DATA + addr: 0x100008000 + size: 8 + offset: 0x8000 + align: 3 + reloff: 0x0 + nreloc: 0 + flags: 0x7 + reserved1: 0x4 + reserved2: 0x0 + reserved3: 0x0 + content: 603F000001000000 + - sectname: __data + segname: __DATA + addr: 0x100008008 + size: 88 + offset: 0x8008 + align: 3 + reloff: 0x0 + nreloc: 0 + flags: 0x0 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: '00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000' + - cmd: LC_SEGMENT_64 + cmdsize: 72 + segname: __LINKEDIT + vmaddr: 4295016448 + vmsize: 32768 + fileoff: 49152 + filesize: 19184 + maxprot: 1 + initprot: 1 + nsects: 0 + flags: 0 + - cmd: LC_DYLD_INFO_ONLY + cmdsize: 48 + rebase_off: 49152 + rebase_size: 8 + bind_off: 49160 + bind_size: 72 + weak_bind_off: 0 + weak_bind_size: 0 + lazy_bind_off: 49232 + lazy_bind_size: 16 + export_off: 49248 + export_size: 96 + - cmd: LC_SYMTAB + cmdsize: 24 + symoff: 49352 + nsyms: 13 + stroff: 49584 + strsize: 104 + - cmd: LC_DYSYMTAB + cmdsize: 80 + ilocalsym: 0 + nlocalsym: 1 + iextdefsym: 1 + nextdefsym: 7 + iundefsym: 8 + nundefsym: 5 + tocoff: 0 + ntoc: 0 + modtaboff: 0 + nmodtab: 0 + extrefsymoff: 0 + nextrefsyms: 0 + indirectsymoff: 49560 + nindirectsyms: 5 + extreloff: 0 + nextrel: 0 + locreloff: 0 + nlocrel: 0 + - cmd: LC_LOAD_DYLINKER + cmdsize: 32 + name: 12 + Content: '/usr/lib/dyld' + ZeroPadBytes: 7 + - cmd: LC_UUID + cmdsize: 24 + uuid: 2018719F-D4DC-3EE9-B8C3-3B790A01EAF7 + - cmd: LC_BUILD_VERSION + cmdsize: 32 + platform: 1 + minos: 917504 + sdk: 918784 + ntools: 1 + Tools: + - tool: 3 + version: 0 + - cmd: LC_SOURCE_VERSION + cmdsize: 16 + version: 0 + - cmd: LC_MAIN + cmdsize: 24 + entryoff: 15960 + stacksize: 0 + - cmd: LC_LOAD_DYLIB + cmdsize: 56 + dylib: + name: 24 + timestamp: 2 + current_version: 88176642 + compatibility_version: 65536 + Content: '/usr/lib/libSystem.B.dylib' + ZeroPadBytes: 6 + - cmd: LC_FUNCTION_STARTS + cmdsize: 16 + dataoff: 49344 + datasize: 8 + - cmd: LC_DATA_IN_CODE + cmdsize: 16 + dataoff: 49352 + datasize: 0 + - cmd: LC_CODE_SIGNATURE + cmdsize: 16 + dataoff: 49696 + datasize: 18640 +LinkEditData: + RebaseOpcodes: + - Opcode: REBASE_OPCODE_SET_TYPE_IMM + Imm: 1 + - Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB + Imm: 3 + ExtraData: [ 0x0 ] + - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES + Imm: 1 + - Opcode: REBASE_OPCODE_DONE + Imm: 0 + BindOpcodes: + - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM + Imm: 1 + Symbol: '' + - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM + Imm: 0 + Symbol: _free + - Opcode: BIND_OPCODE_SET_TYPE_IMM + Imm: 1 + Symbol: '' + - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB + Imm: 2 + ULEBExtraData: [ 0x0 ] + Symbol: '' + - Opcode: BIND_OPCODE_DO_BIND + Imm: 0 + Symbol: '' + - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB + Imm: 3 + ULEBExtraData: [ 0x40 ] + Symbol: '' + - Opcode: BIND_OPCODE_DO_BIND + Imm: 0 + Symbol: '' + - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM + Imm: 0 + Symbol: _malloc + - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB + Imm: 2 + ULEBExtraData: [ 0x8 ] + Symbol: '' + - Opcode: BIND_OPCODE_DO_BIND + Imm: 0 + Symbol: '' + - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB + Imm: 3 + ULEBExtraData: [ 0x30 ] + Symbol: '' + - Opcode: BIND_OPCODE_DO_BIND_ULEB_TIMES_SKIPPING_ULEB + Imm: 0 + ULEBExtraData: [ 0x2, 0xFFFFFFFFFFFFFFF0 ] + Symbol: '' + - Opcode: BIND_OPCODE_DO_BIND + Imm: 0 + Symbol: '' + - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM + Imm: 0 + Symbol: dyld_stub_binder + - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB + Imm: 2 + ULEBExtraData: [ 0x10 ] + Symbol: '' + - Opcode: BIND_OPCODE_DO_BIND + Imm: 0 + Symbol: '' + - Opcode: BIND_OPCODE_DONE + Imm: 0 + Symbol: '' + LazyBindOpcodes: + - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB + Imm: 3 + ULEBExtraData: [ 0x0 ] + Symbol: '' + - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM + Imm: 1 + Symbol: '' + - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM + Imm: 0 + Symbol: _printf + - Opcode: BIND_OPCODE_DO_BIND + Imm: 0 + Symbol: '' + - Opcode: BIND_OPCODE_DONE + Imm: 0 + Symbol: '' + - Opcode: BIND_OPCODE_DONE + Imm: 0 + Symbol: '' + - Opcode: BIND_OPCODE_DONE + Imm: 0 + Symbol: '' + ExportTrie: + TerminalSize: 0 + NodeOffset: 0 + Name: '' + Flags: 0x0 + Address: 0x0 + Other: 0x0 + ImportName: '' + Children: + - TerminalSize: 0 + NodeOffset: 48 + Name: _ + Flags: 0x0 + Address: 0x0 + Other: 0x0 + ImportName: '' + Children: + - TerminalSize: 2 + NodeOffset: 9 + Name: _mh_execute_header + Flags: 0x0 + Address: 0x0 + Other: 0x0 + ImportName: '' + - TerminalSize: 4 + NodeOffset: 13 + Name: a + Flags: 0x0 + Address: 0x8010 + Other: 0x0 + ImportName: '' + - TerminalSize: 4 + NodeOffset: 19 + Name: b + Flags: 0x0 + Address: 0x8020 + Other: 0x0 + ImportName: '' + - TerminalSize: 4 + NodeOffset: 25 + Name: c + Flags: 0x0 + Address: 0x8030 + Other: 0x0 + ImportName: '' + - TerminalSize: 4 + NodeOffset: 31 + Name: d + Flags: 0x0 + Address: 0x8040 + Other: 0x0 + ImportName: '' + - TerminalSize: 4 + NodeOffset: 37 + Name: e + Flags: 0x0 + Address: 0x8050 + Other: 0x0 + ImportName: '' + - TerminalSize: 3 + NodeOffset: 43 + Name: main + Flags: 0x0 + Address: 0x3E58 + Other: 0x0 + ImportName: '' + NameList: + - n_strx: 88 + n_type: 0xE + n_sect: 8 + n_desc: 0 + n_value: 4295000072 + - n_strx: 2 + n_type: 0xF + n_sect: 1 + n_desc: 16 + n_value: 4294967296 + - n_strx: 22 + n_type: 0xF + n_sect: 8 + n_desc: 0 + n_value: 4295000080 + - n_strx: 25 + n_type: 0xF + n_sect: 8 + n_desc: 0 + n_value: 4295000096 + - n_strx: 28 + n_type: 0xF + n_sect: 8 + n_desc: 0 + n_value: 4295000112 + - n_strx: 31 + n_type: 0xF + n_sect: 8 + n_desc: 0 + n_value: 4295000128 + - n_strx: 34 + n_type: 0xF + n_sect: 8 + n_desc: 0 + n_value: 4295000144 + - n_strx: 37 + n_type: 0xF + n_sect: 1 + n_desc: 0 + n_value: 4294983256 + - n_strx: 43 + n_type: 0x1 + n_sect: 0 + n_desc: 256 + n_value: 0 + - n_strx: 49 + n_type: 0x1 + n_sect: 0 + n_desc: 256 + n_value: 0 + - n_strx: 57 + n_type: 0x1 + n_sect: 0 + n_desc: 256 + n_value: 0 + - n_strx: 65 + n_type: 0x1 + n_sect: 0 + n_desc: 256 + n_value: 0 + - n_strx: 71 + n_type: 0x1 + n_sect: 0 + n_desc: 256 + n_value: 0 + StringTable: + - ' ' + - __mh_execute_header + - _a + - _b + - _c + - _d + - _e + - _main + - _free + - _malloc + - _printf + - _read + - dyld_stub_binder + - __dyld_private + - '' + IndirectSymbols: [ 0xA, 0x8, 0x9, 0xC, 0xA ] + FunctionStarts: [ 0x3E58 ] +... diff --git a/llvm/test/Object/macho-bind-negative-skip.test b/llvm/test/Object/macho-bind-negative-skip.test new file mode 100644 index 000000000000..26884a28ea46 --- /dev/null +++ b/llvm/test/Object/macho-bind-negative-skip.test @@ -0,0 +1,17 @@ +// A valid MachO object with a bind table containing an opcode +// `BIND_OPCODE_DO_BIND_ULEB_TIMES_SKIPPING_ULEB` with negative skip value +// (0xFFFFFFFFFFFFFFF0). + +RUN: yaml2obj %p/Inputs/MachO/bind-negative-skip.yaml | \ +RUN: llvm-objdump --bind --macho - | \ +RUN: FileCheck %s + +CHECK: Bind table: +CHECK-NEXT: segment section address type addend dylib symbol +CHECK-NEXT: __DATA_CONST __got 0x100004000 pointer 0 libSystem _free +CHECK-NEXT: __DATA __data 0x100008040 pointer 0 libSystem _free +CHECK-NEXT: __DATA_CONST __got 0x100004008 pointer 0 libSystem _malloc +CHECK-NEXT: __DATA __data 0x100008030 pointer 0 libSystem _malloc +CHECK-NEXT: __DATA __data 0x100008028 pointer 0 libSystem _malloc +CHECK-NEXT: __DATA __data 0x100008020 pointer 0 libSystem _malloc +CHECK-NEXT: __DATA_CONST __got 0x100004010 pointer 0 libSystem dyld_stub_binder -- GitLab From a39a382755c8cf27ecd9a646e720610f48dc09ad Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 9 May 2024 12:29:01 +0900 Subject: [PATCH 098/328] [InstCombine] Thwart complexity-based canonicalization (NFC) These tests did not test what they were supposed to. The transform fails to actually handle the commuted cases. --- llvm/test/Transforms/InstCombine/add.ll | 59 +++++++++++++++++-------- 1 file changed, 40 insertions(+), 19 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll index 56ee54d351e7..42e901ea2d5a 100644 --- a/llvm/test/Transforms/InstCombine/add.ll +++ b/llvm/test/Transforms/InstCombine/add.ll @@ -3284,12 +3284,17 @@ define i32 @add_reduce_sqr_sum_flipped(i32 %a, i32 %b) { ret i32 %add } -define i32 @add_reduce_sqr_sum_flipped2(i32 %a, i32 %b) { +define i32 @add_reduce_sqr_sum_flipped2(i32 %a, i32 %bx) { ; CHECK-LABEL: @add_reduce_sqr_sum_flipped2( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[ADD:%.*]] = mul i32 [[TMP1]], [[TMP1]] +; CHECK-NEXT: [[B:%.*]] = xor i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[A_SQ:%.*]] = mul nsw i32 [[A:%.*]], [[A]] +; CHECK-NEXT: [[TWO_A:%.*]] = shl i32 [[A]], 1 +; CHECK-NEXT: [[TWO_A_PLUS_B:%.*]] = add i32 [[TWO_A]], [[B]] +; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[B]], [[TWO_A_PLUS_B]] +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[MUL]], [[A_SQ]] ; CHECK-NEXT: ret i32 [[ADD]] ; + %b = xor i32 %bx, 42 ; thwart complexity-based canonicalization %a_sq = mul nsw i32 %a, %a %two_a = shl i32 %a, 1 %two_a_plus_b = add i32 %two_a, %b @@ -3342,12 +3347,17 @@ define i32 @add_reduce_sqr_sum_order2_flipped(i32 %a, i32 %b) { ret i32 %ab2 } -define i32 @add_reduce_sqr_sum_order2_flipped2(i32 %a, i32 %b) { +define i32 @add_reduce_sqr_sum_order2_flipped2(i32 %a, i32 %bx) { ; CHECK-LABEL: @add_reduce_sqr_sum_order2_flipped2( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[AB2:%.*]] = mul i32 [[TMP1]], [[TMP1]] +; CHECK-NEXT: [[B:%.*]] = xor i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[A_SQ:%.*]] = mul nsw i32 [[A:%.*]], [[A]] +; CHECK-NEXT: [[TWOA:%.*]] = shl i32 [[A]], 1 +; CHECK-NEXT: [[TWOAB1:%.*]] = add i32 [[B]], [[TWOA]] +; CHECK-NEXT: [[TWOAB_B2:%.*]] = mul i32 [[B]], [[TWOAB1]] +; CHECK-NEXT: [[AB2:%.*]] = add i32 [[A_SQ]], [[TWOAB_B2]] ; CHECK-NEXT: ret i32 [[AB2]] ; + %b = xor i32 %bx, 42 ; thwart complexity-based canonicalization %a_sq = mul nsw i32 %a, %a %twoa = mul i32 %a, 2 %twoab = mul i32 %twoa, %b @@ -3357,12 +3367,17 @@ define i32 @add_reduce_sqr_sum_order2_flipped2(i32 %a, i32 %b) { ret i32 %ab2 } -define i32 @add_reduce_sqr_sum_order2_flipped3(i32 %a, i32 %b) { +define i32 @add_reduce_sqr_sum_order2_flipped3(i32 %a, i32 %bx) { ; CHECK-LABEL: @add_reduce_sqr_sum_order2_flipped3( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[AB2:%.*]] = mul i32 [[TMP1]], [[TMP1]] +; CHECK-NEXT: [[B:%.*]] = xor i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[A_SQ:%.*]] = mul nsw i32 [[A:%.*]], [[A]] +; CHECK-NEXT: [[TWOA:%.*]] = shl i32 [[A]], 1 +; CHECK-NEXT: [[B_SQ1:%.*]] = add i32 [[TWOA]], [[B]] +; CHECK-NEXT: [[TWOAB_B2:%.*]] = mul i32 [[B]], [[B_SQ1]] +; CHECK-NEXT: [[AB2:%.*]] = add i32 [[A_SQ]], [[TWOAB_B2]] ; CHECK-NEXT: ret i32 [[AB2]] ; + %b = xor i32 %bx, 42 ; thwart complexity-based canonicalization %a_sq = mul nsw i32 %a, %a %twoa = mul i32 %a, 2 %twoab = mul i32 %b, %twoa @@ -3552,12 +3567,18 @@ define i32 @add_reduce_sqr_sum_order5_flipped2(i32 %a, i32 %b) { ret i32 %ab2 } -define i32 @add_reduce_sqr_sum_order5_flipped3(i32 %a, i32 %b) { +define i32 @add_reduce_sqr_sum_order5_flipped3(i32 %ax, i32 %b) { ; CHECK-LABEL: @add_reduce_sqr_sum_order5_flipped3( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[B:%.*]], [[A:%.*]] -; CHECK-NEXT: [[AB2:%.*]] = mul i32 [[TMP1]], [[TMP1]] +; CHECK-NEXT: [[A:%.*]] = xor i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[A_SQ:%.*]] = mul nsw i32 [[A]], [[A]] +; CHECK-NEXT: [[TWOB:%.*]] = shl i32 [[B:%.*]], 1 +; CHECK-NEXT: [[TWOAB:%.*]] = mul i32 [[A]], [[TWOB]] +; CHECK-NEXT: [[B_SQ:%.*]] = mul i32 [[B]], [[B]] +; CHECK-NEXT: [[A2_B2:%.*]] = add i32 [[A_SQ]], [[B_SQ]] +; CHECK-NEXT: [[AB2:%.*]] = add i32 [[TWOAB]], [[A2_B2]] ; CHECK-NEXT: ret i32 [[AB2]] ; + %a = xor i32 %ax, 42 ; thwart complexity-based canonicalization %a_sq = mul nsw i32 %a, %a %twob = mul i32 %b, 2 %twoab = mul i32 %a, %twob @@ -4018,8 +4039,8 @@ define i32 @add_reduce_sqr_sum_varC_invalid2(i32 %a, i32 %b) { define i32 @fold_sext_addition_or_disjoint(i8 %x) { ; CHECK-LABEL: @fold_sext_addition_or_disjoint( -; CHECK-NEXT: [[SE:%.*]] = sext i8 [[XX:%.*]] to i32 -; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[SE]], 1246 +; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32 +; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[TMP1]], 1246 ; CHECK-NEXT: ret i32 [[R]] ; %xx = or disjoint i8 %x, 12 @@ -4043,8 +4064,8 @@ define i32 @fold_sext_addition_fail(i8 %x) { define i32 @fold_zext_addition_or_disjoint(i8 %x) { ; CHECK-LABEL: @fold_zext_addition_or_disjoint( -; CHECK-NEXT: [[SE:%.*]] = zext i8 [[XX:%.*]] to i32 -; CHECK-NEXT: [[R:%.*]] = add nuw nsw i32 [[SE]], 1246 +; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32 +; CHECK-NEXT: [[R:%.*]] = add nuw nsw i32 [[TMP1]], 1246 ; CHECK-NEXT: ret i32 [[R]] ; %xx = or disjoint i8 %x, 12 @@ -4055,9 +4076,9 @@ define i32 @fold_zext_addition_or_disjoint(i8 %x) { define i32 @fold_zext_addition_or_disjoint2(i8 %x) { ; CHECK-LABEL: @fold_zext_addition_or_disjoint2( -; CHECK-NEXT: [[XX:%.*]] = add nuw i8 [[X:%.*]], 4 -; CHECK-NEXT: [[SE:%.*]] = zext i8 [[XX]] to i32 -; CHECK-NEXT: ret i32 [[SE]] +; CHECK-NEXT: [[TMP1:%.*]] = add nuw i8 [[X:%.*]], 4 +; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP1]] to i32 +; CHECK-NEXT: ret i32 [[R]] ; %xx = or disjoint i8 %x, 18 %se = zext i8 %xx to i32 -- GitLab From 0d335f78e45341db53d9f956adcebbb2d2616c9a Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 9 May 2024 12:35:16 +0900 Subject: [PATCH 099/328] [InstCombine] Handle more commuted cases in matchesSquareSum() --- .../InstCombine/InstCombineAddSub.cpp | 20 ++++++------- llvm/test/Transforms/InstCombine/add.ll | 29 +++++-------------- 2 files changed, 18 insertions(+), 31 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index 51ac77348ed9..bff09f567668 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -1014,7 +1014,7 @@ static bool matchesSquareSum(BinaryOperator &I, Mul2Rhs M2Rhs, Value *&A, // (a * a) + (((a * 2) + b) * b) if (match(&I, m_c_BinOp( AddOp, m_OneUse(m_BinOp(MulOp, m_Value(A), m_Deferred(A))), - m_OneUse(m_BinOp( + m_OneUse(m_c_BinOp( MulOp, m_c_BinOp(AddOp, m_BinOp(Mul2Op, m_Deferred(A), M2Rhs), m_Value(B)), @@ -1025,16 +1025,16 @@ static bool matchesSquareSum(BinaryOperator &I, Mul2Rhs M2Rhs, Value *&A, // + // (a * a + b * b) or (b * b + a * a) return match( - &I, - m_c_BinOp(AddOp, - m_CombineOr( - m_OneUse(m_BinOp( - Mul2Op, m_BinOp(MulOp, m_Value(A), m_Value(B)), M2Rhs)), - m_OneUse(m_BinOp(MulOp, m_BinOp(Mul2Op, m_Value(A), M2Rhs), + &I, m_c_BinOp( + AddOp, + m_CombineOr( + m_OneUse(m_BinOp( + Mul2Op, m_BinOp(MulOp, m_Value(A), m_Value(B)), M2Rhs)), + m_OneUse(m_c_BinOp(MulOp, m_BinOp(Mul2Op, m_Value(A), M2Rhs), m_Value(B)))), - m_OneUse(m_c_BinOp( - AddOp, m_BinOp(MulOp, m_Deferred(A), m_Deferred(A)), - m_BinOp(MulOp, m_Deferred(B), m_Deferred(B)))))); + m_OneUse( + m_c_BinOp(AddOp, m_BinOp(MulOp, m_Deferred(A), m_Deferred(A)), + m_BinOp(MulOp, m_Deferred(B), m_Deferred(B)))))); } // Fold integer variations of a^2 + 2*a*b + b^2 -> (a + b)^2 diff --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll index 42e901ea2d5a..25087fef68a1 100644 --- a/llvm/test/Transforms/InstCombine/add.ll +++ b/llvm/test/Transforms/InstCombine/add.ll @@ -3287,11 +3287,8 @@ define i32 @add_reduce_sqr_sum_flipped(i32 %a, i32 %b) { define i32 @add_reduce_sqr_sum_flipped2(i32 %a, i32 %bx) { ; CHECK-LABEL: @add_reduce_sqr_sum_flipped2( ; CHECK-NEXT: [[B:%.*]] = xor i32 [[BX:%.*]], 42 -; CHECK-NEXT: [[A_SQ:%.*]] = mul nsw i32 [[A:%.*]], [[A]] -; CHECK-NEXT: [[TWO_A:%.*]] = shl i32 [[A]], 1 -; CHECK-NEXT: [[TWO_A_PLUS_B:%.*]] = add i32 [[TWO_A]], [[B]] -; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[B]], [[TWO_A_PLUS_B]] -; CHECK-NEXT: [[ADD:%.*]] = add i32 [[MUL]], [[A_SQ]] +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[B]], [[A:%.*]] +; CHECK-NEXT: [[ADD:%.*]] = mul i32 [[TMP1]], [[TMP1]] ; CHECK-NEXT: ret i32 [[ADD]] ; %b = xor i32 %bx, 42 ; thwart complexity-based canonicalization @@ -3350,11 +3347,8 @@ define i32 @add_reduce_sqr_sum_order2_flipped(i32 %a, i32 %b) { define i32 @add_reduce_sqr_sum_order2_flipped2(i32 %a, i32 %bx) { ; CHECK-LABEL: @add_reduce_sqr_sum_order2_flipped2( ; CHECK-NEXT: [[B:%.*]] = xor i32 [[BX:%.*]], 42 -; CHECK-NEXT: [[A_SQ:%.*]] = mul nsw i32 [[A:%.*]], [[A]] -; CHECK-NEXT: [[TWOA:%.*]] = shl i32 [[A]], 1 -; CHECK-NEXT: [[TWOAB1:%.*]] = add i32 [[B]], [[TWOA]] -; CHECK-NEXT: [[TWOAB_B2:%.*]] = mul i32 [[B]], [[TWOAB1]] -; CHECK-NEXT: [[AB2:%.*]] = add i32 [[A_SQ]], [[TWOAB_B2]] +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[B]], [[A:%.*]] +; CHECK-NEXT: [[AB2:%.*]] = mul i32 [[TMP1]], [[TMP1]] ; CHECK-NEXT: ret i32 [[AB2]] ; %b = xor i32 %bx, 42 ; thwart complexity-based canonicalization @@ -3370,11 +3364,8 @@ define i32 @add_reduce_sqr_sum_order2_flipped2(i32 %a, i32 %bx) { define i32 @add_reduce_sqr_sum_order2_flipped3(i32 %a, i32 %bx) { ; CHECK-LABEL: @add_reduce_sqr_sum_order2_flipped3( ; CHECK-NEXT: [[B:%.*]] = xor i32 [[BX:%.*]], 42 -; CHECK-NEXT: [[A_SQ:%.*]] = mul nsw i32 [[A:%.*]], [[A]] -; CHECK-NEXT: [[TWOA:%.*]] = shl i32 [[A]], 1 -; CHECK-NEXT: [[B_SQ1:%.*]] = add i32 [[TWOA]], [[B]] -; CHECK-NEXT: [[TWOAB_B2:%.*]] = mul i32 [[B]], [[B_SQ1]] -; CHECK-NEXT: [[AB2:%.*]] = add i32 [[A_SQ]], [[TWOAB_B2]] +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[B]], [[A:%.*]] +; CHECK-NEXT: [[AB2:%.*]] = mul i32 [[TMP1]], [[TMP1]] ; CHECK-NEXT: ret i32 [[AB2]] ; %b = xor i32 %bx, 42 ; thwart complexity-based canonicalization @@ -3570,12 +3561,8 @@ define i32 @add_reduce_sqr_sum_order5_flipped2(i32 %a, i32 %b) { define i32 @add_reduce_sqr_sum_order5_flipped3(i32 %ax, i32 %b) { ; CHECK-LABEL: @add_reduce_sqr_sum_order5_flipped3( ; CHECK-NEXT: [[A:%.*]] = xor i32 [[AX:%.*]], 42 -; CHECK-NEXT: [[A_SQ:%.*]] = mul nsw i32 [[A]], [[A]] -; CHECK-NEXT: [[TWOB:%.*]] = shl i32 [[B:%.*]], 1 -; CHECK-NEXT: [[TWOAB:%.*]] = mul i32 [[A]], [[TWOB]] -; CHECK-NEXT: [[B_SQ:%.*]] = mul i32 [[B]], [[B]] -; CHECK-NEXT: [[A2_B2:%.*]] = add i32 [[A_SQ]], [[B_SQ]] -; CHECK-NEXT: [[AB2:%.*]] = add i32 [[TWOAB]], [[A2_B2]] +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[A]], [[B:%.*]] +; CHECK-NEXT: [[AB2:%.*]] = mul i32 [[TMP1]], [[TMP1]] ; CHECK-NEXT: ret i32 [[AB2]] ; %a = xor i32 %ax, 42 ; thwart complexity-based canonicalization -- GitLab From f958a7348fcb27c3c6b07f1c8bdb902c7525b845 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 9 May 2024 12:43:00 +0900 Subject: [PATCH 100/328] [InstCombine] Fix name clashes in check lines (NFC) These used both lower and upper case variants of the same name, resulting in malformed check lines when regenerated. --- llvm/test/Transforms/InstCombine/call-guard.ll | 16 ++++++++-------- llvm/test/Transforms/InstCombine/fast-math.ll | 8 ++++---- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/call-guard.ll b/llvm/test/Transforms/InstCombine/call-guard.ll index 6d9308bbbd81..358518b9bd1c 100644 --- a/llvm/test/Transforms/InstCombine/call-guard.ll +++ b/llvm/test/Transforms/InstCombine/call-guard.ll @@ -114,22 +114,22 @@ define void @negative_div(i32 %V1, i32 %D) { ; Highlight the limit of the window in a case which would otherwise be mergable define void @negative_window(i32 %V1, i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK-LABEL: @negative_window( -; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[V1:%.*]], 0 -; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[A]], i32 123) [ "deopt"() ] +; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[V1:%.*]], 0 +; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP1]], i32 123) [ "deopt"() ] ; CHECK-NEXT: [[V2:%.*]] = add i32 [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[V3:%.*]] = add i32 [[V2]], [[C:%.*]] ; CHECK-NEXT: [[V4:%.*]] = add i32 [[V3]], [[D:%.*]] -; CHECK-NEXT: [[B:%.*]] = icmp slt i32 [[V4]], 0 -; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[B]], i32 456) [ "deopt"() ] +; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[V4]], 0 +; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP2]], i32 456) [ "deopt"() ] ; CHECK-NEXT: ret void ; - %A = icmp slt i32 %V1, 0 - call void(i1, ...) @llvm.experimental.guard( i1 %A, i32 123 )[ "deopt"() ] + %cmp1 = icmp slt i32 %V1, 0 + call void(i1, ...) @llvm.experimental.guard( i1 %cmp1, i32 123 )[ "deopt"() ] %V2 = add i32 %a, %b %V3 = add i32 %V2, %c %V4 = add i32 %V3, %d - %B = icmp slt i32 %V4, 0 - call void(i1, ...) @llvm.experimental.guard( i1 %B, i32 456 )[ "deopt"() ] + %cmp2 = icmp slt i32 %V4, 0 + call void(i1, ...) @llvm.experimental.guard( i1 %cmp2, i32 456 )[ "deopt"() ] ret void } diff --git a/llvm/test/Transforms/InstCombine/fast-math.ll b/llvm/test/Transforms/InstCombine/fast-math.ll index 83f2091244e5..da403555ebe2 100644 --- a/llvm/test/Transforms/InstCombine/fast-math.ll +++ b/llvm/test/Transforms/InstCombine/fast-math.ll @@ -922,8 +922,8 @@ define float @test55(i1 %which, float %a) { ; CHECK-NEXT: [[TMP0:%.*]] = fadd float [[A:%.*]], 1.000000e+00 ; CHECK-NEXT: br label [[FINAL]] ; CHECK: final: -; CHECK-NEXT: [[A:%.*]] = phi float [ 3.000000e+00, [[ENTRY:%.*]] ], [ [[TMP0]], [[DELAY]] ] -; CHECK-NEXT: ret float [[A]] +; CHECK-NEXT: [[PHI:%.*]] = phi float [ 3.000000e+00, [[ENTRY:%.*]] ], [ [[TMP0]], [[DELAY]] ] +; CHECK-NEXT: ret float [[PHI]] ; entry: br i1 %which, label %final, label %delay @@ -932,7 +932,7 @@ delay: br label %final final: - %A = phi float [ 2.0, %entry ], [ %a, %delay ] - %value = fadd float %A, 1.0 + %phi = phi float [ 2.0, %entry ], [ %a, %delay ] + %value = fadd float %phi, 1.0 ret float %value } -- GitLab From 8f4f34f10345806b25b892d3df15951ee820de82 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Thu, 9 May 2024 11:46:34 +0800 Subject: [PATCH 101/328] [RISCV] Add test for vmerge.vvm that could have splat sunk. NFC --- .../CodeGen/RISCV/rvv/sink-splat-operands.ll | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll index 9046c861c336..6e902e79896b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll @@ -5423,3 +5423,41 @@ vector.body: ; preds = %vector.body, %entry for.cond.cleanup: ; preds = %vector.body ret void } + +define void @sink_splat_select(ptr nocapture %a, i32 signext %x) { +; CHECK-LABEL: sink_splat_select: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: lui a1, 1 +; CHECK-NEXT: add a1, a0, a1 +; CHECK-NEXT: li a2, 42 +; CHECK-NEXT: .LBB117_1: # %vector.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vmseq.vx v0, v9, a2 +; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0 +; CHECK-NEXT: vse32.v v9, (a0) +; CHECK-NEXT: addi a0, a0, 16 +; CHECK-NEXT: bne a0, a1, .LBB117_1 +; CHECK-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-NEXT: ret +entry: + %broadcast.splatinsert = insertelement <4 x i32> poison, i32 %x, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i32, ptr %a, i64 %index + %load = load <4 x i32>, ptr %0, align 4 + %cond = icmp eq <4 x i32> %load, splat (i32 42) + %1 = select <4 x i1> %cond, <4 x i32> %broadcast.splat, <4 x i32> %load + store <4 x i32> %1, ptr %0, align 4 + %index.next = add nuw i64 %index, 4 + %2 = icmp eq i64 %index.next, 1024 + br i1 %2, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body + ret void +} -- GitLab From 73d423319c0957a9b16ed8d5fb7c8336729b9c38 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 9 May 2024 12:48:37 +0900 Subject: [PATCH 102/328] [InstCombine] Regenerate test checks (NFC) --- .../InstCombine/apint-and-xor-merge.ll | 8 +- llvm/test/Transforms/InstCombine/apint-or.ll | 90 +++---- .../Transforms/InstCombine/trunc-binop-ext.ll | 228 ++++++++++-------- 3 files changed, 182 insertions(+), 144 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/apint-and-xor-merge.ll b/llvm/test/Transforms/InstCombine/apint-and-xor-merge.ll index c904035f41ca..9810e5057d8a 100644 --- a/llvm/test/Transforms/InstCombine/apint-and-xor-merge.ll +++ b/llvm/test/Transforms/InstCombine/apint-and-xor-merge.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; This test case checks that the merge of and/xor can work on arbitrary ; precision integers. @@ -7,8 +7,8 @@ ; (x &z ) ^ (y & z) -> (x ^ y) & z define i57 @test1(i57 %x, i57 %y, i57 %z) { ; CHECK-LABEL: @test1( -; CHECK-NEXT: [[TMP61:%.*]] = xor i57 %x, %y -; CHECK-NEXT: [[TMP7:%.*]] = and i57 [[TMP61]], %z +; CHECK-NEXT: [[TMP61:%.*]] = xor i57 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[TMP7:%.*]] = and i57 [[TMP61]], [[Z:%.*]] ; CHECK-NEXT: ret i57 [[TMP7]] ; %tmp3 = and i57 %z, %x @@ -20,7 +20,7 @@ define i57 @test1(i57 %x, i57 %y, i57 %z) { ; (x & y) ^ (x | y) -> x ^ y define i23 @test2(i23 %x, i23 %y, i23 %z) { ; CHECK-LABEL: @test2( -; CHECK-NEXT: [[TMP7:%.*]] = xor i23 %y, %x +; CHECK-NEXT: [[TMP7:%.*]] = xor i23 [[Y:%.*]], [[X:%.*]] ; CHECK-NEXT: ret i23 [[TMP7]] ; %tmp3 = and i23 %y, %x diff --git a/llvm/test/Transforms/InstCombine/apint-or.ll b/llvm/test/Transforms/InstCombine/apint-or.ll index 939d151c21d2..38bffdf35a36 100644 --- a/llvm/test/Transforms/InstCombine/apint-or.ll +++ b/llvm/test/Transforms/InstCombine/apint-or.ll @@ -1,56 +1,64 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s ; These tests are for Integer BitWidth <= 64 && BitWidth % 2 != 0. +;; A | ~A == -1 define i23 @test1(i23 %A) { - ;; A | ~A == -1 - %NotA = xor i23 -1, %A - %B = or i23 %A, %NotA - ret i23 %B -; CHECK-LABEL: @test1 -; CHECK-NEXT: ret i23 -1 +; CHECK-LABEL: define i23 @test1( +; CHECK-SAME: i23 [[A:%.*]]) { +; CHECK-NEXT: ret i23 -1 +; + %NotA = xor i23 -1, %A + %B = or i23 %A, %NotA + ret i23 %B } +;; If we have: ((V + N) & C1) | (V & C2) +;; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0 +;; replace with V+N. define i39 @test2(i39 %V, i39 %M) { - ;; If we have: ((V + N) & C1) | (V & C2) - ;; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0 - ;; replace with V+N. - %C1 = xor i39 274877906943, -1 ;; C2 = 274877906943 - %N = and i39 %M, 274877906944 - %A = add i39 %V, %N - %B = and i39 %A, %C1 - %D = and i39 %V, 274877906943 - %R = or i39 %B, %D - ret i39 %R -; CHECK-LABEL: @test2 -; CHECK-NEXT: %N = and i39 %M, -274877906944 -; CHECK-NEXT: %A = add i39 %N, %V -; CHECK-NEXT: ret i39 %A +; CHECK-LABEL: define i39 @test2( +; CHECK-SAME: i39 [[V:%.*]], i39 [[M:%.*]]) { +; CHECK-NEXT: [[N:%.*]] = and i39 [[M]], -274877906944 +; CHECK-NEXT: [[A:%.*]] = add i39 [[N]], [[V]] +; CHECK-NEXT: ret i39 [[A]] +; + %C1 = xor i39 274877906943, -1 ;; C2 = 274877906943 + %N = and i39 %M, 274877906944 + %A = add i39 %V, %N + %B = and i39 %A, %C1 + %D = and i39 %V, 274877906943 + %R = or i39 %B, %D + ret i39 %R } ; These tests are for Integer BitWidth > 64 && BitWidth <= 1024. +;; A | ~A == -1 define i1023 @test4(i1023 %A) { - ;; A | ~A == -1 - %NotA = xor i1023 -1, %A - %B = or i1023 %A, %NotA - ret i1023 %B -; CHECK-LABEL: @test4 -; CHECK-NEXT: ret i1023 -1 +; CHECK-LABEL: define i1023 @test4( +; CHECK-SAME: i1023 [[A:%.*]]) { +; CHECK-NEXT: ret i1023 -1 +; + %NotA = xor i1023 -1, %A + %B = or i1023 %A, %NotA + ret i1023 %B } +;; If we have: ((V + N) & C1) | (V & C2) +;; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0 +;; replace with V+N. define i399 @test5(i399 %V, i399 %M) { - ;; If we have: ((V + N) & C1) | (V & C2) - ;; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0 - ;; replace with V+N. - %C1 = xor i399 274877906943, -1 ;; C2 = 274877906943 - %N = and i399 %M, 18446742974197923840 - %A = add i399 %V, %N - %B = and i399 %A, %C1 - %D = and i399 %V, 274877906943 - %R = or i399 %B, %D - ret i399 %R -; CHECK-LABEL: @test5 -; CHECK-NEXT: %N = and i399 %M, 18446742974197923840 -; CHECK-NEXT: %A = add i399 %N, %V -; CHECK-NEXT: ret i399 %A +; CHECK-LABEL: define i399 @test5( +; CHECK-SAME: i399 [[V:%.*]], i399 [[M:%.*]]) { +; CHECK-NEXT: [[N:%.*]] = and i399 [[M]], 18446742974197923840 +; CHECK-NEXT: [[A:%.*]] = add i399 [[N]], [[V]] +; CHECK-NEXT: ret i399 [[A]] +; + %C1 = xor i399 274877906943, -1 ;; C2 = 274877906943 + %N = and i399 %M, 18446742974197923840 + %A = add i399 %V, %N + %B = and i399 %A, %C1 + %D = and i399 %V, 274877906943 + %R = or i399 %B, %D + ret i399 %R } - diff --git a/llvm/test/Transforms/InstCombine/trunc-binop-ext.ll b/llvm/test/Transforms/InstCombine/trunc-binop-ext.ll index 787df081eef2..e3103906911a 100644 --- a/llvm/test/Transforms/InstCombine/trunc-binop-ext.ll +++ b/llvm/test/Transforms/InstCombine/trunc-binop-ext.ll @@ -1,9 +1,11 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s define i16 @narrow_sext_and(i16 %x16, i32 %y32) { -; CHECK-LABEL: @narrow_sext_and( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %y32 to i16 -; CHECK-NEXT: [[R:%.*]] = and i16 [[TMP1]], %x16 +; CHECK-LABEL: define i16 @narrow_sext_and( +; CHECK-SAME: i16 [[X16:%.*]], i32 [[Y32:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y32]] to i16 +; CHECK-NEXT: [[R:%.*]] = and i16 [[TMP1]], [[X16]] ; CHECK-NEXT: ret i16 [[R]] ; %x32 = sext i16 %x16 to i32 @@ -13,9 +15,10 @@ define i16 @narrow_sext_and(i16 %x16, i32 %y32) { } define i16 @narrow_zext_and(i16 %x16, i32 %y32) { -; CHECK-LABEL: @narrow_zext_and( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %y32 to i16 -; CHECK-NEXT: [[R:%.*]] = and i16 [[TMP1]], %x16 +; CHECK-LABEL: define i16 @narrow_zext_and( +; CHECK-SAME: i16 [[X16:%.*]], i32 [[Y32:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y32]] to i16 +; CHECK-NEXT: [[R:%.*]] = and i16 [[TMP1]], [[X16]] ; CHECK-NEXT: ret i16 [[R]] ; %x32 = zext i16 %x16 to i32 @@ -25,9 +28,10 @@ define i16 @narrow_zext_and(i16 %x16, i32 %y32) { } define i16 @narrow_sext_or(i16 %x16, i32 %y32) { -; CHECK-LABEL: @narrow_sext_or( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %y32 to i16 -; CHECK-NEXT: [[R:%.*]] = or i16 [[TMP1]], %x16 +; CHECK-LABEL: define i16 @narrow_sext_or( +; CHECK-SAME: i16 [[X16:%.*]], i32 [[Y32:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y32]] to i16 +; CHECK-NEXT: [[R:%.*]] = or i16 [[TMP1]], [[X16]] ; CHECK-NEXT: ret i16 [[R]] ; %x32 = sext i16 %x16 to i32 @@ -37,9 +41,10 @@ define i16 @narrow_sext_or(i16 %x16, i32 %y32) { } define i16 @narrow_zext_or(i16 %x16, i32 %y32) { -; CHECK-LABEL: @narrow_zext_or( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %y32 to i16 -; CHECK-NEXT: [[R:%.*]] = or i16 [[TMP1]], %x16 +; CHECK-LABEL: define i16 @narrow_zext_or( +; CHECK-SAME: i16 [[X16:%.*]], i32 [[Y32:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y32]] to i16 +; CHECK-NEXT: [[R:%.*]] = or i16 [[TMP1]], [[X16]] ; CHECK-NEXT: ret i16 [[R]] ; %x32 = zext i16 %x16 to i32 @@ -49,9 +54,10 @@ define i16 @narrow_zext_or(i16 %x16, i32 %y32) { } define i16 @narrow_sext_xor(i16 %x16, i32 %y32) { -; CHECK-LABEL: @narrow_sext_xor( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %y32 to i16 -; CHECK-NEXT: [[R:%.*]] = xor i16 [[TMP1]], %x16 +; CHECK-LABEL: define i16 @narrow_sext_xor( +; CHECK-SAME: i16 [[X16:%.*]], i32 [[Y32:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y32]] to i16 +; CHECK-NEXT: [[R:%.*]] = xor i16 [[TMP1]], [[X16]] ; CHECK-NEXT: ret i16 [[R]] ; %x32 = sext i16 %x16 to i32 @@ -61,9 +67,10 @@ define i16 @narrow_sext_xor(i16 %x16, i32 %y32) { } define i16 @narrow_zext_xor(i16 %x16, i32 %y32) { -; CHECK-LABEL: @narrow_zext_xor( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %y32 to i16 -; CHECK-NEXT: [[R:%.*]] = xor i16 [[TMP1]], %x16 +; CHECK-LABEL: define i16 @narrow_zext_xor( +; CHECK-SAME: i16 [[X16:%.*]], i32 [[Y32:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y32]] to i16 +; CHECK-NEXT: [[R:%.*]] = xor i16 [[TMP1]], [[X16]] ; CHECK-NEXT: ret i16 [[R]] ; %x32 = zext i16 %x16 to i32 @@ -73,9 +80,10 @@ define i16 @narrow_zext_xor(i16 %x16, i32 %y32) { } define i16 @narrow_sext_add(i16 %x16, i32 %y32) { -; CHECK-LABEL: @narrow_sext_add( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %y32 to i16 -; CHECK-NEXT: [[R:%.*]] = add i16 [[TMP1]], %x16 +; CHECK-LABEL: define i16 @narrow_sext_add( +; CHECK-SAME: i16 [[X16:%.*]], i32 [[Y32:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y32]] to i16 +; CHECK-NEXT: [[R:%.*]] = add i16 [[TMP1]], [[X16]] ; CHECK-NEXT: ret i16 [[R]] ; %x32 = sext i16 %x16 to i32 @@ -85,9 +93,10 @@ define i16 @narrow_sext_add(i16 %x16, i32 %y32) { } define i16 @narrow_zext_add(i16 %x16, i32 %y32) { -; CHECK-LABEL: @narrow_zext_add( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %y32 to i16 -; CHECK-NEXT: [[R:%.*]] = add i16 [[TMP1]], %x16 +; CHECK-LABEL: define i16 @narrow_zext_add( +; CHECK-SAME: i16 [[X16:%.*]], i32 [[Y32:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y32]] to i16 +; CHECK-NEXT: [[R:%.*]] = add i16 [[TMP1]], [[X16]] ; CHECK-NEXT: ret i16 [[R]] ; %x32 = zext i16 %x16 to i32 @@ -97,9 +106,10 @@ define i16 @narrow_zext_add(i16 %x16, i32 %y32) { } define i16 @narrow_sext_sub(i16 %x16, i32 %y32) { -; CHECK-LABEL: @narrow_sext_sub( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %y32 to i16 -; CHECK-NEXT: [[R:%.*]] = sub i16 %x16, [[TMP1]] +; CHECK-LABEL: define i16 @narrow_sext_sub( +; CHECK-SAME: i16 [[X16:%.*]], i32 [[Y32:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y32]] to i16 +; CHECK-NEXT: [[R:%.*]] = sub i16 [[X16]], [[TMP1]] ; CHECK-NEXT: ret i16 [[R]] ; %x32 = sext i16 %x16 to i32 @@ -109,9 +119,10 @@ define i16 @narrow_sext_sub(i16 %x16, i32 %y32) { } define i16 @narrow_zext_sub(i16 %x16, i32 %y32) { -; CHECK-LABEL: @narrow_zext_sub( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %y32 to i16 -; CHECK-NEXT: [[R:%.*]] = sub i16 %x16, [[TMP1]] +; CHECK-LABEL: define i16 @narrow_zext_sub( +; CHECK-SAME: i16 [[X16:%.*]], i32 [[Y32:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y32]] to i16 +; CHECK-NEXT: [[R:%.*]] = sub i16 [[X16]], [[TMP1]] ; CHECK-NEXT: ret i16 [[R]] ; %x32 = zext i16 %x16 to i32 @@ -121,9 +132,10 @@ define i16 @narrow_zext_sub(i16 %x16, i32 %y32) { } define i16 @narrow_sext_mul(i16 %x16, i32 %y32) { -; CHECK-LABEL: @narrow_sext_mul( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %y32 to i16 -; CHECK-NEXT: [[R:%.*]] = mul i16 [[TMP1]], %x16 +; CHECK-LABEL: define i16 @narrow_sext_mul( +; CHECK-SAME: i16 [[X16:%.*]], i32 [[Y32:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y32]] to i16 +; CHECK-NEXT: [[R:%.*]] = mul i16 [[TMP1]], [[X16]] ; CHECK-NEXT: ret i16 [[R]] ; %x32 = sext i16 %x16 to i32 @@ -133,9 +145,10 @@ define i16 @narrow_sext_mul(i16 %x16, i32 %y32) { } define i16 @narrow_zext_mul(i16 %x16, i32 %y32) { -; CHECK-LABEL: @narrow_zext_mul( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %y32 to i16 -; CHECK-NEXT: [[R:%.*]] = mul i16 [[TMP1]], %x16 +; CHECK-LABEL: define i16 @narrow_zext_mul( +; CHECK-SAME: i16 [[X16:%.*]], i32 [[Y32:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[Y32]] to i16 +; CHECK-NEXT: [[R:%.*]] = mul i16 [[TMP1]], [[X16]] ; CHECK-NEXT: ret i16 [[R]] ; %x32 = zext i16 %x16 to i32 @@ -148,10 +161,11 @@ define i16 @narrow_zext_mul(i16 %x16, i32 %y32) { ; canonicalization doesn't swap the binop operands. Use vector types to show those work too. define <2 x i16> @narrow_sext_and_commute(<2 x i16> %x16, <2 x i32> %y32) { -; CHECK-LABEL: @narrow_sext_and_commute( -; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, +; CHECK-LABEL: define <2 x i16> @narrow_sext_and_commute( +; CHECK-SAME: <2 x i16> [[X16:%.*]], <2 x i32> [[Y32:%.*]]) { +; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> [[Y32]], ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16> -; CHECK-NEXT: [[R:%.*]] = and <2 x i16> [[TMP1]], %x16 +; CHECK-NEXT: [[R:%.*]] = and <2 x i16> [[TMP1]], [[X16]] ; CHECK-NEXT: ret <2 x i16> [[R]] ; %y32op0 = sdiv <2 x i32> %y32, @@ -162,10 +176,11 @@ define <2 x i16> @narrow_sext_and_commute(<2 x i16> %x16, <2 x i32> %y32) { } define <2 x i16> @narrow_zext_and_commute(<2 x i16> %x16, <2 x i32> %y32) { -; CHECK-LABEL: @narrow_zext_and_commute( -; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, +; CHECK-LABEL: define <2 x i16> @narrow_zext_and_commute( +; CHECK-SAME: <2 x i16> [[X16:%.*]], <2 x i32> [[Y32:%.*]]) { +; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> [[Y32]], ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16> -; CHECK-NEXT: [[R:%.*]] = and <2 x i16> [[TMP1]], %x16 +; CHECK-NEXT: [[R:%.*]] = and <2 x i16> [[TMP1]], [[X16]] ; CHECK-NEXT: ret <2 x i16> [[R]] ; %y32op0 = sdiv <2 x i32> %y32, @@ -176,10 +191,11 @@ define <2 x i16> @narrow_zext_and_commute(<2 x i16> %x16, <2 x i32> %y32) { } define <2 x i16> @narrow_sext_or_commute(<2 x i16> %x16, <2 x i32> %y32) { -; CHECK-LABEL: @narrow_sext_or_commute( -; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, +; CHECK-LABEL: define <2 x i16> @narrow_sext_or_commute( +; CHECK-SAME: <2 x i16> [[X16:%.*]], <2 x i32> [[Y32:%.*]]) { +; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> [[Y32]], ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16> -; CHECK-NEXT: [[R:%.*]] = or <2 x i16> [[TMP1]], %x16 +; CHECK-NEXT: [[R:%.*]] = or <2 x i16> [[TMP1]], [[X16]] ; CHECK-NEXT: ret <2 x i16> [[R]] ; %y32op0 = sdiv <2 x i32> %y32, @@ -190,10 +206,11 @@ define <2 x i16> @narrow_sext_or_commute(<2 x i16> %x16, <2 x i32> %y32) { } define <2 x i16> @narrow_zext_or_commute(<2 x i16> %x16, <2 x i32> %y32) { -; CHECK-LABEL: @narrow_zext_or_commute( -; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, +; CHECK-LABEL: define <2 x i16> @narrow_zext_or_commute( +; CHECK-SAME: <2 x i16> [[X16:%.*]], <2 x i32> [[Y32:%.*]]) { +; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> [[Y32]], ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16> -; CHECK-NEXT: [[R:%.*]] = or <2 x i16> [[TMP1]], %x16 +; CHECK-NEXT: [[R:%.*]] = or <2 x i16> [[TMP1]], [[X16]] ; CHECK-NEXT: ret <2 x i16> [[R]] ; %y32op0 = sdiv <2 x i32> %y32, @@ -204,10 +221,11 @@ define <2 x i16> @narrow_zext_or_commute(<2 x i16> %x16, <2 x i32> %y32) { } define <2 x i16> @narrow_sext_xor_commute(<2 x i16> %x16, <2 x i32> %y32) { -; CHECK-LABEL: @narrow_sext_xor_commute( -; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, +; CHECK-LABEL: define <2 x i16> @narrow_sext_xor_commute( +; CHECK-SAME: <2 x i16> [[X16:%.*]], <2 x i32> [[Y32:%.*]]) { +; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> [[Y32]], ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16> -; CHECK-NEXT: [[R:%.*]] = xor <2 x i16> [[TMP1]], %x16 +; CHECK-NEXT: [[R:%.*]] = xor <2 x i16> [[TMP1]], [[X16]] ; CHECK-NEXT: ret <2 x i16> [[R]] ; %y32op0 = sdiv <2 x i32> %y32, @@ -218,10 +236,11 @@ define <2 x i16> @narrow_sext_xor_commute(<2 x i16> %x16, <2 x i32> %y32) { } define <2 x i16> @narrow_zext_xor_commute(<2 x i16> %x16, <2 x i32> %y32) { -; CHECK-LABEL: @narrow_zext_xor_commute( -; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, +; CHECK-LABEL: define <2 x i16> @narrow_zext_xor_commute( +; CHECK-SAME: <2 x i16> [[X16:%.*]], <2 x i32> [[Y32:%.*]]) { +; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> [[Y32]], ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16> -; CHECK-NEXT: [[R:%.*]] = xor <2 x i16> [[TMP1]], %x16 +; CHECK-NEXT: [[R:%.*]] = xor <2 x i16> [[TMP1]], [[X16]] ; CHECK-NEXT: ret <2 x i16> [[R]] ; %y32op0 = sdiv <2 x i32> %y32, @@ -232,10 +251,11 @@ define <2 x i16> @narrow_zext_xor_commute(<2 x i16> %x16, <2 x i32> %y32) { } define <2 x i16> @narrow_sext_add_commute(<2 x i16> %x16, <2 x i32> %y32) { -; CHECK-LABEL: @narrow_sext_add_commute( -; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, +; CHECK-LABEL: define <2 x i16> @narrow_sext_add_commute( +; CHECK-SAME: <2 x i16> [[X16:%.*]], <2 x i32> [[Y32:%.*]]) { +; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> [[Y32]], ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16> -; CHECK-NEXT: [[R:%.*]] = add <2 x i16> [[TMP1]], %x16 +; CHECK-NEXT: [[R:%.*]] = add <2 x i16> [[TMP1]], [[X16]] ; CHECK-NEXT: ret <2 x i16> [[R]] ; %y32op0 = sdiv <2 x i32> %y32, @@ -246,10 +266,11 @@ define <2 x i16> @narrow_sext_add_commute(<2 x i16> %x16, <2 x i32> %y32) { } define <2 x i16> @narrow_zext_add_commute(<2 x i16> %x16, <2 x i32> %y32) { -; CHECK-LABEL: @narrow_zext_add_commute( -; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, +; CHECK-LABEL: define <2 x i16> @narrow_zext_add_commute( +; CHECK-SAME: <2 x i16> [[X16:%.*]], <2 x i32> [[Y32:%.*]]) { +; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> [[Y32]], ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16> -; CHECK-NEXT: [[R:%.*]] = add <2 x i16> [[TMP1]], %x16 +; CHECK-NEXT: [[R:%.*]] = add <2 x i16> [[TMP1]], [[X16]] ; CHECK-NEXT: ret <2 x i16> [[R]] ; %y32op0 = sdiv <2 x i32> %y32, @@ -260,10 +281,11 @@ define <2 x i16> @narrow_zext_add_commute(<2 x i16> %x16, <2 x i32> %y32) { } define <2 x i16> @narrow_sext_sub_commute(<2 x i16> %x16, <2 x i32> %y32) { -; CHECK-LABEL: @narrow_sext_sub_commute( -; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, +; CHECK-LABEL: define <2 x i16> @narrow_sext_sub_commute( +; CHECK-SAME: <2 x i16> [[X16:%.*]], <2 x i32> [[Y32:%.*]]) { +; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> [[Y32]], ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16> -; CHECK-NEXT: [[R:%.*]] = sub <2 x i16> [[TMP1]], %x16 +; CHECK-NEXT: [[R:%.*]] = sub <2 x i16> [[TMP1]], [[X16]] ; CHECK-NEXT: ret <2 x i16> [[R]] ; %y32op0 = sdiv <2 x i32> %y32, @@ -274,10 +296,11 @@ define <2 x i16> @narrow_sext_sub_commute(<2 x i16> %x16, <2 x i32> %y32) { } define <2 x i16> @narrow_zext_sub_commute(<2 x i16> %x16, <2 x i32> %y32) { -; CHECK-LABEL: @narrow_zext_sub_commute( -; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, +; CHECK-LABEL: define <2 x i16> @narrow_zext_sub_commute( +; CHECK-SAME: <2 x i16> [[X16:%.*]], <2 x i32> [[Y32:%.*]]) { +; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> [[Y32]], ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16> -; CHECK-NEXT: [[R:%.*]] = sub <2 x i16> [[TMP1]], %x16 +; CHECK-NEXT: [[R:%.*]] = sub <2 x i16> [[TMP1]], [[X16]] ; CHECK-NEXT: ret <2 x i16> [[R]] ; %y32op0 = sdiv <2 x i32> %y32, @@ -288,10 +311,11 @@ define <2 x i16> @narrow_zext_sub_commute(<2 x i16> %x16, <2 x i32> %y32) { } define <2 x i16> @narrow_sext_mul_commute(<2 x i16> %x16, <2 x i32> %y32) { -; CHECK-LABEL: @narrow_sext_mul_commute( -; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, +; CHECK-LABEL: define <2 x i16> @narrow_sext_mul_commute( +; CHECK-SAME: <2 x i16> [[X16:%.*]], <2 x i32> [[Y32:%.*]]) { +; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> [[Y32]], ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16> -; CHECK-NEXT: [[R:%.*]] = mul <2 x i16> [[TMP1]], %x16 +; CHECK-NEXT: [[R:%.*]] = mul <2 x i16> [[TMP1]], [[X16]] ; CHECK-NEXT: ret <2 x i16> [[R]] ; %y32op0 = sdiv <2 x i32> %y32, @@ -302,10 +326,11 @@ define <2 x i16> @narrow_sext_mul_commute(<2 x i16> %x16, <2 x i32> %y32) { } define <2 x i16> @narrow_zext_mul_commute(<2 x i16> %x16, <2 x i32> %y32) { -; CHECK-LABEL: @narrow_zext_mul_commute( -; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, +; CHECK-LABEL: define <2 x i16> @narrow_zext_mul_commute( +; CHECK-SAME: <2 x i16> [[X16:%.*]], <2 x i32> [[Y32:%.*]]) { +; CHECK-NEXT: [[Y32OP0:%.*]] = sdiv <2 x i32> [[Y32]], ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16> -; CHECK-NEXT: [[R:%.*]] = mul <2 x i16> [[TMP1]], %x16 +; CHECK-NEXT: [[R:%.*]] = mul <2 x i16> [[TMP1]], [[X16]] ; CHECK-NEXT: ret <2 x i16> [[R]] ; %y32op0 = sdiv <2 x i32> %y32, @@ -317,12 +342,13 @@ define <2 x i16> @narrow_zext_mul_commute(<2 x i16> %x16, <2 x i32> %y32) { ; Test cases for PR43580 define i8 @narrow_zext_ashr_keep_trunc(i8 %i1, i8 %i2) { -; CHECK-LABEL: @narrow_zext_ashr_keep_trunc( -; CHECK-NEXT: [[I1_EXT:%.*]] = sext i8 [[I1:%.*]] to i16 -; CHECK-NEXT: [[I2_EXT:%.*]] = sext i8 [[I2:%.*]] to i16 +; CHECK-LABEL: define i8 @narrow_zext_ashr_keep_trunc( +; CHECK-SAME: i8 [[I1:%.*]], i8 [[I2:%.*]]) { +; CHECK-NEXT: [[I1_EXT:%.*]] = sext i8 [[I1]] to i16 +; CHECK-NEXT: [[I2_EXT:%.*]] = sext i8 [[I2]] to i16 ; CHECK-NEXT: [[SUB:%.*]] = add nsw i16 [[I1_EXT]], [[I2_EXT]] -; CHECK-NEXT: [[TMP1:%.*]] = lshr i16 [[SUB]], 1 -; CHECK-NEXT: [[T:%.*]] = trunc i16 [[TMP1]] to i8 +; CHECK-NEXT: [[SHIFT:%.*]] = lshr i16 [[SUB]], 1 +; CHECK-NEXT: [[T:%.*]] = trunc i16 [[SHIFT]] to i8 ; CHECK-NEXT: ret i8 [[T]] ; %i1.ext = sext i8 %i1 to i32 @@ -334,12 +360,13 @@ define i8 @narrow_zext_ashr_keep_trunc(i8 %i1, i8 %i2) { } define i8 @narrow_zext_ashr_keep_trunc2(i9 %i1, i9 %i2) { -; CHECK-LABEL: @narrow_zext_ashr_keep_trunc2( -; CHECK-NEXT: [[I1_EXT1:%.*]] = zext i9 [[I1:%.*]] to i16 -; CHECK-NEXT: [[I2_EXT2:%.*]] = zext i9 [[I2:%.*]] to i16 -; CHECK-NEXT: [[SUB:%.*]] = add nuw nsw i16 [[I1_EXT1]], [[I2_EXT2]] -; CHECK-NEXT: [[TMP1:%.*]] = lshr i16 [[SUB]], 1 -; CHECK-NEXT: [[T:%.*]] = trunc i16 [[TMP1]] to i8 +; CHECK-LABEL: define i8 @narrow_zext_ashr_keep_trunc2( +; CHECK-SAME: i9 [[I1:%.*]], i9 [[I2:%.*]]) { +; CHECK-NEXT: [[I1_EXT:%.*]] = zext i9 [[I1]] to i16 +; CHECK-NEXT: [[I2_EXT:%.*]] = zext i9 [[I2]] to i16 +; CHECK-NEXT: [[SUB:%.*]] = add nuw nsw i16 [[I1_EXT]], [[I2_EXT]] +; CHECK-NEXT: [[SHIFT:%.*]] = lshr i16 [[SUB]], 1 +; CHECK-NEXT: [[T:%.*]] = trunc i16 [[SHIFT]] to i8 ; CHECK-NEXT: ret i8 [[T]] ; %i1.ext = sext i9 %i1 to i64 @@ -351,12 +378,13 @@ define i8 @narrow_zext_ashr_keep_trunc2(i9 %i1, i9 %i2) { } define i7 @narrow_zext_ashr_keep_trunc3(i8 %i1, i8 %i2) { -; CHECK-LABEL: @narrow_zext_ashr_keep_trunc3( -; CHECK-NEXT: [[I1_EXT1:%.*]] = zext i8 [[I1:%.*]] to i14 -; CHECK-NEXT: [[I2_EXT2:%.*]] = zext i8 [[I2:%.*]] to i14 -; CHECK-NEXT: [[SUB:%.*]] = add nuw nsw i14 [[I1_EXT1]], [[I2_EXT2]] -; CHECK-NEXT: [[TMP1:%.*]] = lshr i14 [[SUB]], 1 -; CHECK-NEXT: [[T:%.*]] = trunc i14 [[TMP1]] to i7 +; CHECK-LABEL: define i7 @narrow_zext_ashr_keep_trunc3( +; CHECK-SAME: i8 [[I1:%.*]], i8 [[I2:%.*]]) { +; CHECK-NEXT: [[I1_EXT:%.*]] = zext i8 [[I1]] to i14 +; CHECK-NEXT: [[I2_EXT:%.*]] = zext i8 [[I2]] to i14 +; CHECK-NEXT: [[SUB:%.*]] = add nuw nsw i14 [[I1_EXT]], [[I2_EXT]] +; CHECK-NEXT: [[SHIFT:%.*]] = lshr i14 [[SUB]], 1 +; CHECK-NEXT: [[T:%.*]] = trunc i14 [[SHIFT]] to i7 ; CHECK-NEXT: ret i7 [[T]] ; %i1.ext = sext i8 %i1 to i64 @@ -368,12 +396,13 @@ define i7 @narrow_zext_ashr_keep_trunc3(i8 %i1, i8 %i2) { } define <8 x i8> @narrow_zext_ashr_keep_trunc_vector(<8 x i8> %i1, <8 x i8> %i2) { -; CHECK-LABEL: @narrow_zext_ashr_keep_trunc_vector( -; CHECK-NEXT: [[I1_EXT:%.*]] = sext <8 x i8> [[I1:%.*]] to <8 x i32> -; CHECK-NEXT: [[I2_EXT:%.*]] = sext <8 x i8> [[I2:%.*]] to <8 x i32> +; CHECK-LABEL: define <8 x i8> @narrow_zext_ashr_keep_trunc_vector( +; CHECK-SAME: <8 x i8> [[I1:%.*]], <8 x i8> [[I2:%.*]]) { +; CHECK-NEXT: [[I1_EXT:%.*]] = sext <8 x i8> [[I1]] to <8 x i32> +; CHECK-NEXT: [[I2_EXT:%.*]] = sext <8 x i8> [[I2]] to <8 x i32> ; CHECK-NEXT: [[SUB:%.*]] = add nsw <8 x i32> [[I1_EXT]], [[I2_EXT]] -; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> [[SUB]], -; CHECK-NEXT: [[T:%.*]] = trunc <8 x i32> [[TMP1]] to <8 x i8> +; CHECK-NEXT: [[SHIFT:%.*]] = lshr <8 x i32> [[SUB]], +; CHECK-NEXT: [[T:%.*]] = trunc <8 x i32> [[SHIFT]] to <8 x i8> ; CHECK-NEXT: ret <8 x i8> [[T]] ; %i1.ext = sext <8 x i8> %i1 to <8 x i32> @@ -385,12 +414,13 @@ define <8 x i8> @narrow_zext_ashr_keep_trunc_vector(<8 x i8> %i1, <8 x i8> %i2) } define i8 @dont_narrow_zext_ashr_keep_trunc(i8 %i1, i8 %i2) { -; CHECK-LABEL: @dont_narrow_zext_ashr_keep_trunc( -; CHECK-NEXT: [[I1_EXT:%.*]] = sext i8 [[I1:%.*]] to i16 -; CHECK-NEXT: [[I2_EXT:%.*]] = sext i8 [[I2:%.*]] to i16 +; CHECK-LABEL: define i8 @dont_narrow_zext_ashr_keep_trunc( +; CHECK-SAME: i8 [[I1:%.*]], i8 [[I2:%.*]]) { +; CHECK-NEXT: [[I1_EXT:%.*]] = sext i8 [[I1]] to i16 +; CHECK-NEXT: [[I2_EXT:%.*]] = sext i8 [[I2]] to i16 ; CHECK-NEXT: [[SUB:%.*]] = add nsw i16 [[I1_EXT]], [[I2_EXT]] -; CHECK-NEXT: [[TMP1:%.*]] = lshr i16 [[SUB]], 1 -; CHECK-NEXT: [[T:%.*]] = trunc i16 [[TMP1]] to i8 +; CHECK-NEXT: [[SHIFT:%.*]] = lshr i16 [[SUB]], 1 +; CHECK-NEXT: [[T:%.*]] = trunc i16 [[SHIFT]] to i8 ; CHECK-NEXT: ret i8 [[T]] ; %i1.ext = sext i8 %i1 to i16 -- GitLab From 3a3aeb8eba40e981d3a9ff92175f949c2f3d4434 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 9 May 2024 13:27:20 +0900 Subject: [PATCH 103/328] [PPCMergeStringPool] Avoid replacing constant with instruction (#88846) String pool merging currently, for a reason that's not entirely clear to me, tries to create GEP instructions instead of GEP constant expressions when replacing constant references. It only uses constant expressions in cases where this is required. However, it does not catch all cases where such a requirement exists. For example, the landingpad catch clause has to be a constant. Fix this by always using the constant expression variant, which also makes the implementation simpler. Additionally, there are some edge cases where even replacement with a constant GEP is not legal. The one I am aware of is the llvm.eh.typeid.for intrinsic, so add a special case to forbid replacements for it. Fixes https://github.com/llvm/llvm-project/issues/88844. --- .../lib/Target/PowerPC/PPCMergeStringPool.cpp | 57 ++++++------------- .../PowerPC/merge-string-used-by-metadata.mir | 6 +- .../mergeable-string-pool-exceptions.ll | 47 +++++++++++++++ .../mergeable-string-pool-pass-only.mir | 18 +++--- 4 files changed, 75 insertions(+), 53 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/mergeable-string-pool-exceptions.ll diff --git a/llvm/lib/Target/PowerPC/PPCMergeStringPool.cpp b/llvm/lib/Target/PowerPC/PPCMergeStringPool.cpp index 76d60c28f1e4..abc5353e4a5e 100644 --- a/llvm/lib/Target/PowerPC/PPCMergeStringPool.cpp +++ b/llvm/lib/Target/PowerPC/PPCMergeStringPool.cpp @@ -23,6 +23,7 @@ #include "llvm/Analysis/ScalarEvolutionAliasAnalysis.h" #include "llvm/IR/Constants.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/Module.h" #include "llvm/IR/ValueSymbolTable.h" #include "llvm/Pass.h" @@ -117,9 +118,20 @@ private: // sure that they can be replaced. static bool hasReplaceableUsers(GlobalVariable &GV) { for (User *CurrentUser : GV.users()) { - // Instruction users are always valid. - if (isa(CurrentUser)) + if (auto *I = dyn_cast(CurrentUser)) { + // Do not merge globals in exception pads. + if (I->isEHPad()) + return false; + + if (auto *II = dyn_cast(I)) { + // Some intrinsics require a plain global. + if (II->getIntrinsicID() == Intrinsic::eh_typeid_for) + return false; + } + + // Other instruction users are always valid. continue; + } // We cannot replace GlobalValue users because they are not just nodes // in IR. To replace a user like this we would need to create a new @@ -314,14 +326,6 @@ void PPCMergeStringPool::replaceUsesWithGEP(GlobalVariable *GlobalToReplace, Users.push_back(CurrentUser); for (User *CurrentUser : Users) { - Instruction *UserInstruction = dyn_cast(CurrentUser); - Constant *UserConstant = dyn_cast(CurrentUser); - - // At this point we expect that the user is either an instruction or a - // constant. - assert((UserConstant || UserInstruction) && - "Expected the user to be an instruction or a constant."); - // The user was not found so it must have been replaced earlier. if (!userHasOperand(CurrentUser, GlobalToReplace)) continue; @@ -330,38 +334,13 @@ void PPCMergeStringPool::replaceUsesWithGEP(GlobalVariable *GlobalToReplace, if (isa(CurrentUser)) continue; - if (!UserInstruction) { - // User is a constant type. - Constant *ConstGEP = ConstantExpr::getInBoundsGetElementPtr( - PooledStructType, GPool, Indices); - UserConstant->handleOperandChange(GlobalToReplace, ConstGEP); - continue; - } - - if (PHINode *UserPHI = dyn_cast(UserInstruction)) { - // GEP instructions cannot be added before PHI nodes. - // With getInBoundsGetElementPtr we create the GEP and then replace it - // inline into the PHI. - Constant *ConstGEP = ConstantExpr::getInBoundsGetElementPtr( - PooledStructType, GPool, Indices); - UserPHI->replaceUsesOfWith(GlobalToReplace, ConstGEP); - continue; - } - // The user is a valid instruction that is not a PHINode. - GetElementPtrInst *GEPInst = - GetElementPtrInst::Create(PooledStructType, GPool, Indices); - GEPInst->insertBefore(UserInstruction); - - LLVM_DEBUG(dbgs() << "Inserting GEP before:\n"); - LLVM_DEBUG(UserInstruction->dump()); - + Constant *ConstGEP = ConstantExpr::getInBoundsGetElementPtr( + PooledStructType, GPool, Indices); LLVM_DEBUG(dbgs() << "Replacing this global:\n"); LLVM_DEBUG(GlobalToReplace->dump()); LLVM_DEBUG(dbgs() << "with this:\n"); - LLVM_DEBUG(GEPInst->dump()); - - // After the GEP is inserted the GV can be replaced. - CurrentUser->replaceUsesOfWith(GlobalToReplace, GEPInst); + LLVM_DEBUG(ConstGEP->dump()); + GlobalToReplace->replaceAllUsesWith(ConstGEP); } } diff --git a/llvm/test/CodeGen/PowerPC/merge-string-used-by-metadata.mir b/llvm/test/CodeGen/PowerPC/merge-string-used-by-metadata.mir index 2a791966be4e..4a40974a2a22 100644 --- a/llvm/test/CodeGen/PowerPC/merge-string-used-by-metadata.mir +++ b/llvm/test/CodeGen/PowerPC/merge-string-used-by-metadata.mir @@ -14,16 +14,14 @@ define noundef ptr @func1(ptr noundef nonnull align 8 dereferenceable(8) %this) #0 !dbg !6 { ; CHECK-LABEL: func1 - ; CHECK: %0 = getelementptr { [7 x i8], [7 x i8] }, ptr @__ModuleStringPool, i32 0, i32 1 - ; CHECK-NEXT: ret ptr %0, !dbg !14 + ; CHECK: ret ptr getelementptr inbounds ({ [7 x i8], [7 x i8] }, ptr @__ModuleStringPool, i32 0, i32 1), !dbg !14 entry: ret ptr @const.2, !dbg !14 } define noundef ptr @func2(ptr noundef nonnull align 8 dereferenceable(8) %this) #0 { ; CHECK-LABEL: func2 - ; CHECK: %0 = getelementptr { [7 x i8], [7 x i8] }, ptr @__ModuleStringPool, i32 0, i32 0 - ; CHECK-NEXT: ret ptr %0 + ; CHECK: ret ptr @__ModuleStringPool entry: ret ptr @const.1 } diff --git a/llvm/test/CodeGen/PowerPC/mergeable-string-pool-exceptions.ll b/llvm/test/CodeGen/PowerPC/mergeable-string-pool-exceptions.ll new file mode 100644 index 000000000000..03a830e087d2 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/mergeable-string-pool-exceptions.ll @@ -0,0 +1,47 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=ppc64le-unknown-linux-gnu < %s | FileCheck %s + +@id = private unnamed_addr constant [4 x i8] c"@id\00", align 1 +@id2 = private unnamed_addr constant [5 x i8] c"@id2\00", align 1 + +; Higher-aligned dummy to make sure it is first in the string pool. +@dummy = private unnamed_addr constant [1 x i32] [i32 42], align 4 + +define ptr @test1() personality ptr @__gnu_objc_personality_v0 { +; CHECK-LABEL: test1: +; CHECK: # %bb.0: +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: stdu 1, -32(1) +; CHECK-NEXT: std 0, 48(1) +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: .cfi_offset lr, 16 +; CHECK-NEXT: addis 3, 2, .Ldummy@toc@ha +; CHECK-NEXT: addi 3, 3, .Ldummy@toc@l +; CHECK-NEXT: bl foo +; CHECK-NEXT: nop + invoke void @foo(ptr @dummy) + to label %cont unwind label %unwind + +cont: + unreachable + +unwind: + %lp = landingpad { ptr, i32 } + catch ptr @id + resume { ptr, i32 } %lp +} + +define i32 @test2() personality ptr @__gnu_objc_personality_v0 { +; CHECK-LABEL: test2: +; CHECK: # %bb.0: +; CHECK-NEXT: li 3, 1 +; CHECK-NEXT: blr + %id = tail call i32 @llvm.eh.typeid.for(ptr @id2) + ret i32 %id +} + +declare i32 @__gnu_objc_personality_v0(...) + +declare i32 @llvm.eh.typeid.for(ptr) + +declare void @foo() diff --git a/llvm/test/CodeGen/PowerPC/mergeable-string-pool-pass-only.mir b/llvm/test/CodeGen/PowerPC/mergeable-string-pool-pass-only.mir index e2fb0ced8f34..3d8afb604fd3 100644 --- a/llvm/test/CodeGen/PowerPC/mergeable-string-pool-pass-only.mir +++ b/llvm/test/CodeGen/PowerPC/mergeable-string-pool-pass-only.mir @@ -35,8 +35,7 @@ ret i32 %call ; CHECK-LABEL: test1 - ; CHECK: %0 = getelementptr { [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 6 - ; CHECK: tail call signext i32 @calleeStr + ; CHECK: %call = tail call signext i32 @calleeStr(ptr noundef nonnull getelementptr inbounds ({ [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 6)) } define dso_local signext i32 @test2() local_unnamed_addr #0 { @@ -49,7 +48,7 @@ ret i32 %call ; CHECK-LABEL: test2 - ; CHECK: %0 = getelementptr { [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 2 + ; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) %A, ptr noundef nonnull align 4 dereferenceable(24) getelementptr inbounds ({ [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 2), i64 24, i1 false) ; CHECK: call signext i32 @calleeInt } @@ -62,7 +61,7 @@ call void @llvm.lifetime.end.p0(i64 28, ptr nonnull %A) #0 ret i32 %call ; CHECK-LABEL: test3 - ; CHECK: %0 = getelementptr { [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 4 + ; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(28) %A, ptr noundef nonnull align 4 dereferenceable(28) getelementptr inbounds ({ [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 4), i64 28, i1 false) ; CHECK: call signext i32 @calleeFloat } @@ -75,7 +74,7 @@ call void @llvm.lifetime.end.p0(i64 56, ptr nonnull %A) #0 ret i32 %call ; CHECK-LABEL: test4 - ; CHECK: %0 = getelementptr { [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 0 + ; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(56) %A, ptr noundef nonnull align 8 dereferenceable(56) @__ModuleStringPool, i64 56, i1 false) ; CHECK: call signext i32 @calleeDouble } @@ -102,11 +101,10 @@ call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %B) #0 ret i32 %add7 ; CHECK-LABEL: test5 - ; CHECK: %0 = getelementptr { [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 3 - ; CHECK: %1 = getelementptr { [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 5 - ; CHECK: %2 = getelementptr { [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 1 - ; CHECK: %3 = getelementptr { [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 7 - ; CHECK: call signext i32 @calleeStr + ; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) %B, ptr noundef nonnull align 4 dereferenceable(24) getelementptr inbounds ({ [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 3), i64 24, i1 false) + ; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(28) %C, ptr noundef nonnull align 4 dereferenceable(28) getelementptr inbounds ({ [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 5), i64 28, i1 false) + ; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(56) %D, ptr noundef nonnull align 8 dereferenceable(56) getelementptr inbounds ({ [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 1), i64 56, i1 false) + ; CHECK: call signext i32 @calleeStr(ptr noundef nonnull getelementptr inbounds ({ [7 x double], [7 x double], [6 x i32], [6 x i32], [7 x float], [7 x float], [8 x i8], [16 x i8] }, ptr @__ModuleStringPool, i32 0, i32 7)) ; CHECK: call signext i32 @calleeInt ; CHECK: call signext i32 @calleeFloat ; CHECK: call signext i32 @calleeDouble -- GitLab From 5baf58b628a4488de3f1a6af7c0df180358ba5dc Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 8 May 2024 21:53:15 -0700 Subject: [PATCH 104/328] [RISCV] Improve use of BSETI/BCLRI in constant materialization. (#91546) We failed to use BSETI when bit 31 was set and a few bits above bit 31 were set. We also failed to use multiple BSETI when the low 32 bits were zero. I've removed the special cases for constants 0x80000000-0xffffffff and wrote a more generic algorithm for BSETI. I've rewritten the BCLRI handling to be similar to the new BSETI algorithm. This picks up cases where bit 31 is 0 and only a few high bits are 0. --- .../Target/RISCV/MCTargetDesc/RISCVMatInt.cpp | 77 ++++++++----------- llvm/test/CodeGen/RISCV/imm.ll | 17 ++-- llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll | 17 ++-- 3 files changed, 47 insertions(+), 64 deletions(-) diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp index c3bae152993e..0a304d4cb7d9 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp @@ -310,56 +310,45 @@ InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) { } } - // Perform optimization with BCLRI/BSETI in the Zbs extension. + // Perform optimization with BSETI in the Zbs extension. if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZbs)) { - // 1. For values in range 0xffffffff 7fffffff ~ 0xffffffff 00000000, - // call generateInstSeqImpl with Val|0x80000000 (which is expected be - // an int32), then emit (BCLRI r, 31). - // 2. For values in range 0x80000000 ~ 0xffffffff, call generateInstSeqImpl - // with Val&~0x80000000 (which is expected to be an int32), then - // emit (BSETI r, 31). - int64_t NewVal; - unsigned Opc; - if (Val < 0) { - Opc = RISCV::BCLRI; - NewVal = Val | 0x80000000ll; - } else { - Opc = RISCV::BSETI; - NewVal = Val & ~0x80000000ll; - } - if (isInt<32>(NewVal)) { - RISCVMatInt::InstSeq TmpSeq; - generateInstSeqImpl(NewVal, STI, TmpSeq); - if ((TmpSeq.size() + 1) < Res.size()) { - TmpSeq.emplace_back(Opc, 31); - Res = TmpSeq; - } + // Create a simm32 value for LUI+ADDIW by forcing the upper 33 bits to zero. + // Xor that with original value to get which bits should be set by BSETI. + uint64_t Lo = Val & 0x7fffffff; + uint64_t Hi = Val ^ Lo; + assert(Hi != 0); + RISCVMatInt::InstSeq TmpSeq; + + if (Lo != 0) + generateInstSeqImpl(Lo, STI, TmpSeq); + + if (TmpSeq.size() + llvm::popcount(Hi) < Res.size()) { + do { + TmpSeq.emplace_back(RISCV::BSETI, llvm::countr_zero(Hi)); + Hi &= (Hi - 1); // Clear lowest set bit. + } while (Hi != 0); + Res = TmpSeq; } + } + + // Perform optimization with BCLRI in the Zbs extension. + if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZbs)) { + // Create a simm32 value for LUI+ADDIW by forcing the upper 33 bits to one. + // Xor that with original value to get which bits should be cleared by + // BCLRI. + uint64_t Lo = Val | 0xffffffff80000000; + uint64_t Hi = Val ^ Lo; + assert(Hi != 0); - // Try to use BCLRI for upper 32 bits if the original lower 32 bits are - // negative int32, or use BSETI for upper 32 bits if the original lower - // 32 bits are positive int32. - int32_t Lo = Lo_32(Val); - uint32_t Hi = Hi_32(Val); - Opc = 0; RISCVMatInt::InstSeq TmpSeq; generateInstSeqImpl(Lo, STI, TmpSeq); - // Check if it is profitable to use BCLRI/BSETI. - if (Lo > 0 && TmpSeq.size() + llvm::popcount(Hi) < Res.size()) { - Opc = RISCV::BSETI; - } else if (Lo < 0 && TmpSeq.size() + llvm::popcount(~Hi) < Res.size()) { - Opc = RISCV::BCLRI; - Hi = ~Hi; - } - // Search for each bit and build corresponding BCLRI/BSETI. - if (Opc > 0) { - while (Hi != 0) { - unsigned Bit = llvm::countr_zero(Hi); - TmpSeq.emplace_back(Opc, Bit + 32); + + if (TmpSeq.size() + llvm::popcount(Hi) < Res.size()) { + do { + TmpSeq.emplace_back(RISCV::BCLRI, llvm::countr_zero(Hi)); Hi &= (Hi - 1); // Clear lowest set bit. - } - if (TmpSeq.size() < Res.size()) - Res = TmpSeq; + } while (Hi != 0); + Res = TmpSeq; } } diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll index 0dc5c7ceb500..c5c1657b526a 100644 --- a/llvm/test/CodeGen/RISCV/imm.ll +++ b/llvm/test/CodeGen/RISCV/imm.ll @@ -4025,9 +4025,8 @@ define i64 @imm64_0x8000080000000() { ; ; RV64IZBS-LABEL: imm64_0x8000080000000: ; RV64IZBS: # %bb.0: -; RV64IZBS-NEXT: lui a0, 256 -; RV64IZBS-NEXT: addiw a0, a0, 1 -; RV64IZBS-NEXT: slli a0, a0, 31 +; RV64IZBS-NEXT: bseti a0, zero, 31 +; RV64IZBS-NEXT: bseti a0, a0, 51 ; RV64IZBS-NEXT: ret ; ; RV64IXTHEADBB-LABEL: imm64_0x8000080000000: @@ -4083,9 +4082,8 @@ define i64 @imm64_0x10000100000000() { ; ; RV64IZBS-LABEL: imm64_0x10000100000000: ; RV64IZBS: # %bb.0: -; RV64IZBS-NEXT: lui a0, 256 -; RV64IZBS-NEXT: addi a0, a0, 1 -; RV64IZBS-NEXT: slli a0, a0, 32 +; RV64IZBS-NEXT: bseti a0, zero, 32 +; RV64IZBS-NEXT: bseti a0, a0, 52 ; RV64IZBS-NEXT: ret ; ; RV64IXTHEADBB-LABEL: imm64_0x10000100000000: @@ -4146,10 +4144,9 @@ define i64 @imm64_0xFF7FFFFF7FFFFFFE() { ; ; RV64IZBS-LABEL: imm64_0xFF7FFFFF7FFFFFFE: ; RV64IZBS: # %bb.0: -; RV64IZBS-NEXT: lui a0, 1044480 -; RV64IZBS-NEXT: addiw a0, a0, -1 -; RV64IZBS-NEXT: slli a0, a0, 31 -; RV64IZBS-NEXT: addi a0, a0, -1 +; RV64IZBS-NEXT: li a0, -1 +; RV64IZBS-NEXT: bclri a0, a0, 31 +; RV64IZBS-NEXT: bclri a0, a0, 55 ; RV64IZBS-NEXT: ret ; ; RV64IXTHEADBB-LABEL: imm64_0xFF7FFFFF7FFFFFFE: diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll index bac4bb9ce6f1..561686374a9b 100644 --- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll +++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll @@ -2648,9 +2648,8 @@ define i64 @imm64_0x8000080000000() { ; ; RV64IZBS-LABEL: imm64_0x8000080000000: ; RV64IZBS: # %bb.0: -; RV64IZBS-NEXT: lui a0, 256 -; RV64IZBS-NEXT: addiw a0, a0, 1 -; RV64IZBS-NEXT: slli a0, a0, 31 +; RV64IZBS-NEXT: bseti a0, zero, 31 +; RV64IZBS-NEXT: bseti a0, a0, 51 ; RV64IZBS-NEXT: ret ; ; RV64IXTHEADBB-LABEL: imm64_0x8000080000000: @@ -2686,9 +2685,8 @@ define i64 @imm64_0x10000100000000() { ; ; RV64IZBS-LABEL: imm64_0x10000100000000: ; RV64IZBS: # %bb.0: -; RV64IZBS-NEXT: lui a0, 256 -; RV64IZBS-NEXT: addi a0, a0, 1 -; RV64IZBS-NEXT: slli a0, a0, 32 +; RV64IZBS-NEXT: bseti a0, zero, 32 +; RV64IZBS-NEXT: bseti a0, a0, 52 ; RV64IZBS-NEXT: ret ; ; RV64IXTHEADBB-LABEL: imm64_0x10000100000000: @@ -2727,10 +2725,9 @@ define i64 @imm64_0xFF7FFFFF7FFFFFFE() { ; ; RV64IZBS-LABEL: imm64_0xFF7FFFFF7FFFFFFE: ; RV64IZBS: # %bb.0: -; RV64IZBS-NEXT: lui a0, 1044480 -; RV64IZBS-NEXT: addiw a0, a0, -1 -; RV64IZBS-NEXT: slli a0, a0, 31 -; RV64IZBS-NEXT: addi a0, a0, -1 +; RV64IZBS-NEXT: li a0, -1 +; RV64IZBS-NEXT: bclri a0, a0, 31 +; RV64IZBS-NEXT: bclri a0, a0, 55 ; RV64IZBS-NEXT: ret ; ; RV64IXTHEADBB-LABEL: imm64_0xFF7FFFFF7FFFFFFE: -- GitLab From 666970cab2e80055cf1e5b5e9025c8f88e0d0732 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 8 May 2024 22:37:17 -0700 Subject: [PATCH 105/328] [RISCV] Remove unnecessary initialization from RISCVPostRAExpandPseudo pass constructor. It is already initialized in RISCVTargetMachine.cpp --- llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp index 57b473645ae7..52f2ce27164d 100644 --- a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp +++ b/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp @@ -31,9 +31,7 @@ public: const RISCVInstrInfo *TII; static char ID; - RISCVPostRAExpandPseudo() : MachineFunctionPass(ID) { - initializeRISCVPostRAExpandPseudoPass(*PassRegistry::getPassRegistry()); - } + RISCVPostRAExpandPseudo() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; -- GitLab From 2a57657d5571b097eb0070e6f26ad4954c0fd990 Mon Sep 17 00:00:00 2001 From: chandan singh <36783761+chandankds@users.noreply.github.com> Date: Thu, 9 May 2024 11:11:04 +0530 Subject: [PATCH 106/328] [OpenMP] [Flang] Resolved Issue llvm#76121: Implemented Check for Unhandled Arguments in __kmpc_fork_call_if (#82221) Root cause: Segmentation fault is caused by null pointer dereference inside the __kmpc_fork_call_if function at https://github.com/llvm/llvm-project/blob/main/openmp/runtime/src/z_Linux_asm.S#L1186 . __kmpc_fork_call_if is missing case to handle argc=0 . Fix: Added a check inside the __kmp_invoke_microtask function to handle the case when argc is 0. --------- Co-authored-by: Singh --- openmp/runtime/src/z_Linux_asm.S | 4 +++ .../test/misc_bugs/omp__kmpc_fork_call_if.c | 36 +++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 openmp/runtime/test/misc_bugs/omp__kmpc_fork_call_if.c diff --git a/openmp/runtime/src/z_Linux_asm.S b/openmp/runtime/src/z_Linux_asm.S index 201949003c01..5b614e26a833 100644 --- a/openmp/runtime/src/z_Linux_asm.S +++ b/openmp/runtime/src/z_Linux_asm.S @@ -1150,6 +1150,9 @@ KMP_LABEL(kmp_invoke_pass_parms): // put 1st - 6th parms to pkfn in registers. movq %rdi, %rbx // pkfn -> %rbx leaq __gtid(%rbp), %rdi // >id -> %rdi (store 1st parm to pkfn) leaq __tid(%rbp), %rsi // &tid -> %rsi (store 2nd parm to pkfn) + // Check if argc is 0 + cmpq $0, %rax + je KMP_LABEL(kmp_no_args) // Jump ahead movq %r8, %r11 // p_argv -> %r11 @@ -1195,6 +1198,7 @@ KMP_LABEL(kmp_1_exit): cmovnsq (%r11), %rdx // p_argv[0] -> %rdx (store 3rd parm to pkfn) #endif // KMP_MIC +KMP_LABEL(kmp_no_args): call *%rbx // call (*pkfn)(); movq $1, %rax // move 1 into return register; diff --git a/openmp/runtime/test/misc_bugs/omp__kmpc_fork_call_if.c b/openmp/runtime/test/misc_bugs/omp__kmpc_fork_call_if.c new file mode 100644 index 000000000000..60d4bff96787 --- /dev/null +++ b/openmp/runtime/test/misc_bugs/omp__kmpc_fork_call_if.c @@ -0,0 +1,36 @@ +// RUN: %libomp-compile && %t | FileCheck %s + +#include +#include + +typedef int32_t kmp_int32; +typedef void *ident_t; +typedef void *kmpc_micro; + +#ifdef __cplusplus +extern "C" { +#endif +extern void __kmpc_fork_call_if(ident_t *loc, kmp_int32 argc, + kmpc_micro microtask, kmp_int32 cond, + void *args); +#ifdef __cplusplus +} +#endif + +// Microtask function for parallel region +void microtask(int *global_tid, int *bound_tid) { + // CHECK: PASS + if (omp_in_parallel()) { + printf("FAIL\n"); + } else { + printf("PASS\n"); + } +} + +int main() { + // Condition for parallelization (false in this case) + int cond = 0; + // Call __kmpc_fork_call_if + __kmpc_fork_call_if(NULL, 0, microtask, cond, NULL); + return 0; +} -- GitLab From 5adcfd4c17826b2b8f023881baa1c7f79cb23920 Mon Sep 17 00:00:00 2001 From: Michael Klemm Date: Thu, 9 May 2024 08:08:55 +0200 Subject: [PATCH 107/328] [flang][CMake] Add missing dependency to generate Fortran module files (#91517) Fixes bug https://github.com/llvm/llvm-project/issues/90769. Many thanks to @Meinersbur for providing the initial thought and solution to this. --- llvm/runtimes/CMakeLists.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/runtimes/CMakeLists.txt b/llvm/runtimes/CMakeLists.txt index 3020ba72f4a6..8a3ec1e3300d 100644 --- a/llvm/runtimes/CMakeLists.txt +++ b/llvm/runtimes/CMakeLists.txt @@ -431,8 +431,10 @@ if(runtimes) set(LIBOMP_MODULES_INSTALL_PATH "${CMAKE_INSTALL_INCLUDEDIR}/flang") # TODO: This is a workaround until flang becomes a first-class project # in llvm/CMakeList.txt. Until then, this line ensures that flang-new is - # built before "openmp" is built as a runtime project. - list(APPEND extra_deps "flang-new") + # built before "openmp" is built as a runtime project. Besides "flang-new" + # to build the compiler, we also need to add "module_files" to make sure + # that all .mod files are also properly build. + list(APPEND extra_deps "flang-new" "module_files") endif() foreach(dep opt llvm-link llvm-extract clang clang-offload-packager) if(TARGET ${dep}) -- GitLab From 90ffaa6ccc6dc7351c72979da217bd3eb7fd4491 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 9 May 2024 15:04:39 +0900 Subject: [PATCH 108/328] [InstCombine] Add proper test coverage for or of xors pattern (NFC) Test all commuted variants of the pattern, most of which currently fail to fold. --- llvm/test/Transforms/InstCombine/or-xor.ll | 370 ++++++++++++++++++++- 1 file changed, 352 insertions(+), 18 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/or-xor.ll b/llvm/test/Transforms/InstCombine/or-xor.ll index 0a322d6aa023..32198c0a81dd 100644 --- a/llvm/test/Transforms/InstCombine/or-xor.ll +++ b/llvm/test/Transforms/InstCombine/or-xor.ll @@ -7,8 +7,8 @@ declare void @use(i8) define i32 @test1(i32 %x, i32 %y) { ; CHECK-LABEL: @test1( -; CHECK-NEXT: [[Y_NOT:%.*]] = xor i32 [[Y:%.*]], -1 -; CHECK-NEXT: [[Z:%.*]] = or i32 [[Y_NOT]], [[X:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], -1 +; CHECK-NEXT: [[Z:%.*]] = or i32 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: ret i32 [[Z]] ; %or = or i32 %x, %y @@ -22,8 +22,8 @@ define i32 @test1(i32 %x, i32 %y) { define i32 @test2(i32 %x, i32 %y) { ; CHECK-LABEL: @test2( -; CHECK-NEXT: [[X_NOT:%.*]] = xor i32 [[X:%.*]], -1 -; CHECK-NEXT: [[Z:%.*]] = or i32 [[X_NOT]], [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], -1 +; CHECK-NEXT: [[Z:%.*]] = or i32 [[TMP1]], [[Y:%.*]] ; CHECK-NEXT: ret i32 [[Z]] ; %or = or i32 %x, %y @@ -36,8 +36,8 @@ define i32 @test2(i32 %x, i32 %y) { define i32 @test3(i32 %x, i32 %y) { ; CHECK-LABEL: @test3( -; CHECK-NEXT: [[Y_NOT:%.*]] = xor i32 [[Y:%.*]], -1 -; CHECK-NEXT: [[Z:%.*]] = or i32 [[Y_NOT]], [[X:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], -1 +; CHECK-NEXT: [[Z:%.*]] = or i32 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: ret i32 [[Z]] ; %xor = xor i32 %x, %y @@ -51,8 +51,8 @@ define i32 @test3(i32 %x, i32 %y) { define i32 @test4(i32 %x, i32 %y) { ; CHECK-LABEL: @test4( -; CHECK-NEXT: [[X_NOT:%.*]] = xor i32 [[X:%.*]], -1 -; CHECK-NEXT: [[Z:%.*]] = or i32 [[X_NOT]], [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], -1 +; CHECK-NEXT: [[Z:%.*]] = or i32 [[TMP1]], [[Y:%.*]] ; CHECK-NEXT: ret i32 [[Z]] ; %xor = xor i32 %x, %y @@ -205,8 +205,8 @@ define i8 @xor_common_op_commute3(i8 %p, i8 %q) { define i32 @test8(i32 %x, i32 %y) { ; CHECK-LABEL: @test8( -; CHECK-NEXT: [[X_NOT:%.*]] = xor i32 [[X:%.*]], -1 -; CHECK-NEXT: [[Z:%.*]] = or i32 [[X_NOT]], [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], -1 +; CHECK-NEXT: [[Z:%.*]] = or i32 [[TMP1]], [[Y:%.*]] ; CHECK-NEXT: ret i32 [[Z]] ; %not = xor i32 %y, -1 @@ -217,8 +217,8 @@ define i32 @test8(i32 %x, i32 %y) { define i32 @test9(i32 %x, i32 %y) { ; CHECK-LABEL: @test9( -; CHECK-NEXT: [[Y_NOT:%.*]] = xor i32 [[Y:%.*]], -1 -; CHECK-NEXT: [[Z:%.*]] = or i32 [[Y_NOT]], [[X:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], -1 +; CHECK-NEXT: [[Z:%.*]] = or i32 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: ret i32 [[Z]] ; %not = xor i32 %x, -1 @@ -1097,8 +1097,8 @@ define i32 @PR75692_3(i32 %x, i32 %y) { define i32 @or_xor_not(i32 %x, i32 %y) { ; CHECK-LABEL: @or_xor_not( -; CHECK-NEXT: [[X_NOT:%.*]] = xor i32 [[X:%.*]], -1 -; CHECK-NEXT: [[OR1:%.*]] = or i32 [[X_NOT]], [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], -1 +; CHECK-NEXT: [[OR1:%.*]] = or i32 [[TMP1]], [[Y:%.*]] ; CHECK-NEXT: ret i32 [[OR1]] ; %not = xor i32 %y, -1 @@ -1140,8 +1140,8 @@ define i32 @or_xor_not_uses2(i32 %x, i32 %y) { define i32 @or_xor_and_commuted1(i32 %x, i32 %y) { ; CHECK-LABEL: @or_xor_and_commuted1( ; CHECK-NEXT: [[YY:%.*]] = mul i32 [[Y:%.*]], [[Y]] -; CHECK-NEXT: [[X_NOT:%.*]] = xor i32 [[X:%.*]], -1 -; CHECK-NEXT: [[OR1:%.*]] = or i32 [[YY]], [[X_NOT]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], -1 +; CHECK-NEXT: [[OR1:%.*]] = or i32 [[YY]], [[TMP1]] ; CHECK-NEXT: ret i32 [[OR1]] ; %yy = mul i32 %y, %y ; thwart complexity-based ordering @@ -1155,8 +1155,8 @@ define i32 @or_xor_and_commuted2(i32 %x, i32 %y) { ; CHECK-LABEL: @or_xor_and_commuted2( ; CHECK-NEXT: [[YY:%.*]] = mul i32 [[Y:%.*]], [[Y]] ; CHECK-NEXT: [[XX:%.*]] = mul i32 [[X:%.*]], [[X]] -; CHECK-NEXT: [[XX_NOT:%.*]] = xor i32 [[XX]], -1 -; CHECK-NEXT: [[OR1:%.*]] = or i32 [[YY]], [[XX_NOT]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[XX]], -1 +; CHECK-NEXT: [[OR1:%.*]] = or i32 [[YY]], [[TMP1]] ; CHECK-NEXT: ret i32 [[OR1]] ; %yy = mul i32 %y, %y ; thwart complexity-based ordering @@ -1166,3 +1166,337 @@ define i32 @or_xor_and_commuted2(i32 %x, i32 %y) { %or1 = or i32 %xor, %yy ret i32 %or1 } + +; (A ^ B) | ((B ^ C) ^ A) -> (A ^ B) | C and commuted variants. + +define i32 @or_xor_tree_0000(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_0000( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %a, %b + %xor2 = xor i32 %b, %c + %xor3 = xor i32 %xor2, %a + %or = or i32 %xor1, %xor3 + ret i32 %or +} + +define i32 @or_xor_tree_0001(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_0001( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[B]], [[C]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[XOR2]], [[A]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %b, %a + %xor2 = xor i32 %b, %c + %xor3 = xor i32 %xor2, %a + %or = or i32 %xor1, %xor3 + ret i32 %or +} + +define i32 @or_xor_tree_0010(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_0010( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[XOR2]], [[A]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %a, %b + %xor2 = xor i32 %c, %b + %xor3 = xor i32 %xor2, %a + %or = or i32 %xor1, %xor3 + ret i32 %or +} + +define i32 @or_xor_tree_0011(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_0011( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[XOR2]], [[A]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %b, %a + %xor2 = xor i32 %c, %b + %xor3 = xor i32 %xor2, %a + %or = or i32 %xor1, %xor3 + ret i32 %or +} + +define i32 @or_xor_tree_0100(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_0100( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[B]], [[C]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %a, %b + %xor2 = xor i32 %b, %c + %xor3 = xor i32 %a, %xor2 + %or = or i32 %xor1, %xor3 + ret i32 %or +} + +define i32 @or_xor_tree_0101(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_0101( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[B]], [[C]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %b, %a + %xor2 = xor i32 %b, %c + %xor3 = xor i32 %a, %xor2 + %or = or i32 %xor1, %xor3 + ret i32 %or +} + +define i32 @or_xor_tree_0110(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_0110( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %a, %b + %xor2 = xor i32 %c, %b + %xor3 = xor i32 %a, %xor2 + %or = or i32 %xor1, %xor3 + ret i32 %or +} + +define i32 @or_xor_tree_0111(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_0111( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %b, %a + %xor2 = xor i32 %c, %b + %xor3 = xor i32 %a, %xor2 + %or = or i32 %xor1, %xor3 + ret i32 %or +} + +define i32 @or_xor_tree_1000(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_1000( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %a, %b + %xor2 = xor i32 %b, %c + %xor3 = xor i32 %xor2, %a + %or = or i32 %xor3, %xor1 + ret i32 %or +} + +define i32 @or_xor_tree_1001(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_1001( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[B]], [[C]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[XOR2]], [[A]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %b, %a + %xor2 = xor i32 %b, %c + %xor3 = xor i32 %xor2, %a + %or = or i32 %xor3, %xor1 + ret i32 %or +} + +define i32 @or_xor_tree_1010(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_1010( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[XOR2]], [[A]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %a, %b + %xor2 = xor i32 %c, %b + %xor3 = xor i32 %xor2, %a + %or = or i32 %xor3, %xor1 + ret i32 %or +} + +define i32 @or_xor_tree_1011(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_1011( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[XOR2]], [[A]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %b, %a + %xor2 = xor i32 %c, %b + %xor3 = xor i32 %xor2, %a + %or = or i32 %xor3, %xor1 + ret i32 %or +} + +define i32 @or_xor_tree_1100(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_1100( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[B]], [[C]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %a, %b + %xor2 = xor i32 %b, %c + %xor3 = xor i32 %a, %xor2 + %or = or i32 %xor3, %xor1 + ret i32 %or +} + +define i32 @or_xor_tree_1101(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_1101( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[B]], [[C]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %b, %a + %xor2 = xor i32 %b, %c + %xor3 = xor i32 %a, %xor2 + %or = or i32 %xor3, %xor1 + ret i32 %or +} + +define i32 @or_xor_tree_1110(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_1110( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %a, %b + %xor2 = xor i32 %c, %b + %xor3 = xor i32 %a, %xor2 + %or = or i32 %xor3, %xor1 + ret i32 %or +} + +define i32 @or_xor_tree_1111(i32 %ax, i32 %bx, i32 %cx) { +; CHECK-LABEL: @or_xor_tree_1111( +; CHECK-NEXT: [[A:%.*]] = mul i32 [[AX:%.*]], 42 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 +; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 +; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] +; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] +; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: ret i32 [[OR]] +; + %a = mul i32 %ax, 42 + %b = mul i32 %bx, 42 + %c = mul i32 %cx, 42 + %xor1 = xor i32 %b, %a + %xor2 = xor i32 %c, %b + %xor3 = xor i32 %a, %xor2 + %or = or i32 %xor3, %xor1 + ret i32 %or +} -- GitLab From 534701d5f93369e822f3afc9670e3a42b08dfc6f Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 9 May 2024 15:06:36 +0900 Subject: [PATCH 109/328] [InstCombine] Handle commuted variants in or of xor pattern This pattern only handled commutation in the "or", while all involved operations are commutative. Make sure we handle all sixteen patterns. --- .../InstCombine/InstCombineAndOrXor.cpp | 12 ++-- llvm/test/Transforms/InstCombine/or-xor.ll | 56 +++++-------------- 2 files changed, 22 insertions(+), 46 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index ed9a89b14efc..a52c70dbdf3f 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -3599,12 +3599,16 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) { // (A ^ B) | ((B ^ C) ^ A) -> (A ^ B) | C if (match(Op0, m_Xor(m_Value(A), m_Value(B)))) - if (match(Op1, m_Xor(m_Xor(m_Specific(B), m_Value(C)), m_Specific(A)))) + if (match(Op1, + m_c_Xor(m_c_Xor(m_Specific(B), m_Value(C)), m_Specific(A))) || + match(Op1, m_c_Xor(m_c_Xor(m_Specific(A), m_Value(C)), m_Specific(B)))) return BinaryOperator::CreateOr(Op0, C); - // ((A ^ C) ^ B) | (B ^ A) -> (B ^ A) | C - if (match(Op0, m_Xor(m_Xor(m_Value(A), m_Value(C)), m_Value(B)))) - if (match(Op1, m_Xor(m_Specific(B), m_Specific(A)))) + // ((B ^ C) ^ A) | (A ^ B) -> (A ^ B) | C + if (match(Op1, m_Xor(m_Value(A), m_Value(B)))) + if (match(Op0, + m_c_Xor(m_c_Xor(m_Specific(B), m_Value(C)), m_Specific(A))) || + match(Op0, m_c_Xor(m_c_Xor(m_Specific(A), m_Value(C)), m_Specific(B)))) return BinaryOperator::CreateOr(Op1, C); if (Instruction *DeMorgan = matchDeMorgansLaws(I, *this)) diff --git a/llvm/test/Transforms/InstCombine/or-xor.ll b/llvm/test/Transforms/InstCombine/or-xor.ll index 32198c0a81dd..cf6b9000182d 100644 --- a/llvm/test/Transforms/InstCombine/or-xor.ll +++ b/llvm/test/Transforms/InstCombine/or-xor.ll @@ -1194,9 +1194,7 @@ define i32 @or_xor_tree_0001(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[B]], [[C]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[XOR2]], [[A]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1215,9 +1213,7 @@ define i32 @or_xor_tree_0010(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[XOR2]], [[A]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1236,9 +1232,7 @@ define i32 @or_xor_tree_0011(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[XOR2]], [[A]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1257,9 +1251,7 @@ define i32 @or_xor_tree_0100(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[B]], [[C]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1278,9 +1270,7 @@ define i32 @or_xor_tree_0101(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[B]], [[C]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1299,9 +1289,7 @@ define i32 @or_xor_tree_0110(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1320,9 +1308,7 @@ define i32 @or_xor_tree_0111(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[XOR3]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1360,9 +1346,7 @@ define i32 @or_xor_tree_1001(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[B]], [[C]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[XOR2]], [[A]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1381,9 +1365,7 @@ define i32 @or_xor_tree_1010(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[XOR2]], [[A]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1402,9 +1384,7 @@ define i32 @or_xor_tree_1011(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[XOR2]], [[A]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1423,9 +1403,7 @@ define i32 @or_xor_tree_1100(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[B]], [[C]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1444,9 +1422,7 @@ define i32 @or_xor_tree_1101(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[B]], [[C]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1465,9 +1441,7 @@ define i32 @or_xor_tree_1110(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], [[B]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 @@ -1486,9 +1460,7 @@ define i32 @or_xor_tree_1111(i32 %ax, i32 %bx, i32 %cx) { ; CHECK-NEXT: [[B:%.*]] = mul i32 [[BX:%.*]], 42 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[CX:%.*]], 42 ; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[B]], [[A]] -; CHECK-NEXT: [[XOR2:%.*]] = xor i32 [[C]], [[B]] -; CHECK-NEXT: [[XOR3:%.*]] = xor i32 [[A]], [[XOR2]] -; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR3]], [[XOR1]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR1]], [[C]] ; CHECK-NEXT: ret i32 [[OR]] ; %a = mul i32 %ax, 42 -- GitLab From 97be79ca126c1a0e174fdbc345a28868edc7cdc7 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 9 May 2024 15:19:29 +0900 Subject: [PATCH 110/328] [Reassociate] Generate test checks (NFC) --- .../Reassociate/fast-ArrayOutOfBounds.ll | 45 ++++++++++--------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/llvm/test/Transforms/Reassociate/fast-ArrayOutOfBounds.ll b/llvm/test/Transforms/Reassociate/fast-ArrayOutOfBounds.ll index faabd8d7815b..6dc7b89a9b18 100644 --- a/llvm/test/Transforms/Reassociate/fast-ArrayOutOfBounds.ll +++ b/llvm/test/Transforms/Reassociate/fast-ArrayOutOfBounds.ll @@ -1,25 +1,28 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt < %s -passes=reassociate,instcombine -S | FileCheck %s ; Not marked as fast, so must not change. define float @test1(float %a0, float %a1, float %a2, float %a3, float %a4) { -; CHECK-LABEL: test1 -; CHECK-NEXT: %tmp.2 = fadd float %a3, %a4 -; CHECK-NEXT: %tmp.4 = fadd float %tmp.2, %a2 -; CHECK-NEXT: %tmp.6 = fadd float %tmp.4, %a1 -; CHECK-NEXT: %tmp.8 = fadd float %tmp.6, %a0 -; CHECK-NEXT: %tmp.11 = fadd float %a2, %a3 -; CHECK-NEXT: %tmp.13 = fadd float %tmp.11, %a1 -; CHECK-NEXT: %tmp.15 = fadd float %tmp.13, %a0 -; CHECK-NEXT: %tmp.18 = fadd float %a1, %a2 -; CHECK-NEXT: %tmp.20 = fadd float %tmp.18, %a0 -; CHECK-NEXT: %tmp.23 = fadd float %a0, %a1 -; CHECK-NEXT: %tmp.26 = fsub float %tmp.8, %tmp.15 -; CHECK-NEXT: %tmp.28 = fadd float %tmp.20, %tmp.26 -; CHECK-NEXT: %tmp.30 = fsub float %tmp.28, %tmp.23 -; CHECK-NEXT: %tmp.32 = fsub float %tmp.30, %a4 -; CHECK-NEXT: %tmp.34 = fsub float %tmp.32, %a2 -; CHECK-NEXT: %T = fmul float %tmp.34, %tmp.34 -; CHECK-NEXT: ret float %T +; CHECK-LABEL: define float @test1( +; CHECK-SAME: float [[A0:%.*]], float [[A1:%.*]], float [[A2:%.*]], float [[A3:%.*]], float [[A4:%.*]]) { +; CHECK-NEXT: [[TMP_2:%.*]] = fadd float [[A3]], [[A4]] +; CHECK-NEXT: [[TMP_4:%.*]] = fadd float [[TMP_2]], [[A2]] +; CHECK-NEXT: [[TMP_6:%.*]] = fadd float [[TMP_4]], [[A1]] +; CHECK-NEXT: [[TMP_8:%.*]] = fadd float [[TMP_6]], [[A0]] +; CHECK-NEXT: [[TMP_11:%.*]] = fadd float [[A2]], [[A3]] +; CHECK-NEXT: [[TMP_13:%.*]] = fadd float [[TMP_11]], [[A1]] +; CHECK-NEXT: [[TMP_15:%.*]] = fadd float [[TMP_13]], [[A0]] +; CHECK-NEXT: [[TMP_18:%.*]] = fadd float [[A1]], [[A2]] +; CHECK-NEXT: [[TMP_20:%.*]] = fadd float [[TMP_18]], [[A0]] +; CHECK-NEXT: [[TMP_23:%.*]] = fadd float [[A0]], [[A1]] +; CHECK-NEXT: [[TMP_26:%.*]] = fsub float [[TMP_8]], [[TMP_15]] +; CHECK-NEXT: [[TMP_28:%.*]] = fadd float [[TMP_20]], [[TMP_26]] +; CHECK-NEXT: [[TMP_30:%.*]] = fsub float [[TMP_28]], [[TMP_23]] +; CHECK-NEXT: [[TMP_32:%.*]] = fsub float [[TMP_30]], [[A4]] +; CHECK-NEXT: [[TMP_34:%.*]] = fsub float [[TMP_32]], [[A2]] +; CHECK-NEXT: [[T:%.*]] = fmul float [[TMP_34]], [[TMP_34]] +; CHECK-NEXT: ret float [[T]] +; %tmp.2 = fadd float %a4, %a3 %tmp.4 = fadd float %tmp.2, %a2 @@ -42,8 +45,10 @@ define float @test1(float %a0, float %a1, float %a2, float %a3, float %a4) { ; Should be able to eliminate everything. define float @test2(float %a0, float %a1, float %a2, float %a3, float %a4) { -; CHECK-LABEL: test2 -; CHECK: ret float 0.000000e+00 +; CHECK-LABEL: define float @test2( +; CHECK-SAME: float [[A0:%.*]], float [[A1:%.*]], float [[A2:%.*]], float [[A3:%.*]], float [[A4:%.*]]) { +; CHECK-NEXT: ret float 0.000000e+00 +; %tmp.2 = fadd fast float %a4, %a3 %tmp.4 = fadd fast float %tmp.2, %a2 -- GitLab From 042a0b000dfe602ee0432be5ff88c67f531791bc Mon Sep 17 00:00:00 2001 From: Pavel Labath Date: Thu, 9 May 2024 08:37:48 +0200 Subject: [PATCH 111/328] [lldb] Make SBType::GetDirectNestedType (mostly) work with typedefs (#91189) The implementation is straight-forward, but comes with a big disclaimer. See #91186 for details. --- .../Plugins/TypeSystem/Clang/TypeSystemClang.cpp | 2 ++ lldb/test/API/python_api/type/TestTypeList.py | 16 ++++++++++++++++ lldb/test/API/python_api/type/main.cpp | 5 +++++ 3 files changed, 23 insertions(+) diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp index a771016039e8..d0033fcd9cdf 100644 --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp @@ -7106,6 +7106,8 @@ TypeSystemClang::GetDirectNestedTypeWithName(lldb::opaque_compiler_type_t type, for (NamedDecl *decl : record_decl->lookup(decl_name)) { if (auto *tag_decl = dyn_cast(decl)) return GetType(getASTContext().getTagDeclType(tag_decl)); + if (auto *typedef_decl = dyn_cast(decl)) + return GetType(getASTContext().getTypedefType(typedef_decl)); } break; } diff --git a/lldb/test/API/python_api/type/TestTypeList.py b/lldb/test/API/python_api/type/TestTypeList.py index 0498396903dc..b028929eea44 100644 --- a/lldb/test/API/python_api/type/TestTypeList.py +++ b/lldb/test/API/python_api/type/TestTypeList.py @@ -273,6 +273,22 @@ class TypeAndTypeListTestCase(TestBase): self.DebugSBType(int_enum_uchar) self.assertEqual(int_enum_uchar.GetName(), "unsigned char") + def test_nested_typedef(self): + """Exercise FindDirectNestedType for typedefs.""" + self.build() + target = self.dbg.CreateTarget(self.getBuildArtifact()) + self.assertTrue(target) + + with_nested_typedef = target.FindFirstType("WithNestedTypedef") + self.assertTrue(with_nested_typedef) + + # This is necessary to work around #91186 + self.assertTrue(target.FindFirstGlobalVariable("typedefed_value").GetType()) + + the_typedef = with_nested_typedef.FindDirectNestedType("TheTypedef") + self.assertTrue(the_typedef) + self.assertEqual(the_typedef.GetTypedefedType().GetName(), "int") + def test_GetByteAlign(self): """Exercise SBType::GetByteAlign""" self.build() diff --git a/lldb/test/API/python_api/type/main.cpp b/lldb/test/API/python_api/type/main.cpp index 986ed3009a15..6acde5bb666a 100644 --- a/lldb/test/API/python_api/type/main.cpp +++ b/lldb/test/API/python_api/type/main.cpp @@ -53,6 +53,11 @@ enum class EnumUChar : unsigned char {}; struct alignas(128) OverAlignedStruct {}; OverAlignedStruct over_aligned_struct; +struct WithNestedTypedef { + typedef int TheTypedef; +}; +WithNestedTypedef::TheTypedef typedefed_value; + int main (int argc, char const *argv[]) { Task *task_head = new Task(-1, NULL); -- GitLab From fd1bd53ba5a06f344698a55578f6a5d79c457e30 Mon Sep 17 00:00:00 2001 From: Pavel Labath Date: Thu, 9 May 2024 08:47:12 +0200 Subject: [PATCH 112/328] [lldb/aarch64] Fix unwinding when signal interrupts a leaf function (#91321) A leaf function may not store the link register to stack, but we it can still end up being a non-zero frame if it gets interrupted by a signal. Currently, we were unable to unwind past this function because we could not read the link register value. To make this work, this patch: - changes the function-entry unwind plan to include the `fp|lr = ` rules. This in turn necessitated an adjustment in the generic instruction emulation logic to ensure that `lr=[sp-X]` can override the `` rule. - allows the `` rule for pc and lr in all `m_all_registers_available` frames (and not just frame zero). The test verifies that we can unwind in a situation like this, and that the backtrace matches the one we computed before getting a signal. --- .../ARM64/EmulateInstructionARM64.cpp | 2 ++ .../UnwindAssemblyInstEmulation.cpp | 4 +--- lldb/source/Target/RegisterContextUnwind.cpp | 6 ++--- .../Inputs/signal-in-leaf-function-aarch64.c | 15 ++++++++++++ .../signal-in-leaf-function-aarch64.test | 24 +++++++++++++++++++ .../ARM64/TestArm64InstEmulation.cpp | 24 +++++++++++++++---- 6 files changed, 65 insertions(+), 10 deletions(-) create mode 100644 lldb/test/Shell/Unwind/Inputs/signal-in-leaf-function-aarch64.c create mode 100644 lldb/test/Shell/Unwind/signal-in-leaf-function-aarch64.test diff --git a/lldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp b/lldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp index 6ca4fb052457..62ecac3e0831 100644 --- a/lldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp +++ b/lldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp @@ -444,6 +444,8 @@ bool EmulateInstructionARM64::CreateFunctionEntryUnwind( // Our previous Call Frame Address is the stack pointer row->GetCFAValue().SetIsRegisterPlusOffset(gpr_sp_arm64, 0); + row->SetRegisterLocationToSame(gpr_lr_arm64, /*must_replace=*/false); + row->SetRegisterLocationToSame(gpr_fp_arm64, /*must_replace=*/false); unwind_plan.AppendRow(row); unwind_plan.SetSourceName("EmulateInstructionARM64"); diff --git a/lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp b/lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp index c4a171ec7d01..49edd40544e3 100644 --- a/lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp +++ b/lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp @@ -424,8 +424,6 @@ size_t UnwindAssemblyInstEmulation::WriteMemory( log->PutString(strm.GetString()); } - const bool cant_replace = false; - switch (context.type) { default: case EmulateInstruction::eContextInvalid: @@ -467,7 +465,7 @@ size_t UnwindAssemblyInstEmulation::WriteMemory( m_pushed_regs[reg_num] = addr; const int32_t offset = addr - m_initial_sp; m_curr_row->SetRegisterLocationToAtCFAPlusOffset(reg_num, offset, - cant_replace); + /*can_replace=*/true); m_curr_row_modified = true; } } diff --git a/lldb/source/Target/RegisterContextUnwind.cpp b/lldb/source/Target/RegisterContextUnwind.cpp index 13e101413a47..e2d712cb72ea 100644 --- a/lldb/source/Target/RegisterContextUnwind.cpp +++ b/lldb/source/Target/RegisterContextUnwind.cpp @@ -1555,12 +1555,12 @@ RegisterContextUnwind::SavedLocationForRegister( } if (unwindplan_regloc.IsSame()) { - if (!IsFrameZero() && + if (!m_all_registers_available && (regnum.GetAsKind(eRegisterKindGeneric) == LLDB_REGNUM_GENERIC_PC || regnum.GetAsKind(eRegisterKindGeneric) == LLDB_REGNUM_GENERIC_RA)) { UnwindLogMsg("register %s (%d) is marked as 'IsSame' - it is a pc or " - "return address reg on a non-zero frame -- treat as if we " - "have no information", + "return address reg on a frame which does not have all " + "registers available -- treat as if we have no information", regnum.GetName(), regnum.GetAsKind(eRegisterKindLLDB)); return UnwindLLDB::RegisterSearchResult::eRegisterNotFound; } else { diff --git a/lldb/test/Shell/Unwind/Inputs/signal-in-leaf-function-aarch64.c b/lldb/test/Shell/Unwind/Inputs/signal-in-leaf-function-aarch64.c new file mode 100644 index 000000000000..9a751330623f --- /dev/null +++ b/lldb/test/Shell/Unwind/Inputs/signal-in-leaf-function-aarch64.c @@ -0,0 +1,15 @@ +#include +#include + +int __attribute__((naked)) signal_generating_add(int a, int b) { + asm("add w0, w1, w0\n\t" + "udf #0xdead\n\t" + "ret"); +} + +void sigill_handler(int) { _exit(0); } + +int main() { + signal(SIGILL, sigill_handler); + return signal_generating_add(42, 47); +} diff --git a/lldb/test/Shell/Unwind/signal-in-leaf-function-aarch64.test b/lldb/test/Shell/Unwind/signal-in-leaf-function-aarch64.test new file mode 100644 index 000000000000..0580d0cf734a --- /dev/null +++ b/lldb/test/Shell/Unwind/signal-in-leaf-function-aarch64.test @@ -0,0 +1,24 @@ +# REQUIRES: target-aarch64 && native +# UNSUPPORTED: system-windows + +# RUN: %clang_host %S/Inputs/signal-in-leaf-function-aarch64.c -o %t +# RUN: %lldb -s %s -o exit %t | FileCheck %s + +breakpoint set -n sigill_handler +# CHECK: Breakpoint 1: where = {{.*}}`sigill_handler + +run +# CHECK: thread #1, {{.*}} stop reason = signal SIGILL + +thread backtrace +# CHECK: frame #0: [[ADD:0x[0-9a-fA-F]*]] {{.*}}`signal_generating_add +# CHECK: frame #1: [[MAIN:0x[0-9a-fA-F]*]] {{.*}}`main + +continue +# CHECK: thread #1, {{.*}} stop reason = breakpoint 1 + +thread backtrace +# CHECK: frame #0: {{.*}}`sigill_handler +# Unknown number of signal trampoline frames +# CHECK: frame #{{[0-9]+}}: [[ADD]] {{.*}}`signal_generating_add +# CHECK: frame #{{[0-9]+}}: [[MAIN]] {{.*}}`main diff --git a/lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp b/lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp index 80abeb8fae9e..9303d6f5f3c6 100644 --- a/lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp +++ b/lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp @@ -77,7 +77,7 @@ TEST_F(TestArm64InstEmulation, TestSimpleDarwinFunction) { // UnwindPlan we expect: - // row[0]: 0: CFA=sp +0 => + // row[0]: 0: CFA=sp +0 => fp= lr= // row[1]: 4: CFA=sp+16 => fp=[CFA-16] lr=[CFA-8] // row[2]: 8: CFA=fp+16 => fp=[CFA-16] lr=[CFA-8] // row[2]: 16: CFA=sp+16 => fp=[CFA-16] lr=[CFA-8] @@ -88,13 +88,19 @@ TEST_F(TestArm64InstEmulation, TestSimpleDarwinFunction) { EXPECT_TRUE(engine->GetNonCallSiteUnwindPlanFromAssembly( sample_range, data, sizeof(data), unwind_plan)); - // CFA=sp +0 + // CFA=sp +0 => fp= lr= row_sp = unwind_plan.GetRowForFunctionOffset(0); EXPECT_EQ(0ull, row_sp->GetOffset()); EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); + EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_fp_arm64, regloc)); + EXPECT_TRUE(regloc.IsSame()); + + EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_arm64, regloc)); + EXPECT_TRUE(regloc.IsSame()); + // CFA=sp+16 => fp=[CFA-16] lr=[CFA-8] row_sp = unwind_plan.GetRowForFunctionOffset(4); EXPECT_EQ(4ull, row_sp->GetOffset()); @@ -146,6 +152,12 @@ TEST_F(TestArm64InstEmulation, TestSimpleDarwinFunction) { EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); + + EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_fp_arm64, regloc)); + EXPECT_TRUE(regloc.IsSame()); + + EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_arm64, regloc)); + EXPECT_TRUE(regloc.IsSame()); } TEST_F(TestArm64InstEmulation, TestMediumDarwinFunction) { @@ -381,8 +393,12 @@ TEST_F(TestArm64InstEmulation, TestFramelessThreeEpilogueFunction) { EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x26_arm64, regloc)); EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x27_arm64, regloc)); EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x28_arm64, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_fp_arm64, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_lr_arm64, regloc)); + + EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_fp_arm64, regloc)); + EXPECT_TRUE(regloc.IsSame()); + + EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_arm64, regloc)); + EXPECT_TRUE(regloc.IsSame()); row_sp = unwind_plan.GetRowForFunctionOffset(36); EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64); -- GitLab From dec8055a1e71fe25d4b85416ede742e8fdfaf3f0 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Wed, 8 May 2024 23:52:22 -0700 Subject: [PATCH 113/328] [mlir] Use StringRef::operator== instead of StringRef::equals (NFC) (#91560) I'm planning to remove StringRef::equals in favor of StringRef::operator==. - StringRef::operator==/!= outnumber StringRef::equals by a factor of 10 under mlir/ in terms of their usage. - The elimination of StringRef::equals brings StringRef closer to std::string_view, which has operator== but not equals. - S == "foo" is more readable than S.equals("foo"), especially for !Long.Expression.equals("str") vs Long.Expression != "str". --- .../Conversion/GPUCommon/GPUToLLVMConversion.cpp | 2 +- mlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp | 16 ++++++++-------- mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp | 2 +- mlir/lib/Dialect/Affine/IR/AffineOps.cpp | 14 ++++++-------- mlir/lib/Dialect/GPU/IR/GPUDialect.cpp | 13 +++++-------- mlir/lib/Dialect/LLVMIR/IR/TypeDetail.h | 3 +-- mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp | 14 ++++++-------- .../SparseTensor/IR/Detail/LvlTypeParser.cpp | 6 +++--- mlir/lib/IR/AttributeDetail.h | 2 +- mlir/lib/TableGen/Builder.cpp | 2 +- .../Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp | 4 ++-- mlir/test/lib/Dialect/Test/TestOpsSyntax.cpp | 2 +- mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp | 2 +- mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp | 4 ++-- 14 files changed, 39 insertions(+), 47 deletions(-) diff --git a/mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp b/mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp index 3a4fc7d8063f..82bfa9514a88 100644 --- a/mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp +++ b/mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp @@ -926,7 +926,7 @@ LogicalResult ConvertAsyncYieldToGpuRuntimeCallPattern::matchAndRewrite( static bool isDefinedByCallTo(Value value, StringRef functionName) { assert(isa(value.getType())); if (auto defOp = value.getDefiningOp()) - return defOp.getCallee()->equals(functionName); + return *defOp.getCallee() == functionName; return false; } diff --git a/mlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp b/mlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp index 775dd1e60903..b7fd454c6090 100644 --- a/mlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp +++ b/mlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp @@ -42,11 +42,11 @@ static LogicalResult areAllLLVMTypes(Operation *op, ValueRange operands, static constexpr StringRef kInvalidCaseStr = "Unsupported WMMA variant."; static NVVM::MMAFrag convertOperand(StringRef operandName) { - if (operandName.equals("AOp")) + if (operandName == "AOp") return NVVM::MMAFrag::a; - if (operandName.equals("BOp")) + if (operandName == "BOp") return NVVM::MMAFrag::b; - if (operandName.equals("COp")) + if (operandName == "COp") return NVVM::MMAFrag::c; llvm_unreachable("Unknown operand name"); } @@ -55,8 +55,8 @@ static NVVM::MMATypes getElementType(gpu::MMAMatrixType type) { if (type.getElementType().isF16()) return NVVM::MMATypes::f16; if (type.getElementType().isF32()) - return type.getOperand().equals("COp") ? NVVM::MMATypes::f32 - : NVVM::MMATypes::tf32; + return type.getOperand() == "COp" ? NVVM::MMATypes::f32 + : NVVM::MMATypes::tf32; if (type.getElementType().isSignedInteger(8)) return NVVM::MMATypes::s8; @@ -99,15 +99,15 @@ struct WmmaLoadOpToNVVMLowering NVVM::MMATypes eltype = getElementType(retType); // NVVM intrinsics require to give mxnxk dimensions, infer the missing // dimension based on the valid intrinsics available. - if (retType.getOperand().equals("AOp")) { + if (retType.getOperand() == "AOp") { m = retTypeShape[0]; k = retTypeShape[1]; n = NVVM::WMMALoadOp::inferNDimension(m, k, eltype); - } else if (retType.getOperand().equals("BOp")) { + } else if (retType.getOperand() == "BOp") { k = retTypeShape[0]; n = retTypeShape[1]; m = NVVM::WMMALoadOp::inferMDimension(k, n, eltype); - } else if (retType.getOperand().equals("COp")) { + } else if (retType.getOperand() == "COp") { m = retTypeShape[0]; n = retTypeShape[1]; k = NVVM::WMMALoadOp::inferKDimension(m, n, eltype); diff --git a/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp b/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp index f8485e02a220..19f02297bfbb 100644 --- a/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp +++ b/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp @@ -261,7 +261,7 @@ static void maybeApplyPassLabel(OpBuilder &b, OpTy newXferOp, template static bool isTensorOp(OpTy xferOp) { if (isa(xferOp.getShapedType())) { - if (xferOp.getOperationName().equals(TransferWriteOp::getOperationName())) { + if (xferOp.getOperationName() == TransferWriteOp::getOperationName()) { // TransferWriteOps on tensors have a result. assert(xferOp->getNumResults() > 0); } diff --git a/mlir/lib/Dialect/Affine/IR/AffineOps.cpp b/mlir/lib/Dialect/Affine/IR/AffineOps.cpp index c9c0a7b4cc68..2e31487bd55a 100644 --- a/mlir/lib/Dialect/Affine/IR/AffineOps.cpp +++ b/mlir/lib/Dialect/Affine/IR/AffineOps.cpp @@ -3585,20 +3585,18 @@ ParseResult AffinePrefetchOp::parse(OpAsmParser &parser, parser.resolveOperands(mapOperands, indexTy, result.operands)) return failure(); - if (!readOrWrite.equals("read") && !readOrWrite.equals("write")) + if (readOrWrite != "read" && readOrWrite != "write") return parser.emitError(parser.getNameLoc(), "rw specifier has to be 'read' or 'write'"); - result.addAttribute( - AffinePrefetchOp::getIsWriteAttrStrName(), - parser.getBuilder().getBoolAttr(readOrWrite.equals("write"))); + result.addAttribute(AffinePrefetchOp::getIsWriteAttrStrName(), + parser.getBuilder().getBoolAttr(readOrWrite == "write")); - if (!cacheType.equals("data") && !cacheType.equals("instr")) + if (cacheType != "data" && cacheType != "instr") return parser.emitError(parser.getNameLoc(), "cache type has to be 'data' or 'instr'"); - result.addAttribute( - AffinePrefetchOp::getIsDataCacheAttrStrName(), - parser.getBuilder().getBoolAttr(cacheType.equals("data"))); + result.addAttribute(AffinePrefetchOp::getIsDataCacheAttrStrName(), + parser.getBuilder().getBoolAttr(cacheType == "data")); return success(); } diff --git a/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp b/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp index f1b9ca5c5002..0c2590d71130 100644 --- a/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp +++ b/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp @@ -152,8 +152,7 @@ LogicalResult MMAMatrixType::verify(function_ref emitError, ArrayRef shape, Type elementType, StringRef operand) { - if (!operand.equals("AOp") && !operand.equals("BOp") && - !operand.equals("COp")) + if (operand != "AOp" && operand != "BOp" && operand != "COp") return emitError() << "operand expected to be one of AOp, BOp or COp"; if (shape.size() != 2) @@ -1941,8 +1940,7 @@ LogicalResult SubgroupMmaLoadMatrixOp::verify() { return emitError( "expected source memref most minor dim must have unit stride"); - if (!operand.equals("AOp") && !operand.equals("BOp") && - !operand.equals("COp")) + if (operand != "AOp" && operand != "BOp" && operand != "COp") return emitError("only AOp, BOp and COp can be loaded"); return success(); @@ -1962,7 +1960,7 @@ LogicalResult SubgroupMmaStoreMatrixOp::verify() { return emitError( "expected destination memref most minor dim must have unit stride"); - if (!srcMatrixType.getOperand().equals("COp")) + if (srcMatrixType.getOperand() != "COp") return emitError( "expected the operand matrix being stored to have 'COp' operand type"); @@ -1980,9 +1978,8 @@ LogicalResult SubgroupMmaComputeOp::verify() { opTypes.push_back(llvm::cast(getOpB().getType())); opTypes.push_back(llvm::cast(getOpC().getType())); - if (!opTypes[A].getOperand().equals("AOp") || - !opTypes[B].getOperand().equals("BOp") || - !opTypes[C].getOperand().equals("COp")) + if (opTypes[A].getOperand() != "AOp" || opTypes[B].getOperand() != "BOp" || + opTypes[C].getOperand() != "COp") return emitError("operands must be in the order AOp, BOp, COp"); ArrayRef aShape, bShape, cShape; diff --git a/mlir/lib/Dialect/LLVMIR/IR/TypeDetail.h b/mlir/lib/Dialect/LLVMIR/IR/TypeDetail.h index 2040d0a06b2e..8767b1c3ffc5 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/TypeDetail.h +++ b/mlir/lib/Dialect/LLVMIR/IR/TypeDetail.h @@ -131,8 +131,7 @@ public: /// Compares two keys. bool operator==(const Key &other) const { if (isIdentified()) - return other.isIdentified() && - other.getIdentifier().equals(getIdentifier()); + return other.isIdentified() && other.getIdentifier() == getIdentifier(); return !other.isIdentified() && other.isPacked() == isPacked() && other.getTypeList() == getTypeList(); diff --git a/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp b/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp index c9a85919ec79..199e7330a233 100644 --- a/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp +++ b/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp @@ -1742,20 +1742,18 @@ ParseResult PrefetchOp::parse(OpAsmParser &parser, OperationState &result) { parser.resolveOperands(indexInfo, indexTy, result.operands)) return failure(); - if (!readOrWrite.equals("read") && !readOrWrite.equals("write")) + if (readOrWrite != "read" && readOrWrite != "write") return parser.emitError(parser.getNameLoc(), "rw specifier has to be 'read' or 'write'"); - result.addAttribute( - PrefetchOp::getIsWriteAttrStrName(), - parser.getBuilder().getBoolAttr(readOrWrite.equals("write"))); + result.addAttribute(PrefetchOp::getIsWriteAttrStrName(), + parser.getBuilder().getBoolAttr(readOrWrite == "write")); - if (!cacheType.equals("data") && !cacheType.equals("instr")) + if (cacheType != "data" && cacheType != "instr") return parser.emitError(parser.getNameLoc(), "cache type has to be 'data' or 'instr'"); - result.addAttribute( - PrefetchOp::getIsDataCacheAttrStrName(), - parser.getBuilder().getBoolAttr(cacheType.equals("data"))); + result.addAttribute(PrefetchOp::getIsDataCacheAttrStrName(), + parser.getBuilder().getBoolAttr(cacheType == "data")); return success(); } diff --git a/mlir/lib/Dialect/SparseTensor/IR/Detail/LvlTypeParser.cpp b/mlir/lib/Dialect/SparseTensor/IR/Detail/LvlTypeParser.cpp index 92e5efaa8104..39f5cf1a7508 100644 --- a/mlir/lib/Dialect/SparseTensor/IR/Detail/LvlTypeParser.cpp +++ b/mlir/lib/Dialect/SparseTensor/IR/Detail/LvlTypeParser.cpp @@ -89,11 +89,11 @@ ParseResult LvlTypeParser::parseProperty(AsmParser &parser, auto loc = parser.getCurrentLocation(); ERROR_IF(failed(parser.parseOptionalKeyword(&strVal)), "expected valid level property (e.g. nonordered, nonunique or high)") - if (strVal.equals(toPropString(LevelPropNonDefault::Nonunique))) { + if (strVal == toPropString(LevelPropNonDefault::Nonunique)) { *properties |= static_cast(LevelPropNonDefault::Nonunique); - } else if (strVal.equals(toPropString(LevelPropNonDefault::Nonordered))) { + } else if (strVal == toPropString(LevelPropNonDefault::Nonordered)) { *properties |= static_cast(LevelPropNonDefault::Nonordered); - } else if (strVal.equals(toPropString(LevelPropNonDefault::SoA))) { + } else if (strVal == toPropString(LevelPropNonDefault::SoA)) { *properties |= static_cast(LevelPropNonDefault::SoA); } else { parser.emitError(loc, "unknown level property: ") << strVal; diff --git a/mlir/lib/IR/AttributeDetail.h b/mlir/lib/IR/AttributeDetail.h index dcd24af0107d..26d40ac3a38f 100644 --- a/mlir/lib/IR/AttributeDetail.h +++ b/mlir/lib/IR/AttributeDetail.h @@ -261,7 +261,7 @@ struct DenseStringElementsAttrStorage : public DenseElementsAttributeStorage { // Check to see if this storage represents a splat. If it doesn't then // combine the hash for the data starting with the first non splat element. for (size_t i = 1, e = data.size(); i != e; i++) - if (!firstElt.equals(data[i])) + if (firstElt != data[i]) return KeyTy(ty, data, llvm::hash_combine(hashVal, data.drop_front(i))); // Otherwise, this is a splat so just return the hash of the first element. diff --git a/mlir/lib/TableGen/Builder.cpp b/mlir/lib/TableGen/Builder.cpp index 47a2f6cc4456..044765c72601 100644 --- a/mlir/lib/TableGen/Builder.cpp +++ b/mlir/lib/TableGen/Builder.cpp @@ -52,7 +52,7 @@ Builder::Builder(const llvm::Record *record, ArrayRef loc) // Initialize the parameters of the builder. const llvm::DagInit *dag = def->getValueAsDag("dagParams"); auto *defInit = dyn_cast(dag->getOperator()); - if (!defInit || !defInit->getDef()->getName().equals("ins")) + if (!defInit || defInit->getDef()->getName() != "ins") PrintFatalError(def->getLoc(), "expected 'ins' in builders"); bool seenDefaultValue = false; diff --git a/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp index 40d8253d822f..06673965245c 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp @@ -93,7 +93,7 @@ static LogicalResult setProfilingAttr(OpBuilder &builder, llvm::MDNode *node, return failure(); // Handle function entry count metadata. - if (name->getString().equals("function_entry_count")) { + if (name->getString() == "function_entry_count") { // TODO support function entry count metadata with GUID fields. if (node->getNumOperands() != 2) @@ -111,7 +111,7 @@ static LogicalResult setProfilingAttr(OpBuilder &builder, llvm::MDNode *node, << "expected function_entry_count to be attached to a function"; } - if (!name->getString().equals("branch_weights")) + if (name->getString() != "branch_weights") return failure(); // Handle branch weights metadata. diff --git a/mlir/test/lib/Dialect/Test/TestOpsSyntax.cpp b/mlir/test/lib/Dialect/Test/TestOpsSyntax.cpp index c376d6c73c64..ebaced57a24a 100644 --- a/mlir/test/lib/Dialect/Test/TestOpsSyntax.cpp +++ b/mlir/test/lib/Dialect/Test/TestOpsSyntax.cpp @@ -413,7 +413,7 @@ void PrettyPrintedRegionOp::print(OpAsmPrinter &p) { // of inner-op), then we can print the entire region in a succinct way. // Here we assume that the prototype of "test.special.op" can be trivially // derived while parsing it back. - if (innerOp.getName().getStringRef().equals("test.special.op")) { + if (innerOp.getName().getStringRef() == "test.special.op") { p << " start test.special.op end"; } else { p << " ("; diff --git a/mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp b/mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp index b9a72119790e..55bc0714c20e 100644 --- a/mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp +++ b/mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp @@ -50,7 +50,7 @@ static void collectAllDefs(StringRef selectedDialect, } else { // Otherwise, generate the defs that belong to the selected dialect. auto dialectDefs = llvm::make_filter_range(defs, [&](const auto &def) { - return def.getDialect().getName().equals(selectedDialect); + return def.getDialect().getName() == selectedDialect; }); resultDefs.assign(dialectDefs.begin(), dialectDefs.end()); } diff --git a/mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp b/mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp index 814008c25451..052020acdcb7 100644 --- a/mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp +++ b/mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp @@ -457,7 +457,7 @@ static void emitAttributeAccessors(const Operator &op, raw_ostream &os) { std::string sanitizedName = sanitizeName(namedAttr.name); // Unit attributes are handled specially. - if (namedAttr.attr.getStorageType().trim().equals("::mlir::UnitAttr")) { + if (namedAttr.attr.getStorageType().trim() == "::mlir::UnitAttr") { os << llvm::formatv(unitAttributeGetterTemplate, sanitizedName, namedAttr.name); os << llvm::formatv(unitAttributeSetterTemplate, sanitizedName, @@ -668,7 +668,7 @@ populateBuilderLinesAttr(const Operator &op, continue; // Unit attributes are handled specially. - if (attribute->attr.getStorageType().trim().equals("::mlir::UnitAttr")) { + if (attribute->attr.getStorageType().trim() == "::mlir::UnitAttr") { builderLines.push_back(llvm::formatv(initUnitAttributeTemplate, attribute->name, argNames[i])); continue; -- GitLab From aacea0d0f67401f5a0b74947f3ff179ade9cbf6d Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Wed, 8 May 2024 23:58:55 -0700 Subject: [PATCH 114/328] [utils] Add script to generate elaborated IR and assembly tests (#89026) Generally, IR and assembly test files benefit from being cleaned to remove unnecessary details. However, for tests requiring elaborate IR or assembly files where cleanup is less practical (e.g., large amount of debug information output from Clang), the current practice is to include the C/C++ source file and the generation instructions as comments. This is inconvenient when regeneration is needed. This patch adds `llvm/utils/update_test_body.py` to allow easier regeneration. `ld.lld --debug-names` tests (#86508) utilize this script for Clang-generated assembly tests. Note: `-o pipefail` is standard (since https://www.austingroupbugs.net/view.php?id=789) but not supported by dash. Link: https://discourse.llvm.org/t/utility-to-generate-elaborated-assembly-ir-tests/78408 --- llvm/docs/TestingGuide.rst | 81 +++++++++++++ .../test/tools/UpdateTestChecks/lit.local.cfg | 7 +- .../Inputs/basic-asm.test.expected | 13 +++ .../Inputs/basic.test.expected | 16 +++ .../update_test_body/basic-asm.test | 11 ++ .../update_test_body/basic.test | 13 +++ .../update_test_body/empty-stdout.test | 13 +++ .../update_test_body/gen-absent.test | 7 ++ .../update_test_body/gen-fail.test | 11 ++ .../update_test_body/gen-unterminated.test | 8 ++ .../update_test_body/lit.local.cfg | 4 + .../tools/llvm-dwarfdump/X86/formclass4.s | 26 +++-- .../X86/prettyprint_type_units_split_v5.s | 14 +-- llvm/utils/update_test_body.py | 110 ++++++++++++++++++ 14 files changed, 314 insertions(+), 20 deletions(-) create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_body/Inputs/basic-asm.test.expected create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_body/Inputs/basic.test.expected create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_body/basic-asm.test create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_body/basic.test create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_body/empty-stdout.test create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_body/gen-absent.test create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_body/gen-fail.test create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_body/gen-unterminated.test create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_body/lit.local.cfg create mode 100755 llvm/utils/update_test_body.py diff --git a/llvm/docs/TestingGuide.rst b/llvm/docs/TestingGuide.rst index e32e4d1e535a..e24feb3bf5fa 100644 --- a/llvm/docs/TestingGuide.rst +++ b/llvm/docs/TestingGuide.rst @@ -433,6 +433,87 @@ actually participate in the test besides holding the ``RUN:`` lines. putting the extra files in an ``Inputs/`` directory. This pattern is deprecated. +Elaborated tests +---------------- + +Generally, IR and assembly test files benefit from being cleaned to remove +unnecessary details. However, for tests requiring elaborate IR or assembly +files where cleanup is less practical (e.g., large amount of debug information +output from Clang), you can include generation instructions within +``split-file`` part called ``gen``. Then, run +``llvm/utils/update_test_body.py`` on the test file to generate the needed +content. + +.. code-block:: none + + ; RUN: rm -rf %t && split-file %s %t && cd %t + ; RUN: opt -S a.ll ... | FileCheck %s + + ; CHECK: hello + + ;--- a.cc + int va; + ;--- gen + clang --target=x86_64-linux -S -emit-llvm -g a.cc -o - + + ;--- a.ll + # content generated by the script 'gen' + +.. code-block:: bash + + PATH=/path/to/clang_build/bin:$PATH llvm/utils/update_test_body.py path/to/test.ll + +The script will prepare extra files with ``split-file``, invoke ``gen``, and +then rewrite the part after ``gen`` with its stdout. + +For convenience, if the test needs one single assembly file, you can also wrap +``gen`` and its required files with ``.ifdef`` and ``.endif``. Then you can +skip ``split-file`` in RUN lines. + +.. code-block:: none + + # RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o a.o + # RUN: ... | FileCheck %s + + # CHECK: hello + + .ifdef GEN + #--- a.cc + int va; + #--- gen + clang --target=x86_64-linux -S -g a.cc -o - + .endif + # content generated by the script 'gen' + +.. note:: + + Consider specifying an explicit target triple to avoid differences when + regeneration is needed on another machine. + + ``gen`` is invoked with ``PWD`` set to ``/proc/self/cwd``. Clang commands + don't need ``-fdebug-compilation-dir=`` since its default value is ``PWD``. + + Check prefixes should be placed before ``.endif`` since the part after + ``.endif`` is replaced. + +If the test body contains multiple files, you can print ``---`` separators and +utilize ``split-file`` in ``RUN`` lines. + +.. code-block:: none + + # RUN: rm -rf %t && split-file %s %t && cd %t + ... + + #--- a.cc + int va; + #--- b.cc + int vb; + #--- gen + clang --target=x86_64-linux -S -O1 -g a.cc -o - + echo '#--- b.s' + clang --target=x86_64-linux -S -O1 -g b.cc -o - + #--- a.s + Fragile tests ------------- diff --git a/llvm/test/tools/UpdateTestChecks/lit.local.cfg b/llvm/test/tools/UpdateTestChecks/lit.local.cfg index f8ab6b82cde7..2e695490b005 100644 --- a/llvm/test/tools/UpdateTestChecks/lit.local.cfg +++ b/llvm/test/tools/UpdateTestChecks/lit.local.cfg @@ -19,7 +19,8 @@ def add_update_script_substition( # Specify an explicit default version in UTC tests, so that the --version # embedded in UTC_ARGS does not change in all test expectations every time # the default is bumped. - extra_args += " --version=1" + if name != "%update_test_body": + extra_args += " --version=1" config.substitutions.append( (name, "'%s' %s %s" % (python_exe, script_path, extra_args)) ) @@ -47,3 +48,7 @@ if os.path.isfile(llvm_mca_path): config.available_features.add("llvm-mca-binary") mca_arg = "--llvm-mca-binary " + shell_quote(llvm_mca_path) add_update_script_substition("%update_test_checks", extra_args=mca_arg) + +split_file_path = os.path.join(config.llvm_tools_dir, "split-file") +if os.path.isfile(split_file_path): + add_update_script_substition("%update_test_body") diff --git a/llvm/test/tools/UpdateTestChecks/update_test_body/Inputs/basic-asm.test.expected b/llvm/test/tools/UpdateTestChecks/update_test_body/Inputs/basic-asm.test.expected new file mode 100644 index 000000000000..05024d8799cd --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_test_body/Inputs/basic-asm.test.expected @@ -0,0 +1,13 @@ +# RUN: cp %s %t && %update_test_body %t 2>&1 | count 0 +# RUN: diff -u %S/Inputs/basic-asm.test.expected %t + +.ifdef GEN +#--- a.txt +.long 0 +#--- b.txt +.long 1 +#--- gen +cat a.txt b.txt +.endif +.long 0 +.long 1 diff --git a/llvm/test/tools/UpdateTestChecks/update_test_body/Inputs/basic.test.expected b/llvm/test/tools/UpdateTestChecks/update_test_body/Inputs/basic.test.expected new file mode 100644 index 000000000000..80a2676d0a75 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_test_body/Inputs/basic.test.expected @@ -0,0 +1,16 @@ +; RUN: cp %s %t && %update_test_body %t 2>&1 | count 0 +; RUN: diff -u %S/Inputs/basic.test.expected %t + +;--- a.txt +@a = global i32 0 +;--- b.txt +@b = global i32 0 +;--- gen +cat a.txt +echo ';--- b.ll' +cat b.txt + +;--- a.ll +@a = global i32 0 +;--- b.ll +@b = global i32 0 diff --git a/llvm/test/tools/UpdateTestChecks/update_test_body/basic-asm.test b/llvm/test/tools/UpdateTestChecks/update_test_body/basic-asm.test new file mode 100644 index 000000000000..3e82a3ffab9a --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_test_body/basic-asm.test @@ -0,0 +1,11 @@ +# RUN: cp %s %t && %update_test_body %t 2>&1 | count 0 +# RUN: diff -u %S/Inputs/basic-asm.test.expected %t + +.ifdef GEN +#--- a.txt +.long 0 +#--- b.txt +.long 1 +#--- gen +cat a.txt b.txt +.endif diff --git a/llvm/test/tools/UpdateTestChecks/update_test_body/basic.test b/llvm/test/tools/UpdateTestChecks/update_test_body/basic.test new file mode 100644 index 000000000000..d99946e2bd92 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_test_body/basic.test @@ -0,0 +1,13 @@ +; RUN: cp %s %t && %update_test_body %t 2>&1 | count 0 +; RUN: diff -u %S/Inputs/basic.test.expected %t + +;--- a.txt +@a = global i32 0 +;--- b.txt +@b = global i32 0 +;--- gen +cat a.txt +echo ';--- b.ll' +cat b.txt + +;--- a.ll diff --git a/llvm/test/tools/UpdateTestChecks/update_test_body/empty-stdout.test b/llvm/test/tools/UpdateTestChecks/update_test_body/empty-stdout.test new file mode 100644 index 000000000000..9ea9c7bc7ac9 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_test_body/empty-stdout.test @@ -0,0 +1,13 @@ +# RUN: cp %s %t && not %update_test_body %t 2>&1 | FileCheck %s +# RUN: diff -u %t %s + +# CHECK: stdout is empty; forgot -o - ? + +.ifdef GEN +#--- a.txt +.long 0 +#--- b.txt +.long 1 +#--- gen +true +.endif diff --git a/llvm/test/tools/UpdateTestChecks/update_test_body/gen-absent.test b/llvm/test/tools/UpdateTestChecks/update_test_body/gen-absent.test new file mode 100644 index 000000000000..c12f22adceb2 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_test_body/gen-absent.test @@ -0,0 +1,7 @@ +# RUN: cp %s %t && not %update_test_body %t 2>&1 | FileCheck %s + +# CHECK: 'gen' does not exist + +.ifdef GEN +#--- a.txt +.endif diff --git a/llvm/test/tools/UpdateTestChecks/update_test_body/gen-fail.test b/llvm/test/tools/UpdateTestChecks/update_test_body/gen-fail.test new file mode 100644 index 000000000000..7e1a9365df14 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_test_body/gen-fail.test @@ -0,0 +1,11 @@ +# RUN: cp %s %t && not %update_test_body %t 2>&1 | FileCheck %s + +# CHECK: log +# CHECK-NEXT: 'gen' failed + +.ifdef GEN +#--- gen +echo log >&2 +false # gen fails due to sh -e +true +.endif diff --git a/llvm/test/tools/UpdateTestChecks/update_test_body/gen-unterminated.test b/llvm/test/tools/UpdateTestChecks/update_test_body/gen-unterminated.test new file mode 100644 index 000000000000..c0026939e414 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_test_body/gen-unterminated.test @@ -0,0 +1,8 @@ +# RUN: cp %s %t && not %update_test_body %t 2>&1 | FileCheck %s + +# CHECK: 'gen' should be followed by another part (---) or .endif + +#--- a.txt +.long 0 +#--- gen +cat a.txt diff --git a/llvm/test/tools/UpdateTestChecks/update_test_body/lit.local.cfg b/llvm/test/tools/UpdateTestChecks/update_test_body/lit.local.cfg new file mode 100644 index 000000000000..1bb2464ad957 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_test_body/lit.local.cfg @@ -0,0 +1,4 @@ +import platform + +if platform.system() == "Windows": + config.unsupported = True diff --git a/llvm/test/tools/llvm-dwarfdump/X86/formclass4.s b/llvm/test/tools/llvm-dwarfdump/X86/formclass4.s index d0f8857c638f..5b3cdfc97790 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/formclass4.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/formclass4.s @@ -1,15 +1,3 @@ -# Source: -# struct e { -# enum {} f[16384]; -# short g; -# }; -# e foo() { -# auto E = new e; -# return *E; -# } -# Compile with: -# clang -O2 -gdwarf-4 -S a.cpp -o a4.s - # RUN: llvm-mc %s -filetype obj -triple x86_64-apple-darwin -o %t.o # RUN: llvm-dwarfdump -debug-info -name g %t.o | FileCheck %s @@ -17,6 +5,20 @@ # CHECK: DW_AT_name ("g") # CHECK: DW_AT_data_member_location (0x4000) +.ifdef GEN +#--- a.cpp +struct e { + enum {} f[16384]; + short g; +}; +e foo() { + auto E = new e; + return *E; +} +#--- gen +clang --target=x86_64-apple-macosx -O2 -gdwarf-4 -S a.cpp -o - +.endif + .section __TEXT,__text,regular,pure_instructions .macosx_version_min 10, 14 .globl __Z3foov ## -- Begin function _Z3foov diff --git a/llvm/test/tools/llvm-dwarfdump/X86/prettyprint_type_units_split_v5.s b/llvm/test/tools/llvm-dwarfdump/X86/prettyprint_type_units_split_v5.s index e8bb95175087..81d15cd2be22 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/prettyprint_type_units_split_v5.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/prettyprint_type_units_split_v5.s @@ -1,16 +1,16 @@ # RUN: llvm-mc < %s -filetype obj -triple x86_64 -o - \ # RUN: | llvm-dwarfdump - | FileCheck %s -# Generated from: -# -# struct t1 { }; -# t1 v1; -# -# $ clang++ -S -g -fdebug-types-section -gsplit-dwarf -o test.5.split.s -gdwarf-5 -g - # CHECK: DW_TAG_variable # CHECK: DW_AT_type ({{.*}} "t1") +.ifdef GEN +#--- test.cpp +struct t1 { }; +t1 v1; +#--- gen +clang++ --target=x86_64-linux -S -g -fdebug-types-section -gsplit-dwarf -gdwarf-5 test.cpp -o - +.endif .text .file "test.cpp" .section .debug_types.dwo,"e",@progbits diff --git a/llvm/utils/update_test_body.py b/llvm/utils/update_test_body.py new file mode 100755 index 000000000000..661b0270d783 --- /dev/null +++ b/llvm/utils/update_test_body.py @@ -0,0 +1,110 @@ +#!/usr/bin/env python3 +"""Generate test body using split-file and a custom script. + +The script will prepare extra files with `split-file`, invoke `gen`, and then +rewrite the part after `gen` with its stdout. + +https://llvm.org/docs/TestingGuide.html#elaborated-tests + +Example: +PATH=/path/to/clang_build/bin:$PATH llvm/utils/update_test_body.py path/to/test.s +""" +import argparse +import contextlib +import os +import re +import subprocess +import sys +import tempfile + + +@contextlib.contextmanager +def cd(directory): + cwd = os.getcwd() + os.chdir(directory) + try: + yield + finally: + os.chdir(cwd) + + +def process(args, path): + prolog = [] + seen_gen = False + with open(path) as f: + for line in f.readlines(): + line = line.rstrip() + prolog.append(line) + if (seen_gen and re.match(r"(.|//)---", line)) or line.startswith(".endif"): + break + if re.match(r"(.|//)--- gen", line): + seen_gen = True + else: + print( + "'gen' should be followed by another part (---) or .endif", + file=sys.stderr, + ) + return 1 + + if not seen_gen: + print("'gen' does not exist", file=sys.stderr) + return 1 + with tempfile.TemporaryDirectory(prefix="update_test_body_") as dir: + try: + # If the last line starts with ".endif", remove it. + sub = subprocess.run( + ["split-file", "-", dir], + input="\n".join( + prolog[:-1] if prolog[-1].startswith(".endif") else prolog + ).encode(), + capture_output=True, + check=True, + ) + except subprocess.CalledProcessError as ex: + sys.stderr.write(ex.stderr.decode()) + return 1 + with cd(dir): + if args.shell: + print(f"invoke shell in the temporary directory '{dir}'") + subprocess.run([os.environ.get("SHELL", "sh")]) + return 0 + + sub = subprocess.run( + ["sh", "-eu", "gen"], + capture_output=True, + # Don't encode the directory information to the Clang output. + # Remove unneeded details (.ident) as well. + env=dict( + os.environ, + CCC_OVERRIDE_OPTIONS="#^-fno-ident", + PWD="/proc/self/cwd", + ), + ) + sys.stderr.write(sub.stderr.decode()) + if sub.returncode != 0: + print("'gen' failed", file=sys.stderr) + return sub.returncode + if not sub.stdout: + print("stdout is empty; forgot -o - ?", file=sys.stderr) + return 1 + content = sub.stdout.decode() + + with open(path, "w") as f: + # Print lines up to '.endif'. + print("\n".join(prolog), file=f) + # Then print the stdout of 'gen'. + f.write(content) + + +parser = argparse.ArgumentParser( + description="Generate test body using split-file and a custom script" +) +parser.add_argument("files", nargs="+") +parser.add_argument( + "--shell", action="store_true", help="invoke shell instead of 'gen'" +) +args = parser.parse_args() +for path in args.files: + retcode = process(args, path) + if retcode != 0: + sys.exit(retcode) -- GitLab From c4a3d184db5fdffe798208b8281dfe944616f9ed Mon Sep 17 00:00:00 2001 From: Vlad Mishel <43666597+vmishelcs@users.noreply.github.com> Date: Thu, 9 May 2024 00:06:18 -0700 Subject: [PATCH 115/328] [libc] Replace `MutexLock` with `cpp::lock_guard` (#89340) This PR address issue #89002. #### Changes in this PR * Added a simple implementation of `cpp::lock_guard` (an equivalent of `std::lock_guard`) in libc/src/__support/CPP inspired by the libstdc++ implementation * Added tests for `cpp::lock_guard` in /libc/test/src/__support/CPP/mutex_test.cpp * Replaced all references to `MutexLock` with `cpp::lock_guard` --------- Co-authored-by: Guillaume Chatelet --- libc/src/__support/CPP/CMakeLists.txt | 6 ++ libc/src/__support/CPP/mutex.h | 46 +++++++++++ libc/src/__support/File/CMakeLists.txt | 1 + libc/src/__support/File/dir.cpp | 5 +- libc/src/__support/threads/CMakeLists.txt | 2 + libc/src/__support/threads/fork_callbacks.cpp | 9 ++- libc/src/__support/threads/thread.cpp | 11 +-- libc/src/stdlib/CMakeLists.txt | 1 + libc/src/stdlib/atexit.cpp | 3 +- libc/src/threads/linux/CMakeLists.txt | 1 + libc/src/threads/linux/CndVar.h | 5 +- libc/test/src/__support/CPP/CMakeLists.txt | 10 +++ libc/test/src/__support/CPP/mutex_test.cpp | 79 +++++++++++++++++++ 13 files changed, 165 insertions(+), 14 deletions(-) create mode 100644 libc/src/__support/CPP/mutex.h create mode 100644 libc/test/src/__support/CPP/mutex_test.cpp diff --git a/libc/src/__support/CPP/CMakeLists.txt b/libc/src/__support/CPP/CMakeLists.txt index 84d01fe04516..08661aba5b6b 100644 --- a/libc/src/__support/CPP/CMakeLists.txt +++ b/libc/src/__support/CPP/CMakeLists.txt @@ -51,6 +51,12 @@ add_header_library( libc.src.__support.macros.properties.types ) +add_header_library( + mutex + HDRS + mutex.h +) + add_header_library( span HDRS diff --git a/libc/src/__support/CPP/mutex.h b/libc/src/__support/CPP/mutex.h new file mode 100644 index 000000000000..c25c1155b766 --- /dev/null +++ b/libc/src/__support/CPP/mutex.h @@ -0,0 +1,46 @@ +//===--- A self contained equivalent of std::mutex --------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC___SUPPORT_CPP_MUTEX_H +#define LLVM_LIBC_SRC___SUPPORT_CPP_MUTEX_H + +namespace LIBC_NAMESPACE { +namespace cpp { + +// Assume the calling thread has already obtained mutex ownership. +struct adopt_lock_t { + explicit adopt_lock_t() = default; +}; + +// Tag used to make a scoped lock take ownership of a locked mutex. +constexpr adopt_lock_t adopt_lock{}; + +// An RAII class for easy locking and unlocking of mutexes. +template class lock_guard { + MutexType &mutex; + +public: + // Calls `m.lock()` upon resource acquisition. + explicit lock_guard(MutexType &m) : mutex(m) { mutex.lock(); } + + // Acquires ownership of the mutex object `m` without attempting to lock + // it. The behavior is undefined if the current thread does not hold the + // lock on `m`. Does not call `m.lock()` upon resource acquisition. + lock_guard(MutexType &m, adopt_lock_t t) : mutex(m) {} + + ~lock_guard() { mutex.unlock(); } + + // non-copyable + lock_guard &operator=(const lock_guard &) = delete; + lock_guard(const lock_guard &) = delete; +}; + +} // namespace cpp +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC___SUPPORT_CPP_MUTEX_H diff --git a/libc/src/__support/File/CMakeLists.txt b/libc/src/__support/File/CMakeLists.txt index b7c0612096aa..0416ac2cc902 100644 --- a/libc/src/__support/File/CMakeLists.txt +++ b/libc/src/__support/File/CMakeLists.txt @@ -25,6 +25,7 @@ add_object_library( HDRS dir.h DEPENDS + libc.src.__support.CPP.mutex libc.src.__support.CPP.new libc.src.__support.CPP.span libc.src.__support.threads.mutex diff --git a/libc/src/__support/File/dir.cpp b/libc/src/__support/File/dir.cpp index 9ff639a777e2..e0f7695b3932 100644 --- a/libc/src/__support/File/dir.cpp +++ b/libc/src/__support/File/dir.cpp @@ -8,6 +8,7 @@ #include "dir.h" +#include "src/__support/CPP/mutex.h" // lock_guard #include "src/__support/CPP/new.h" #include "src/__support/error_or.h" #include "src/errno/libc_errno.h" // For error macros @@ -27,7 +28,7 @@ ErrorOr Dir::open(const char *path) { } ErrorOr Dir::read() { - MutexLock lock(&mutex); + cpp::lock_guard lock(mutex); if (readptr >= fillsize) { auto readsize = platform_fetch_dirents(fd, buffer); if (!readsize) @@ -51,7 +52,7 @@ ErrorOr Dir::read() { int Dir::close() { { - MutexLock lock(&mutex); + cpp::lock_guard lock(mutex); int retval = platform_closedir(fd); if (retval != 0) return retval; diff --git a/libc/src/__support/threads/CMakeLists.txt b/libc/src/__support/threads/CMakeLists.txt index 731adf6f9c8e..34412be4dfed 100644 --- a/libc/src/__support/threads/CMakeLists.txt +++ b/libc/src/__support/threads/CMakeLists.txt @@ -31,6 +31,7 @@ if(TARGET libc.src.__support.threads.${LIBC_TARGET_OS}.mutex) fork_callbacks.h DEPENDS .mutex + libc.src.__support.CPP.mutex ) endif() @@ -57,6 +58,7 @@ if(TARGET libc.src.__support.threads.${LIBC_TARGET_OS}.thread) libc.src.__support.common libc.src.__support.fixedvector libc.src.__support.CPP.array + libc.src.__support.CPP.mutex libc.src.__support.CPP.optional ) endif() diff --git a/libc/src/__support/threads/fork_callbacks.cpp b/libc/src/__support/threads/fork_callbacks.cpp index 54fda676f281..6efaf62f135a 100644 --- a/libc/src/__support/threads/fork_callbacks.cpp +++ b/libc/src/__support/threads/fork_callbacks.cpp @@ -8,6 +8,7 @@ #include "fork_callbacks.h" +#include "src/__support/CPP/mutex.h" // lock_guard #include "src/__support/threads/mutex.h" #include // For size_t @@ -35,7 +36,7 @@ public: constexpr AtForkCallbackManager() : mtx(false, false, false), next_index(0) {} bool register_triple(const ForkCallbackTriple &triple) { - MutexLock lock(&mtx); + cpp::lock_guard lock(mtx); if (next_index >= CALLBACK_SIZE) return false; list[next_index] = triple; @@ -44,7 +45,7 @@ public: } void invoke_prepare() { - MutexLock lock(&mtx); + cpp::lock_guard lock(mtx); for (size_t i = 0; i < next_index; ++i) { auto prepare = list[i].prepare; if (prepare) @@ -53,7 +54,7 @@ public: } void invoke_parent() { - MutexLock lock(&mtx); + cpp::lock_guard lock(mtx); for (size_t i = 0; i < next_index; ++i) { auto parent = list[i].parent; if (parent) @@ -62,7 +63,7 @@ public: } void invoke_child() { - MutexLock lock(&mtx); + cpp::lock_guard lock(mtx); for (size_t i = 0; i < next_index; ++i) { auto child = list[i].child; if (child) diff --git a/libc/src/__support/threads/thread.cpp b/libc/src/__support/threads/thread.cpp index c1785343671c..7b02f8246e24 100644 --- a/libc/src/__support/threads/thread.cpp +++ b/libc/src/__support/threads/thread.cpp @@ -10,6 +10,7 @@ #include "src/__support/threads/mutex.h" #include "src/__support/CPP/array.h" +#include "src/__support/CPP/mutex.h" // lock_guard #include "src/__support/CPP/optional.h" #include "src/__support/fixedvector.h" #include "src/__support/macros/attributes.h" @@ -56,7 +57,7 @@ public: constexpr TSSKeyMgr() : mtx(false, false, false) {} cpp::optional new_key(TSSDtor *dtor) { - MutexLock lock(&mtx); + cpp::lock_guard lock(mtx); for (unsigned int i = 0; i < TSS_KEY_COUNT; ++i) { TSSKeyUnit &u = units[i]; if (!u.active) { @@ -70,20 +71,20 @@ public: TSSDtor *get_dtor(unsigned int key) { if (key >= TSS_KEY_COUNT) return nullptr; - MutexLock lock(&mtx); + cpp::lock_guard lock(mtx); return units[key].dtor; } bool remove_key(unsigned int key) { if (key >= TSS_KEY_COUNT) return false; - MutexLock lock(&mtx); + cpp::lock_guard lock(mtx); units[key].reset(); return true; } bool is_valid_key(unsigned int key) { - MutexLock lock(&mtx); + cpp::lock_guard lock(mtx); return units[key].active; } }; @@ -113,7 +114,7 @@ public: constexpr ThreadAtExitCallbackMgr() : mtx(false, false, false) {} int add_callback(AtExitCallback *callback, void *obj) { - MutexLock lock(&mtx); + cpp::lock_guard lock(mtx); return callback_list.push_back({callback, obj}); } diff --git a/libc/src/stdlib/CMakeLists.txt b/libc/src/stdlib/CMakeLists.txt index e526ba040bef..9b76a6a0f857 100644 --- a/libc/src/stdlib/CMakeLists.txt +++ b/libc/src/stdlib/CMakeLists.txt @@ -414,6 +414,7 @@ add_entrypoint_object( CXX_STANDARD 20 # For constinit of the atexit callback list. DEPENDS + libc.src.__support.CPP.mutex libc.src.__support.CPP.new libc.src.__support.OSUtil.osutil libc.src.__support.blockstore diff --git a/libc/src/stdlib/atexit.cpp b/libc/src/stdlib/atexit.cpp index fa072b2fdf8d..4f0497444773 100644 --- a/libc/src/stdlib/atexit.cpp +++ b/libc/src/stdlib/atexit.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "src/stdlib/atexit.h" +#include "src/__support/CPP/mutex.h" // lock_guard #include "src/__support/blockstore.h" #include "src/__support/common.h" #include "src/__support/fixedvector.h" @@ -68,7 +69,7 @@ void call_exit_callbacks() { } int add_atexit_unit(const AtExitUnit &unit) { - MutexLock lock(&handler_list_mtx); + cpp::lock_guard lock(handler_list_mtx); if (exit_callbacks.push_back(unit)) return 0; return -1; diff --git a/libc/src/threads/linux/CMakeLists.txt b/libc/src/threads/linux/CMakeLists.txt index d372bd9e18c4..68b7106c2052 100644 --- a/libc/src/threads/linux/CMakeLists.txt +++ b/libc/src/threads/linux/CMakeLists.txt @@ -7,6 +7,7 @@ add_header_library( libc.include.sys_syscall libc.include.threads libc.src.__support.CPP.atomic + libc.src.__support.CPP.mutex libc.src.__support.OSUtil.osutil libc.src.__support.threads.mutex libc.src.__support.threads.linux.futex_utils diff --git a/libc/src/threads/linux/CndVar.h b/libc/src/threads/linux/CndVar.h index 525a8f0f2b53..c08ffa393856 100644 --- a/libc/src/threads/linux/CndVar.h +++ b/libc/src/threads/linux/CndVar.h @@ -10,6 +10,7 @@ #define LLVM_LIBC_SRC_THREADS_LINUX_CNDVAR_H #include "src/__support/CPP/atomic.h" +#include "src/__support/CPP/mutex.h" // lock_guard #include "src/__support/CPP/optional.h" #include "src/__support/OSUtil/syscall.h" // For syscall functions. #include "src/__support/threads/linux/futex_utils.h" @@ -59,7 +60,7 @@ struct CndVar { CndWaiter waiter; { - MutexLock ml(&qmtx); + cpp::lock_guard ml(qmtx); CndWaiter *old_back = nullptr; if (waitq_front == nullptr) { waitq_front = waitq_back = &waiter; @@ -118,7 +119,7 @@ struct CndVar { } int broadcast() { - MutexLock ml(&qmtx); + cpp::lock_guard ml(qmtx); uint32_t dummy_futex_word; CndWaiter *waiter = waitq_front; waitq_front = waitq_back = nullptr; diff --git a/libc/test/src/__support/CPP/CMakeLists.txt b/libc/test/src/__support/CPP/CMakeLists.txt index 708548f812c6..cec13afc8dd1 100644 --- a/libc/test/src/__support/CPP/CMakeLists.txt +++ b/libc/test/src/__support/CPP/CMakeLists.txt @@ -64,6 +64,16 @@ add_libc_test( libc.src.__support.macros.properties.types ) +add_libc_test( + mutex_test + SUITE + libc-cpp-utils-tests + SRCS + mutex_test.cpp + DEPENDS + libc.src.__support.CPP.mutex +) + add_libc_test( int_seq_test SUITE diff --git a/libc/test/src/__support/CPP/mutex_test.cpp b/libc/test/src/__support/CPP/mutex_test.cpp new file mode 100644 index 000000000000..a68c84cfc78a --- /dev/null +++ b/libc/test/src/__support/CPP/mutex_test.cpp @@ -0,0 +1,79 @@ +//===-- Unittests for mutex -----------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/mutex.h" +#include "test/UnitTest/Test.h" + +using LIBC_NAMESPACE::cpp::adopt_lock; +using LIBC_NAMESPACE::cpp::lock_guard; + +// Simple struct for testing cpp::lock_guard. It defines methods 'lock' and +// 'unlock' which are required for the cpp::lock_guard class template. +struct Mutex { + // Flag to show whether this mutex is locked. + bool locked = false; + + // Flag to show if this mutex has been double locked. + bool double_locked = false; + + // Flag to show if this mutex has been double unlocked. + bool double_unlocked = false; + + Mutex() {} + + void lock() { + if (locked) + double_locked = true; + + locked = true; + } + + void unlock() { + if (!locked) + double_unlocked = true; + + locked = false; + } +}; + +TEST(LlvmLibcMutexTest, Basic) { + Mutex m; + ASSERT_FALSE(m.locked); + ASSERT_FALSE(m.double_locked); + ASSERT_FALSE(m.double_unlocked); + + { + lock_guard lg(m); + ASSERT_TRUE(m.locked); + ASSERT_FALSE(m.double_locked); + } + + ASSERT_FALSE(m.locked); + ASSERT_FALSE(m.double_unlocked); +} + +TEST(LlvmLibcMutexTest, AcquireLocked) { + Mutex m; + ASSERT_FALSE(m.locked); + ASSERT_FALSE(m.double_locked); + ASSERT_FALSE(m.double_unlocked); + + // Lock the mutex before placing a lock guard on it. + m.lock(); + ASSERT_TRUE(m.locked); + ASSERT_FALSE(m.double_locked); + + { + lock_guard lg(m, adopt_lock); + ASSERT_TRUE(m.locked); + ASSERT_FALSE(m.double_locked); + } + + ASSERT_FALSE(m.locked); + ASSERT_FALSE(m.double_unlocked); +} -- GitLab From 443377a9d1a8d4a69a317a1a892184c59dd0aec6 Mon Sep 17 00:00:00 2001 From: "Daniel M. Katz" Date: Thu, 9 May 2024 03:22:11 -0400 Subject: [PATCH 116/328] [Clang] Fix P2564 handling of variable initializers (#89565) The following program produces a diagnostic in Clang and EDG, but compiles correctly in GCC and MSVC: ```cpp #include consteval std::vector fn() { return {1,2,3}; } constexpr int a = fn()[1]; ``` Clang's diagnostic is as follows: ```cpp :6:19: error: call to consteval function 'fn' is not a constant expression 6 | constexpr int a = fn()[1]; | ^ :6:19: note: pointer to subobject of heap-allocated object is not a constant expression /opt/compiler-explorer/gcc-snapshot/lib/gcc/x86_64-linux-gnu/14.0.1/../../../../include/c++/14.0.1/bits/allocator.h:193:31: note: heap allocation performed here 193 | return static_cast<_Tp*>(::operator new(__n)); | ^ 1 error generated. Compiler returned: 1 ``` Based on my understanding of [`[dcl.constexpr]/6`](https://eel.is/c++draft/dcl.constexpr#6): > In any constexpr variable declaration, the full-expression of the initialization shall be a constant expression It seems to me that GCC and MSVC are correct: the initializer `fn()[1]` does not evaluate to an lvalue referencing a heap-allocated value within the `vector` returned by `fn()`; it evaluates to an lvalue-to-rvalue conversion _from_ that heap-allocated value. This PR turns out to be a bug fix on the implementation of [P2564R3](https://wg21.link/p2564r3); as such, it only applies to C++23 and later. The core problem is that the definition of a constant-initialized variable ([`[expr.const/2]`](https://eel.is/c++draft/expr.const#2)) is contingent on whether the initializer can be evaluated as a constant expression: > A variable or temporary object o is _constant-initialized_ if [...] the full-expression of its initialization is a constant expression when interpreted as a _constant-expression_, [...] That can't be known until we've finished parsing the initializer, by which time we've already added immediate invocations and consteval references to the current expression evaluation context. This will have the effect of evaluating said invocations as full expressions when the context is popped, even if they're subexpressions of a larger constant expression initializer. If, however, the variable _is_ constant-initialized, then its initializer is [manifestly constant-evaluated](https://eel.is/c++draft/expr.const#20): > An expression or conversion is _manifestly constant-evaluated_ if it is [...] **the initializer of a variable that is usable in constant expressions or has constant initialization** [...] which in turn means that any subexpressions naming an immediate function are in an [immediate function context](https://eel.is/c++draft/expr.const#16): > An expression or conversion is in an immediate function context if it is potentially evaluated and either [...] it is a **subexpression of a manifestly constant-evaluated expression** or conversion and therefore _are not to be considered [immediate invocations](https://eel.is/c++draft/expr.const#16) or [immediate-escalating expressions](https://eel.is/c++draft/expr.const#17) in the first place_: > An invocation is an _immediate invocation_ if it is a potentially-evaluated explicit or implicit invocation of an immediate function and **is not in an immediate function context**. > An expression or conversion is _immediate-escalating_ if **it is not initially in an immediate function context** and [...] The approach that I'm therefore proposing is: 1. Create a new expression evaluation context for _every_ variable initializer (rather than only nonlocal ones). 2. Attach initializers to `VarDecl`s _prior_ to popping the expression evaluation context / scope / etc. This sequences the determination of whether the initializer is in an immediate function context _before_ any contained immediate invocations are evaluated. 3. When popping an expression evaluation context, elide all evaluations of constant invocations, and all checks for consteval references, if the context is an immediate function context. Note that if it could be ascertained that this was an immediate function context at parse-time, we [would never have registered](https://github.com/llvm/llvm-project/blob/760910ddb918d77e7632be1678f69909384d69ae/clang/lib/Sema/SemaExpr.cpp#L17799) these immediate invocations or consteval references in the first place. Most of the test changes previously made for this PR are now reverted and passing as-is. The only test updates needed are now as follows: - A few diagnostics in `consteval-cxx2a.cpp` are updated to reflect that it is the `consteval tester::tester` constructor, not the more narrow `make_name` function call, which fails to be evaluated as a constant expression. - The reclassification of `warn_impcast_integer_precision_constant` as a compile-time diagnostic adds a (somewhat duplicative) warning when attempting to define an enum constant using a narrowing conversion. It also, however, retains the existing diagnostics which @erichkeane (rightly) objected to being lost from an earlier revision of this PR. --------- Co-authored-by: cor3ntin --- clang/docs/ReleaseNotes.rst | 4 ++ clang/include/clang/Sema/Sema.h | 4 +- clang/lib/Parse/ParseDecl.cpp | 21 ++++---- clang/lib/Sema/SemaChecking.cpp | 9 ++-- clang/lib/Sema/SemaDeclCXX.cpp | 53 ++++++++++--------- clang/lib/Sema/SemaExpr.cpp | 2 +- clang/test/SemaCXX/cxx2a-consteval.cpp | 16 ++++-- .../SemaCXX/cxx2b-consteval-propagate.cpp | 26 +++++++++ clang/test/SemaCXX/enum-scoped.cpp | 1 + 9 files changed, 90 insertions(+), 46 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index a3c8e4141ca5..4547636318a7 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -699,6 +699,10 @@ Bug Fixes to C++ Support performed incorrectly when checking constraints. Fixes (#GH90349). - Clang now allows constrained member functions to be explicitly specialized for an implicit instantiation of a class template. +- Fix a C++23 bug in implementation of P2564R3 which evaluates immediate invocations in place + within initializers for variables that are usable in constant expressions or are constant + initialized, rather than evaluating them as a part of the larger manifestly constant evaluated + expression. Bug Fixes to AST Handling ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index ddb3de2b6602..4efd3878e861 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -10202,7 +10202,9 @@ public: S.ExprEvalContexts.back().InImmediateFunctionContext = FD->isImmediateFunction() || S.ExprEvalContexts[S.ExprEvalContexts.size() - 2] - .isConstantEvaluated(); + .isConstantEvaluated() || + S.ExprEvalContexts[S.ExprEvalContexts.size() - 2] + .isImmediateFunctionContext(); S.ExprEvalContexts.back().InImmediateEscalatingFunctionContext = S.getLangOpts().CPlusPlus20 && FD->isImmediateEscalating(); } else diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp index 4e4b05b21383..2c11ae693c35 100644 --- a/clang/lib/Parse/ParseDecl.cpp +++ b/clang/lib/Parse/ParseDecl.cpp @@ -2587,25 +2587,30 @@ Decl *Parser::ParseDeclarationAfterDeclaratorAndAttributes( Parser &P; Declarator &D; Decl *ThisDecl; + bool Entered; InitializerScopeRAII(Parser &P, Declarator &D, Decl *ThisDecl) - : P(P), D(D), ThisDecl(ThisDecl) { + : P(P), D(D), ThisDecl(ThisDecl), Entered(false) { if (ThisDecl && P.getLangOpts().CPlusPlus) { Scope *S = nullptr; if (D.getCXXScopeSpec().isSet()) { P.EnterScope(0); S = P.getCurScope(); } - P.Actions.ActOnCXXEnterDeclInitializer(S, ThisDecl); + if (ThisDecl && !ThisDecl->isInvalidDecl()) { + P.Actions.ActOnCXXEnterDeclInitializer(S, ThisDecl); + Entered = true; + } } } - ~InitializerScopeRAII() { pop(); } - void pop() { + ~InitializerScopeRAII() { if (ThisDecl && P.getLangOpts().CPlusPlus) { Scope *S = nullptr; if (D.getCXXScopeSpec().isSet()) S = P.getCurScope(); - P.Actions.ActOnCXXExitDeclInitializer(S, ThisDecl); + + if (Entered) + P.Actions.ActOnCXXExitDeclInitializer(S, ThisDecl); if (S) P.ExitScope(); } @@ -2736,8 +2741,6 @@ Decl *Parser::ParseDeclarationAfterDeclaratorAndAttributes( FRI->RangeExpr = Init; } - InitScope.pop(); - if (Init.isInvalid()) { SmallVector StopTokens; StopTokens.push_back(tok::comma); @@ -2785,8 +2788,6 @@ Decl *Parser::ParseDeclarationAfterDeclaratorAndAttributes( bool SawError = ParseExpressionList(Exprs, ExpressionStarts); - InitScope.pop(); - if (SawError) { if (ThisVarDecl && PP.isCodeCompletionReached() && !CalledSignatureHelp) { Actions.ProduceConstructorSignatureHelp( @@ -2818,8 +2819,6 @@ Decl *Parser::ParseDeclarationAfterDeclaratorAndAttributes( PreferredType.enterVariableInit(Tok.getLocation(), ThisDecl); ExprResult Init(ParseBraceInitializer()); - InitScope.pop(); - if (Init.isInvalid()) { Actions.ActOnInitializerError(ThisDecl); } else diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index e8e74467208c..54789dde5069 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -16574,11 +16574,10 @@ static void CheckImplicitConversion(Sema &S, Expr *E, QualType T, std::string PrettySourceValue = toString(Value, 10); std::string PrettyTargetValue = PrettyPrintInRange(Value, TargetRange); - S.DiagRuntimeBehavior( - E->getExprLoc(), E, - S.PDiag(diag::warn_impcast_integer_precision_constant) - << PrettySourceValue << PrettyTargetValue << E->getType() << T - << E->getSourceRange() << SourceRange(CC)); + S.Diag(E->getExprLoc(), + S.PDiag(diag::warn_impcast_integer_precision_constant) + << PrettySourceValue << PrettyTargetValue << E->getType() + << T << E->getSourceRange() << SourceRange(CC)); return; } } diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp index 157d42c09cfc..d77b9507066b 100644 --- a/clang/lib/Sema/SemaDeclCXX.cpp +++ b/clang/lib/Sema/SemaDeclCXX.cpp @@ -18553,15 +18553,6 @@ void Sema::ActOnPureSpecifier(Decl *D, SourceLocation ZeroLoc) { Diag(D->getLocation(), diag::err_illegal_initializer); } -/// Determine whether the given declaration is a global variable or -/// static data member. -static bool isNonlocalVariable(const Decl *D) { - if (const VarDecl *Var = dyn_cast_or_null(D)) - return Var->hasGlobalStorage(); - - return false; -} - /// Invoked when we are about to parse an initializer for the declaration /// 'Dcl'. /// @@ -18570,9 +18561,7 @@ static bool isNonlocalVariable(const Decl *D) { /// class X. If the declaration had a scope specifier, a scope will have /// been created and passed in for this purpose. Otherwise, S will be null. void Sema::ActOnCXXEnterDeclInitializer(Scope *S, Decl *D) { - // If there is no declaration, there was an error parsing it. - if (!D || D->isInvalidDecl()) - return; + assert(D && !D->isInvalidDecl()); // We will always have a nested name specifier here, but this declaration // might not be out of line if the specifier names the current namespace: @@ -18581,25 +18570,41 @@ void Sema::ActOnCXXEnterDeclInitializer(Scope *S, Decl *D) { if (S && D->isOutOfLine()) EnterDeclaratorContext(S, D->getDeclContext()); - // If we are parsing the initializer for a static data member, push a - // new expression evaluation context that is associated with this static - // data member. - if (isNonlocalVariable(D)) - PushExpressionEvaluationContext( - ExpressionEvaluationContext::PotentiallyEvaluated, D); + PushExpressionEvaluationContext( + ExpressionEvaluationContext::PotentiallyEvaluated, D); } /// Invoked after we are finished parsing an initializer for the declaration D. void Sema::ActOnCXXExitDeclInitializer(Scope *S, Decl *D) { - // If there is no declaration, there was an error parsing it. - if (!D || D->isInvalidDecl()) - return; - - if (isNonlocalVariable(D)) - PopExpressionEvaluationContext(); + assert(D); if (S && D->isOutOfLine()) ExitDeclaratorContext(S); + + if (getLangOpts().CPlusPlus23) { + // An expression or conversion is 'manifestly constant-evaluated' if it is: + // [...] + // - the initializer of a variable that is usable in constant expressions or + // has constant initialization. + if (auto *VD = dyn_cast(D); + VD && (VD->isUsableInConstantExpressions(Context) || + VD->hasConstantInitialization())) { + // An expression or conversion is in an 'immediate function context' if it + // is potentially evaluated and either: + // [...] + // - it is a subexpression of a manifestly constant-evaluated expression + // or conversion. + ExprEvalContexts.back().InImmediateFunctionContext = true; + } + } + + // Unless the initializer is in an immediate function context (as determined + // above), this will evaluate all contained immediate function calls as + // constant expressions. If the initializer IS an immediate function context, + // the initializer has been determined to be a constant expression, and all + // such evaluations will be elided (i.e., as if we "knew the whole time" that + // it was a constant expression). + PopExpressionEvaluationContext(); } /// ActOnCXXConditionDeclarationExpr - Parsed a condition declaration of a diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 94f99a423f0e..c688cb21f236 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -18039,7 +18039,7 @@ HandleImmediateInvocations(Sema &SemaRef, Sema::ExpressionEvaluationContextRecord &Rec) { if ((Rec.ImmediateInvocationCandidates.size() == 0 && Rec.ReferenceToConsteval.size() == 0) || - SemaRef.RebuildingImmediateInvocation) + Rec.isImmediateFunctionContext() || SemaRef.RebuildingImmediateInvocation) return; /// When we have more than 1 ImmediateInvocationCandidates or previously diff --git a/clang/test/SemaCXX/cxx2a-consteval.cpp b/clang/test/SemaCXX/cxx2a-consteval.cpp index e19807437207..622ec31c459d 100644 --- a/clang/test/SemaCXX/cxx2a-consteval.cpp +++ b/clang/test/SemaCXX/cxx2a-consteval.cpp @@ -1068,6 +1068,14 @@ void test() { constexpr int (*f2)(void) = lstatic; // expected-error {{constexpr variable 'f2' must be initialized by a constant expression}} \ // expected-note {{pointer to a consteval declaration is not a constant expression}} + int (*f3)(void) = []() consteval { return 3; }; // expected-error {{cannot take address of consteval call operator of '(lambda at}} \ + // expected-note {{declared here}} +} + +consteval void consteval_test() { + constexpr auto l1 = []() consteval { return 3; }; + + int (*f1)(void) = l1; // ok } } @@ -1098,11 +1106,11 @@ int bad = 10; // expected-note 6{{declared here}} tester glob1(make_name("glob1")); tester glob2(make_name("glob2")); constexpr tester cglob(make_name("cglob")); -tester paddedglob(make_name(pad(bad))); // expected-error {{call to consteval function 'GH58207::make_name' is not a constant expression}} \ +tester paddedglob(make_name(pad(bad))); // expected-error {{call to consteval function 'GH58207::tester::tester' is not a constant expression}} \ // expected-note {{read of non-const variable 'bad' is not allowed in a constant expression}} constexpr tester glob3 = { make_name("glob3") }; -constexpr tester glob4 = { make_name(pad(bad)) }; // expected-error {{call to consteval function 'GH58207::make_name' is not a constant expression}} \ +constexpr tester glob4 = { make_name(pad(bad)) }; // expected-error {{call to consteval function 'GH58207::tester::tester' is not a constant expression}} \ // expected-error {{constexpr variable 'glob4' must be initialized by a constant expression}} \ // expected-note 2{{read of non-const variable 'bad' is not allowed in a constant expression}} @@ -1114,12 +1122,12 @@ auto V1 = make_name(pad(bad)); // expected-error {{call to consteval function 'G void foo() { static tester loc1(make_name("loc1")); static constexpr tester loc2(make_name("loc2")); - static tester paddedloc(make_name(pad(bad))); // expected-error {{call to consteval function 'GH58207::make_name' is not a constant expression}} \ + static tester paddedloc(make_name(pad(bad))); // expected-error {{call to consteval function 'GH58207::tester::tester' is not a constant expression}} \ // expected-note {{read of non-const variable 'bad' is not allowed in a constant expression}} } void bar() { - static tester paddedloc(make_name(pad(bad))); // expected-error {{call to consteval function 'GH58207::make_name' is not a constant expression}} \ + static tester paddedloc(make_name(pad(bad))); // expected-error {{call to consteval function 'GH58207::tester::tester' is not a constant expression}} \ // expected-note {{read of non-const variable 'bad' is not allowed in a constant expression}} } } diff --git a/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp b/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp index 4a75392045d0..37fa1f1bdf59 100644 --- a/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp +++ b/clang/test/SemaCXX/cxx2b-consteval-propagate.cpp @@ -394,3 +394,29 @@ static_assert(none_of( )); } + +#if __cplusplus >= 202302L +namespace lvalue_to_rvalue_init_from_heap { + +struct S { + int *value; + constexpr S(int v) : value(new int {v}) {} // expected-note 2 {{heap allocation performed here}} + constexpr ~S() { delete value; } +}; +consteval S fn() { return S(5); } +int fn2() { return 2; } // expected-note {{declared here}} + +constexpr int a = *fn().value; +constinit int b = *fn().value; +const int c = *fn().value; +int d = *fn().value; + +constexpr int e = *fn().value + fn2(); // expected-error {{must be initialized by a constant expression}} \ + // expected-error {{call to consteval function 'lvalue_to_rvalue_init_from_heap::fn' is not a constant expression}} \ + // expected-note {{non-constexpr function 'fn2'}} \ + // expected-note {{pointer to heap-allocated object}} + +int f = *fn().value + fn2(); // expected-error {{call to consteval function 'lvalue_to_rvalue_init_from_heap::fn' is not a constant expression}} \ + // expected-note {{pointer to heap-allocated object}} +} +#endif diff --git a/clang/test/SemaCXX/enum-scoped.cpp b/clang/test/SemaCXX/enum-scoped.cpp index b1d9a215c437..d7b7923430af 100644 --- a/clang/test/SemaCXX/enum-scoped.cpp +++ b/clang/test/SemaCXX/enum-scoped.cpp @@ -53,6 +53,7 @@ enum class E4 { e1 = -2147483648, // ok e2 = 2147483647, // ok e3 = 2147483648 // expected-error{{enumerator value evaluates to 2147483648, which cannot be narrowed to type 'int'}} + // expected-warning@-1{{changes value}} }; enum class E5 { -- GitLab From febd89cafea11e6603f593e41be1a21ca9d009ac Mon Sep 17 00:00:00 2001 From: Vadim D <36827317+vvd170501@users.noreply.github.com> Date: Thu, 9 May 2024 11:25:26 +0300 Subject: [PATCH 117/328] [clang-tidy] check `std::string_view` and custom string-like classes in `readability-string-compare` (#88636) This PR aims to expand the list of classes that are considered to be "strings" by `readability-string-compare` check. 1. Currently only `std::string;:compare` is checked, but `std::string_view` has a similar `compare` method. This PR enables checking of `std::string_view::compare` by default. 2. Some codebases use custom string-like classes that have public interfaces similar to `std::string` or `std::string_view`. Example: [TStringBase](https://github.com/yandex/yatool/blob/main/util/generic/strbase.h#L38), A new option, `readability-string-compare.StringClassNames`, is added to allow specifying a custom list of string-like classes. Related to, but does not solve #28396 (only adds support for custom string-like classes, not custom functions) --- .../readability/StringCompareCheck.cpp | 27 ++++++++++++-- .../readability/StringCompareCheck.h | 10 ++++- clang-tools-extra/docs/ReleaseNotes.rst | 5 +++ .../checks/readability/string-compare.rst | 37 ++++++++++++++++++- .../clang-tidy/checkers/Inputs/Headers/string | 10 +++++ .../string-compare-custom-string-classes.cpp | 35 ++++++++++++++++++ .../checkers/readability/string-compare.cpp | 23 ++++++++++++ 7 files changed, 139 insertions(+), 8 deletions(-) create mode 100644 clang-tools-extra/test/clang-tidy/checkers/readability/string-compare-custom-string-classes.cpp diff --git a/clang-tools-extra/clang-tidy/readability/StringCompareCheck.cpp b/clang-tools-extra/clang-tidy/readability/StringCompareCheck.cpp index 3b5d89c8c647..7c0bbef3ca08 100644 --- a/clang-tools-extra/clang-tidy/readability/StringCompareCheck.cpp +++ b/clang-tools-extra/clang-tidy/readability/StringCompareCheck.cpp @@ -7,12 +7,15 @@ //===----------------------------------------------------------------------===// #include "StringCompareCheck.h" -#include "../utils/FixItHintUtils.h" +#include "../utils/OptionsUtils.h" #include "clang/AST/ASTContext.h" #include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/ASTMatchers/ASTMatchers.h" #include "clang/Tooling/FixIt.h" +#include "llvm/ADT/StringRef.h" using namespace clang::ast_matchers; +namespace optutils = clang::tidy::utils::options; namespace clang::tidy::readability { @@ -20,11 +23,27 @@ static const StringRef CompareMessage = "do not use 'compare' to test equality " "of strings; use the string equality " "operator instead"; +static const StringRef DefaultStringLikeClasses = "::std::basic_string;" + "::std::basic_string_view"; + +StringCompareCheck::StringCompareCheck(StringRef Name, + ClangTidyContext *Context) + : ClangTidyCheck(Name, Context), + StringLikeClasses(optutils::parseStringList( + Options.get("StringLikeClasses", DefaultStringLikeClasses))) {} + +void StringCompareCheck::storeOptions(ClangTidyOptions::OptionMap &Opts) { + Options.store(Opts, "StringLikeClasses", + optutils::serializeStringList(StringLikeClasses)); +} + void StringCompareCheck::registerMatchers(MatchFinder *Finder) { + if (StringLikeClasses.empty()) { + return; + } const auto StrCompare = cxxMemberCallExpr( - callee(cxxMethodDecl(hasName("compare"), - ofClass(classTemplateSpecializationDecl( - hasName("::std::basic_string"))))), + callee(cxxMethodDecl(hasName("compare"), ofClass(cxxRecordDecl(hasAnyName( + StringLikeClasses))))), hasArgument(0, expr().bind("str2")), argumentCountIs(1), callee(memberExpr().bind("str1"))); diff --git a/clang-tools-extra/clang-tidy/readability/StringCompareCheck.h b/clang-tools-extra/clang-tidy/readability/StringCompareCheck.h index 812736d806b7..150090901a6e 100644 --- a/clang-tools-extra/clang-tidy/readability/StringCompareCheck.h +++ b/clang-tools-extra/clang-tidy/readability/StringCompareCheck.h @@ -10,6 +10,7 @@ #define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_READABILITY_STRINGCOMPARECHECK_H #include "../ClangTidyCheck.h" +#include namespace clang::tidy::readability { @@ -20,13 +21,18 @@ namespace clang::tidy::readability { /// http://clang.llvm.org/extra/clang-tidy/checks/readability/string-compare.html class StringCompareCheck : public ClangTidyCheck { public: - StringCompareCheck(StringRef Name, ClangTidyContext *Context) - : ClangTidyCheck(Name, Context) {} + StringCompareCheck(StringRef Name, ClangTidyContext *Context); + bool isLanguageVersionSupported(const LangOptions &LangOpts) const override { return LangOpts.CPlusPlus; } + void registerMatchers(ast_matchers::MatchFinder *Finder) override; void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + void storeOptions(ClangTidyOptions::OptionMap &Opts) override; + +private: + const std::vector StringLikeClasses; }; } // namespace clang::tidy::readability diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 5b7ea42c63d6..3f0d25ec8c75 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -362,6 +362,11 @@ Changes in existing checks check by resolving fix-it overlaps in template code by disregarding implicit instances. +- Improved :doc:`readability-string-compare + ` check to also detect + usages of ``std::string_view::compare``. Added a `StringLikeClasses` option + to detect usages of ``compare`` method in custom string-like classes. + Removed checks ^^^^^^^^^^^^^^ diff --git a/clang-tools-extra/docs/clang-tidy/checks/readability/string-compare.rst b/clang-tools-extra/docs/clang-tidy/checks/readability/string-compare.rst index 268632eee61a..4be2473bed2d 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/readability/string-compare.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/readability/string-compare.rst @@ -14,10 +14,12 @@ recommended to avoid the risk of incorrect interpretation of the return value and to simplify the code. The string equality and inequality operators can also be faster than the ``compare`` method due to early termination. -Examples: +Example +------- .. code-block:: c++ + // The same rules apply to std::string_view. std::string str1{"a"}; std::string str2{"b"}; @@ -50,5 +52,36 @@ Examples: } The above code examples show the list of if-statements that this check will -give a warning for. All of them uses ``compare`` to check if equality or +give a warning for. All of them use ``compare`` to check equality or inequality of two strings instead of using the correct operators. + +Options +------- + +.. option:: StringLikeClasses + + A string containing semicolon-separated names of string-like classes. + By default contains only ``::std::basic_string`` + and ``::std::basic_string_view``. If a class from this list has + a ``compare`` method similar to that of ``std::string``, it will be checked + in the same way. + +Example +^^^^^^^ + +.. code-block:: c++ + + struct CustomString { + public: + int compare (const CustomString& other) const; + } + + CustomString str1; + CustomString str2; + + // use str1 != str2 instead. + if (str1.compare(str2)) { + } + +If `StringLikeClasses` contains ``CustomString``, the check will suggest +replacing ``compare`` with equality operator. diff --git a/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string b/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string index d031f27beb9d..0c160bc182b6 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string +++ b/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string @@ -108,6 +108,8 @@ struct basic_string_view { constexpr bool starts_with(C ch) const noexcept; constexpr bool starts_with(const C* s) const; + constexpr int compare(basic_string_view sv) const noexcept; + static constexpr size_t npos = -1; }; @@ -132,6 +134,14 @@ bool operator==(const std::wstring&, const std::wstring&); bool operator==(const std::wstring&, const wchar_t*); bool operator==(const wchar_t*, const std::wstring&); +bool operator==(const std::string_view&, const std::string_view&); +bool operator==(const std::string_view&, const char*); +bool operator==(const char*, const std::string_view&); + +bool operator!=(const std::string_view&, const std::string_view&); +bool operator!=(const std::string_view&, const char*); +bool operator!=(const char*, const std::string_view&); + size_t strlen(const char* str); } diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/string-compare-custom-string-classes.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/string-compare-custom-string-classes.cpp new file mode 100644 index 000000000000..faf135833ee1 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/string-compare-custom-string-classes.cpp @@ -0,0 +1,35 @@ +// RUN: %check_clang_tidy %s readability-string-compare %t -- -config='{CheckOptions: {readability-string-compare.StringLikeClasses: "CustomStringTemplateBase;CustomStringNonTemplateBase"}}' -- -isystem %clang_tidy_headers +#include + +struct CustomStringNonTemplateBase { + int compare(const CustomStringNonTemplateBase& Other) const { + return 123; // value is not important for check + } +}; + +template +struct CustomStringTemplateBase { + int compare(const CustomStringTemplateBase& Other) const { + return 123; + } +}; + +struct CustomString1 : CustomStringNonTemplateBase {}; +struct CustomString2 : CustomStringTemplateBase {}; + +void CustomStringClasses() { + std::string_view sv1("a"); + std::string_view sv2("b"); + if (sv1.compare(sv2)) { // No warning - if a std class is not listed in StringLikeClasses, it won't be checked. + } + + CustomString1 custom1; + if (custom1.compare(custom1)) { + } + // CHECK-MESSAGES: [[@LINE-2]]:7: warning: do not use 'compare' to test equality of strings; use the string equality operator instead [readability-string-compare] + + CustomString2 custom2; + if (custom2.compare(custom2)) { + } + // CHECK-MESSAGES: [[@LINE-2]]:7: warning: do not use 'compare' to test equality of strings; use the string equality operator instead [readability-string-compare] +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/string-compare.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/string-compare.cpp index 2c08b86cf72f..c4fea4341617 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/string-compare.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/string-compare.cpp @@ -67,11 +67,27 @@ void Test() { if (str1.compare(comp())) { } // CHECK-MESSAGES: [[@LINE-2]]:7: warning: do not use 'compare' to test equality of strings; + + std::string_view sv1("a"); + std::string_view sv2("b"); + if (sv1.compare(sv2)) { + } + // CHECK-MESSAGES: [[@LINE-2]]:7: warning: do not use 'compare' to test equality of strings; use the string equality operator instead [readability-string-compare] +} + +struct DerivedFromStdString : std::string {}; + +void TestDerivedClass() { + DerivedFromStdString derived; + if (derived.compare(derived)) { + } + // CHECK-MESSAGES: [[@LINE-2]]:7: warning: do not use 'compare' to test equality of strings; use the string equality operator instead [readability-string-compare] } void Valid() { std::string str1("a", 1); std::string str2("b", 1); + if (str1 == str2) { } if (str1 != str2) { @@ -96,4 +112,11 @@ void Valid() { } if (str1.compare(str2) == -1) { } + + std::string_view sv1("a"); + std::string_view sv2("b"); + if (sv1 == sv2) { + } + if (sv1.compare(sv2) > 0) { + } } -- GitLab From b52fa9461ab73eaf2d04f32c806a1715b2595830 Mon Sep 17 00:00:00 2001 From: David Sherwood <57997763+david-arm@users.noreply.github.com> Date: Thu, 9 May 2024 09:40:33 +0100 Subject: [PATCH 118/328] [Analysis] Add cost model for experimental.cttz.elts intrinsic (#90720) In PR #88385 I've added support for auto-vectorisation of some early exit loops, which requires using the experimental.cttz.elts to calculate final indices in the early exit block. We need a more accurate cost model for this intrinsic to better reflect the cost of work required in the early exit block. I've tried to accurately represent the expansion code for the intrinsic when the target does not have efficient lowering for it. It's quite tricky to model because you need to first figure out what types will actually be used in the expansion. The type used can have a significant effect on the cost if you end up using illegal vector types. Tests added here: Analysis/CostModel/AArch64/cttz_elts.ll Analysis/CostModel/RISCV/cttz_elts.ll --- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 48 ++++ llvm/include/llvm/CodeGen/TargetLowering.h | 6 + .../SelectionDAG/SelectionDAGBuilder.cpp | 19 +- llvm/lib/CodeGen/TargetLoweringBase.cpp | 18 ++ .../Analysis/CostModel/AArch64/cttz_elts.ll | 209 ++++++++++++++++++ .../Analysis/CostModel/RISCV/cttz_elts.ll | 149 +++++++++++++ 6 files changed, 437 insertions(+), 12 deletions(-) create mode 100644 llvm/test/Analysis/CostModel/AArch64/cttz_elts.ll create mode 100644 llvm/test/Analysis/CostModel/RISCV/cttz_elts.ll diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index c6e90e57e46e..bcb60c656296 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -25,6 +25,7 @@ #include "llvm/Analysis/OptimizationRemarkEmitter.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/TargetTransformInfoImpl.h" +#include "llvm/Analysis/ValueTracking.h" #include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" @@ -1758,6 +1759,53 @@ public: CmpInst::ICMP_ULT, CostKind); return Cost; } + case Intrinsic::experimental_cttz_elts: { + EVT ArgType = getTLI()->getValueType(DL, ICA.getArgTypes()[0], true); + + // If we're not expanding the intrinsic then we assume this is cheap + // to implement. + if (!getTLI()->shouldExpandCttzElements(ArgType)) + return getTypeLegalizationCost(RetTy).first; + + // TODO: The costs below reflect the expansion code in + // SelectionDAGBuilder, but we may want to sacrifice some accuracy in + // favour of compile time. + + // Find the smallest "sensible" element type to use for the expansion. + bool ZeroIsPoison = !cast(Args[1])->isZero(); + ConstantRange VScaleRange(APInt(64, 1), APInt::getZero(64)); + if (isa(ICA.getArgTypes()[0]) && I && I->getCaller()) + VScaleRange = getVScaleRange(I->getCaller(), 64); + + unsigned EltWidth = getTLI()->getBitWidthForCttzElements( + RetTy, ArgType.getVectorElementCount(), ZeroIsPoison, &VScaleRange); + Type *NewEltTy = IntegerType::getIntNTy(RetTy->getContext(), EltWidth); + + // Create the new vector type & get the vector length + Type *NewVecTy = VectorType::get( + NewEltTy, cast(Args[0]->getType())->getElementCount()); + + IntrinsicCostAttributes StepVecAttrs(Intrinsic::experimental_stepvector, + NewVecTy, {}, FMF); + InstructionCost Cost = + thisT()->getIntrinsicInstrCost(StepVecAttrs, CostKind); + + Cost += + thisT()->getArithmeticInstrCost(Instruction::Sub, NewVecTy, CostKind); + Cost += thisT()->getCastInstrCost(Instruction::SExt, NewVecTy, + Args[0]->getType(), + TTI::CastContextHint::None, CostKind); + Cost += + thisT()->getArithmeticInstrCost(Instruction::And, NewVecTy, CostKind); + + IntrinsicCostAttributes ReducAttrs(Intrinsic::vector_reduce_umax, + NewEltTy, NewVecTy, FMF, I, 1); + Cost += thisT()->getTypeBasedIntrinsicInstrCost(ReducAttrs, CostKind); + Cost += + thisT()->getArithmeticInstrCost(Instruction::Sub, NewEltTy, CostKind); + + return Cost; + } } // VP Intrinsics should have the same cost as their non-vp counterpart. diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 7ed08cfa8a20..50a8c7eb75af 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -470,6 +470,12 @@ public: /// expanded using generic code in SelectionDAGBuilder. virtual bool shouldExpandCttzElements(EVT VT) const { return true; } + /// Return the minimum number of bits required to hold the maximum possible + /// number of trailing zero vector elements. + unsigned getBitWidthForCttzElements(Type *RetTy, ElementCount EC, + bool ZeroIsPoison, + const ConstantRange *VScaleRange) const; + // Return true if op(vecreduce(x), vecreduce(y)) should be reassociated to // vecreduce(op(x, y)) for the reduction opcode RedOpc. virtual bool shouldReassociateReduction(unsigned RedOpc, EVT VT) const { diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 55aed43070df..9ef02a792fd0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -7861,20 +7861,15 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, Op = DAG.getSetCC(DL, OpVT, Op, AllZero, ISD::SETNE); } - // Find the smallest "sensible" element type to use for the expansion. - ConstantRange CR( - APInt(64, OpVT.getVectorElementCount().getKnownMinValue())); - if (OpVT.isScalableVT()) - CR = CR.umul_sat(getVScaleRange(I.getCaller(), 64)); - // If the zero-is-poison flag is set, we can assume the upper limit // of the result is VF-1. - if (!cast(getValue(I.getOperand(1)))->isZero()) - CR = CR.subtract(APInt(64, 1)); - - unsigned EltWidth = I.getType()->getScalarSizeInBits(); - EltWidth = std::min(EltWidth, (unsigned)CR.getActiveBits()); - EltWidth = std::max(llvm::bit_ceil(EltWidth), (unsigned)8); + bool ZeroIsPoison = + !cast(getValue(I.getOperand(1)))->isZero(); + ConstantRange VScaleRange(1, true); // Dummy value. + if (isa(I.getOperand(0)->getType())) + VScaleRange = getVScaleRange(I.getCaller(), 64); + unsigned EltWidth = TLI.getBitWidthForCttzElements( + I.getType(), OpVT.getVectorElementCount(), ZeroIsPoison, &VScaleRange); MVT NewEltTy = MVT::getIntegerVT(EltWidth); diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index 75b3f14e9622..09b70cfb7227 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -1048,6 +1048,24 @@ bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS, return TM.isNoopAddrSpaceCast(SrcAS, DestAS); } +unsigned TargetLoweringBase::getBitWidthForCttzElements( + Type *RetTy, ElementCount EC, bool ZeroIsPoison, + const ConstantRange *VScaleRange) const { + // Find the smallest "sensible" element type to use for the expansion. + ConstantRange CR(APInt(64, EC.getKnownMinValue())); + if (EC.isScalable()) + CR = CR.umul_sat(*VScaleRange); + + if (ZeroIsPoison) + CR = CR.subtract(APInt(64, 1)); + + unsigned EltWidth = RetTy->getScalarSizeInBits(); + EltWidth = std::min(EltWidth, (unsigned)CR.getActiveBits()); + EltWidth = std::max(llvm::bit_ceil(EltWidth), (unsigned)8); + + return EltWidth; +} + void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { // If the command-line option was specified, ignore this request. if (!JumpIsExpensiveOverride.getNumOccurrences()) diff --git a/llvm/test/Analysis/CostModel/AArch64/cttz_elts.ll b/llvm/test/Analysis/CostModel/AArch64/cttz_elts.ll new file mode 100644 index 000000000000..01dc086d9385 --- /dev/null +++ b/llvm/test/Analysis/CostModel/AArch64/cttz_elts.ll @@ -0,0 +1,209 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes="print" 2>&1 -disable-output -mtriple=aarch64-linux-gnu -mattr=+sve | FileCheck %s + +define void @foo_no_vscale_range() { +; CHECK-LABEL: 'foo_no_vscale_range' +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.nxv2i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res.i64.nxv4i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %res.i64.nxv8i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv16i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %res.i64.nxv32i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv2i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv4i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res.i32.nxv8i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv16i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %res.i32.nxv32i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.v2i1.zip = call i64 @llvm.experimental.cttz.elts.i64.v2i1(<2 x i1> undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.v4i1.zip = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.v8i1.zip = call i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1> undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.v16i1.zip = call i64 @llvm.experimental.cttz.elts.i64.v16i1(<16 x i1> undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res.i64.v32i1.zip = call i64 @llvm.experimental.cttz.elts.i64.v32i1(<32 x i1> undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.v2i1.zip = call i32 @llvm.experimental.cttz.elts.i32.v2i1(<2 x i1> undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.v4i1.zip = call i32 @llvm.experimental.cttz.elts.i32.v4i1(<4 x i1> undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.v8i1.zip = call i32 @llvm.experimental.cttz.elts.i32.v8i1(<8 x i1> undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.v16i1.zip = call i32 @llvm.experimental.cttz.elts.i32.v16i1(<16 x i1> undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res.i32.v32i1.zip = call i32 @llvm.experimental.cttz.elts.i32.v32i1(<32 x i1> undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.nxv2i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res.i64.nxv4i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %res.i64.nxv8i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv16i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %res.i64.nxv32i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv2i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv4i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res.i32.nxv8i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv16i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %res.i32.nxv32i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.v2i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.v2i1(<2 x i1> undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.v4i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.v8i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1> undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.v16i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.v16i1(<16 x i1> undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res.i64.v32i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.v32i1(<32 x i1> undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.v2i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.v2i1(<2 x i1> undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.v4i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.v4i1(<4 x i1> undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.v8i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.v8i1(<8 x i1> undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.v16i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.v16i1(<16 x i1> undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res.i32.v32i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.v32i1(<32 x i1> undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %res.i64.nxv2i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 true) + %res.i64.nxv4i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 true) + %res.i64.nxv8i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 true) + %res.i64.nxv16i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv161( undef, i1 true) + %res.i64.nxv32i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 true) + %res.i32.nxv2i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 true) + %res.i32.nxv4i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 true) + %res.i32.nxv8i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 true) + %res.i32.nxv16i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv161( undef, i1 true) + %res.i32.nxv32i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 true) + + %res.i64.v2i1.zip = call i64 @llvm.experimental.cttz.elts.i64.v2i1(<2 x i1> undef, i1 true) + %res.i64.v4i1.zip = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> undef, i1 true) + %res.i64.v8i1.zip = call i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1> undef, i1 true) + %res.i64.v16i1.zip = call i64 @llvm.experimental.cttz.elts.i64.v161(<16 x i1> undef, i1 true) + %res.i64.v32i1.zip = call i64 @llvm.experimental.cttz.elts.i64.v32i1(<32 x i1> undef, i1 true) + %res.i32.v2i1.zip = call i32 @llvm.experimental.cttz.elts.i32.v2i1(<2 x i1> undef, i1 true) + %res.i32.v4i1.zip = call i32 @llvm.experimental.cttz.elts.i32.v4i1(<4 x i1> undef, i1 true) + %res.i32.v8i1.zip = call i32 @llvm.experimental.cttz.elts.i32.v8i1(<8 x i1> undef, i1 true) + %res.i32.v16i1.zip = call i32 @llvm.experimental.cttz.elts.i32.v161(<16 x i1> undef, i1 true) + %res.i32.v32i1.zip = call i32 @llvm.experimental.cttz.elts.i32.v32i1(<32 x i1> undef, i1 true) + + %res.i64.nxv2i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 false) + %res.i64.nxv4i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 false) + %res.i64.nxv8i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 false) + %res.i64.nxv16i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv161( undef, i1 false) + %res.i64.nxv32i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 false) + %res.i32.nxv2i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 false) + %res.i32.nxv4i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 false) + %res.i32.nxv8i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 false) + %res.i32.nxv16i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv161( undef, i1 false) + %res.i32.nxv32i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 false) + + %res.i64.v2i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.v2i1(<2 x i1> undef, i1 false) + %res.i64.v4i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> undef, i1 false) + %res.i64.v8i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1> undef, i1 false) + %res.i64.v16i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.v161(<16 x i1> undef, i1 false) + %res.i64.v32i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.v32i1(<32 x i1> undef, i1 false) + %res.i32.v2i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.v2i1(<2 x i1> undef, i1 false) + %res.i32.v4i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.v4i1(<4 x i1> undef, i1 false) + %res.i32.v8i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.v8i1(<8 x i1> undef, i1 false) + %res.i32.v16i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.v161(<16 x i1> undef, i1 false) + %res.i32.v32i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.v32i1(<32 x i1> undef, i1 false) + + ret void +} + + +define void @foo_vscale_range_1_16() vscale_range(1,16) { +; CHECK-LABEL: 'foo_vscale_range_1_16' +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.nxv2i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.nxv4i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.nxv8i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv16i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res.i64.nxv32i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv2i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv4i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv8i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv16i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res.i32.nxv32i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.nxv2i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.nxv4i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.nxv8i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv16i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res.i64.nxv32i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv2i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv4i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv8i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv16i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res.i32.nxv32i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %res.i64.nxv2i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 true) + %res.i64.nxv4i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 true) + %res.i64.nxv8i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 true) + %res.i64.nxv16i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv161( undef, i1 true) + %res.i64.nxv32i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 true) + %res.i32.nxv2i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 true) + %res.i32.nxv4i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 true) + %res.i32.nxv8i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 true) + %res.i32.nxv16i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv161( undef, i1 true) + %res.i32.nxv32i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 true) + + %res.i64.nxv2i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 false) + %res.i64.nxv4i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 false) + %res.i64.nxv8i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 false) + %res.i64.nxv16i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv161( undef, i1 false) + %res.i64.nxv32i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 false) + %res.i32.nxv2i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 false) + %res.i32.nxv4i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 false) + %res.i32.nxv8i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 false) + %res.i32.nxv16i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv161( undef, i1 false) + %res.i32.nxv32i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 false) + + ret void +} + +define void @foo_vscale_range_1_16384() vscale_range(1,16384) { +; CHECK-LABEL: 'foo_vscale_range_1_16384' +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.nxv2i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.nxv4i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res.i64.nxv8i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv16i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %res.i64.nxv32i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv2i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv4i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res.i32.nxv8i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv16i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %res.i32.nxv32i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.nxv2i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i64.nxv4i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res.i64.nxv8i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv16i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %res.i64.nxv32i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv2i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %res.i32.nxv4i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res.i32.nxv8i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv16i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %res.i32.nxv32i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %res.i64.nxv2i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 true) + %res.i64.nxv4i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 true) + %res.i64.nxv8i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 true) + %res.i64.nxv16i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv161( undef, i1 true) + %res.i64.nxv32i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 true) + %res.i32.nxv2i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 true) + %res.i32.nxv4i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 true) + %res.i32.nxv8i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 true) + %res.i32.nxv16i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv161( undef, i1 true) + %res.i32.nxv32i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 true) + + %res.i64.nxv2i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 false) + %res.i64.nxv4i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 false) + %res.i64.nxv8i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 false) + %res.i64.nxv16i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv161( undef, i1 false) + %res.i64.nxv32i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 false) + %res.i32.nxv2i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 false) + %res.i32.nxv4i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 false) + %res.i32.nxv8i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 false) + %res.i32.nxv16i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv161( undef, i1 false) + %res.i32.nxv32i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 false) + + ret void +} + +declare i64 @llvm.experimental.cttz.elts.i64.nxv2i1(, i1) +declare i64 @llvm.experimental.cttz.elts.i64.nxv4i1(, i1) +declare i64 @llvm.experimental.cttz.elts.i64.nxv8i1(, i1) +declare i64 @llvm.experimental.cttz.elts.i64.nxv16i1(, i1) +declare i64 @llvm.experimental.cttz.elts.i64.nxv32i1(, i1) +declare i64 @llvm.experimental.cttz.elts.i64.v2i1(<2 x i1>, i1) +declare i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1>, i1) +declare i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1>, i1) +declare i64 @llvm.experimental.cttz.elts.i64.v16i1(<16 x i1>, i1) +declare i64 @llvm.experimental.cttz.elts.i64.v32i1(<32 x i1>, i1) + +declare i32 @llvm.experimental.cttz.elts.i32.nxv2i1(, i1) +declare i32 @llvm.experimental.cttz.elts.i32.nxv4i1(, i1) +declare i32 @llvm.experimental.cttz.elts.i32.nxv8i1(, i1) +declare i32 @llvm.experimental.cttz.elts.i32.nxv16i1(, i1) +declare i32 @llvm.experimental.cttz.elts.i32.nxv32i1(, i1) diff --git a/llvm/test/Analysis/CostModel/RISCV/cttz_elts.ll b/llvm/test/Analysis/CostModel/RISCV/cttz_elts.ll new file mode 100644 index 000000000000..ca09d027b547 --- /dev/null +++ b/llvm/test/Analysis/CostModel/RISCV/cttz_elts.ll @@ -0,0 +1,149 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v | FileCheck %s + +define void @foo_no_vscale_range() { +; CHECK-LABEL: 'foo_no_vscale_range' +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv2i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv4i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv8i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv16i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv32i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv64i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv64i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 781 for instruction: %res.i64.nxv128i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv128i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv2i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv4i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv8i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv16i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv32i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv64i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv64i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 390 for instruction: %res.i32.nxv128i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv128i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv2i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv4i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv8i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv16i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv32i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv64i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv64i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 781 for instruction: %res.i64.nxv128i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv128i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv2i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv4i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv8i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv16i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv32i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv64i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv64i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 390 for instruction: %res.i32.nxv128i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv128i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %res.i64.nxv2i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 true) + %res.i64.nxv4i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 true) + %res.i64.nxv8i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 true) + %res.i64.nxv16i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv161( undef, i1 true) + %res.i64.nxv32i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 true) + %res.i64.nxv64i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv64i1( undef, i1 true) + %res.i64.nxv128i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv128i1( undef, i1 true) + %res.i32.nxv2i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 true) + %res.i32.nxv4i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 true) + %res.i32.nxv8i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 true) + %res.i32.nxv16i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv161( undef, i1 true) + %res.i32.nxv32i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 true) + %res.i32.nxv64i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv64i1( undef, i1 true) + %res.i32.nxv128i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv128i1( undef, i1 true) + + %res.i64.nxv2i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 false) + %res.i64.nxv4i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 false) + %res.i64.nxv8i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 false) + %res.i64.nxv16i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv161( undef, i1 false) + %res.i64.nxv32i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 false) + %res.i64.nxv64i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv64i1( undef, i1 false) + %res.i64.nxv128i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv128i1( undef, i1 false) + %res.i32.nxv2i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 false) + %res.i32.nxv4i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 false) + %res.i32.nxv8i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 false) + %res.i32.nxv16i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv161( undef, i1 false) + %res.i32.nxv32i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 false) + %res.i32.nxv64i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv64i1( undef, i1 false) + %res.i32.nxv128i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv128i1( undef, i1 false) + + ret void +} + + +define void @foo_vscale_range_2_16() vscale_range(2,16) { +; CHECK-LABEL: 'foo_vscale_range_2_16' +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv2i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv4i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv8i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv16i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv32i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv64i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv64i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 195 for instruction: %res.i64.nxv128i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv128i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv2i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv4i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv8i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv16i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv32i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv64i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv64i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 195 for instruction: %res.i32.nxv128i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv128i1( undef, i1 true) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv2i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv4i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv8i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv16i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv32i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i64.nxv64i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv64i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 195 for instruction: %res.i64.nxv128i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv128i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv2i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv4i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv8i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv16i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv32i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.i32.nxv64i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv64i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 195 for instruction: %res.i32.nxv128i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv128i1( undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %res.i64.nxv2i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 true) + %res.i64.nxv4i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 true) + %res.i64.nxv8i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 true) + %res.i64.nxv16i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv161( undef, i1 true) + %res.i64.nxv32i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 true) + %res.i64.nxv64i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv64i1( undef, i1 true) + %res.i64.nxv128i1.zip = call i64 @llvm.experimental.cttz.elts.i64.nxv128i1( undef, i1 true) + %res.i32.nxv2i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 true) + %res.i32.nxv4i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 true) + %res.i32.nxv8i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 true) + %res.i32.nxv16i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv161( undef, i1 true) + %res.i32.nxv32i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 true) + %res.i32.nxv64i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv64i1( undef, i1 true) + %res.i32.nxv128i1.zip = call i32 @llvm.experimental.cttz.elts.i32.nxv128i1( undef, i1 true) + + %res.i64.nxv2i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( undef, i1 false) + %res.i64.nxv4i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( undef, i1 false) + %res.i64.nxv8i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( undef, i1 false) + %res.i64.nxv16i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv161( undef, i1 false) + %res.i64.nxv32i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( undef, i1 false) + %res.i64.nxv64i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv64i1( undef, i1 false) + %res.i64.nxv128i1.nzip = call i64 @llvm.experimental.cttz.elts.i64.nxv128i1( undef, i1 false) + %res.i32.nxv2i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv2i1( undef, i1 false) + %res.i32.nxv4i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv4i1( undef, i1 false) + %res.i32.nxv8i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv8i1( undef, i1 false) + %res.i32.nxv16i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv161( undef, i1 false) + %res.i32.nxv32i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv32i1( undef, i1 false) + %res.i32.nxv64i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv64i1( undef, i1 false) + %res.i32.nxv128i1.nzip = call i32 @llvm.experimental.cttz.elts.i32.nxv128i1( undef, i1 false) + + ret void +} + +declare i64 @llvm.experimental.cttz.elts.i64.nxv2i1(, i1) +declare i64 @llvm.experimental.cttz.elts.i64.nxv4i1(, i1) +declare i64 @llvm.experimental.cttz.elts.i64.nxv8i1(, i1) +declare i64 @llvm.experimental.cttz.elts.i64.nxv16i1(, i1) +declare i64 @llvm.experimental.cttz.elts.i64.nxv32i1(, i1) +declare i64 @llvm.experimental.cttz.elts.i64.nxv64i1(, i1) +declare i64 @llvm.experimental.cttz.elts.i64.nxv128i1(, i1) + +declare i32 @llvm.experimental.cttz.elts.i32.nxv2i1(, i1) +declare i32 @llvm.experimental.cttz.elts.i32.nxv4i1(, i1) +declare i32 @llvm.experimental.cttz.elts.i32.nxv8i1(, i1) +declare i32 @llvm.experimental.cttz.elts.i32.nxv16i1(, i1) +declare i32 @llvm.experimental.cttz.elts.i32.nxv32i1(, i1) +declare i32 @llvm.experimental.cttz.elts.i32.nxv64i1(, i1) +declare i32 @llvm.experimental.cttz.elts.i32.nxv128i1(, i1) -- GitLab From 105dd60fc86a20404bd97ea7132e2c746ade300a Mon Sep 17 00:00:00 2001 From: Lukacma Date: Thu, 9 May 2024 10:45:19 +0100 Subject: [PATCH 119/328] [Clang][AArch64] Fixed incorrect _BitInt alignment (#90602) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch makes determining alignment and width of BitInt to be target ABI specific and makes it consistent with [Procedure Call Standard for the Arm® 64-bit Architecture (AArch64)](https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst) for AArch64 targets. --- clang/include/clang/Basic/TargetInfo.h | 20 ++++++++ clang/lib/AST/ASTContext.cpp | 5 +- clang/lib/Basic/Targets/AArch64.cpp | 1 + clang/test/CodeGen/aapcs64-align.cpp | 64 +++++++++++++++++++++++++- 4 files changed, 86 insertions(+), 4 deletions(-) diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index 3ced2e7397a7..8a6511b9ced8 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -97,6 +97,10 @@ struct TransferrableTargetInfo { unsigned char LongLongWidth, LongLongAlign; unsigned char Int128Align; + // This is an optional parameter for targets that + // don't use 'LongLongAlign' for '_BitInt' max alignment + std::optional BitIntMaxAlign; + // Fixed point bit widths unsigned char ShortAccumWidth, ShortAccumAlign; unsigned char AccumWidth, AccumAlign; @@ -518,6 +522,22 @@ public: /// getInt128Align() - Returns the alignment of Int128. unsigned getInt128Align() const { return Int128Align; } + /// getBitIntMaxAlign() - Returns the maximum possible alignment of + /// '_BitInt' and 'unsigned _BitInt'. + unsigned getBitIntMaxAlign() const { + return BitIntMaxAlign.value_or(LongLongAlign); + } + + /// getBitIntAlign/Width - Return aligned size of '_BitInt' and + /// 'unsigned _BitInt' for this target, in bits. + unsigned getBitIntWidth(unsigned NumBits) const { + return llvm::alignTo(NumBits, getBitIntAlign(NumBits)); + } + unsigned getBitIntAlign(unsigned NumBits) const { + return std::clamp(llvm::PowerOf2Ceil(NumBits), getCharWidth(), + getBitIntMaxAlign()); + } + /// getShortAccumWidth/Align - Return the size of 'signed short _Accum' and /// 'unsigned short _Accum' for this target, in bits. unsigned getShortAccumWidth() const { return ShortAccumWidth; } diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index 91e7a5f67a93..4475f399a120 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -2258,9 +2258,8 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T) const { } case Type::BitInt: { const auto *EIT = cast(T); - Align = std::clamp(llvm::PowerOf2Ceil(EIT->getNumBits()), - getCharWidth(), Target->getLongLongAlign()); - Width = llvm::alignTo(EIT->getNumBits(), Align); + Align = Target->getBitIntAlign(EIT->getNumBits()); + Width = Target->getBitIntWidth(EIT->getNumBits()); break; } case Type::Record: diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index 1a02520d7bd1..4b1545339f69 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -154,6 +154,7 @@ AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple, else LongWidth = LongAlign = PointerWidth = PointerAlign = 32; + BitIntMaxAlign = 128; MaxVectorAlign = 128; MaxAtomicInlineWidth = 128; MaxAtomicPromoteWidth = 128; diff --git a/clang/test/CodeGen/aapcs64-align.cpp b/clang/test/CodeGen/aapcs64-align.cpp index de231f2123b9..7a8151022852 100644 --- a/clang/test/CodeGen/aapcs64-align.cpp +++ b/clang/test/CodeGen/aapcs64-align.cpp @@ -1,7 +1,7 @@ // REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple aarch64-none-elf \ // RUN: -O2 \ -// RUN: -emit-llvm -o - %s | FileCheck %s +// RUN: -emit-llvm -fexperimental-max-bitint-width=1024 -o - %s | FileCheck %s extern "C" { @@ -100,4 +100,66 @@ void f5m(int, int, int, int, int, P16); // CHECK: declare void @f5(i32 noundef, [2 x i64]) // CHECK: declare void @f5m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [2 x i64]) +//BitInt alignment +struct BITINT129 { + char ch; + unsigned _BitInt(129) v; +}; + +int test_bitint129(){ + return __builtin_offsetof(struct BITINT129, v); } +// CHECK: ret i32 16 + +struct BITINT127 { + char ch; + _BitInt(127) v; +}; + +int test_bitint127(){ + return __builtin_offsetof(struct BITINT127, v); +} +// CHECK: ret i32 16 + +struct BITINT63 { + char ch; + _BitInt(63) v; +}; + +int test_bitint63(){ + return __builtin_offsetof(struct BITINT63, v); +} +// CHECK: ret i32 8 + +struct BITINT32 { + char ch; + unsigned _BitInt(32) v; +}; + +int test_bitint32(){ + return __builtin_offsetof(struct BITINT32, v); +} +// CHECK: ret i32 4 + +struct BITINT9 { + char ch; + unsigned _BitInt(9) v; +}; + +int test_bitint9(){ + return __builtin_offsetof(struct BITINT9, v); +} +// CHECK: ret i32 2 + +struct BITINT8 { + char ch; + unsigned _BitInt(8) v; +}; + +int test_bitint8(){ + return __builtin_offsetof(struct BITINT8, v); +} +// CHECK: ret i32 1 + +} + -- GitLab From 8afa6cf510608079e24d07423782c4db20de7498 Mon Sep 17 00:00:00 2001 From: Hristo Hristov Date: Thu, 9 May 2024 12:48:37 +0300 Subject: [PATCH 120/328] [libc++][functional] P2944R3 (partial): Comparisons for `reference_wrapper` (`reference_wrapper` operators only) (#88384) Implements https://wg21.link/P2944R3 (partially) Implements https://wg21.link/LWG4071 / https://cplusplus.github.io/LWG/issue4071 (fixes build failures in the test suite) - https://eel.is/c++draft/refwrap.comparisons --- libcxx/docs/FeatureTestMacroTable.rst | 2 +- libcxx/docs/ReleaseNotes/19.rst | 1 + libcxx/docs/Status/Cxx2c.rst | 1 + libcxx/docs/Status/Cxx2cIssues.csv | 1 + libcxx/docs/Status/Cxx2cPapers.csv | 2 +- .../include/__functional/reference_wrapper.h | 51 ++++++++++ libcxx/include/functional | 9 ++ libcxx/include/version | 2 +- .../functional.version.compile.pass.cpp | 16 +--- .../version.version.compile.pass.cpp | 16 +--- ...mpare.three_way.refwrap.const_ref.pass.cpp | 89 +++++++++++++++++ ...compare.three_way.refwrap.refwrap.pass.cpp | 93 ++++++++++++++++++ ...e.three_way.refwrap.refwrap_const.pass.cpp | 95 +++++++++++++++++++ .../equal.refwrap.const_ref.pass.cpp | 62 ++++++++++++ .../equal.refwrap.refwrap.pass.cpp | 64 +++++++++++++ .../equal.refwrap.refwrap_const.pass.cpp | 67 +++++++++++++ .../refwrap.comparissons/helper_concepts.h | 38 ++++++++ .../refwrap.comparissons/helper_types.h | 30 ++++++ .../generate_feature_test_macro_components.py | 1 - 19 files changed, 614 insertions(+), 26 deletions(-) create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/compare.three_way.refwrap.const_ref.pass.cpp create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/compare.three_way.refwrap.refwrap.pass.cpp create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/compare.three_way.refwrap.refwrap_const.pass.cpp create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/equal.refwrap.const_ref.pass.cpp create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/equal.refwrap.refwrap.pass.cpp create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/equal.refwrap.refwrap_const.pass.cpp create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/helper_concepts.h create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/helper_types.h diff --git a/libcxx/docs/FeatureTestMacroTable.rst b/libcxx/docs/FeatureTestMacroTable.rst index 1032a9c338f4..17b3476d2c86 100644 --- a/libcxx/docs/FeatureTestMacroTable.rst +++ b/libcxx/docs/FeatureTestMacroTable.rst @@ -446,7 +446,7 @@ Status ---------------------------------------------------------- ----------------- ``__cpp_lib_rcu`` *unimplemented* ---------------------------------------------------------- ----------------- - ``__cpp_lib_reference_wrapper`` *unimplemented* + ``__cpp_lib_reference_wrapper`` ``202403L`` ---------------------------------------------------------- ----------------- ``__cpp_lib_saturation_arithmetic`` ``202311L`` ---------------------------------------------------------- ----------------- diff --git a/libcxx/docs/ReleaseNotes/19.rst b/libcxx/docs/ReleaseNotes/19.rst index 5a07b11cbcd5..3fc007f45985 100644 --- a/libcxx/docs/ReleaseNotes/19.rst +++ b/libcxx/docs/ReleaseNotes/19.rst @@ -46,6 +46,7 @@ Implemented Papers - P2869R4 - Remove Deprecated ``shared_ptr`` Atomic Access APIs from C++26 - P2872R3 - Remove ``wstring_convert`` From C++26 - P3142R0 - Printing Blank Lines with ``println`` (as DR against C++23) +- P2944R3 - Comparisons for ``reference_wrapper`` (comparison operators for ``reference_wrapper`` only) - P2302R4 - ``std::ranges::contains`` - P1659R3 - ``std::ranges::starts_with`` and ``std::ranges::ends_with`` - P3029R1 - Better ``mdspan``'s CTAD diff --git a/libcxx/docs/Status/Cxx2c.rst b/libcxx/docs/Status/Cxx2c.rst index e3d9cbb551ff..5f459b4b3e4e 100644 --- a/libcxx/docs/Status/Cxx2c.rst +++ b/libcxx/docs/Status/Cxx2c.rst @@ -41,6 +41,7 @@ Paper Status .. [#note-P2510R3] This paper is applied as DR against C++20. (MSVC STL and libstdc++ will do the same.) .. [#note-P3142R0] This paper is applied as DR against C++23. (MSVC STL and libstdc++ will do the same.) + .. [#note-P2944R3] Implemented comparisons for ``reference_wrapper`` only. .. _issues-status-cxx2c: diff --git a/libcxx/docs/Status/Cxx2cIssues.csv b/libcxx/docs/Status/Cxx2cIssues.csv index 30a059f8a3df..76717e1d3448 100644 --- a/libcxx/docs/Status/Cxx2cIssues.csv +++ b/libcxx/docs/Status/Cxx2cIssues.csv @@ -64,4 +64,5 @@ "","","","","","" "`3343 `__","Ordering of calls to ``unlock()`` and ``notify_all()`` in Effects element of ``notify_all_at_thread_exit()`` should be reversed","Not Yet Adopted","|Complete|","16.0","" "XXXX","","The sys_info range should be affected by save","Not Yet Adopted","|Complete|","19.0" +"`4071 `__","","``reference_wrapper`` comparisons are not SFINAE-friendly","Not Yet Adopted","|Complete|","19.0" "","","","","","" diff --git a/libcxx/docs/Status/Cxx2cPapers.csv b/libcxx/docs/Status/Cxx2cPapers.csv index 409278db1e87..30a601858b63 100644 --- a/libcxx/docs/Status/Cxx2cPapers.csv +++ b/libcxx/docs/Status/Cxx2cPapers.csv @@ -59,7 +59,7 @@ "`P2248R8 `__","LWG","Enabling list-initialization for algorithms","Tokyo March 2024","","","" "`P2810R4 `__","LWG","``is_debugger_present`` ``is_replaceable``","Tokyo March 2024","","","" "`P1068R11 `__","LWG","Vector API for random number generation","Tokyo March 2024","","","" -"`P2944R3 `__","LWG","Comparisons for ``reference_wrapper``","Tokyo March 2024","","","" +"`P2944R3 `__","LWG","Comparisons for ``reference_wrapper``","Tokyo March 2024","|Partial| [#note-P2944R3]_","19.0","" "`P2642R6 `__","LWG","Padded ``mdspan`` layouts","Tokyo March 2024","","","" "`P3029R1 `__","LWG","Better ``mdspan``'s CTAD","Tokyo March 2024","|Complete|","19.0","" "","","","","","","" diff --git a/libcxx/include/__functional/reference_wrapper.h b/libcxx/include/__functional/reference_wrapper.h index 94b39e3bc786..ab5d7c7cee11 100644 --- a/libcxx/include/__functional/reference_wrapper.h +++ b/libcxx/include/__functional/reference_wrapper.h @@ -10,11 +10,14 @@ #ifndef _LIBCPP___FUNCTIONAL_REFERENCE_WRAPPER_H #define _LIBCPP___FUNCTIONAL_REFERENCE_WRAPPER_H +#include <__compare/synth_three_way.h> +#include <__concepts/boolean_testable.h> #include <__config> #include <__functional/invoke.h> #include <__functional/weak_result_type.h> #include <__memory/addressof.h> #include <__type_traits/enable_if.h> +#include <__type_traits/is_const.h> #include <__type_traits/remove_cvref.h> #include <__type_traits/void_t.h> #include <__utility/declval.h> @@ -64,6 +67,54 @@ public: { return std::__invoke(get(), std::forward<_ArgTypes>(__args)...); } + +#if _LIBCPP_STD_VER >= 26 + + // [refwrap.comparisons], comparisons + + _LIBCPP_HIDE_FROM_ABI friend constexpr bool operator==(reference_wrapper __x, reference_wrapper __y) + requires requires { + { __x.get() == __y.get() } -> __boolean_testable; + } + { + return __x.get() == __y.get(); + } + + _LIBCPP_HIDE_FROM_ABI friend constexpr bool operator==(reference_wrapper __x, const _Tp& __y) + requires requires { + { __x.get() == __y } -> __boolean_testable; + } + { + return __x.get() == __y; + } + + _LIBCPP_HIDE_FROM_ABI friend constexpr bool operator==(reference_wrapper __x, reference_wrapper __y) + requires(!is_const_v<_Tp>) && requires { + { __x.get() == __y.get() } -> __boolean_testable; + } + { + return __x.get() == __y.get(); + } + + _LIBCPP_HIDE_FROM_ABI friend constexpr auto operator<=>(reference_wrapper __x, reference_wrapper __y) + requires requires { std::__synth_three_way(__x.get(), __y.get()); } + { + return std::__synth_three_way(__x.get(), __y.get()); + } + + _LIBCPP_HIDE_FROM_ABI friend constexpr auto operator<=>(reference_wrapper __x, const _Tp& __y) + requires requires { std::__synth_three_way(__x.get(), __y); } + { + return std::__synth_three_way(__x.get(), __y); + } + + _LIBCPP_HIDE_FROM_ABI friend constexpr auto operator<=>(reference_wrapper __x, reference_wrapper __y) + requires(!is_const_v<_Tp>) && requires { std::__synth_three_way(__x.get(), __y.get()); } + { + return std::__synth_three_way(__x.get(), __y.get()); + } + +#endif // _LIBCPP_STD_VER >= 26 }; #if _LIBCPP_STD_VER >= 17 diff --git a/libcxx/include/functional b/libcxx/include/functional index a2476c93ad1b..27cf21e1a4c8 100644 --- a/libcxx/include/functional +++ b/libcxx/include/functional @@ -77,6 +77,15 @@ template struct unwrap_ref_decay : unwrap_reference> { }; template using unwrap_reference_t = typename unwrap_reference::type; // since C++20 template using unwrap_ref_decay_t = typename unwrap_ref_decay::type; // since C++20 +// [refwrap.comparisons], comparisons +friend constexpr bool operator==(reference_wrapper, reference_wrapper); // Since C++26 +friend constexpr bool operator==(reference_wrapper, const T&); // Since C++26 +friend constexpr bool operator==(reference_wrapper, reference_wrapper); // Since C++26 + +friend constexpr auto operator<=>(reference_wrapper, reference_wrapper); // Since C++26 +friend constexpr auto operator<=>(reference_wrapper, const T&); // Since C++26 +friend constexpr auto operator<=>(reference_wrapper, reference_wrapper); // Since C++26 + template // in C++14 struct plus { T operator()(const T& x, const T& y) const; diff --git a/libcxx/include/version b/libcxx/include/version index eb5fd5c80578..ba116957b033 100644 --- a/libcxx/include/version +++ b/libcxx/include/version @@ -526,7 +526,7 @@ __cpp_lib_within_lifetime 202306L // # define __cpp_lib_ranges_concat 202403L # define __cpp_lib_ratio 202306L // # define __cpp_lib_rcu 202306L -// # define __cpp_lib_reference_wrapper 202403L +# define __cpp_lib_reference_wrapper 202403L # define __cpp_lib_saturation_arithmetic 202311L // # define __cpp_lib_smart_ptr_owner_equality 202306L # define __cpp_lib_span_at 202311L diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp index aeb09a30b425..27e76e5b2b05 100644 --- a/libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp +++ b/libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp @@ -535,17 +535,11 @@ # error "__cpp_lib_ranges should have the value 202207L in c++26" # endif -# if !defined(_LIBCPP_VERSION) -# ifndef __cpp_lib_reference_wrapper -# error "__cpp_lib_reference_wrapper should be defined in c++26" -# endif -# if __cpp_lib_reference_wrapper != 202403L -# error "__cpp_lib_reference_wrapper should have the value 202403L in c++26" -# endif -# else // _LIBCPP_VERSION -# ifdef __cpp_lib_reference_wrapper -# error "__cpp_lib_reference_wrapper should not be defined because it is unimplemented in libc++!" -# endif +# ifndef __cpp_lib_reference_wrapper +# error "__cpp_lib_reference_wrapper should be defined in c++26" +# endif +# if __cpp_lib_reference_wrapper != 202403L +# error "__cpp_lib_reference_wrapper should have the value 202403L in c++26" # endif # ifndef __cpp_lib_result_of_sfinae diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp index da7a780528c7..d7035d7e5e3a 100644 --- a/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp +++ b/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp @@ -7464,17 +7464,11 @@ # endif # endif -# if !defined(_LIBCPP_VERSION) -# ifndef __cpp_lib_reference_wrapper -# error "__cpp_lib_reference_wrapper should be defined in c++26" -# endif -# if __cpp_lib_reference_wrapper != 202403L -# error "__cpp_lib_reference_wrapper should have the value 202403L in c++26" -# endif -# else // _LIBCPP_VERSION -# ifdef __cpp_lib_reference_wrapper -# error "__cpp_lib_reference_wrapper should not be defined because it is unimplemented in libc++!" -# endif +# ifndef __cpp_lib_reference_wrapper +# error "__cpp_lib_reference_wrapper should be defined in c++26" +# endif +# if __cpp_lib_reference_wrapper != 202403L +# error "__cpp_lib_reference_wrapper should have the value 202403L in c++26" # endif # ifndef __cpp_lib_remove_cvref diff --git a/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/compare.three_way.refwrap.const_ref.pass.cpp b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/compare.three_way.refwrap.const_ref.pass.cpp new file mode 100644 index 000000000000..85106c18ec35 --- /dev/null +++ b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/compare.three_way.refwrap.const_ref.pass.cpp @@ -0,0 +1,89 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17, c++20, c++23 + +// + +// class reference_wrapper + +// [refwrap.comparisons], comparisons + +// friend constexpr auto operator<=>(reference_wrapper, const T&); // Since C++26 + +#include +#include +#include + +#include "test_comparisons.h" +#include "test_macros.h" + +#include "helper_concepts.h" +#include "helper_types.h" + +// Test SFINAE. + +static_assert(HasSpaceshipOperatorWithInt>); +static_assert(HasSpaceshipOperatorWithInt>); +static_assert(HasSpaceshipOperatorWithInt>); + +static_assert(!HasSpaceshipOperatorWithInt>); + +// Test comparisons. + +template +constexpr void test() { + T t{47}; + + T bigger{94}; + T smaller{82}; + + T unordered{std::numeric_limits::min()}; + + // Identical contents + { + std::reference_wrapper rw1{t}; + assert(testOrder(rw1, t, Order::equivalent)); + } + // Less + { + std::reference_wrapper rw1{smaller}; + assert(testOrder(rw1, bigger, Order::less)); + } + // Greater + { + std::reference_wrapper rw1{bigger}; + assert(testOrder(rw1, smaller, Order::greater)); + } + // Unordered + if constexpr (std::same_as) { + std::reference_wrapper rw1{bigger}; + assert(testOrder(rw1, unordered, Order::unordered)); + } +} + +constexpr bool test() { + test(); + test(); + test(); + test(); + test(); + test(); + + // `LessAndEqComp` does not have `operator<=>`. Ordering is synthesized based on `operator<` + test(); + + return true; +} + +int main(int, char**) { + test(); + static_assert(test()); + + return 0; +} diff --git a/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/compare.three_way.refwrap.refwrap.pass.cpp b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/compare.three_way.refwrap.refwrap.pass.cpp new file mode 100644 index 000000000000..794fac00de8a --- /dev/null +++ b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/compare.three_way.refwrap.refwrap.pass.cpp @@ -0,0 +1,93 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17, c++20, c++23 + +// + +// class reference_wrapper + +// [refwrap.comparisons], comparisons + +// friend constexpr auto operator<=>(reference_wrapper, reference_wrapper); // Since C++26 + +#include +#include +#include + +#include "test_comparisons.h" +#include "test_macros.h" + +#include "helper_concepts.h" +#include "helper_types.h" + +// Test SFINAE. + +static_assert(std::three_way_comparable>); +static_assert(std::three_way_comparable>); +static_assert(std::three_way_comparable>); + +static_assert(!std::three_way_comparable>); + +// Test comparisons. + +template +constexpr void test() { + T t{47}; + + T bigger{94}; + T smaller{82}; + + T unordered{std::numeric_limits::min()}; + + // Identical contents + { + std::reference_wrapper rw1{t}; + std::reference_wrapper rw2{t}; + assert(testOrder(rw1, rw2, Order::equivalent)); + } + // Less + { + std::reference_wrapper rw1{smaller}; + std::reference_wrapper rw2{bigger}; + assert(testOrder(rw1, rw2, Order::less)); + } + // Greater + { + std::reference_wrapper rw1{bigger}; + std::reference_wrapper rw2{smaller}; + assert(testOrder(rw1, rw2, Order::greater)); + } + // Unordered + if constexpr (std::same_as) { + std::reference_wrapper rw1{bigger}; + std::reference_wrapper rw2{unordered}; + assert(testOrder(rw1, rw2, Order::unordered)); + } +} + +constexpr bool test() { + test(); + test(); + test(); + test(); + test(); + test(); + + // `LessAndEqComp` does not have `operator<=>`. Ordering is synthesized based on `operator<` + test(); + + return true; +} + +int main(int, char**) { + test(); + static_assert(test()); + + return 0; +} diff --git a/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/compare.three_way.refwrap.refwrap_const.pass.cpp b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/compare.three_way.refwrap.refwrap_const.pass.cpp new file mode 100644 index 000000000000..9b1302affa85 --- /dev/null +++ b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/compare.three_way.refwrap.refwrap_const.pass.cpp @@ -0,0 +1,95 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17, c++20, c++23 + +// + +// class reference_wrapper + +// [refwrap.comparisons], comparisons + +// friend constexpr auto operator<=>(reference_wrapper, reference_wrapper); // Since C++26 + +#include +#include +#include + +#include "test_comparisons.h" +#include "test_macros.h" + +#include "helper_concepts.h" +#include "helper_types.h" + +// Test SFINAE. + +static_assert(std::three_way_comparable_with, const StrongOrder>); +static_assert(std::three_way_comparable_with, const WeakOrder>); +static_assert(std::three_way_comparable_with, const PartialOrder>); + +static_assert(!std::three_way_comparable_with, const NonComparable>); +static_assert(!std::three_way_comparable_with, const NonComparable>); +static_assert(!std::three_way_comparable_with, const NonComparable>); + +// Test comparisons. + +template +constexpr void test() { + T t{47}; + + T bigger{94}; + T smaller{82}; + + T unordered{std::numeric_limits::min()}; + + // Identical contents + { + std::reference_wrapper rw1{t}; + std::reference_wrapper rw2{t}; + assert(testOrder(rw1, rw2, Order::equivalent)); + } + // Less + { + std::reference_wrapper rw1{smaller}; + std::reference_wrapper rw2{bigger}; + assert(testOrder(rw1, rw2, Order::less)); + } + // Greater + { + std::reference_wrapper rw1{bigger}; + std::reference_wrapper rw2{smaller}; + assert(testOrder(rw1, rw2, Order::greater)); + } + // Unordered + if constexpr (std::same_as) { + std::reference_wrapper rw1{bigger}; + std::reference_wrapper rw2{unordered}; + assert(testOrder(rw1, rw2, Order::unordered)); + } +} + +constexpr bool test() { + test(); + test(); + test(); + test(); + test(); + test(); + + // `LessAndEqComp` does not have `operator<=>`. Ordering is synthesized based on `operator<` + test(); + + return true; +} + +int main(int, char**) { + test(); + static_assert(test()); + + return 0; +} diff --git a/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/equal.refwrap.const_ref.pass.cpp b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/equal.refwrap.const_ref.pass.cpp new file mode 100644 index 000000000000..465326818f17 --- /dev/null +++ b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/equal.refwrap.const_ref.pass.cpp @@ -0,0 +1,62 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17, c++20, c++23 + +// + +// class reference_wrapper + +// [refwrap.comparisons], comparisons + +// friend constexpr bool operator==(reference_wrapper, const T&); // Since C++26 + +#include +#include +#include + +#include "test_comparisons.h" +#include "test_macros.h" + +#include "helper_concepts.h" +#include "helper_types.h" + +// Test SFINAE. + +static_assert(HasEqualityOperatorWithInt>); + +static_assert(!HasEqualityOperatorWithInt>); + +// Test equality. + +template +constexpr void test() { + T i{92}; + T j{84}; + + std::reference_wrapper rw1{i}; + + // refwrap, const& + AssertEqualityReturnBool(); + assert(testEquality(rw1, i, true)); + assert(testEquality(rw1, j, false)); +} + +constexpr bool test() { + test(); + test(); + + return true; +} + +int main(int, char**) { + test(); + static_assert(test()); + + return 0; +} diff --git a/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/equal.refwrap.refwrap.pass.cpp b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/equal.refwrap.refwrap.pass.cpp new file mode 100644 index 000000000000..a50b530bbc6e --- /dev/null +++ b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/equal.refwrap.refwrap.pass.cpp @@ -0,0 +1,64 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17, c++20, c++23 + +// + +// class reference_wrapper + +// [refwrap.comparisons], comparisons +// friend constexpr bool operator==(reference_wrapper, reference_wrapper); // Since C++26 + +#include +#include +#include + +#include "test_comparisons.h" +#include "test_macros.h" + +#include "helper_concepts.h" +#include "helper_types.h" + +// Test SFINAE. + +static_assert(std::equality_comparable>); + +static_assert(!std::equality_comparable>); + +// Test equality. + +template +constexpr void test() { + T i{92}; + T j{84}; + + std::reference_wrapper rw1{i}; + std::reference_wrapper rw2 = rw1; + std::reference_wrapper rw3{j}; + std::reference_wrapper crw1{i}; + std::reference_wrapper crw3{j}; + + AssertEqualityReturnBool(); + assert(testEquality(rw1, rw2, true)); + assert(testEquality(rw1, rw3, false)); +} + +constexpr bool test() { + test(); + test(); + + return true; +} + +int main(int, char**) { + test(); + static_assert(test()); + + return 0; +} diff --git a/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/equal.refwrap.refwrap_const.pass.cpp b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/equal.refwrap.refwrap_const.pass.cpp new file mode 100644 index 000000000000..10f017742a87 --- /dev/null +++ b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/equal.refwrap.refwrap_const.pass.cpp @@ -0,0 +1,67 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17, c++20, c++23 + +// + +// class reference_wrapper + +// [refwrap.comparisons], comparisons + +// friend constexpr bool operator==(reference_wrapper, reference_wrapper); // Since C++26 + +#include +#include +#include + +#include "test_comparisons.h" +#include "test_macros.h" + +#include "helper_concepts.h" +#include "helper_types.h" + +// Test SFINAE. + +static_assert(std::equality_comparable_with, + std::reference_wrapper>); + +static_assert(!std::equality_comparable_with, + std::reference_wrapper>); + +// Test equality. + +template +constexpr void test() { + T i{92}; + T j{84}; + + std::reference_wrapper rw1{i}; + + std::reference_wrapper rw3{j}; + std::reference_wrapper crw1{i}; + std::reference_wrapper crw3{j}; + + AssertEqualityReturnBool(); + assert(testEquality(rw1, crw1, true)); + assert(testEquality(rw1, crw3, false)); +} + +constexpr bool test() { + test(); + test(); + + return true; +} + +int main(int, char**) { + test(); + static_assert(test()); + + return 0; +} diff --git a/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/helper_concepts.h b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/helper_concepts.h new file mode 100644 index 000000000000..2dbb304f8af6 --- /dev/null +++ b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/helper_concepts.h @@ -0,0 +1,38 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef TEST_STD_FUNCTIONOBJECTS_REFWRAP_HELPER_CONCEPTS_H +#define TEST_STD_FUNCTIONOBJECTS_REFWRAP_HELPER_CONCEPTS_H + +#include +#include + +// Equality + +template +concept HasEqualityOperatorWithInt = requires(T t, int i) { + { t.get() == i } -> std::convertible_to; +}; + +// Spaceship + +template +concept BooleanTestableImpl = std::convertible_to; + +template +concept BooleanTestable = BooleanTestableImpl && requires(T&& t) { + { !std::forward(t) } -> BooleanTestableImpl; +}; + +template +concept HasSpaceshipOperatorWithInt = requires(T t, int i) { + { t < i } -> BooleanTestable; + { i < t } -> BooleanTestable; +}; + +#endif // TEST_STD_FUNCTIONOBJECTS_REFWRAP_HELPER_CONCEPTS_H diff --git a/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/helper_types.h b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/helper_types.h new file mode 100644 index 000000000000..cf5e568dbf93 --- /dev/null +++ b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.comparissons/helper_types.h @@ -0,0 +1,30 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef TEST_STD_FUNCTIONOBJECTS_REFWRAP_HELPER_TYPES_H +#define TEST_STD_FUNCTIONOBJECTS_REFWRAP_HELPER_TYPES_H + +#include + +struct EqualityComparable { + constexpr EqualityComparable(int value) : value_{value} {}; + + friend constexpr bool operator==(const EqualityComparable&, const EqualityComparable&) noexcept = default; + + int value_; +}; + +static_assert(std::equality_comparable); +static_assert(EqualityComparable{94} == EqualityComparable{94}); +static_assert(EqualityComparable{94} != EqualityComparable{82}); + +struct NonComparable {}; + +static_assert(!std::three_way_comparable); + +#endif // TEST_STD_FUNCTIONOBJECTS_REFWRAP_HELPER_TYPES_H diff --git a/libcxx/utils/generate_feature_test_macro_components.py b/libcxx/utils/generate_feature_test_macro_components.py index 29c8ceba0c7e..d0171c84acbc 100755 --- a/libcxx/utils/generate_feature_test_macro_components.py +++ b/libcxx/utils/generate_feature_test_macro_components.py @@ -1044,7 +1044,6 @@ feature_test_macros = [ "name": "__cpp_lib_reference_wrapper", "values": {"c++26": 202403}, # P2944R3: Comparisons for reference_wrapper "headers": ["functional"], - "unimplemented": True, }, { "name": "__cpp_lib_remove_cvref", -- GitLab From 2cbfe4a823020b2efe53d32ad7eccbc5a037943f Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 9 May 2024 10:59:25 +0100 Subject: [PATCH 121/328] [AMDGPU] Remove duplicate -mtriple options in tests (#91576) --- .../GlobalISel/llvm.amdgcn.workitem.id.ll | 6 +++--- llvm/test/CodeGen/AMDGPU/combine_vloads.ll | 2 +- llvm/test/CodeGen/AMDGPU/dead_bundle.mir | 2 +- llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll | 2 +- llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll | 18 +++++++++--------- .../CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/load-constant-i1.ll | 2 +- llvm/test/CodeGen/AMDGPU/load-global-i1.ll | 2 +- llvm/test/CodeGen/AMDGPU/load-local-i1.ll | 2 +- llvm/test/CodeGen/AMDGPU/load-local-i8.ll | 2 +- .../AMDGPU/nullptr-long-address-spaces.ll | 2 +- llvm/test/CodeGen/AMDGPU/nullptr.ll | 2 +- llvm/test/CodeGen/AMDGPU/setcc.ll | 2 +- llvm/test/CodeGen/AMDGPU/sext-in-reg.ll | 2 +- llvm/test/CodeGen/AMDGPU/shl.ll | 2 +- llvm/test/CodeGen/AMDGPU/sra.ll | 2 +- llvm/test/CodeGen/AMDGPU/store-global.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/store-local.ll | 4 ++-- .../trunc-vector-store-assertion-failure.ll | 2 +- llvm/test/CodeGen/AMDGPU/unknown-processor.ll | 2 +- llvm/test/CodeGen/AMDGPU/unsupported-calls.ll | 2 +- llvm/test/CodeGen/AMDGPU/vector-alloca.ll | 2 +- .../CodeGen/AMDGPU/wrong-transalu-pos-fix.ll | 2 +- 23 files changed, 36 insertions(+), 36 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll index 2e62d13f1e69..09882c446fc0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll @@ -4,9 +4,9 @@ ; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -mattr=+flat-for-global -verify-machineinstrs | FileCheck --check-prefixes=ALL,MESA,UNPACKED %s ; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=+flat-for-global -mcpu=hawaii -verify-machineinstrs | FileCheck -check-prefixes=ALL,MESA3D,UNPACKED %s ; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=ALL,MESA3D,UNPACKED %s -; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -verify-machineinstrs | FileCheck -check-prefixes=ALL,PACKED-TID %s -; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=ALL,PACKED-TID %s -; RUN: sed 's/CODE_OBJECT_VERSION/600/g' %s | llc -global-isel -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=6 -mcpu=gfx11-generic -verify-machineinstrs -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=ALL,PACKED-TID %s +; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -verify-machineinstrs | FileCheck -check-prefixes=ALL,PACKED-TID %s +; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=ALL,PACKED-TID %s +; RUN: sed 's/CODE_OBJECT_VERSION/600/g' %s | llc -global-isel -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=6 -mcpu=gfx11-generic -verify-machineinstrs -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=ALL,PACKED-TID %s declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.y() #0 diff --git a/llvm/test/CodeGen/AMDGPU/combine_vloads.ll b/llvm/test/CodeGen/AMDGPU/combine_vloads.ll index 10b7d62e275d..42a9b80b134c 100644 --- a/llvm/test/CodeGen/AMDGPU/combine_vloads.ll +++ b/llvm/test/CodeGen/AMDGPU/combine_vloads.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=EG %s +; RUN: llc -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=EG %s ; ; kernel void combine_vloads(global char8 addrspace(5)* src, global char8 addrspace(5)* result) { diff --git a/llvm/test/CodeGen/AMDGPU/dead_bundle.mir b/llvm/test/CodeGen/AMDGPU/dead_bundle.mir index dd9d6a1c788e..af656ea1c719 100644 --- a/llvm/test/CodeGen/AMDGPU/dead_bundle.mir +++ b/llvm/test/CodeGen/AMDGPU/dead_bundle.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn--amdpal -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs=1 -start-before=greedy,0 -stop-after=virtregrewriter,0 -stress-regalloc=5 %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -verify-machineinstrs=1 -start-before=greedy,0 -stop-after=virtregrewriter,0 -stress-regalloc=5 %s -o - | FileCheck %s # This test checks that dead bundles are handled correctly. --- diff --git a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll index 7c5bdd691fc4..1c093bf31ea7 100644 --- a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll @@ -1,6 +1,6 @@ ; RUN: not llc -mtriple=amdgcn-- -mcpu=tahiti -mattr=+promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck %s ; RUN: not llc -mtriple=amdgcn-- -mcpu=tahiti -mattr=-promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck %s -; RUN: not llc -mtriple=r600 -mtriple=r600-- -mcpu=cypress < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=r600-- -mcpu=cypress < %s 2>&1 | FileCheck %s target datalayout = "A5" ; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll index 1633d21c41d5..e4ffedd686ac 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll @@ -7,17 +7,17 @@ ; RUN: llc < %s -mtriple=amdgcn -mcpu=carrizo -mattr=+xnack -verify-machineinstrs | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s ; RUN: llc < %s -mtriple=amdgcn -mcpu=stoney -mattr=+xnack -verify-machineinstrs | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s -; RUN: llc < %s -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck -check-prefixes=GCN %s -; RUN: llc < %s -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-NOXNACK,HSA-VI-NOXNACK,GCN %s -; RUN: llc < %s -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=+xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-XNACK,HSA-VI-XNACK,GCN %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck -check-prefixes=GCN %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-NOXNACK,HSA-VI-NOXNACK,GCN %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=+xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-XNACK,HSA-VI-XNACK,GCN %s -; RUN: llc < %s -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=+architected-flat-scratch -verify-machineinstrs | FileCheck -check-prefixes=GCN %s -; RUN: llc < %s -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=+architected-flat-scratch,-xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-NOXNACK,GFX9-ARCH-FLAT,GCN %s -; RUN: llc < %s -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=+architected-flat-scratch,+xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-XNACK,GFX9-ARCH-FLAT,GCN %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=+architected-flat-scratch -verify-machineinstrs | FileCheck -check-prefixes=GCN %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=+architected-flat-scratch,-xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-NOXNACK,GFX9-ARCH-FLAT,GCN %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=+architected-flat-scratch,+xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-XNACK,GFX9-ARCH-FLAT,GCN %s -; RUN: llc < %s -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+architected-flat-scratch -verify-machineinstrs | FileCheck -check-prefixes=GCN %s -; RUN: llc < %s -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+architected-flat-scratch,-xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-NOXNACK,GFX10-ARCH-FLAT,GCN %s -; RUN: llc < %s -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+architected-flat-scratch,+xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-XNACK,GFX10-ARCH-FLAT,GCN %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+architected-flat-scratch -verify-machineinstrs | FileCheck -check-prefixes=GCN %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+architected-flat-scratch,-xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-NOXNACK,GFX10-ARCH-FLAT,GCN %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+architected-flat-scratch,+xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-XNACK,GFX10-ARCH-FLAT,GCN %s ; GCN-LABEL: {{^}}no_vcc_no_flat: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll index a1835ea176d5..47f988fc17d2 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll @@ -2,8 +2,8 @@ ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=ALL,MESA,UNPACKED %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,MESA3D,UNPACKED %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,MESA3D,UNPACKED %s -; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,PACKED-TID %s -; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=ALL,PACKED-TID %s +; RUN: llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,PACKED-TID %s +; RUN: llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=ALL,PACKED-TID %s declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.y() #0 diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll index 88b18232ef9c..502cd14284e1 100644 --- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll +++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6 %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s -; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=EG %s +; RUN: llc -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=EG %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s define amdgpu_kernel void @constant_load_i1(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 { diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i1.ll b/llvm/test/CodeGen/AMDGPU/load-global-i1.ll index 5ab1f3d972b0..dac928d70c65 100644 --- a/llvm/test/CodeGen/AMDGPU/load-global-i1.ll +++ b/llvm/test/CodeGen/AMDGPU/load-global-i1.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s -; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}global_load_i1: ; GCN: buffer_load_ubyte diff --git a/llvm/test/CodeGen/AMDGPU/load-local-i1.ll b/llvm/test/CodeGen/AMDGPU/load-local-i1.ll index ea858fb67443..578170941efa 100644 --- a/llvm/test/CodeGen/AMDGPU/load-local-i1.ll +++ b/llvm/test/CodeGen/AMDGPU/load-local-i1.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s -; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefixes=EG,FUNC %s +; RUN: llc -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefixes=EG,FUNC %s ; FUNC-LABEL: {{^}}local_load_i1: ; SICIVI: s_mov_b32 m0 diff --git a/llvm/test/CodeGen/AMDGPU/load-local-i8.ll b/llvm/test/CodeGen/AMDGPU/load-local-i8.ll index 9b1b32a65f23..a2e55ce06b52 100644 --- a/llvm/test/CodeGen/AMDGPU/load-local-i8.ll +++ b/llvm/test/CodeGen/AMDGPU/load-local-i8.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,SI,SICIVI,FUNC %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,VI,SICIVI,FUNC %s ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GFX9,FUNC %s -; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s ; Testing for ds_read/write_b128 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=+enable-ds128 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=CIVI,FUNC %s diff --git a/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll b/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll index 98c869f23d47..6556f07c7350 100644 --- a/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll +++ b/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll @@ -1,6 +1,6 @@ ; XFAIL: * ; RUN: llc < %s -mtriple=amdgcn-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,GCN %s -; RUN: llc < %s -mtriple=r600 -mtriple=r600-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,R600 %s +; RUN: llc < %s -mtriple=r600-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,R600 %s ; This is a temporary xfail, as the assembly printer is broken when dealing with ; lowerConstant() trying to return a value of size greater than 8 bytes. diff --git a/llvm/test/CodeGen/AMDGPU/nullptr.ll b/llvm/test/CodeGen/AMDGPU/nullptr.ll index b7a15f97e103..5a736aabd4ee 100644 --- a/llvm/test/CodeGen/AMDGPU/nullptr.ll +++ b/llvm/test/CodeGen/AMDGPU/nullptr.ll @@ -1,5 +1,5 @@ ;RUN: llc < %s -mtriple=amdgcn-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,GCN %s -;RUN: llc < %s -mtriple=r600 -mtriple=r600-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,R600 %s +;RUN: llc < %s -mtriple=r600-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,R600 %s %struct.S = type { ptr addrspace(5), ptr addrspace(1), ptr addrspace(4), ptr addrspace(3), ptr, ptr addrspace(2)} diff --git a/llvm/test/CodeGen/AMDGPU/setcc.ll b/llvm/test/CodeGen/AMDGPU/setcc.ll index 6ab49382b904..c00cd763992d 100644 --- a/llvm/test/CodeGen/AMDGPU/setcc.ll +++ b/llvm/test/CodeGen/AMDGPU/setcc.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=FUNC %s -; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=R600 -check-prefix=FUNC %s +; RUN: llc -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=R600 -check-prefix=FUNC %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll b/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll index 38672da3c647..4e3dccb975fe 100644 --- a/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll +++ b/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll @@ -1,7 +1,7 @@ ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,SI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX89,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX9,GFX89,FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mtriple=r600-- -mcpu=cypress < %s | FileCheck -enable-var-scope --check-prefixes=EG,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600-- -mcpu=cypress < %s | FileCheck -enable-var-scope --check-prefixes=EG,FUNC %s ; FIXME: i16 promotion pass ruins the scalar cases when legal. ; FIXME: r600 fails verifier diff --git a/llvm/test/CodeGen/AMDGPU/shl.ll b/llvm/test/CodeGen/AMDGPU/shl.ll index c440392153ad..b1a82daa8e7d 100644 --- a/llvm/test/CodeGen/AMDGPU/shl.ll +++ b/llvm/test/CodeGen/AMDGPU/shl.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefixes=SI ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=VI -; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs | FileCheck %s --check-prefixes=EG +; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=r600-- -mcpu=redwood -verify-machineinstrs | FileCheck %s --check-prefixes=EG declare i32 @llvm.amdgcn.workitem.id.x() #0 diff --git a/llvm/test/CodeGen/AMDGPU/sra.ll b/llvm/test/CodeGen/AMDGPU/sra.ll index ae0221b8b32b..b8cf69237206 100644 --- a/llvm/test/CodeGen/AMDGPU/sra.ll +++ b/llvm/test/CodeGen/AMDGPU/sra.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=VI -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s -check-prefixes=EG +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s -check-prefixes=EG declare i32 @llvm.amdgcn.workitem.id.x() #0 diff --git a/llvm/test/CodeGen/AMDGPU/store-global.ll b/llvm/test/CodeGen/AMDGPU/store-global.ll index f068b1481aa9..1ff9b117237f 100644 --- a/llvm/test/CodeGen/AMDGPU/store-global.ll +++ b/llvm/test/CodeGen/AMDGPU/store-global.ll @@ -1,8 +1,8 @@ ; RUN: llc -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=VI -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=FUNC %s -; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s +; RUN: llc -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -mtriple=r600-- -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}store_i1: ; EG: MEM_RAT MSKOR diff --git a/llvm/test/CodeGen/AMDGPU/store-local.ll b/llvm/test/CodeGen/AMDGPU/store-local.ll index 479f881cd40c..76e2d4366e3e 100644 --- a/llvm/test/CodeGen/AMDGPU/store-local.ll +++ b/llvm/test/CodeGen/AMDGPU/store-local.ll @@ -1,8 +1,8 @@ ; RUN: llc -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,VI,FUNC %s ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s -; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s -; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=cayman < %s | FileCheck -check-prefixes=CM,FUNC %s +; RUN: llc -mtriple=r600-- -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s +; RUN: llc -mtriple=r600-- -mcpu=cayman < %s | FileCheck -check-prefixes=CM,FUNC %s ; FUNC-LABEL: {{^}}store_local_i1: ; SICIVI: s_mov_b32 m0 diff --git a/llvm/test/CodeGen/AMDGPU/trunc-vector-store-assertion-failure.ll b/llvm/test/CodeGen/AMDGPU/trunc-vector-store-assertion-failure.ll index 8ccd3b9dd124..8de059d1d7b8 100644 --- a/llvm/test/CodeGen/AMDGPU/trunc-vector-store-assertion-failure.ll +++ b/llvm/test/CodeGen/AMDGPU/trunc-vector-store-assertion-failure.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=r600 -mtriple=r600-- -mcpu=redwood | FileCheck %s +; RUN: llc < %s -mtriple=r600-- -mcpu=redwood | FileCheck %s ; This tests for a bug in the SelectionDAG where custom lowered truncated ; vector stores at the end of a basic block were not being added to the diff --git a/llvm/test/CodeGen/AMDGPU/unknown-processor.ll b/llvm/test/CodeGen/AMDGPU/unknown-processor.ll index f1f1c92bcbed..9cfba8b2e5c0 100644 --- a/llvm/test/CodeGen/AMDGPU/unknown-processor.ll +++ b/llvm/test/CodeGen/AMDGPU/unknown-processor.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=amdgcn-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s -; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=R600 %s +; RUN: llc -mtriple=r600-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=R600 %s target datalayout = "A5" ; Should not crash when the processor is not recognized and the diff --git a/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll b/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll index 694f444b7747..fc00937e6c8a 100644 --- a/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll +++ b/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll @@ -1,6 +1,6 @@ ; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s ; RUN: not llc -mtriple=amdgcn--amdpal -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s -; RUN: not llc -mtriple=r600 -mtriple=r600-- -mcpu=cypress -tailcallopt < %s 2>&1 | FileCheck -check-prefix=R600 %s +; RUN: not llc -mtriple=r600-- -mcpu=cypress -tailcallopt < %s 2>&1 | FileCheck -check-prefix=R600 %s declare i32 @external_function(i32) nounwind diff --git a/llvm/test/CodeGen/AMDGPU/vector-alloca.ll b/llvm/test/CodeGen/AMDGPU/vector-alloca.ll index 5ef794b64c0b..2c87680284e2 100644 --- a/llvm/test/CodeGen/AMDGPU/vector-alloca.ll +++ b/llvm/test/CodeGen/AMDGPU/vector-alloca.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=amdgcn-- -mcpu=verde -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s -; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s +; RUN: llc -mtriple=r600-- -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s ; RUN: opt -S -mtriple=amdgcn-- -passes='amdgpu-promote-alloca,sroa,instcombine' < %s | FileCheck -check-prefix=OPT %s target datalayout = "A5" diff --git a/llvm/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll b/llvm/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll index bdfa89d9f304..6db7fe80c3cc 100644 --- a/llvm/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll +++ b/llvm/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=r600 -mcpu=redwood -mtriple=r600-- < %s | FileCheck %s +; RUN: llc -mtriple=r600-- -mcpu=redwood < %s | FileCheck %s ; We want all MULLO_INT inst to be last in their instruction group ;CHECK: {{^}}fill3d: -- GitLab From 643c38333fc1b1e7e705e6e1035c595bbd95bc74 Mon Sep 17 00:00:00 2001 From: Lukacma Date: Thu, 9 May 2024 11:10:02 +0100 Subject: [PATCH 122/328] [AArch64] Remove EXT instr before UZP when extracting elements from vector (#91328) Assembly generated for getting odd/even elements from vector contained extra EXT instruction. This was due to way llvm constructs DAGs when vector_shuffling from larger type to smaller. This patch optimises DAG in these situations, allowing for correct assembly to be emitted. --- .../Target/AArch64/AArch64ISelLowering.cpp | 24 ++++++++++ llvm/test/CodeGen/AArch64/aarch64-vuzp.ll | 10 ++-- ...complex-deinterleaving-f16-add-scalable.ll | 18 +++---- ...complex-deinterleaving-f16-mul-scalable.ll | 29 ++++++----- .../AArch64/fixed-vector-deinterleave.ll | 22 +++------ llvm/test/CodeGen/AArch64/neon-perm.ll | 7 +-- .../AArch64/sve-vector-deinterleave.ll | 48 +++++++++---------- 7 files changed, 87 insertions(+), 71 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index c1ca78af5cda..7344387ffe55 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -21448,6 +21448,29 @@ static SDValue performUzpCombine(SDNode *N, SelectionDAG &DAG, SDValue Op1 = N->getOperand(1); EVT ResVT = N->getValueType(0); + // uzp(extract_lo(x), extract_hi(x)) -> extract_lo(uzp x, x) + if (Op0.getOpcode() == ISD::EXTRACT_SUBVECTOR && + Op1.getOpcode() == ISD::EXTRACT_SUBVECTOR && + Op0.getOperand(0) == Op1.getOperand(0)) { + + SDValue SourceVec = Op0.getOperand(0); + uint64_t ExtIdx0 = Op0.getConstantOperandVal(1); + uint64_t ExtIdx1 = Op1.getConstantOperandVal(1); + uint64_t NumElements = SourceVec.getValueType().getVectorMinNumElements(); + if (ExtIdx0 == 0 && ExtIdx1 == NumElements / 2) { + EVT OpVT = Op0.getOperand(1).getValueType(); + EVT WidenedResVT = ResVT.getDoubleNumVectorElementsVT(*DAG.getContext()); + SDValue Uzp = DAG.getNode(N->getOpcode(), DL, WidenedResVT, SourceVec, + DAG.getUNDEF(WidenedResVT)); + return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResVT, Uzp, + DAG.getConstant(0, DL, OpVT)); + } + } + + // Following optimizations only work with uzp1. + if (N->getOpcode() == AArch64ISD::UZP2) + return SDValue(); + // uzp1(x, undef) -> concat(truncate(x), undef) if (Op1.getOpcode() == ISD::UNDEF) { EVT BCVT = MVT::Other, HalfVT = MVT::Other; @@ -24665,6 +24688,7 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N, case AArch64ISD::UUNPKHI: return performUnpackCombine(N, DAG, Subtarget); case AArch64ISD::UZP1: + case AArch64ISD::UZP2: return performUzpCombine(N, DAG, Subtarget); case AArch64ISD::SETCC_MERGE_ZERO: return performSetccMergeZeroCombine(N, DCI); diff --git a/llvm/test/CodeGen/AArch64/aarch64-vuzp.ll b/llvm/test/CodeGen/AArch64/aarch64-vuzp.ll index ba1ad9ba989c..1debf0256467 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-vuzp.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-vuzp.ll @@ -3,18 +3,18 @@ declare <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8>, <16 x i8>) ; CHECK-LABEL: fun1: -; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b define i32 @fun1() { entry: %vtbl1.i.1 = tail call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> , <16 x i8> undef) - %vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> - %scevgep = getelementptr <8 x i8>, ptr undef, i64 1 - store <8 x i8> %vuzp.i212.1, ptr %scevgep, align 1 + %vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> %vtbl1.i.1, <16 x i32> + %scevgep = getelementptr <16 x i8>, ptr undef, i64 1 + store <16 x i8> %vuzp.i212.1, ptr %scevgep, align 1 ret i32 undef } ; CHECK-LABEL: fun2: -; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b define i32 @fun2() { entry: %vtbl1.i.1 = tail call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> , <16 x i8> undef) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll index dae8d9f89e99..c2fc959d8e10 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll @@ -7,18 +7,18 @@ target triple = "aarch64" define @complex_add_v4f16( %a, %b) { ; CHECK-LABEL: complex_add_v4f16: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: uunpkhi z2.d, z0.s +; CHECK-NEXT: uzp1 z2.s, z0.s, z0.s +; CHECK-NEXT: uzp2 z0.s, z0.s, z0.s +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: uzp2 z3.s, z1.s, z0.s +; CHECK-NEXT: uzp1 z1.s, z1.s, z0.s +; CHECK-NEXT: uunpklo z2.d, z2.s ; CHECK-NEXT: uunpklo z0.d, z0.s -; CHECK-NEXT: uunpkhi z3.d, z1.s +; CHECK-NEXT: uunpklo z3.d, z3.s ; CHECK-NEXT: uunpklo z1.d, z1.s -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: uzp1 z4.d, z0.d, z2.d -; CHECK-NEXT: uzp2 z0.d, z0.d, z2.d -; CHECK-NEXT: uzp2 z2.d, z1.d, z3.d -; CHECK-NEXT: uzp1 z1.d, z1.d, z3.d ; CHECK-NEXT: fsubr z0.h, p0/m, z0.h, z1.h -; CHECK-NEXT: movprfx z1, z2 -; CHECK-NEXT: fadd z1.h, p0/m, z1.h, z4.h +; CHECK-NEXT: movprfx z1, z3 +; CHECK-NEXT: fadd z1.h, p0/m, z1.h, z2.h ; CHECK-NEXT: zip2 z2.d, z0.d, z1.d ; CHECK-NEXT: zip1 z0.d, z0.d, z1.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z2.s diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll index c09ec616b015..b42d484ea74c 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll @@ -7,23 +7,22 @@ target triple = "aarch64" define @complex_mul_v4f16( %a, %b) { ; CHECK-LABEL: complex_mul_v4f16: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: uunpkhi z2.d, z0.s +; CHECK-NEXT: uzp2 z2.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: uzp2 z3.s, z1.s, z0.s ; CHECK-NEXT: uunpklo z0.d, z0.s -; CHECK-NEXT: uunpkhi z3.d, z1.s +; CHECK-NEXT: uunpklo z2.d, z2.s +; CHECK-NEXT: uunpklo z3.d, z3.s +; CHECK-NEXT: uzp1 z1.s, z1.s, z0.s ; CHECK-NEXT: uunpklo z1.d, z1.s -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: uzp2 z4.d, z0.d, z2.d -; CHECK-NEXT: uzp1 z0.d, z0.d, z2.d -; CHECK-NEXT: uzp2 z2.d, z1.d, z3.d -; CHECK-NEXT: uzp1 z1.d, z1.d, z3.d -; CHECK-NEXT: movprfx z5, z2 -; CHECK-NEXT: fmul z5.h, p0/m, z5.h, z0.h -; CHECK-NEXT: fmul z2.h, p0/m, z2.h, z4.h -; CHECK-NEXT: movprfx z3, z5 -; CHECK-NEXT: fmla z3.h, p0/m, z1.h, z4.h -; CHECK-NEXT: fnmsb z0.h, p0/m, z1.h, z2.h -; CHECK-NEXT: zip2 z1.d, z0.d, z3.d -; CHECK-NEXT: zip1 z0.d, z0.d, z3.d +; CHECK-NEXT: movprfx z4, z3 +; CHECK-NEXT: fmul z4.h, p0/m, z4.h, z0.h +; CHECK-NEXT: fmul z3.h, p0/m, z3.h, z2.h +; CHECK-NEXT: fmad z2.h, p0/m, z1.h, z4.h +; CHECK-NEXT: fnmsb z0.h, p0/m, z1.h, z3.h +; CHECK-NEXT: zip2 z1.d, z0.d, z2.d +; CHECK-NEXT: zip1 z0.d, z0.d, z2.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll b/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll index c58db8290c87..5bd680ed4893 100644 --- a/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll +++ b/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll @@ -30,21 +30,13 @@ define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec } define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec) { -; CHECK-SD-LABEL: vector_deinterleave_v4f16_v8f16: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-SD-NEXT: uzp1 v2.4h, v0.4h, v1.4h -; CHECK-SD-NEXT: uzp2 v1.4h, v0.4h, v1.4h -; CHECK-SD-NEXT: fmov d0, d2 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: vector_deinterleave_v4f16_v8f16: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: uzp1 v2.8h, v0.8h, v0.8h -; CHECK-GI-NEXT: uzp2 v1.8h, v0.8h, v0.8h -; CHECK-GI-NEXT: // kill: def $d1 killed $d1 killed $q1 -; CHECK-GI-NEXT: fmov d0, d2 -; CHECK-GI-NEXT: ret +; CHECK-LABEL: vector_deinterleave_v4f16_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: uzp1 v2.8h, v0.8h, v0.8h +; CHECK-NEXT: uzp2 v1.8h, v0.8h, v0.8h +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1 +; CHECK-NEXT: fmov d0, d2 +; CHECK-NEXT: ret %retval = call {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half> %vec) ret {<4 x half>, <4 x half>} %retval } diff --git a/llvm/test/CodeGen/AArch64/neon-perm.ll b/llvm/test/CodeGen/AArch64/neon-perm.ll index 037451eb803c..15763543113e 100644 --- a/llvm/test/CodeGen/AArch64/neon-perm.ll +++ b/llvm/test/CodeGen/AArch64/neon-perm.ll @@ -4092,9 +4092,9 @@ entry: define %struct.uint8x8x2_t @test_uzp(<16 x i8> %y) { ; CHECK-SD-LABEL: test_uzp: ; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-SD-NEXT: uzp1 v2.8b, v0.8b, v1.8b -; CHECK-SD-NEXT: uzp2 v1.8b, v0.8b, v1.8b +; CHECK-SD-NEXT: xtn v2.8b, v0.8h +; CHECK-SD-NEXT: uzp2 v1.16b, v0.16b, v0.16b +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1 ; CHECK-SD-NEXT: fmov d0, d2 ; CHECK-SD-NEXT: ret ; @@ -4106,6 +4106,7 @@ define %struct.uint8x8x2_t @test_uzp(<16 x i8> %y) { ; CHECK-GI-NEXT: fmov d0, d2 ; CHECK-GI-NEXT: ret + %vuzp.i = shufflevector <16 x i8> %y, <16 x i8> undef, <8 x i32> %vuzp1.i = shufflevector <16 x i8> %y, <16 x i8> undef, <8 x i32> %.fca.0.0.insert = insertvalue %struct.uint8x8x2_t undef, <8 x i8> %vuzp.i, 0, 0 diff --git a/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll b/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll index 478f4a689d3c..fd1365d56fee 100644 --- a/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll +++ b/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll @@ -4,10 +4,10 @@ define {, } @vector_deinterleave_nxv2f16_nxv4f16( %vec) { ; CHECK-LABEL: vector_deinterleave_nxv2f16_nxv4f16: ; CHECK: // %bb.0: -; CHECK-NEXT: uunpkhi z1.d, z0.s -; CHECK-NEXT: uunpklo z2.d, z0.s -; CHECK-NEXT: uzp1 z0.d, z2.d, z1.d -; CHECK-NEXT: uzp2 z1.d, z2.d, z1.d +; CHECK-NEXT: uzp1 z1.s, z0.s, z0.s +; CHECK-NEXT: uzp2 z2.s, z0.s, z0.s +; CHECK-NEXT: uunpklo z0.d, z1.s +; CHECK-NEXT: uunpklo z1.d, z2.s ; CHECK-NEXT: ret %retval = call {, } @llvm.vector.deinterleave2.nxv4f16( %vec) ret {, } %retval @@ -16,10 +16,10 @@ define {, } @vector_deinterleave_nxv2f16_n define {, } @vector_deinterleave_nxv4f16_nxv8f16( %vec) { ; CHECK-LABEL: vector_deinterleave_nxv4f16_nxv8f16: ; CHECK: // %bb.0: -; CHECK-NEXT: uunpkhi z1.s, z0.h -; CHECK-NEXT: uunpklo z2.s, z0.h -; CHECK-NEXT: uzp1 z0.s, z2.s, z1.s -; CHECK-NEXT: uzp2 z1.s, z2.s, z1.s +; CHECK-NEXT: uzp1 z1.h, z0.h, z0.h +; CHECK-NEXT: uzp2 z2.h, z0.h, z0.h +; CHECK-NEXT: uunpklo z0.s, z1.h +; CHECK-NEXT: uunpklo z1.s, z2.h ; CHECK-NEXT: ret %retval = call {, } @llvm.vector.deinterleave2.nxv8f16( %vec) ret {, } %retval @@ -39,10 +39,10 @@ define {, } @vector_deinterleave_nxv8f16_n define {, } @vector_deinterleave_nxv2f32_nxv4f32( %vec) { ; CHECK-LABEL: vector_deinterleave_nxv2f32_nxv4f32: ; CHECK: // %bb.0: -; CHECK-NEXT: uunpkhi z1.d, z0.s -; CHECK-NEXT: uunpklo z2.d, z0.s -; CHECK-NEXT: uzp1 z0.d, z2.d, z1.d -; CHECK-NEXT: uzp2 z1.d, z2.d, z1.d +; CHECK-NEXT: uzp1 z1.s, z0.s, z0.s +; CHECK-NEXT: uzp2 z2.s, z0.s, z0.s +; CHECK-NEXT: uunpklo z0.d, z1.s +; CHECK-NEXT: uunpklo z1.d, z2.s ; CHECK-NEXT: ret %retval = call {, } @llvm.vector.deinterleave2.nxv4f32( %vec) ret {, } %retval @@ -131,10 +131,10 @@ define {, } @vector_deinterleave_nxv16i1_nxv define {, } @vector_deinterleave_nxv8i1_nxv16i1( %vec) { ; CHECK-LABEL: vector_deinterleave_nxv8i1_nxv16i1: ; CHECK: // %bb.0: -; CHECK-NEXT: punpkhi p1.h, p0.b -; CHECK-NEXT: punpklo p2.h, p0.b -; CHECK-NEXT: uzp1 p0.h, p2.h, p1.h -; CHECK-NEXT: uzp2 p1.h, p2.h, p1.h +; CHECK-NEXT: uzp1 p1.b, p0.b, p0.b +; CHECK-NEXT: uzp2 p2.b, p0.b, p0.b +; CHECK-NEXT: punpklo p0.h, p1.b +; CHECK-NEXT: punpklo p1.h, p2.b ; CHECK-NEXT: ret %retval = call {, } @llvm.vector.deinterleave2.nxv16i1( %vec) ret {, } %retval @@ -143,10 +143,10 @@ define {, } @vector_deinterleave_nxv8i1_nxv16i define {, } @vector_deinterleave_nxv4i1_nxv8i1( %vec) { ; CHECK-LABEL: vector_deinterleave_nxv4i1_nxv8i1: ; CHECK: // %bb.0: -; CHECK-NEXT: punpkhi p1.h, p0.b -; CHECK-NEXT: punpklo p2.h, p0.b -; CHECK-NEXT: uzp1 p0.s, p2.s, p1.s -; CHECK-NEXT: uzp2 p1.s, p2.s, p1.s +; CHECK-NEXT: uzp1 p1.h, p0.h, p0.h +; CHECK-NEXT: uzp2 p2.h, p0.h, p0.h +; CHECK-NEXT: punpklo p0.h, p1.b +; CHECK-NEXT: punpklo p1.h, p2.b ; CHECK-NEXT: ret %retval = call {, } @llvm.vector.deinterleave2.nxv8i1( %vec) ret {, } %retval @@ -155,10 +155,10 @@ define {, } @vector_deinterleave_nxv4i1_nxv8i1 define {, } @vector_deinterleave_nxv2i1_nxv4i1( %vec) { ; CHECK-LABEL: vector_deinterleave_nxv2i1_nxv4i1: ; CHECK: // %bb.0: -; CHECK-NEXT: punpkhi p1.h, p0.b -; CHECK-NEXT: punpklo p2.h, p0.b -; CHECK-NEXT: uzp1 p0.d, p2.d, p1.d -; CHECK-NEXT: uzp2 p1.d, p2.d, p1.d +; CHECK-NEXT: uzp1 p1.s, p0.s, p0.s +; CHECK-NEXT: uzp2 p2.s, p0.s, p0.s +; CHECK-NEXT: punpklo p0.h, p1.b +; CHECK-NEXT: punpklo p1.h, p2.b ; CHECK-NEXT: ret %retval = call {, } @llvm.vector.deinterleave2.nxv4i1( %vec) ret {, } %retval -- GitLab From 1494d8849fa2aef575dabd431b0060639f4a57c1 Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 9 May 2024 06:17:01 -0400 Subject: [PATCH 123/328] [AMDGPU] Always Inline preserved analyses (#91198) When replacing all uses, the structural-hash of the IR can change, so keep track of changes using Changed variable and return it to pass manager. --- llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp index b53def912ab6..f55f656ff922 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp @@ -42,7 +42,7 @@ public: void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesAll(); - } + } }; } // End anonymous namespace @@ -89,6 +89,7 @@ recursivelyVisitUsers(GlobalValue &GV, static bool alwaysInlineImpl(Module &M, bool GlobalOpt) { std::vector AliasesToRemove; + bool Changed = false; SmallPtrSet FuncsToAlwaysInline; SmallPtrSet FuncsToNoInline; Triple TT(M.getTargetTriple()); @@ -98,6 +99,7 @@ static bool alwaysInlineImpl(Module &M, bool GlobalOpt) { if (TT.getArch() == Triple::amdgcn && A.getLinkage() != GlobalValue::InternalLinkage) continue; + Changed = true; A.replaceAllUsesWith(F); AliasesToRemove.push_back(&A); } @@ -153,7 +155,7 @@ static bool alwaysInlineImpl(Module &M, bool GlobalOpt) { for (Function *F : FuncsToNoInline) F->addFnAttr(Attribute::NoInline); - return !FuncsToAlwaysInline.empty() || !FuncsToNoInline.empty(); + return Changed || !FuncsToAlwaysInline.empty() || !FuncsToNoInline.empty(); } bool AMDGPUAlwaysInline::runOnModule(Module &M) { @@ -166,6 +168,6 @@ ModulePass *llvm::createAMDGPUAlwaysInlinePass(bool GlobalOpt) { PreservedAnalyses AMDGPUAlwaysInlinePass::run(Module &M, ModuleAnalysisManager &AM) { - alwaysInlineImpl(M, GlobalOpt); - return PreservedAnalyses::all(); + const bool Changed = alwaysInlineImpl(M, GlobalOpt); + return Changed ? PreservedAnalyses::none() : PreservedAnalyses::all(); } -- GitLab From 6eb9e214b3cb06fc31f2547275e746761c3e41de Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 9 May 2024 11:37:28 +0100 Subject: [PATCH 124/328] RFC: [AMDGPU] Check subtarget features for consistency (#86957) Implement GCNSubtarget::checkSubtargetFeatures as a canonical place to check subtarget features for consistency and diagnose any inconsistencies. To start with, the implementation just checks that either wavefrontsize32 or wavefrontsize64 is selected. checkSubtargetFeatures is called at the start of instruction selection. This is pretty arbitrary. It is just a convenient point at which we have access to the subtarget that we're going to use for codegenning a particular function. --- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 1 + llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 1 + llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 10 ++++++++++ llvm/lib/Target/AMDGPU/GCNSubtarget.h | 4 ++++ llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll | 10 ++++++++++ .../AMDGPU/remove-incompatible-wave32-feature.ll | 8 ++++---- llvm/test/CodeGen/AMDGPU/unknown-processor.ll | 2 +- 7 files changed, 31 insertions(+), 5 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index bba7682cd7a0..c11c7a57e059 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -132,6 +132,7 @@ bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { } #endif Subtarget = &MF.getSubtarget(); + Subtarget->checkSubtargetFeatures(MF.getFunction()); Mode = SIModeRegisterDefaults(MF.getFunction(), *Subtarget); return SelectionDAGISel::runOnMachineFunction(MF); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index e13c13913d4e..b48a09489653 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -63,6 +63,7 @@ void AMDGPUInstructionSelector::setupMF(MachineFunction &MF, GISelKnownBits *KB, BlockFrequencyInfo *BFI) { MRI = &MF.getRegInfo(); Subtarget = &MF.getSubtarget(); + Subtarget->checkSubtargetFeatures(MF.getFunction()); InstructionSelector::setupMF(MF, KB, CoverageInfo, PSI, BFI); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index 36e453f04426..9cfe81e5288e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -25,6 +25,7 @@ #include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/TargetFrameLowering.h" +#include "llvm/IR/DiagnosticInfo.h" #include "llvm/IR/IntrinsicsAMDGPU.h" #include "llvm/IR/IntrinsicsR600.h" #include "llvm/IR/MDBuilder.h" @@ -165,6 +166,15 @@ GCNSubtarget::initializeSubtargetDependencies(const Triple &TT, return *this; } +void GCNSubtarget::checkSubtargetFeatures(const Function &F) const { + LLVMContext &Ctx = F.getContext(); + if (hasFeature(AMDGPU::FeatureWavefrontSize32) == + hasFeature(AMDGPU::FeatureWavefrontSize64)) { + Ctx.diagnose(DiagnosticInfoUnsupported( + F, "must specify exactly one of wavefrontsize32 and wavefrontsize64")); + } +} + AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT) : TargetTriple(TT) {} bool AMDGPUSubtarget::useRealTrue16Insts() const { diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index be337e0b2192..b7548671f2c5 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -250,6 +250,10 @@ public: GCNSubtarget &initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS); + /// Diagnose inconsistent subtarget features before attempting to codegen + /// function \p F. + void checkSubtargetFeatures(const Function &F) const; + const SIInstrInfo *getInstrInfo() const override { return &InstrInfo; } diff --git a/llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll b/llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll new file mode 100644 index 000000000000..c24693981104 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll @@ -0,0 +1,10 @@ +; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,-wavefrontsize64 < %s 2>&1 | FileCheck %s -check-prefix=ERR -implicit-check-not=error: +; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,-wavefrontsize64 < %s 2>&1 | FileCheck %s -check-prefix=ERR -implicit-check-not=error: +; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+wavefrontsize64 < %s 2>&1 | FileCheck %s -check-prefix=ERR -implicit-check-not=error: +; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+wavefrontsize64 < %s 2>&1 | FileCheck %s -check-prefix=ERR -implicit-check-not=error: + +; ERR: error: {{.*}} in function f void (): must specify exactly one of wavefrontsize32 and wavefrontsize64 + +define void @f() { + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll b/llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll index 8ef1d3ff27e5..406c953a06d9 100644 --- a/llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll +++ b/llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll @@ -8,13 +8,13 @@ ; RUN: FileCheck --check-prefix=WARN-GFX90A %s < %t ; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -mattr=+wavefrontsize64 -verify-machineinstrs < %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 -mattr=+wavefrontsize64 -stop-after=amdgpu-remove-incompatible-functions\ +; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 -mattr=-wavefrontsize32,+wavefrontsize64 -stop-after=amdgpu-remove-incompatible-functions\ ; RUN: -pass-remarks=amdgpu-remove-incompatible-functions < %s 2>%t | FileCheck -check-prefixes=GFX10 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 -mattr=+wavefrontsize64 -verify-machineinstrs < %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -stop-after=amdgpu-remove-incompatible-functions\ +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -stop-after=amdgpu-remove-incompatible-functions\ ; RUN: -pass-remarks=amdgpu-remove-incompatible-functions < %s 2>%t | FileCheck -check-prefixes=GFX11 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machineinstrs < %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s ; WARN-GFX906: removing function 'needs_wavefrontsize32': +wavefrontsize32 is not supported on the current target ; WARN-GFX906-NOT: not supported diff --git a/llvm/test/CodeGen/AMDGPU/unknown-processor.ll b/llvm/test/CodeGen/AMDGPU/unknown-processor.ll index 9cfba8b2e5c0..683ba98e52cf 100644 --- a/llvm/test/CodeGen/AMDGPU/unknown-processor.ll +++ b/llvm/test/CodeGen/AMDGPU/unknown-processor.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s +; RUN: not llc -mtriple=amdgcn-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s ; RUN: llc -mtriple=r600-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=R600 %s target datalayout = "A5" -- GitLab From 58a94b1d0ad8df85bc6b1edb22c74ffb718ca1a1 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Wed, 8 May 2024 06:53:12 -0700 Subject: [PATCH 125/328] [SLP]Fix PR91467: Look through scalar cast, when trying to cast to another type. Need to look through the SExt/ZExt scalars to be gathered, when trying to reduce their width after minbitwidth analysis to prevent permanent attempts to revectorize such gathered instructions. --- .../Transforms/Vectorize/SLPVectorizer.cpp | 10 ++- .../AArch64/gather-with-minbith-user.ll | 9 +-- .../AArch64/user-node-not-in-bitwidths.ll | 7 +- .../SystemZ/minbitwidth-root-trunc.ll | 3 +- .../X86/extended-vectorized-gathered-inst.ll | 65 +++++++++++++++++++ 5 files changed, 77 insertions(+), 17 deletions(-) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/extended-vectorized-gathered-inst.ll diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 98561f9ca044..2e0a39c4b4fd 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -11419,8 +11419,16 @@ Value *BoUpSLP::gather(ArrayRef VL, Value *Root, Type *ScalarTy) { if (Scalar->getType() != Ty) { assert(Scalar->getType()->isIntegerTy() && Ty->isIntegerTy() && "Expected integer types only."); + Value *V = Scalar; + if (auto *CI = dyn_cast(Scalar); + isa_and_nonnull(CI)) { + Value *Op = CI->getOperand(0); + if (auto *IOp = dyn_cast(Op); + !IOp || !(isDeleted(IOp) || getTreeEntry(IOp))) + V = Op; + } Scalar = Builder.CreateIntCast( - Scalar, Ty, !isKnownNonNegative(Scalar, SimplifyQuery(*DL))); + V, Ty, !isKnownNonNegative(Scalar, SimplifyQuery(*DL))); } Vec = Builder.CreateInsertElement(Vec, Scalar, Builder.getInt32(Pos)); diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll index 76bb882171b1..3ebe920d1734 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll @@ -5,14 +5,7 @@ define void @h() { ; CHECK-LABEL: define void @h() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16 -; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 0 to i1 -; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i1> , i1 [[TMP6]], i32 4 -; CHECK-NEXT: [[TMP1:%.*]] = sub <8 x i1> [[TMP0]], zeroinitializer -; CHECK-NEXT: [[TMP2:%.*]] = add <8 x i1> [[TMP0]], zeroinitializer -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP2]], <8 x i32> -; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i1> [[TMP3]], zeroinitializer -; CHECK-NEXT: [[TMP4:%.*]] = zext <8 x i1> [[TMP5]] to <8 x i16> -; CHECK-NEXT: store <8 x i16> [[TMP4]], ptr [[ARRAYIDX2]], align 2 +; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 2 ; CHECK-NEXT: ret void ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll index 2ab6e919c23b..6404cf4a2cd1 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll @@ -5,12 +5,7 @@ define void @h() { ; CHECK-LABEL: define void @h() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16 -; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 0 to i1 -; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i1> , i1 [[TMP0]], i32 4 -; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i1> zeroinitializer, [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i1> zeroinitializer, [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = zext <8 x i1> [[TMP3]] to <8 x i16> -; CHECK-NEXT: store <8 x i16> [[TMP4]], ptr [[ARRAYIDX2]], align 2 +; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 2 ; CHECK-NEXT: ret void ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll index 1bb87bf6205f..3c8e98485ffc 100644 --- a/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll +++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll @@ -4,10 +4,9 @@ define void @test(ptr %a, i8 %0, i16 %b.promoted.i) { ; CHECK-LABEL: define void @test( ; CHECK-SAME: ptr [[A:%.*]], i8 [[TMP0:%.*]], i16 [[B_PROMOTED_I:%.*]]) #[[ATTR0:[0-9]+]] { -; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP0]] to i128 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[B_PROMOTED_I]], i32 0 ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP5:%.*]] = trunc i128 [[TMP2]] to i16 +; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP0]] to i16 ; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i16> poison, i16 [[TMP5]], i32 0 ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i16> [[TMP6]], <4 x i16> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP4]], [[TMP7]] diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extended-vectorized-gathered-inst.ll b/llvm/test/Transforms/SLPVectorizer/X86/extended-vectorized-gathered-inst.ll new file mode 100644 index 000000000000..2d028060f491 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/extended-vectorized-gathered-inst.ll @@ -0,0 +1,65 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux < %s | FileCheck %s + +define void @test(ptr %top) { +; CHECK-LABEL: define void @test( +; CHECK-SAME: ptr [[TOP:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[TOP]], align 1 +; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i8> [[TMP0]], zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i8> [[TMP0]], i32 2 +; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i8 +; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> , i8 [[TMP4]], i32 3 +; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i8> [[TMP1]], [[TMP5]] +; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i8> [[TMP6]], zeroinitializer +; CHECK-NEXT: [[TMP8:%.*]] = lshr <4 x i8> [[TMP7]], +; CHECK-NEXT: br label [[FOR_COND_I:%.*]] +; CHECK: for.cond.i: +; CHECK-NEXT: store <4 x i8> [[TMP8]], ptr null, align 1 +; CHECK-NEXT: br label [[FOR_COND_I]] +; +entry: + %0 = load i8, ptr %top, align 1 + %conv2.i = zext i8 %0 to i32 + %mul.i = mul i32 %conv2.i, 0 + %add.i = or i32 %mul.i, 0 + %arrayidx3.i = getelementptr i8, ptr %top, i64 1 + %1 = load i8, ptr %arrayidx3.i, align 1 + %conv4.i = zext i8 %1 to i32 + %add5.i = or i32 %add.i, 0 + %shr.i = lshr i32 %add5.i, 2 + %conv7.i = trunc i32 %shr.i to i8 + %mul12.i = mul i32 %conv4.i, 0 + %arrayidx14.i = getelementptr i8, ptr %top, i64 2 + %2 = load i8, ptr %arrayidx14.i, align 1 + %conv15.i = zext i8 %2 to i32 + %add16.i = or i32 %mul12.i, 0 + %add17.i = or i32 %add16.i, 0 + %shr18.i = lshr i32 %add17.i, 2 + %conv19.i = trunc i32 %shr18.i to i8 + %mul25.i = mul i32 %conv15.i, 0 + %arrayidx27.i = getelementptr i8, ptr %top, i64 3 + %3 = load i8, ptr %arrayidx27.i, align 1 + %conv28.i = zext i8 %3 to i32 + %add29.i = or i32 %mul25.i, 0 + %add30.i = or i32 %add29.i, 0 + %shr31.i = lshr i32 %add30.i, 2 + %conv32.i = trunc i32 %shr31.i to i8 + %mul38.i = mul i32 %conv28.i, 0 + %add39.i = or i32 %mul38.i, %conv15.i + %add42.i = or i32 %add39.i, 0 + %shr44.i = lshr i32 %add42.i, 2 + %conv45.i = trunc i32 %shr44.i to i8 + br label %for.cond.i + +for.cond.i: + store i8 %conv7.i, ptr null, align 1 + %vals.sroa.5.0.add.ptr.sroa_idx.i = getelementptr i8, ptr null, i64 1 + store i8 %conv19.i, ptr %vals.sroa.5.0.add.ptr.sroa_idx.i, align 1 + %vals.sroa.7.0.add.ptr.sroa_idx.i = getelementptr i8, ptr null, i64 2 + store i8 %conv32.i, ptr %vals.sroa.7.0.add.ptr.sroa_idx.i, align 1 + %vals.sroa.9.0.add.ptr.sroa_idx.i = getelementptr i8, ptr null, i64 3 + store i8 %conv45.i, ptr %vals.sroa.9.0.add.ptr.sroa_idx.i, align 1 + br label %for.cond.i +} -- GitLab From aa16de6399a42421076ed642c3b4f7fb12c6d44b Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Thu, 9 May 2024 06:35:18 -0500 Subject: [PATCH 126/328] [Linker] Propagate `nobuiltin` attributes when linking known libcalls (#89431) Summary: As discussed in https://discourse.llvm.org/t/rfc-libc-ffreestanding-fno-builtin. LLVM ascribes special semantics to several functions that are known to be `libcalls`. These are functions that middle-end optimizations may transforms calls into or perform optimizations based off of known semantics. However, these assumptions require an opaque function call to be known valid. In situations like LTO or IR linking it is possible to bring a libcall definition into the current module. Once this happens, we can no longer make any guarantees about the semantics of these functions. We currently attempt to solve this by preventing all inlining if the called function has `no-builtin` https://reviews.llvm.org/D74162. However, this is overly pessimistic as it prevents all inlining even for non-libcall functions. This patch modifies the IRMover class to track known libcalls enabled for the given target. If we encounter a known libcall during IR linking, we then need to append the `nobuiltin` attribute to the destination module. Afterwards, all new definitions we link in will be applied as well. --- llvm/include/llvm/Linker/IRMover.h | 33 ++++++++++++++- llvm/lib/Linker/CMakeLists.txt | 1 + llvm/lib/Linker/IRMover.cpp | 67 ++++++++++++++++++++++++++++-- llvm/test/Linker/Inputs/strlen.ll | 21 ++++++++++ llvm/test/Linker/libcalls.ll | 39 +++++++++++++++++ 5 files changed, 156 insertions(+), 5 deletions(-) create mode 100644 llvm/test/Linker/Inputs/strlen.ll create mode 100644 llvm/test/Linker/libcalls.ll diff --git a/llvm/include/llvm/Linker/IRMover.h b/llvm/include/llvm/Linker/IRMover.h index 1e3c5394ffa2..8e71c6080dff 100644 --- a/llvm/include/llvm/Linker/IRMover.h +++ b/llvm/include/llvm/Linker/IRMover.h @@ -12,11 +12,14 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/FunctionExtras.h" +#include "llvm/ADT/StringSet.h" +#include "llvm/IR/GlobalValue.h" +#include "llvm/Support/StringSaver.h" +#include "llvm/TargetParser/Triple.h" #include namespace llvm { class Error; -class GlobalValue; class Metadata; class Module; class StructType; @@ -60,6 +63,33 @@ public: bool hasType(StructType *Ty); }; + /// Utility for handling linking of known libcall functions. If a merged + /// module contains a recognized library call we can no longer perform any + /// libcall related transformations. + class LibcallHandler { + bool HasLibcalls = false; + + StringSet<> Libcalls; + StringSet<> Triples; + + BumpPtrAllocator Alloc; + StringSaver Saver; + + public: + LibcallHandler() : Saver(Alloc) {} + + void updateLibcalls(const Triple &TheTriple); + + bool checkLibcalls(GlobalValue &GV) { + if (HasLibcalls) + return false; + return HasLibcalls = isa(&GV) && !GV.isDeclaration() && + Libcalls.count(GV.getName()); + } + + bool hasLibcalls() const { return HasLibcalls; } + }; + IRMover(Module &M); typedef std::function ValueAdder; @@ -84,6 +114,7 @@ private: Module &Composite; IdentifiedStructTypeSet IdentifiedStructTypes; MDMapT SharedMDs; ///< A Metadata map to use for all calls to \a move(). + LibcallHandler Libcalls; }; } // End llvm namespace diff --git a/llvm/lib/Linker/CMakeLists.txt b/llvm/lib/Linker/CMakeLists.txt index 5afb40f8b588..25001c09a62d 100644 --- a/llvm/lib/Linker/CMakeLists.txt +++ b/llvm/lib/Linker/CMakeLists.txt @@ -9,6 +9,7 @@ add_llvm_component_library(LLVMLinker intrinsics_gen LINK_COMPONENTS + Analysis Core Object Support diff --git a/llvm/lib/Linker/IRMover.cpp b/llvm/lib/Linker/IRMover.cpp index 7a5aa0c80478..fe2b53183589 100644 --- a/llvm/lib/Linker/IRMover.cpp +++ b/llvm/lib/Linker/IRMover.cpp @@ -12,6 +12,7 @@ #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallString.h" +#include "llvm/Analysis/TargetLibraryInfo.h" #include "llvm/IR/AutoUpgrade.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DebugInfoMetadata.h" @@ -399,6 +400,9 @@ class IRLinker { /// A metadata map that's shared between IRLinker instances. MDMapT &SharedMDs; + /// A list of libcalls that the current target may call. + IRMover::LibcallHandler &Libcalls; + /// Mapping of values from what they used to be in Src, to what they are now /// in DstM. ValueToValueMapTy is a ValueMap, which involves some overhead /// due to the use of Value handles which the Linker doesn't actually need, @@ -540,10 +544,12 @@ public: IRLinker(Module &DstM, MDMapT &SharedMDs, IRMover::IdentifiedStructTypeSet &Set, std::unique_ptr SrcM, ArrayRef ValuesToLink, - IRMover::LazyCallback AddLazyFor, bool IsPerformingImport) + IRMover::LibcallHandler &Libcalls, IRMover::LazyCallback AddLazyFor, + bool IsPerformingImport) : DstM(DstM), SrcM(std::move(SrcM)), AddLazyFor(std::move(AddLazyFor)), TypeMap(Set), GValMaterializer(*this), LValMaterializer(*this), - SharedMDs(SharedMDs), IsPerformingImport(IsPerformingImport), + SharedMDs(SharedMDs), Libcalls(Libcalls), + IsPerformingImport(IsPerformingImport), Mapper(ValueMap, RF_ReuseAndMutateDistinctMDs | RF_IgnoreMissingLocals, &TypeMap, &GValMaterializer), IndirectSymbolMCID(Mapper.registerAlternateMappingContext( @@ -561,6 +567,13 @@ public: }; } +static void addNoBuiltinAttributes(Function &F) { + F.setAttributes( + F.getAttributes().addFnAttribute(F.getContext(), "no-builtins")); + F.setAttributes( + F.getAttributes().addFnAttribute(F.getContext(), Attribute::NoBuiltin)); +} + /// The LLVM SymbolTable class autorenames globals that conflict in the symbol /// table. This is good for all clients except for us. Go through the trouble /// to force this back. @@ -1605,14 +1618,26 @@ Error IRLinker::run() { DstM.setTargetTriple(SrcTriple.merge(DstTriple)); + // Update the target triple's libcall information if it was changed. + Libcalls.updateLibcalls(Triple(DstM.getTargetTriple())); + // Loop over all of the linked values to compute type mappings. computeTypeMapping(); + bool AddsLibcalls = false; std::reverse(Worklist.begin(), Worklist.end()); while (!Worklist.empty()) { GlobalValue *GV = Worklist.back(); Worklist.pop_back(); + // If the module already contains libcall functions we need every function + // linked in to have `nobuiltin` attributes. Otherwise check if this is a + // libcall definition. + if (Function *F = dyn_cast(GV); F && Libcalls.hasLibcalls()) + addNoBuiltinAttributes(*F); + else + AddsLibcalls = Libcalls.checkLibcalls(*GV); + // Already mapped. if (ValueMap.find(GV) != ValueMap.end() || IndirectSymbolValueMap.find(GV) != IndirectSymbolValueMap.end()) @@ -1675,6 +1700,13 @@ Error IRLinker::run() { } } + // If we have imported a recognized libcall function we can no longer make any + // reasonable optimizations based off of its semantics. Add the 'nobuiltin' + // attribute to every function to suppress libcall detection. + if (AddsLibcalls) + for (Function &F : DstM.functions()) + addNoBuiltinAttributes(F); + // Merge the module flags into the DstM module. return linkModuleFlagsMetadata(); } @@ -1757,6 +1789,22 @@ bool IRMover::IdentifiedStructTypeSet::hasType(StructType *Ty) { return I == NonOpaqueStructTypes.end() ? false : *I == Ty; } +void IRMover::LibcallHandler::updateLibcalls(const Triple &TheTriple) { + if (Triples.count(TheTriple.getTriple())) + return; + Triples.insert(Saver.save(TheTriple.getTriple())); + + // Collect the names of runtime functions that the target may want to call. + TargetLibraryInfoImpl TLII(TheTriple); + TargetLibraryInfo TLI(TLII); + for (unsigned I = 0, E = static_cast(LibFunc::NumLibFuncs); I != E; + ++I) { + LibFunc F = static_cast(I); + if (TLI.has(F)) + Libcalls.insert(TLI.getName(F)); + } +} + IRMover::IRMover(Module &M) : Composite(M) { TypeFinder StructTypes; StructTypes.run(M, /* OnlyNamed */ false); @@ -1772,14 +1820,25 @@ IRMover::IRMover(Module &M) : Composite(M) { for (const auto *MD : StructTypes.getVisitedMetadata()) { SharedMDs[MD].reset(const_cast(MD)); } + + // Check the composite module for any already present libcalls. If we define + // these then it is important to mark any imported functions as 'nobuiltin'. + Libcalls.updateLibcalls(Triple(Composite.getTargetTriple())); + for (Function &F : Composite.functions()) + if (Libcalls.checkLibcalls(F)) + break; + + if (Libcalls.hasLibcalls()) + for (Function &F : Composite.functions()) + addNoBuiltinAttributes(F); } Error IRMover::move(std::unique_ptr Src, ArrayRef ValuesToLink, LazyCallback AddLazyFor, bool IsPerformingImport) { IRLinker TheIRLinker(Composite, SharedMDs, IdentifiedStructTypes, - std::move(Src), ValuesToLink, std::move(AddLazyFor), - IsPerformingImport); + std::move(Src), ValuesToLink, Libcalls, + std::move(AddLazyFor), IsPerformingImport); Error E = TheIRLinker.run(); Composite.dropTriviallyDeadConstantArrays(); return E; diff --git a/llvm/test/Linker/Inputs/strlen.ll b/llvm/test/Linker/Inputs/strlen.ll new file mode 100644 index 000000000000..bc54aaf41e0c --- /dev/null +++ b/llvm/test/Linker/Inputs/strlen.ll @@ -0,0 +1,21 @@ +target triple = "x86_64-unknown-linux-gnu" + +define i64 @strlen(ptr %s) #0 { +entry: + br label %for.cond + +for.cond: + %s.addr.0 = phi ptr [ %s, %entry ], [ %incdec.ptr, %for.cond ] + %0 = load i8, ptr %s.addr.0, align 1 + %tobool.not = icmp eq i8 %0, 0 + %incdec.ptr = getelementptr inbounds i8, ptr %s.addr.0, i64 1 + br i1 %tobool.not, label %for.end, label %for.cond + +for.end: + %sub.ptr.lhs.cast = ptrtoint ptr %s.addr.0 to i64 + %sub.ptr.rhs.cast = ptrtoint ptr %s to i64 + %sub.ptr.sub = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast + ret i64 %sub.ptr.sub +} + +attributes #0 = { noinline } diff --git a/llvm/test/Linker/libcalls.ll b/llvm/test/Linker/libcalls.ll new file mode 100644 index 000000000000..ddc0d35e91d9 --- /dev/null +++ b/llvm/test/Linker/libcalls.ll @@ -0,0 +1,39 @@ +; RUN: llvm-link %s %S/Inputs/strlen.ll -S -o - 2>%t.a.err | FileCheck %s --check-prefix=CHECK1 +; RUN: llvm-link %S/Inputs/strlen.ll %s -S -o - 2>%t.a.err | FileCheck %s --check-prefix=CHECK2 + +target triple = "x86_64-unknown-linux-gnu" + +@.str = private unnamed_addr constant [7 x i8] c"string\00", align 1 +@str = dso_local global ptr @.str, align 8 + +define void @foo() #0 { + ret void +} + +declare i64 @strlen(ptr) + +define void @bar() #0 { + ret void +} + +define i64 @baz() #0 { +entry: + %0 = load ptr, ptr @str, align 8 + %call = call i64 @strlen(ptr noundef %0) + ret i64 %call +} + +attributes #0 = { noinline } + +; CHECK1: define void @foo() #[[ATTR0:[0-9]+]] +; CHECK1: define void @bar() #[[ATTR0:[0-9]+]] +; CHECK1: define i64 @baz() #[[ATTR0:[0-9]+]] +; CHECK1: define i64 @strlen(ptr [[S:%.*]]) #[[ATTR0]] + +; CHECK2: define i64 @strlen(ptr [[S:%.*]]) #[[ATTR0:[0-9]+]] +; CHECK2: define void @foo() #[[ATTR0:[0-9]+]] +; CHECK2: define void @bar() #[[ATTR0:[0-9]+]] +; CHECK2: define i64 @baz() #[[ATTR0]] + +; CHECK1: attributes #[[ATTR0]] = { nobuiltin noinline "no-builtins" } +; CHECK2: attributes #[[ATTR0]] = { nobuiltin noinline "no-builtins" } -- GitLab From 80f9e814ec896fdc57ee84afad8ac4cb1f8e4627 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Thu, 9 May 2024 06:35:54 -0500 Subject: [PATCH 127/328] [Libomptarget] Statically link all plugin runtimes (#87009) This patch overhauls the `libomptarget` and plugin interface. Currently, we define a C API and compile each plugin as a separate shared library. Then, `libomptarget` loads these API functions and forwards its internal calls to them. This was originally designed to allow multiple implementations of a library to be live. However, since then no one has used this functionality and it prevents us from using much nicer interfaces. If the old behavior is desired it should instead be implemented as a separate plugin. This patch replaces the `PluginAdaptorTy` interface with the `GenericPluginTy` that is used by the plugins. Each plugin exports a `createPlugin_` function that is used to get the specific implementation. This code is now shared with `libomptarget`. There are some notable improvements to this. 1. Massively improved lifetimes of life runtime objects 2. The plugins can use a C++ interface 3. Global state does not need to be duplicated for each plugin + libomptarget 4. Easier to use and add features and improve error handling 5. Less function call overhead / Improved LTO performance. Additional changes in this plugin are related to contending with the fact that state is now shared. Initialization and deinitialization is now handled correctly and in phase with the underlying runtime, allowing us to actually know when something is getting deallocated. Depends on https://github.com/llvm/llvm-project/pull/86971 https://github.com/llvm/llvm-project/pull/86875 https://github.com/llvm/llvm-project/pull/86868 --- clang/test/Driver/linker-wrapper-image.c | 2 +- .../Frontend/Offloading/OffloadWrapper.cpp | 7 +- offload/include/PluginManager.h | 61 ++---- offload/include/device.h | 8 +- offload/plugins-nextgen/CMakeLists.txt | 19 +- offload/plugins-nextgen/amdgpu/CMakeLists.txt | 5 - offload/plugins-nextgen/amdgpu/src/rtl.cpp | 14 +- offload/plugins-nextgen/common/CMakeLists.txt | 5 +- .../common/include/PluginInterface.h | 94 +------- .../common/include/Utils/ELF.h | 2 - offload/plugins-nextgen/common/src/JIT.cpp | 40 ++-- .../common/src/PluginInterface.cpp | 205 ------------------ offload/plugins-nextgen/cuda/CMakeLists.txt | 5 - offload/plugins-nextgen/cuda/src/rtl.cpp | 14 +- offload/plugins-nextgen/host/CMakeLists.txt | 8 - offload/plugins-nextgen/host/src/rtl.cpp | 14 +- offload/src/CMakeLists.txt | 4 + offload/src/OffloadRTL.cpp | 1 + offload/src/OpenMP/InteropAPI.cpp | 4 +- offload/src/PluginManager.cpp | 129 ++++------- offload/src/device.cpp | 3 +- offload/src/interface.cpp | 2 - .../kernelreplay/llvm-omp-kernel-replay.cpp | 2 - .../unittests/Plugins/NextgenPluginsTest.cpp | 1 - 24 files changed, 125 insertions(+), 524 deletions(-) diff --git a/clang/test/Driver/linker-wrapper-image.c b/clang/test/Driver/linker-wrapper-image.c index d01445e3aed0..5d5d62805e17 100644 --- a/clang/test/Driver/linker-wrapper-image.c +++ b/clang/test/Driver/linker-wrapper-image.c @@ -30,8 +30,8 @@ // OPENMP: define internal void @.omp_offloading.descriptor_reg() section ".text.startup" { // OPENMP-NEXT: entry: -// OPENMP-NEXT: %0 = call i32 @atexit(ptr @.omp_offloading.descriptor_unreg) // OPENMP-NEXT: call void @__tgt_register_lib(ptr @.omp_offloading.descriptor) +// OPENMP-NEXT: %0 = call i32 @atexit(ptr @.omp_offloading.descriptor_unreg) // OPENMP-NEXT: ret void // OPENMP-NEXT: } diff --git a/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp b/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp index 7241d15ed1c6..8b6f9ea1f4cc 100644 --- a/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp +++ b/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp @@ -232,12 +232,13 @@ void createRegisterFunction(Module &M, GlobalVariable *BinDesc, // Construct function body IRBuilder<> Builder(BasicBlock::Create(C, "entry", Func)); + Builder.CreateCall(RegFuncC, BinDesc); + // Register the destructors with 'atexit'. This is expected by the CUDA // runtime and ensures that we clean up before dynamic objects are destroyed. - // This needs to be done before the runtime is called and registers its own. + // This needs to be done after plugin initialization to ensure that it is + // called before the plugin runtime is destroyed. Builder.CreateCall(AtExit, UnregFunc); - - Builder.CreateCall(RegFuncC, BinDesc); Builder.CreateRetVoid(); // Add this function to constructors. diff --git a/offload/include/PluginManager.h b/offload/include/PluginManager.h index eece7525e25e..1d6804da75d9 100644 --- a/offload/include/PluginManager.h +++ b/offload/include/PluginManager.h @@ -13,10 +13,11 @@ #ifndef OMPTARGET_PLUGIN_MANAGER_H #define OMPTARGET_PLUGIN_MANAGER_H +#include "PluginInterface.h" + #include "DeviceImage.h" #include "ExclusiveAccess.h" #include "Shared/APITypes.h" -#include "Shared/PluginAPI.h" #include "Shared/Requirements.h" #include "device.h" @@ -34,38 +35,7 @@ #include #include -struct PluginManager; - -/// Plugin adaptors should be created via `PluginAdaptorTy::create` which will -/// invoke the constructor and call `PluginAdaptorTy::init`. Eventual errors are -/// reported back to the caller, otherwise a valid and initialized adaptor is -/// returned. -struct PluginAdaptorTy { - /// Try to create a plugin adaptor from a filename. - static llvm::Expected> - create(const std::string &Name); - - /// Name of the shared object file representing the plugin. - std::string Name; - - /// Access to the shared object file representing the plugin. - std::unique_ptr LibraryHandler; - -#define PLUGIN_API_HANDLE(NAME) \ - using NAME##_ty = decltype(__tgt_rtl_##NAME); \ - NAME##_ty *NAME = nullptr; - -#include "Shared/PluginAPI.inc" -#undef PLUGIN_API_HANDLE - - /// Create a plugin adaptor for filename \p Name with a dynamic library \p DL. - PluginAdaptorTy(const std::string &Name, - std::unique_ptr DL); - - /// Initialize the plugin adaptor, this can fail in which case the adaptor is - /// useless. - llvm::Error init(); -}; +using GenericPluginTy = llvm::omp::target::plugin::GenericPluginTy; /// Struct for the data required to handle plugins struct PluginManager { @@ -80,6 +50,8 @@ struct PluginManager { void init(); + void deinit(); + // Register a shared library with all (compatible) RTLs. void registerLib(__tgt_bin_desc *Desc); @@ -92,10 +64,9 @@ struct PluginManager { std::make_unique(TgtBinDesc, TgtDeviceImage)); } - /// Initialize as many devices as possible for this plugin adaptor. Devices - /// that fail to initialize are ignored. Returns the offset the devices were - /// registered at. - void initDevices(PluginAdaptorTy &RTL); + /// Initialize as many devices as possible for this plugin. Devices that fail + /// to initialize are ignored. + void initDevices(GenericPluginTy &RTL); /// Return the device presented to the user as device \p DeviceNo if it is /// initialized and ready. Otherwise return an error explaining the problem. @@ -151,8 +122,8 @@ struct PluginManager { // Initialize all plugins. void initAllPlugins(); - /// Iterator range for all plugin adaptors (in use or not, but always valid). - auto pluginAdaptors() { return llvm::make_pointee_range(PluginAdaptors); } + /// Iterator range for all plugins (in use or not, but always valid). + auto plugins() { return llvm::make_pointee_range(Plugins); } /// Return the user provided requirements. int64_t getRequirements() const { return Requirements.getRequirements(); } @@ -164,14 +135,14 @@ private: bool RTLsLoaded = false; llvm::SmallVector<__tgt_bin_desc *> DelayedBinDesc; - // List of all plugin adaptors, in use or not. - llvm::SmallVector> PluginAdaptors; + // List of all plugins, in use or not. + llvm::SmallVector> Plugins; - // Mapping of plugin adaptors to offsets in the device table. - llvm::DenseMap DeviceOffsets; + // Mapping of plugins to offsets in the device table. + llvm::DenseMap DeviceOffsets; - // Mapping of plugin adaptors to the number of used devices. - llvm::DenseMap DeviceUsed; + // Mapping of plugins to the number of used devices. + llvm::DenseMap DeviceUsed; // Set of all device images currently in use. llvm::DenseSet UsedImages; diff --git a/offload/include/device.h b/offload/include/device.h index bd2829722bb3..fd6e5fba5fc5 100644 --- a/offload/include/device.h +++ b/offload/include/device.h @@ -33,17 +33,19 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" +#include "PluginInterface.h" +using GenericPluginTy = llvm::omp::target::plugin::GenericPluginTy; + // Forward declarations. -struct PluginAdaptorTy; struct __tgt_bin_desc; struct __tgt_target_table; struct DeviceTy { int32_t DeviceID; - PluginAdaptorTy *RTL; + GenericPluginTy *RTL; int32_t RTLDeviceID; - DeviceTy(PluginAdaptorTy *RTL, int32_t DeviceID, int32_t RTLDeviceID); + DeviceTy(GenericPluginTy *RTL, int32_t DeviceID, int32_t RTLDeviceID); // DeviceTy is not copyable DeviceTy(const DeviceTy &D) = delete; DeviceTy &operator=(const DeviceTy &D) = delete; diff --git a/offload/plugins-nextgen/CMakeLists.txt b/offload/plugins-nextgen/CMakeLists.txt index df625e97c7eb..d1079f8a3e9c 100644 --- a/offload/plugins-nextgen/CMakeLists.txt +++ b/offload/plugins-nextgen/CMakeLists.txt @@ -14,7 +14,7 @@ set(common_dir ${CMAKE_CURRENT_SOURCE_DIR}/common) add_subdirectory(common) function(add_target_library target_name lib_name) - add_llvm_library(${target_name} SHARED + add_llvm_library(${target_name} STATIC LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD} AggressiveInstCombine @@ -46,27 +46,14 @@ function(add_target_library target_name lib_name) ) llvm_update_compile_flags(${target_name}) + target_include_directories(${target_name} PUBLIC ${common_dir}/include) target_link_libraries(${target_name} PRIVATE PluginCommon ${OPENMP_PTHREAD_LIB}) target_compile_definitions(${target_name} PRIVATE TARGET_NAME=${lib_name}) target_compile_definitions(${target_name} PRIVATE DEBUG_PREFIX="TARGET ${lib_name} RTL") - - if(CMAKE_SYSTEM_NAME MATCHES "FreeBSD") - # On FreeBSD, the 'environ' symbol is undefined at link time, but resolved by - # the dynamic linker at runtime. Therefore, allow the symbol to be undefined - # when creating a shared library. - target_link_libraries(${target_name} PRIVATE "-Wl,--allow-shlib-undefined") - else() - target_link_libraries(${target_name} PRIVATE "-Wl,-z,defs") - endif() - - if(LIBOMP_HAVE_VERSION_SCRIPT_FLAG) - target_link_libraries(${target_name} PRIVATE - "-Wl,--version-script=${common_dir}/../exports") - endif() - set_target_properties(${target_name} PROPERTIES CXX_VISIBILITY_PRESET protected) + set_target_properties(${target_name} PROPERTIES POSITION_INDEPENDENT_CODE ON) endfunction() foreach(plugin IN LISTS LIBOMPTARGET_PLUGINS_TO_BUILD) diff --git a/offload/plugins-nextgen/amdgpu/CMakeLists.txt b/offload/plugins-nextgen/amdgpu/CMakeLists.txt index f5f7096137c2..738183f8945e 100644 --- a/offload/plugins-nextgen/amdgpu/CMakeLists.txt +++ b/offload/plugins-nextgen/amdgpu/CMakeLists.txt @@ -57,8 +57,3 @@ else() libomptarget_say("Not generating AMDGPU tests, no supported devices detected." " Use 'LIBOMPTARGET_FORCE_AMDGPU_TESTS' to override.") endif() - -# Install plugin under the lib destination folder. -install(TARGETS omptarget.rtl.amdgpu LIBRARY DESTINATION "${OFFLOAD_INSTALL_LIBDIR}") -set_target_properties(omptarget.rtl.amdgpu PROPERTIES - INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/..") diff --git a/offload/plugins-nextgen/amdgpu/src/rtl.cpp b/offload/plugins-nextgen/amdgpu/src/rtl.cpp index 00650b801b42..295685fceaa4 100644 --- a/offload/plugins-nextgen/amdgpu/src/rtl.cpp +++ b/offload/plugins-nextgen/amdgpu/src/rtl.cpp @@ -3064,10 +3064,6 @@ struct AMDGPUPluginTy final : public GenericPluginTy { // HSA functions from now on, e.g., hsa_shut_down. Initialized = true; -#ifdef OMPT_SUPPORT - ompt::connectLibrary(); -#endif - // Register event handler to detect memory errors on the devices. Status = hsa_amd_register_system_event_handler(eventHandler, nullptr); if (auto Err = Plugin::check( @@ -3155,6 +3151,8 @@ struct AMDGPUPluginTy final : public GenericPluginTy { Triple::ArchType getTripleArch() const override { return Triple::amdgcn; } + const char *getName() const override { return GETNAME(TARGET_NAME); } + /// Get the ELF code for recognizing the compatible image binary. uint16_t getMagicElfBits() const override { return ELF::EM_AMDGPU; } @@ -3387,8 +3385,6 @@ Error AMDGPUKernelTy::printLaunchInfoDetails(GenericDeviceTy &GenericDevice, return Plugin::success(); } -GenericPluginTy *PluginTy::createPlugin() { return new AMDGPUPluginTy(); } - template static Error Plugin::check(int32_t Code, const char *ErrFmt, ArgsTy... Args) { hsa_status_t ResultCode = static_cast(Code); @@ -3476,3 +3472,9 @@ void *AMDGPUDeviceTy::allocate(size_t Size, void *, TargetAllocTy Kind) { } // namespace target } // namespace omp } // namespace llvm + +extern "C" { +llvm::omp::target::plugin::GenericPluginTy *createPlugin_amdgpu() { + return new llvm::omp::target::plugin::AMDGPUPluginTy(); +} +} diff --git a/offload/plugins-nextgen/common/CMakeLists.txt b/offload/plugins-nextgen/common/CMakeLists.txt index acf0af63f050..a6bbb7e9454b 100644 --- a/offload/plugins-nextgen/common/CMakeLists.txt +++ b/offload/plugins-nextgen/common/CMakeLists.txt @@ -46,7 +46,6 @@ endif() # If we have OMPT enabled include it in the list of sources. if (OMPT_TARGET_DEFAULT AND LIBOMPTARGET_OMPT_SUPPORT) - target_sources(PluginCommon PRIVATE OMPT/OmptCallback.cpp) target_include_directories(PluginCommon PRIVATE OMPT) endif() @@ -66,6 +65,4 @@ target_include_directories(PluginCommon PUBLIC ${LIBOMPTARGET_INCLUDE_DIR} ) -set_target_properties(PluginCommon PROPERTIES - POSITION_INDEPENDENT_CODE ON - CXX_VISIBILITY_PRESET protected) +set_target_properties(PluginCommon PROPERTIES POSITION_INDEPENDENT_CODE ON) diff --git a/offload/plugins-nextgen/common/include/PluginInterface.h b/offload/plugins-nextgen/common/include/PluginInterface.h index 79e8464bfda5..e7a008f3a857 100644 --- a/offload/plugins-nextgen/common/include/PluginInterface.h +++ b/offload/plugins-nextgen/common/include/PluginInterface.h @@ -1010,6 +1010,9 @@ struct GenericPluginTy { /// Get the target triple of this plugin. virtual Triple::ArchType getTripleArch() const = 0; + /// Get the constant name identifier for this plugin. + virtual const char *getName() const = 0; + /// Allocate a structure using the internal allocator. template Ty *allocate() { return reinterpret_cast(Allocator.Allocate(sizeof(Ty), alignof(Ty))); @@ -1226,7 +1229,7 @@ namespace Plugin { /// Create a success error. This is the same as calling Error::success(), but /// it is recommended to use this one for consistency with Plugin::error() and /// Plugin::check(). -static Error success() { return Error::success(); } +static inline Error success() { return Error::success(); } /// Create a string error. template @@ -1246,95 +1249,6 @@ template static Error check(int32_t ErrorCode, const char *ErrFmt, ArgsTy... Args); } // namespace Plugin -/// Class for simplifying the getter operation of the plugin. Anywhere on the -/// code, the current plugin can be retrieved by Plugin::get(). The class also -/// declares functions to create plugin-specific object instances. The check(), -/// createPlugin(), createDevice() and createGlobalHandler() functions should be -/// defined by each plugin implementation. -class PluginTy { - // Reference to the plugin instance. - static GenericPluginTy *SpecificPlugin; - - PluginTy() { - if (auto Err = init()) - REPORT("Failed to initialize plugin: %s\n", - toString(std::move(Err)).data()); - } - - ~PluginTy() { - if (auto Err = deinit()) - REPORT("Failed to deinitialize plugin: %s\n", - toString(std::move(Err)).data()); - } - - PluginTy(const PluginTy &) = delete; - void operator=(const PluginTy &) = delete; - - /// Create and intialize the plugin instance. - static Error init() { - assert(!SpecificPlugin && "Plugin already created"); - - // Create the specific plugin. - SpecificPlugin = createPlugin(); - assert(SpecificPlugin && "Plugin was not created"); - - // Initialize the plugin. - return SpecificPlugin->init(); - } - - // Deinitialize and destroy the plugin instance. - static Error deinit() { - assert(SpecificPlugin && "Plugin no longer valid"); - - for (int32_t DevNo = 0, NumDev = SpecificPlugin->getNumDevices(); - DevNo < NumDev; ++DevNo) - if (auto Err = SpecificPlugin->deinitDevice(DevNo)) - return Err; - - // Deinitialize the plugin. - if (auto Err = SpecificPlugin->deinit()) - return Err; - - // Delete the plugin instance. - delete SpecificPlugin; - - // Invalidate the plugin reference. - SpecificPlugin = nullptr; - - return Plugin::success(); - } - -public: - /// Initialize the plugin if needed. The plugin could have been initialized by - /// a previous call to Plugin::get(). - static Error initIfNeeded() { - // Trigger the initialization if needed. - get(); - - return Error::success(); - } - - /// Get a reference (or create if it was not created) to the plugin instance. - static GenericPluginTy &get() { - // This static variable will initialize the underlying plugin instance in - // case there was no previous explicit initialization. The initialization is - // thread safe. - static PluginTy Plugin; - - assert(SpecificPlugin && "Plugin is not active"); - return *SpecificPlugin; - } - - /// Get a reference to the plugin with a specific plugin-specific type. - template static Ty &get() { return static_cast(get()); } - - /// Indicate whether the plugin is active. - static bool isActive() { return SpecificPlugin != nullptr; } - - /// Create a plugin instance. - static GenericPluginTy *createPlugin(); -}; - /// Auxiliary interface class for GenericDeviceResourceManagerTy. This class /// acts as a reference to a device resource, such as a stream, and requires /// some basic functions to be implemented. The derived class should define an diff --git a/offload/plugins-nextgen/common/include/Utils/ELF.h b/offload/plugins-nextgen/common/include/Utils/ELF.h index f87e0a5ed02b..dcfdb5bd7b03 100644 --- a/offload/plugins-nextgen/common/include/Utils/ELF.h +++ b/offload/plugins-nextgen/common/include/Utils/ELF.h @@ -13,8 +13,6 @@ #ifndef LLVM_OPENMP_LIBOMPTARGET_PLUGINS_ELF_UTILS_H #define LLVM_OPENMP_LIBOMPTARGET_PLUGINS_ELF_UTILS_H -#include "Shared/PluginAPI.h" - #include "llvm/Object/ELF.h" #include "llvm/Object/ELFObjectFile.h" diff --git a/offload/plugins-nextgen/common/src/JIT.cpp b/offload/plugins-nextgen/common/src/JIT.cpp index 9eb610cab4de..9d58e6060646 100644 --- a/offload/plugins-nextgen/common/src/JIT.cpp +++ b/offload/plugins-nextgen/common/src/JIT.cpp @@ -56,28 +56,6 @@ bool isImageBitcode(const __tgt_device_image &Image) { return identify_magic(Binary) == file_magic::bitcode; } -std::once_flag InitFlag; - -void init(Triple TT) { - codegen::RegisterCodeGenFlags(); -#ifdef LIBOMPTARGET_JIT_NVPTX - if (TT.isNVPTX()) { - LLVMInitializeNVPTXTargetInfo(); - LLVMInitializeNVPTXTarget(); - LLVMInitializeNVPTXTargetMC(); - LLVMInitializeNVPTXAsmPrinter(); - } -#endif -#ifdef LIBOMPTARGET_JIT_AMDGPU - if (TT.isAMDGPU()) { - LLVMInitializeAMDGPUTargetInfo(); - LLVMInitializeAMDGPUTarget(); - LLVMInitializeAMDGPUTargetMC(); - LLVMInitializeAMDGPUAsmPrinter(); - } -#endif -} - Expected> createModuleFromMemoryBuffer(std::unique_ptr &MB, LLVMContext &Context) { @@ -148,7 +126,23 @@ createTargetMachine(Module &M, std::string CPU, unsigned OptLevel) { } // namespace JITEngine::JITEngine(Triple::ArchType TA) : TT(Triple::getArchTypeName(TA)) { - std::call_once(InitFlag, init, TT); + codegen::RegisterCodeGenFlags(); +#ifdef LIBOMPTARGET_JIT_NVPTX + if (TT.isNVPTX()) { + LLVMInitializeNVPTXTargetInfo(); + LLVMInitializeNVPTXTarget(); + LLVMInitializeNVPTXTargetMC(); + LLVMInitializeNVPTXAsmPrinter(); + } +#endif +#ifdef LIBOMPTARGET_JIT_AMDGPU + if (TT.isAMDGPU()) { + LLVMInitializeAMDGPUTargetInfo(); + LLVMInitializeAMDGPUTarget(); + LLVMInitializeAMDGPUTargetMC(); + LLVMInitializeAMDGPUAsmPrinter(); + } +#endif } void JITEngine::opt(TargetMachine *TM, TargetLibraryInfoImpl *TLII, Module &M, diff --git a/offload/plugins-nextgen/common/src/PluginInterface.cpp b/offload/plugins-nextgen/common/src/PluginInterface.cpp index 8de93ba17a56..fae197527850 100644 --- a/offload/plugins-nextgen/common/src/PluginInterface.cpp +++ b/offload/plugins-nextgen/common/src/PluginInterface.cpp @@ -13,7 +13,6 @@ #include "Shared/APITypes.h" #include "Shared/Debug.h" #include "Shared/Environment.h" -#include "Shared/PluginAPI.h" #include "GlobalHandler.h" #include "JIT.h" @@ -39,8 +38,6 @@ using namespace omp; using namespace target; using namespace plugin; -GenericPluginTy *PluginTy::SpecificPlugin = nullptr; - // TODO: Fix any thread safety issues for multi-threaded kernel recording. struct RecordReplayTy { @@ -2035,205 +2032,3 @@ bool llvm::omp::target::plugin::libomptargetSupportsRPC() { return false; #endif } - -/// Exposed library API function, basically wrappers around the GenericDeviceTy -/// functionality with the same name. All non-async functions are redirected -/// to the async versions right away with a NULL AsyncInfoPtr. -#ifdef __cplusplus -extern "C" { -#endif - -int32_t __tgt_rtl_init_plugin() { - auto Err = PluginTy::initIfNeeded(); - if (Err) { - [[maybe_unused]] std::string ErrStr = toString(std::move(Err)); - DP("Failed to init plugin: %s", ErrStr.c_str()); - return OFFLOAD_FAIL; - } - - return OFFLOAD_SUCCESS; -} - -int32_t __tgt_rtl_is_valid_binary(__tgt_device_image *Image) { - if (!PluginTy::isActive()) - return false; - - return PluginTy::get().is_valid_binary(Image); -} - -int32_t __tgt_rtl_init_device(int32_t DeviceId) { - return PluginTy::get().init_device(DeviceId); -} - -int32_t __tgt_rtl_number_of_devices() { - return PluginTy::get().number_of_devices(); -} - -int64_t __tgt_rtl_init_requires(int64_t RequiresFlags) { - return PluginTy::get().init_requires(RequiresFlags); -} - -int32_t __tgt_rtl_is_data_exchangable(int32_t SrcDeviceId, - int32_t DstDeviceId) { - return PluginTy::get().is_data_exchangable(SrcDeviceId, DstDeviceId); -} - -int32_t __tgt_rtl_initialize_record_replay(int32_t DeviceId, int64_t MemorySize, - void *VAddr, bool isRecord, - bool SaveOutput, - uint64_t &ReqPtrArgOffset) { - return PluginTy::get().initialize_record_replay( - DeviceId, MemorySize, VAddr, isRecord, SaveOutput, ReqPtrArgOffset); -} - -int32_t __tgt_rtl_load_binary(int32_t DeviceId, __tgt_device_image *TgtImage, - __tgt_device_binary *Binary) { - return PluginTy::get().load_binary(DeviceId, TgtImage, Binary); -} - -void *__tgt_rtl_data_alloc(int32_t DeviceId, int64_t Size, void *HostPtr, - int32_t Kind) { - return PluginTy::get().data_alloc(DeviceId, Size, HostPtr, Kind); -} - -int32_t __tgt_rtl_data_delete(int32_t DeviceId, void *TgtPtr, int32_t Kind) { - return PluginTy::get().data_delete(DeviceId, TgtPtr, Kind); -} - -int32_t __tgt_rtl_data_lock(int32_t DeviceId, void *Ptr, int64_t Size, - void **LockedPtr) { - return PluginTy::get().data_lock(DeviceId, Ptr, Size, LockedPtr); -} - -int32_t __tgt_rtl_data_unlock(int32_t DeviceId, void *Ptr) { - return PluginTy::get().data_unlock(DeviceId, Ptr); -} - -int32_t __tgt_rtl_data_notify_mapped(int32_t DeviceId, void *HstPtr, - int64_t Size) { - return PluginTy::get().data_notify_mapped(DeviceId, HstPtr, Size); -} - -int32_t __tgt_rtl_data_notify_unmapped(int32_t DeviceId, void *HstPtr) { - return PluginTy::get().data_notify_unmapped(DeviceId, HstPtr); -} - -int32_t __tgt_rtl_data_submit(int32_t DeviceId, void *TgtPtr, void *HstPtr, - int64_t Size) { - return PluginTy::get().data_submit(DeviceId, TgtPtr, HstPtr, Size); -} - -int32_t __tgt_rtl_data_submit_async(int32_t DeviceId, void *TgtPtr, - void *HstPtr, int64_t Size, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().data_submit_async(DeviceId, TgtPtr, HstPtr, Size, - AsyncInfoPtr); -} - -int32_t __tgt_rtl_data_retrieve(int32_t DeviceId, void *HstPtr, void *TgtPtr, - int64_t Size) { - return PluginTy::get().data_retrieve(DeviceId, HstPtr, TgtPtr, Size); -} - -int32_t __tgt_rtl_data_retrieve_async(int32_t DeviceId, void *HstPtr, - void *TgtPtr, int64_t Size, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().data_retrieve_async(DeviceId, HstPtr, TgtPtr, Size, - AsyncInfoPtr); -} - -int32_t __tgt_rtl_data_exchange(int32_t SrcDeviceId, void *SrcPtr, - int32_t DstDeviceId, void *DstPtr, - int64_t Size) { - return PluginTy::get().data_exchange(SrcDeviceId, SrcPtr, DstDeviceId, DstPtr, - Size); -} - -int32_t __tgt_rtl_data_exchange_async(int32_t SrcDeviceId, void *SrcPtr, - int DstDeviceId, void *DstPtr, - int64_t Size, - __tgt_async_info *AsyncInfo) { - return PluginTy::get().data_exchange_async(SrcDeviceId, SrcPtr, DstDeviceId, - DstPtr, Size, AsyncInfo); -} - -int32_t __tgt_rtl_launch_kernel(int32_t DeviceId, void *TgtEntryPtr, - void **TgtArgs, ptrdiff_t *TgtOffsets, - KernelArgsTy *KernelArgs, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().launch_kernel(DeviceId, TgtEntryPtr, TgtArgs, - TgtOffsets, KernelArgs, AsyncInfoPtr); -} - -int32_t __tgt_rtl_synchronize(int32_t DeviceId, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().synchronize(DeviceId, AsyncInfoPtr); -} - -int32_t __tgt_rtl_query_async(int32_t DeviceId, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().query_async(DeviceId, AsyncInfoPtr); -} - -void __tgt_rtl_print_device_info(int32_t DeviceId) { - PluginTy::get().print_device_info(DeviceId); -} - -int32_t __tgt_rtl_create_event(int32_t DeviceId, void **EventPtr) { - return PluginTy::get().create_event(DeviceId, EventPtr); -} - -int32_t __tgt_rtl_record_event(int32_t DeviceId, void *EventPtr, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().record_event(DeviceId, EventPtr, AsyncInfoPtr); -} - -int32_t __tgt_rtl_wait_event(int32_t DeviceId, void *EventPtr, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().wait_event(DeviceId, EventPtr, AsyncInfoPtr); -} - -int32_t __tgt_rtl_sync_event(int32_t DeviceId, void *EventPtr) { - return PluginTy::get().sync_event(DeviceId, EventPtr); -} - -int32_t __tgt_rtl_destroy_event(int32_t DeviceId, void *EventPtr) { - return PluginTy::get().destroy_event(DeviceId, EventPtr); -} - -void __tgt_rtl_set_info_flag(uint32_t NewInfoLevel) { - return PluginTy::get().set_info_flag(NewInfoLevel); -} - -int32_t __tgt_rtl_init_async_info(int32_t DeviceId, - __tgt_async_info **AsyncInfoPtr) { - return PluginTy::get().init_async_info(DeviceId, AsyncInfoPtr); -} - -int32_t __tgt_rtl_init_device_info(int32_t DeviceId, - __tgt_device_info *DeviceInfo, - const char **ErrStr) { - return PluginTy::get().init_device_info(DeviceId, DeviceInfo, ErrStr); -} - -int32_t __tgt_rtl_set_device_offset(int32_t DeviceIdOffset) { - return PluginTy::get().set_device_offset(DeviceIdOffset); -} - -int32_t __tgt_rtl_use_auto_zero_copy(int32_t DeviceId) { - return PluginTy::get().use_auto_zero_copy(DeviceId); -} - -int32_t __tgt_rtl_get_global(__tgt_device_binary Binary, uint64_t Size, - const char *Name, void **DevicePtr) { - return PluginTy::get().get_global(Binary, Size, Name, DevicePtr); -} - -int32_t __tgt_rtl_get_function(__tgt_device_binary Binary, const char *Name, - void **KernelPtr) { - return PluginTy::get().get_function(Binary, Name, KernelPtr); -} - -#ifdef __cplusplus -} -#endif diff --git a/offload/plugins-nextgen/cuda/CMakeLists.txt b/offload/plugins-nextgen/cuda/CMakeLists.txt index 0284bd22d2a4..dd684bb22343 100644 --- a/offload/plugins-nextgen/cuda/CMakeLists.txt +++ b/offload/plugins-nextgen/cuda/CMakeLists.txt @@ -51,8 +51,3 @@ else() libomptarget_say("Not generating NVIDIA tests, no supported devices detected." " Use 'LIBOMPTARGET_FORCE_NVIDIA_TESTS' to override.") endif() - -# Install plugin under the lib destination folder. -install(TARGETS omptarget.rtl.cuda LIBRARY DESTINATION "${OFFLOAD_INSTALL_LIBDIR}") -set_target_properties(omptarget.rtl.cuda PROPERTIES - INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/..") diff --git a/offload/plugins-nextgen/cuda/src/rtl.cpp b/offload/plugins-nextgen/cuda/src/rtl.cpp index fc74c6aa23fd..b260334baa18 100644 --- a/offload/plugins-nextgen/cuda/src/rtl.cpp +++ b/offload/plugins-nextgen/cuda/src/rtl.cpp @@ -1342,10 +1342,6 @@ struct CUDAPluginTy final : public GenericPluginTy { return 0; } -#ifdef OMPT_SUPPORT - ompt::connectLibrary(); -#endif - if (Res == CUDA_ERROR_NO_DEVICE) { // Do not initialize if there are no devices. DP("There are no devices supporting CUDA.\n"); @@ -1390,6 +1386,8 @@ struct CUDAPluginTy final : public GenericPluginTy { return Triple::nvptx64; } + const char *getName() const override { return GETNAME(TARGET_NAME); } + /// Check whether the image is compatible with the available CUDA devices. Expected isELFCompatible(StringRef Image) const override { auto ElfOrErr = @@ -1495,8 +1493,6 @@ Error CUDADeviceTy::dataExchangeImpl(const void *SrcPtr, return Plugin::check(Res, "Error in cuMemcpyDtoDAsync: %s"); } -GenericPluginTy *PluginTy::createPlugin() { return new CUDAPluginTy(); } - template static Error Plugin::check(int32_t Code, const char *ErrFmt, ArgsTy... Args) { CUresult ResultCode = static_cast(Code); @@ -1516,3 +1512,9 @@ static Error Plugin::check(int32_t Code, const char *ErrFmt, ArgsTy... Args) { } // namespace target } // namespace omp } // namespace llvm + +extern "C" { +llvm::omp::target::plugin::GenericPluginTy *createPlugin_cuda() { + return new llvm::omp::target::plugin::CUDAPluginTy(); +} +} diff --git a/offload/plugins-nextgen/host/CMakeLists.txt b/offload/plugins-nextgen/host/CMakeLists.txt index 1d000442c84d..72b5681283fe 100644 --- a/offload/plugins-nextgen/host/CMakeLists.txt +++ b/offload/plugins-nextgen/host/CMakeLists.txt @@ -31,14 +31,6 @@ else() target_include_directories(omptarget.rtl.host PRIVATE dynamic_ffi) endif() -# Install plugin under the lib destination folder. -install(TARGETS omptarget.rtl.host - LIBRARY DESTINATION "${OFFLOAD_INSTALL_LIBDIR}") -set_target_properties(omptarget.rtl.host PROPERTIES - INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/.." - POSITION_INDEPENDENT_CODE ON - CXX_VISIBILITY_PRESET protected) - target_include_directories(omptarget.rtl.host PRIVATE ${LIBOMPTARGET_INCLUDE_DIR}) diff --git a/offload/plugins-nextgen/host/src/rtl.cpp b/offload/plugins-nextgen/host/src/rtl.cpp index 4bdcae3dd6a1..409b44b1640a 100644 --- a/offload/plugins-nextgen/host/src/rtl.cpp +++ b/offload/plugins-nextgen/host/src/rtl.cpp @@ -385,10 +385,6 @@ struct GenELF64PluginTy final : public GenericPluginTy { /// Initialize the plugin and return the number of devices. Expected initImpl() override { -#ifdef OMPT_SUPPORT - ompt::connectLibrary(); -#endif - #ifdef USES_DYNAMIC_FFI if (auto Err = Plugin::check(ffi_init(), "Failed to initialize libffi")) return std::move(Err); @@ -445,9 +441,9 @@ struct GenELF64PluginTy final : public GenericPluginTy { return llvm::Triple::UnknownArch; #endif } -}; -GenericPluginTy *PluginTy::createPlugin() { return new GenELF64PluginTy(); } + const char *getName() const override { return GETNAME(TARGET_NAME); } +}; template static Error Plugin::check(int32_t Code, const char *ErrMsg, ArgsTy... Args) { @@ -462,3 +458,9 @@ static Error Plugin::check(int32_t Code, const char *ErrMsg, ArgsTy... Args) { } // namespace target } // namespace omp } // namespace llvm + +extern "C" { +llvm::omp::target::plugin::GenericPluginTy *createPlugin_host() { + return new llvm::omp::target::plugin::GenELF64PluginTy(); +} +} diff --git a/offload/src/CMakeLists.txt b/offload/src/CMakeLists.txt index eda5a85ff1ab..8fe6d19d83eb 100644 --- a/offload/src/CMakeLists.txt +++ b/offload/src/CMakeLists.txt @@ -65,6 +65,10 @@ target_compile_definitions(omptarget PRIVATE DEBUG_PREFIX="omptarget" ) +foreach(plugin IN LISTS LIBOMPTARGET_PLUGINS_TO_BUILD) + target_link_libraries(omptarget PRIVATE omptarget.rtl.${plugin}) +endforeach() + target_compile_options(omptarget PUBLIC ${offload_compile_flags}) target_link_options(omptarget PUBLIC ${offload_link_flags}) diff --git a/offload/src/OffloadRTL.cpp b/offload/src/OffloadRTL.cpp index dd75b1b18150..29b573a27d08 100644 --- a/offload/src/OffloadRTL.cpp +++ b/offload/src/OffloadRTL.cpp @@ -50,6 +50,7 @@ void deinitRuntime() { if (RefCount == 1) { DP("Deinit offload library!\n"); + PM->deinit(); delete PM; PM = nullptr; } diff --git a/offload/src/OpenMP/InteropAPI.cpp b/offload/src/OpenMP/InteropAPI.cpp index 1a995cde7816..bdbc440c64a2 100644 --- a/offload/src/OpenMP/InteropAPI.cpp +++ b/offload/src/OpenMP/InteropAPI.cpp @@ -230,14 +230,14 @@ void __tgt_interop_init(ident_t *LocRef, int32_t Gtid, } DeviceTy &Device = *DeviceOrErr; - if (!Device.RTL || !Device.RTL->init_device_info || + if (!Device.RTL || Device.RTL->init_device_info(DeviceId, &(InteropPtr)->device_info, &(InteropPtr)->err_str)) { delete InteropPtr; InteropPtr = omp_interop_none; } if (InteropType == kmp_interop_type_tasksync) { - if (!Device.RTL || !Device.RTL->init_async_info || + if (!Device.RTL || Device.RTL->init_async_info(DeviceId, &(InteropPtr)->async_info)) { delete InteropPtr; InteropPtr = omp_interop_none; diff --git a/offload/src/PluginManager.cpp b/offload/src/PluginManager.cpp index dbb556c179e5..191afa345641 100644 --- a/offload/src/PluginManager.cpp +++ b/offload/src/PluginManager.cpp @@ -23,85 +23,25 @@ using namespace llvm::sys; PluginManager *PM = nullptr; -Expected> -PluginAdaptorTy::create(const std::string &Name) { - DP("Attempting to load library '%s'...\n", Name.c_str()); - TIMESCOPE_WITH_NAME_AND_IDENT(Name, (const ident_t *)nullptr); - - std::string ErrMsg; - auto LibraryHandler = std::make_unique( - DynamicLibrary::getPermanentLibrary(Name.c_str(), &ErrMsg)); - - if (!LibraryHandler->isValid()) { - // Library does not exist or cannot be found. - return createStringError(inconvertibleErrorCode(), - "Unable to load library '%s': %s!\n", Name.c_str(), - ErrMsg.c_str()); - } - - DP("Successfully loaded library '%s'!\n", Name.c_str()); - auto PluginAdaptor = std::unique_ptr( - new PluginAdaptorTy(Name, std::move(LibraryHandler))); - if (auto Err = PluginAdaptor->init()) - return Err; - return std::move(PluginAdaptor); -} - -PluginAdaptorTy::PluginAdaptorTy(const std::string &Name, - std::unique_ptr DL) - : Name(Name), LibraryHandler(std::move(DL)) {} - -Error PluginAdaptorTy::init() { - -#define PLUGIN_API_HANDLE(NAME) \ - NAME = reinterpret_cast( \ - LibraryHandler->getAddressOfSymbol(GETNAME(__tgt_rtl_##NAME))); \ - if (!NAME) { \ - return createStringError(inconvertibleErrorCode(), \ - "Invalid plugin as necessary interface function " \ - "(%s) was not found.\n", \ - std::string(#NAME).c_str()); \ - } - -#include "Shared/PluginAPI.inc" -#undef PLUGIN_API_HANDLE - - // Remove plugin on failure to call optional init_plugin - int32_t Rc = init_plugin(); - if (Rc != OFFLOAD_SUCCESS) { - return createStringError(inconvertibleErrorCode(), - "Unable to initialize library '%s': %u!\n", - Name.c_str(), Rc); - } - - // No devices are supported by this RTL? - int32_t NumberOfPluginDevices = number_of_devices(); - if (!NumberOfPluginDevices) { - return createStringError(inconvertibleErrorCode(), - "No devices supported in this RTL\n"); - } - - DP("Registered '%s' with %d plugin visible devices!\n", Name.c_str(), - NumberOfPluginDevices); - return Error::success(); -} +// Every plugin exports this method to create an instance of the plugin type. +#define PLUGIN_TARGET(Name) extern "C" GenericPluginTy *createPlugin_##Name(); +#include "Shared/Targets.def" void PluginManager::init() { TIMESCOPE(); DP("Loading RTLs...\n"); - // Attempt to open all the plugins and, if they exist, check if the interface - // is correct and if they are supporting any devices. + // Attempt to create an instance of each supported plugin. #define PLUGIN_TARGET(Name) \ do { \ - auto PluginAdaptorOrErr = \ - PluginAdaptorTy::create("libomptarget.rtl." #Name ".so"); \ - if (!PluginAdaptorOrErr) { \ - [[maybe_unused]] std::string InfoMsg = \ - toString(PluginAdaptorOrErr.takeError()); \ - DP("%s", InfoMsg.c_str()); \ + auto Plugin = std::unique_ptr(createPlugin_##Name()); \ + if (auto Err = Plugin->init()) { \ + [[maybe_unused]] std::string InfoMsg = toString(std::move(Err)); \ + DP("Failed to init plugin: %s\n", InfoMsg.c_str()); \ } else { \ - PluginAdaptors.push_back(std::move(*PluginAdaptorOrErr)); \ + DP("Registered plugin %s with %d visible device(s)\n", \ + Plugin->getName(), Plugin->number_of_devices()); \ + Plugins.emplace_back(std::move(Plugin)); \ } \ } while (false); #include "Shared/Targets.def" @@ -109,15 +49,29 @@ void PluginManager::init() { DP("RTLs loaded!\n"); } -void PluginManager::initDevices(PluginAdaptorTy &RTL) { +void PluginManager::deinit() { + TIMESCOPE(); + DP("Unloading RTLs...\n"); + + for (auto &Plugin : Plugins) { + if (auto Err = Plugin->deinit()) { + [[maybe_unused]] std::string InfoMsg = toString(std::move(Err)); + DP("Failed to deinit plugin: %s\n", InfoMsg.c_str()); + } + Plugin.release(); + } + + DP("RTLs unloaded!\n"); +} + +void PluginManager::initDevices(GenericPluginTy &RTL) { // If this RTL has already been initialized. if (PM->DeviceOffsets.contains(&RTL)) return; TIMESCOPE(); // If this RTL is not already in use, initialize it. - assert(RTL.number_of_devices() > 0 && - "Tried to initialize useless plugin adaptor"); + assert(RTL.number_of_devices() > 0 && "Tried to initialize useless plugin!"); // Initialize the device information for the RTL we are about to use. auto ExclusiveDevicesAccessor = getExclusiveDevicesAccessor(); @@ -157,13 +111,12 @@ void PluginManager::initDevices(PluginAdaptorTy &RTL) { DeviceOffsets[&RTL] = DeviceOffset; DeviceUsed[&RTL] = NumberOfUserDevices; - DP("Plugin adaptor " DPxMOD " has index %d, exposes %d out of %d devices!\n", - DPxPTR(RTL.LibraryHandler.get()), DeviceOffset, NumberOfUserDevices, - RTL.number_of_devices()); + DP("Plugin has index %d, exposes %d out of %d devices!\n", DeviceOffset, + NumberOfUserDevices, RTL.number_of_devices()); } void PluginManager::initAllPlugins() { - for (auto &R : PluginAdaptors) + for (auto &R : Plugins) initDevices(*R); } @@ -216,19 +169,22 @@ void PluginManager::registerLib(__tgt_bin_desc *Desc) { // Obtain the image and information that was previously extracted. __tgt_device_image *Img = &DI.getExecutableImage(); - PluginAdaptorTy *FoundRTL = nullptr; + GenericPluginTy *FoundRTL = nullptr; // Scan the RTLs that have associated images until we find one that supports // the current image. - for (auto &R : PM->pluginAdaptors()) { + for (auto &R : PM->plugins()) { + if (!R.number_of_devices()) + continue; + if (!R.is_valid_binary(Img)) { DP("Image " DPxMOD " is NOT compatible with RTL %s!\n", - DPxPTR(Img->ImageStart), R.Name.c_str()); + DPxPTR(Img->ImageStart), R.getName()); continue; } DP("Image " DPxMOD " is compatible with RTL %s!\n", - DPxPTR(Img->ImageStart), R.Name.c_str()); + DPxPTR(Img->ImageStart), R.getName()); PM->initDevices(R); @@ -247,7 +203,7 @@ void PluginManager::registerLib(__tgt_bin_desc *Desc) { (PM->HostEntriesBeginToTransTable)[Desc->HostEntriesBegin]; DP("Registering image " DPxMOD " with RTL %s!\n", DPxPTR(Img->ImageStart), - R.Name.c_str()); + R.getName()); registerImageIntoTranslationTable(TransTable, PM->DeviceOffsets[&R], PM->DeviceUsed[&R], Img); @@ -282,11 +238,11 @@ void PluginManager::unregisterLib(__tgt_bin_desc *Desc) { // Obtain the image and information that was previously extracted. __tgt_device_image *Img = &DI.getExecutableImage(); - PluginAdaptorTy *FoundRTL = NULL; + GenericPluginTy *FoundRTL = NULL; // Scan the RTLs that have associated images until we find one that supports // the current image. We only need to scan RTLs that are already being used. - for (auto &R : PM->pluginAdaptors()) { + for (auto &R : PM->plugins()) { if (!DeviceOffsets.contains(&R)) continue; @@ -296,8 +252,7 @@ void PluginManager::unregisterLib(__tgt_bin_desc *Desc) { FoundRTL = &R; - DP("Unregistered image " DPxMOD " from RTL " DPxMOD "!\n", - DPxPTR(Img->ImageStart), DPxPTR(R.LibraryHandler.get())); + DP("Unregistered image " DPxMOD " from RTL\n", DPxPTR(Img->ImageStart)); break; } diff --git a/offload/src/device.cpp b/offload/src/device.cpp index 44a2facc8d3d..749b4c567f8e 100644 --- a/offload/src/device.cpp +++ b/offload/src/device.cpp @@ -64,7 +64,7 @@ int HostDataToTargetTy::addEventIfNecessary(DeviceTy &Device, return OFFLOAD_SUCCESS; } -DeviceTy::DeviceTy(PluginAdaptorTy *RTL, int32_t DeviceID, int32_t RTLDeviceID) +DeviceTy::DeviceTy(GenericPluginTy *RTL, int32_t DeviceID, int32_t RTLDeviceID) : DeviceID(DeviceID), RTL(RTL), RTLDeviceID(RTLDeviceID), MappingInfo(*this) {} @@ -192,7 +192,6 @@ int32_t DeviceTy::dataExchange(void *SrcPtr, DeviceTy &DstDev, void *DstPtr, RTLDeviceID, SrcPtr, DstDev.RTLDeviceID, DstPtr, Size, /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) if (!AsyncInfo) { - assert(RTL->data_exchange && "RTL->data_exchange is nullptr"); return RTL->data_exchange(RTLDeviceID, SrcPtr, DstDev.RTLDeviceID, DstPtr, Size); } diff --git a/offload/src/interface.cpp b/offload/src/interface.cpp index 557703632c62..763b051cc6d7 100644 --- a/offload/src/interface.cpp +++ b/offload/src/interface.cpp @@ -456,8 +456,6 @@ EXTERN void __tgt_set_info_flag(uint32_t NewInfoLevel) { assert(PM && "Runtime not initialized"); std::atomic &InfoLevel = getInfoLevelInternal(); InfoLevel.store(NewInfoLevel); - for (auto &R : PM->pluginAdaptors()) - R.set_info_flag(NewInfoLevel); } EXTERN int __tgt_print_device_info(int64_t DeviceId) { diff --git a/offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp b/offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp index 761e04e4c7bb..1e9a6a84d805 100644 --- a/offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp +++ b/offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp @@ -13,8 +13,6 @@ #include "omptarget.h" -#include "Shared/PluginAPI.h" - #include "llvm/Support/CommandLine.h" #include "llvm/Support/JSON.h" #include "llvm/Support/MemoryBuffer.h" diff --git a/offload/unittests/Plugins/NextgenPluginsTest.cpp b/offload/unittests/Plugins/NextgenPluginsTest.cpp index 635bd1637c90..479b3f614aed 100644 --- a/offload/unittests/Plugins/NextgenPluginsTest.cpp +++ b/offload/unittests/Plugins/NextgenPluginsTest.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// -#include "Shared/PluginAPI.h" #include "omptarget.h" #include "gtest/gtest.h" -- GitLab From b903badd73a2467fdd4e363231f2bf9b0704b546 Mon Sep 17 00:00:00 2001 From: Pavel Labath Date: Thu, 9 May 2024 11:29:07 +0000 Subject: [PATCH 128/328] [lldb] Attempt to fix signal-in-leaf-function-aarch64 on darwin Convert settings set EXC_BAD_INSTRUCTION to SIGILL so we get uniform behavior (and can resume the inferior). Fix a "omitting the parameter name in a function definition is a C23 extension" warning as a drive-by. --- .../test/Shell/Unwind/Inputs/signal-in-leaf-function-aarch64.c | 2 +- lldb/test/Shell/Unwind/signal-in-leaf-function-aarch64.test | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/lldb/test/Shell/Unwind/Inputs/signal-in-leaf-function-aarch64.c b/lldb/test/Shell/Unwind/Inputs/signal-in-leaf-function-aarch64.c index 9a751330623f..fe020affcad0 100644 --- a/lldb/test/Shell/Unwind/Inputs/signal-in-leaf-function-aarch64.c +++ b/lldb/test/Shell/Unwind/Inputs/signal-in-leaf-function-aarch64.c @@ -7,7 +7,7 @@ int __attribute__((naked)) signal_generating_add(int a, int b) { "ret"); } -void sigill_handler(int) { _exit(0); } +void sigill_handler(int signo) { _exit(0); } int main() { signal(SIGILL, sigill_handler); diff --git a/lldb/test/Shell/Unwind/signal-in-leaf-function-aarch64.test b/lldb/test/Shell/Unwind/signal-in-leaf-function-aarch64.test index 0580d0cf734a..09f17c174bbf 100644 --- a/lldb/test/Shell/Unwind/signal-in-leaf-function-aarch64.test +++ b/lldb/test/Shell/Unwind/signal-in-leaf-function-aarch64.test @@ -4,6 +4,9 @@ # RUN: %clang_host %S/Inputs/signal-in-leaf-function-aarch64.c -o %t # RUN: %lldb -s %s -o exit %t | FileCheck %s +# Convert EXC_BAD_INSTRUCTION to SIGILL on darwin +settings set platform.plugin.darwin.ignored-exceptions EXC_BAD_INSTRUCTION + breakpoint set -n sigill_handler # CHECK: Breakpoint 1: where = {{.*}}`sigill_handler -- GitLab From b452b34932a3f0450026c40fb797698a6671f9a7 Mon Sep 17 00:00:00 2001 From: Shan Huang <52285902006@stu.ecnu.edu.cn> Date: Thu, 9 May 2024 19:58:53 +0800 Subject: [PATCH 129/328] [DebugInfo][IndVarSimplify] Fix missing debug location updates (#91443) Adds debug location updates for the newly created `phi`, `add`, `icmp` and `sitofp` instructions in `IndVarSimplify`. Fixes #91436 --- llvm/lib/Transforms/Scalar/IndVarSimplify.cpp | 10 ++- .../IndVarSimplify/preserving-debugloc.ll | 61 +++++++++++++++++++ 2 files changed, 68 insertions(+), 3 deletions(-) create mode 100644 llvm/test/Transforms/IndVarSimplify/preserving-debugloc.ll diff --git a/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp b/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp index ba392e187b8b..dd7c89034ca0 100644 --- a/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp +++ b/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp @@ -359,15 +359,18 @@ bool IndVarSimplify::handleFloatingPointIV(Loop *L, PHINode *PN) { PHINode::Create(Int32Ty, 2, PN->getName() + ".int", PN->getIterator()); NewPHI->addIncoming(ConstantInt::get(Int32Ty, InitValue), PN->getIncomingBlock(IncomingEdge)); + NewPHI->setDebugLoc(PN->getDebugLoc()); - Value *NewAdd = + Instruction *NewAdd = BinaryOperator::CreateAdd(NewPHI, ConstantInt::get(Int32Ty, IncValue), Incr->getName() + ".int", Incr->getIterator()); + NewAdd->setDebugLoc(Incr->getDebugLoc()); NewPHI->addIncoming(NewAdd, PN->getIncomingBlock(BackEdge)); ICmpInst *NewCompare = new ICmpInst(TheBr->getIterator(), NewPred, NewAdd, ConstantInt::get(Int32Ty, ExitValue), Compare->getName()); + NewCompare->setDebugLoc(Compare->getDebugLoc()); // In the following deletions, PN may become dead and may be deleted. // Use a WeakTrackingVH to observe whether this happens. @@ -391,8 +394,9 @@ bool IndVarSimplify::handleFloatingPointIV(Loop *L, PHINode *PN) { // We give preference to sitofp over uitofp because it is faster on most // platforms. if (WeakPH) { - Value *Conv = new SIToFPInst(NewPHI, PN->getType(), "indvar.conv", - PN->getParent()->getFirstInsertionPt()); + Instruction *Conv = new SIToFPInst(NewPHI, PN->getType(), "indvar.conv", + PN->getParent()->getFirstInsertionPt()); + Conv->setDebugLoc(PN->getDebugLoc()); PN->replaceAllUsesWith(Conv); RecursivelyDeleteTriviallyDeadInstructions(PN, TLI, MSSAU.get()); } diff --git a/llvm/test/Transforms/IndVarSimplify/preserving-debugloc.ll b/llvm/test/Transforms/IndVarSimplify/preserving-debugloc.ll new file mode 100644 index 000000000000..7d23c8697efa --- /dev/null +++ b/llvm/test/Transforms/IndVarSimplify/preserving-debugloc.ll @@ -0,0 +1,61 @@ +; RUN: opt < %s -passes=indvars -S | FileCheck %s + +; This testcase checks the preservation of debug locations of newly created +; phi, sitofp, add and icmp instructions in IndVarSimplify Pass. + +define void @test1() !dbg !5 { +; CHECK-LABEL: @test1( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[BB:%.*]], !dbg +; CHECK: bb: +; CHECK: [[IV_INT:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[DOTINT:%.*]], [[BB]] ], !dbg ![[DBG1:[0-9]+]] +; CHECK: [[INDVAR_CONV:%.*]] = sitofp i32 [[IV_INT]] to double, !dbg ![[DBG1]] +; CHECK: [[DOTINT]] = add nuw nsw i32 [[IV_INT]], 1, !dbg ![[DBG2:[0-9]+]] +; CHECK: [[TMP1:%.*]] = icmp ult i32 [[DOTINT]], 10000, !dbg ![[DBG3:[0-9]+]] +; CHECK: ![[DBG1]] = !DILocation(line: 2 +; CHECK: ![[DBG2]] = !DILocation(line: 4 +; CHECK: ![[DBG3]] = !DILocation(line: 5 +; +entry: + br label %bb, !dbg !16 + +bb: ; preds = %bb, %entry + %iv = phi double [ 0.000000e+00, %entry ], [ %1, %bb ], !dbg !17 + %0 = tail call i32 @foo(double %iv), !dbg !18 + %1 = fadd double %iv, 1.000000e+00, !dbg !19 + %2 = fcmp olt double %1, 1.000000e+04, !dbg !20 + br i1 %2, label %bb, label %return, !dbg !21 + +return: ; preds = %bb + ret void, !dbg !22 +} + +declare i32 @foo(double) + +!llvm.dbg.cu = !{!0} +!llvm.debugify = !{!2, !3} +!llvm.module.flags = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) +!1 = !DIFile(filename: "indvars-preserving.ll", directory: "/") +!2 = !{i32 7} +!3 = !{i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = distinct !DISubprogram(name: "test1", linkageName: "test1", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) +!6 = !DISubroutineType(types: !7) +!7 = !{} +!8 = !{!9, !11, !13, !14} +!9 = !DILocalVariable(name: "1", scope: !5, file: !1, line: 2, type: !10) +!10 = !DIBasicType(name: "ty64", size: 64, encoding: DW_ATE_unsigned) +!11 = !DILocalVariable(name: "2", scope: !5, file: !1, line: 3, type: !12) +!12 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned) +!13 = !DILocalVariable(name: "3", scope: !5, file: !1, line: 4, type: !10) +!14 = !DILocalVariable(name: "4", scope: !5, file: !1, line: 5, type: !15) +!15 = !DIBasicType(name: "ty8", size: 8, encoding: DW_ATE_unsigned) +!16 = !DILocation(line: 1, column: 1, scope: !5) +!17 = !DILocation(line: 2, column: 1, scope: !5) +!18 = !DILocation(line: 3, column: 1, scope: !5) +!19 = !DILocation(line: 4, column: 1, scope: !5) +!20 = !DILocation(line: 5, column: 1, scope: !5) +!21 = !DILocation(line: 6, column: 1, scope: !5) +!22 = !DILocation(line: 7, column: 1, scope: !5) -- GitLab From a7ee81e8279e0bf6e05617a4a638e5f2f8e45022 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Thu, 9 May 2024 06:59:45 -0500 Subject: [PATCH 130/328] [libc] Remove unused variable causing build errors --- libc/src/__support/CPP/mutex.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libc/src/__support/CPP/mutex.h b/libc/src/__support/CPP/mutex.h index c25c1155b766..345816fae233 100644 --- a/libc/src/__support/CPP/mutex.h +++ b/libc/src/__support/CPP/mutex.h @@ -31,7 +31,7 @@ public: // Acquires ownership of the mutex object `m` without attempting to lock // it. The behavior is undefined if the current thread does not hold the // lock on `m`. Does not call `m.lock()` upon resource acquisition. - lock_guard(MutexType &m, adopt_lock_t t) : mutex(m) {} + lock_guard(MutexType &m, adopt_lock_t /* t */) : mutex(m) {} ~lock_guard() { mutex.unlock(); } -- GitLab From d86b68afd7f0d7684adc312bcdc87f9027d0d896 Mon Sep 17 00:00:00 2001 From: Janek van Oirschot <5994977+JanekvO@users.noreply.github.com> Date: Thu, 9 May 2024 13:02:32 +0100 Subject: [PATCH 131/328] MCExpr-ify SIProgramInfo (#88257) Convert members in SIProgramInfo affected by variables provided by AMDGPUResourceUsageAnalysis into MCExprs. --- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 421 ++++++++++++------ llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h | 2 + .../AMDGPU/AMDGPUHSAMetadataStreamer.cpp | 30 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 25 +- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 6 +- .../AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp | 201 +++++++++ .../Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h | 42 +- llvm/lib/Target/AMDGPU/SIProgramInfo.cpp | 207 +++++++-- llvm/lib/Target/AMDGPU/SIProgramInfo.h | 49 +- .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 39 +- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 12 + llvm/test/MC/AMDGPU/alignto_mcexpr.s | 15 + llvm/test/MC/AMDGPU/extrasgprs_mcexpr.s | 31 ++ llvm/test/MC/AMDGPU/occupancy_mcexpr.s | 61 +++ llvm/test/MC/AMDGPU/totalnumvgpr_mcexpr.s | 26 ++ llvm/unittests/MC/AMDGPU/CMakeLists.txt | 10 +- .../MC/AMDGPU/SIProgramInfoMCExprs.cpp | 81 ++++ 17 files changed, 1040 insertions(+), 218 deletions(-) create mode 100644 llvm/test/MC/AMDGPU/alignto_mcexpr.s create mode 100644 llvm/test/MC/AMDGPU/extrasgprs_mcexpr.s create mode 100644 llvm/test/MC/AMDGPU/occupancy_mcexpr.s create mode 100644 llvm/test/MC/AMDGPU/totalnumvgpr_mcexpr.s create mode 100644 llvm/unittests/MC/AMDGPU/SIProgramInfoMCExprs.cpp diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 89a5ceac629b..de81904143b7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -22,6 +22,7 @@ #include "AMDKernelCodeT.h" #include "GCNSubtarget.h" #include "MCTargetDesc/AMDGPUInstPrinter.h" +#include "MCTargetDesc/AMDGPUMCExpr.h" #include "MCTargetDesc/AMDGPUMCKernelDescriptor.h" #include "MCTargetDesc/AMDGPUTargetStreamer.h" #include "R600AsmPrinter.h" @@ -134,6 +135,15 @@ void AMDGPUAsmPrinter::initTargetStreamer(Module &M) { getTargetStreamer()->getPALMetadata()->readFromIR(M); } +uint64_t AMDGPUAsmPrinter::getMCExprValue(const MCExpr *Value, MCContext &Ctx) { + int64_t Val; + if (!Value->evaluateAsAbsolute(Val)) { + Ctx.reportError(SMLoc(), "could not resolve expression when required."); + return 0; + } + return static_cast(Val); +} + void AMDGPUAsmPrinter::emitEndOfAsmFile(Module &M) { // Init target streamer if it has not yet happened if (!IsTargetStreamerInitialized) @@ -237,12 +247,14 @@ void AMDGPUAsmPrinter::emitFunctionBodyEnd() { getNameWithPrefix(KernelName, &MF->getFunction()); getTargetStreamer()->EmitAmdhsaKernelDescriptor( STM, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo), - CurrentProgramInfo.NumVGPRsForWavesPerEU, - CurrentProgramInfo.NumSGPRsForWavesPerEU - + getMCExprValue(CurrentProgramInfo.NumVGPRsForWavesPerEU, Context), + getMCExprValue(CurrentProgramInfo.NumSGPRsForWavesPerEU, Context) - IsaInfo::getNumExtraSGPRs( - &STM, CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed, + &STM, getMCExprValue(CurrentProgramInfo.VCCUsed, Context), + getMCExprValue(CurrentProgramInfo.FlatUsed, Context), getTargetStreamer()->getTargetID()->isXnackOnOrAny()), - CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed); + getMCExprValue(CurrentProgramInfo.VCCUsed, Context), + getMCExprValue(CurrentProgramInfo.FlatUsed, Context)); Streamer.popSection(); } @@ -422,7 +434,7 @@ uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties( amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32; } - if (CurrentProgramInfo.DynamicCallStack && + if (getMCExprValue(CurrentProgramInfo.DynamicCallStack, MF.getContext()) && CodeObjectVersion >= AMDGPU::AMDHSA_COV5) KernelCodeProperties |= amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK; @@ -439,29 +451,22 @@ AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(const MachineFunction &MF, MCKernelDescriptor KernelDescriptor; - assert(isUInt<32>(PI.ScratchSize)); - assert(isUInt<32>(PI.getComputePGMRSrc1(STM))); - assert(isUInt<32>(PI.getComputePGMRSrc2())); - KernelDescriptor.group_segment_fixed_size = MCConstantExpr::create(PI.LDSSize, Ctx); - KernelDescriptor.private_segment_fixed_size = - MCConstantExpr::create(PI.ScratchSize, Ctx); + KernelDescriptor.private_segment_fixed_size = PI.ScratchSize; Align MaxKernArgAlign; KernelDescriptor.kernarg_size = MCConstantExpr::create( STM.getKernArgSegmentSize(F, MaxKernArgAlign), Ctx); - KernelDescriptor.compute_pgm_rsrc1 = - MCConstantExpr::create(PI.getComputePGMRSrc1(STM), Ctx); - KernelDescriptor.compute_pgm_rsrc2 = - MCConstantExpr::create(PI.getComputePGMRSrc2(), Ctx); + KernelDescriptor.compute_pgm_rsrc1 = PI.getComputePGMRSrc1(STM, Ctx); + KernelDescriptor.compute_pgm_rsrc2 = PI.getComputePGMRSrc2(Ctx); KernelDescriptor.kernel_code_properties = MCConstantExpr::create(getAmdhsaKernelCodeProperties(MF), Ctx); - assert(STM.hasGFX90AInsts() || CurrentProgramInfo.ComputePGMRSrc3GFX90A == 0); - KernelDescriptor.compute_pgm_rsrc3 = MCConstantExpr::create( - STM.hasGFX90AInsts() ? CurrentProgramInfo.ComputePGMRSrc3GFX90A : 0, Ctx); + assert(STM.hasGFX90AInsts() || + getMCExprValue(CurrentProgramInfo.ComputePGMRSrc3GFX90A, Ctx) == 0); + KernelDescriptor.compute_pgm_rsrc3 = CurrentProgramInfo.ComputePGMRSrc3GFX90A; KernelDescriptor.kernarg_preload = MCConstantExpr::create( AMDGPU::hasKernargPreload(STM) ? Info->getNumKernargPreloadedSGPRs() : 0, @@ -477,9 +482,10 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { initTargetStreamer(*MF.getFunction().getParent()); ResourceUsage = &getAnalysis(); - CurrentProgramInfo = SIProgramInfo(); + CurrentProgramInfo.reset(MF); const AMDGPUMachineFunction *MFI = MF.getInfo(); + MCContext &Ctx = MF.getContext(); // The starting address of all shader programs must be 256 bytes aligned. // Regular functions just need the basic required instruction alignment. @@ -550,11 +556,13 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { OutStreamer->emitRawComment(" Kernel info:", false); emitCommonFunctionComments( - CurrentProgramInfo.NumArchVGPR, - STM.hasMAIInsts() ? CurrentProgramInfo.NumAccVGPR + getMCExprValue(CurrentProgramInfo.NumArchVGPR, Ctx), + STM.hasMAIInsts() ? getMCExprValue(CurrentProgramInfo.NumAccVGPR, Ctx) : std::optional(), - CurrentProgramInfo.NumVGPR, CurrentProgramInfo.NumSGPR, - CurrentProgramInfo.ScratchSize, getFunctionCodeSize(MF), MFI); + getMCExprValue(CurrentProgramInfo.NumVGPR, Ctx), + getMCExprValue(CurrentProgramInfo.NumSGPR, Ctx), + getMCExprValue(CurrentProgramInfo.ScratchSize, Ctx), + getFunctionCodeSize(MF), MFI); OutStreamer->emitRawComment( " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false); @@ -565,32 +573,44 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { " bytes/workgroup (compile time only)", false); OutStreamer->emitRawComment( - " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false); + " SGPRBlocks: " + + Twine(getMCExprValue(CurrentProgramInfo.SGPRBlocks, Ctx)), + false); OutStreamer->emitRawComment( - " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false); + " VGPRBlocks: " + + Twine(getMCExprValue(CurrentProgramInfo.VGPRBlocks, Ctx)), + false); OutStreamer->emitRawComment( - " NumSGPRsForWavesPerEU: " + - Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false); + " NumSGPRsForWavesPerEU: " + + Twine( + getMCExprValue(CurrentProgramInfo.NumSGPRsForWavesPerEU, Ctx)), + false); OutStreamer->emitRawComment( - " NumVGPRsForWavesPerEU: " + - Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false); + " NumVGPRsForWavesPerEU: " + + Twine( + getMCExprValue(CurrentProgramInfo.NumVGPRsForWavesPerEU, Ctx)), + false); if (STM.hasGFX90AInsts()) OutStreamer->emitRawComment( - " AccumOffset: " + - Twine((CurrentProgramInfo.AccumOffset + 1) * 4), false); + " AccumOffset: " + + Twine((getMCExprValue(CurrentProgramInfo.AccumOffset, Ctx) + 1) * + 4), + false); OutStreamer->emitRawComment( - " Occupancy: " + - Twine(CurrentProgramInfo.Occupancy), false); + " Occupancy: " + + Twine(getMCExprValue(CurrentProgramInfo.Occupancy, Ctx)), + false); OutStreamer->emitRawComment( " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false); - OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:SCRATCH_EN: " + - Twine(CurrentProgramInfo.ScratchEnable), - false); + OutStreamer->emitRawComment( + " COMPUTE_PGM_RSRC2:SCRATCH_EN: " + + Twine(getMCExprValue(CurrentProgramInfo.ScratchEnable, Ctx)), + false); OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " + Twine(CurrentProgramInfo.UserSGPR), false); @@ -611,18 +631,20 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { false); assert(STM.hasGFX90AInsts() || - CurrentProgramInfo.ComputePGMRSrc3GFX90A == 0); + getMCExprValue(CurrentProgramInfo.ComputePGMRSrc3GFX90A, Ctx) == 0); if (STM.hasGFX90AInsts()) { OutStreamer->emitRawComment( - " COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: " + - Twine((AMDHSA_BITS_GET(CurrentProgramInfo.ComputePGMRSrc3GFX90A, - amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET))), - false); + " COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: " + + Twine((AMDHSA_BITS_GET( + getMCExprValue(CurrentProgramInfo.ComputePGMRSrc3GFX90A, Ctx), + amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET))), + false); OutStreamer->emitRawComment( - " COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: " + - Twine((AMDHSA_BITS_GET(CurrentProgramInfo.ComputePGMRSrc3GFX90A, - amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT))), - false); + " COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: " + + Twine((AMDHSA_BITS_GET( + getMCExprValue(CurrentProgramInfo.ComputePGMRSrc3GFX90A, Ctx), + amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT))), + false); } } @@ -702,23 +724,40 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, const AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo &Info = ResourceUsage->getResourceInfo(&MF.getFunction()); const GCNSubtarget &STM = MF.getSubtarget(); + MCContext &Ctx = MF.getContext(); + + auto CreateExpr = [&Ctx](int64_t Value) { + return MCConstantExpr::create(Value, Ctx); + }; - ProgInfo.NumArchVGPR = Info.NumVGPR; - ProgInfo.NumAccVGPR = Info.NumAGPR; - ProgInfo.NumVGPR = Info.getTotalNumVGPRs(STM); - ProgInfo.AccumOffset = alignTo(std::max(1, Info.NumVGPR), 4) / 4 - 1; + auto TryGetMCExprValue = [&Ctx](const MCExpr *Value, uint64_t &Res) -> bool { + int64_t Val; + if (Value->evaluateAsAbsolute(Val)) { + Res = Val; + return true; + } + return false; + }; + + ProgInfo.NumArchVGPR = CreateExpr(Info.NumVGPR); + ProgInfo.NumAccVGPR = CreateExpr(Info.NumAGPR); + ProgInfo.NumVGPR = CreateExpr(Info.getTotalNumVGPRs(STM)); + ProgInfo.AccumOffset = + CreateExpr(alignTo(std::max(1, Info.NumVGPR), 4) / 4 - 1); ProgInfo.TgSplit = STM.isTgSplitEnabled(); - ProgInfo.NumSGPR = Info.NumExplicitSGPR; - ProgInfo.ScratchSize = Info.PrivateSegmentSize; - ProgInfo.VCCUsed = Info.UsesVCC; - ProgInfo.FlatUsed = Info.UsesFlatScratch; - ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion; + ProgInfo.NumSGPR = CreateExpr(Info.NumExplicitSGPR); + ProgInfo.ScratchSize = CreateExpr(Info.PrivateSegmentSize); + ProgInfo.VCCUsed = CreateExpr(Info.UsesVCC); + ProgInfo.FlatUsed = CreateExpr(Info.UsesFlatScratch); + ProgInfo.DynamicCallStack = + CreateExpr(Info.HasDynamicallySizedStack || Info.HasRecursion); const uint64_t MaxScratchPerWorkitem = STM.getMaxWaveScratchSize() / STM.getWavefrontSize(); - if (ProgInfo.ScratchSize > MaxScratchPerWorkitem) { - DiagnosticInfoStackSize DiagStackSize(MF.getFunction(), - ProgInfo.ScratchSize, + uint64_t ScratchSize; + if (TryGetMCExprValue(ProgInfo.ScratchSize, ScratchSize) && + ScratchSize > MaxScratchPerWorkitem) { + DiagnosticInfoStackSize DiagStackSize(MF.getFunction(), ScratchSize, MaxScratchPerWorkitem, DS_Error); MF.getFunction().getContext().diagnose(DiagStackSize); } @@ -728,27 +767,29 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, // The calculations related to SGPR/VGPR blocks are // duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be // unified. - unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs( - &STM, ProgInfo.VCCUsed, ProgInfo.FlatUsed, - getTargetStreamer()->getTargetID()->isXnackOnOrAny()); + const MCExpr *ExtraSGPRs = AMDGPUVariadicMCExpr::createExtraSGPRs( + ProgInfo.VCCUsed, ProgInfo.FlatUsed, + getTargetStreamer()->getTargetID()->isXnackOnOrAny(), Ctx); // Check the addressable register limit before we add ExtraSGPRs. if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS && !STM.hasSGPRInitBug()) { unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs(); - if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) { + uint64_t NumSgpr; + if (TryGetMCExprValue(ProgInfo.NumSGPR, NumSgpr) && + NumSgpr > MaxAddressableNumSGPRs) { // This can happen due to a compiler bug or when using inline asm. LLVMContext &Ctx = MF.getFunction().getContext(); DiagnosticInfoResourceLimit Diag( - MF.getFunction(), "addressable scalar registers", ProgInfo.NumSGPR, + MF.getFunction(), "addressable scalar registers", NumSgpr, MaxAddressableNumSGPRs, DS_Error, DK_ResourceLimit); Ctx.diagnose(Diag); - ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1; + ProgInfo.NumSGPR = CreateExpr(MaxAddressableNumSGPRs - 1); } } // Account for extra SGPRs and VGPRs reserved for debugger use. - ProgInfo.NumSGPR += ExtraSGPRs; + ProgInfo.NumSGPR = MCBinaryExpr::createAdd(ProgInfo.NumSGPR, ExtraSGPRs, Ctx); const Function &F = MF.getFunction(); @@ -819,40 +860,51 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, } } } - ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR); - ProgInfo.NumArchVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR); - ProgInfo.NumVGPR = - Info.getTotalNumVGPRs(STM, Info.NumAGPR, ProgInfo.NumArchVGPR); + ProgInfo.NumSGPR = AMDGPUVariadicMCExpr::createMax( + {ProgInfo.NumSGPR, CreateExpr(WaveDispatchNumSGPR)}, Ctx); + + ProgInfo.NumArchVGPR = AMDGPUVariadicMCExpr::createMax( + {ProgInfo.NumVGPR, CreateExpr(WaveDispatchNumVGPR)}, Ctx); + + ProgInfo.NumVGPR = AMDGPUVariadicMCExpr::createTotalNumVGPR( + ProgInfo.NumAccVGPR, ProgInfo.NumArchVGPR, Ctx); } // Adjust number of registers used to meet default/requested minimum/maximum // number of waves per execution unit request. - ProgInfo.NumSGPRsForWavesPerEU = std::max( - std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU())); - ProgInfo.NumVGPRsForWavesPerEU = std::max( - std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU())); + unsigned MaxWaves = MFI->getMaxWavesPerEU(); + ProgInfo.NumSGPRsForWavesPerEU = AMDGPUVariadicMCExpr::createMax( + {ProgInfo.NumSGPR, CreateExpr(1ul), + CreateExpr(STM.getMinNumSGPRs(MaxWaves))}, + Ctx); + ProgInfo.NumVGPRsForWavesPerEU = AMDGPUVariadicMCExpr::createMax( + {ProgInfo.NumVGPR, CreateExpr(1ul), + CreateExpr(STM.getMinNumVGPRs(MaxWaves))}, + Ctx); if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS || STM.hasSGPRInitBug()) { unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs(); - if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) { + uint64_t NumSgpr; + if (TryGetMCExprValue(ProgInfo.NumSGPR, NumSgpr) && + NumSgpr > MaxAddressableNumSGPRs) { // This can happen due to a compiler bug or when using inline asm to use // the registers which are usually reserved for vcc etc. LLVMContext &Ctx = MF.getFunction().getContext(); DiagnosticInfoResourceLimit Diag(MF.getFunction(), "scalar registers", - ProgInfo.NumSGPR, MaxAddressableNumSGPRs, + NumSgpr, MaxAddressableNumSGPRs, DS_Error, DK_ResourceLimit); Ctx.diagnose(Diag); - ProgInfo.NumSGPR = MaxAddressableNumSGPRs; - ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs; + ProgInfo.NumSGPR = CreateExpr(MaxAddressableNumSGPRs); + ProgInfo.NumSGPRsForWavesPerEU = CreateExpr(MaxAddressableNumSGPRs); } } if (STM.hasSGPRInitBug()) { ProgInfo.NumSGPR = - AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG; + CreateExpr(AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG); ProgInfo.NumSGPRsForWavesPerEU = - AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG; + CreateExpr(AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG); } if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) { @@ -871,11 +923,26 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, STM.getAddressableLocalMemorySize(), DS_Error); Ctx.diagnose(Diag); } + // The MCExpr equivalent of getNumSGPRBlocks/getNumVGPRBlocks: + // (alignTo(max(1u, NumGPR), GPREncodingGranule) / GPREncodingGranule) - 1 + auto GetNumGPRBlocks = [&CreateExpr, &Ctx](const MCExpr *NumGPR, + unsigned Granule) { + const MCExpr *OneConst = CreateExpr(1ul); + const MCExpr *GranuleConst = CreateExpr(Granule); + const MCExpr *MaxNumGPR = + AMDGPUVariadicMCExpr::createMax({NumGPR, OneConst}, Ctx); + const MCExpr *AlignToGPR = + AMDGPUVariadicMCExpr::createAlignTo(MaxNumGPR, GranuleConst, Ctx); + const MCExpr *DivGPR = + MCBinaryExpr::createDiv(AlignToGPR, GranuleConst, Ctx); + const MCExpr *SubGPR = MCBinaryExpr::createSub(DivGPR, OneConst, Ctx); + return SubGPR; + }; - ProgInfo.SGPRBlocks = IsaInfo::getNumSGPRBlocks( - &STM, ProgInfo.NumSGPRsForWavesPerEU); - ProgInfo.VGPRBlocks = - IsaInfo::getEncodedNumVGPRBlocks(&STM, ProgInfo.NumVGPRsForWavesPerEU); + ProgInfo.SGPRBlocks = GetNumGPRBlocks(ProgInfo.NumSGPRsForWavesPerEU, + IsaInfo::getSGPREncodingGranule(&STM)); + ProgInfo.VGPRBlocks = GetNumGPRBlocks(ProgInfo.NumVGPRsForWavesPerEU, + IsaInfo::getVGPREncodingGranule(&STM)); const SIModeRegisterDefaults Mode = MFI->getMode(); @@ -904,14 +971,23 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, ProgInfo.LDSBlocks = alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift; + // The MCExpr equivalent of divideCeil. + auto DivideCeil = [&Ctx](const MCExpr *Numerator, const MCExpr *Denominator) { + const MCExpr *Ceil = + AMDGPUVariadicMCExpr::createAlignTo(Numerator, Denominator, Ctx); + return MCBinaryExpr::createDiv(Ceil, Denominator, Ctx); + }; + // Scratch is allocated in 64-dword or 256-dword blocks. unsigned ScratchAlignShift = STM.getGeneration() >= AMDGPUSubtarget::GFX11 ? 8 : 10; // We need to program the hardware with the amount of scratch memory that // is used by the entire wave. ProgInfo.ScratchSize is the amount of // scratch memory used per thread. - ProgInfo.ScratchBlocks = divideCeil( - ProgInfo.ScratchSize * STM.getWavefrontSize(), 1ULL << ScratchAlignShift); + ProgInfo.ScratchBlocks = DivideCeil( + MCBinaryExpr::createMul(ProgInfo.ScratchSize, + CreateExpr(STM.getWavefrontSize()), Ctx), + CreateExpr(1ULL << ScratchAlignShift)); if (getIsaVersion(getGlobalSTI()->getCPU()).Major >= 10) { ProgInfo.WgpMode = STM.isCuModeEnabled() ? 0 : 1; @@ -930,8 +1006,11 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, // anything to disable it if we know the stack isn't used here. We may still // have emitted code reading it to initialize scratch, but if that's unused // reading garbage should be OK. - ProgInfo.ScratchEnable = - ProgInfo.ScratchBlocks > 0 || ProgInfo.DynamicCallStack; + ProgInfo.ScratchEnable = MCBinaryExpr::createLOr( + MCBinaryExpr::createGT(ProgInfo.ScratchBlocks, + MCConstantExpr::create(0, Ctx), Ctx), + ProgInfo.DynamicCallStack, Ctx); + ProgInfo.UserSGPR = MFI->getNumUserSGPRs(); // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP. ProgInfo.TrapHandlerEnable = @@ -947,26 +1026,41 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, ProgInfo.EXCPEnable = 0; if (STM.hasGFX90AInsts()) { - AMDHSA_BITS_SET(ProgInfo.ComputePGMRSrc3GFX90A, - amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET, - ProgInfo.AccumOffset); - AMDHSA_BITS_SET(ProgInfo.ComputePGMRSrc3GFX90A, - amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, - ProgInfo.TgSplit); + // return ((Dst & ~Mask) | (Value << Shift)) + auto SetBits = [&Ctx](const MCExpr *Dst, const MCExpr *Value, uint32_t Mask, + uint32_t Shift) { + auto Shft = MCConstantExpr::create(Shift, Ctx); + auto Msk = MCConstantExpr::create(Mask, Ctx); + Dst = MCBinaryExpr::createAnd(Dst, MCUnaryExpr::createNot(Msk, Ctx), Ctx); + Dst = MCBinaryExpr::createOr( + Dst, MCBinaryExpr::createShl(Value, Shft, Ctx), Ctx); + return Dst; + }; + + ProgInfo.ComputePGMRSrc3GFX90A = + SetBits(ProgInfo.ComputePGMRSrc3GFX90A, ProgInfo.AccumOffset, + amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET, + amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET_SHIFT); + ProgInfo.ComputePGMRSrc3GFX90A = + SetBits(ProgInfo.ComputePGMRSrc3GFX90A, CreateExpr(ProgInfo.TgSplit), + amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, + amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT); } - ProgInfo.Occupancy = STM.computeOccupancy(MF.getFunction(), ProgInfo.LDSSize, - ProgInfo.NumSGPRsForWavesPerEU, - ProgInfo.NumVGPRsForWavesPerEU); + ProgInfo.Occupancy = AMDGPUVariadicMCExpr::createOccupancy( + STM.computeOccupancy(F, ProgInfo.LDSSize), ProgInfo.NumSGPRsForWavesPerEU, + ProgInfo.NumVGPRsForWavesPerEU, STM, Ctx); + const auto [MinWEU, MaxWEU] = AMDGPU::getIntegerPairAttribute(F, "amdgpu-waves-per-eu", {0, 0}, true); - if (ProgInfo.Occupancy < MinWEU) { + uint64_t Occupancy; + if (TryGetMCExprValue(ProgInfo.Occupancy, Occupancy) && Occupancy < MinWEU) { DiagnosticInfoOptimizationFailure Diag( F, F.getSubprogram(), "failed to meet occupancy target given by 'amdgpu-waves-per-eu' in " "'" + F.getName() + "': desired occupancy was " + Twine(MinWEU) + - ", final occupancy is " + Twine(ProgInfo.Occupancy)); + ", final occupancy is " + Twine(Occupancy)); F.getContext().diagnose(Diag); } } @@ -989,36 +1083,78 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF, const SIMachineFunctionInfo *MFI = MF.getInfo(); const GCNSubtarget &STM = MF.getSubtarget(); unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv()); + MCContext &Ctx = MF.getContext(); + + // (((Value) & Mask) << Shift) + auto SetBits = [&Ctx](const MCExpr *Value, uint32_t Mask, uint32_t Shift) { + const MCExpr *msk = MCConstantExpr::create(Mask, Ctx); + const MCExpr *shft = MCConstantExpr::create(Shift, Ctx); + return MCBinaryExpr::createShl(MCBinaryExpr::createAnd(Value, msk, Ctx), + shft, Ctx); + }; + + auto EmitResolvedOrExpr = [this](const MCExpr *Value, unsigned Size) { + int64_t Val; + if (Value->evaluateAsAbsolute(Val)) + OutStreamer->emitIntValue(static_cast(Val), Size); + else + OutStreamer->emitValue(Value, Size); + }; if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) { OutStreamer->emitInt32(R_00B848_COMPUTE_PGM_RSRC1); - OutStreamer->emitInt32(CurrentProgramInfo.getComputePGMRSrc1(STM)); + EmitResolvedOrExpr(CurrentProgramInfo.getComputePGMRSrc1(STM, Ctx), + /*Size=*/4); OutStreamer->emitInt32(R_00B84C_COMPUTE_PGM_RSRC2); - OutStreamer->emitInt32(CurrentProgramInfo.getComputePGMRSrc2()); + EmitResolvedOrExpr(CurrentProgramInfo.getComputePGMRSrc2(Ctx), /*Size=*/4); OutStreamer->emitInt32(R_00B860_COMPUTE_TMPRING_SIZE); - OutStreamer->emitInt32( - STM.getGeneration() >= AMDGPUSubtarget::GFX12 - ? S_00B860_WAVESIZE_GFX12Plus(CurrentProgramInfo.ScratchBlocks) - : STM.getGeneration() == AMDGPUSubtarget::GFX11 - ? S_00B860_WAVESIZE_GFX11(CurrentProgramInfo.ScratchBlocks) - : S_00B860_WAVESIZE_PreGFX11(CurrentProgramInfo.ScratchBlocks)); + + // Sets bits according to S_0286E8_WAVESIZE_* mask and shift values for the + // appropriate generation. + if (STM.getGeneration() >= AMDGPUSubtarget::GFX12) { + EmitResolvedOrExpr(SetBits(CurrentProgramInfo.ScratchBlocks, + /*Mask=*/0x3FFFF, /*Shift=*/12), + /*Size=*/4); + } else if (STM.getGeneration() == AMDGPUSubtarget::GFX11) { + EmitResolvedOrExpr(SetBits(CurrentProgramInfo.ScratchBlocks, + /*Mask=*/0x7FFF, /*Shift=*/12), + /*Size=*/4); + } else { + EmitResolvedOrExpr(SetBits(CurrentProgramInfo.ScratchBlocks, + /*Mask=*/0x1FFF, /*Shift=*/12), + /*Size=*/4); + } // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 = // 0" comment but I don't see a corresponding field in the register spec. } else { OutStreamer->emitInt32(RsrcReg); - OutStreamer->emitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) | - S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4); + + const MCExpr *GPRBlocks = MCBinaryExpr::createOr( + SetBits(CurrentProgramInfo.VGPRBlocks, /*Mask=*/0x3F, /*Shift=*/0), + SetBits(CurrentProgramInfo.SGPRBlocks, /*Mask=*/0x0F, /*Shift=*/6), + MF.getContext()); + EmitResolvedOrExpr(GPRBlocks, /*Size=*/4); OutStreamer->emitInt32(R_0286E8_SPI_TMPRING_SIZE); - OutStreamer->emitInt32( - STM.getGeneration() >= AMDGPUSubtarget::GFX12 - ? S_0286E8_WAVESIZE_GFX12Plus(CurrentProgramInfo.ScratchBlocks) - : STM.getGeneration() == AMDGPUSubtarget::GFX11 - ? S_0286E8_WAVESIZE_GFX11(CurrentProgramInfo.ScratchBlocks) - : S_0286E8_WAVESIZE_PreGFX11(CurrentProgramInfo.ScratchBlocks)); + + // Sets bits according to S_0286E8_WAVESIZE_* mask and shift values for the + // appropriate generation. + if (STM.getGeneration() >= AMDGPUSubtarget::GFX12) { + EmitResolvedOrExpr(SetBits(CurrentProgramInfo.ScratchBlocks, + /*Mask=*/0x3FFFF, /*Shift=*/12), + /*Size=*/4); + } else if (STM.getGeneration() == AMDGPUSubtarget::GFX11) { + EmitResolvedOrExpr(SetBits(CurrentProgramInfo.ScratchBlocks, + /*Mask=*/0x7FFF, /*Shift=*/12), + /*Size=*/4); + } else { + EmitResolvedOrExpr(SetBits(CurrentProgramInfo.ScratchBlocks, + /*Mask=*/0x1FFF, /*Shift=*/12), + /*Size=*/4); + } } if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) { @@ -1070,33 +1206,38 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF, const SIMachineFunctionInfo *MFI = MF.getInfo(); auto CC = MF.getFunction().getCallingConv(); auto MD = getTargetStreamer()->getPALMetadata(); + auto &Ctx = MF.getContext(); MD->setEntryPoint(CC, MF.getFunction().getName()); - MD->setNumUsedVgprs(CC, CurrentProgramInfo.NumVGPRsForWavesPerEU); + MD->setNumUsedVgprs( + CC, getMCExprValue(CurrentProgramInfo.NumVGPRsForWavesPerEU, Ctx)); // Only set AGPRs for supported devices const GCNSubtarget &STM = MF.getSubtarget(); if (STM.hasMAIInsts()) { - MD->setNumUsedAgprs(CC, CurrentProgramInfo.NumAccVGPR); + MD->setNumUsedAgprs(CC, getMCExprValue(CurrentProgramInfo.NumAccVGPR, Ctx)); } - MD->setNumUsedSgprs(CC, CurrentProgramInfo.NumSGPRsForWavesPerEU); + MD->setNumUsedSgprs( + CC, getMCExprValue(CurrentProgramInfo.NumSGPRsForWavesPerEU, Ctx)); if (MD->getPALMajorVersion() < 3) { MD->setRsrc1(CC, CurrentProgramInfo.getPGMRSrc1(CC, STM)); if (AMDGPU::isCompute(CC)) { MD->setRsrc2(CC, CurrentProgramInfo.getComputePGMRSrc2()); } else { - if (CurrentProgramInfo.ScratchBlocks > 0) + if (getMCExprValue(CurrentProgramInfo.ScratchBlocks, Ctx) > 0) MD->setRsrc2(CC, S_00B84C_SCRATCH_EN(1)); } } else { MD->setHwStage(CC, ".debug_mode", (bool)CurrentProgramInfo.DebugMode); - MD->setHwStage(CC, ".scratch_en", (bool)CurrentProgramInfo.ScratchEnable); + MD->setHwStage(CC, ".scratch_en", + (bool)getMCExprValue(CurrentProgramInfo.ScratchEnable, Ctx)); EmitPALMetadataCommon(MD, CurrentProgramInfo, CC, STM); } // ScratchSize is in bytes, 16 aligned. - MD->setScratchSize(CC, alignTo(CurrentProgramInfo.ScratchSize, 16)); + MD->setScratchSize( + CC, alignTo(getMCExprValue(CurrentProgramInfo.ScratchSize, Ctx), 16)); if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) { unsigned ExtraLDSSize = STM.getGeneration() >= AMDGPUSubtarget::GFX11 ? divideCeil(CurrentProgramInfo.LDSBlocks, 2) @@ -1145,6 +1286,7 @@ void AMDGPUAsmPrinter::emitPALFunctionMetadata(const MachineFunction &MF) { StringRef FnName = MF.getFunction().getName(); MD->setFunctionScratchSize(FnName, MFI.getStackSize()); const GCNSubtarget &ST = MF.getSubtarget(); + MCContext &Ctx = MF.getContext(); if (MD->getPALMajorVersion() < 3) { // Set compute registers @@ -1158,8 +1300,10 @@ void AMDGPUAsmPrinter::emitPALFunctionMetadata(const MachineFunction &MF) { // Set optional info MD->setFunctionLdsSize(FnName, CurrentProgramInfo.LDSSize); - MD->setFunctionNumUsedVgprs(FnName, CurrentProgramInfo.NumVGPRsForWavesPerEU); - MD->setFunctionNumUsedSgprs(FnName, CurrentProgramInfo.NumSGPRsForWavesPerEU); + MD->setFunctionNumUsedVgprs( + FnName, getMCExprValue(CurrentProgramInfo.NumVGPRsForWavesPerEU, Ctx)); + MD->setFunctionNumUsedSgprs( + FnName, getMCExprValue(CurrentProgramInfo.NumSGPRsForWavesPerEU, Ctx)); } // This is supposed to be log2(Size) @@ -1185,6 +1329,7 @@ void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out, const SIMachineFunctionInfo *MFI = MF.getInfo(); const GCNSubtarget &STM = MF.getSubtarget(); + MCContext &Ctx = MF.getContext(); AMDGPU::initDefaultAMDKernelCodeT(Out, &STM); @@ -1193,7 +1338,7 @@ void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out, (CurrentProgramInfo.getComputePGMRSrc2() << 32); Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64; - if (CurrentProgramInfo.DynamicCallStack) + if (getMCExprValue(CurrentProgramInfo.DynamicCallStack, Ctx)) Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK; AMD_HSA_BITS_SET(Out.code_properties, @@ -1229,9 +1374,10 @@ void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out, Align MaxKernArgAlign; Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign); - Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR; - Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR; - Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize; + Out.wavefront_sgpr_count = getMCExprValue(CurrentProgramInfo.NumSGPR, Ctx); + Out.workitem_vgpr_count = getMCExprValue(CurrentProgramInfo.NumVGPR, Ctx); + Out.workitem_private_segment_byte_size = + getMCExprValue(CurrentProgramInfo.ScratchSize, Ctx); Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize; // kernarg_segment_alignment is specified as log of the alignment. @@ -1322,19 +1468,28 @@ void AMDGPUAsmPrinter::emitResourceUsageRemarks( // remarks to simulate newlines. If and when clang does accept newlines, this // formatting should be aggregated into one remark with newlines to avoid // printing multiple diagnostic location and diag opts. + MCContext &MCCtx = MF.getContext(); EmitResourceUsageRemark("FunctionName", "Function Name", MF.getFunction().getName()); - EmitResourceUsageRemark("NumSGPR", "SGPRs", CurrentProgramInfo.NumSGPR); - EmitResourceUsageRemark("NumVGPR", "VGPRs", CurrentProgramInfo.NumArchVGPR); - if (hasMAIInsts) - EmitResourceUsageRemark("NumAGPR", "AGPRs", CurrentProgramInfo.NumAccVGPR); - EmitResourceUsageRemark("ScratchSize", "ScratchSize [bytes/lane]", - CurrentProgramInfo.ScratchSize); + EmitResourceUsageRemark("NumSGPR", "SGPRs", + getMCExprValue(CurrentProgramInfo.NumSGPR, MCCtx)); + EmitResourceUsageRemark( + "NumVGPR", "VGPRs", + getMCExprValue(CurrentProgramInfo.NumArchVGPR, MCCtx)); + if (hasMAIInsts) { + EmitResourceUsageRemark( + "NumAGPR", "AGPRs", + getMCExprValue(CurrentProgramInfo.NumAccVGPR, MCCtx)); + } + EmitResourceUsageRemark( + "ScratchSize", "ScratchSize [bytes/lane]", + getMCExprValue(CurrentProgramInfo.ScratchSize, MCCtx)); StringRef DynamicStackStr = - CurrentProgramInfo.DynamicCallStack ? "True" : "False"; + getMCExprValue(CurrentProgramInfo.DynamicCallStack, MCCtx) ? "True" + : "False"; EmitResourceUsageRemark("DynamicStack", "Dynamic Stack", DynamicStackStr); EmitResourceUsageRemark("Occupancy", "Occupancy [waves/SIMD]", - CurrentProgramInfo.Occupancy); + getMCExprValue(CurrentProgramInfo.Occupancy, MCCtx)); EmitResourceUsageRemark("SGPRSpill", "SGPRs Spill", CurrentProgramInfo.SGPRSpill); EmitResourceUsageRemark("VGPRSpill", "VGPRs Spill", diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h index b8b2718d293e..16d8952a533e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h @@ -78,6 +78,8 @@ private: void initTargetStreamer(Module &M); + static uint64_t getMCExprValue(const MCExpr *Value, MCContext &Ctx); + public: explicit AMDGPUAsmPrinter(TargetMachine &TM, std::unique_ptr Streamer); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp index 9e288ab50e17..7ab9ba285133 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp @@ -19,6 +19,8 @@ #include "SIMachineFunctionInfo.h" #include "SIProgramInfo.h" #include "llvm/IR/Module.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" using namespace llvm; static std::pair getArgumentTypeAlign(const Argument &Arg, @@ -462,6 +464,16 @@ MetadataStreamerMsgPackV4::getHSAKernelProps(const MachineFunction &MF, const SIMachineFunctionInfo &MFI = *MF.getInfo(); const Function &F = MF.getFunction(); + auto GetMCExprValue = [&MF](const MCExpr *Value) { + int64_t Val; + if (!Value->evaluateAsAbsolute(Val)) { + MCContext &Ctx = MF.getContext(); + Ctx.reportError(SMLoc(), "could not resolve expression when required."); + Val = 0; + } + return static_cast(Val); + }; + auto Kern = HSAMetadataDoc->getMapNode(); Align MaxKernArgAlign; @@ -470,10 +482,11 @@ MetadataStreamerMsgPackV4::getHSAKernelProps(const MachineFunction &MF, Kern[".group_segment_fixed_size"] = Kern.getDocument()->getNode(ProgramInfo.LDSSize); Kern[".private_segment_fixed_size"] = - Kern.getDocument()->getNode(ProgramInfo.ScratchSize); - if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) - Kern[".uses_dynamic_stack"] = - Kern.getDocument()->getNode(ProgramInfo.DynamicCallStack); + Kern.getDocument()->getNode(GetMCExprValue(ProgramInfo.ScratchSize)); + if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) { + Kern[".uses_dynamic_stack"] = Kern.getDocument()->getNode( + static_cast(GetMCExprValue(ProgramInfo.DynamicCallStack))); + } if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5 && STM.supportsWGP()) Kern[".workgroup_processor_mode"] = @@ -484,12 +497,15 @@ MetadataStreamerMsgPackV4::getHSAKernelProps(const MachineFunction &MF, Kern.getDocument()->getNode(std::max(Align(4), MaxKernArgAlign).value()); Kern[".wavefront_size"] = Kern.getDocument()->getNode(STM.getWavefrontSize()); - Kern[".sgpr_count"] = Kern.getDocument()->getNode(ProgramInfo.NumSGPR); - Kern[".vgpr_count"] = Kern.getDocument()->getNode(ProgramInfo.NumVGPR); + Kern[".sgpr_count"] = + Kern.getDocument()->getNode(GetMCExprValue(ProgramInfo.NumSGPR)); + Kern[".vgpr_count"] = + Kern.getDocument()->getNode(GetMCExprValue(ProgramInfo.NumVGPR)); // Only add AGPR count to metadata for supported devices if (STM.hasMAIInsts()) { - Kern[".agpr_count"] = Kern.getDocument()->getNode(ProgramInfo.NumAccVGPR); + Kern[".agpr_count"] = + Kern.getDocument()->getNode(GetMCExprValue(ProgramInfo.NumAccVGPR)); } Kern[".max_flat_workgroup_size"] = diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index 9cfe81e5288e..94ee4ac78142 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -674,29 +674,8 @@ bool GCNSubtarget::useVGPRIndexMode() const { bool GCNSubtarget::useAA() const { return UseAA; } unsigned GCNSubtarget::getOccupancyWithNumSGPRs(unsigned SGPRs) const { - if (getGeneration() >= AMDGPUSubtarget::GFX10) - return getMaxWavesPerEU(); - - if (getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { - if (SGPRs <= 80) - return 10; - if (SGPRs <= 88) - return 9; - if (SGPRs <= 100) - return 8; - return 7; - } - if (SGPRs <= 48) - return 10; - if (SGPRs <= 56) - return 9; - if (SGPRs <= 64) - return 8; - if (SGPRs <= 72) - return 7; - if (SGPRs <= 80) - return 6; - return 5; + return AMDGPU::IsaInfo::getOccupancyWithNumSGPRs(SGPRs, getMaxWavesPerEU(), + getGeneration()); } unsigned GCNSubtarget::getOccupancyWithNumVGPRs(unsigned NumVGPRs) const { diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 5ac245ac3b63..d47a5f8ebb81 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -8399,12 +8399,16 @@ bool AMDGPUAsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) { AGVK VK = StringSwitch(TokenId) .Case("max", AGVK::AGVK_Max) .Case("or", AGVK::AGVK_Or) + .Case("extrasgprs", AGVK::AGVK_ExtraSGPRs) + .Case("totalnumvgprs", AGVK::AGVK_TotalNumVGPRs) + .Case("alignto", AGVK::AGVK_AlignTo) + .Case("occupancy", AGVK::AGVK_Occupancy) .Default(AGVK::AGVK_None); if (VK != AGVK::AGVK_None && peekToken().is(AsmToken::LParen)) { SmallVector Exprs; uint64_t CommaCount = 0; - lex(); // Eat 'max'/'or' + lex(); // Eat Arg ('or', 'max', 'occupancy', etc.) lex(); // Eat '(' while (true) { if (trySkipToken(AsmToken::RParen)) { diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp index 4578c33d92dc..159664faf983 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp @@ -7,6 +7,9 @@ //===----------------------------------------------------------------------===// #include "AMDGPUMCExpr.h" +#include "GCNSubtarget.h" +#include "Utils/AMDGPUBaseInfo.h" +#include "llvm/IR/Function.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" @@ -16,6 +19,7 @@ #include using namespace llvm; +using namespace llvm::AMDGPU; AMDGPUVariadicMCExpr::AMDGPUVariadicMCExpr(VariadicKind Kind, ArrayRef Args, @@ -61,6 +65,18 @@ void AMDGPUVariadicMCExpr::printImpl(raw_ostream &OS, case AGVK_Max: OS << "max("; break; + case AGVK_ExtraSGPRs: + OS << "extrasgprs("; + break; + case AGVK_TotalNumVGPRs: + OS << "totalnumvgprs("; + break; + case AGVK_AlignTo: + OS << "alignto("; + break; + case AGVK_Occupancy: + OS << "occupancy("; + break; } for (auto It = Args.begin(); It != Args.end(); ++It) { (*It)->print(OS, MAI, /*InParens=*/false); @@ -82,10 +98,151 @@ static int64_t op(AMDGPUVariadicMCExpr::VariadicKind Kind, int64_t Arg1, } } +bool AMDGPUVariadicMCExpr::evaluateExtraSGPRs(MCValue &Res, + const MCAsmLayout *Layout, + const MCFixup *Fixup) const { + auto TryGetMCExprValue = [&](const MCExpr *Arg, uint64_t &ConstantValue) { + MCValue MCVal; + if (!Arg->evaluateAsRelocatable(MCVal, Layout, Fixup) || + !MCVal.isAbsolute()) + return false; + + ConstantValue = MCVal.getConstant(); + return true; + }; + + assert(Args.size() == 3 && + "AMDGPUVariadic Argument count incorrect for ExtraSGPRs"); + const MCSubtargetInfo *STI = Ctx.getSubtargetInfo(); + uint64_t VCCUsed = 0, FlatScrUsed = 0, XNACKUsed = 0; + + bool Success = TryGetMCExprValue(Args[2], XNACKUsed); + + assert(Success && "Arguments 3 for ExtraSGPRs should be a known constant"); + if (!Success || !TryGetMCExprValue(Args[0], VCCUsed) || + !TryGetMCExprValue(Args[1], FlatScrUsed)) + return false; + + uint64_t ExtraSGPRs = IsaInfo::getNumExtraSGPRs( + STI, (bool)VCCUsed, (bool)FlatScrUsed, (bool)XNACKUsed); + Res = MCValue::get(ExtraSGPRs); + return true; +} + +bool AMDGPUVariadicMCExpr::evaluateTotalNumVGPR(MCValue &Res, + const MCAsmLayout *Layout, + const MCFixup *Fixup) const { + auto TryGetMCExprValue = [&](const MCExpr *Arg, uint64_t &ConstantValue) { + MCValue MCVal; + if (!Arg->evaluateAsRelocatable(MCVal, Layout, Fixup) || + !MCVal.isAbsolute()) + return false; + + ConstantValue = MCVal.getConstant(); + return true; + }; + assert(Args.size() == 2 && + "AMDGPUVariadic Argument count incorrect for TotalNumVGPRs"); + const MCSubtargetInfo *STI = Ctx.getSubtargetInfo(); + uint64_t NumAGPR = 0, NumVGPR = 0; + + bool Has90AInsts = AMDGPU::isGFX90A(*STI); + + if (!TryGetMCExprValue(Args[0], NumAGPR) || + !TryGetMCExprValue(Args[1], NumVGPR)) + return false; + + uint64_t TotalNum = Has90AInsts && NumAGPR ? alignTo(NumVGPR, 4) + NumAGPR + : std::max(NumVGPR, NumAGPR); + Res = MCValue::get(TotalNum); + return true; +} + +bool AMDGPUVariadicMCExpr::evaluateAlignTo(MCValue &Res, + const MCAsmLayout *Layout, + const MCFixup *Fixup) const { + auto TryGetMCExprValue = [&](const MCExpr *Arg, uint64_t &ConstantValue) { + MCValue MCVal; + if (!Arg->evaluateAsRelocatable(MCVal, Layout, Fixup) || + !MCVal.isAbsolute()) + return false; + + ConstantValue = MCVal.getConstant(); + return true; + }; + + assert(Args.size() == 2 && + "AMDGPUVariadic Argument count incorrect for AlignTo"); + uint64_t Value = 0, Align = 0; + if (!TryGetMCExprValue(Args[0], Value) || !TryGetMCExprValue(Args[1], Align)) + return false; + + Res = MCValue::get(alignTo(Value, Align)); + return true; +} + +bool AMDGPUVariadicMCExpr::evaluateOccupancy(MCValue &Res, + const MCAsmLayout *Layout, + const MCFixup *Fixup) const { + auto TryGetMCExprValue = [&](const MCExpr *Arg, uint64_t &ConstantValue) { + MCValue MCVal; + if (!Arg->evaluateAsRelocatable(MCVal, Layout, Fixup) || + !MCVal.isAbsolute()) + return false; + + ConstantValue = MCVal.getConstant(); + return true; + }; + assert(Args.size() == 7 && + "AMDGPUVariadic Argument count incorrect for Occupancy"); + uint64_t InitOccupancy, MaxWaves, Granule, TargetTotalNumVGPRs, Generation, + NumSGPRs, NumVGPRs; + + bool Success = true; + Success &= TryGetMCExprValue(Args[0], MaxWaves); + Success &= TryGetMCExprValue(Args[1], Granule); + Success &= TryGetMCExprValue(Args[2], TargetTotalNumVGPRs); + Success &= TryGetMCExprValue(Args[3], Generation); + Success &= TryGetMCExprValue(Args[4], InitOccupancy); + + assert(Success && "Arguments 1 to 5 for Occupancy should be known constants"); + + if (!Success || !TryGetMCExprValue(Args[5], NumSGPRs) || + !TryGetMCExprValue(Args[6], NumVGPRs)) + return false; + + unsigned Occupancy = InitOccupancy; + if (NumSGPRs) + Occupancy = std::min( + Occupancy, IsaInfo::getOccupancyWithNumSGPRs( + NumSGPRs, MaxWaves, + static_cast(Generation))); + if (NumVGPRs) + Occupancy = std::min(Occupancy, + IsaInfo::getNumWavesPerEUWithNumVGPRs( + NumVGPRs, Granule, MaxWaves, TargetTotalNumVGPRs)); + + Res = MCValue::get(Occupancy); + return true; +} + bool AMDGPUVariadicMCExpr::evaluateAsRelocatableImpl( MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const { std::optional Total; + switch (Kind) { + default: + break; + case AGVK_ExtraSGPRs: + return evaluateExtraSGPRs(Res, Layout, Fixup); + case AGVK_AlignTo: + return evaluateAlignTo(Res, Layout, Fixup); + case AGVK_TotalNumVGPRs: + return evaluateTotalNumVGPR(Res, Layout, Fixup); + case AGVK_Occupancy: + return evaluateOccupancy(Res, Layout, Fixup); + } + for (const MCExpr *Arg : Args) { MCValue ArgRes; if (!Arg->evaluateAsRelocatable(ArgRes, Layout, Fixup) || @@ -113,3 +270,47 @@ MCFragment *AMDGPUVariadicMCExpr::findAssociatedFragment() const { } return nullptr; } + +/// Allow delayed MCExpr resolve of ExtraSGPRs (in case VCCUsed or FlatScrUsed +/// are unresolvable but needed for further MCExprs). Derived from +/// implementation of IsaInfo::getNumExtraSGPRs in AMDGPUBaseInfo.cpp. +/// +const AMDGPUVariadicMCExpr * +AMDGPUVariadicMCExpr::createExtraSGPRs(const MCExpr *VCCUsed, + const MCExpr *FlatScrUsed, + bool XNACKUsed, MCContext &Ctx) { + + return create(AGVK_ExtraSGPRs, + {VCCUsed, FlatScrUsed, MCConstantExpr::create(XNACKUsed, Ctx)}, + Ctx); +} + +const AMDGPUVariadicMCExpr *AMDGPUVariadicMCExpr::createTotalNumVGPR( + const MCExpr *NumAGPR, const MCExpr *NumVGPR, MCContext &Ctx) { + return create(AGVK_TotalNumVGPRs, {NumAGPR, NumVGPR}, Ctx); +} + +/// Mimics GCNSubtarget::computeOccupancy for MCExpr. +/// +/// Remove dependency on GCNSubtarget and depend only only the necessary values +/// for said occupancy computation. Should match computeOccupancy implementation +/// without passing \p STM on. +const AMDGPUVariadicMCExpr * +AMDGPUVariadicMCExpr::createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs, + const MCExpr *NumVGPRs, + const GCNSubtarget &STM, MCContext &Ctx) { + unsigned MaxWaves = IsaInfo::getMaxWavesPerEU(&STM); + unsigned Granule = IsaInfo::getVGPRAllocGranule(&STM); + unsigned TargetTotalNumVGPRs = IsaInfo::getTotalNumVGPRs(&STM); + unsigned Generation = STM.getGeneration(); + + auto CreateExpr = [&Ctx](unsigned Value) { + return MCConstantExpr::create(Value, Ctx); + }; + + return create(AGVK_Occupancy, + {CreateExpr(MaxWaves), CreateExpr(Granule), + CreateExpr(TargetTotalNumVGPRs), CreateExpr(Generation), + CreateExpr(InitOcc), NumSGPRs, NumVGPRs}, + Ctx); +} diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h index 238e0dea791b..f92350b59235 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h @@ -14,6 +14,9 @@ namespace llvm { +class Function; +class GCNSubtarget; + /// AMDGPU target specific variadic MCExpr operations. /// /// Takes in a minimum of 1 argument to be used with an operation. The supported @@ -26,7 +29,15 @@ namespace llvm { /// class AMDGPUVariadicMCExpr : public MCTargetExpr { public: - enum VariadicKind { AGVK_None, AGVK_Or, AGVK_Max }; + enum VariadicKind { + AGVK_None, + AGVK_Or, + AGVK_Max, + AGVK_ExtraSGPRs, + AGVK_TotalNumVGPRs, + AGVK_AlignTo, + AGVK_Occupancy + }; private: VariadicKind Kind; @@ -38,6 +49,15 @@ private: MCContext &Ctx); ~AMDGPUVariadicMCExpr(); + bool evaluateExtraSGPRs(MCValue &Res, const MCAsmLayout *Layout, + const MCFixup *Fixup) const; + bool evaluateTotalNumVGPR(MCValue &Res, const MCAsmLayout *Layout, + const MCFixup *Fixup) const; + bool evaluateAlignTo(MCValue &Res, const MCAsmLayout *Layout, + const MCFixup *Fixup) const; + bool evaluateOccupancy(MCValue &Res, const MCAsmLayout *Layout, + const MCFixup *Fixup) const; + public: static const AMDGPUVariadicMCExpr * create(VariadicKind Kind, ArrayRef Args, MCContext &Ctx); @@ -52,6 +72,26 @@ public: return create(VariadicKind::AGVK_Max, Args, Ctx); } + static const AMDGPUVariadicMCExpr *createExtraSGPRs(const MCExpr *VCCUsed, + const MCExpr *FlatScrUsed, + bool XNACKUsed, + MCContext &Ctx); + + static const AMDGPUVariadicMCExpr *createTotalNumVGPR(const MCExpr *NumAGPR, + const MCExpr *NumVGPR, + MCContext &Ctx); + + static const AMDGPUVariadicMCExpr * + createAlignTo(const MCExpr *Value, const MCExpr *Align, MCContext &Ctx) { + return create(VariadicKind::AGVK_AlignTo, {Value, Align}, Ctx); + } + + static const AMDGPUVariadicMCExpr *createOccupancy(unsigned InitOcc, + const MCExpr *NumSGPRs, + const MCExpr *NumVGPRs, + const GCNSubtarget &STM, + MCContext &Ctx); + VariadicKind getKind() const { return Kind; } const MCExpr *getSubExpr(size_t Index) const; diff --git a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp index 9ed7aacc0538..0d40816cdd4b 100644 --- a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp @@ -18,57 +18,114 @@ #include "GCNSubtarget.h" #include "SIDefines.h" #include "Utils/AMDGPUBaseInfo.h" +#include "llvm/MC/MCExpr.h" using namespace llvm; -uint64_t SIProgramInfo::getComputePGMRSrc1(const GCNSubtarget &ST) const { - uint64_t Reg = S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) | - S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) | - S_00B848_PRIV(Priv) | S_00B848_DEBUG_MODE(DebugMode) | - S_00B848_WGP_MODE(WgpMode) | S_00B848_MEM_ORDERED(MemOrdered); +void SIProgramInfo::reset(const MachineFunction &MF) { + MCContext &Ctx = MF.getContext(); + + const MCExpr *ZeroExpr = MCConstantExpr::create(0, Ctx); + + VGPRBlocks = ZeroExpr; + SGPRBlocks = ZeroExpr; + Priority = 0; + FloatMode = 0; + Priv = 0; + DX10Clamp = 0; + DebugMode = 0; + IEEEMode = 0; + WgpMode = 0; + MemOrdered = 0; + RrWgMode = 0; + ScratchSize = ZeroExpr; + + LDSBlocks = 0; + ScratchBlocks = ZeroExpr; + + ScratchEnable = ZeroExpr; + UserSGPR = 0; + TrapHandlerEnable = 0; + TGIdXEnable = 0; + TGIdYEnable = 0; + TGIdZEnable = 0; + TGSizeEnable = 0; + TIdIGCompCount = 0; + EXCPEnMSB = 0; + LdsSize = 0; + EXCPEnable = 0; + + ComputePGMRSrc3GFX90A = ZeroExpr; + + NumVGPR = ZeroExpr; + NumArchVGPR = ZeroExpr; + NumAccVGPR = ZeroExpr; + AccumOffset = ZeroExpr; + TgSplit = 0; + NumSGPR = ZeroExpr; + SGPRSpill = 0; + VGPRSpill = 0; + LDSSize = 0; + FlatUsed = ZeroExpr; + + NumSGPRsForWavesPerEU = ZeroExpr; + NumVGPRsForWavesPerEU = ZeroExpr; + Occupancy = ZeroExpr; + DynamicCallStack = ZeroExpr; + VCCUsed = ZeroExpr; +} + +static uint64_t getComputePGMRSrc1Reg(const SIProgramInfo &ProgInfo, + const GCNSubtarget &ST) { + uint64_t Reg = S_00B848_PRIORITY(ProgInfo.Priority) | + S_00B848_FLOAT_MODE(ProgInfo.FloatMode) | + S_00B848_PRIV(ProgInfo.Priv) | + S_00B848_DEBUG_MODE(ProgInfo.DebugMode) | + S_00B848_WGP_MODE(ProgInfo.WgpMode) | + S_00B848_MEM_ORDERED(ProgInfo.MemOrdered); if (ST.hasDX10ClampMode()) - Reg |= S_00B848_DX10_CLAMP(DX10Clamp); + Reg |= S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp); if (ST.hasIEEEMode()) - Reg |= S_00B848_IEEE_MODE(IEEEMode); + Reg |= S_00B848_IEEE_MODE(ProgInfo.IEEEMode); if (ST.hasRrWGMode()) - Reg |= S_00B848_RR_WG_MODE(RrWgMode); + Reg |= S_00B848_RR_WG_MODE(ProgInfo.RrWgMode); return Reg; } -uint64_t SIProgramInfo::getPGMRSrc1(CallingConv::ID CC, - const GCNSubtarget &ST) const { - if (AMDGPU::isCompute(CC)) { - return getComputePGMRSrc1(ST); - } - uint64_t Reg = S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) | - S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) | - S_00B848_PRIV(Priv) | S_00B848_DEBUG_MODE(DebugMode); +static uint64_t getPGMRSrc1Reg(const SIProgramInfo &ProgInfo, + CallingConv::ID CC, const GCNSubtarget &ST) { + uint64_t Reg = S_00B848_PRIORITY(ProgInfo.Priority) | + S_00B848_FLOAT_MODE(ProgInfo.FloatMode) | + S_00B848_PRIV(ProgInfo.Priv) | + S_00B848_DEBUG_MODE(ProgInfo.DebugMode); if (ST.hasDX10ClampMode()) - Reg |= S_00B848_DX10_CLAMP(DX10Clamp); + Reg |= S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp); if (ST.hasIEEEMode()) - Reg |= S_00B848_IEEE_MODE(IEEEMode); + Reg |= S_00B848_IEEE_MODE(ProgInfo.IEEEMode); if (ST.hasRrWGMode()) - Reg |= S_00B848_RR_WG_MODE(RrWgMode); + Reg |= S_00B848_RR_WG_MODE(ProgInfo.RrWgMode); switch (CC) { case CallingConv::AMDGPU_PS: - Reg |= S_00B028_MEM_ORDERED(MemOrdered); + Reg |= S_00B028_MEM_ORDERED(ProgInfo.MemOrdered); break; case CallingConv::AMDGPU_VS: - Reg |= S_00B128_MEM_ORDERED(MemOrdered); + Reg |= S_00B128_MEM_ORDERED(ProgInfo.MemOrdered); break; case CallingConv::AMDGPU_GS: - Reg |= S_00B228_WGP_MODE(WgpMode) | S_00B228_MEM_ORDERED(MemOrdered); + Reg |= S_00B228_WGP_MODE(ProgInfo.WgpMode) | + S_00B228_MEM_ORDERED(ProgInfo.MemOrdered); break; case CallingConv::AMDGPU_HS: - Reg |= S_00B428_WGP_MODE(WgpMode) | S_00B428_MEM_ORDERED(MemOrdered); + Reg |= S_00B428_WGP_MODE(ProgInfo.WgpMode) | + S_00B428_MEM_ORDERED(ProgInfo.MemOrdered); break; default: break; @@ -76,22 +133,108 @@ uint64_t SIProgramInfo::getPGMRSrc1(CallingConv::ID CC, return Reg; } -uint64_t SIProgramInfo::getComputePGMRSrc2() const { - uint64_t Reg = - S_00B84C_SCRATCH_EN(ScratchEnable) | S_00B84C_USER_SGPR(UserSGPR) | - S_00B84C_TRAP_HANDLER(TrapHandlerEnable) | - S_00B84C_TGID_X_EN(TGIdXEnable) | S_00B84C_TGID_Y_EN(TGIdYEnable) | - S_00B84C_TGID_Z_EN(TGIdZEnable) | S_00B84C_TG_SIZE_EN(TGSizeEnable) | - S_00B84C_TIDIG_COMP_CNT(TIdIGCompCount) | - S_00B84C_EXCP_EN_MSB(EXCPEnMSB) | S_00B84C_LDS_SIZE(LdsSize) | - S_00B84C_EXCP_EN(EXCPEnable); +static uint64_t getComputePGMRSrc2Reg(const SIProgramInfo &ProgInfo) { + uint64_t Reg = S_00B84C_USER_SGPR(ProgInfo.UserSGPR) | + S_00B84C_TRAP_HANDLER(ProgInfo.TrapHandlerEnable) | + S_00B84C_TGID_X_EN(ProgInfo.TGIdXEnable) | + S_00B84C_TGID_Y_EN(ProgInfo.TGIdYEnable) | + S_00B84C_TGID_Z_EN(ProgInfo.TGIdZEnable) | + S_00B84C_TG_SIZE_EN(ProgInfo.TGSizeEnable) | + S_00B84C_TIDIG_COMP_CNT(ProgInfo.TIdIGCompCount) | + S_00B84C_EXCP_EN_MSB(ProgInfo.EXCPEnMSB) | + S_00B84C_LDS_SIZE(ProgInfo.LdsSize) | + S_00B84C_EXCP_EN(ProgInfo.EXCPEnable); + + return Reg; +} + +static const MCExpr *MaskShift(const MCExpr *Val, uint32_t Mask, uint32_t Shift, + MCContext &Ctx) { + if (Mask) { + const MCExpr *MaskExpr = MCConstantExpr::create(Mask, Ctx); + Val = MCBinaryExpr::createAnd(Val, MaskExpr, Ctx); + } + if (Shift) { + const MCExpr *ShiftExpr = MCConstantExpr::create(Shift, Ctx); + Val = MCBinaryExpr::createShl(Val, ShiftExpr, Ctx); + } + return Val; +} + +uint64_t SIProgramInfo::getComputePGMRSrc1(const GCNSubtarget &ST) const { + int64_t VBlocks, SBlocks; + VGPRBlocks->evaluateAsAbsolute(VBlocks); + SGPRBlocks->evaluateAsAbsolute(SBlocks); + + uint64_t Reg = S_00B848_VGPRS(static_cast(VBlocks)) | + S_00B848_SGPRS(static_cast(SBlocks)) | + getComputePGMRSrc1Reg(*this, ST); return Reg; } +uint64_t SIProgramInfo::getPGMRSrc1(CallingConv::ID CC, + const GCNSubtarget &ST) const { + if (AMDGPU::isCompute(CC)) { + return getComputePGMRSrc1(ST); + } + int64_t VBlocks, SBlocks; + VGPRBlocks->evaluateAsAbsolute(VBlocks); + SGPRBlocks->evaluateAsAbsolute(SBlocks); + + return getPGMRSrc1Reg(*this, CC, ST) | + S_00B848_VGPRS(static_cast(VBlocks)) | + S_00B848_SGPRS(static_cast(SBlocks)); +} + +uint64_t SIProgramInfo::getComputePGMRSrc2() const { + int64_t ScratchEn; + ScratchEnable->evaluateAsAbsolute(ScratchEn); + return ScratchEn | getComputePGMRSrc2Reg(*this); +} + uint64_t SIProgramInfo::getPGMRSrc2(CallingConv::ID CC) const { if (AMDGPU::isCompute(CC)) return getComputePGMRSrc2(); return 0; } + +const MCExpr *SIProgramInfo::getComputePGMRSrc1(const GCNSubtarget &ST, + MCContext &Ctx) const { + uint64_t Reg = getComputePGMRSrc1Reg(*this, ST); + const MCExpr *RegExpr = MCConstantExpr::create(Reg, Ctx); + const MCExpr *Res = MCBinaryExpr::createOr( + MaskShift(VGPRBlocks, /*Mask=*/0x3F, /*Shift=*/0, Ctx), + MaskShift(SGPRBlocks, /*Mask=*/0xF, /*Shift=*/6, Ctx), Ctx); + return MCBinaryExpr::createOr(RegExpr, Res, Ctx); +} + +const MCExpr *SIProgramInfo::getPGMRSrc1(CallingConv::ID CC, + const GCNSubtarget &ST, + MCContext &Ctx) const { + if (AMDGPU::isCompute(CC)) { + return getComputePGMRSrc1(ST, Ctx); + } + + uint64_t Reg = getPGMRSrc1Reg(*this, CC, ST); + const MCExpr *RegExpr = MCConstantExpr::create(Reg, Ctx); + const MCExpr *Res = MCBinaryExpr::createOr( + MaskShift(VGPRBlocks, /*Mask=*/0x3F, /*Shift=*/0, Ctx), + MaskShift(SGPRBlocks, /*Mask=*/0xF, /*Shift=*/6, Ctx), Ctx); + return MCBinaryExpr::createOr(RegExpr, Res, Ctx); +} + +const MCExpr *SIProgramInfo::getComputePGMRSrc2(MCContext &Ctx) const { + uint64_t Reg = getComputePGMRSrc2Reg(*this); + const MCExpr *RegExpr = MCConstantExpr::create(Reg, Ctx); + return MCBinaryExpr::createOr(ScratchEnable, RegExpr, Ctx); +} + +const MCExpr *SIProgramInfo::getPGMRSrc2(CallingConv::ID CC, + MCContext &Ctx) const { + if (AMDGPU::isCompute(CC)) + return getComputePGMRSrc2(Ctx); + + return MCConstantExpr::create(0, Ctx); +} diff --git a/llvm/lib/Target/AMDGPU/SIProgramInfo.h b/llvm/lib/Target/AMDGPU/SIProgramInfo.h index 8c26789f936c..c0a353033c3c 100644 --- a/llvm/lib/Target/AMDGPU/SIProgramInfo.h +++ b/llvm/lib/Target/AMDGPU/SIProgramInfo.h @@ -22,12 +22,15 @@ namespace llvm { class GCNSubtarget; +class MCContext; +class MCExpr; +class MachineFunction; /// Track resource usage for kernels / entry functions. struct SIProgramInfo { // Fields set in PGM_RSRC1 pm4 packet. - uint32_t VGPRBlocks = 0; - uint32_t SGPRBlocks = 0; + const MCExpr *VGPRBlocks = nullptr; + const MCExpr *SGPRBlocks = nullptr; uint32_t Priority = 0; uint32_t FloatMode = 0; uint32_t Priv = 0; @@ -37,14 +40,14 @@ struct SIProgramInfo { uint32_t WgpMode = 0; // GFX10+ uint32_t MemOrdered = 0; // GFX10+ uint32_t RrWgMode = 0; // GFX12+ - uint64_t ScratchSize = 0; + const MCExpr *ScratchSize = nullptr; // State used to calculate fields set in PGM_RSRC2 pm4 packet. uint32_t LDSBlocks = 0; - uint32_t ScratchBlocks = 0; + const MCExpr *ScratchBlocks = nullptr; // Fields set in PGM_RSRC2 pm4 packet - uint32_t ScratchEnable = 0; + const MCExpr *ScratchEnable = nullptr; uint32_t UserSGPR = 0; uint32_t TrapHandlerEnable = 0; uint32_t TGIdXEnable = 0; @@ -56,44 +59,56 @@ struct SIProgramInfo { uint32_t LdsSize = 0; uint32_t EXCPEnable = 0; - uint64_t ComputePGMRSrc3GFX90A = 0; + const MCExpr *ComputePGMRSrc3GFX90A = nullptr; - uint32_t NumVGPR = 0; - uint32_t NumArchVGPR = 0; - uint32_t NumAccVGPR = 0; - uint32_t AccumOffset = 0; + const MCExpr *NumVGPR = nullptr; + const MCExpr *NumArchVGPR = nullptr; + const MCExpr *NumAccVGPR = nullptr; + const MCExpr *AccumOffset = nullptr; uint32_t TgSplit = 0; - uint32_t NumSGPR = 0; + const MCExpr *NumSGPR = nullptr; unsigned SGPRSpill = 0; unsigned VGPRSpill = 0; uint32_t LDSSize = 0; - bool FlatUsed = false; + const MCExpr *FlatUsed = nullptr; // Number of SGPRs that meets number of waves per execution unit request. - uint32_t NumSGPRsForWavesPerEU = 0; + const MCExpr *NumSGPRsForWavesPerEU = nullptr; // Number of VGPRs that meets number of waves per execution unit request. - uint32_t NumVGPRsForWavesPerEU = 0; + const MCExpr *NumVGPRsForWavesPerEU = nullptr; // Final occupancy. - uint32_t Occupancy = 0; + const MCExpr *Occupancy = nullptr; // Whether there is recursion, dynamic allocas, indirect calls or some other // reason there may be statically unknown stack usage. - bool DynamicCallStack = false; + const MCExpr *DynamicCallStack = nullptr; // Bonus information for debugging. - bool VCCUsed = false; + const MCExpr *VCCUsed = nullptr; SIProgramInfo() = default; + // The constructor sets the values for each member as shown in the struct. + // However, setting the MCExpr members to their zero value equivalent + // happens in reset together with (duplicated) value re-set for the + // non-MCExpr members. + void reset(const MachineFunction &MF); + /// Compute the value of the ComputePGMRsrc1 register. uint64_t getComputePGMRSrc1(const GCNSubtarget &ST) const; uint64_t getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST) const; + const MCExpr *getComputePGMRSrc1(const GCNSubtarget &ST, + MCContext &Ctx) const; + const MCExpr *getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST, + MCContext &Ctx) const; /// Compute the value of the ComputePGMRsrc2 register. uint64_t getComputePGMRSrc2() const; uint64_t getPGMRSrc2(CallingConv::ID CC) const; + const MCExpr *getComputePGMRSrc2(MCContext &Ctx) const; + const MCExpr *getPGMRSrc2(CallingConv::ID CC, MCContext &Ctx) const; }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 2fae7a31d70b..2beaf903542b 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -1129,12 +1129,45 @@ unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI) { unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs) { - unsigned MaxWaves = getMaxWavesPerEU(STI); - unsigned Granule = getVGPRAllocGranule(STI); + return getNumWavesPerEUWithNumVGPRs(NumVGPRs, getVGPRAllocGranule(STI), + getMaxWavesPerEU(STI), + getTotalNumVGPRs(STI)); +} + +unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule, + unsigned MaxWaves, + unsigned TotalNumVGPRs) { if (NumVGPRs < Granule) return MaxWaves; unsigned RoundedRegs = alignTo(NumVGPRs, Granule); - return std::min(std::max(getTotalNumVGPRs(STI) / RoundedRegs, 1u), MaxWaves); + return std::min(std::max(TotalNumVGPRs / RoundedRegs, 1u), MaxWaves); +} + +unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves, + AMDGPUSubtarget::Generation Gen) { + if (Gen >= AMDGPUSubtarget::GFX10) + return MaxWaves; + + if (Gen >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { + if (SGPRs <= 80) + return 10; + if (SGPRs <= 88) + return 9; + if (SGPRs <= 100) + return 8; + return 7; + } + if (SGPRs <= 48) + return 10; + if (SGPRs <= 56) + return 9; + if (SGPRs <= 64) + return 8; + if (SGPRs <= 72) + return 7; + if (SGPRs <= 80) + return 6; + return 5; } unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) { diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index 12d1b3a55ccc..fc4147df76e3 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H +#include "AMDGPUSubtarget.h" #include "SIDefines.h" #include "llvm/IR/CallingConv.h" #include "llvm/IR/InstrTypes.h" @@ -311,6 +312,17 @@ unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU); unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs); +/// \returns Number of waves reachable for a given \p NumVGPRs usage, \p Granule +/// size, \p MaxWaves possible, and \p TotalNumVGPRs available. +unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule, + unsigned MaxWaves, + unsigned TotalNumVGPRs); + +/// \returns Occupancy for a given \p SGPRs usage, \p MaxWaves possible, and \p +/// Gen. +unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves, + AMDGPUSubtarget::Generation Gen); + /// \returns Number of VGPR blocks needed for given subtarget \p STI when /// \p NumVGPRs are used. We actually return the number of blocks -1, since /// that's what we encode. diff --git a/llvm/test/MC/AMDGPU/alignto_mcexpr.s b/llvm/test/MC/AMDGPU/alignto_mcexpr.s new file mode 100644 index 000000000000..e864f3736828 --- /dev/null +++ b/llvm/test/MC/AMDGPU/alignto_mcexpr.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -triple amdgcn-amd-amdhsa < %s | FileCheck --check-prefix=ASM %s + +// ASM: .set alignto_zero_eight, 0 +// ASM: .set alignto_one_eight, 8 +// ASM: .set alignto_five_eight, 8 +// ASM: .set alignto_seven_eight, 8 +// ASM: .set alignto_eight_eight, 8 +// ASM: .set alignto_ten_eight, 16 + +.set alignto_zero_eight, alignto(0, 8) +.set alignto_one_eight, alignto(1, 8) +.set alignto_five_eight, alignto(5, 8) +.set alignto_seven_eight, alignto(7, 8) +.set alignto_eight_eight, alignto(8, 8) +.set alignto_ten_eight, alignto(10, 8) diff --git a/llvm/test/MC/AMDGPU/extrasgprs_mcexpr.s b/llvm/test/MC/AMDGPU/extrasgprs_mcexpr.s new file mode 100644 index 000000000000..e88b23bb34d4 --- /dev/null +++ b/llvm/test/MC/AMDGPU/extrasgprs_mcexpr.s @@ -0,0 +1,31 @@ +// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=bonaire < %s | FileCheck --check-prefix=GFX7 %s +// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck --check-prefix=GFX90A %s +// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx940 < %s | FileCheck --check-prefix=GFX940 %s +// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s + +// gfx940 has architected flat scratch enabled. + +// GFX7: .set extrasgpr_none, 0 +// GFX7: .set extrasgpr_vcc, 2 +// GFX7: .set extrasgpr_flatscr, 4 +// GFX7: .set extrasgpr_xnack, 0 + +// GFX90A: .set extrasgpr_none, 0 +// GFX90A: .set extrasgpr_vcc, 2 +// GFX90A: .set extrasgpr_flatscr, 6 +// GFX90A: .set extrasgpr_xnack, 4 + +// GFX940: .set extrasgpr_none, 6 +// GFX940: .set extrasgpr_vcc, 6 +// GFX940: .set extrasgpr_flatscr, 6 +// GFX940: .set extrasgpr_xnack, 6 + +// GFX10: .set extrasgpr_none, 0 +// GFX10: .set extrasgpr_vcc, 2 +// GFX10: .set extrasgpr_flatscr, 0 +// GFX10: .set extrasgpr_xnack, 0 + +.set extrasgpr_none, extrasgprs(0, 0, 0) +.set extrasgpr_vcc, extrasgprs(1, 0, 0) +.set extrasgpr_flatscr, extrasgprs(0, 1, 0) +.set extrasgpr_xnack, extrasgprs(0, 0, 1) diff --git a/llvm/test/MC/AMDGPU/occupancy_mcexpr.s b/llvm/test/MC/AMDGPU/occupancy_mcexpr.s new file mode 100644 index 000000000000..06bec8c538da --- /dev/null +++ b/llvm/test/MC/AMDGPU/occupancy_mcexpr.s @@ -0,0 +1,61 @@ +// RUN: llvm-mc -triple amdgcn-amd-amdhsa < %s | FileCheck --check-prefix=ASM %s + +// ASM: .set occupancy_init_one, 1 +// ASM: .set occupancy_init_seven, 7 +// ASM: .set occupancy_init_eight, 8 + +.set occupancy_init_one, occupancy(0, 0, 0, 0, 1, 0, 0) +.set occupancy_init_seven, occupancy(0, 0, 0, 0, 7, 0, 0) +.set occupancy_init_eight, occupancy(0, 0, 0, 0, 8, 0, 0) + +// ASM: .set occupancy_numsgpr_seaisle_ten, 10 +// ASM: .set occupancy_numsgpr_seaisle_nine, 9 +// ASM: .set occupancy_numsgpr_seaisle_eight, 8 +// ASM: .set occupancy_numsgpr_seaisle_seven, 7 +// ASM: .set occupancy_numsgpr_seaisle_six, 6 +// ASM: .set occupancy_numsgpr_seaisle_five, 5 + +.set occupancy_numsgpr_seaisle_ten, occupancy(0, 0, 0, 6, 11, 1, 0) +.set occupancy_numsgpr_seaisle_nine, occupancy(0, 0, 0, 6, 11, 49, 0) +.set occupancy_numsgpr_seaisle_eight, occupancy(0, 0, 0, 6, 11, 57, 0) +.set occupancy_numsgpr_seaisle_seven, occupancy(0, 0, 0, 6, 11, 65, 0) +.set occupancy_numsgpr_seaisle_six, occupancy(0, 0, 0, 6, 11, 73, 0) +.set occupancy_numsgpr_seaisle_five, occupancy(0, 0, 0, 6, 11, 81, 0) + +// ASM: .set occupancy_numsgpr_gfx9_ten, 10 +// ASM: .set occupancy_numsgpr_gfx9_nine, 9 +// ASM: .set occupancy_numsgpr_gfx9_eight, 8 +// ASM: .set occupancy_numsgpr_gfx9_seven, 7 + +.set occupancy_numsgpr_gfx9_ten, occupancy(0, 0, 0, 8, 11, 1, 0) +.set occupancy_numsgpr_gfx9_nine, occupancy(0, 0, 0, 8, 11, 81, 0) +.set occupancy_numsgpr_gfx9_eight, occupancy(0, 0, 0, 8, 11, 89, 0) +.set occupancy_numsgpr_gfx9_seven, occupancy(0, 0, 0, 8, 11, 101, 0) + +// ASM: .set occupancy_numsgpr_gfx10_one, 1 +// ASM: .set occupancy_numsgpr_gfx10_seven, 7 +// ASM: .set occupancy_numsgpr_gfx10_eight, 8 + +.set occupancy_numsgpr_gfx10_one, occupancy(1, 0, 0, 9, 11, 1, 0) +.set occupancy_numsgpr_gfx10_seven, occupancy(7, 0, 0, 9, 11, 1, 0) +.set occupancy_numsgpr_gfx10_eight, occupancy(8, 0, 0, 9, 11, 1, 0) + +// ASM: .set occupancy_numvgpr_high_granule_one, 1 +// ASM: .set occupancy_numvgpr_high_granule_seven, 7 +// ASM: .set occupancy_numvgpr_high_granule_eight, 8 + +.set occupancy_numvgpr_high_granule_one, occupancy(1, 2, 0, 0, 11, 0, 1) +.set occupancy_numvgpr_high_granule_seven, occupancy(7, 2, 0, 0, 11, 0, 1) +.set occupancy_numvgpr_high_granule_eight, occupancy(8, 2, 0, 0, 11, 0, 1) + +// ASM: .set occupancy_numvgpr_low_total_one, 1 +// ASM: .set occupancy_numvgpr_one, 1 +// ASM: .set occupancy_numvgpr_seven, 7 +// ASM: .set occupancy_numvgpr_eight, 8 +// ASM: .set occupancy_numvgpr_ten, 10 + +.set occupancy_numvgpr_low_total_one, occupancy(11, 4, 2, 0, 11, 0, 4) +.set occupancy_numvgpr_one, occupancy(11, 4, 4, 0, 11, 0, 4) +.set occupancy_numvgpr_seven, occupancy(11, 4, 28, 0, 11, 0, 4) +.set occupancy_numvgpr_eight, occupancy(11, 4, 32, 0, 11, 0, 4) +.set occupancy_numvgpr_ten, occupancy(11, 4, 40, 0, 11, 0, 4) diff --git a/llvm/test/MC/AMDGPU/totalnumvgpr_mcexpr.s b/llvm/test/MC/AMDGPU/totalnumvgpr_mcexpr.s new file mode 100644 index 000000000000..29bb885b2080 --- /dev/null +++ b/llvm/test/MC/AMDGPU/totalnumvgpr_mcexpr.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck --check-prefix=GFX90A %s +// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s + +// GFX10: .set totalvgpr_none, 0 +// GFX10: .set totalvgpr_one, 1 +// GFX10: .set totalvgpr_two, 2 + +.set totalvgpr_none, totalnumvgprs(0, 0) +.set totalvgpr_one, totalnumvgprs(1, 0) +.set totalvgpr_two, totalnumvgprs(1, 2) + +// GFX90A: .set totalvgpr90a_none, 0 +// GFX90A: .set totalvgpr90a_one, 1 +// GFX90A: .set totalvgpr90a_two, 2 + +.set totalvgpr90a_none, totalnumvgprs(0, 0) +.set totalvgpr90a_one, totalnumvgprs(0, 1) +.set totalvgpr90a_two, totalnumvgprs(0, 2) + +// GFX90A: .set totalvgpr90a_agpr_minimal, 1 +// GFX90A: .set totalvgpr90a_agpr_rounded_eight, 8 +// GFX90A: .set totalvgpr90a_agpr_exact_eight, 8 + +.set totalvgpr90a_agpr_minimal, totalnumvgprs(1, 0) +.set totalvgpr90a_agpr_rounded_eight, totalnumvgprs(4, 2) +.set totalvgpr90a_agpr_exact_eight, totalnumvgprs(4, 4) diff --git a/llvm/unittests/MC/AMDGPU/CMakeLists.txt b/llvm/unittests/MC/AMDGPU/CMakeLists.txt index 06ca89a72a7c..be8ff572e6f7 100644 --- a/llvm/unittests/MC/AMDGPU/CMakeLists.txt +++ b/llvm/unittests/MC/AMDGPU/CMakeLists.txt @@ -1,12 +1,20 @@ +include_directories( + ${PROJECT_SOURCE_DIR}/lib/Target/AMDGPU + ${PROJECT_BINARY_DIR}/lib/Target/AMDGPU + ) + set(LLVM_LINK_COMPONENTS AMDGPUCodeGen AMDGPUDesc AMDGPUInfo + CodeGen + Core MC Support TargetParser ) -add_llvm_unittest(AMDGPUDwarfTests +add_llvm_unittest(AMDGPUMCTests DwarfRegMappings.cpp + SIProgramInfoMCExprs.cpp ) diff --git a/llvm/unittests/MC/AMDGPU/SIProgramInfoMCExprs.cpp b/llvm/unittests/MC/AMDGPU/SIProgramInfoMCExprs.cpp new file mode 100644 index 000000000000..f2161f71e6e9 --- /dev/null +++ b/llvm/unittests/MC/AMDGPU/SIProgramInfoMCExprs.cpp @@ -0,0 +1,81 @@ +//===- llvm/unittests/MC/AMDGPU/SIProgramInfoMCExprs.cpp ------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "AMDGPUHSAMetadataStreamer.h" +#include "AMDGPUTargetMachine.h" +#include "GCNSubtarget.h" +#include "SIProgramInfo.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCTargetOptions.h" +#include "llvm/MC/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" +#include "llvm/Target/TargetMachine.h" +#include "gtest/gtest.h" + +using namespace llvm; + +class SIProgramInfoMCExprsTest : public testing::Test { +protected: + std::unique_ptr TM; + std::unique_ptr Ctx; + std::unique_ptr ST; + std::unique_ptr MMI; + std::unique_ptr MF; + std::unique_ptr M; + + SIProgramInfo PI; + + static void SetUpTestSuite() { + LLVMInitializeAMDGPUTargetInfo(); + LLVMInitializeAMDGPUTarget(); + LLVMInitializeAMDGPUTargetMC(); + } + + SIProgramInfoMCExprsTest() { + std::string Triple = "amdgcn-amd-amdhsa"; + std::string CPU = "gfx1010"; + std::string FS = ""; + + std::string Error; + const Target *TheTarget = TargetRegistry::lookupTarget(Triple, Error); + TargetOptions Options; + + TM.reset(static_cast(TheTarget->createTargetMachine( + Triple, CPU, FS, Options, std::nullopt, std::nullopt))); + + Ctx = std::make_unique(); + M = std::make_unique("Module", *Ctx); + M->setDataLayout(TM->createDataLayout()); + auto *FType = FunctionType::get(Type::getVoidTy(*Ctx), false); + auto *F = Function::Create(FType, GlobalValue::ExternalLinkage, "Test", *M); + MMI = std::make_unique(TM.get()); + + ST = std::make_unique(TM->getTargetTriple(), + TM->getTargetCPU(), + TM->getTargetFeatureString(), *TM); + + MF = std::make_unique(*F, *TM, *ST, 1, *MMI); + PI.reset(*MF.get()); + } +}; + +TEST_F(SIProgramInfoMCExprsTest, TestDeathHSAKernelEmit) { + MCContext &Ctx = MF->getContext(); + MCSymbol *Sym = Ctx.getOrCreateSymbol("Unknown"); + PI.ScratchSize = MCSymbolRefExpr::create(Sym, Ctx); + + auto &Func = MF->getFunction(); + Func.setCallingConv(CallingConv::AMDGPU_KERNEL); + AMDGPU::HSAMD::MetadataStreamerMsgPackV4 MD; + EXPECT_DEATH(MD.emitKernel(*MF, PI), + "could not resolve expression when required."); +} -- GitLab From e5e66073c3d404f4dedf1b0be160b7815ccf8903 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Thu, 9 May 2024 07:04:48 -0500 Subject: [PATCH 132/328] Revert "[Libomptarget] Statically link all plugin runtimes (#87009)" Caused failures on build-bots, reverting to investigate. This reverts commit 80f9e814ec896fdc57ee84afad8ac4cb1f8e4627. --- clang/test/Driver/linker-wrapper-image.c | 2 +- .../Frontend/Offloading/OffloadWrapper.cpp | 7 +- offload/include/PluginManager.h | 61 ++++-- offload/include/device.h | 8 +- offload/plugins-nextgen/CMakeLists.txt | 19 +- offload/plugins-nextgen/amdgpu/CMakeLists.txt | 5 + offload/plugins-nextgen/amdgpu/src/rtl.cpp | 14 +- offload/plugins-nextgen/common/CMakeLists.txt | 5 +- .../common/include/PluginInterface.h | 94 +++++++- .../common/include/Utils/ELF.h | 2 + offload/plugins-nextgen/common/src/JIT.cpp | 40 ++-- .../common/src/PluginInterface.cpp | 205 ++++++++++++++++++ offload/plugins-nextgen/cuda/CMakeLists.txt | 5 + offload/plugins-nextgen/cuda/src/rtl.cpp | 14 +- offload/plugins-nextgen/host/CMakeLists.txt | 8 + offload/plugins-nextgen/host/src/rtl.cpp | 14 +- offload/src/CMakeLists.txt | 4 - offload/src/OffloadRTL.cpp | 1 - offload/src/OpenMP/InteropAPI.cpp | 4 +- offload/src/PluginManager.cpp | 129 +++++++---- offload/src/device.cpp | 3 +- offload/src/interface.cpp | 2 + .../kernelreplay/llvm-omp-kernel-replay.cpp | 2 + .../unittests/Plugins/NextgenPluginsTest.cpp | 1 + 24 files changed, 524 insertions(+), 125 deletions(-) diff --git a/clang/test/Driver/linker-wrapper-image.c b/clang/test/Driver/linker-wrapper-image.c index 5d5d62805e17..d01445e3aed0 100644 --- a/clang/test/Driver/linker-wrapper-image.c +++ b/clang/test/Driver/linker-wrapper-image.c @@ -30,8 +30,8 @@ // OPENMP: define internal void @.omp_offloading.descriptor_reg() section ".text.startup" { // OPENMP-NEXT: entry: -// OPENMP-NEXT: call void @__tgt_register_lib(ptr @.omp_offloading.descriptor) // OPENMP-NEXT: %0 = call i32 @atexit(ptr @.omp_offloading.descriptor_unreg) +// OPENMP-NEXT: call void @__tgt_register_lib(ptr @.omp_offloading.descriptor) // OPENMP-NEXT: ret void // OPENMP-NEXT: } diff --git a/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp b/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp index 8b6f9ea1f4cc..7241d15ed1c6 100644 --- a/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp +++ b/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp @@ -232,13 +232,12 @@ void createRegisterFunction(Module &M, GlobalVariable *BinDesc, // Construct function body IRBuilder<> Builder(BasicBlock::Create(C, "entry", Func)); - Builder.CreateCall(RegFuncC, BinDesc); - // Register the destructors with 'atexit'. This is expected by the CUDA // runtime and ensures that we clean up before dynamic objects are destroyed. - // This needs to be done after plugin initialization to ensure that it is - // called before the plugin runtime is destroyed. + // This needs to be done before the runtime is called and registers its own. Builder.CreateCall(AtExit, UnregFunc); + + Builder.CreateCall(RegFuncC, BinDesc); Builder.CreateRetVoid(); // Add this function to constructors. diff --git a/offload/include/PluginManager.h b/offload/include/PluginManager.h index 1d6804da75d9..eece7525e25e 100644 --- a/offload/include/PluginManager.h +++ b/offload/include/PluginManager.h @@ -13,11 +13,10 @@ #ifndef OMPTARGET_PLUGIN_MANAGER_H #define OMPTARGET_PLUGIN_MANAGER_H -#include "PluginInterface.h" - #include "DeviceImage.h" #include "ExclusiveAccess.h" #include "Shared/APITypes.h" +#include "Shared/PluginAPI.h" #include "Shared/Requirements.h" #include "device.h" @@ -35,7 +34,38 @@ #include #include -using GenericPluginTy = llvm::omp::target::plugin::GenericPluginTy; +struct PluginManager; + +/// Plugin adaptors should be created via `PluginAdaptorTy::create` which will +/// invoke the constructor and call `PluginAdaptorTy::init`. Eventual errors are +/// reported back to the caller, otherwise a valid and initialized adaptor is +/// returned. +struct PluginAdaptorTy { + /// Try to create a plugin adaptor from a filename. + static llvm::Expected> + create(const std::string &Name); + + /// Name of the shared object file representing the plugin. + std::string Name; + + /// Access to the shared object file representing the plugin. + std::unique_ptr LibraryHandler; + +#define PLUGIN_API_HANDLE(NAME) \ + using NAME##_ty = decltype(__tgt_rtl_##NAME); \ + NAME##_ty *NAME = nullptr; + +#include "Shared/PluginAPI.inc" +#undef PLUGIN_API_HANDLE + + /// Create a plugin adaptor for filename \p Name with a dynamic library \p DL. + PluginAdaptorTy(const std::string &Name, + std::unique_ptr DL); + + /// Initialize the plugin adaptor, this can fail in which case the adaptor is + /// useless. + llvm::Error init(); +}; /// Struct for the data required to handle plugins struct PluginManager { @@ -50,8 +80,6 @@ struct PluginManager { void init(); - void deinit(); - // Register a shared library with all (compatible) RTLs. void registerLib(__tgt_bin_desc *Desc); @@ -64,9 +92,10 @@ struct PluginManager { std::make_unique(TgtBinDesc, TgtDeviceImage)); } - /// Initialize as many devices as possible for this plugin. Devices that fail - /// to initialize are ignored. - void initDevices(GenericPluginTy &RTL); + /// Initialize as many devices as possible for this plugin adaptor. Devices + /// that fail to initialize are ignored. Returns the offset the devices were + /// registered at. + void initDevices(PluginAdaptorTy &RTL); /// Return the device presented to the user as device \p DeviceNo if it is /// initialized and ready. Otherwise return an error explaining the problem. @@ -122,8 +151,8 @@ struct PluginManager { // Initialize all plugins. void initAllPlugins(); - /// Iterator range for all plugins (in use or not, but always valid). - auto plugins() { return llvm::make_pointee_range(Plugins); } + /// Iterator range for all plugin adaptors (in use or not, but always valid). + auto pluginAdaptors() { return llvm::make_pointee_range(PluginAdaptors); } /// Return the user provided requirements. int64_t getRequirements() const { return Requirements.getRequirements(); } @@ -135,14 +164,14 @@ private: bool RTLsLoaded = false; llvm::SmallVector<__tgt_bin_desc *> DelayedBinDesc; - // List of all plugins, in use or not. - llvm::SmallVector> Plugins; + // List of all plugin adaptors, in use or not. + llvm::SmallVector> PluginAdaptors; - // Mapping of plugins to offsets in the device table. - llvm::DenseMap DeviceOffsets; + // Mapping of plugin adaptors to offsets in the device table. + llvm::DenseMap DeviceOffsets; - // Mapping of plugins to the number of used devices. - llvm::DenseMap DeviceUsed; + // Mapping of plugin adaptors to the number of used devices. + llvm::DenseMap DeviceUsed; // Set of all device images currently in use. llvm::DenseSet UsedImages; diff --git a/offload/include/device.h b/offload/include/device.h index fd6e5fba5fc5..bd2829722bb3 100644 --- a/offload/include/device.h +++ b/offload/include/device.h @@ -33,19 +33,17 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" -#include "PluginInterface.h" -using GenericPluginTy = llvm::omp::target::plugin::GenericPluginTy; - // Forward declarations. +struct PluginAdaptorTy; struct __tgt_bin_desc; struct __tgt_target_table; struct DeviceTy { int32_t DeviceID; - GenericPluginTy *RTL; + PluginAdaptorTy *RTL; int32_t RTLDeviceID; - DeviceTy(GenericPluginTy *RTL, int32_t DeviceID, int32_t RTLDeviceID); + DeviceTy(PluginAdaptorTy *RTL, int32_t DeviceID, int32_t RTLDeviceID); // DeviceTy is not copyable DeviceTy(const DeviceTy &D) = delete; DeviceTy &operator=(const DeviceTy &D) = delete; diff --git a/offload/plugins-nextgen/CMakeLists.txt b/offload/plugins-nextgen/CMakeLists.txt index d1079f8a3e9c..df625e97c7eb 100644 --- a/offload/plugins-nextgen/CMakeLists.txt +++ b/offload/plugins-nextgen/CMakeLists.txt @@ -14,7 +14,7 @@ set(common_dir ${CMAKE_CURRENT_SOURCE_DIR}/common) add_subdirectory(common) function(add_target_library target_name lib_name) - add_llvm_library(${target_name} STATIC + add_llvm_library(${target_name} SHARED LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD} AggressiveInstCombine @@ -46,14 +46,27 @@ function(add_target_library target_name lib_name) ) llvm_update_compile_flags(${target_name}) - target_include_directories(${target_name} PUBLIC ${common_dir}/include) target_link_libraries(${target_name} PRIVATE PluginCommon ${OPENMP_PTHREAD_LIB}) target_compile_definitions(${target_name} PRIVATE TARGET_NAME=${lib_name}) target_compile_definitions(${target_name} PRIVATE DEBUG_PREFIX="TARGET ${lib_name} RTL") - set_target_properties(${target_name} PROPERTIES POSITION_INDEPENDENT_CODE ON) + + if(CMAKE_SYSTEM_NAME MATCHES "FreeBSD") + # On FreeBSD, the 'environ' symbol is undefined at link time, but resolved by + # the dynamic linker at runtime. Therefore, allow the symbol to be undefined + # when creating a shared library. + target_link_libraries(${target_name} PRIVATE "-Wl,--allow-shlib-undefined") + else() + target_link_libraries(${target_name} PRIVATE "-Wl,-z,defs") + endif() + + if(LIBOMP_HAVE_VERSION_SCRIPT_FLAG) + target_link_libraries(${target_name} PRIVATE + "-Wl,--version-script=${common_dir}/../exports") + endif() + set_target_properties(${target_name} PROPERTIES CXX_VISIBILITY_PRESET protected) endfunction() foreach(plugin IN LISTS LIBOMPTARGET_PLUGINS_TO_BUILD) diff --git a/offload/plugins-nextgen/amdgpu/CMakeLists.txt b/offload/plugins-nextgen/amdgpu/CMakeLists.txt index 738183f8945e..f5f7096137c2 100644 --- a/offload/plugins-nextgen/amdgpu/CMakeLists.txt +++ b/offload/plugins-nextgen/amdgpu/CMakeLists.txt @@ -57,3 +57,8 @@ else() libomptarget_say("Not generating AMDGPU tests, no supported devices detected." " Use 'LIBOMPTARGET_FORCE_AMDGPU_TESTS' to override.") endif() + +# Install plugin under the lib destination folder. +install(TARGETS omptarget.rtl.amdgpu LIBRARY DESTINATION "${OFFLOAD_INSTALL_LIBDIR}") +set_target_properties(omptarget.rtl.amdgpu PROPERTIES + INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/..") diff --git a/offload/plugins-nextgen/amdgpu/src/rtl.cpp b/offload/plugins-nextgen/amdgpu/src/rtl.cpp index 295685fceaa4..00650b801b42 100644 --- a/offload/plugins-nextgen/amdgpu/src/rtl.cpp +++ b/offload/plugins-nextgen/amdgpu/src/rtl.cpp @@ -3064,6 +3064,10 @@ struct AMDGPUPluginTy final : public GenericPluginTy { // HSA functions from now on, e.g., hsa_shut_down. Initialized = true; +#ifdef OMPT_SUPPORT + ompt::connectLibrary(); +#endif + // Register event handler to detect memory errors on the devices. Status = hsa_amd_register_system_event_handler(eventHandler, nullptr); if (auto Err = Plugin::check( @@ -3151,8 +3155,6 @@ struct AMDGPUPluginTy final : public GenericPluginTy { Triple::ArchType getTripleArch() const override { return Triple::amdgcn; } - const char *getName() const override { return GETNAME(TARGET_NAME); } - /// Get the ELF code for recognizing the compatible image binary. uint16_t getMagicElfBits() const override { return ELF::EM_AMDGPU; } @@ -3385,6 +3387,8 @@ Error AMDGPUKernelTy::printLaunchInfoDetails(GenericDeviceTy &GenericDevice, return Plugin::success(); } +GenericPluginTy *PluginTy::createPlugin() { return new AMDGPUPluginTy(); } + template static Error Plugin::check(int32_t Code, const char *ErrFmt, ArgsTy... Args) { hsa_status_t ResultCode = static_cast(Code); @@ -3472,9 +3476,3 @@ void *AMDGPUDeviceTy::allocate(size_t Size, void *, TargetAllocTy Kind) { } // namespace target } // namespace omp } // namespace llvm - -extern "C" { -llvm::omp::target::plugin::GenericPluginTy *createPlugin_amdgpu() { - return new llvm::omp::target::plugin::AMDGPUPluginTy(); -} -} diff --git a/offload/plugins-nextgen/common/CMakeLists.txt b/offload/plugins-nextgen/common/CMakeLists.txt index a6bbb7e9454b..acf0af63f050 100644 --- a/offload/plugins-nextgen/common/CMakeLists.txt +++ b/offload/plugins-nextgen/common/CMakeLists.txt @@ -46,6 +46,7 @@ endif() # If we have OMPT enabled include it in the list of sources. if (OMPT_TARGET_DEFAULT AND LIBOMPTARGET_OMPT_SUPPORT) + target_sources(PluginCommon PRIVATE OMPT/OmptCallback.cpp) target_include_directories(PluginCommon PRIVATE OMPT) endif() @@ -65,4 +66,6 @@ target_include_directories(PluginCommon PUBLIC ${LIBOMPTARGET_INCLUDE_DIR} ) -set_target_properties(PluginCommon PROPERTIES POSITION_INDEPENDENT_CODE ON) +set_target_properties(PluginCommon PROPERTIES + POSITION_INDEPENDENT_CODE ON + CXX_VISIBILITY_PRESET protected) diff --git a/offload/plugins-nextgen/common/include/PluginInterface.h b/offload/plugins-nextgen/common/include/PluginInterface.h index e7a008f3a857..79e8464bfda5 100644 --- a/offload/plugins-nextgen/common/include/PluginInterface.h +++ b/offload/plugins-nextgen/common/include/PluginInterface.h @@ -1010,9 +1010,6 @@ struct GenericPluginTy { /// Get the target triple of this plugin. virtual Triple::ArchType getTripleArch() const = 0; - /// Get the constant name identifier for this plugin. - virtual const char *getName() const = 0; - /// Allocate a structure using the internal allocator. template Ty *allocate() { return reinterpret_cast(Allocator.Allocate(sizeof(Ty), alignof(Ty))); @@ -1229,7 +1226,7 @@ namespace Plugin { /// Create a success error. This is the same as calling Error::success(), but /// it is recommended to use this one for consistency with Plugin::error() and /// Plugin::check(). -static inline Error success() { return Error::success(); } +static Error success() { return Error::success(); } /// Create a string error. template @@ -1249,6 +1246,95 @@ template static Error check(int32_t ErrorCode, const char *ErrFmt, ArgsTy... Args); } // namespace Plugin +/// Class for simplifying the getter operation of the plugin. Anywhere on the +/// code, the current plugin can be retrieved by Plugin::get(). The class also +/// declares functions to create plugin-specific object instances. The check(), +/// createPlugin(), createDevice() and createGlobalHandler() functions should be +/// defined by each plugin implementation. +class PluginTy { + // Reference to the plugin instance. + static GenericPluginTy *SpecificPlugin; + + PluginTy() { + if (auto Err = init()) + REPORT("Failed to initialize plugin: %s\n", + toString(std::move(Err)).data()); + } + + ~PluginTy() { + if (auto Err = deinit()) + REPORT("Failed to deinitialize plugin: %s\n", + toString(std::move(Err)).data()); + } + + PluginTy(const PluginTy &) = delete; + void operator=(const PluginTy &) = delete; + + /// Create and intialize the plugin instance. + static Error init() { + assert(!SpecificPlugin && "Plugin already created"); + + // Create the specific plugin. + SpecificPlugin = createPlugin(); + assert(SpecificPlugin && "Plugin was not created"); + + // Initialize the plugin. + return SpecificPlugin->init(); + } + + // Deinitialize and destroy the plugin instance. + static Error deinit() { + assert(SpecificPlugin && "Plugin no longer valid"); + + for (int32_t DevNo = 0, NumDev = SpecificPlugin->getNumDevices(); + DevNo < NumDev; ++DevNo) + if (auto Err = SpecificPlugin->deinitDevice(DevNo)) + return Err; + + // Deinitialize the plugin. + if (auto Err = SpecificPlugin->deinit()) + return Err; + + // Delete the plugin instance. + delete SpecificPlugin; + + // Invalidate the plugin reference. + SpecificPlugin = nullptr; + + return Plugin::success(); + } + +public: + /// Initialize the plugin if needed. The plugin could have been initialized by + /// a previous call to Plugin::get(). + static Error initIfNeeded() { + // Trigger the initialization if needed. + get(); + + return Error::success(); + } + + /// Get a reference (or create if it was not created) to the plugin instance. + static GenericPluginTy &get() { + // This static variable will initialize the underlying plugin instance in + // case there was no previous explicit initialization. The initialization is + // thread safe. + static PluginTy Plugin; + + assert(SpecificPlugin && "Plugin is not active"); + return *SpecificPlugin; + } + + /// Get a reference to the plugin with a specific plugin-specific type. + template static Ty &get() { return static_cast(get()); } + + /// Indicate whether the plugin is active. + static bool isActive() { return SpecificPlugin != nullptr; } + + /// Create a plugin instance. + static GenericPluginTy *createPlugin(); +}; + /// Auxiliary interface class for GenericDeviceResourceManagerTy. This class /// acts as a reference to a device resource, such as a stream, and requires /// some basic functions to be implemented. The derived class should define an diff --git a/offload/plugins-nextgen/common/include/Utils/ELF.h b/offload/plugins-nextgen/common/include/Utils/ELF.h index dcfdb5bd7b03..f87e0a5ed02b 100644 --- a/offload/plugins-nextgen/common/include/Utils/ELF.h +++ b/offload/plugins-nextgen/common/include/Utils/ELF.h @@ -13,6 +13,8 @@ #ifndef LLVM_OPENMP_LIBOMPTARGET_PLUGINS_ELF_UTILS_H #define LLVM_OPENMP_LIBOMPTARGET_PLUGINS_ELF_UTILS_H +#include "Shared/PluginAPI.h" + #include "llvm/Object/ELF.h" #include "llvm/Object/ELFObjectFile.h" diff --git a/offload/plugins-nextgen/common/src/JIT.cpp b/offload/plugins-nextgen/common/src/JIT.cpp index 9d58e6060646..9eb610cab4de 100644 --- a/offload/plugins-nextgen/common/src/JIT.cpp +++ b/offload/plugins-nextgen/common/src/JIT.cpp @@ -56,6 +56,28 @@ bool isImageBitcode(const __tgt_device_image &Image) { return identify_magic(Binary) == file_magic::bitcode; } +std::once_flag InitFlag; + +void init(Triple TT) { + codegen::RegisterCodeGenFlags(); +#ifdef LIBOMPTARGET_JIT_NVPTX + if (TT.isNVPTX()) { + LLVMInitializeNVPTXTargetInfo(); + LLVMInitializeNVPTXTarget(); + LLVMInitializeNVPTXTargetMC(); + LLVMInitializeNVPTXAsmPrinter(); + } +#endif +#ifdef LIBOMPTARGET_JIT_AMDGPU + if (TT.isAMDGPU()) { + LLVMInitializeAMDGPUTargetInfo(); + LLVMInitializeAMDGPUTarget(); + LLVMInitializeAMDGPUTargetMC(); + LLVMInitializeAMDGPUAsmPrinter(); + } +#endif +} + Expected> createModuleFromMemoryBuffer(std::unique_ptr &MB, LLVMContext &Context) { @@ -126,23 +148,7 @@ createTargetMachine(Module &M, std::string CPU, unsigned OptLevel) { } // namespace JITEngine::JITEngine(Triple::ArchType TA) : TT(Triple::getArchTypeName(TA)) { - codegen::RegisterCodeGenFlags(); -#ifdef LIBOMPTARGET_JIT_NVPTX - if (TT.isNVPTX()) { - LLVMInitializeNVPTXTargetInfo(); - LLVMInitializeNVPTXTarget(); - LLVMInitializeNVPTXTargetMC(); - LLVMInitializeNVPTXAsmPrinter(); - } -#endif -#ifdef LIBOMPTARGET_JIT_AMDGPU - if (TT.isAMDGPU()) { - LLVMInitializeAMDGPUTargetInfo(); - LLVMInitializeAMDGPUTarget(); - LLVMInitializeAMDGPUTargetMC(); - LLVMInitializeAMDGPUAsmPrinter(); - } -#endif + std::call_once(InitFlag, init, TT); } void JITEngine::opt(TargetMachine *TM, TargetLibraryInfoImpl *TLII, Module &M, diff --git a/offload/plugins-nextgen/common/src/PluginInterface.cpp b/offload/plugins-nextgen/common/src/PluginInterface.cpp index fae197527850..8de93ba17a56 100644 --- a/offload/plugins-nextgen/common/src/PluginInterface.cpp +++ b/offload/plugins-nextgen/common/src/PluginInterface.cpp @@ -13,6 +13,7 @@ #include "Shared/APITypes.h" #include "Shared/Debug.h" #include "Shared/Environment.h" +#include "Shared/PluginAPI.h" #include "GlobalHandler.h" #include "JIT.h" @@ -38,6 +39,8 @@ using namespace omp; using namespace target; using namespace plugin; +GenericPluginTy *PluginTy::SpecificPlugin = nullptr; + // TODO: Fix any thread safety issues for multi-threaded kernel recording. struct RecordReplayTy { @@ -2032,3 +2035,205 @@ bool llvm::omp::target::plugin::libomptargetSupportsRPC() { return false; #endif } + +/// Exposed library API function, basically wrappers around the GenericDeviceTy +/// functionality with the same name. All non-async functions are redirected +/// to the async versions right away with a NULL AsyncInfoPtr. +#ifdef __cplusplus +extern "C" { +#endif + +int32_t __tgt_rtl_init_plugin() { + auto Err = PluginTy::initIfNeeded(); + if (Err) { + [[maybe_unused]] std::string ErrStr = toString(std::move(Err)); + DP("Failed to init plugin: %s", ErrStr.c_str()); + return OFFLOAD_FAIL; + } + + return OFFLOAD_SUCCESS; +} + +int32_t __tgt_rtl_is_valid_binary(__tgt_device_image *Image) { + if (!PluginTy::isActive()) + return false; + + return PluginTy::get().is_valid_binary(Image); +} + +int32_t __tgt_rtl_init_device(int32_t DeviceId) { + return PluginTy::get().init_device(DeviceId); +} + +int32_t __tgt_rtl_number_of_devices() { + return PluginTy::get().number_of_devices(); +} + +int64_t __tgt_rtl_init_requires(int64_t RequiresFlags) { + return PluginTy::get().init_requires(RequiresFlags); +} + +int32_t __tgt_rtl_is_data_exchangable(int32_t SrcDeviceId, + int32_t DstDeviceId) { + return PluginTy::get().is_data_exchangable(SrcDeviceId, DstDeviceId); +} + +int32_t __tgt_rtl_initialize_record_replay(int32_t DeviceId, int64_t MemorySize, + void *VAddr, bool isRecord, + bool SaveOutput, + uint64_t &ReqPtrArgOffset) { + return PluginTy::get().initialize_record_replay( + DeviceId, MemorySize, VAddr, isRecord, SaveOutput, ReqPtrArgOffset); +} + +int32_t __tgt_rtl_load_binary(int32_t DeviceId, __tgt_device_image *TgtImage, + __tgt_device_binary *Binary) { + return PluginTy::get().load_binary(DeviceId, TgtImage, Binary); +} + +void *__tgt_rtl_data_alloc(int32_t DeviceId, int64_t Size, void *HostPtr, + int32_t Kind) { + return PluginTy::get().data_alloc(DeviceId, Size, HostPtr, Kind); +} + +int32_t __tgt_rtl_data_delete(int32_t DeviceId, void *TgtPtr, int32_t Kind) { + return PluginTy::get().data_delete(DeviceId, TgtPtr, Kind); +} + +int32_t __tgt_rtl_data_lock(int32_t DeviceId, void *Ptr, int64_t Size, + void **LockedPtr) { + return PluginTy::get().data_lock(DeviceId, Ptr, Size, LockedPtr); +} + +int32_t __tgt_rtl_data_unlock(int32_t DeviceId, void *Ptr) { + return PluginTy::get().data_unlock(DeviceId, Ptr); +} + +int32_t __tgt_rtl_data_notify_mapped(int32_t DeviceId, void *HstPtr, + int64_t Size) { + return PluginTy::get().data_notify_mapped(DeviceId, HstPtr, Size); +} + +int32_t __tgt_rtl_data_notify_unmapped(int32_t DeviceId, void *HstPtr) { + return PluginTy::get().data_notify_unmapped(DeviceId, HstPtr); +} + +int32_t __tgt_rtl_data_submit(int32_t DeviceId, void *TgtPtr, void *HstPtr, + int64_t Size) { + return PluginTy::get().data_submit(DeviceId, TgtPtr, HstPtr, Size); +} + +int32_t __tgt_rtl_data_submit_async(int32_t DeviceId, void *TgtPtr, + void *HstPtr, int64_t Size, + __tgt_async_info *AsyncInfoPtr) { + return PluginTy::get().data_submit_async(DeviceId, TgtPtr, HstPtr, Size, + AsyncInfoPtr); +} + +int32_t __tgt_rtl_data_retrieve(int32_t DeviceId, void *HstPtr, void *TgtPtr, + int64_t Size) { + return PluginTy::get().data_retrieve(DeviceId, HstPtr, TgtPtr, Size); +} + +int32_t __tgt_rtl_data_retrieve_async(int32_t DeviceId, void *HstPtr, + void *TgtPtr, int64_t Size, + __tgt_async_info *AsyncInfoPtr) { + return PluginTy::get().data_retrieve_async(DeviceId, HstPtr, TgtPtr, Size, + AsyncInfoPtr); +} + +int32_t __tgt_rtl_data_exchange(int32_t SrcDeviceId, void *SrcPtr, + int32_t DstDeviceId, void *DstPtr, + int64_t Size) { + return PluginTy::get().data_exchange(SrcDeviceId, SrcPtr, DstDeviceId, DstPtr, + Size); +} + +int32_t __tgt_rtl_data_exchange_async(int32_t SrcDeviceId, void *SrcPtr, + int DstDeviceId, void *DstPtr, + int64_t Size, + __tgt_async_info *AsyncInfo) { + return PluginTy::get().data_exchange_async(SrcDeviceId, SrcPtr, DstDeviceId, + DstPtr, Size, AsyncInfo); +} + +int32_t __tgt_rtl_launch_kernel(int32_t DeviceId, void *TgtEntryPtr, + void **TgtArgs, ptrdiff_t *TgtOffsets, + KernelArgsTy *KernelArgs, + __tgt_async_info *AsyncInfoPtr) { + return PluginTy::get().launch_kernel(DeviceId, TgtEntryPtr, TgtArgs, + TgtOffsets, KernelArgs, AsyncInfoPtr); +} + +int32_t __tgt_rtl_synchronize(int32_t DeviceId, + __tgt_async_info *AsyncInfoPtr) { + return PluginTy::get().synchronize(DeviceId, AsyncInfoPtr); +} + +int32_t __tgt_rtl_query_async(int32_t DeviceId, + __tgt_async_info *AsyncInfoPtr) { + return PluginTy::get().query_async(DeviceId, AsyncInfoPtr); +} + +void __tgt_rtl_print_device_info(int32_t DeviceId) { + PluginTy::get().print_device_info(DeviceId); +} + +int32_t __tgt_rtl_create_event(int32_t DeviceId, void **EventPtr) { + return PluginTy::get().create_event(DeviceId, EventPtr); +} + +int32_t __tgt_rtl_record_event(int32_t DeviceId, void *EventPtr, + __tgt_async_info *AsyncInfoPtr) { + return PluginTy::get().record_event(DeviceId, EventPtr, AsyncInfoPtr); +} + +int32_t __tgt_rtl_wait_event(int32_t DeviceId, void *EventPtr, + __tgt_async_info *AsyncInfoPtr) { + return PluginTy::get().wait_event(DeviceId, EventPtr, AsyncInfoPtr); +} + +int32_t __tgt_rtl_sync_event(int32_t DeviceId, void *EventPtr) { + return PluginTy::get().sync_event(DeviceId, EventPtr); +} + +int32_t __tgt_rtl_destroy_event(int32_t DeviceId, void *EventPtr) { + return PluginTy::get().destroy_event(DeviceId, EventPtr); +} + +void __tgt_rtl_set_info_flag(uint32_t NewInfoLevel) { + return PluginTy::get().set_info_flag(NewInfoLevel); +} + +int32_t __tgt_rtl_init_async_info(int32_t DeviceId, + __tgt_async_info **AsyncInfoPtr) { + return PluginTy::get().init_async_info(DeviceId, AsyncInfoPtr); +} + +int32_t __tgt_rtl_init_device_info(int32_t DeviceId, + __tgt_device_info *DeviceInfo, + const char **ErrStr) { + return PluginTy::get().init_device_info(DeviceId, DeviceInfo, ErrStr); +} + +int32_t __tgt_rtl_set_device_offset(int32_t DeviceIdOffset) { + return PluginTy::get().set_device_offset(DeviceIdOffset); +} + +int32_t __tgt_rtl_use_auto_zero_copy(int32_t DeviceId) { + return PluginTy::get().use_auto_zero_copy(DeviceId); +} + +int32_t __tgt_rtl_get_global(__tgt_device_binary Binary, uint64_t Size, + const char *Name, void **DevicePtr) { + return PluginTy::get().get_global(Binary, Size, Name, DevicePtr); +} + +int32_t __tgt_rtl_get_function(__tgt_device_binary Binary, const char *Name, + void **KernelPtr) { + return PluginTy::get().get_function(Binary, Name, KernelPtr); +} + +#ifdef __cplusplus +} +#endif diff --git a/offload/plugins-nextgen/cuda/CMakeLists.txt b/offload/plugins-nextgen/cuda/CMakeLists.txt index dd684bb22343..0284bd22d2a4 100644 --- a/offload/plugins-nextgen/cuda/CMakeLists.txt +++ b/offload/plugins-nextgen/cuda/CMakeLists.txt @@ -51,3 +51,8 @@ else() libomptarget_say("Not generating NVIDIA tests, no supported devices detected." " Use 'LIBOMPTARGET_FORCE_NVIDIA_TESTS' to override.") endif() + +# Install plugin under the lib destination folder. +install(TARGETS omptarget.rtl.cuda LIBRARY DESTINATION "${OFFLOAD_INSTALL_LIBDIR}") +set_target_properties(omptarget.rtl.cuda PROPERTIES + INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/..") diff --git a/offload/plugins-nextgen/cuda/src/rtl.cpp b/offload/plugins-nextgen/cuda/src/rtl.cpp index b260334baa18..fc74c6aa23fd 100644 --- a/offload/plugins-nextgen/cuda/src/rtl.cpp +++ b/offload/plugins-nextgen/cuda/src/rtl.cpp @@ -1342,6 +1342,10 @@ struct CUDAPluginTy final : public GenericPluginTy { return 0; } +#ifdef OMPT_SUPPORT + ompt::connectLibrary(); +#endif + if (Res == CUDA_ERROR_NO_DEVICE) { // Do not initialize if there are no devices. DP("There are no devices supporting CUDA.\n"); @@ -1386,8 +1390,6 @@ struct CUDAPluginTy final : public GenericPluginTy { return Triple::nvptx64; } - const char *getName() const override { return GETNAME(TARGET_NAME); } - /// Check whether the image is compatible with the available CUDA devices. Expected isELFCompatible(StringRef Image) const override { auto ElfOrErr = @@ -1493,6 +1495,8 @@ Error CUDADeviceTy::dataExchangeImpl(const void *SrcPtr, return Plugin::check(Res, "Error in cuMemcpyDtoDAsync: %s"); } +GenericPluginTy *PluginTy::createPlugin() { return new CUDAPluginTy(); } + template static Error Plugin::check(int32_t Code, const char *ErrFmt, ArgsTy... Args) { CUresult ResultCode = static_cast(Code); @@ -1512,9 +1516,3 @@ static Error Plugin::check(int32_t Code, const char *ErrFmt, ArgsTy... Args) { } // namespace target } // namespace omp } // namespace llvm - -extern "C" { -llvm::omp::target::plugin::GenericPluginTy *createPlugin_cuda() { - return new llvm::omp::target::plugin::CUDAPluginTy(); -} -} diff --git a/offload/plugins-nextgen/host/CMakeLists.txt b/offload/plugins-nextgen/host/CMakeLists.txt index 72b5681283fe..1d000442c84d 100644 --- a/offload/plugins-nextgen/host/CMakeLists.txt +++ b/offload/plugins-nextgen/host/CMakeLists.txt @@ -31,6 +31,14 @@ else() target_include_directories(omptarget.rtl.host PRIVATE dynamic_ffi) endif() +# Install plugin under the lib destination folder. +install(TARGETS omptarget.rtl.host + LIBRARY DESTINATION "${OFFLOAD_INSTALL_LIBDIR}") +set_target_properties(omptarget.rtl.host PROPERTIES + INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/.." + POSITION_INDEPENDENT_CODE ON + CXX_VISIBILITY_PRESET protected) + target_include_directories(omptarget.rtl.host PRIVATE ${LIBOMPTARGET_INCLUDE_DIR}) diff --git a/offload/plugins-nextgen/host/src/rtl.cpp b/offload/plugins-nextgen/host/src/rtl.cpp index 409b44b1640a..4bdcae3dd6a1 100644 --- a/offload/plugins-nextgen/host/src/rtl.cpp +++ b/offload/plugins-nextgen/host/src/rtl.cpp @@ -385,6 +385,10 @@ struct GenELF64PluginTy final : public GenericPluginTy { /// Initialize the plugin and return the number of devices. Expected initImpl() override { +#ifdef OMPT_SUPPORT + ompt::connectLibrary(); +#endif + #ifdef USES_DYNAMIC_FFI if (auto Err = Plugin::check(ffi_init(), "Failed to initialize libffi")) return std::move(Err); @@ -441,10 +445,10 @@ struct GenELF64PluginTy final : public GenericPluginTy { return llvm::Triple::UnknownArch; #endif } - - const char *getName() const override { return GETNAME(TARGET_NAME); } }; +GenericPluginTy *PluginTy::createPlugin() { return new GenELF64PluginTy(); } + template static Error Plugin::check(int32_t Code, const char *ErrMsg, ArgsTy... Args) { if (Code == 0) @@ -458,9 +462,3 @@ static Error Plugin::check(int32_t Code, const char *ErrMsg, ArgsTy... Args) { } // namespace target } // namespace omp } // namespace llvm - -extern "C" { -llvm::omp::target::plugin::GenericPluginTy *createPlugin_host() { - return new llvm::omp::target::plugin::GenELF64PluginTy(); -} -} diff --git a/offload/src/CMakeLists.txt b/offload/src/CMakeLists.txt index 8fe6d19d83eb..eda5a85ff1ab 100644 --- a/offload/src/CMakeLists.txt +++ b/offload/src/CMakeLists.txt @@ -65,10 +65,6 @@ target_compile_definitions(omptarget PRIVATE DEBUG_PREFIX="omptarget" ) -foreach(plugin IN LISTS LIBOMPTARGET_PLUGINS_TO_BUILD) - target_link_libraries(omptarget PRIVATE omptarget.rtl.${plugin}) -endforeach() - target_compile_options(omptarget PUBLIC ${offload_compile_flags}) target_link_options(omptarget PUBLIC ${offload_link_flags}) diff --git a/offload/src/OffloadRTL.cpp b/offload/src/OffloadRTL.cpp index 29b573a27d08..dd75b1b18150 100644 --- a/offload/src/OffloadRTL.cpp +++ b/offload/src/OffloadRTL.cpp @@ -50,7 +50,6 @@ void deinitRuntime() { if (RefCount == 1) { DP("Deinit offload library!\n"); - PM->deinit(); delete PM; PM = nullptr; } diff --git a/offload/src/OpenMP/InteropAPI.cpp b/offload/src/OpenMP/InteropAPI.cpp index bdbc440c64a2..1a995cde7816 100644 --- a/offload/src/OpenMP/InteropAPI.cpp +++ b/offload/src/OpenMP/InteropAPI.cpp @@ -230,14 +230,14 @@ void __tgt_interop_init(ident_t *LocRef, int32_t Gtid, } DeviceTy &Device = *DeviceOrErr; - if (!Device.RTL || + if (!Device.RTL || !Device.RTL->init_device_info || Device.RTL->init_device_info(DeviceId, &(InteropPtr)->device_info, &(InteropPtr)->err_str)) { delete InteropPtr; InteropPtr = omp_interop_none; } if (InteropType == kmp_interop_type_tasksync) { - if (!Device.RTL || + if (!Device.RTL || !Device.RTL->init_async_info || Device.RTL->init_async_info(DeviceId, &(InteropPtr)->async_info)) { delete InteropPtr; InteropPtr = omp_interop_none; diff --git a/offload/src/PluginManager.cpp b/offload/src/PluginManager.cpp index 191afa345641..dbb556c179e5 100644 --- a/offload/src/PluginManager.cpp +++ b/offload/src/PluginManager.cpp @@ -23,25 +23,85 @@ using namespace llvm::sys; PluginManager *PM = nullptr; -// Every plugin exports this method to create an instance of the plugin type. -#define PLUGIN_TARGET(Name) extern "C" GenericPluginTy *createPlugin_##Name(); -#include "Shared/Targets.def" +Expected> +PluginAdaptorTy::create(const std::string &Name) { + DP("Attempting to load library '%s'...\n", Name.c_str()); + TIMESCOPE_WITH_NAME_AND_IDENT(Name, (const ident_t *)nullptr); + + std::string ErrMsg; + auto LibraryHandler = std::make_unique( + DynamicLibrary::getPermanentLibrary(Name.c_str(), &ErrMsg)); + + if (!LibraryHandler->isValid()) { + // Library does not exist or cannot be found. + return createStringError(inconvertibleErrorCode(), + "Unable to load library '%s': %s!\n", Name.c_str(), + ErrMsg.c_str()); + } + + DP("Successfully loaded library '%s'!\n", Name.c_str()); + auto PluginAdaptor = std::unique_ptr( + new PluginAdaptorTy(Name, std::move(LibraryHandler))); + if (auto Err = PluginAdaptor->init()) + return Err; + return std::move(PluginAdaptor); +} + +PluginAdaptorTy::PluginAdaptorTy(const std::string &Name, + std::unique_ptr DL) + : Name(Name), LibraryHandler(std::move(DL)) {} + +Error PluginAdaptorTy::init() { + +#define PLUGIN_API_HANDLE(NAME) \ + NAME = reinterpret_cast( \ + LibraryHandler->getAddressOfSymbol(GETNAME(__tgt_rtl_##NAME))); \ + if (!NAME) { \ + return createStringError(inconvertibleErrorCode(), \ + "Invalid plugin as necessary interface function " \ + "(%s) was not found.\n", \ + std::string(#NAME).c_str()); \ + } + +#include "Shared/PluginAPI.inc" +#undef PLUGIN_API_HANDLE + + // Remove plugin on failure to call optional init_plugin + int32_t Rc = init_plugin(); + if (Rc != OFFLOAD_SUCCESS) { + return createStringError(inconvertibleErrorCode(), + "Unable to initialize library '%s': %u!\n", + Name.c_str(), Rc); + } + + // No devices are supported by this RTL? + int32_t NumberOfPluginDevices = number_of_devices(); + if (!NumberOfPluginDevices) { + return createStringError(inconvertibleErrorCode(), + "No devices supported in this RTL\n"); + } + + DP("Registered '%s' with %d plugin visible devices!\n", Name.c_str(), + NumberOfPluginDevices); + return Error::success(); +} void PluginManager::init() { TIMESCOPE(); DP("Loading RTLs...\n"); - // Attempt to create an instance of each supported plugin. + // Attempt to open all the plugins and, if they exist, check if the interface + // is correct and if they are supporting any devices. #define PLUGIN_TARGET(Name) \ do { \ - auto Plugin = std::unique_ptr(createPlugin_##Name()); \ - if (auto Err = Plugin->init()) { \ - [[maybe_unused]] std::string InfoMsg = toString(std::move(Err)); \ - DP("Failed to init plugin: %s\n", InfoMsg.c_str()); \ + auto PluginAdaptorOrErr = \ + PluginAdaptorTy::create("libomptarget.rtl." #Name ".so"); \ + if (!PluginAdaptorOrErr) { \ + [[maybe_unused]] std::string InfoMsg = \ + toString(PluginAdaptorOrErr.takeError()); \ + DP("%s", InfoMsg.c_str()); \ } else { \ - DP("Registered plugin %s with %d visible device(s)\n", \ - Plugin->getName(), Plugin->number_of_devices()); \ - Plugins.emplace_back(std::move(Plugin)); \ + PluginAdaptors.push_back(std::move(*PluginAdaptorOrErr)); \ } \ } while (false); #include "Shared/Targets.def" @@ -49,29 +109,15 @@ void PluginManager::init() { DP("RTLs loaded!\n"); } -void PluginManager::deinit() { - TIMESCOPE(); - DP("Unloading RTLs...\n"); - - for (auto &Plugin : Plugins) { - if (auto Err = Plugin->deinit()) { - [[maybe_unused]] std::string InfoMsg = toString(std::move(Err)); - DP("Failed to deinit plugin: %s\n", InfoMsg.c_str()); - } - Plugin.release(); - } - - DP("RTLs unloaded!\n"); -} - -void PluginManager::initDevices(GenericPluginTy &RTL) { +void PluginManager::initDevices(PluginAdaptorTy &RTL) { // If this RTL has already been initialized. if (PM->DeviceOffsets.contains(&RTL)) return; TIMESCOPE(); // If this RTL is not already in use, initialize it. - assert(RTL.number_of_devices() > 0 && "Tried to initialize useless plugin!"); + assert(RTL.number_of_devices() > 0 && + "Tried to initialize useless plugin adaptor"); // Initialize the device information for the RTL we are about to use. auto ExclusiveDevicesAccessor = getExclusiveDevicesAccessor(); @@ -111,12 +157,13 @@ void PluginManager::initDevices(GenericPluginTy &RTL) { DeviceOffsets[&RTL] = DeviceOffset; DeviceUsed[&RTL] = NumberOfUserDevices; - DP("Plugin has index %d, exposes %d out of %d devices!\n", DeviceOffset, - NumberOfUserDevices, RTL.number_of_devices()); + DP("Plugin adaptor " DPxMOD " has index %d, exposes %d out of %d devices!\n", + DPxPTR(RTL.LibraryHandler.get()), DeviceOffset, NumberOfUserDevices, + RTL.number_of_devices()); } void PluginManager::initAllPlugins() { - for (auto &R : Plugins) + for (auto &R : PluginAdaptors) initDevices(*R); } @@ -169,22 +216,19 @@ void PluginManager::registerLib(__tgt_bin_desc *Desc) { // Obtain the image and information that was previously extracted. __tgt_device_image *Img = &DI.getExecutableImage(); - GenericPluginTy *FoundRTL = nullptr; + PluginAdaptorTy *FoundRTL = nullptr; // Scan the RTLs that have associated images until we find one that supports // the current image. - for (auto &R : PM->plugins()) { - if (!R.number_of_devices()) - continue; - + for (auto &R : PM->pluginAdaptors()) { if (!R.is_valid_binary(Img)) { DP("Image " DPxMOD " is NOT compatible with RTL %s!\n", - DPxPTR(Img->ImageStart), R.getName()); + DPxPTR(Img->ImageStart), R.Name.c_str()); continue; } DP("Image " DPxMOD " is compatible with RTL %s!\n", - DPxPTR(Img->ImageStart), R.getName()); + DPxPTR(Img->ImageStart), R.Name.c_str()); PM->initDevices(R); @@ -203,7 +247,7 @@ void PluginManager::registerLib(__tgt_bin_desc *Desc) { (PM->HostEntriesBeginToTransTable)[Desc->HostEntriesBegin]; DP("Registering image " DPxMOD " with RTL %s!\n", DPxPTR(Img->ImageStart), - R.getName()); + R.Name.c_str()); registerImageIntoTranslationTable(TransTable, PM->DeviceOffsets[&R], PM->DeviceUsed[&R], Img); @@ -238,11 +282,11 @@ void PluginManager::unregisterLib(__tgt_bin_desc *Desc) { // Obtain the image and information that was previously extracted. __tgt_device_image *Img = &DI.getExecutableImage(); - GenericPluginTy *FoundRTL = NULL; + PluginAdaptorTy *FoundRTL = NULL; // Scan the RTLs that have associated images until we find one that supports // the current image. We only need to scan RTLs that are already being used. - for (auto &R : PM->plugins()) { + for (auto &R : PM->pluginAdaptors()) { if (!DeviceOffsets.contains(&R)) continue; @@ -252,7 +296,8 @@ void PluginManager::unregisterLib(__tgt_bin_desc *Desc) { FoundRTL = &R; - DP("Unregistered image " DPxMOD " from RTL\n", DPxPTR(Img->ImageStart)); + DP("Unregistered image " DPxMOD " from RTL " DPxMOD "!\n", + DPxPTR(Img->ImageStart), DPxPTR(R.LibraryHandler.get())); break; } diff --git a/offload/src/device.cpp b/offload/src/device.cpp index 749b4c567f8e..44a2facc8d3d 100644 --- a/offload/src/device.cpp +++ b/offload/src/device.cpp @@ -64,7 +64,7 @@ int HostDataToTargetTy::addEventIfNecessary(DeviceTy &Device, return OFFLOAD_SUCCESS; } -DeviceTy::DeviceTy(GenericPluginTy *RTL, int32_t DeviceID, int32_t RTLDeviceID) +DeviceTy::DeviceTy(PluginAdaptorTy *RTL, int32_t DeviceID, int32_t RTLDeviceID) : DeviceID(DeviceID), RTL(RTL), RTLDeviceID(RTLDeviceID), MappingInfo(*this) {} @@ -192,6 +192,7 @@ int32_t DeviceTy::dataExchange(void *SrcPtr, DeviceTy &DstDev, void *DstPtr, RTLDeviceID, SrcPtr, DstDev.RTLDeviceID, DstPtr, Size, /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) if (!AsyncInfo) { + assert(RTL->data_exchange && "RTL->data_exchange is nullptr"); return RTL->data_exchange(RTLDeviceID, SrcPtr, DstDev.RTLDeviceID, DstPtr, Size); } diff --git a/offload/src/interface.cpp b/offload/src/interface.cpp index 763b051cc6d7..557703632c62 100644 --- a/offload/src/interface.cpp +++ b/offload/src/interface.cpp @@ -456,6 +456,8 @@ EXTERN void __tgt_set_info_flag(uint32_t NewInfoLevel) { assert(PM && "Runtime not initialized"); std::atomic &InfoLevel = getInfoLevelInternal(); InfoLevel.store(NewInfoLevel); + for (auto &R : PM->pluginAdaptors()) + R.set_info_flag(NewInfoLevel); } EXTERN int __tgt_print_device_info(int64_t DeviceId) { diff --git a/offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp b/offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp index 1e9a6a84d805..761e04e4c7bb 100644 --- a/offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp +++ b/offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp @@ -13,6 +13,8 @@ #include "omptarget.h" +#include "Shared/PluginAPI.h" + #include "llvm/Support/CommandLine.h" #include "llvm/Support/JSON.h" #include "llvm/Support/MemoryBuffer.h" diff --git a/offload/unittests/Plugins/NextgenPluginsTest.cpp b/offload/unittests/Plugins/NextgenPluginsTest.cpp index 479b3f614aed..635bd1637c90 100644 --- a/offload/unittests/Plugins/NextgenPluginsTest.cpp +++ b/offload/unittests/Plugins/NextgenPluginsTest.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "Shared/PluginAPI.h" #include "omptarget.h" #include "gtest/gtest.h" -- GitLab From e0d8dbc1dc203983243860c1fcc4698f60de37c0 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 9 May 2024 13:13:08 +0100 Subject: [PATCH 133/328] [X86] opt-shuff-tstore.ll - regenerate checks --- llvm/test/CodeGen/X86/opt-shuff-tstore.ll | 33 ++++++++++++++--------- 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/llvm/test/CodeGen/X86/opt-shuff-tstore.ll b/llvm/test/CodeGen/X86/opt-shuff-tstore.ll index 0a2d4e9ba9fe..c331f8ffb369 100644 --- a/llvm/test/CodeGen/X86/opt-shuff-tstore.ll +++ b/llvm/test/CodeGen/X86/opt-shuff-tstore.ll @@ -1,37 +1,46 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc -mcpu=corei7 -mtriple=x86_64-linux < %s -mattr=+sse2,+sse4.1 | FileCheck %s -; CHECK: func_4_8 ; A single memory write -; CHECK: movd -; CHECK-NEXT: ret define void @func_4_8(<4 x i8> %param, ptr %p) { +; CHECK-LABEL: func_4_8: +; CHECK: # %bb.0: +; CHECK-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: movd %xmm0, (%rdi) +; CHECK-NEXT: retq %r = add <4 x i8> %param, store <4 x i8> %r, ptr %p ret void } -; CHECK: func_4_16 -; CHECK: movq -; CHECK-NEXT: ret define void @func_4_16(<4 x i16> %param, ptr %p) { +; CHECK-LABEL: func_4_16: +; CHECK: # %bb.0: +; CHECK-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: movq %xmm0, (%rdi) +; CHECK-NEXT: retq %r = add <4 x i16> %param, store <4 x i16> %r, ptr %p ret void } -; CHECK: func_8_8 -; CHECK: movq -; CHECK-NEXT: ret define void @func_8_8(<8 x i8> %param, ptr %p) { +; CHECK-LABEL: func_8_8: +; CHECK: # %bb.0: +; CHECK-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: movq %xmm0, (%rdi) +; CHECK-NEXT: retq %r = add <8 x i8> %param, store <8 x i8> %r, ptr %p ret void } -; CHECK: func_2_32 -; CHECK: movq -; CHECK-NEXT: ret define void @func_2_32(<2 x i32> %param, ptr %p) { +; CHECK-LABEL: func_2_32: +; CHECK: # %bb.0: +; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: movq %xmm0, (%rdi) +; CHECK-NEXT: retq %r = add <2 x i32> %param, store <2 x i32> %r, ptr %p ret void -- GitLab From 8b400de79eff2a4fb95f06b6e4d167e65abbf448 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 9 May 2024 13:15:01 +0100 Subject: [PATCH 134/328] [X86] Enable TuningSlowDivide64 on Barcelona/Bobcat/Bulldozer/Ryzen Families (#91277) Despite most AMD cpus having a lower latency for i64 divisions that converge early, we are still better off testing for values representable as i32 and performing a i32 division if possible. All AMD cpus appear to have been missed when we added the "idivq-to-divl" attribute - this patch now matches Intel cpu behaviour (and the x86-64/v2/3/4 levels). Unfortunately the difference in code scheduling means I've had to stop using the update_llc_test_checks script and just use old-fashioned CHECK-DAG checks for divl/divq pairs. Fixes #90985 --- llvm/lib/Target/X86/X86.td | 5 + .../CodeGen/X86/bypass-slow-division-64.ll | 95 +++++++++---------- 2 files changed, 52 insertions(+), 48 deletions(-) diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 25ab08187cf1..9f5b58d78fcc 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -1350,6 +1350,7 @@ def ProcessorFeatures { FeatureCMOV, FeatureX86_64]; list BarcelonaTuning = [TuningFastScalarShiftMasks, + TuningSlowDivide64, TuningSlowSHLD, TuningSBBDepBreaking, TuningInsertVZEROUPPER]; @@ -1372,6 +1373,7 @@ def ProcessorFeatures { list BtVer1Tuning = [TuningFast15ByteNOP, TuningFastScalarShiftMasks, TuningFastVectorShiftMasks, + TuningSlowDivide64, TuningSlowSHLD, TuningFastImm16, TuningSBBDepBreaking, @@ -1396,6 +1398,7 @@ def ProcessorFeatures { TuningFastMOVBE, TuningFastImm16, TuningSBBDepBreaking, + TuningSlowDivide64, TuningSlowSHLD]; list BtVer2Features = !listconcat(BtVer1Features, BtVer2AdditionalFeatures); @@ -1420,6 +1423,7 @@ def ProcessorFeatures { FeatureLWP, FeatureLAHFSAHF64]; list BdVer1Tuning = [TuningSlowSHLD, + TuningSlowDivide64, TuningFast11ByteNOP, TuningFastScalarShiftMasks, TuningBranchFusion, @@ -1500,6 +1504,7 @@ def ProcessorFeatures { TuningFastVariablePerLaneShuffle, TuningFastMOVBE, TuningFastImm16, + TuningSlowDivide64, TuningSlowSHLD, TuningSBBDepBreaking, TuningInsertVZEROUPPER, diff --git a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll index 66d7082d9b7c..6e0cfdd26a78 100644 --- a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll +++ b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll @@ -1,4 +1,3 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; Check that 64-bit division is bypassed correctly. ; RUN: llc < %s -mtriple=x86_64-- -mattr=-idivq-to-divl | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ ; RUN: llc < %s -mtriple=x86_64-- -mattr=+idivq-to-divl | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ @@ -13,17 +12,17 @@ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=alderlake | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ ; AMD -; RUN: llc < %s -mtriple=x86_64-- -mcpu=barcelona | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ -; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver1 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ -; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver2 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ -; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver1 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ -; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ -; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver3 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ -; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ -; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ -; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ -; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ -; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ +; RUN: llc < %s -mtriple=x86_64-- -mcpu=barcelona | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ +; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver1 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ +; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver2 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ +; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver1 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ +; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ +; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver3 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ +; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ ; Additional tests for 64-bit divide bypass @@ -41,18 +40,18 @@ define i64 @sdiv_quotient(i64 %a, i64 %b) nounwind { ; ; SLOW-DIVQ-LABEL: sdiv_quotient: ; SLOW-DIVQ: # %bb.0: -; SLOW-DIVQ-NEXT: movq %rdi, %rax -; SLOW-DIVQ-NEXT: movq %rdi, %rcx -; SLOW-DIVQ-NEXT: orq %rsi, %rcx -; SLOW-DIVQ-NEXT: shrq $32, %rcx +; SLOW-DIVQ-DAG: movq %rdi, %rax +; SLOW-DIVQ-DAG: movq %rdi, %rcx +; SLOW-DIVQ-DAG: orq %rsi, %rcx +; SLOW-DIVQ-DAG: shrq $32, %rcx ; SLOW-DIVQ-NEXT: je .LBB0_1 ; SLOW-DIVQ-NEXT: # %bb.2: ; SLOW-DIVQ-NEXT: cqto ; SLOW-DIVQ-NEXT: idivq %rsi ; SLOW-DIVQ-NEXT: retq ; SLOW-DIVQ-NEXT: .LBB0_1: -; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax killed $rax -; SLOW-DIVQ-NEXT: xorl %edx, %edx +; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax +; SLOW-DIVQ-DAG: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divl %esi ; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax def $rax ; SLOW-DIVQ-NEXT: retq @@ -93,10 +92,10 @@ define i64 @sdiv_remainder(i64 %a, i64 %b) nounwind { ; ; SLOW-DIVQ-LABEL: sdiv_remainder: ; SLOW-DIVQ: # %bb.0: -; SLOW-DIVQ-NEXT: movq %rdi, %rax -; SLOW-DIVQ-NEXT: movq %rdi, %rcx -; SLOW-DIVQ-NEXT: orq %rsi, %rcx -; SLOW-DIVQ-NEXT: shrq $32, %rcx +; SLOW-DIVQ-DAG: movq %rdi, %rax +; SLOW-DIVQ-DAG: movq %rdi, %rcx +; SLOW-DIVQ-DAG: orq %rsi, %rcx +; SLOW-DIVQ-DAG: shrq $32, %rcx ; SLOW-DIVQ-NEXT: je .LBB3_1 ; SLOW-DIVQ-NEXT: # %bb.2: ; SLOW-DIVQ-NEXT: cqto @@ -104,8 +103,8 @@ define i64 @sdiv_remainder(i64 %a, i64 %b) nounwind { ; SLOW-DIVQ-NEXT: movq %rdx, %rax ; SLOW-DIVQ-NEXT: retq ; SLOW-DIVQ-NEXT: .LBB3_1: -; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax killed $rax -; SLOW-DIVQ-NEXT: xorl %edx, %edx +; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax +; SLOW-DIVQ-DAG: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divl %esi ; SLOW-DIVQ-NEXT: movl %edx, %eax ; SLOW-DIVQ-NEXT: retq @@ -148,10 +147,10 @@ define i64 @sdiv_quotient_and_remainder(i64 %a, i64 %b) nounwind { ; ; SLOW-DIVQ-LABEL: sdiv_quotient_and_remainder: ; SLOW-DIVQ: # %bb.0: -; SLOW-DIVQ-NEXT: movq %rdi, %rax -; SLOW-DIVQ-NEXT: movq %rdi, %rcx -; SLOW-DIVQ-NEXT: orq %rsi, %rcx -; SLOW-DIVQ-NEXT: shrq $32, %rcx +; SLOW-DIVQ-DAG: movq %rdi, %rax +; SLOW-DIVQ-DAG: movq %rdi, %rcx +; SLOW-DIVQ-DAG: orq %rsi, %rcx +; SLOW-DIVQ-DAG: shrq $32, %rcx ; SLOW-DIVQ-NEXT: je .LBB6_1 ; SLOW-DIVQ-NEXT: # %bb.2: ; SLOW-DIVQ-NEXT: cqto @@ -159,8 +158,8 @@ define i64 @sdiv_quotient_and_remainder(i64 %a, i64 %b) nounwind { ; SLOW-DIVQ-NEXT: addq %rdx, %rax ; SLOW-DIVQ-NEXT: retq ; SLOW-DIVQ-NEXT: .LBB6_1: -; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax killed $rax -; SLOW-DIVQ-NEXT: xorl %edx, %edx +; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax +; SLOW-DIVQ-DAG: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divl %esi ; SLOW-DIVQ-NEXT: # kill: def $edx killed $edx def $rdx ; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax def $rax @@ -214,18 +213,18 @@ define i64 @udiv_quotient(i64 %a, i64 %b) nounwind { ; ; SLOW-DIVQ-LABEL: udiv_quotient: ; SLOW-DIVQ: # %bb.0: -; SLOW-DIVQ-NEXT: movq %rdi, %rax -; SLOW-DIVQ-NEXT: movq %rdi, %rcx -; SLOW-DIVQ-NEXT: orq %rsi, %rcx -; SLOW-DIVQ-NEXT: shrq $32, %rcx +; SLOW-DIVQ-DAG: movq %rdi, %rax +; SLOW-DIVQ-DAG: movq %rdi, %rcx +; SLOW-DIVQ-DAG: orq %rsi, %rcx +; SLOW-DIVQ-DAG: shrq $32, %rcx ; SLOW-DIVQ-NEXT: je .LBB9_1 ; SLOW-DIVQ-NEXT: # %bb.2: ; SLOW-DIVQ-NEXT: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divq %rsi ; SLOW-DIVQ-NEXT: retq ; SLOW-DIVQ-NEXT: .LBB9_1: -; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax killed $rax -; SLOW-DIVQ-NEXT: xorl %edx, %edx +; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax +; SLOW-DIVQ-DAG: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divl %esi ; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax def $rax ; SLOW-DIVQ-NEXT: retq @@ -266,10 +265,10 @@ define i64 @udiv_remainder(i64 %a, i64 %b) nounwind { ; ; SLOW-DIVQ-LABEL: udiv_remainder: ; SLOW-DIVQ: # %bb.0: -; SLOW-DIVQ-NEXT: movq %rdi, %rax -; SLOW-DIVQ-NEXT: movq %rdi, %rcx -; SLOW-DIVQ-NEXT: orq %rsi, %rcx -; SLOW-DIVQ-NEXT: shrq $32, %rcx +; SLOW-DIVQ-DAG: movq %rdi, %rax +; SLOW-DIVQ-DAG: movq %rdi, %rcx +; SLOW-DIVQ-DAG: orq %rsi, %rcx +; SLOW-DIVQ-DAG: shrq $32, %rcx ; SLOW-DIVQ-NEXT: je .LBB12_1 ; SLOW-DIVQ-NEXT: # %bb.2: ; SLOW-DIVQ-NEXT: xorl %edx, %edx @@ -277,8 +276,8 @@ define i64 @udiv_remainder(i64 %a, i64 %b) nounwind { ; SLOW-DIVQ-NEXT: movq %rdx, %rax ; SLOW-DIVQ-NEXT: retq ; SLOW-DIVQ-NEXT: .LBB12_1: -; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax killed $rax -; SLOW-DIVQ-NEXT: xorl %edx, %edx +; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax +; SLOW-DIVQ-DAG: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divl %esi ; SLOW-DIVQ-NEXT: movl %edx, %eax ; SLOW-DIVQ-NEXT: retq @@ -321,10 +320,10 @@ define i64 @udiv_quotient_and_remainder(i64 %a, i64 %b) nounwind { ; ; SLOW-DIVQ-LABEL: udiv_quotient_and_remainder: ; SLOW-DIVQ: # %bb.0: -; SLOW-DIVQ-NEXT: movq %rdi, %rax -; SLOW-DIVQ-NEXT: movq %rdi, %rcx -; SLOW-DIVQ-NEXT: orq %rsi, %rcx -; SLOW-DIVQ-NEXT: shrq $32, %rcx +; SLOW-DIVQ-DAG: movq %rdi, %rax +; SLOW-DIVQ-DAG: movq %rdi, %rcx +; SLOW-DIVQ-DAG: orq %rsi, %rcx +; SLOW-DIVQ-DAG: shrq $32, %rcx ; SLOW-DIVQ-NEXT: je .LBB15_1 ; SLOW-DIVQ-NEXT: # %bb.2: ; SLOW-DIVQ-NEXT: xorl %edx, %edx @@ -332,8 +331,8 @@ define i64 @udiv_quotient_and_remainder(i64 %a, i64 %b) nounwind { ; SLOW-DIVQ-NEXT: addq %rdx, %rax ; SLOW-DIVQ-NEXT: retq ; SLOW-DIVQ-NEXT: .LBB15_1: -; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax killed $rax -; SLOW-DIVQ-NEXT: xorl %edx, %edx +; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax +; SLOW-DIVQ-DAG: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divl %esi ; SLOW-DIVQ-NEXT: # kill: def $edx killed $edx def $rdx ; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax def $rax -- GitLab From c2a87d7e032f8e6c8cbe6ab4c7cfbb7f7996ca9f Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Thu, 9 May 2024 20:14:30 +0800 Subject: [PATCH 135/328] [AMDGPU] Remove unused lambda capture (NFC) /llvm-project/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp:733:30: error: lambda capture 'Ctx' is not used [-Werror,-Wunused-lambda-capture] auto TryGetMCExprValue = [&Ctx](const MCExpr *Value, uint64_t &Res) -> bool { ~^~~ 1 error generated. --- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index de81904143b7..b7388ed9e85a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -730,7 +730,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, return MCConstantExpr::create(Value, Ctx); }; - auto TryGetMCExprValue = [&Ctx](const MCExpr *Value, uint64_t &Res) -> bool { + auto TryGetMCExprValue = [](const MCExpr *Value, uint64_t &Res) -> bool { int64_t Val; if (Value->evaluateAsAbsolute(Val)) { Res = Val; -- GitLab From ad652efa1f65e16f5380acfba1bb132145984805 Mon Sep 17 00:00:00 2001 From: Daniil Kovalev Date: Thu, 9 May 2024 15:32:18 +0300 Subject: [PATCH 136/328] [AArch64][PAC][clang][ELF] Support PAuth ABI core info (#85235) Depends on #87545 Emit PAuth ABI compatibility tag values as llvm module flags: - `aarch64-elf-pauthabi-platform` - `aarch64-elf-pauthabi-version` For platform 0x10000002 (llvm_linux), the version value bits correspond to the following LangOptions defined in #85232: - bit 0: `PointerAuthIntrinsics`; - bit 1: `PointerAuthCalls`; - bit 2: `PointerAuthReturns`; - bit 3: `PointerAuthAuthTraps`; - bit 4: `PointerAuthVTPtrAddressDiscrimination`; - bit 5: `PointerAuthVTPtrTypeDiscrimination`; - bit 6: `PointerAuthInitFini`. --------- Co-authored-by: Ahmed Bougacha --- clang/include/clang/Basic/Features.def | 6 ++ clang/include/clang/Basic/LangOptions.def | 6 ++ clang/include/clang/Driver/Options.td | 8 ++ clang/lib/CodeGen/CodeGenModule.cpp | 32 +++++++ clang/lib/Driver/ToolChains/Clang.cpp | 14 +++ clang/lib/Frontend/CompilerInvocation.cpp | 20 ++++ clang/test/CodeGen/aarch64-elf-pauthabi.c | 59 ++++++++++++ clang/test/Driver/aarch64-ptrauth.c | 28 +++++- clang/test/Preprocessor/ptrauth_feature.c | 107 +++++++++++++++++++++- 9 files changed, 274 insertions(+), 6 deletions(-) create mode 100644 clang/test/CodeGen/aarch64-elf-pauthabi.c diff --git a/clang/include/clang/Basic/Features.def b/clang/include/clang/Basic/Features.def index fe4d1c4afcca..b762e44e755e 100644 --- a/clang/include/clang/Basic/Features.def +++ b/clang/include/clang/Basic/Features.def @@ -103,6 +103,12 @@ FEATURE(thread_sanitizer, LangOpts.Sanitize.has(SanitizerKind::Thread)) FEATURE(dataflow_sanitizer, LangOpts.Sanitize.has(SanitizerKind::DataFlow)) FEATURE(scudo, LangOpts.Sanitize.hasOneOf(SanitizerKind::Scudo)) FEATURE(ptrauth_intrinsics, LangOpts.PointerAuthIntrinsics) +FEATURE(ptrauth_calls, LangOpts.PointerAuthCalls) +FEATURE(ptrauth_returns, LangOpts.PointerAuthReturns) +FEATURE(ptrauth_vtable_pointer_address_discrimination, LangOpts.PointerAuthVTPtrAddressDiscrimination) +FEATURE(ptrauth_vtable_pointer_type_discrimination, LangOpts.PointerAuthVTPtrTypeDiscrimination) +FEATURE(ptrauth_member_function_pointer_type_discrimination, LangOpts.PointerAuthCalls) +FEATURE(ptrauth_init_fini, LangOpts.PointerAuthInitFini) EXTENSION(swiftcc, PP.getTargetInfo().checkCallingConvention(CC_Swift) == clang::TargetInfo::CCCR_OK) diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def index c967d8b22292..09eb92d6f10d 100644 --- a/clang/include/clang/Basic/LangOptions.def +++ b/clang/include/clang/Basic/LangOptions.def @@ -162,6 +162,12 @@ LANGOPT(RelaxedTemplateTemplateArgs, 1, 1, "C++17 relaxed matching of template t LANGOPT(ExperimentalLibrary, 1, 0, "enable unstable and experimental library features") LANGOPT(PointerAuthIntrinsics, 1, 0, "pointer authentication intrinsics") +LANGOPT(PointerAuthCalls , 1, 0, "function pointer authentication") +LANGOPT(PointerAuthReturns, 1, 0, "return pointer authentication") +LANGOPT(PointerAuthAuthTraps, 1, 0, "pointer authentication failure traps") +LANGOPT(PointerAuthVTPtrAddressDiscrimination, 1, 0, "incorporate address discrimination in authenticated vtable pointers") +LANGOPT(PointerAuthVTPtrTypeDiscrimination, 1, 0, "incorporate type discrimination in authenticated vtable pointers") +LANGOPT(PointerAuthInitFini, 1, 0, "sign function pointers in init/fini arrays") LANGOPT(DoubleSquareBracketAttributes, 1, 0, "'[[]]' attributes extension for all language standard modes") LANGOPT(ExperimentalLateParseAttributes, 1, 0, "experimental late parsing of attributes") diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 142952897585..73a2518480e9 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -4180,6 +4180,14 @@ defm strict_return : BoolFOption<"strict-return", let Flags = [TargetSpecific] in { defm ptrauth_intrinsics : OptInCC1FFlag<"ptrauth-intrinsics", "Enable pointer authentication intrinsics">; +defm ptrauth_calls : OptInCC1FFlag<"ptrauth-calls", "Enable signing and authentication of all indirect calls">; +defm ptrauth_returns : OptInCC1FFlag<"ptrauth-returns", "Enable signing and authentication of return addresses">; +defm ptrauth_auth_traps : OptInCC1FFlag<"ptrauth-auth-traps", "Enable traps on authentication failures">; +defm ptrauth_vtable_pointer_address_discrimination : + OptInCC1FFlag<"ptrauth-vtable-pointer-address-discrimination", "Enable address discrimination of vtable pointers">; +defm ptrauth_vtable_pointer_type_discrimination : + OptInCC1FFlag<"ptrauth-vtable-pointer-type-discrimination", "Enable type discrimination of vtable pointers">; +defm ptrauth_init_fini : OptInCC1FFlag<"ptrauth-init-fini", "Enable signing of function pointers in init/fini arrays">; } def fenable_matrix : Flag<["-"], "fenable-matrix">, Group, diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index c8898ce196c1..489c08a4d481 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -53,6 +53,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/Analysis/TargetLibraryInfo.h" +#include "llvm/BinaryFormat/ELF.h" #include "llvm/Frontend/OpenMP/OMPIRBuilder.h" #include "llvm/IR/AttributeMask.h" #include "llvm/IR/CallingConv.h" @@ -1190,6 +1191,37 @@ void CodeGenModule::Release() { if (!LangOpts.isSignReturnAddressWithAKey()) getModule().addModuleFlag(llvm::Module::Min, "sign-return-address-with-bkey", 1); + + if (getTriple().isOSLinux()) { + assert(getTriple().isOSBinFormatELF()); + using namespace llvm::ELF; + uint64_t PAuthABIVersion = + (LangOpts.PointerAuthIntrinsics + << AARCH64_PAUTH_PLATFORM_LLVM_LINUX_VERSION_INTRINSICS) | + (LangOpts.PointerAuthCalls + << AARCH64_PAUTH_PLATFORM_LLVM_LINUX_VERSION_CALLS) | + (LangOpts.PointerAuthReturns + << AARCH64_PAUTH_PLATFORM_LLVM_LINUX_VERSION_RETURNS) | + (LangOpts.PointerAuthAuthTraps + << AARCH64_PAUTH_PLATFORM_LLVM_LINUX_VERSION_AUTHTRAPS) | + (LangOpts.PointerAuthVTPtrAddressDiscrimination + << AARCH64_PAUTH_PLATFORM_LLVM_LINUX_VERSION_VPTRADDRDISCR) | + (LangOpts.PointerAuthVTPtrTypeDiscrimination + << AARCH64_PAUTH_PLATFORM_LLVM_LINUX_VERSION_VPTRTYPEDISCR) | + (LangOpts.PointerAuthInitFini + << AARCH64_PAUTH_PLATFORM_LLVM_LINUX_VERSION_INITFINI); + static_assert(AARCH64_PAUTH_PLATFORM_LLVM_LINUX_VERSION_INITFINI == + AARCH64_PAUTH_PLATFORM_LLVM_LINUX_VERSION_LAST, + "Update when new enum items are defined"); + if (PAuthABIVersion != 0) { + getModule().addModuleFlag(llvm::Module::Error, + "aarch64-elf-pauthabi-platform", + AARCH64_PAUTH_PLATFORM_LLVM_LINUX); + getModule().addModuleFlag(llvm::Module::Error, + "aarch64-elf-pauthabi-version", + PAuthABIVersion); + } + } } if (CodeGenOpts.StackClashProtector) diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 0a2ea96de738..775dc249999e 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -1756,6 +1756,20 @@ void Clang::AddAArch64TargetArgs(const ArgList &Args, Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_intrinsics, options::OPT_fno_ptrauth_intrinsics); + Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_calls, + options::OPT_fno_ptrauth_calls); + Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_returns, + options::OPT_fno_ptrauth_returns); + Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_auth_traps, + options::OPT_fno_ptrauth_auth_traps); + Args.addOptInFlag( + CmdArgs, options::OPT_fptrauth_vtable_pointer_address_discrimination, + options::OPT_fno_ptrauth_vtable_pointer_address_discrimination); + Args.addOptInFlag( + CmdArgs, options::OPT_fptrauth_vtable_pointer_type_discrimination, + options::OPT_fno_ptrauth_vtable_pointer_type_discrimination); + Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_init_fini, + options::OPT_fno_ptrauth_init_fini); } void Clang::AddLoongArchTargetArgs(const ArgList &Args, diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 948fe08c863a..dbb5f5662ebf 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -3346,11 +3346,31 @@ static void GeneratePointerAuthArgs(const LangOptions &Opts, ArgumentConsumer Consumer) { if (Opts.PointerAuthIntrinsics) GenerateArg(Consumer, OPT_fptrauth_intrinsics); + if (Opts.PointerAuthCalls) + GenerateArg(Consumer, OPT_fptrauth_calls); + if (Opts.PointerAuthReturns) + GenerateArg(Consumer, OPT_fptrauth_returns); + if (Opts.PointerAuthAuthTraps) + GenerateArg(Consumer, OPT_fptrauth_auth_traps); + if (Opts.PointerAuthVTPtrAddressDiscrimination) + GenerateArg(Consumer, OPT_fptrauth_vtable_pointer_address_discrimination); + if (Opts.PointerAuthVTPtrTypeDiscrimination) + GenerateArg(Consumer, OPT_fptrauth_vtable_pointer_type_discrimination); + if (Opts.PointerAuthInitFini) + GenerateArg(Consumer, OPT_fptrauth_init_fini); } static void ParsePointerAuthArgs(LangOptions &Opts, ArgList &Args, DiagnosticsEngine &Diags) { Opts.PointerAuthIntrinsics = Args.hasArg(OPT_fptrauth_intrinsics); + Opts.PointerAuthCalls = Args.hasArg(OPT_fptrauth_calls); + Opts.PointerAuthReturns = Args.hasArg(OPT_fptrauth_returns); + Opts.PointerAuthAuthTraps = Args.hasArg(OPT_fptrauth_auth_traps); + Opts.PointerAuthVTPtrAddressDiscrimination = + Args.hasArg(OPT_fptrauth_vtable_pointer_address_discrimination); + Opts.PointerAuthVTPtrTypeDiscrimination = + Args.hasArg(OPT_fptrauth_vtable_pointer_type_discrimination); + Opts.PointerAuthInitFini = Args.hasArg(OPT_fptrauth_init_fini); } /// Check if input file kind and language standard are compatible. diff --git a/clang/test/CodeGen/aarch64-elf-pauthabi.c b/clang/test/CodeGen/aarch64-elf-pauthabi.c new file mode 100644 index 000000000000..aa83ee3e0d7b --- /dev/null +++ b/clang/test/CodeGen/aarch64-elf-pauthabi.c @@ -0,0 +1,59 @@ +// RUN: %clang_cc1 -triple aarch64-linux -emit-llvm -o - \ +// RUN: -fptrauth-intrinsics \ +// RUN: -fptrauth-calls \ +// RUN: -fptrauth-returns \ +// RUN: -fptrauth-auth-traps \ +// RUN: -fptrauth-vtable-pointer-address-discrimination \ +// RUN: -fptrauth-vtable-pointer-type-discrimination \ +// RUN: -fptrauth-init-fini %s | \ +// RUN: FileCheck %s --check-prefix=ALL + +// RUN: %clang_cc1 -triple aarch64-linux -emit-llvm -o - \ +// RUN: -fptrauth-intrinsics %s | FileCheck %s --check-prefix=INTRIN + +// RUN: %clang_cc1 -triple aarch64-linux -emit-llvm -o - \ +// RUN: -fptrauth-calls %s | FileCheck %s --check-prefix=CALL + +// RUN: %clang_cc1 -triple aarch64-linux -emit-llvm -o - \ +// RUN: -fptrauth-returns %s | FileCheck %s --check-prefix=RET + +// RUN: %clang_cc1 -triple aarch64-linux -emit-llvm -o - \ +// RUN: -fptrauth-auth-traps %s | FileCheck %s --check-prefix=TRAP + +// RUN: %clang_cc1 -triple aarch64-linux -emit-llvm -o - \ +// RUN: -fptrauth-calls -fptrauth-vtable-pointer-address-discrimination %s | \ +// RUN: FileCheck %s --check-prefix=VPTRADDR + +// RUN: %clang_cc1 -triple aarch64-linux -emit-llvm -o - \ +// RUN: -fptrauth-calls -fptrauth-vtable-pointer-type-discrimination %s | \ +// RUN: FileCheck %s --check-prefix=VPTRTYPE + +// RUN: %clang_cc1 -triple aarch64-linux -emit-llvm -o - \ +// RUN: -fptrauth-calls -fptrauth-init-fini %s | \ +// RUN: FileCheck %s --check-prefix=INITFINI + +// ALL: !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} +// ALL: !{i32 1, !"aarch64-elf-pauthabi-version", i32 127} + +// INTRIN: !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} +// INTRIN: !{i32 1, !"aarch64-elf-pauthabi-version", i32 1} + +// CALL: !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} +// CALL: !{i32 1, !"aarch64-elf-pauthabi-version", i32 2} + +// RET: !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} +// RET: !{i32 1, !"aarch64-elf-pauthabi-version", i32 4} + +// TRAP: !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} +// TRAP: !{i32 1, !"aarch64-elf-pauthabi-version", i32 8} + +// VPTRADDR: !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} +// VPTRADDR: !{i32 1, !"aarch64-elf-pauthabi-version", i32 18} + +// VPTRTYPE: !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} +// VPTRTYPE: !{i32 1, !"aarch64-elf-pauthabi-version", i32 34} + +// INITFINI: !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} +// INITFINI: !{i32 1, !"aarch64-elf-pauthabi-version", i32 66} + +void foo() {} diff --git a/clang/test/Driver/aarch64-ptrauth.c b/clang/test/Driver/aarch64-ptrauth.c index 1a69b2c6edfb..fa0125f4b22a 100644 --- a/clang/test/Driver/aarch64-ptrauth.c +++ b/clang/test/Driver/aarch64-ptrauth.c @@ -1,5 +1,25 @@ -// RUN: %clang -### -c --target=aarch64 -fno-ptrauth-intrinsics -fptrauth-intrinsics %s 2>&1 | FileCheck %s --check-prefix=INTRIN -// INTRIN: "-cc1"{{.*}} "-fptrauth-intrinsics" +// RUN: %clang -### -c --target=aarch64 %s 2>&1 | FileCheck %s --check-prefix NONE +// NONE: "-cc1" +// NONE-NOT: "-fptrauth- -// RUN: not %clang -### -c --target=x86_64 -fptrauth-intrinsics %s 2>&1 | FileCheck %s --check-prefix=ERR -// ERR: error: unsupported option '-fptrauth-intrinsics' for target '{{.*}}' +// RUN: %clang -### -c --target=aarch64 \ +// RUN: -fno-ptrauth-intrinsics -fptrauth-intrinsics \ +// RUN: -fno-ptrauth-calls -fptrauth-calls \ +// RUN: -fno-ptrauth-returns -fptrauth-returns \ +// RUN: -fno-ptrauth-auth-traps -fptrauth-auth-traps \ +// RUN: -fno-ptrauth-vtable-pointer-address-discrimination -fptrauth-vtable-pointer-address-discrimination \ +// RUN: -fno-ptrauth-vtable-pointer-type-discrimination -fptrauth-vtable-pointer-type-discrimination \ +// RUN: -fno-ptrauth-init-fini -fptrauth-init-fini \ +// RUN: %s 2>&1 | FileCheck %s --check-prefix=ALL +// ALL: "-cc1"{{.*}} "-fptrauth-intrinsics" "-fptrauth-calls" "-fptrauth-returns" "-fptrauth-auth-traps" "-fptrauth-vtable-pointer-address-discrimination" "-fptrauth-vtable-pointer-type-discrimination" "-fptrauth-init-fini" + +// RUN: not %clang -### -c --target=x86_64 -fptrauth-intrinsics -fptrauth-calls -fptrauth-returns -fptrauth-auth-traps \ +// RUN: -fptrauth-vtable-pointer-address-discrimination -fptrauth-vtable-pointer-type-discrimination \ +// RUN: -fptrauth-init-fini %s 2>&1 | FileCheck %s --check-prefix=ERR +// ERR: error: unsupported option '-fptrauth-intrinsics' for target '{{.*}}' +// ERR-NEXT: error: unsupported option '-fptrauth-calls' for target '{{.*}}' +// ERR-NEXT: error: unsupported option '-fptrauth-returns' for target '{{.*}}' +// ERR-NEXT: error: unsupported option '-fptrauth-auth-traps' for target '{{.*}}' +// ERR-NEXT: error: unsupported option '-fptrauth-vtable-pointer-address-discrimination' for target '{{.*}}' +// ERR-NEXT: error: unsupported option '-fptrauth-vtable-pointer-type-discrimination' for target '{{.*}}' +// ERR-NEXT: error: unsupported option '-fptrauth-init-fini' for target '{{.*}}' diff --git a/clang/test/Preprocessor/ptrauth_feature.c b/clang/test/Preprocessor/ptrauth_feature.c index e45c6ea90fd1..80e239110ffc 100644 --- a/clang/test/Preprocessor/ptrauth_feature.c +++ b/clang/test/Preprocessor/ptrauth_feature.c @@ -1,5 +1,59 @@ -// RUN: %clang_cc1 %s -E -triple=arm64-- | FileCheck %s --check-prefixes=NOINTRIN -// RUN: %clang_cc1 %s -E -triple=arm64-- -fptrauth-intrinsics | FileCheck %s --check-prefixes=INTRIN +// RUN: %clang_cc1 -E %s -triple=aarch64 \ +// RUN: -fptrauth-intrinsics \ +// RUN: -fptrauth-calls \ +// RUN: -fptrauth-returns \ +// RUN: -fptrauth-vtable-pointer-address-discrimination \ +// RUN: -fptrauth-vtable-pointer-type-discrimination \ +// RUN: -fptrauth-init-fini | \ +// RUN: FileCheck %s --check-prefixes=INTRIN,CALLS,RETS,VPTR_ADDR_DISCR,VPTR_TYPE_DISCR,INITFINI + +// RUN: %clang_cc1 -E %s -triple=aarch64 \ +// RUN: -fptrauth-calls \ +// RUN: -fptrauth-returns \ +// RUN: -fptrauth-vtable-pointer-address-discrimination \ +// RUN: -fptrauth-vtable-pointer-type-discrimination \ +// RUN: -fptrauth-init-fini | \ +// RUN: FileCheck %s --check-prefixes=NOINTRIN,CALLS,RETS,VPTR_ADDR_DISCR,VPTR_TYPE_DISCR,INITFINI + +// RUN: %clang_cc1 -E %s -triple=aarch64 \ +// RUN: -fptrauth-intrinsics \ +// RUN: -fptrauth-returns \ +// RUN: -fptrauth-vtable-pointer-address-discrimination \ +// RUN: -fptrauth-vtable-pointer-type-discrimination \ +// RUN: -fptrauth-init-fini | \ +// RUN: FileCheck %s --check-prefixes=INTRIN,NOCALLS,RETS,VPTR_ADDR_DISCR,VPTR_TYPE_DISCR,INITFINI + +// RUN: %clang_cc1 -E %s -triple=aarch64 \ +// RUN: -fptrauth-intrinsics \ +// RUN: -fptrauth-calls \ +// RUN: -fptrauth-vtable-pointer-address-discrimination \ +// RUN: -fptrauth-vtable-pointer-type-discrimination \ +// RUN: -fptrauth-init-fini | \ +// RUN: FileCheck %s --check-prefixes=INTRIN,CALLS,NORETS,VPTR_ADDR_DISCR,VPTR_TYPE_DISCR,INITFINI + +// RUN: %clang_cc1 -E %s -triple=aarch64 \ +// RUN: -fptrauth-intrinsics \ +// RUN: -fptrauth-calls \ +// RUN: -fptrauth-returns \ +// RUN: -fptrauth-vtable-pointer-type-discrimination \ +// RUN: -fptrauth-init-fini | \ +// RUN: FileCheck %s --check-prefixes=INTRIN,CALLS,RETS,NOVPTR_ADDR_DISCR,VPTR_TYPE_DISCR,INITFINI + +// RUN: %clang_cc1 -E %s -triple=aarch64 \ +// RUN: -fptrauth-intrinsics \ +// RUN: -fptrauth-calls \ +// RUN: -fptrauth-returns \ +// RUN: -fptrauth-vtable-pointer-address-discrimination \ +// RUN: -fptrauth-init-fini | \ +// RUN: FileCheck %s --check-prefixes=INTRIN,CALLS,RETS,VPTR_ADDR_DISCR,NOVPTR_TYPE_DISCR,INITFINI + +// RUN: %clang_cc1 -E %s -triple=aarch64 \ +// RUN: -fptrauth-intrinsics \ +// RUN: -fptrauth-calls \ +// RUN: -fptrauth-returns \ +// RUN: -fptrauth-vtable-pointer-address-discrimination \ +// RUN: -fptrauth-vtable-pointer-type-discrimination | \ +// RUN: FileCheck %s --check-prefixes=INTRIN,CALLS,RETS,VPTR_ADDR_DISCR,VPTR_TYPE_DISCR,NOINITFINI #if __has_feature(ptrauth_intrinsics) // INTRIN: has_ptrauth_intrinsics @@ -8,3 +62,52 @@ void has_ptrauth_intrinsics() {} // NOINTRIN: no_ptrauth_intrinsics void no_ptrauth_intrinsics() {} #endif + +#if __has_feature(ptrauth_calls) +// CALLS: has_ptrauth_calls +void has_ptrauth_calls() {} +#else +// NOCALLS: no_ptrauth_calls +void no_ptrauth_calls() {} +#endif + +// This is always enabled when ptrauth_calls is enabled +#if __has_feature(ptrauth_member_function_pointer_type_discrimination) +// CALLS: has_ptrauth_member_function_pointer_type_discrimination +void has_ptrauth_member_function_pointer_type_discrimination() {} +#else +// NOCALLS: no_ptrauth_member_function_pointer_type_discrimination +void no_ptrauth_member_function_pointer_type_discrimination() {} +#endif + +#if __has_feature(ptrauth_returns) +// RETS: has_ptrauth_returns +void has_ptrauth_returns() {} +#else +// NORETS: no_ptrauth_returns +void no_ptrauth_returns() {} +#endif + +#if __has_feature(ptrauth_vtable_pointer_address_discrimination) +// VPTR_ADDR_DISCR: has_ptrauth_vtable_pointer_address_discrimination +void has_ptrauth_vtable_pointer_address_discrimination() {} +#else +// NOVPTR_ADDR_DISCR: no_ptrauth_vtable_pointer_address_discrimination +void no_ptrauth_vtable_pointer_address_discrimination() {} +#endif + +#if __has_feature(ptrauth_vtable_pointer_type_discrimination) +// VPTR_TYPE_DISCR: has_ptrauth_vtable_pointer_type_discrimination +void has_ptrauth_vtable_pointer_type_discrimination() {} +#else +// NOVPTR_TYPE_DISCR: no_ptrauth_vtable_pointer_type_discrimination +void no_ptrauth_vtable_pointer_type_discrimination() {} +#endif + +#if __has_feature(ptrauth_init_fini) +// INITFINI: has_ptrauth_init_fini +void has_ptrauth_init_fini() {} +#else +// NOINITFINI: no_ptrauth_init_fini +void no_ptrauth_init_fini() {} +#endif -- GitLab From 6a8d30b1c1be5e46deb9b3a17915d488e1dbc470 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 9 May 2024 14:41:13 +0200 Subject: [PATCH 137/328] DAG: Skip 0 sign handling in minimum/maximum lowering for _ieee case (#91326) dc9664a8adae17f2083fbcc8e96cfce606c56d57 changed the documentation to assume these order -0 as less than +0. --- .../CodeGen/SelectionDAG/TargetLowering.cpp | 10 +- llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll | 3438 +++-------------- llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll | 267 +- llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll | 484 +-- llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll | 2600 ++----------- llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll | 267 +- llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll | 484 +-- .../test/CodeGen/PowerPC/fminimum-fmaximum.ll | 240 +- 8 files changed, 1286 insertions(+), 6504 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 9ec3ac4f9991..7beaeb9b7a17 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -8401,8 +8401,14 @@ SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N, SDValue MinMax; unsigned CompOpcIeee = IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE; unsigned CompOpc = IsMax ? ISD::FMAXNUM : ISD::FMINNUM; + + // FIXME: We should probably define fminnum/fmaxnum variants with correct + // signed zero behavior. + bool MinMaxMustRespectOrderedZero = false; + if (isOperationLegalOrCustom(CompOpcIeee, VT)) { MinMax = DAG.getNode(CompOpcIeee, DL, VT, LHS, RHS); + MinMaxMustRespectOrderedZero = true; } else if (isOperationLegalOrCustom(CompOpc, VT)) { MinMax = DAG.getNode(CompOpc, DL, VT, LHS, RHS); } else { @@ -8422,8 +8428,8 @@ SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N, } // fminimum/fmaximum requires -0.0 less than +0.0 - if (!N->getFlags().hasNoSignedZeros() && !DAG.isKnownNeverZeroFloat(RHS) && - !DAG.isKnownNeverZeroFloat(LHS)) { + if (!MinMaxMustRespectOrderedZero && !N->getFlags().hasNoSignedZeros() && + !DAG.isKnownNeverZeroFloat(RHS) && !DAG.isKnownNeverZeroFloat(LHS)) { SDValue IsZero = DAG.getSetCC(DL, CCVT, MinMax, DAG.getConstantFP(0.0, DL, VT), ISD::SETEQ); SDValue TestZero = diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll index c476208ed8f4..7d7a46259710 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll @@ -18,13 +18,7 @@ define half @v_maximum_f16(half %src0, half %src1) { ; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_max_f32_e32 v3, v0, v1 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_f16: @@ -33,13 +27,7 @@ define half @v_maximum_f16(half %src0, half %src1) { ; GFX8-NEXT: v_max_f16_e32 v2, v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_f16: @@ -48,13 +36,7 @@ define half @v_maximum_f16(half %src0, half %src1) { ; GFX9-NEXT: v_max_f16_e32 v2, v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_f16: @@ -64,16 +46,7 @@ define half @v_maximum_f16(half %src0, half %src1) { ; GFX940-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_f16: @@ -81,13 +54,7 @@ define half @v_maximum_f16(half %src0, half %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_max_f16_e32 v2, v0, v1 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_f16: @@ -95,15 +62,8 @@ define half @v_maximum_f16(half %src0, half %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_max_f16_e32 v2, v0, v1 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_f16: @@ -127,78 +87,37 @@ define half @v_maximum_f16__nnan(half %src0, half %src1) { ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_max_f32_e32 v2, v0, v1 -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_max_f32_e32 v0, v0, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_f16__nnan: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_max_f16_e32 v2, v0, v1 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_max_f16_e32 v0, v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_f16__nnan: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_max_f16_e32 v2, v0, v1 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_max_f16_e32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_f16__nnan: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_max_f16_e32 v2, v0, v1 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_max_f16_e32 v0, v0, v1 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_f16__nnan: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_max_f16_e32 v2, v0, v1 -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_max_f16_e32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_f16__nnan: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f16_e32 v2, v0, v1 -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: v_max_f16_e32 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_f16__nnan: @@ -352,13 +271,7 @@ define half @v_maximum_f16__nnan_src0(half %arg0, half %src1) { ; GFX7-NEXT: v_add_f32_e32 v0, 1.0, v0 ; GFX7-NEXT: v_max_f32_e32 v3, v0, v1 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_f16__nnan_src0: @@ -368,13 +281,7 @@ define half @v_maximum_f16__nnan_src0(half %arg0, half %src1) { ; GFX8-NEXT: v_max_f16_e32 v2, v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_f16__nnan_src0: @@ -384,13 +291,7 @@ define half @v_maximum_f16__nnan_src0(half %arg0, half %src1) { ; GFX9-NEXT: v_max_f16_e32 v2, v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_f16__nnan_src0: @@ -401,16 +302,7 @@ define half @v_maximum_f16__nnan_src0(half %arg0, half %src1) { ; GFX940-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_f16__nnan_src0: @@ -419,13 +311,7 @@ define half @v_maximum_f16__nnan_src0(half %arg0, half %src1) { ; GFX10-NEXT: v_add_f16_e32 v0, 1.0, v0 ; GFX10-NEXT: v_max_f16_e32 v2, v0, v1 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_f16__nnan_src0: @@ -435,15 +321,7 @@ define half @v_maximum_f16__nnan_src0(half %arg0, half %src1) { ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_max_f16_e32 v2, v0, v1 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_f16__nnan_src0: @@ -474,13 +352,7 @@ define half @v_maximum_f16__nnan_src1(half %src0, half %arg1) { ; GFX7-NEXT: v_add_f32_e32 v1, 1.0, v1 ; GFX7-NEXT: v_max_f32_e32 v3, v0, v1 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_f16__nnan_src1: @@ -490,13 +362,7 @@ define half @v_maximum_f16__nnan_src1(half %src0, half %arg1) { ; GFX8-NEXT: v_max_f16_e32 v2, v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_f16__nnan_src1: @@ -506,13 +372,7 @@ define half @v_maximum_f16__nnan_src1(half %src0, half %arg1) { ; GFX9-NEXT: v_max_f16_e32 v2, v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_f16__nnan_src1: @@ -523,16 +383,7 @@ define half @v_maximum_f16__nnan_src1(half %src0, half %arg1) { ; GFX940-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_f16__nnan_src1: @@ -541,13 +392,7 @@ define half @v_maximum_f16__nnan_src1(half %src0, half %arg1) { ; GFX10-NEXT: v_add_f16_e32 v1, 1.0, v1 ; GFX10-NEXT: v_max_f16_e32 v2, v0, v1 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_f16__nnan_src1: @@ -557,15 +402,7 @@ define half @v_maximum_f16__nnan_src1(half %src0, half %arg1) { ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_max_f16_e32 v2, v0, v1 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_f16__nnan_src1: @@ -595,13 +432,7 @@ define void @s_maximum_f16(half inreg %src0, half inreg %src1) { ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-NEXT: v_max_f32_e32 v3, v1, v0 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: ;;#ASMSTART ; GFX7-NEXT: ; use v0 @@ -615,14 +446,7 @@ define void @s_maximum_f16(half inreg %src0, half inreg %src1) { ; GFX8-NEXT: v_max_f16_e32 v1, s4, v0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, s4, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX8-NEXT: v_mov_b32_e32 v2, s4 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, s4, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, s5, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use v0 @@ -636,14 +460,7 @@ define void @s_maximum_f16(half inreg %src0, half inreg %src1) { ; GFX9-NEXT: v_max_f16_e32 v1, s4, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, s4, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX9-NEXT: v_mov_b32_e32 v2, s4 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, s4, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, s5, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; use v0 @@ -658,17 +475,7 @@ define void @s_maximum_f16(half inreg %src0, half inreg %src1) { ; GFX940-NEXT: v_mov_b32_e32 v2, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, s0, v0 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX940-NEXT: v_mov_b32_e32 v2, s0 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, s0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, s1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX940-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX940-NEXT: ;;#ASMSTART ; GFX940-NEXT: ; use v0 @@ -680,13 +487,7 @@ define void @s_maximum_f16(half inreg %src0, half inreg %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_max_f16_e64 v0, s4, s5 ; GFX10-NEXT: v_cmp_o_f16_e64 vcc_lo, s4, s5 -; GFX10-NEXT: v_cmp_class_f16_e64 s6, s4, 64 ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v1, v0, s4, s6 -; GFX10-NEXT: v_cmp_class_f16_e64 s4, s5, 64 -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s5, s4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use v0 @@ -698,16 +499,8 @@ define void @s_maximum_f16(half inreg %src0, half inreg %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_max_f16_e64 v0, s0, s1 ; GFX11-NEXT: v_cmp_o_f16_e64 vcc_lo, s0, s1 -; GFX11-NEXT: v_cmp_class_f16_e64 s2, s0, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v0, s0, s2 -; GFX11-NEXT: v_cmp_class_f16_e64 s0, s1, 64 -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s1, s0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use v0 @@ -750,22 +543,10 @@ define <2 x half> @v_maximum_v2f16(<2 x half> %src0, <2 x half> %src1) { ; GFX7-NEXT: v_mov_b32_e32 v5, 0x7fc00000 ; GFX7-NEXT: v_max_f32_e32 v4, v0, v2 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v2, v1, v3 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v2f16: @@ -805,23 +586,9 @@ define <2 x half> @v_maximum_v2f16(<2 x half> %src0, <2 x half> %src1) { ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_mov_b32 s4, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -835,30 +602,10 @@ define <2 x half> @v_maximum_v2f16(<2 x half> %src0, <2 x half> %src1) { ; GFX940-NEXT: s_mov_b32 s0, 0x5040100 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 ; GFX940-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: v_perm_b32 v0, v0, v4, s0 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; @@ -866,26 +613,12 @@ define <2 x half> @v_maximum_v2f16(<2 x half> %src0, <2 x half> %src1) { ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_max_f16 v2, v0, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v0 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo -; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo +; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_v2f16: @@ -897,25 +630,10 @@ define <2 x half> @v_maximum_v2f16(<2 x half> %src0, <2 x half> %src1) { ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v5, vcc_lo ; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; @@ -947,22 +665,10 @@ define <2 x half> @v_maximum_v2f16__nnan(<2 x half> %src0, <2 x half> %src1) { ; GFX7-NEXT: v_mov_b32_e32 v5, 0x7fc00000 ; GFX7-NEXT: v_max_f32_e32 v4, v0, v2 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v2, v1, v3 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v2f16__nnan: @@ -993,100 +699,25 @@ define <2 x half> @v_maximum_v2f16__nnan(<2 x half> %src0, <2 x half> %src1) { ; GFX9-LABEL: v_maximum_v2f16__nnan: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GFX9-NEXT: v_pk_max_f16 v3, v0, v1 -; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX9-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4 +; GFX9-NEXT: v_pk_max_f16 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_v2f16__nnan: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GFX940-NEXT: v_pk_max_f16 v3, v0, v1 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX940-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX940-NEXT: s_mov_b32 s0, 0x5040100 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX940-NEXT: v_perm_b32 v0, v2, v0, s0 +; GFX940-NEXT: v_pk_max_f16 v0, v0, v1 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_v2f16__nnan: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_pk_max_f16 v2, v0, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX10-NEXT: v_pk_max_f16 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_v2f16__nnan: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_pk_max_f16 v2, v0, v1 -; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-NEXT: v_pk_max_f16 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_v2f16__nnan: @@ -1117,22 +748,10 @@ define <2 x half> @v_maximum_v2f16__nsz(<2 x half> %src0, <2 x half> %src1) { ; GFX7-NEXT: v_mov_b32_e32 v5, 0x7fc00000 ; GFX7-NEXT: v_max_f32_e32 v4, v0, v2 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v2, v1, v3 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v2f16__nsz: @@ -1239,22 +858,10 @@ define <2 x half> @v_maximum_v2f16__nnan_nsz(<2 x half> %src0, <2 x half> %src1) ; GFX7-NEXT: v_mov_b32_e32 v5, 0x7fc00000 ; GFX7-NEXT: v_max_f32_e32 v4, v0, v2 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v2, v1, v3 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v2f16__nnan_nsz: @@ -1322,23 +929,11 @@ define void @s_maximum_v2f16(<2 x half> inreg %src0, <2 x half> inreg %src1) { ; GFX7-NEXT: v_mov_b32_e32 v5, 0x7fc00000 ; GFX7-NEXT: v_max_f32_e32 v4, v1, v0 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v1, v3, v2 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 ; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX7-NEXT: v_or_b32_e32 v0, v1, v0 @@ -1389,30 +984,16 @@ define void @s_maximum_v2f16(<2 x half> inreg %src0, <2 x half> inreg %src1) { ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v0, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: s_lshr_b32 s5, s5, 16 ; GFX9-NEXT: v_pk_max_f16 v1, s4, v1 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, s4, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v2, v1, vcc -; GFX9-NEXT: v_mov_b32_e32 v4, s4 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, s4, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, s5, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX9-NEXT: s_lshr_b32 s5, s5, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX9-NEXT: s_lshr_b32 s4, s4, 16 ; GFX9-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, s4, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX9-NEXT: v_mov_b32_e32 v2, s4 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, s4, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, s5, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX9-NEXT: ;;#ASMSTART @@ -1425,38 +1006,18 @@ define void @s_maximum_v2f16(<2 x half> inreg %src0, <2 x half> inreg %src1) { ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX940-NEXT: v_mov_b32_e32 v0, s1 ; GFX940-NEXT: v_mov_b32_e32 v1, s1 +; GFX940-NEXT: s_lshr_b32 s1, s1, 16 ; GFX940-NEXT: v_pk_max_f16 v1, s0, v1 ; GFX940-NEXT: v_mov_b32_e32 v2, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, s0, v0 -; GFX940-NEXT: v_mov_b32_e32 v4, s0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v2, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, s0, 64 ; GFX940-NEXT: s_lshr_b32 s0, s0, 16 -; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, s1, 64 -; GFX940-NEXT: s_lshr_b32 s1, s1, 16 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX940-NEXT: v_mov_b32_e32 v3, s1 +; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, s0, v3 ; GFX940-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX940-NEXT: v_mov_b32_e32 v2, s0 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, s0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, s1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX940-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX940-NEXT: ;;#ASMSTART ; GFX940-NEXT: ; use v0 @@ -1469,24 +1030,12 @@ define void @s_maximum_v2f16(<2 x half> inreg %src0, <2 x half> inreg %src1) { ; GFX10-NEXT: v_pk_max_f16 v0, s4, s5 ; GFX10-NEXT: v_cmp_o_f16_e64 vcc_lo, s4, s5 ; GFX10-NEXT: s_lshr_b32 s6, s5, 16 -; GFX10-NEXT: s_lshr_b32 s7, s4, 16 -; GFX10-NEXT: v_cmp_class_f16_e64 s8, s4, 64 +; GFX10-NEXT: s_lshr_b32 s4, s4, 16 ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e64 vcc_lo, s7, s6 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v0, s4, s8 -; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 s4, s7, 64 -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v1, s7, s4 -; GFX10-NEXT: v_cmp_class_f16_e64 s4, s5, 64 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s5, s4 -; GFX10-NEXT: v_cmp_class_f16_e64 s4, s6, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s6, s4 -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1 +; GFX10-NEXT: v_cmp_o_f16_e64 vcc_lo, s4, s6 ; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v1, vcc_lo ; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use v0 @@ -1499,27 +1048,14 @@ define void @s_maximum_v2f16(<2 x half> inreg %src0, <2 x half> inreg %src1) { ; GFX11-NEXT: v_pk_max_f16 v0, s0, s1 ; GFX11-NEXT: v_cmp_o_f16_e64 vcc_lo, s0, s1 ; GFX11-NEXT: s_lshr_b32 s2, s1, 16 -; GFX11-NEXT: s_lshr_b32 s3, s0, 16 -; GFX11-NEXT: v_cmp_class_f16_e64 s4, s0, 64 +; GFX11-NEXT: s_lshr_b32 s0, s0, 16 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e64 vcc_lo, s3, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e64 v2, v0, s0, s4 +; GFX11-NEXT: v_cmp_o_f16_e64 vcc_lo, s0, s2 +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 s0, s3, 64 -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v3, v1, s3, s0 -; GFX11-NEXT: v_cmp_class_f16_e64 s0, s1, 64 -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s1, s0 -; GFX11-NEXT: v_cmp_class_f16_e64 s0, s2, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s2, s0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_and_b32 v0, 0xffff, v0 ; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use v0 @@ -1552,42 +1088,24 @@ define <3 x half> @v_maximum_v3f16(<3 x half> %src0, <3 x half> %src1) { ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4 ; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 -; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5 ; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 +; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX7-NEXT: v_max_f32_e32 v6, v0, v3 ; GFX7-NEXT: v_mov_b32_e32 v7, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 -; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 -; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v6, vcc ; GFX7-NEXT: v_max_f32_e32 v3, v1, v4 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v4, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc ; GFX7-NEXT: v_max_f32_e32 v3, v2, v5 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v5 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v5, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v3f16: @@ -1598,31 +1116,13 @@ define <3 x half> @v_maximum_v3f16(<3 x half> %src0, <3 x half> %src1) { ; GFX8-NEXT: v_max_f16_e32 v6, v5, v4 ; GFX8-NEXT: v_mov_b32_e32 v7, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v5, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc ; GFX8-NEXT: v_max_f16_e32 v5, v1, v3 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc ; GFX8-NEXT: v_max_f16_e32 v3, v0, v2 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v3, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -1633,33 +1133,13 @@ define <3 x half> @v_maximum_v3f16(<3 x half> %src0, <3 x half> %src1) { ; GFX9-NEXT: v_pk_max_f16 v4, v1, v3 ; GFX9-NEXT: v_mov_b32_e32 v5, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc ; GFX9-NEXT: v_pk_max_f16 v3, v0, v2 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc ; GFX9-NEXT: s_mov_b32 s4, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -1670,46 +1150,16 @@ define <3 x half> @v_maximum_v3f16(<3 x half> %src0, <3 x half> %src1) { ; GFX940-NEXT: v_pk_max_f16 v4, v1, v3 ; GFX940-NEXT: v_mov_b32_e32 v5, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 -; GFX940-NEXT: s_mov_b32 s0, 0x5040100 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 ; GFX940-NEXT: v_pk_max_f16 v3, v0, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX940-NEXT: s_mov_b32 s0, 0x5040100 +; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 ; GFX940-NEXT: s_nop 1 ; GFX940-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 ; GFX940-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX940-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc ; GFX940-NEXT: v_perm_b32 v0, v0, v4, s0 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; @@ -1717,35 +1167,15 @@ define <3 x half> @v_maximum_v3f16(<3 x half> %src0, <3 x half> %src1) { ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_max_f16 v4, v0, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v0 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2 -; GFX10-NEXT: v_pk_max_f16 v8, v1, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v4 +; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v4, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v7, 0x7e00, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_pk_max_f16 v2, v1, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v8, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo +; GFX10-NEXT: v_perm_b32 v0, v0, v4, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_v3f16: @@ -1755,35 +1185,17 @@ define <3 x half> @v_maximum_v3f16(<3 x half> %src0, <3 x half> %src1) { ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v0 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_pk_max_f16 v8, v1, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v4, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v7, 0x7e00, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo +; GFX11-NEXT: v_pk_max_f16 v4, v1, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v7, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3 -; GFX11-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v8, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v6, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v7 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_v3f16: @@ -1808,201 +1220,61 @@ define <3 x half> @v_maximum_v3f16__nnan(<3 x half> %src0, <3 x half> %src1) { ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4 ; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 -; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5 ; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 +; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX7-NEXT: v_max_f32_e32 v6, v0, v3 ; GFX7-NEXT: v_mov_b32_e32 v7, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 -; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 -; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v6, vcc ; GFX7-NEXT: v_max_f32_e32 v3, v1, v4 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v4, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc ; GFX7-NEXT: v_max_f32_e32 v3, v2, v5 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v5 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v5, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v3f16__nnan: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 -; GFX8-NEXT: v_max_f16_e32 v6, v5, v4 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX8-NEXT: v_max_f16_e32 v5, v1, v3 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_max_f16_e32 v3, v0, v2 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 -; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v2 +; GFX8-NEXT: v_max_f16_e32 v1, v1, v3 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_v3f16__nnan: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v0 -; GFX9-NEXT: v_pk_max_f16 v5, v0, v2 -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX9-NEXT: v_pk_max_f16 v6, v1, v3 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX9-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4 +; GFX9-NEXT: v_pk_max_f16 v0, v0, v2 +; GFX9-NEXT: v_pk_max_f16 v1, v1, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_v3f16__nnan: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v0 -; GFX940-NEXT: v_pk_max_f16 v5, v0, v2 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX940-NEXT: v_lshrrev_b32_e32 v7, 16, v2 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX940-NEXT: s_mov_b32 s0, 0x5040100 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX940-NEXT: v_pk_max_f16 v6, v1, v3 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX940-NEXT: v_perm_b32 v0, v4, v0, s0 +; GFX940-NEXT: v_pk_max_f16 v0, v0, v2 +; GFX940-NEXT: v_pk_max_f16 v1, v1, v3 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_v3f16__nnan: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_pk_max_f16 v4, v0, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v0 -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v2 -; GFX10-NEXT: v_pk_max_f16 v8, v1, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo +; GFX10-NEXT: v_pk_max_f16 v0, v0, v2 +; GFX10-NEXT: v_pk_max_f16 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_v3f16__nnan: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_pk_max_f16 v4, v0, v2 -; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0 -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v2 -; GFX11-NEXT: v_pk_max_f16 v8, v1, v3 -; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v6 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 +; GFX11-NEXT: v_pk_max_f16 v0, v0, v2 +; GFX11-NEXT: v_pk_max_f16 v1, v1, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_v3f16__nnan: @@ -2027,42 +1299,24 @@ define <3 x half> @v_maximum_v3f16__nsz(<3 x half> %src0, <3 x half> %src1) { ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4 ; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 -; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5 ; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 +; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX7-NEXT: v_max_f32_e32 v6, v0, v3 ; GFX7-NEXT: v_mov_b32_e32 v7, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 -; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 -; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v6, vcc ; GFX7-NEXT: v_max_f32_e32 v3, v1, v4 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v4, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc ; GFX7-NEXT: v_max_f32_e32 v3, v2, v5 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v5 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v5, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v3f16__nsz: @@ -2177,42 +1431,24 @@ define <3 x half> @v_maximum_v3f16__nnan_nsz(<3 x half> %src0, <3 x half> %src1) ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4 ; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 -; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5 ; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 +; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX7-NEXT: v_max_f32_e32 v6, v0, v3 ; GFX7-NEXT: v_mov_b32_e32 v7, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v6 -; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 -; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v6, vcc ; GFX7-NEXT: v_max_f32_e32 v3, v1, v4 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v4, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc ; GFX7-NEXT: v_max_f32_e32 v3, v2, v5 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v5 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v5, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v3f16__nnan_nsz: @@ -2274,55 +1510,31 @@ define <4 x half> @v_maximum_v4f16(<4 x half> %src0, <4 x half> %src1) { ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5 ; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 -; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v6, v6 ; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 +; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 +; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 +; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 +; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 ; GFX7-NEXT: v_max_f32_e32 v8, v0, v4 ; GFX7-NEXT: v_mov_b32_e32 v9, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v4, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 -; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3 -; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 -; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc ; GFX7-NEXT: v_max_f32_e32 v4, v1, v5 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v5 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v5, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 -; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v4, v2, v6 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v6 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v6, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v2, v9, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v4, v3, v7 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v7 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v7, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v4f16: @@ -2333,42 +1545,18 @@ define <4 x half> @v_maximum_v4f16(<4 x half> %src0, <4 x half> %src1) { ; GFX8-NEXT: v_max_f16_e32 v6, v5, v4 ; GFX8-NEXT: v_mov_b32_e32 v7, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v5, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 ; GFX8-NEXT: v_max_f16_e32 v8, v6, v5 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v6, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v7, v8, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc ; GFX8-NEXT: v_max_f16_e32 v6, v1, v3 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc ; GFX8-NEXT: v_max_f16_e32 v3, v0, v2 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v3, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 @@ -2382,43 +1570,15 @@ define <4 x half> @v_maximum_v4f16(<4 x half> %src0, <4 x half> %src1) { ; GFX9-NEXT: v_mov_b32_e32 v5, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v6, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc ; GFX9-NEXT: v_pk_max_f16 v3, v0, v2 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v4, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v2, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc ; GFX9-NEXT: s_mov_b32 s4, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4 ; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4 @@ -2433,59 +1593,19 @@ define <4 x half> @v_maximum_v4f16(<4 x half> %src0, <4 x half> %src1) { ; GFX940-NEXT: s_mov_b32 s0, 0x5040100 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 ; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v6, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX940-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_max_f16 v3, v0, v2 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 ; GFX940-NEXT: v_perm_b32 v1, v1, v6, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 ; GFX940-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v4, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v7, v2, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX940-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc ; GFX940-NEXT: v_perm_b32 v0, v0, v4, s0 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; @@ -2494,46 +1614,18 @@ define <4 x half> @v_maximum_v4f16(<4 x half> %src0, <4 x half> %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_max_f16 v4, v1, v3 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GFX10-NEXT: v_pk_max_f16 v7, v0, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v4, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo +; GFX10-NEXT: v_pk_max_f16 v5, v0, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v4, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v11, 0x7e00, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v4, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v10, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v7, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v4, v10, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v3, v6, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v3 -; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo -; GFX10-NEXT: v_perm_b32 v1, v3, v1, 0x5040100 +; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v5 +; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v5, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v7, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_perm_b32 v0, v0, v5, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo +; GFX10-NEXT: v_perm_b32 v1, v1, v6, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_v4f16: @@ -2541,47 +1633,23 @@ define <4 x half> @v_maximum_v4f16(<4 x half> %src0, <4 x half> %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_pk_max_f16 v4, v1, v3 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3 +; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v1 ; GFX11-NEXT: v_pk_max_f16 v7, v0, v2 -; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v4, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v0 -; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v2 +; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v11, 0x7e00, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v7 +; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v7, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v8 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v9, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v4, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v10, v9 -; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v7, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v4, v10, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v3, v6, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v11 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v3 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v4, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_perm_b32 v1, v3, v1, 0x5040100 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; @@ -2607,266 +1675,70 @@ define <4 x half> @v_maximum_v4f16__nnan(<4 x half> %src0, <4 x half> %src1) { ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5 ; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 -; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v6, v6 ; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 +; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 +; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 +; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 +; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 ; GFX7-NEXT: v_max_f32_e32 v8, v0, v4 ; GFX7-NEXT: v_mov_b32_e32 v9, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v4, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 -; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3 -; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 -; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc ; GFX7-NEXT: v_max_f32_e32 v4, v1, v5 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v5 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v5, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 -; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v4, v2, v6 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v6 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v6, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v2, v9, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v4, v3, v7 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v7 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v7, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v4f16__nnan: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX8-NEXT: v_max_f16_e32 v6, v5, v4 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX8-NEXT: v_max_f16_e32 v7, v6, v5 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX8-NEXT: v_max_f16_e32 v6, v1, v3 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX8-NEXT: v_max_f16_e32 v3, v0, v2 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5 -; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 -; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_max_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_e32 v1, v1, v3 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v5 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_v4f16__nnan: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v1 -; GFX9-NEXT: v_pk_max_f16 v5, v1, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX9-NEXT: v_pk_max_f16 v7, v0, v2 -; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v7 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v9, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc -; GFX9-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-NEXT: v_perm_b32 v0, v6, v0, s4 -; GFX9-NEXT: v_perm_b32 v1, v4, v1, s4 +; GFX9-NEXT: v_pk_max_f16 v0, v0, v2 +; GFX9-NEXT: v_pk_max_f16 v1, v1, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_v4f16__nnan: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v1 -; GFX940-NEXT: v_pk_max_f16 v5, v1, v3 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX940-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v9, 16, v2 -; GFX940-NEXT: s_mov_b32 s0, 0x5040100 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX940-NEXT: v_pk_max_f16 v7, v0, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX940-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX940-NEXT: v_lshrrev_b32_e32 v8, 16, v7 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v9, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX940-NEXT: v_perm_b32 v1, v4, v1, s0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc -; GFX940-NEXT: v_perm_b32 v0, v6, v0, s0 +; GFX940-NEXT: v_pk_max_f16 v0, v0, v2 +; GFX940-NEXT: v_pk_max_f16 v1, v1, v3 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_v4f16__nnan: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_pk_max_f16 v4, v1, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX10-NEXT: v_pk_max_f16 v6, v0, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v4 -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v7, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo -; GFX10-NEXT: v_perm_b32 v1, v5, v1, 0x5040100 +; GFX10-NEXT: v_pk_max_f16 v0, v0, v2 +; GFX10-NEXT: v_pk_max_f16 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_v4f16__nnan: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_pk_max_f16 v4, v1, v3 -; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX11-NEXT: v_pk_max_f16 v6, v0, v2 -; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v0 -; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v4 -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v6 -; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v11 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v11, v7, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v6 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo -; GFX11-NEXT: v_perm_b32 v1, v5, v1, 0x5040100 +; GFX11-NEXT: v_pk_max_f16 v0, v0, v2 +; GFX11-NEXT: v_pk_max_f16 v1, v1, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_v4f16__nnan: @@ -2891,55 +1763,31 @@ define <4 x half> @v_maximum_v4f16__nsz(<4 x half> %src0, <4 x half> %src1) { ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5 ; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 -; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v6, v6 ; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 +; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 +; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 +; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 +; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 ; GFX7-NEXT: v_max_f32_e32 v8, v0, v4 ; GFX7-NEXT: v_mov_b32_e32 v9, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v4, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 -; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3 -; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 -; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc ; GFX7-NEXT: v_max_f32_e32 v4, v1, v5 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v5 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v5, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 -; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v4, v2, v6 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v6 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v6, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v2, v9, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v4, v3, v7 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v7 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v7, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v4f16__nsz: @@ -3080,55 +1928,31 @@ define <4 x half> @v_maximum_v4f16__nnan_nsz(<4 x half> %src0, <4 x half> %src1) ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5 ; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 -; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v6, v6 ; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 +; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 +; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 +; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 +; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 ; GFX7-NEXT: v_max_f32_e32 v8, v0, v4 ; GFX7-NEXT: v_mov_b32_e32 v9, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v4, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 -; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3 -; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 -; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc ; GFX7-NEXT: v_max_f32_e32 v4, v1, v5 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v5 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v5, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 -; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v4, v2, v6 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v6 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v6, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v2, v9, v4, vcc ; GFX7-NEXT: v_max_f32_e32 v4, v3, v7 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v7 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v7, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v4f16__nnan_nsz: @@ -3192,107 +2016,59 @@ define <8 x half> @v_maximum_v8f16(<8 x half> %src0, <8 x half> %src1) { ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v9, v9 ; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 -; GFX7-NEXT: v_cvt_f32_f16_e32 v8, v8 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v10, v10 ; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX7-NEXT: v_cvt_f16_f32_e32 v11, v11 +; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX7-NEXT: v_cvt_f16_f32_e32 v12, v12 +; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4 +; GFX7-NEXT: v_cvt_f32_f16_e32 v8, v8 +; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-NEXT: v_cvt_f16_f32_e32 v13, v13 +; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5 ; GFX7-NEXT: v_cvt_f32_f16_e32 v9, v9 ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-NEXT: v_cvt_f16_f32_e32 v14, v14 +; GFX7-NEXT: v_cvt_f16_f32_e32 v6, v6 +; GFX7-NEXT: v_cvt_f32_f16_e32 v10, v10 +; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX7-NEXT: v_cvt_f16_f32_e32 v15, v15 +; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 +; GFX7-NEXT: v_cvt_f32_f16_e32 v11, v11 +; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX7-NEXT: v_cvt_f32_f16_e32 v12, v12 +; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 ; GFX7-NEXT: v_max_f32_e32 v16, v0, v8 ; GFX7-NEXT: v_mov_b32_e32 v17, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v8 -; GFX7-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v8, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v16 -; GFX7-NEXT: v_cvt_f16_f32_e32 v11, v11 -; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3 -; GFX7-NEXT: v_cvt_f32_f16_e32 v10, v10 -; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc +; GFX7-NEXT: v_cvt_f32_f16_e32 v13, v13 +; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 +; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v16, vcc ; GFX7-NEXT: v_max_f32_e32 v8, v1, v9 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v9 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v9, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX7-NEXT: v_cvt_f16_f32_e32 v12, v12 -; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4 -; GFX7-NEXT: v_cvt_f32_f16_e32 v11, v11 -; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc +; GFX7-NEXT: v_cvt_f32_f16_e32 v14, v14 +; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 +; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v8, vcc ; GFX7-NEXT: v_max_f32_e32 v8, v2, v10 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v10 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v10, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX7-NEXT: v_cvt_f16_f32_e32 v13, v13 -; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5 -; GFX7-NEXT: v_cvt_f32_f16_e32 v12, v12 -; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc +; GFX7-NEXT: v_cvt_f32_f16_e32 v15, v15 +; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 +; GFX7-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc ; GFX7-NEXT: v_max_f32_e32 v8, v3, v11 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v11 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v11, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX7-NEXT: v_cvt_f16_f32_e32 v14, v14 -; GFX7-NEXT: v_cvt_f16_f32_e32 v6, v6 -; GFX7-NEXT: v_cvt_f32_f16_e32 v13, v13 -; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v8, vcc ; GFX7-NEXT: v_max_f32_e32 v8, v4, v12 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v4, v12 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v4, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v12, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX7-NEXT: v_cvt_f16_f32_e32 v15, v15 -; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 -; GFX7-NEXT: v_cvt_f32_f16_e32 v14, v14 -; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v4, v17, v8, vcc ; GFX7-NEXT: v_max_f32_e32 v8, v5, v13 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v5, v13 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v5, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v13, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX7-NEXT: v_cvt_f32_f16_e32 v15, v15 -; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v5, v17, v8, vcc ; GFX7-NEXT: v_max_f32_e32 v8, v6, v14 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v6, v14 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v6, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v14, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v6, v17, v8, vcc ; GFX7-NEXT: v_max_f32_e32 v8, v7, v15 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v7, v15 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v7, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v15, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v8 -; GFX7-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v7, v17, v8, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v8f16: @@ -3303,82 +2079,34 @@ define <8 x half> @v_maximum_v8f16(<8 x half> %src0, <8 x half> %src1) { ; GFX8-NEXT: v_max_f16_e32 v10, v9, v8 ; GFX8-NEXT: v_mov_b32_e32 v11, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v9, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v9, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v8, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v10, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v6 ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2 ; GFX8-NEXT: v_max_f16_e32 v12, v10, v9 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v10, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v11, v12, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v10, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v9, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v5 ; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v1 ; GFX8-NEXT: v_max_f16_e32 v13, v12, v10 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v12, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v11, v13, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v12, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v10, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v4 ; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v0 ; GFX8-NEXT: v_max_f16_e32 v14, v13, v12 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v13, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v14, v11, v14, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v13, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v14, v13, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v12, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v12, v11, v14, vcc ; GFX8-NEXT: v_max_f16_e32 v13, v3, v7 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v3, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v11, v13, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v13, vcc ; GFX8-NEXT: v_max_f16_e32 v7, v2, v6 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v2, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v7, vcc ; GFX8-NEXT: v_max_f16_e32 v6, v1, v5 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v11, v6, vcc ; GFX8-NEXT: v_max_f16_e32 v5, v0, v4 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v11, v5, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v12 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v10 @@ -3396,83 +2124,27 @@ define <8 x half> @v_maximum_v8f16(<8 x half> %src0, <8 x half> %src1) { ; GFX9-NEXT: v_mov_b32_e32 v9, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v7 ; GFX9-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v10, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v7, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v7 -; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v8, vcc ; GFX9-NEXT: v_pk_max_f16 v7, v2, v6 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v2, v6 ; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v7, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v8, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v6, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v2, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v7, vcc ; GFX9-NEXT: v_pk_max_f16 v6, v1, v5 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v5 ; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v6, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v7, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v5, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v6, vcc ; GFX9-NEXT: v_pk_max_f16 v5, v0, v4 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v6, v9, v5, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v6, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v4, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v4 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v5, vcc ; GFX9-NEXT: s_mov_b32 s4, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v0, v6, s4 ; GFX9-NEXT: v_perm_b32 v1, v1, v7, s4 @@ -3489,117 +2161,37 @@ define <8 x half> @v_maximum_v8f16(<8 x half> %src0, <8 x half> %src1) { ; GFX940-NEXT: s_mov_b32 s0, 0x5040100 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 ; GFX940-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v10, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v11, v7, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX940-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v3, v7 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_max_f16 v7, v2, v6 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v3, v9, v8, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v2, v6 ; GFX940-NEXT: v_perm_b32 v3, v3, v10, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v8, v9, v7, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 ; GFX940-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v8, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v11, v6, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 -; GFX940-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v2, v6 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_max_f16 v6, v1, v5 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v2, v9, v7, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v1, v5 ; GFX940-NEXT: v_perm_b32 v2, v2, v8, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v7, v9, v6, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 ; GFX940-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v7, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v11, v5, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX940-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v1, v5 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_max_f16 v5, v0, v4 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v1, v9, v6, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v4 ; GFX940-NEXT: v_perm_b32 v1, v1, v7, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v6, v9, v5, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 ; GFX940-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v6, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v11, v4, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v4 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v0, v4 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v9, v5, vcc ; GFX940-NEXT: v_perm_b32 v0, v0, v6, s0 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; @@ -3608,88 +2200,32 @@ define <8 x half> @v_maximum_v8f16(<8 x half> %src0, <8 x half> %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_max_f16 v8, v3, v7 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v3 -; GFX10-NEXT: v_pk_max_f16 v13, v1, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v8, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v11, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v8, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v11, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v8, v11, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v9 -; GFX10-NEXT: v_pk_max_f16 v11, v2, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v2 +; GFX10-NEXT: v_pk_max_f16 v9, v2, v6 +; GFX10-NEXT: v_pk_max_f16 v12, v1, v5 +; GFX10-NEXT: v_pk_max_f16 v13, v0, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v10, 0x7e00, v8, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v11, 0x7e00, v11, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v10, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v12, 0x7e00, v12, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v9 +; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v9, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v11, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v14, 0x7e00, v13, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v14, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v10, v9, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX10-NEXT: v_pk_max_f16 v10, v0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v15, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14 -; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v0 -; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v13 +; GFX10-NEXT: v_perm_b32 v2, v2, v9, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v12, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v4 -; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v10, 0x7e00, v10, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v12, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v14, 0x7e00, v14, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5 +; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v12 ; GFX10-NEXT: v_cndmask_b32_e32 v13, 0x7e00, v13, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v12, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v11, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v11, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13 -; GFX10-NEXT: v_perm_b32 v0, v4, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_perm_b32 v1, v1, v9, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v7, vcc_lo -; GFX10-NEXT: v_perm_b32 v3, v5, v3, 0x5040100 +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v4 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v11, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_perm_b32 v0, v0, v13, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v12, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_perm_b32 v1, v1, v6, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v8, vcc_lo +; GFX10-NEXT: v_perm_b32 v3, v3, v10, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_v8f16: @@ -3697,94 +2233,42 @@ define <8 x half> @v_maximum_v8f16(<8 x half> %src0, <8 x half> %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_pk_max_f16 v8, v3, v7 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7 -; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v7 -; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v3 -; GFX11-NEXT: v_pk_max_f16 v13, v1, v5 +; GFX11-NEXT: v_pk_max_f16 v10, v2, v6 +; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v6 +; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v2 +; GFX11-NEXT: v_pk_max_f16 v14, v1, v5 ; GFX11-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v8, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v11, v10 -; GFX11-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v8, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v11, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v8, v11, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v9 -; GFX11-NEXT: v_pk_max_f16 v11, v2, v6 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v6 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v11 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo -; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v2 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6 -; GFX11-NEXT: v_cndmask_b32_e32 v11, 0x7e00, v11, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v10, v9 -; GFX11-NEXT: v_cndmask_b32_e32 v12, 0x7e00, v12, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v13, 16, v10 +; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v10, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v12, v11 +; GFX11-NEXT: v_pk_max_f16 v11, v0, v4 +; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v4 +; GFX11-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v13, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v14, 0x7e00, v13, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v15, v14, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v10, v9, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX11-NEXT: v_pk_max_f16 v10, v0, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v9, v15, v5, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v11 +; GFX11-NEXT: v_lshrrev_b32_e32 v13, 16, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12 -; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14 -; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-NEXT: v_perm_b32 v2, v6, v2, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX11-NEXT: v_lshrrev_b32_e32 v15, 16, v11 +; GFX11-NEXT: v_cndmask_b32_e32 v10, 0x7e00, v14, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v4 -; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v10 -; GFX11-NEXT: v_cndmask_b32_e32 v10, 0x7e00, v10, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v12, v11 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e32 v14, 0x7e00, v14, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX11-NEXT: v_perm_b32 v2, v6, v2, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v11, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v13, v12 +; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v15, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v13, 0x7e00, v13, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v12, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v11, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v12, v11, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v10 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_perm_b32 v1, v1, v9, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v7, vcc_lo ; GFX11-NEXT: v_perm_b32 v0, v4, v0, 0x5040100 -; GFX11-NEXT: v_perm_b32 v3, v5, v3, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v14, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7 +; GFX11-NEXT: v_perm_b32 v1, v1, v10, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v8, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_perm_b32 v3, v3, v9, 0x5040100 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_v8f16: @@ -3809,381 +2293,189 @@ define <16 x half> @v_maximum_v16f16(<16 x half> %src0, <16 x half> %src1) { ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_cvt_f16_f32_e32 v16, v16 ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-NEXT: v_cvt_f16_f32_e32 v6, v6 +; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 +; GFX7-NEXT: v_cvt_f32_f16_e32 v16, v16 +; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 +; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 +; GFX7-NEXT: v_cvt_f16_f32_e32 v8, v8 +; GFX7-NEXT: v_cmp_o_f32_e64 s[12:13], v0, v16 +; GFX7-NEXT: v_max_f32_e32 v0, v0, v16 +; GFX7-NEXT: v_cvt_f16_f32_e32 v16, v22 +; GFX7-NEXT: v_cvt_f32_f16_e32 v8, v8 +; GFX7-NEXT: v_cvt_f16_f32_e32 v9, v9 +; GFX7-NEXT: v_cvt_f16_f32_e32 v10, v10 +; GFX7-NEXT: v_cvt_f32_f16_e32 v16, v16 ; GFX7-NEXT: v_cvt_f16_f32_e32 v17, v17 +; GFX7-NEXT: v_cvt_f32_f16_e32 v9, v9 +; GFX7-NEXT: v_cvt_f32_f16_e32 v10, v10 +; GFX7-NEXT: v_cmp_o_f32_e64 s[14:15], v6, v16 +; GFX7-NEXT: v_max_f32_e32 v6, v6, v16 +; GFX7-NEXT: v_cvt_f16_f32_e32 v16, v23 ; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 -; GFX7-NEXT: v_cvt_f32_f16_e32 v31, v16 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_mov_b32_e32 v16, 0x7fc00000 ; GFX7-NEXT: v_cvt_f32_f16_e32 v17, v17 -; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 -; GFX7-NEXT: v_max_f32_e32 v32, v0, v31 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v31 -; GFX7-NEXT: v_cvt_f16_f32_e32 v18, v18 ; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v32, v16, v32, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v32, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v31, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v31, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v32 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v32, v0, vcc -; GFX7-NEXT: v_max_f32_e32 v31, v1, v17 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v17 -; GFX7-NEXT: v_cvt_f32_f16_e32 v18, v18 -; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v31, v16, v31, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v31, v1, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v17, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v31 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v31, v1, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v2, v18 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v18 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v2, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v17, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v18, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc -; GFX7-NEXT: v_cvt_f16_f32_e32 v18, v20 -; GFX7-NEXT: buffer_load_dword v20, off, s[0:3], s32 -; GFX7-NEXT: v_cvt_f16_f32_e32 v19, v19 +; GFX7-NEXT: v_cvt_f32_f16_e32 v16, v16 +; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3 -; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4 -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 -; GFX7-NEXT: v_cvt_f32_f16_e32 v19, v19 +; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX7-NEXT: v_cmp_o_f32_e64 s[16:17], v7, v16 +; GFX7-NEXT: v_max_f32_e32 v7, v7, v16 +; GFX7-NEXT: v_cvt_f16_f32_e32 v16, v24 +; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v17 +; GFX7-NEXT: v_max_f32_e32 v1, v1, v17 +; GFX7-NEXT: v_cvt_f16_f32_e32 v17, v18 +; GFX7-NEXT: v_cvt_f32_f16_e32 v16, v16 ; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v17, v2, vcc -; GFX7-NEXT: v_cvt_f32_f16_e32 v18, v18 +; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4 +; GFX7-NEXT: v_cvt_f32_f16_e32 v17, v17 +; GFX7-NEXT: v_cmp_o_f32_e64 s[18:19], v8, v16 +; GFX7-NEXT: v_max_f32_e32 v8, v8, v16 +; GFX7-NEXT: v_cvt_f16_f32_e32 v16, v25 +; GFX7-NEXT: v_cmp_o_f32_e64 s[4:5], v2, v17 +; GFX7-NEXT: v_max_f32_e32 v2, v2, v17 +; GFX7-NEXT: v_cvt_f16_f32_e32 v17, v19 +; GFX7-NEXT: v_cvt_f32_f16_e32 v16, v16 ; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4 -; GFX7-NEXT: v_max_f32_e32 v17, v3, v19 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v19 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v3, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v19, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 -; GFX7-NEXT: v_cvt_f16_f32_e32 v19, v21 ; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v4, v18 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v4, v18 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v4, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v17, v4, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v18, 64 -; GFX7-NEXT: v_cvt_f32_f16_e32 v19, v19 +; GFX7-NEXT: v_cvt_f32_f16_e32 v17, v17 +; GFX7-NEXT: v_cmp_o_f32_e64 s[20:21], v9, v16 +; GFX7-NEXT: v_max_f32_e32 v9, v9, v16 +; GFX7-NEXT: v_cvt_f16_f32_e32 v16, v26 +; GFX7-NEXT: v_cmp_o_f32_e64 s[6:7], v3, v17 +; GFX7-NEXT: v_max_f32_e32 v3, v3, v17 +; GFX7-NEXT: v_cvt_f16_f32_e32 v17, v20 +; GFX7-NEXT: v_cvt_f32_f16_e32 v16, v16 ; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v18, vcc -; GFX7-NEXT: v_cvt_f16_f32_e32 v18, v22 -; GFX7-NEXT: v_cvt_f16_f32_e32 v6, v6 -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 -; GFX7-NEXT: v_cndmask_b32_e32 v4, v17, v4, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v5, v19 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v5, v19 -; GFX7-NEXT: v_cvt_f32_f16_e32 v18, v18 -; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v5, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v19, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v19, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 -; GFX7-NEXT: v_cvt_f16_f32_e32 v19, v23 -; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v6, v18 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v6, v18 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v6, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v17, v6, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v18, 64 -; GFX7-NEXT: v_cvt_f32_f16_e32 v19, v19 -; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v6, v18, vcc -; GFX7-NEXT: v_cvt_f16_f32_e32 v18, v24 -; GFX7-NEXT: v_cvt_f16_f32_e32 v8, v8 -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 -; GFX7-NEXT: v_cndmask_b32_e32 v6, v17, v6, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v7, v19 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v7, v19 -; GFX7-NEXT: v_cvt_f32_f16_e32 v18, v18 -; GFX7-NEXT: v_cvt_f32_f16_e32 v8, v8 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v7, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v19, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v7, v7, v19, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 -; GFX7-NEXT: v_cvt_f16_f32_e32 v19, v25 -; GFX7-NEXT: v_cvt_f16_f32_e32 v9, v9 -; GFX7-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v8, v18 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v8, v18 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v8, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v18, 64 -; GFX7-NEXT: v_cvt_f32_f16_e32 v19, v19 -; GFX7-NEXT: v_cvt_f32_f16_e32 v9, v9 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v8, v18, vcc -; GFX7-NEXT: v_cvt_f16_f32_e32 v18, v26 -; GFX7-NEXT: v_cvt_f16_f32_e32 v10, v10 -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 -; GFX7-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v9, v19 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v9, v19 -; GFX7-NEXT: v_cvt_f32_f16_e32 v18, v18 -; GFX7-NEXT: v_cvt_f32_f16_e32 v10, v10 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v9, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v19, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v9, v9, v19, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 -; GFX7-NEXT: v_cvt_f16_f32_e32 v19, v27 ; GFX7-NEXT: v_cvt_f16_f32_e32 v11, v11 -; GFX7-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v10, v18 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v10, v18 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v10, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v18, 64 -; GFX7-NEXT: v_cvt_f32_f16_e32 v19, v19 -; GFX7-NEXT: v_cvt_f32_f16_e32 v11, v11 -; GFX7-NEXT: v_cndmask_b32_e32 v10, v10, v18, vcc -; GFX7-NEXT: v_cvt_f16_f32_e32 v18, v28 +; GFX7-NEXT: v_cvt_f32_f16_e32 v17, v17 +; GFX7-NEXT: v_cmp_o_f32_e64 s[22:23], v10, v16 +; GFX7-NEXT: v_max_f32_e32 v10, v10, v16 +; GFX7-NEXT: buffer_load_dword v16, off, s[0:3], s32 +; GFX7-NEXT: v_cmp_o_f32_e64 s[8:9], v4, v17 +; GFX7-NEXT: v_max_f32_e32 v4, v4, v17 +; GFX7-NEXT: v_cvt_f16_f32_e32 v17, v21 +; GFX7-NEXT: v_cvt_f16_f32_e32 v20, v28 ; GFX7-NEXT: v_cvt_f16_f32_e32 v12, v12 -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 -; GFX7-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v11, v19 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v11, v19 -; GFX7-NEXT: v_cvt_f32_f16_e32 v18, v18 -; GFX7-NEXT: v_cvt_f32_f16_e32 v12, v12 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v11, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v19, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v11, v11, v19, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 -; GFX7-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v12, v18 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v12, v18 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v12, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v18, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v12, v12, v18, vcc -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_cvt_f16_f32_e32 v18, v20 -; GFX7-NEXT: v_cvt_f16_f32_e32 v20, v29 +; GFX7-NEXT: v_cvt_f16_f32_e32 v19, v29 +; GFX7-NEXT: v_cvt_f32_f16_e32 v17, v17 ; GFX7-NEXT: v_cvt_f16_f32_e32 v13, v13 -; GFX7-NEXT: v_cvt_f16_f32_e32 v19, v30 +; GFX7-NEXT: v_cvt_f16_f32_e32 v18, v30 ; GFX7-NEXT: v_cvt_f16_f32_e32 v14, v14 -; GFX7-NEXT: v_cvt_f32_f16_e32 v20, v20 -; GFX7-NEXT: v_cvt_f32_f16_e32 v13, v13 -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 +; GFX7-NEXT: v_cmp_o_f32_e64 s[10:11], v5, v17 +; GFX7-NEXT: v_max_f32_e32 v5, v5, v17 +; GFX7-NEXT: v_cvt_f16_f32_e32 v17, v27 +; GFX7-NEXT: v_cvt_f32_f16_e32 v11, v11 ; GFX7-NEXT: v_cvt_f16_f32_e32 v15, v15 +; GFX7-NEXT: v_cvt_f32_f16_e32 v20, v20 +; GFX7-NEXT: v_cvt_f32_f16_e32 v17, v17 +; GFX7-NEXT: v_cvt_f32_f16_e32 v12, v12 ; GFX7-NEXT: v_cvt_f32_f16_e32 v19, v19 -; GFX7-NEXT: v_cvt_f32_f16_e32 v14, v14 -; GFX7-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v13, v20 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v13, v20 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v13, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v20, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v13, v13, v20, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 +; GFX7-NEXT: v_cvt_f32_f16_e32 v13, v13 ; GFX7-NEXT: v_cvt_f32_f16_e32 v18, v18 +; GFX7-NEXT: v_cvt_f32_f16_e32 v14, v14 +; GFX7-NEXT: v_cmp_o_f32_e64 s[24:25], v11, v17 +; GFX7-NEXT: v_max_f32_e32 v11, v11, v17 +; GFX7-NEXT: v_mov_b32_e32 v17, 0x7fc00000 ; GFX7-NEXT: v_cvt_f32_f16_e32 v15, v15 -; GFX7-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v14, v19 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v14, v19 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v14, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v14, v17, v14, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v19, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v14, v14, v19, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v17 -; GFX7-NEXT: v_cndmask_b32_e32 v14, v17, v14, vcc -; GFX7-NEXT: v_max_f32_e32 v17, v15, v18 -; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v15, v18 -; GFX7-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v15, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v18, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v16 -; GFX7-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc +; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v12, v20 +; GFX7-NEXT: v_max_f32_e32 v12, v12, v20 +; GFX7-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc +; GFX7-NEXT: v_max_f32_e32 v20, v13, v19 +; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v13, v19 +; GFX7-NEXT: v_cndmask_b32_e32 v13, v17, v20, vcc +; GFX7-NEXT: v_max_f32_e32 v19, v14, v18 +; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v14, v18 +; GFX7-NEXT: v_cndmask_b32_e32 v14, v17, v19, vcc +; GFX7-NEXT: v_cndmask_b32_e64 v0, v17, v0, s[12:13] +; GFX7-NEXT: v_cndmask_b32_e64 v2, v17, v2, s[4:5] +; GFX7-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[6:7] +; GFX7-NEXT: v_cndmask_b32_e64 v4, v17, v4, s[8:9] +; GFX7-NEXT: v_cndmask_b32_e64 v5, v17, v5, s[10:11] +; GFX7-NEXT: v_cndmask_b32_e64 v6, v17, v6, s[14:15] +; GFX7-NEXT: v_cndmask_b32_e64 v7, v17, v7, s[16:17] +; GFX7-NEXT: v_cndmask_b32_e64 v8, v17, v8, s[18:19] +; GFX7-NEXT: v_cndmask_b32_e64 v9, v17, v9, s[20:21] +; GFX7-NEXT: v_cndmask_b32_e64 v10, v17, v10, s[22:23] +; GFX7-NEXT: v_cndmask_b32_e64 v11, v17, v11, s[24:25] +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_cvt_f16_f32_e32 v16, v16 +; GFX7-NEXT: v_cvt_f32_f16_e32 v16, v16 +; GFX7-NEXT: v_max_f32_e32 v18, v15, v16 +; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v15, v16 +; GFX7-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_v16f16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v15 -; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v7 -; GFX8-NEXT: v_max_f16_e32 v19, v18, v16 -; GFX8-NEXT: v_mov_b32_e32 v17, 0x7e00 -; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v18, v16 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v17, v19, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v18, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v16, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v16, v19, v16, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v14 -; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v6 -; GFX8-NEXT: v_max_f16_e32 v20, v19, v18 -; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v19, v18 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v19, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v18, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v20 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v13 +; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v7 +; GFX8-NEXT: v_max_f16_e32 v18, v17, v16 +; GFX8-NEXT: v_mov_b32_e32 v19, 0x7e00 +; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v17, v16 +; GFX8-NEXT: v_cndmask_b32_e32 v16, v19, v18, vcc +; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v14 +; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v6 +; GFX8-NEXT: v_max_f16_e32 v20, v18, v17 +; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v18, v17 +; GFX8-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc +; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v13 ; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v5 -; GFX8-NEXT: v_max_f16_e32 v21, v20, v19 -; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v20, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v17, v21, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v20, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v19, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v21 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc +; GFX8-NEXT: v_max_f16_e32 v21, v20, v18 +; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v20, v18 +; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v21, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v12 ; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v4 ; GFX8-NEXT: v_max_f16_e32 v22, v21, v20 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v21, v20 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v17, v22, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v21, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v20, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v22 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v20, v19, v22, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v11 ; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v3 ; GFX8-NEXT: v_max_f16_e32 v23, v22, v21 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v22, v21 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v17, v23, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v22, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v21, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v21, v19, v23, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v10 ; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v2 ; GFX8-NEXT: v_max_f16_e32 v24, v23, v22 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v23, v22 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v17, v24, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v23, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v22, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v22, v19, v24, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v9 ; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v1 ; GFX8-NEXT: v_max_f16_e32 v25, v24, v23 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v24, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v25, v17, v25, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v24, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v23, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v25 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v23, v19, v25, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v8 ; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v0 ; GFX8-NEXT: v_max_f16_e32 v26, v25, v24 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v25, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v26, v17, v26, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v25, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v25, v26, v25, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v24, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v26 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v26, v24, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v24, v19, v26, vcc ; GFX8-NEXT: v_max_f16_e32 v25, v7, v15 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v7, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v25, v17, v25, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v15, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v25 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v19, v25, vcc ; GFX8-NEXT: v_max_f16_e32 v15, v6, v14 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v6, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v15, v17, v15, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v14, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v19, v15, vcc ; GFX8-NEXT: v_max_f16_e32 v14, v5, v13 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v5, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v14, v17, v14, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v13, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v19, v14, vcc ; GFX8-NEXT: v_max_f16_e32 v13, v4, v12 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v4, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v12, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v19, v13, vcc ; GFX8-NEXT: v_max_f16_e32 v12, v3, v11 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v3, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v11, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v12, vcc ; GFX8-NEXT: v_max_f16_e32 v11, v2, v10 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v2, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v10, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v19, v11, vcc ; GFX8-NEXT: v_max_f16_e32 v10, v1, v9 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v9, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v19, v10, vcc ; GFX8-NEXT: v_max_f16_e32 v9, v0, v8 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v8, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v19, v9, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v24 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v23 @@ -4194,9 +2486,9 @@ define <16 x half> @v_maximum_v16f16(<16 x half> %src0, <16 x half> %src1) { ; GFX8-NEXT: v_or_b32_sdwa v3, v3, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v20 ; GFX8-NEXT: v_or_b32_sdwa v4, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v19 -; GFX8-NEXT: v_or_b32_sdwa v5, v5, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v18 +; GFX8-NEXT: v_or_b32_sdwa v5, v5, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v17 ; GFX8-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v16 ; GFX8-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD @@ -4205,414 +2497,142 @@ define <16 x half> @v_maximum_v16f16(<16 x half> %src0, <16 x half> %src1) { ; GFX9-LABEL: v_maximum_v16f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_pk_max_f16 v18, v7, v15 +; GFX9-NEXT: v_pk_max_f16 v16, v7, v15 ; GFX9-NEXT: v_mov_b32_e32 v17, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v7, v15 -; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v16, v7, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v15, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v15, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v16 -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX9-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v7, v15 -; GFX9-NEXT: v_cndmask_b32_e32 v18, v17, v18, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v18, v7, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v15, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v18, v7, vcc -; GFX9-NEXT: v_pk_max_f16 v18, v6, v14 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v6, v14 -; GFX9-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v15, v6, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v14, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v14, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v15 -; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v15, v15, v19, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX9-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc +; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v7, v15 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v7, v17, v16, vcc +; GFX9-NEXT: v_pk_max_f16 v15, v6, v14 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v6, v14 -; GFX9-NEXT: v_cndmask_b32_e32 v18, v17, v18, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v14, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc -; GFX9-NEXT: v_pk_max_f16 v18, v5, v13 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v5, v13 -; GFX9-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v14, v5, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v13, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v13, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v14 -; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v19, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v15, vcc +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v6, v14 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v6, v17, v15, vcc +; GFX9-NEXT: v_pk_max_f16 v14, v5, v13 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v5, v13 -; GFX9-NEXT: v_cndmask_b32_e32 v18, v17, v18, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v18, v5, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v13, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v18, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v15, v17, v14, vcc +; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v5, v13 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v5, v17, v14, vcc ; GFX9-NEXT: v_pk_max_f16 v13, v4, v12 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v4, v12 -; GFX9-NEXT: v_cndmask_b32_e32 v18, v17, v13, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v18, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v12, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v12, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v14, v17, v13, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v4, v12 -; GFX9-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v12, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v4, v12 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v17, v13, vcc ; GFX9-NEXT: v_pk_max_f16 v12, v3, v11 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v11 ; GFX9-NEXT: v_cndmask_b32_e32 v13, v17, v12, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v13, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v11, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v11, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 -; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v13, v13, v19, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v11 -; GFX9-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v11, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v12 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v3, v11 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v12, vcc ; GFX9-NEXT: v_pk_max_f16 v11, v2, v10 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v2, v10 ; GFX9-NEXT: v_cndmask_b32_e32 v12, v17, v11, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v12, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v10, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v10, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v12 -; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v19, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v2, v10 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v10, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v11 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v2, v10 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v11, vcc ; GFX9-NEXT: v_pk_max_f16 v10, v1, v9 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v9 ; GFX9-NEXT: v_cndmask_b32_e32 v11, v17, v10, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v11, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v9, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v9, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v11 -; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v19, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v9 -; GFX9-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v9, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v9 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v10, vcc ; GFX9-NEXT: v_pk_max_f16 v9, v0, v8 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v8 ; GFX9-NEXT: v_cndmask_b32_e32 v10, v17, v9, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v10, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v8, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v8, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v19, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v8 -; GFX9-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v8, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v9 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v8 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v9, vcc ; GFX9-NEXT: s_mov_b32 s4, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v0, v10, s4 ; GFX9-NEXT: v_perm_b32 v1, v1, v11, s4 ; GFX9-NEXT: v_perm_b32 v2, v2, v12, s4 ; GFX9-NEXT: v_perm_b32 v3, v3, v13, s4 -; GFX9-NEXT: v_perm_b32 v4, v4, v18, s4 -; GFX9-NEXT: v_perm_b32 v5, v5, v14, s4 -; GFX9-NEXT: v_perm_b32 v6, v6, v15, s4 -; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4 +; GFX9-NEXT: v_perm_b32 v4, v4, v14, s4 +; GFX9-NEXT: v_perm_b32 v5, v5, v15, s4 +; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4 +; GFX9-NEXT: v_perm_b32 v7, v7, v18, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_v16f16: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_pk_max_f16 v18, v7, v15 +; GFX940-NEXT: v_pk_max_f16 v16, v7, v15 ; GFX940-NEXT: v_mov_b32_e32 v17, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v7, v15 ; GFX940-NEXT: s_mov_b32 s0, 0x5040100 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v16, v7, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v15, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GFX940-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc +; GFX940-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v7, v15 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX940-NEXT: v_pk_max_f16 v15, v6, v14 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v15, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v16 -; GFX940-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v7, v15 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v18, v17, v18, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v7, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v18, v7, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v15, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v18, v7, vcc -; GFX940-NEXT: v_pk_max_f16 v18, v6, v14 +; GFX940-NEXT: v_cndmask_b32_e32 v7, v17, v16, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v6, v14 -; GFX940-NEXT: v_perm_b32 v7, v7, v16, s0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX940-NEXT: v_perm_b32 v7, v7, v18, s0 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v15, v6, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v14, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v14, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v15 -; GFX940-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX940-NEXT: v_cndmask_b32_e32 v16, v17, v15, vcc +; GFX940-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v6, v14 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX940-NEXT: v_pk_max_f16 v14, v5, v13 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v15, v15, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v6, v14 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v18, v17, v18, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v6, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v14, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc -; GFX940-NEXT: v_pk_max_f16 v18, v5, v13 +; GFX940-NEXT: v_cndmask_b32_e32 v6, v17, v15, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v5, v13 -; GFX940-NEXT: v_perm_b32 v6, v6, v15, s0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v14, v5, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v13, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v13, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v14 -; GFX940-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GFX940-NEXT: v_perm_b32 v6, v6, v16, s0 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v14, v14, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v5, v13 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v18, v17, v18, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v5, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v18, v5, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v13, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 +; GFX940-NEXT: v_cndmask_b32_e32 v15, v17, v14, vcc +; GFX940-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v5, v13 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_max_f16 v13, v4, v12 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v18, v5, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v5, v17, v14, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v4, v12 -; GFX940-NEXT: v_perm_b32 v5, v5, v14, s0 +; GFX940-NEXT: v_perm_b32 v5, v5, v15, s0 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v18, v17, v13, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 +; GFX940-NEXT: v_cndmask_b32_e32 v14, v17, v13, vcc ; GFX940-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v18, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v12, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v12, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX940-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v4, v12 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v4, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v12, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v4, v12 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_max_f16 v12, v3, v11 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v4, v17, v13, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v3, v11 -; GFX940-NEXT: v_perm_b32 v4, v4, v18, s0 +; GFX940-NEXT: v_perm_b32 v4, v4, v14, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v13, v17, v12, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 ; GFX940-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v13, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v11, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v11, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 -; GFX940-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v13, v13, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v3, v11 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v11, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v12 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v3, v11 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_max_f16 v11, v2, v10 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v3, v17, v12, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v2, v10 ; GFX940-NEXT: v_perm_b32 v3, v3, v13, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v12, v17, v11, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 ; GFX940-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v12, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v10, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v10, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v12 -; GFX940-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v12, v12, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v2, v10 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v10, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v11 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v2, v10 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_max_f16 v10, v1, v9 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v2, v17, v11, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v1, v9 ; GFX940-NEXT: v_perm_b32 v2, v2, v12, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v11, v17, v10, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 ; GFX940-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v11, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v9, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v9, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v11 -; GFX940-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v11, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v1, v9 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v9, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v1, v9 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_max_f16 v9, v0, v8 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v1, v17, v10, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v8 ; GFX940-NEXT: v_perm_b32 v1, v1, v11, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v10, v17, v9, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 ; GFX940-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v10, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v8, 64 -; GFX940-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v8, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX940-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v10, v10, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v8 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v8, 64 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v0, v8 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v9 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v17, v9, vcc ; GFX940-NEXT: v_perm_b32 v0, v0, v10, s0 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; @@ -4621,353 +2641,145 @@ define <16 x half> @v_maximum_v16f16(<16 x half> %src0, <16 x half> %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_max_f16 v16, v7, v15 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v7, v15 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v14 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v17, 0x7e00, v16, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v17, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v15, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v15, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v7, v15 ; GFX10-NEXT: v_pk_max_f16 v18, v6, v14 +; GFX10-NEXT: v_pk_max_f16 v19, v3, v11 +; GFX10-NEXT: v_pk_max_f16 v20, v2, v10 +; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v16 ; GFX10-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v16, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v7, v15 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v18 +; GFX10-NEXT: v_pk_max_f16 v21, v0, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v7, 0x7e00, v17, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v14 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v18 +; GFX10-NEXT: v_pk_max_f16 v17, v5, v13 +; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v21 +; GFX10-NEXT: v_perm_b32 v7, v7, v16, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v18, 0x7e00, v18, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v20, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v21, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v15, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v20, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v21, v20, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v14, 64 -; GFX10-NEXT: v_pk_max_f16 v20, v4, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v19, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v13 -; GFX10-NEXT: v_perm_b32 v7, v7, v17, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v15, v19, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v18 -; GFX10-NEXT: v_pk_max_f16 v15, v5, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v21, v14, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v6, v14 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v17 +; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v15, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v5, v13 -; GFX10-NEXT: v_perm_b32 v6, v14, v6, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v15, 0x7e00, v15, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v18, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v19, 0x7e00, v19, vcc_lo +; GFX10-NEXT: v_perm_b32 v6, v6, v18, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v15, 0x7e00, v17, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v5, v13 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_pk_max_f16 v17, v4, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v14, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v20, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v18, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v21, v4, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v13, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v16, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v18, v16, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v12, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v22, v12, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v15 -; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v19, v13, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v11 -; GFX10-NEXT: v_perm_b32 v5, v13, v5, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v21, v16, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v12 -; GFX10-NEXT: v_pk_max_f16 v16, v3, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v18, 0x7e00, v18, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v17 +; GFX10-NEXT: v_perm_b32 v5, v5, v15, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v13, 0x7e00, v17, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v11 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v16, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v20, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v21, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v18, v4, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v20, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v12, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v11, 64 -; GFX10-NEXT: v_pk_max_f16 v12, v2, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v19, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v20, v19, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v16 -; GFX10-NEXT: v_pk_max_f16 v19, v1, v9 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v21, v11, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v19 +; GFX10-NEXT: v_cndmask_b32_e32 v19, 0x7e00, v19, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v3, v11 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_pk_max_f16 v11, v1, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v17, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v10 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v2 -; GFX10-NEXT: v_perm_b32 v3, v11, v3, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v12, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v9 -; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v22, 0x7e00, v19, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v21, v20 -; GFX10-NEXT: v_cndmask_b32_e32 v12, 0x7e00, v12, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v22, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 64 -; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v21, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v12, v21, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v23, v9, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v16 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v20, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v20, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v22 -; GFX10-NEXT: v_pk_max_f16 v20, v0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v22, v21, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v11 +; GFX10-NEXT: v_perm_b32 v3, v3, v19, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v17, 0x7e00, v20, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v9 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v20 -; GFX10-NEXT: v_cndmask_b32_e32 v19, 0x7e00, v19, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v11, 0x7e00, v11, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v1, v9 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v22, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v20, 0x7e00, v20, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v22, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v23, 0x7e00, v23, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v20, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v22, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v8, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v21, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v22, v21, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v20 -; GFX10-NEXT: v_perm_b32 v1, v1, v16, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v20, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v23, v8, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12 -; GFX10-NEXT: v_perm_b32 v0, v8, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v12, v10, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v18 -; GFX10-NEXT: v_perm_b32 v2, v9, v2, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v18, v4, vcc_lo -; GFX10-NEXT: v_perm_b32 v4, v4, v15, 0x5040100 +; GFX10-NEXT: v_perm_b32 v1, v1, v11, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v21, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v8 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v23, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v2, v10 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_perm_b32 v0, v0, v9, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v20, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v4, v12 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_perm_b32 v2, v2, v17, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v14, vcc_lo +; GFX10-NEXT: v_perm_b32 v4, v4, v13, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_v16f16: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_pk_max_f16 v16, v7, v15 +; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v15 +; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v7 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v7, v15 -; GFX11-NEXT: v_lshrrev_b32_e32 v20, 16, v6 -; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v14 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e32 v17, 0x7e00, v16, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GFX11-NEXT: v_cndmask_b32_e32 v18, v17, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v15, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e32 v18, v18, v15, vcc_lo -; GFX11-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v17 -; GFX11-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v7, v15 -; GFX11-NEXT: v_pk_max_f16 v18, v6, v14 -; GFX11-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v16, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v14 -; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v18 -; GFX11-NEXT: v_cndmask_b32_e32 v18, 0x7e00, v18, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v20, v19 -; GFX11-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v21, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v15, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v20, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v15, v21, v20, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v14, 64 +; GFX11-NEXT: v_pk_max_f16 v15, v6, v14 +; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v16 ; GFX11-NEXT: v_pk_max_f16 v20, v4, v12 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v16 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v19, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v13 -; GFX11-NEXT: v_cndmask_b32_e32 v14, v15, v19, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v18 -; GFX11-NEXT: v_pk_max_f16 v15, v5, v13 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v21 -; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_pk_max_f16 v22, v2, v10 +; GFX11-NEXT: v_cndmask_b32_e32 v7, 0x7e00, v16, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v18, v17 +; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v14 +; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v6 +; GFX11-NEXT: v_lshrrev_b32_e32 v23, 16, v8 +; GFX11-NEXT: v_lshrrev_b32_e32 v24, 16, v0 +; GFX11-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v19, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v14 ; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v15 -; GFX11-NEXT: v_perm_b32 v7, v7, v17, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v14, v21, v14, vcc_lo +; GFX11-NEXT: v_pk_max_f16 v14, v5, v13 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_perm_b32 v7, v16, v7, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v15, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v18, v17 +; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v13 +; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v5 +; GFX11-NEXT: v_cndmask_b32_e32 v15, 0x7e00, v19, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v5, v13 -; GFX11-NEXT: v_cndmask_b32_e32 v15, 0x7e00, v15, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v18, v16 -; GFX11-NEXT: v_cndmask_b32_e32 v19, 0x7e00, v19, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v14 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: v_perm_b32 v6, v15, v6, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v14, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v18, v17 +; GFX11-NEXT: v_pk_max_f16 v17, v3, v11 +; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v20 +; GFX11-NEXT: v_cndmask_b32_e32 v13, 0x7e00, v19, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v12 -; GFX11-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v20, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v18, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v22, v21, v4, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v13, 64 +; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v11 +; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v17 +; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v12 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v16, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v13, v18, v16, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v12, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v20 +; GFX11-NEXT: v_cndmask_b32_e32 v14, 0x7e00, v20, vcc_lo ; GFX11-NEXT: v_lshrrev_b32_e32 v20, 16, v3 -; GFX11-NEXT: v_perm_b32 v6, v14, v6, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v16, v22, v12, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v15 -; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v19 -; GFX11-NEXT: v_cndmask_b32_e32 v13, v19, v13, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v21 -; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v11 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-NEXT: v_perm_b32 v5, v13, v5, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v15, v21, v16, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v12 -; GFX11-NEXT: v_pk_max_f16 v16, v3, v11 -; GFX11-NEXT: v_cndmask_b32_e32 v18, 0x7e00, v18, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v11 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v16 -; GFX11-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v16, vcc_lo +; GFX11-NEXT: v_perm_b32 v5, v13, v5, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v17, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v20, v19 -; GFX11-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v21, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v18, v4, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v20, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v12, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v11, 64 -; GFX11-NEXT: v_pk_max_f16 v12, v2, v10 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v19, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v11, v20, v19, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v16 -; GFX11-NEXT: v_lshrrev_b32_e32 v20, 16, v10 ; GFX11-NEXT: v_pk_max_f16 v19, v1, v9 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v21 -; GFX11-NEXT: v_cndmask_b32_e32 v11, v21, v11, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v20, 16, v22 +; GFX11-NEXT: v_cndmask_b32_e32 v11, 0x7e00, v21, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v10 -; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v12, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_perm_b32 v3, v11, v3, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v17, 0x7e00, v22, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v9 -; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX11-NEXT: v_cndmask_b32_e32 v22, 0x7e00, v19, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v21, v20 -; GFX11-NEXT: v_cndmask_b32_e32 v12, 0x7e00, v12, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v23, v22, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 64 -; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v21, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v10, v12, v21, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v21, v23, v9, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v16 ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v20, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v20, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v22 -; GFX11-NEXT: v_pk_max_f16 v20, v0, v8 -; GFX11-NEXT: v_perm_b32 v3, v11, v3, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v16, v22, v21, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX11-NEXT: v_pk_max_f16 v22, v0, v8 +; GFX11-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v19, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v9 -; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v8 -; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v0 -; GFX11-NEXT: v_lshrrev_b32_e32 v23, 16, v20 -; GFX11-NEXT: v_cndmask_b32_e32 v19, 0x7e00, v19, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v25, 16, v22 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v19, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v8 -; GFX11-NEXT: v_cndmask_b32_e32 v20, 0x7e00, v20, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v22, v21 -; GFX11-NEXT: v_cndmask_b32_e32 v23, 0x7e00, v23, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v20, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v22, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v8, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v21, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v8, v22, v21, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v19 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v20 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v20, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v23 -; GFX11-NEXT: v_cndmask_b32_e32 v8, v23, v8, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_perm_b32 v1, v1, v21, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v22, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v24, v23 +; GFX11-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v25, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v10 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_perm_b32 v0, v8, v0, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v9, v12, v10, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v18 -; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x5040100 -; GFX11-NEXT: v_perm_b32 v2, v9, v2, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v18, v4, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v20, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v12 +; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v18, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_perm_b32 v4, v4, v15, 0x5040100 +; GFX11-NEXT: v_perm_b32 v4, v4, v14, 0x5040100 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_v16f16: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll index 920c57c90b71..7c5bc7da4df2 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll @@ -14,13 +14,7 @@ define float @v_maximum_f32(float %src0, float %src1) { ; GFX7-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX7-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_f32: @@ -29,13 +23,7 @@ define float @v_maximum_f32(float %src0, float %src1) { ; GFX8-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_f32: @@ -44,13 +32,7 @@ define float @v_maximum_f32(float %src0, float %src1) { ; GFX9-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_f32: @@ -60,16 +42,7 @@ define float @v_maximum_f32(float %src0, float %src1) { ; GFX940-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX940-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_f32: @@ -77,13 +50,7 @@ define float @v_maximum_f32(float %src0, float %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_f32: @@ -91,15 +58,8 @@ define float @v_maximum_f32(float %src0, float %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_f32: @@ -119,78 +79,37 @@ define float @v_maximum_f32__nnan(float %src0, float %src1) { ; GFX7-LABEL: v_maximum_f32__nnan: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_max_f32_e32 v2, v0, v1 -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_max_f32_e32 v0, v0, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_f32__nnan: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_max_f32_e32 v2, v0, v1 -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_max_f32_e32 v0, v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_f32__nnan: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_max_f32_e32 v2, v0, v1 -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_max_f32_e32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_f32__nnan: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_max_f32_e32 v2, v0, v1 -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_max_f32_e32 v0, v0, v1 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_f32__nnan: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_max_f32_e32 v2, v0, v1 -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_max_f32_e32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_f32__nnan: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f32_e32 v2, v0, v1 -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: v_max_f32_e32 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_f32__nnan: @@ -332,13 +251,7 @@ define float @v_maximum_f32__nnan_src0(float %arg0, float %src1) { ; GFX7-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX7-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_f32__nnan_src0: @@ -348,13 +261,7 @@ define float @v_maximum_f32__nnan_src0(float %arg0, float %src1) { ; GFX8-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_f32__nnan_src0: @@ -364,13 +271,7 @@ define float @v_maximum_f32__nnan_src0(float %arg0, float %src1) { ; GFX9-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_f32__nnan_src0: @@ -381,16 +282,7 @@ define float @v_maximum_f32__nnan_src0(float %arg0, float %src1) { ; GFX940-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX940-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_f32__nnan_src0: @@ -399,13 +291,7 @@ define float @v_maximum_f32__nnan_src0(float %arg0, float %src1) { ; GFX10-NEXT: v_add_f32_e32 v0, 1.0, v0 ; GFX10-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_f32__nnan_src0: @@ -415,15 +301,7 @@ define float @v_maximum_f32__nnan_src0(float %arg0, float %src1) { ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_f32__nnan_src0: @@ -450,13 +328,7 @@ define float @v_maximum_f32__nnan_src1(float %src0, float %arg1) { ; GFX7-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX7-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_f32__nnan_src1: @@ -466,13 +338,7 @@ define float @v_maximum_f32__nnan_src1(float %src0, float %arg1) { ; GFX8-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_f32__nnan_src1: @@ -482,13 +348,7 @@ define float @v_maximum_f32__nnan_src1(float %src0, float %arg1) { ; GFX9-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_f32__nnan_src1: @@ -499,16 +359,7 @@ define float @v_maximum_f32__nnan_src1(float %src0, float %arg1) { ; GFX940-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX940-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_f32__nnan_src1: @@ -517,13 +368,7 @@ define float @v_maximum_f32__nnan_src1(float %src0, float %arg1) { ; GFX10-NEXT: v_add_f32_e32 v1, 1.0, v1 ; GFX10-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 64 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_f32__nnan_src1: @@ -533,15 +378,7 @@ define float @v_maximum_f32__nnan_src1(float %src0, float %arg1) { ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 64 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_f32__nnan_src1: @@ -568,14 +405,7 @@ define void @s_maximum_f32(float inreg %src0, float inreg %src1) { ; GFX7-NEXT: v_max_f32_e32 v1, s4, v0 ; GFX7-NEXT: v_mov_b32_e32 v2, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, s4, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX7-NEXT: v_mov_b32_e32 v2, s4 -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, s4, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, s5, 64 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX7-NEXT: ;;#ASMSTART ; GFX7-NEXT: ; use v0 ; GFX7-NEXT: ;;#ASMEND @@ -588,14 +418,7 @@ define void @s_maximum_f32(float inreg %src0, float inreg %src1) { ; GFX8-NEXT: v_max_f32_e32 v1, s4, v0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000 ; GFX8-NEXT: v_cmp_o_f32_e32 vcc, s4, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX8-NEXT: v_mov_b32_e32 v2, s4 -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, s4, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, s5, 64 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use v0 ; GFX8-NEXT: ;;#ASMEND @@ -608,14 +431,7 @@ define void @s_maximum_f32(float inreg %src0, float inreg %src1) { ; GFX9-NEXT: v_max_f32_e32 v1, s4, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000 ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s4, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX9-NEXT: v_mov_b32_e32 v2, s4 -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, s4, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, s5, 64 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; use v0 ; GFX9-NEXT: ;;#ASMEND @@ -629,17 +445,7 @@ define void @s_maximum_f32(float inreg %src0, float inreg %src1) { ; GFX940-NEXT: v_mov_b32_e32 v2, 0x7fc00000 ; GFX940-NEXT: v_cmp_o_f32_e32 vcc, s0, v0 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX940-NEXT: v_mov_b32_e32 v2, s0 -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, s0, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, s1, 64 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX940-NEXT: ;;#ASMSTART ; GFX940-NEXT: ; use v0 ; GFX940-NEXT: ;;#ASMEND @@ -650,13 +456,7 @@ define void @s_maximum_f32(float inreg %src0, float inreg %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_max_f32_e64 v0, s4, s5 ; GFX10-NEXT: v_cmp_o_f32_e64 vcc_lo, s4, s5 -; GFX10-NEXT: v_cmp_class_f32_e64 s6, s4, 64 ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v1, v0, s4, s6 -; GFX10-NEXT: v_cmp_class_f32_e64 s4, s5, 64 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s5, s4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use v0 ; GFX10-NEXT: ;;#ASMEND @@ -667,15 +467,8 @@ define void @s_maximum_f32(float inreg %src0, float inreg %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_max_f32_e64 v0, s0, s1 ; GFX11-NEXT: v_cmp_o_f32_e64 vcc_lo, s0, s1 -; GFX11-NEXT: v_cmp_class_f32_e64 s2, s0, 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v0, s0, s2 -; GFX11-NEXT: v_cmp_class_f32_e64 s0, s1, 64 -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s1, s0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use v0 ; GFX11-NEXT: ;;#ASMEND diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll index e6b62b18bc37..d60a28e74043 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll @@ -13,18 +13,9 @@ define double @v_maximum_f64(double %src0, double %src1) { ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000 -; GFX7-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 64 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX7-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX7-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_f64: @@ -32,18 +23,9 @@ define double @v_maximum_f64(double %src0, double %src1) { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000 -; GFX8-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 64 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX8-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX8-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_f64: @@ -51,39 +33,20 @@ define double @v_maximum_f64(double %src0, double %src1) { ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000 -; GFX9-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 64 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX9-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX9-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_f64: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX940-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] -; GFX940-NEXT: v_mov_b32_e32 v6, 0x7ff80000 ; GFX940-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX940-NEXT: v_cmp_class_f64_e64 s[0:1], v[2:3], 64 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX940-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX940-NEXT: v_cmp_eq_f64_e64 s[2:3], 0, v[4:5] +; GFX940-NEXT: v_mov_b32_e32 v1, 0x7ff80000 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[2:3] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[2:3] ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_f64: @@ -91,17 +54,8 @@ define double @v_maximum_f64(double %src0, double %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3] -; GFX10-NEXT: v_cmp_class_f64_e64 s4, v[2:3], 64 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo -; GFX10-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 64 -; GFX10-NEXT: v_cmp_eq_f64_e64 s5, 0, v[4:5] -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_f64: @@ -109,20 +63,9 @@ define double @v_maximum_f64(double %src0, double %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3] -; GFX11-NEXT: v_cmp_class_f64_e64 s0, v[2:3], 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo -; GFX11-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cmp_eq_f64_e64 s1, 0, v[4:5] -; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v0, s1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, v1, s1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_f64: @@ -142,93 +85,37 @@ define double @v_maximum_f64__nnan(double %src0, double %src1) { ; GFX7-LABEL: v_maximum_f64__nnan: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] -; GFX7-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX7-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 64 -; GFX7-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] +; GFX7-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_f64__nnan: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] -; GFX8-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX8-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 64 -; GFX8-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] +; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_f64__nnan: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] -; GFX9-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX9-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 64 -; GFX9-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] +; GFX9-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_f64__nnan: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] -; GFX940-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX940-NEXT: v_cmp_class_f64_e64 s[0:1], v[2:3], 64 -; GFX940-NEXT: v_cmp_eq_f64_e64 s[2:3], 0, v[4:5] -; GFX940-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[2:3] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[2:3] +; GFX940-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_f64__nnan: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] -; GFX10-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 64 -; GFX10-NEXT: v_cmp_class_f64_e64 s4, v[2:3], 64 -; GFX10-NEXT: v_cmp_eq_f64_e64 s5, 0, v[4:5] -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s5 +; GFX10-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_f64__nnan: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] -; GFX11-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 64 -; GFX11-NEXT: v_cmp_class_f64_e64 s0, v[2:3], 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cmp_eq_f64_e64 s1, 0, v[4:5] -; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v0, s1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, v1, s1 +; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_f64__nnan: @@ -373,60 +260,33 @@ define double @v_maximum_f64__nnan_src0(double %arg0, double %src1) { ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000 -; GFX7-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 64 ; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX7-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX7-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_f64__nnan_src0: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000 -; GFX8-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 64 ; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX8-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX8-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_f64__nnan_src0: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000 -; GFX9-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 64 ; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX9-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX9-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_f64__nnan_src0: @@ -434,62 +294,33 @@ define double @v_maximum_f64__nnan_src0(double %arg0, double %src1) { ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX940-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 ; GFX940-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] -; GFX940-NEXT: v_mov_b32_e32 v6, 0x7ff80000 ; GFX940-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX940-NEXT: v_cmp_class_f64_e64 s[0:1], v[2:3], 64 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX940-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX940-NEXT: v_cmp_eq_f64_e64 s[2:3], 0, v[4:5] +; GFX940-NEXT: v_mov_b32_e32 v1, 0x7ff80000 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[2:3] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[2:3] ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_f64__nnan_src0: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; GFX10-NEXT: v_cmp_class_f64_e64 s4, v[2:3], 64 ; GFX10-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3] -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo -; GFX10-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 64 -; GFX10-NEXT: v_cmp_eq_f64_e64 s5, 0, v[4:5] -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_f64__nnan_src0: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; GFX11-NEXT: v_cmp_class_f64_e64 s0, v[2:3], 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3] -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo -; GFX11-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 64 -; GFX11-NEXT: v_cmp_eq_f64_e64 s1, 0, v[4:5] -; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v0, s1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, v1, s1 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_f64__nnan_src0: @@ -513,60 +344,33 @@ define double @v_maximum_f64__nnan_src1(double %src0, double %arg1) { ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 -; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000 ; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX7-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 64 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX7-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX7-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_maximum_f64__nnan_src1: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 -; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000 ; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX8-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 64 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX8-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX8-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximum_f64__nnan_src1: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 -; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000 ; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX9-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 64 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX9-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX9-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_maximum_f64__nnan_src1: @@ -574,21 +378,11 @@ define double @v_maximum_f64__nnan_src1(double %src0, double %arg1) { ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX940-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 ; GFX940-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] -; GFX940-NEXT: v_mov_b32_e32 v6, 0x7ff80000 ; GFX940-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX940-NEXT: v_cmp_class_f64_e64 s[0:1], v[2:3], 64 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX940-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 64 -; GFX940-NEXT: v_cmp_eq_f64_e64 s[2:3], 0, v[4:5] +; GFX940-NEXT: v_mov_b32_e32 v1, 0x7ff80000 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[2:3] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[2:3] ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_maximum_f64__nnan_src1: @@ -597,39 +391,20 @@ define double @v_maximum_f64__nnan_src1(double %src0, double %arg1) { ; GFX10-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 ; GFX10-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3] -; GFX10-NEXT: v_cmp_class_f64_e64 s4, v[2:3], 64 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo -; GFX10-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 64 -; GFX10-NEXT: v_cmp_eq_f64_e64 s5, 0, v[4:5] -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_maximum_f64__nnan_src1: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] ; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3] -; GFX11-NEXT: v_cmp_class_f64_e64 s0, v[2:3], 64 -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo -; GFX11-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 64 -; GFX11-NEXT: v_cmp_eq_f64_e64 s1, 0, v[4:5] -; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v0, s1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, v1, s1 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_maximum_f64__nnan_src1: @@ -654,30 +429,13 @@ define void @s_maximum_f64(double inreg %src0, double inreg %src1) { ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_mov_b32_e32 v0, s6 ; GFX7-NEXT: v_mov_b32_e32 v1, s7 -; GFX7-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[0:1] ; GFX7-NEXT: v_max_f64 v[2:3], s[4:5], v[0:1] -; GFX7-NEXT: v_cmp_class_f64_e64 s[8:9], s[4:5], 64 -; GFX7-NEXT: s_and_b64 s[10:11], vcc, exec -; GFX7-NEXT: v_readfirstlane_b32 s12, v3 -; GFX7-NEXT: v_readfirstlane_b32 s10, v2 -; GFX7-NEXT: s_cselect_b32 s11, 0x7ff80000, s12 -; GFX7-NEXT: v_cmp_class_f64_e64 s[12:13], s[6:7], 64 -; GFX7-NEXT: s_cselect_b32 s10, 0, s10 -; GFX7-NEXT: v_cmp_eq_f64_e64 s[14:15], s[10:11], 0 -; GFX7-NEXT: s_and_b64 s[16:17], s[8:9], exec -; GFX7-NEXT: s_cselect_b32 s5, s5, s11 -; GFX7-NEXT: s_and_b64 s[16:17], s[12:13], exec -; GFX7-NEXT: s_cselect_b32 s5, s7, s5 -; GFX7-NEXT: s_and_b64 s[16:17], s[14:15], exec -; GFX7-NEXT: s_cselect_b32 s5, s5, s11 -; GFX7-NEXT: s_and_b64 s[8:9], s[8:9], exec -; GFX7-NEXT: s_cselect_b32 s4, s4, s10 -; GFX7-NEXT: s_and_b64 s[8:9], s[12:13], exec -; GFX7-NEXT: s_cselect_b32 s4, s6, s4 -; GFX7-NEXT: s_and_b64 s[6:7], s[14:15], exec -; GFX7-NEXT: s_cselect_b32 s4, s4, s10 +; GFX7-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[0:1] +; GFX7-NEXT: v_mov_b32_e32 v4, 0x7ff80000 +; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc ; GFX7-NEXT: ;;#ASMSTART -; GFX7-NEXT: ; use s[4:5] +; GFX7-NEXT: ; use v[0:1] ; GFX7-NEXT: ;;#ASMEND ; GFX7-NEXT: s_setpc_b64 s[30:31] ; @@ -686,30 +444,13 @@ define void @s_maximum_f64(double inreg %src0, double inreg %src1) { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v1, s7 -; GFX8-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[0:1] ; GFX8-NEXT: v_max_f64 v[2:3], s[4:5], v[0:1] -; GFX8-NEXT: v_cmp_class_f64_e64 s[8:9], s[4:5], 64 -; GFX8-NEXT: s_and_b64 s[10:11], vcc, exec -; GFX8-NEXT: v_readfirstlane_b32 s12, v3 -; GFX8-NEXT: v_readfirstlane_b32 s10, v2 -; GFX8-NEXT: s_cselect_b32 s11, 0x7ff80000, s12 -; GFX8-NEXT: v_cmp_class_f64_e64 s[12:13], s[6:7], 64 -; GFX8-NEXT: s_cselect_b32 s10, 0, s10 -; GFX8-NEXT: v_cmp_eq_f64_e64 s[14:15], s[10:11], 0 -; GFX8-NEXT: s_and_b64 s[16:17], s[8:9], exec -; GFX8-NEXT: s_cselect_b32 s5, s5, s11 -; GFX8-NEXT: s_and_b64 s[16:17], s[12:13], exec -; GFX8-NEXT: s_cselect_b32 s5, s7, s5 -; GFX8-NEXT: s_and_b64 s[16:17], s[14:15], exec -; GFX8-NEXT: s_cselect_b32 s5, s5, s11 -; GFX8-NEXT: s_and_b64 s[8:9], s[8:9], exec -; GFX8-NEXT: s_cselect_b32 s4, s4, s10 -; GFX8-NEXT: s_and_b64 s[8:9], s[12:13], exec -; GFX8-NEXT: s_cselect_b32 s4, s6, s4 -; GFX8-NEXT: s_and_b64 s[6:7], s[14:15], exec -; GFX8-NEXT: s_cselect_b32 s4, s4, s10 +; GFX8-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v4, 0x7ff80000 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc ; GFX8-NEXT: ;;#ASMSTART -; GFX8-NEXT: ; use s[4:5] +; GFX8-NEXT: ; use v[0:1] ; GFX8-NEXT: ;;#ASMEND ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -718,30 +459,13 @@ define void @s_maximum_f64(double inreg %src0, double inreg %src1) { ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s7 -; GFX9-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[0:1] ; GFX9-NEXT: v_max_f64 v[2:3], s[4:5], v[0:1] -; GFX9-NEXT: v_cmp_class_f64_e64 s[8:9], s[4:5], 64 -; GFX9-NEXT: s_and_b64 s[10:11], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s12, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v2 -; GFX9-NEXT: s_cselect_b32 s11, 0x7ff80000, s12 -; GFX9-NEXT: v_cmp_class_f64_e64 s[12:13], s[6:7], 64 -; GFX9-NEXT: s_cselect_b32 s10, 0, s10 -; GFX9-NEXT: v_cmp_eq_f64_e64 s[14:15], s[10:11], 0 -; GFX9-NEXT: s_and_b64 s[16:17], s[8:9], exec -; GFX9-NEXT: s_cselect_b32 s5, s5, s11 -; GFX9-NEXT: s_and_b64 s[16:17], s[12:13], exec -; GFX9-NEXT: s_cselect_b32 s5, s7, s5 -; GFX9-NEXT: s_and_b64 s[16:17], s[14:15], exec -; GFX9-NEXT: s_cselect_b32 s5, s5, s11 -; GFX9-NEXT: s_and_b64 s[8:9], s[8:9], exec -; GFX9-NEXT: s_cselect_b32 s4, s4, s10 -; GFX9-NEXT: s_and_b64 s[8:9], s[12:13], exec -; GFX9-NEXT: s_cselect_b32 s4, s6, s4 -; GFX9-NEXT: s_and_b64 s[6:7], s[14:15], exec -; GFX9-NEXT: s_cselect_b32 s4, s4, s10 +; GFX9-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[0:1] +; GFX9-NEXT: v_mov_b32_e32 v4, 0x7ff80000 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc ; GFX9-NEXT: ;;#ASMSTART -; GFX9-NEXT: ; use s[4:5] +; GFX9-NEXT: ; use v[0:1] ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -749,30 +473,14 @@ define void @s_maximum_f64(double inreg %src0, double inreg %src1) { ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX940-NEXT: v_mov_b64_e32 v[0:1], s[2:3] +; GFX940-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1] +; GFX940-NEXT: v_mov_b32_e32 v4, 0x7ff80000 ; GFX940-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1] -; GFX940-NEXT: v_max_f64 v[0:1], s[0:1], v[0:1] -; GFX940-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX940-NEXT: v_readfirstlane_b32 s6, v1 -; GFX940-NEXT: v_readfirstlane_b32 s4, v0 -; GFX940-NEXT: v_cmp_class_f64_e64 s[8:9], s[0:1], 64 -; GFX940-NEXT: s_cselect_b32 s5, 0x7ff80000, s6 -; GFX940-NEXT: s_cselect_b32 s4, 0, s4 -; GFX940-NEXT: s_and_b64 s[10:11], s[8:9], exec -; GFX940-NEXT: v_cmp_class_f64_e64 s[10:11], s[2:3], 64 -; GFX940-NEXT: v_cmp_eq_f64_e64 s[6:7], s[4:5], 0 -; GFX940-NEXT: s_cselect_b32 s1, s1, s5 -; GFX940-NEXT: s_and_b64 s[12:13], s[10:11], exec -; GFX940-NEXT: s_cselect_b32 s1, s3, s1 -; GFX940-NEXT: s_and_b64 s[12:13], s[6:7], exec -; GFX940-NEXT: s_cselect_b32 s1, s1, s5 -; GFX940-NEXT: s_and_b64 s[8:9], s[8:9], exec -; GFX940-NEXT: s_cselect_b32 s0, s0, s4 -; GFX940-NEXT: s_and_b64 s[8:9], s[10:11], exec -; GFX940-NEXT: s_cselect_b32 s0, s2, s0 -; GFX940-NEXT: s_and_b64 s[2:3], s[6:7], exec -; GFX940-NEXT: s_cselect_b32 s0, s0, s4 +; GFX940-NEXT: s_nop 1 +; GFX940-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX940-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc ; GFX940-NEXT: ;;#ASMSTART -; GFX940-NEXT: ; use s[0:1] +; GFX940-NEXT: ; use v[0:1] ; GFX940-NEXT: ;;#ASMEND ; GFX940-NEXT: s_setpc_b64 s[30:31] ; @@ -780,29 +488,11 @@ define void @s_maximum_f64(double inreg %src0, double inreg %src1) { ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_max_f64 v[0:1], s[4:5], s[6:7] -; GFX10-NEXT: v_cmp_u_f64_e64 s8, s[4:5], s[6:7] -; GFX10-NEXT: v_cmp_class_f64_e64 s11, s[4:5], 64 -; GFX10-NEXT: v_cmp_class_f64_e64 s12, s[6:7], 64 -; GFX10-NEXT: v_readfirstlane_b32 s9, v1 -; GFX10-NEXT: v_readfirstlane_b32 s10, v0 -; GFX10-NEXT: s_and_b32 s8, s8, exec_lo -; GFX10-NEXT: s_cselect_b32 s9, 0x7ff80000, s9 -; GFX10-NEXT: s_cselect_b32 s8, 0, s10 -; GFX10-NEXT: s_and_b32 s13, s11, exec_lo -; GFX10-NEXT: v_cmp_eq_f64_e64 s10, s[8:9], 0 -; GFX10-NEXT: s_cselect_b32 s5, s5, s9 -; GFX10-NEXT: s_and_b32 s13, s12, exec_lo -; GFX10-NEXT: s_cselect_b32 s5, s7, s5 -; GFX10-NEXT: s_and_b32 s7, s10, exec_lo -; GFX10-NEXT: s_cselect_b32 s5, s5, s9 -; GFX10-NEXT: s_and_b32 s7, s11, exec_lo -; GFX10-NEXT: s_cselect_b32 s4, s4, s8 -; GFX10-NEXT: s_and_b32 s7, s12, exec_lo -; GFX10-NEXT: s_cselect_b32 s4, s6, s4 -; GFX10-NEXT: s_and_b32 s6, s10, exec_lo -; GFX10-NEXT: s_cselect_b32 s4, s4, s8 +; GFX10-NEXT: v_cmp_u_f64_e64 s4, s[4:5], s[6:7] +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0, s4 ; GFX10-NEXT: ;;#ASMSTART -; GFX10-NEXT: ; use s[4:5] +; GFX10-NEXT: ; use v[0:1] ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: s_setpc_b64 s[30:31] ; @@ -810,32 +500,12 @@ define void @s_maximum_f64(double inreg %src0, double inreg %src1) { ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_max_f64 v[0:1], s[0:1], s[2:3] -; GFX11-NEXT: v_cmp_u_f64_e64 s4, s[0:1], s[2:3] -; GFX11-NEXT: v_cmp_class_f64_e64 s7, s[0:1], 64 -; GFX11-NEXT: v_cmp_class_f64_e64 s8, s[2:3], 64 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_readfirstlane_b32 s5, v1 -; GFX11-NEXT: v_readfirstlane_b32 s6, v0 -; GFX11-NEXT: s_and_b32 s4, s4, exec_lo -; GFX11-NEXT: s_cselect_b32 s5, 0x7ff80000, s5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: s_cselect_b32 s4, 0, s6 -; GFX11-NEXT: s_and_b32 s9, s7, exec_lo -; GFX11-NEXT: v_cmp_eq_f64_e64 s6, s[4:5], 0 -; GFX11-NEXT: s_cselect_b32 s1, s1, s5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: s_and_b32 s9, s8, exec_lo -; GFX11-NEXT: s_cselect_b32 s1, s3, s1 -; GFX11-NEXT: s_and_b32 s3, s6, exec_lo -; GFX11-NEXT: s_cselect_b32 s1, s1, s5 -; GFX11-NEXT: s_and_b32 s3, s7, exec_lo -; GFX11-NEXT: s_cselect_b32 s0, s0, s4 -; GFX11-NEXT: s_and_b32 s3, s8, exec_lo -; GFX11-NEXT: s_cselect_b32 s0, s2, s0 -; GFX11-NEXT: s_and_b32 s2, s6, exec_lo -; GFX11-NEXT: s_cselect_b32 s0, s0, s4 +; GFX11-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[2:3] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0 ; GFX11-NEXT: ;;#ASMSTART -; GFX11-NEXT: ; use s[0:1] +; GFX11-NEXT: ; use v[0:1] ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: s_setpc_b64 s[30:31] ; diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll index 66f3a48b13ee..95d351e8f1fa 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll @@ -14,13 +14,7 @@ define half @v_minimum_f16(half %src0, half %src1) { ; GFX8-NEXT: v_min_f16_e32 v2, v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_f16: @@ -29,13 +23,7 @@ define half @v_minimum_f16(half %src0, half %src1) { ; GFX9-NEXT: v_min_f16_e32 v2, v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_f16: @@ -45,16 +33,7 @@ define half @v_minimum_f16(half %src0, half %src1) { ; GFX940-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_f16: @@ -62,13 +41,7 @@ define half @v_minimum_f16(half %src0, half %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_min_f16_e32 v2, v0, v1 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_f16: @@ -76,15 +49,8 @@ define half @v_minimum_f16(half %src0, half %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_min_f16_e32 v2, v0, v1 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_f16: @@ -104,66 +70,31 @@ define half @v_minimum_f16__nnan(half %src0, half %src1) { ; GFX8-LABEL: v_minimum_f16__nnan: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_min_f16_e32 v2, v0, v1 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_min_f16_e32 v0, v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_f16__nnan: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_min_f16_e32 v2, v0, v1 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_min_f16_e32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_f16__nnan: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_min_f16_e32 v2, v0, v1 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_min_f16_e32 v0, v0, v1 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_f16__nnan: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_min_f16_e32 v2, v0, v1 -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_min_f16_e32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_f16__nnan: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_min_f16_e32 v2, v0, v1 -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: v_min_f16_e32 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_f16__nnan: @@ -290,13 +221,7 @@ define half @v_minimum_f16__nnan_src0(half %arg0, half %src1) { ; GFX8-NEXT: v_min_f16_e32 v2, v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_f16__nnan_src0: @@ -306,13 +231,7 @@ define half @v_minimum_f16__nnan_src0(half %arg0, half %src1) { ; GFX9-NEXT: v_min_f16_e32 v2, v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_f16__nnan_src0: @@ -323,16 +242,7 @@ define half @v_minimum_f16__nnan_src0(half %arg0, half %src1) { ; GFX940-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_f16__nnan_src0: @@ -341,13 +251,7 @@ define half @v_minimum_f16__nnan_src0(half %arg0, half %src1) { ; GFX10-NEXT: v_add_f16_e32 v0, 1.0, v0 ; GFX10-NEXT: v_min_f16_e32 v2, v0, v1 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_f16__nnan_src0: @@ -357,15 +261,7 @@ define half @v_minimum_f16__nnan_src0(half %arg0, half %src1) { ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_min_f16_e32 v2, v0, v1 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_f16__nnan_src0: @@ -392,13 +288,7 @@ define half @v_minimum_f16__nnan_src1(half %src0, half %arg1) { ; GFX8-NEXT: v_min_f16_e32 v2, v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_f16__nnan_src1: @@ -408,13 +298,7 @@ define half @v_minimum_f16__nnan_src1(half %src0, half %arg1) { ; GFX9-NEXT: v_min_f16_e32 v2, v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_f16__nnan_src1: @@ -425,16 +309,7 @@ define half @v_minimum_f16__nnan_src1(half %src0, half %arg1) { ; GFX940-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_f16__nnan_src1: @@ -443,13 +318,7 @@ define half @v_minimum_f16__nnan_src1(half %src0, half %arg1) { ; GFX10-NEXT: v_add_f16_e32 v1, 1.0, v1 ; GFX10-NEXT: v_min_f16_e32 v2, v0, v1 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_f16__nnan_src1: @@ -459,15 +328,7 @@ define half @v_minimum_f16__nnan_src1(half %src0, half %arg1) { ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_min_f16_e32 v2, v0, v1 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_f16__nnan_src1: @@ -494,14 +355,7 @@ define void @s_minimum_f16(half inreg %src0, half inreg %src1) { ; GFX8-NEXT: v_min_f16_e32 v1, s4, v0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, s4, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX8-NEXT: v_mov_b32_e32 v2, s4 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, s4, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, s5, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use v0 @@ -515,14 +369,7 @@ define void @s_minimum_f16(half inreg %src0, half inreg %src1) { ; GFX9-NEXT: v_min_f16_e32 v1, s4, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, s4, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX9-NEXT: v_mov_b32_e32 v2, s4 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, s4, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, s5, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; use v0 @@ -537,17 +384,7 @@ define void @s_minimum_f16(half inreg %src0, half inreg %src1) { ; GFX940-NEXT: v_mov_b32_e32 v2, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, s0, v0 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX940-NEXT: v_mov_b32_e32 v2, s0 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, s0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, s1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX940-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX940-NEXT: ;;#ASMSTART ; GFX940-NEXT: ; use v0 @@ -559,13 +396,7 @@ define void @s_minimum_f16(half inreg %src0, half inreg %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_min_f16_e64 v0, s4, s5 ; GFX10-NEXT: v_cmp_o_f16_e64 vcc_lo, s4, s5 -; GFX10-NEXT: v_cmp_class_f16_e64 s6, s4, 32 ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v1, v0, s4, s6 -; GFX10-NEXT: v_cmp_class_f16_e64 s4, s5, 32 -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s5, s4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use v0 @@ -577,16 +408,8 @@ define void @s_minimum_f16(half inreg %src0, half inreg %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_min_f16_e64 v0, s0, s1 ; GFX11-NEXT: v_cmp_o_f16_e64 vcc_lo, s0, s1 -; GFX11-NEXT: v_cmp_class_f16_e64 s2, s0, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v0, s0, s2 -; GFX11-NEXT: v_cmp_class_f16_e64 s0, s1, 32 -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s1, s0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use v0 @@ -652,23 +475,9 @@ define <2 x half> @v_minimum_v2f16(<2 x half> %src0, <2 x half> %src1) { ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_mov_b32 s4, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -682,30 +491,10 @@ define <2 x half> @v_minimum_v2f16(<2 x half> %src0, <2 x half> %src1) { ; GFX940-NEXT: s_mov_b32 s0, 0x5040100 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 ; GFX940-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: v_perm_b32 v0, v0, v4, s0 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; @@ -713,26 +502,12 @@ define <2 x half> @v_minimum_v2f16(<2 x half> %src0, <2 x half> %src1) { ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_min_f16 v2, v0, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v0 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo -; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo +; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_v2f16: @@ -744,25 +519,10 @@ define <2 x half> @v_minimum_v2f16(<2 x half> %src0, <2 x half> %src1) { ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v5, vcc_lo ; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; @@ -808,100 +568,25 @@ define <2 x half> @v_minimum_v2f16__nnan(<2 x half> %src0, <2 x half> %src1) { ; GFX9-LABEL: v_minimum_v2f16__nnan: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GFX9-NEXT: v_pk_min_f16 v3, v0, v1 -; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX9-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4 +; GFX9-NEXT: v_pk_min_f16 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_v2f16__nnan: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GFX940-NEXT: v_pk_min_f16 v3, v0, v1 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX940-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX940-NEXT: s_mov_b32 s0, 0x5040100 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX940-NEXT: v_perm_b32 v0, v2, v0, s0 +; GFX940-NEXT: v_pk_min_f16 v0, v0, v1 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_v2f16__nnan: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_pk_min_f16 v2, v0, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX10-NEXT: v_pk_min_f16 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_v2f16__nnan: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_pk_min_f16 v2, v0, v1 -; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX11-NEXT: v_pk_min_f16 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_v2f16__nnan: @@ -1101,30 +786,16 @@ define void @s_minimum_v2f16(<2 x half> inreg %src0, <2 x half> inreg %src1) { ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v0, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: s_lshr_b32 s5, s5, 16 ; GFX9-NEXT: v_pk_min_f16 v1, s4, v1 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, s4, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v2, v1, vcc -; GFX9-NEXT: v_mov_b32_e32 v4, s4 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, s4, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, s5, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX9-NEXT: s_lshr_b32 s5, s5, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX9-NEXT: s_lshr_b32 s4, s4, 16 ; GFX9-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, s4, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX9-NEXT: v_mov_b32_e32 v2, s4 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, s4, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, s5, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX9-NEXT: ;;#ASMSTART @@ -1137,38 +808,18 @@ define void @s_minimum_v2f16(<2 x half> inreg %src0, <2 x half> inreg %src1) { ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX940-NEXT: v_mov_b32_e32 v0, s1 ; GFX940-NEXT: v_mov_b32_e32 v1, s1 +; GFX940-NEXT: s_lshr_b32 s1, s1, 16 ; GFX940-NEXT: v_pk_min_f16 v1, s0, v1 ; GFX940-NEXT: v_mov_b32_e32 v2, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, s0, v0 -; GFX940-NEXT: v_mov_b32_e32 v4, s0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v2, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, s0, 32 ; GFX940-NEXT: s_lshr_b32 s0, s0, 16 -; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, s1, 32 -; GFX940-NEXT: s_lshr_b32 s1, s1, 16 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX940-NEXT: v_mov_b32_e32 v3, s1 +; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, s0, v3 ; GFX940-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX940-NEXT: v_mov_b32_e32 v2, s0 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, s0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, s1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX940-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX940-NEXT: ;;#ASMSTART ; GFX940-NEXT: ; use v0 @@ -1181,24 +832,12 @@ define void @s_minimum_v2f16(<2 x half> inreg %src0, <2 x half> inreg %src1) { ; GFX10-NEXT: v_pk_min_f16 v0, s4, s5 ; GFX10-NEXT: v_cmp_o_f16_e64 vcc_lo, s4, s5 ; GFX10-NEXT: s_lshr_b32 s6, s5, 16 -; GFX10-NEXT: s_lshr_b32 s7, s4, 16 -; GFX10-NEXT: v_cmp_class_f16_e64 s8, s4, 32 +; GFX10-NEXT: s_lshr_b32 s4, s4, 16 ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e64 vcc_lo, s7, s6 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v0, s4, s8 -; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 s4, s7, 32 -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v1, s7, s4 -; GFX10-NEXT: v_cmp_class_f16_e64 s4, s5, 32 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s5, s4 -; GFX10-NEXT: v_cmp_class_f16_e64 s4, s6, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s6, s4 -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1 +; GFX10-NEXT: v_cmp_o_f16_e64 vcc_lo, s4, s6 ; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v1, vcc_lo ; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use v0 @@ -1211,27 +850,14 @@ define void @s_minimum_v2f16(<2 x half> inreg %src0, <2 x half> inreg %src1) { ; GFX11-NEXT: v_pk_min_f16 v0, s0, s1 ; GFX11-NEXT: v_cmp_o_f16_e64 vcc_lo, s0, s1 ; GFX11-NEXT: s_lshr_b32 s2, s1, 16 -; GFX11-NEXT: s_lshr_b32 s3, s0, 16 -; GFX11-NEXT: v_cmp_class_f16_e64 s4, s0, 32 +; GFX11-NEXT: s_lshr_b32 s0, s0, 16 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e64 vcc_lo, s3, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e64 v2, v0, s0, s4 +; GFX11-NEXT: v_cmp_o_f16_e64 vcc_lo, s0, s2 +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 s0, s3, 32 -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v3, v1, s3, s0 -; GFX11-NEXT: v_cmp_class_f16_e64 s0, s1, 32 -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s1, s0 -; GFX11-NEXT: v_cmp_class_f16_e64 s0, s2, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s2, s0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_and_b32 v0, 0xffff, v0 ; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use v0 @@ -1265,31 +891,13 @@ define <3 x half> @v_minimum_v3f16(<3 x half> %src0, <3 x half> %src1) { ; GFX8-NEXT: v_min_f16_e32 v6, v5, v4 ; GFX8-NEXT: v_mov_b32_e32 v7, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v5, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc ; GFX8-NEXT: v_min_f16_e32 v5, v1, v3 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc ; GFX8-NEXT: v_min_f16_e32 v3, v0, v2 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v3, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] @@ -1300,33 +908,13 @@ define <3 x half> @v_minimum_v3f16(<3 x half> %src0, <3 x half> %src1) { ; GFX9-NEXT: v_pk_min_f16 v4, v1, v3 ; GFX9-NEXT: v_mov_b32_e32 v5, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc ; GFX9-NEXT: v_pk_min_f16 v3, v0, v2 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc ; GFX9-NEXT: s_mov_b32 s4, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -1337,46 +925,16 @@ define <3 x half> @v_minimum_v3f16(<3 x half> %src0, <3 x half> %src1) { ; GFX940-NEXT: v_pk_min_f16 v4, v1, v3 ; GFX940-NEXT: v_mov_b32_e32 v5, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 -; GFX940-NEXT: s_mov_b32 s0, 0x5040100 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 ; GFX940-NEXT: v_pk_min_f16 v3, v0, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX940-NEXT: s_mov_b32 s0, 0x5040100 +; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 ; GFX940-NEXT: s_nop 1 ; GFX940-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 ; GFX940-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX940-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc ; GFX940-NEXT: v_perm_b32 v0, v0, v4, s0 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; @@ -1384,35 +942,15 @@ define <3 x half> @v_minimum_v3f16(<3 x half> %src0, <3 x half> %src1) { ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_min_f16 v4, v0, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v0 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2 -; GFX10-NEXT: v_pk_min_f16 v8, v1, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v4 +; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v4, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v7, 0x7e00, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_pk_min_f16 v2, v1, v3 +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v8, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo +; GFX10-NEXT: v_perm_b32 v0, v0, v4, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_v3f16: @@ -1422,35 +960,17 @@ define <3 x half> @v_minimum_v3f16(<3 x half> %src0, <3 x half> %src1) { ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v0 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_pk_min_f16 v8, v1, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v4, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v7, 0x7e00, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo +; GFX11-NEXT: v_pk_min_f16 v4, v1, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v7, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3 -; GFX11-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v8, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v6, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v7 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo ; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_v3f16: @@ -1471,160 +991,38 @@ define <3 x half> @v_minimum_v3f16__nnan(<3 x half> %src0, <3 x half> %src1) { ; GFX8-LABEL: v_minimum_v3f16__nnan: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 -; GFX8-NEXT: v_min_f16_e32 v6, v5, v4 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX8-NEXT: v_min_f16_e32 v5, v1, v3 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_min_f16_e32 v3, v0, v2 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 -; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_min_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_min_f16_e32 v0, v0, v2 +; GFX8-NEXT: v_min_f16_e32 v1, v1, v3 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_v3f16__nnan: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v0 -; GFX9-NEXT: v_pk_min_f16 v5, v0, v2 -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX9-NEXT: v_pk_min_f16 v6, v1, v3 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX9-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4 +; GFX9-NEXT: v_pk_min_f16 v0, v0, v2 +; GFX9-NEXT: v_pk_min_f16 v1, v1, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_v3f16__nnan: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v0 -; GFX940-NEXT: v_pk_min_f16 v5, v0, v2 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX940-NEXT: v_lshrrev_b32_e32 v7, 16, v2 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX940-NEXT: s_mov_b32 s0, 0x5040100 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX940-NEXT: v_pk_min_f16 v6, v1, v3 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX940-NEXT: v_perm_b32 v0, v4, v0, s0 +; GFX940-NEXT: v_pk_min_f16 v0, v0, v2 +; GFX940-NEXT: v_pk_min_f16 v1, v1, v3 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_v3f16__nnan: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_pk_min_f16 v4, v0, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v0 -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v2 -; GFX10-NEXT: v_pk_min_f16 v8, v1, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo +; GFX10-NEXT: v_pk_min_f16 v0, v0, v2 +; GFX10-NEXT: v_pk_min_f16 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_v3f16__nnan: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_pk_min_f16 v4, v0, v2 -; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0 -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v2 -; GFX11-NEXT: v_pk_min_f16 v8, v1, v3 -; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v6 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 +; GFX11-NEXT: v_pk_min_f16 v0, v0, v2 +; GFX11-NEXT: v_pk_min_f16 v1, v1, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_v3f16__nnan: @@ -1807,42 +1205,18 @@ define <4 x half> @v_minimum_v4f16(<4 x half> %src0, <4 x half> %src1) { ; GFX8-NEXT: v_min_f16_e32 v6, v5, v4 ; GFX8-NEXT: v_mov_b32_e32 v7, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v5, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 ; GFX8-NEXT: v_min_f16_e32 v8, v6, v5 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v6, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v7, v8, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc ; GFX8-NEXT: v_min_f16_e32 v6, v1, v3 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc ; GFX8-NEXT: v_min_f16_e32 v3, v0, v2 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v3, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 @@ -1856,44 +1230,16 @@ define <4 x half> @v_minimum_v4f16(<4 x half> %src0, <4 x half> %src1) { ; GFX9-NEXT: v_mov_b32_e32 v5, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v6, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc ; GFX9-NEXT: v_pk_min_f16 v3, v0, v2 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v4, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v2, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX9-NEXT: s_mov_b32 s4, 0x5040100 +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc +; GFX9-NEXT: s_mov_b32 s4, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4 ; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -1907,59 +1253,19 @@ define <4 x half> @v_minimum_v4f16(<4 x half> %src0, <4 x half> %src1) { ; GFX940-NEXT: s_mov_b32 s0, 0x5040100 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 ; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v6, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX940-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_min_f16 v3, v0, v2 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 ; GFX940-NEXT: v_perm_b32 v1, v1, v6, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 ; GFX940-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v4, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v7, v2, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v4 -; GFX940-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc ; GFX940-NEXT: v_perm_b32 v0, v0, v4, s0 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; @@ -1968,46 +1274,18 @@ define <4 x half> @v_minimum_v4f16(<4 x half> %src0, <4 x half> %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_min_f16 v4, v1, v3 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GFX10-NEXT: v_pk_min_f16 v7, v0, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v4, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo +; GFX10-NEXT: v_pk_min_f16 v5, v0, v2 +; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v4, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v11, 0x7e00, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v4, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v10, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v7, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v4, v10, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v3, v6, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v3 -; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo -; GFX10-NEXT: v_perm_b32 v1, v3, v1, 0x5040100 +; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v5 +; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v5, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v7, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_perm_b32 v0, v0, v5, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo +; GFX10-NEXT: v_perm_b32 v1, v1, v6, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_v4f16: @@ -2015,47 +1293,23 @@ define <4 x half> @v_minimum_v4f16(<4 x half> %src0, <4 x half> %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_pk_min_f16 v4, v1, v3 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3 +; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v1 ; GFX11-NEXT: v_pk_min_f16 v7, v0, v2 -; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v3 -; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v4, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v0 -; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v2 +; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v11, 0x7e00, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v7 +; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v7, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v8 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v9, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v4, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v10, v9 -; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v7, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v4, v10, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v3, v6, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v11 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v3 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v4, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_perm_b32 v1, v3, v1, 0x5040100 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; @@ -2077,212 +1331,40 @@ define <4 x half> @v_minimum_v4f16__nnan(<4 x half> %src0, <4 x half> %src1) { ; GFX8-LABEL: v_minimum_v4f16__nnan: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX8-NEXT: v_min_f16_e32 v6, v5, v4 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX8-NEXT: v_min_f16_e32 v7, v6, v5 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX8-NEXT: v_min_f16_e32 v6, v1, v3 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX8-NEXT: v_min_f16_e32 v3, v0, v2 -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5 -; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 -; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_min_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_min_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_min_f16_e32 v1, v1, v3 +; GFX8-NEXT: v_min_f16_e32 v0, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v5 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_v4f16__nnan: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v1 -; GFX9-NEXT: v_pk_min_f16 v5, v1, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX9-NEXT: v_pk_min_f16 v7, v0, v2 -; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v7 -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v9, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc -; GFX9-NEXT: s_mov_b32 s4, 0x5040100 -; GFX9-NEXT: v_perm_b32 v0, v6, v0, s4 -; GFX9-NEXT: v_perm_b32 v1, v4, v1, s4 +; GFX9-NEXT: v_pk_min_f16 v0, v0, v2 +; GFX9-NEXT: v_pk_min_f16 v1, v1, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_v4f16__nnan: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v1 -; GFX940-NEXT: v_pk_min_f16 v5, v1, v3 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; GFX940-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v9, 16, v2 -; GFX940-NEXT: s_mov_b32 s0, 0x5040100 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX940-NEXT: v_pk_min_f16 v7, v0, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GFX940-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX940-NEXT: v_lshrrev_b32_e32 v8, 16, v7 -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v9, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX940-NEXT: v_perm_b32 v1, v4, v1, s0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc -; GFX940-NEXT: v_perm_b32 v0, v6, v0, s0 +; GFX940-NEXT: v_pk_min_f16 v0, v0, v2 +; GFX940-NEXT: v_pk_min_f16 v1, v1, v3 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_v4f16__nnan: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_pk_min_f16 v4, v1, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX10-NEXT: v_pk_min_f16 v6, v0, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v4 -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v7, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo -; GFX10-NEXT: v_perm_b32 v1, v5, v1, 0x5040100 +; GFX10-NEXT: v_pk_min_f16 v0, v0, v2 +; GFX10-NEXT: v_pk_min_f16 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_v4f16__nnan: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_pk_min_f16 v4, v1, v3 -; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX11-NEXT: v_pk_min_f16 v6, v0, v2 -; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v0 -; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v4 -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v6 -; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v11 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v11, v7, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v6 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo -; GFX11-NEXT: v_perm_b32 v1, v5, v1, 0x5040100 +; GFX11-NEXT: v_pk_min_f16 v0, v0, v2 +; GFX11-NEXT: v_pk_min_f16 v1, v1, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_v4f16__nnan: @@ -2493,82 +1575,34 @@ define <8 x half> @v_minimum_v8f16(<8 x half> %src0, <8 x half> %src1) { ; GFX8-NEXT: v_min_f16_e32 v10, v9, v8 ; GFX8-NEXT: v_mov_b32_e32 v11, 0x7e00 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v9, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v9, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v8, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v10, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v6 ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2 ; GFX8-NEXT: v_min_f16_e32 v12, v10, v9 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v10, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v11, v12, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v10, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v9, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v5 ; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v1 ; GFX8-NEXT: v_min_f16_e32 v13, v12, v10 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v12, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v11, v13, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v12, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v10, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v13, v10, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v4 ; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v0 ; GFX8-NEXT: v_min_f16_e32 v14, v13, v12 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v13, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v14, v11, v14, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v13, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v14, v13, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v12, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v12, v11, v14, vcc ; GFX8-NEXT: v_min_f16_e32 v13, v3, v7 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v3, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v11, v13, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v13, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v13, vcc ; GFX8-NEXT: v_min_f16_e32 v7, v2, v6 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v2, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v7, vcc ; GFX8-NEXT: v_min_f16_e32 v6, v1, v5 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v11, v6, vcc ; GFX8-NEXT: v_min_f16_e32 v5, v0, v4 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v11, v5, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v12 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v10 @@ -2586,83 +1620,27 @@ define <8 x half> @v_minimum_v8f16(<8 x half> %src0, <8 x half> %src1) { ; GFX9-NEXT: v_mov_b32_e32 v9, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v7 ; GFX9-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v10, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v7, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v7 -; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v8, vcc ; GFX9-NEXT: v_pk_min_f16 v7, v2, v6 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v2, v6 ; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v7, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v8, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v6, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v2, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v7, vcc ; GFX9-NEXT: v_pk_min_f16 v6, v1, v5 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v5 ; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v6, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v7, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v5, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v6, vcc ; GFX9-NEXT: v_pk_min_f16 v5, v0, v4 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v6, v9, v5, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v6, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v4, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v4 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v5, vcc ; GFX9-NEXT: s_mov_b32 s4, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v0, v6, s4 ; GFX9-NEXT: v_perm_b32 v1, v1, v7, s4 @@ -2679,117 +1657,37 @@ define <8 x half> @v_minimum_v8f16(<8 x half> %src0, <8 x half> %src1) { ; GFX940-NEXT: s_mov_b32 s0, 0x5040100 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 ; GFX940-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v10, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v11, v7, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX940-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v3, v7 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_min_f16 v7, v2, v6 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v3, v9, v8, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v2, v6 ; GFX940-NEXT: v_perm_b32 v3, v3, v10, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v8, v9, v7, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 ; GFX940-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v8, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v11, v6, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v8 -; GFX940-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v2, v6 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_min_f16 v6, v1, v5 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v2, v9, v7, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v1, v5 ; GFX940-NEXT: v_perm_b32 v2, v2, v8, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v7, v9, v6, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 ; GFX940-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v7, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v11, v5, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v7 -; GFX940-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v1, v5 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_min_f16 v5, v0, v4 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v1, v9, v6, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v4 ; GFX940-NEXT: v_perm_b32 v1, v1, v7, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v6, v9, v5, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 ; GFX940-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v6, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v11, v4, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v6 -; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v4 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v0, v4 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v5 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v9, v5, vcc ; GFX940-NEXT: v_perm_b32 v0, v0, v6, s0 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; @@ -2798,88 +1696,32 @@ define <8 x half> @v_minimum_v8f16(<8 x half> %src0, <8 x half> %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_min_f16 v8, v3, v7 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v7 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v3 -; GFX10-NEXT: v_pk_min_f16 v13, v1, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v8, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v11, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v8, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v11, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v8, v11, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v9 -; GFX10-NEXT: v_pk_min_f16 v11, v2, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v6 -; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v2 +; GFX10-NEXT: v_pk_min_f16 v9, v2, v6 +; GFX10-NEXT: v_pk_min_f16 v12, v1, v5 +; GFX10-NEXT: v_pk_min_f16 v13, v0, v4 +; GFX10-NEXT: v_cndmask_b32_e32 v10, 0x7e00, v8, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v11, 0x7e00, v11, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v10, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v12, 0x7e00, v12, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v9 +; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v9, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v11, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v14, 0x7e00, v13, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v14, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v10, v9, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX10-NEXT: v_pk_min_f16 v10, v0, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v15, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v11 -; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12 -; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14 -; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v0 -; GFX10-NEXT: v_perm_b32 v2, v6, v2, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v13 +; GFX10-NEXT: v_perm_b32 v2, v2, v9, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v12, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v4 -; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v10, 0x7e00, v10, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v12, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v14, 0x7e00, v14, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5 +; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v12 ; GFX10-NEXT: v_cndmask_b32_e32 v13, 0x7e00, v13, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v12, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v11, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v11, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13 -; GFX10-NEXT: v_perm_b32 v0, v4, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 -; GFX10-NEXT: v_perm_b32 v1, v1, v9, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v7, vcc_lo -; GFX10-NEXT: v_perm_b32 v3, v5, v3, 0x5040100 +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v4 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v11, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_perm_b32 v0, v0, v13, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v12, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_perm_b32 v1, v1, v6, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v8, vcc_lo +; GFX10-NEXT: v_perm_b32 v3, v3, v10, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_v8f16: @@ -2887,94 +1729,42 @@ define <8 x half> @v_minimum_v8f16(<8 x half> %src0, <8 x half> %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_pk_min_f16 v8, v3, v7 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7 -; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v7 -; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v3 -; GFX11-NEXT: v_pk_min_f16 v13, v1, v5 +; GFX11-NEXT: v_pk_min_f16 v10, v2, v6 +; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v6 +; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v2 +; GFX11-NEXT: v_pk_min_f16 v14, v1, v5 ; GFX11-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v8, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v11, v10 -; GFX11-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v8, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v11, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v8, v11, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v9 -; GFX11-NEXT: v_pk_min_f16 v11, v2, v6 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v6 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v11 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo -; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v2 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6 -; GFX11-NEXT: v_cndmask_b32_e32 v11, 0x7e00, v11, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v10, v9 -; GFX11-NEXT: v_cndmask_b32_e32 v12, 0x7e00, v12, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v13, 16, v10 +; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v10, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v12, v11 +; GFX11-NEXT: v_pk_min_f16 v11, v0, v4 +; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v4 +; GFX11-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v13, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v14, 0x7e00, v13, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v15, v14, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v10, v9, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX11-NEXT: v_pk_min_f16 v10, v0, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v9, v15, v5, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v11 +; GFX11-NEXT: v_lshrrev_b32_e32 v13, 16, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12 -; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14 -; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-NEXT: v_perm_b32 v2, v6, v2, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX11-NEXT: v_lshrrev_b32_e32 v15, 16, v11 +; GFX11-NEXT: v_cndmask_b32_e32 v10, 0x7e00, v14, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v4 -; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v10 -; GFX11-NEXT: v_cndmask_b32_e32 v10, 0x7e00, v10, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v12, v11 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e32 v14, 0x7e00, v14, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX11-NEXT: v_perm_b32 v2, v6, v2, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v11, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v13, v12 +; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v15, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5 -; GFX11-NEXT: v_cndmask_b32_e32 v13, 0x7e00, v13, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v12, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v11, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v12, v11, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v10 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v8 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_perm_b32 v1, v1, v9, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v7, vcc_lo ; GFX11-NEXT: v_perm_b32 v0, v4, v0, 0x5040100 -; GFX11-NEXT: v_perm_b32 v3, v5, v3, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v14, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7 +; GFX11-NEXT: v_perm_b32 v1, v1, v10, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v8, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_perm_b32 v3, v3, v9, 0x5040100 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_v8f16: @@ -2998,166 +1788,70 @@ define <16 x half> @v_minimum_v16f16(<16 x half> %src0, <16 x half> %src1) { ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v15 -; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v7 -; GFX8-NEXT: v_min_f16_e32 v19, v18, v16 -; GFX8-NEXT: v_mov_b32_e32 v17, 0x7e00 -; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v18, v16 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v17, v19, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v18, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v16, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v16, v19, v16, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v14 -; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v6 -; GFX8-NEXT: v_min_f16_e32 v20, v19, v18 -; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v19, v18 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v19, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v18, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v20 -; GFX8-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v13 +; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v7 +; GFX8-NEXT: v_min_f16_e32 v18, v17, v16 +; GFX8-NEXT: v_mov_b32_e32 v19, 0x7e00 +; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v17, v16 +; GFX8-NEXT: v_cndmask_b32_e32 v16, v19, v18, vcc +; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v14 +; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v6 +; GFX8-NEXT: v_min_f16_e32 v20, v18, v17 +; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v18, v17 +; GFX8-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc +; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v13 ; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v5 -; GFX8-NEXT: v_min_f16_e32 v21, v20, v19 -; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v20, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v17, v21, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v20, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v19, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v21 -; GFX8-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc +; GFX8-NEXT: v_min_f16_e32 v21, v20, v18 +; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v20, v18 +; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v21, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v12 ; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v4 ; GFX8-NEXT: v_min_f16_e32 v22, v21, v20 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v21, v20 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v17, v22, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v21, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v20, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v22 -; GFX8-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v20, v19, v22, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v11 ; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v3 ; GFX8-NEXT: v_min_f16_e32 v23, v22, v21 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v22, v21 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v17, v23, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v22, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v21, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v21, v19, v23, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v10 ; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v2 ; GFX8-NEXT: v_min_f16_e32 v24, v23, v22 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v23, v22 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v17, v24, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v23, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v22, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v22, v19, v24, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v9 ; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v1 ; GFX8-NEXT: v_min_f16_e32 v25, v24, v23 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v24, v23 -; GFX8-NEXT: v_cndmask_b32_e32 v25, v17, v25, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v24, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v23, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v25 -; GFX8-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v23, v19, v25, vcc ; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v8 ; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v0 ; GFX8-NEXT: v_min_f16_e32 v26, v25, v24 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v25, v24 -; GFX8-NEXT: v_cndmask_b32_e32 v26, v17, v26, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v25, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v25, v26, v25, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v24, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v26 -; GFX8-NEXT: v_cndmask_b32_e32 v24, v26, v24, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v24, v19, v26, vcc ; GFX8-NEXT: v_min_f16_e32 v25, v7, v15 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v7, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v25, v17, v25, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v15, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v25 -; GFX8-NEXT: v_cndmask_b32_e32 v7, v25, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, v19, v25, vcc ; GFX8-NEXT: v_min_f16_e32 v15, v6, v14 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v6, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v15, v17, v15, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v14, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v15 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v6, v19, v15, vcc ; GFX8-NEXT: v_min_f16_e32 v14, v5, v13 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v5, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v14, v17, v14, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v13, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v14 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v5, v19, v14, vcc ; GFX8-NEXT: v_min_f16_e32 v13, v4, v12 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v4, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v12, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v19, v13, vcc ; GFX8-NEXT: v_min_f16_e32 v12, v3, v11 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v3, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v11, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v12 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v12, vcc ; GFX8-NEXT: v_min_f16_e32 v11, v2, v10 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v2, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v10, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v11 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v19, v11, vcc ; GFX8-NEXT: v_min_f16_e32 v10, v1, v9 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v9, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v19, v10, vcc ; GFX8-NEXT: v_min_f16_e32 v9, v0, v8 ; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v8 -; GFX8-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc -; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v8, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v9 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v19, v9, vcc ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v24 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v23 @@ -3168,9 +1862,9 @@ define <16 x half> @v_minimum_v16f16(<16 x half> %src0, <16 x half> %src1) { ; GFX8-NEXT: v_or_b32_sdwa v3, v3, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v20 ; GFX8-NEXT: v_or_b32_sdwa v4, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v19 -; GFX8-NEXT: v_or_b32_sdwa v5, v5, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v18 +; GFX8-NEXT: v_or_b32_sdwa v5, v5, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v17 ; GFX8-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v16 ; GFX8-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD @@ -3179,414 +1873,142 @@ define <16 x half> @v_minimum_v16f16(<16 x half> %src0, <16 x half> %src1) { ; GFX9-LABEL: v_minimum_v16f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_pk_min_f16 v18, v7, v15 +; GFX9-NEXT: v_pk_min_f16 v16, v7, v15 ; GFX9-NEXT: v_mov_b32_e32 v17, 0x7e00 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v7, v15 -; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v16, v7, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v15, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v15, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v16 -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX9-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v7, v15 -; GFX9-NEXT: v_cndmask_b32_e32 v18, v17, v18, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v18, v7, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v15, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v18, v7, vcc -; GFX9-NEXT: v_pk_min_f16 v18, v6, v14 +; GFX9-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc +; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v7, v15 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v7, v17, v16, vcc +; GFX9-NEXT: v_pk_min_f16 v15, v6, v14 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v6, v14 -; GFX9-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v15, v6, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v14, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v14, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v15 -; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v15, v15, v19, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v6, v14 -; GFX9-NEXT: v_cndmask_b32_e32 v18, v17, v18, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v14, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc -; GFX9-NEXT: v_pk_min_f16 v18, v5, v13 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v5, v13 -; GFX9-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v14, v5, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v13, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v13, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v14 -; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v19, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v15, vcc +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v6, v14 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v6, v17, v15, vcc +; GFX9-NEXT: v_pk_min_f16 v14, v5, v13 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v5, v13 -; GFX9-NEXT: v_cndmask_b32_e32 v18, v17, v18, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v18, v5, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v13, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v18, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v15, v17, v14, vcc +; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v5, v13 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v5, v17, v14, vcc ; GFX9-NEXT: v_pk_min_f16 v13, v4, v12 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v4, v12 -; GFX9-NEXT: v_cndmask_b32_e32 v18, v17, v13, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v18, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v12, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v12, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v14, v17, v13, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v4, v12 -; GFX9-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v12, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v4, v12 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v17, v13, vcc ; GFX9-NEXT: v_pk_min_f16 v12, v3, v11 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v11 ; GFX9-NEXT: v_cndmask_b32_e32 v13, v17, v12, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v13, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v11, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v11, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 -; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v13, v13, v19, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v11 -; GFX9-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v11, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v12 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v3, v11 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v12, vcc ; GFX9-NEXT: v_pk_min_f16 v11, v2, v10 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v2, v10 ; GFX9-NEXT: v_cndmask_b32_e32 v12, v17, v11, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v12, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v10, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v10, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v12 -; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v19, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v2, v10 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v10, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v11 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v2, v10 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v11, vcc ; GFX9-NEXT: v_pk_min_f16 v10, v1, v9 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v9 ; GFX9-NEXT: v_cndmask_b32_e32 v11, v17, v10, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v11, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v9, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v9, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v11 -; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v19, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v9 -; GFX9-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v9, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v9 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v10, vcc ; GFX9-NEXT: v_pk_min_f16 v9, v0, v8 ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v8 ; GFX9-NEXT: v_cndmask_b32_e32 v10, v17, v9, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v10, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v8, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v8, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v19, vcc ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v8 -; GFX9-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc -; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v8, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v9 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc +; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v8 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v9, vcc ; GFX9-NEXT: s_mov_b32 s4, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v0, v10, s4 ; GFX9-NEXT: v_perm_b32 v1, v1, v11, s4 ; GFX9-NEXT: v_perm_b32 v2, v2, v12, s4 ; GFX9-NEXT: v_perm_b32 v3, v3, v13, s4 -; GFX9-NEXT: v_perm_b32 v4, v4, v18, s4 -; GFX9-NEXT: v_perm_b32 v5, v5, v14, s4 -; GFX9-NEXT: v_perm_b32 v6, v6, v15, s4 -; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4 +; GFX9-NEXT: v_perm_b32 v4, v4, v14, s4 +; GFX9-NEXT: v_perm_b32 v5, v5, v15, s4 +; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4 +; GFX9-NEXT: v_perm_b32 v7, v7, v18, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_v16f16: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_pk_min_f16 v18, v7, v15 +; GFX940-NEXT: v_pk_min_f16 v16, v7, v15 ; GFX940-NEXT: v_mov_b32_e32 v17, 0x7e00 ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v7, v15 ; GFX940-NEXT: s_mov_b32 s0, 0x5040100 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v16, v7, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v15, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v15, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v16 -; GFX940-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GFX940-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc +; GFX940-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v7, v15 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX940-NEXT: v_pk_min_f16 v15, v6, v14 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v7, v15 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v18, v17, v18, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v7, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v18, v7, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v15, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v7, v18, v7, vcc -; GFX940-NEXT: v_pk_min_f16 v18, v6, v14 +; GFX940-NEXT: v_cndmask_b32_e32 v7, v17, v16, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v6, v14 -; GFX940-NEXT: v_perm_b32 v7, v7, v16, s0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX940-NEXT: v_perm_b32 v7, v7, v18, s0 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v15, v6, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v14, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v14, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v15 -; GFX940-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX940-NEXT: v_cndmask_b32_e32 v16, v17, v15, vcc +; GFX940-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v6, v14 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX940-NEXT: v_pk_min_f16 v14, v5, v13 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v15, v15, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v6, v14 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v18, v17, v18, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v6, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v14, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc -; GFX940-NEXT: v_pk_min_f16 v18, v5, v13 +; GFX940-NEXT: v_cndmask_b32_e32 v6, v17, v15, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v5, v13 -; GFX940-NEXT: v_perm_b32 v6, v6, v15, s0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v14, v5, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v13, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v13, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v14 -; GFX940-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GFX940-NEXT: v_perm_b32 v6, v6, v16, s0 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v14, v14, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v5, v13 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v18, v17, v18, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v5, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v18, v5, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v13, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 +; GFX940-NEXT: v_cndmask_b32_e32 v15, v17, v14, vcc +; GFX940-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v5, v13 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_min_f16 v13, v4, v12 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v18, v5, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v5, v17, v14, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v4, v12 -; GFX940-NEXT: v_perm_b32 v5, v5, v14, s0 +; GFX940-NEXT: v_perm_b32 v5, v5, v15, s0 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v18, v17, v13, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 +; GFX940-NEXT: v_cndmask_b32_e32 v14, v17, v13, vcc ; GFX940-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v18, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v12, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v12, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v18 -; GFX940-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v4, v12 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v4, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v12, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v4, v12 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_min_f16 v12, v3, v11 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v4, v17, v13, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v3, v11 -; GFX940-NEXT: v_perm_b32 v4, v4, v18, s0 +; GFX940-NEXT: v_perm_b32 v4, v4, v14, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v13, v17, v12, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 ; GFX940-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v13, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v11, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v11, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v13 -; GFX940-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v13, v13, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v3, v11 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v3, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v11, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v12 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v3, v11 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_min_f16 v11, v2, v10 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v3, v17, v12, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v2, v10 ; GFX940-NEXT: v_perm_b32 v3, v3, v13, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v12, v17, v11, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 ; GFX940-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v12, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v10, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v10, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v12 -; GFX940-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v12, v12, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v2, v10 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v2, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v10, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v11 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v2, v10 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_min_f16 v10, v1, v9 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v2, v17, v11, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v1, v9 ; GFX940-NEXT: v_perm_b32 v2, v2, v12, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v11, v17, v10, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 ; GFX940-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v11, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v9, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v9, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v11 -; GFX940-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v11, v11, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v1, v9 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v9, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v1, v9 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: v_pk_min_f16 v9, v0, v8 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v1, v17, v10, vcc ; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v8 ; GFX940-NEXT: v_perm_b32 v1, v1, v11, s0 ; GFX940-NEXT: s_nop 0 ; GFX940-NEXT: v_cndmask_b32_e32 v10, v17, v9, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 ; GFX940-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v10, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v8, 32 -; GFX940-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v19, v19, v8, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v10 -; GFX940-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v10, v10, v19, vcc -; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v8 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc -; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v8, 32 +; GFX940-NEXT: v_cmp_o_f16_sdwa vcc, v0, v8 src0_sel:WORD_1 src1_sel:WORD_1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc -; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v9 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v17, v9, vcc ; GFX940-NEXT: v_perm_b32 v0, v0, v10, s0 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; @@ -3595,353 +2017,145 @@ define <16 x half> @v_minimum_v16f16(<16 x half> %src0, <16 x half> %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_min_f16 v16, v7, v15 ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v7, v15 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v14 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v6 -; GFX10-NEXT: v_cndmask_b32_e32 v17, 0x7e00, v16, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v17, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v15, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v15, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v17 -; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v7, v15 ; GFX10-NEXT: v_pk_min_f16 v18, v6, v14 +; GFX10-NEXT: v_pk_min_f16 v19, v3, v11 +; GFX10-NEXT: v_pk_min_f16 v20, v2, v10 +; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v16 ; GFX10-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v16, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v7, v15 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v18 +; GFX10-NEXT: v_pk_min_f16 v21, v0, v8 +; GFX10-NEXT: v_cndmask_b32_e32 v7, 0x7e00, v17, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v14 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v18 +; GFX10-NEXT: v_pk_min_f16 v17, v5, v13 +; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v21 +; GFX10-NEXT: v_perm_b32 v7, v7, v16, 0x5040100 ; GFX10-NEXT: v_cndmask_b32_e32 v18, 0x7e00, v18, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v20, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v21, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v15, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v20, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v21, v20, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v14, 32 -; GFX10-NEXT: v_pk_min_f16 v20, v4, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v19, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v13 -; GFX10-NEXT: v_perm_b32 v7, v7, v17, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v15, v19, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v18 -; GFX10-NEXT: v_pk_min_f16 v15, v5, v13 -; GFX10-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v5 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v15 -; GFX10-NEXT: v_cndmask_b32_e32 v14, v21, v14, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v6, v14 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v17 +; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v15, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v5, v13 -; GFX10-NEXT: v_perm_b32 v6, v14, v6, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v15, 0x7e00, v15, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v18, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v19, 0x7e00, v19, vcc_lo +; GFX10-NEXT: v_perm_b32 v6, v6, v18, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v15, 0x7e00, v17, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v5, v13 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_pk_min_f16 v17, v4, v12 +; GFX10-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v14, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v20, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v18, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v21, v4, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v13, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v16, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v18, v16, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v12, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v22, v12, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v15 -; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v13, v19, v13, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v11 -; GFX10-NEXT: v_perm_b32 v5, v13, v5, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v15, v21, v16, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v12 -; GFX10-NEXT: v_pk_min_f16 v16, v3, v11 -; GFX10-NEXT: v_cndmask_b32_e32 v18, 0x7e00, v18, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v17 +; GFX10-NEXT: v_perm_b32 v5, v5, v15, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v13, 0x7e00, v17, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v11 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v16 -; GFX10-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v16, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v20, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v21, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v18, v4, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v20, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v12, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v11, 32 -; GFX10-NEXT: v_pk_min_f16 v12, v2, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v19, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v20, v19, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v16 -; GFX10-NEXT: v_pk_min_f16 v19, v1, v9 -; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v10 -; GFX10-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v11, v21, v11, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v19 +; GFX10-NEXT: v_cndmask_b32_e32 v19, 0x7e00, v19, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v3, v11 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_pk_min_f16 v11, v1, v9 +; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v17, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v10 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v2 -; GFX10-NEXT: v_perm_b32 v3, v11, v3, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v12, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v11 +; GFX10-NEXT: v_perm_b32 v3, v3, v19, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v17, 0x7e00, v20, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v9 -; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX10-NEXT: v_cndmask_b32_e32 v22, 0x7e00, v19, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v21, v20 -; GFX10-NEXT: v_cndmask_b32_e32 v12, 0x7e00, v12, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v23, v22, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 32 -; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v21, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v12, v21, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v21, v23, v9, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v16 -; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX10-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v20, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v20, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v22 -; GFX10-NEXT: v_pk_min_f16 v20, v0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v16, v22, v21, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v9 -; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v8 -; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v20 -; GFX10-NEXT: v_cndmask_b32_e32 v19, 0x7e00, v19, vcc_lo +; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX10-NEXT: v_cndmask_b32_e32 v11, 0x7e00, v11, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v1, v9 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v22, vcc_lo ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v8 -; GFX10-NEXT: v_cndmask_b32_e32 v20, 0x7e00, v20, vcc_lo -; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v22, v21 -; GFX10-NEXT: v_cndmask_b32_e32 v23, 0x7e00, v23, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v20, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v22, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v8, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo -; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v21, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v22, v21, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v19 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v20 -; GFX10-NEXT: v_perm_b32 v1, v1, v16, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v20, v0, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v23 -; GFX10-NEXT: v_cndmask_b32_e32 v8, v23, v8, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12 -; GFX10-NEXT: v_perm_b32 v0, v8, v0, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v9, v12, v10, vcc_lo -; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v18 -; GFX10-NEXT: v_perm_b32 v2, v9, v2, 0x5040100 -; GFX10-NEXT: v_cndmask_b32_e32 v4, v18, v4, vcc_lo -; GFX10-NEXT: v_perm_b32 v4, v4, v15, 0x5040100 +; GFX10-NEXT: v_perm_b32 v1, v1, v11, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v21, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v8 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v23, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v2, v10 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_perm_b32 v0, v0, v9, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v20, vcc_lo +; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v4, v12 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-NEXT: v_perm_b32 v2, v2, v17, 0x5040100 +; GFX10-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v14, vcc_lo +; GFX10-NEXT: v_perm_b32 v4, v4, v13, 0x5040100 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_v16f16: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_pk_min_f16 v16, v7, v15 +; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v15 +; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v7 ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v7, v15 -; GFX11-NEXT: v_lshrrev_b32_e32 v20, 16, v6 -; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v14 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e32 v17, 0x7e00, v16, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GFX11-NEXT: v_cndmask_b32_e32 v18, v17, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v15, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e32 v18, v18, v15, vcc_lo -; GFX11-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v17 -; GFX11-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v7, v15 -; GFX11-NEXT: v_pk_min_f16 v18, v6, v14 -; GFX11-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v16, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v14 -; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v18 -; GFX11-NEXT: v_cndmask_b32_e32 v18, 0x7e00, v18, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v7, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v20, v19 -; GFX11-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v21, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v6, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v15, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v20, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v15, v21, v20, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v14, 32 +; GFX11-NEXT: v_pk_min_f16 v15, v6, v14 +; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v16 ; GFX11-NEXT: v_pk_min_f16 v20, v4, v12 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v16 -; GFX11-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v19, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v13 -; GFX11-NEXT: v_cndmask_b32_e32 v14, v15, v19, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v18 -; GFX11-NEXT: v_pk_min_f16 v15, v5, v13 -; GFX11-NEXT: v_cndmask_b32_e32 v6, v18, v6, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v21 -; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_pk_min_f16 v22, v2, v10 +; GFX11-NEXT: v_cndmask_b32_e32 v7, 0x7e00, v16, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v18, v17 +; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v14 +; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v6 +; GFX11-NEXT: v_lshrrev_b32_e32 v23, 16, v8 +; GFX11-NEXT: v_lshrrev_b32_e32 v24, 16, v0 +; GFX11-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v19, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v14 ; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v15 -; GFX11-NEXT: v_perm_b32 v7, v7, v17, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v14, v21, v14, vcc_lo +; GFX11-NEXT: v_pk_min_f16 v14, v5, v13 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_perm_b32 v7, v16, v7, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v15, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v18, v17 +; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v13 +; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v5 +; GFX11-NEXT: v_cndmask_b32_e32 v15, 0x7e00, v19, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v5, v13 -; GFX11-NEXT: v_cndmask_b32_e32 v15, 0x7e00, v15, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v18, v16 -; GFX11-NEXT: v_cndmask_b32_e32 v19, 0x7e00, v19, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v14 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: v_perm_b32 v6, v15, v6, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v14, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v18, v17 +; GFX11-NEXT: v_pk_min_f16 v17, v3, v11 +; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v20 +; GFX11-NEXT: v_cndmask_b32_e32 v13, 0x7e00, v19, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v12 -; GFX11-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v20, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v5, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v18, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v22, v21, v4, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v13, 32 +; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v11 +; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v17 +; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v12 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v16, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v13, v18, v16, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v12, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v20 +; GFX11-NEXT: v_cndmask_b32_e32 v14, 0x7e00, v20, vcc_lo ; GFX11-NEXT: v_lshrrev_b32_e32 v20, 16, v3 -; GFX11-NEXT: v_perm_b32 v6, v14, v6, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v16, v22, v12, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v15 -; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX11-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v19 -; GFX11-NEXT: v_cndmask_b32_e32 v13, v19, v13, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v21 -; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v11 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-NEXT: v_perm_b32 v5, v13, v5, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v15, v21, v16, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v12 -; GFX11-NEXT: v_pk_min_f16 v16, v3, v11 -; GFX11-NEXT: v_cndmask_b32_e32 v18, 0x7e00, v18, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v11 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v16 -; GFX11-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v16, vcc_lo +; GFX11-NEXT: v_perm_b32 v5, v13, v5, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v17, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v20, v19 -; GFX11-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v21, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v4, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v18, v4, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v3, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v20, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v12, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v11, 32 -; GFX11-NEXT: v_pk_min_f16 v12, v2, v10 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v19, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v11, v20, v19, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v16 -; GFX11-NEXT: v_lshrrev_b32_e32 v20, 16, v10 ; GFX11-NEXT: v_pk_min_f16 v19, v1, v9 -; GFX11-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v21 -; GFX11-NEXT: v_cndmask_b32_e32 v11, v21, v11, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v20, 16, v22 +; GFX11-NEXT: v_cndmask_b32_e32 v11, 0x7e00, v21, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v10 -; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v16, 0x7e00, v12, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_perm_b32 v3, v11, v3, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v17, 0x7e00, v22, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v9 -; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; GFX11-NEXT: v_cndmask_b32_e32 v22, 0x7e00, v19, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v2, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v21, v20 -; GFX11-NEXT: v_cndmask_b32_e32 v12, 0x7e00, v12, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v23, v22, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v10, 32 -; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v21, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v10, v12, v21, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v21, v23, v9, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v16 ; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX11-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v20, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v20, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v22 -; GFX11-NEXT: v_pk_min_f16 v20, v0, v8 -; GFX11-NEXT: v_perm_b32 v3, v11, v3, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v16, v22, v21, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX11-NEXT: v_pk_min_f16 v22, v0, v8 +; GFX11-NEXT: v_cndmask_b32_e32 v21, 0x7e00, v19, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v9 -; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v8 -; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v0 -; GFX11-NEXT: v_lshrrev_b32_e32 v23, 16, v20 -; GFX11-NEXT: v_cndmask_b32_e32 v19, 0x7e00, v19, vcc_lo +; GFX11-NEXT: v_lshrrev_b32_e32 v25, 16, v22 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v19, vcc_lo ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v8 -; GFX11-NEXT: v_cndmask_b32_e32 v20, 0x7e00, v20, vcc_lo -; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v22, v21 -; GFX11-NEXT: v_cndmask_b32_e32 v23, 0x7e00, v23, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v20, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v22, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v9, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v8, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo -; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v21, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v8, v22, v21, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v19 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v20 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v20, v0, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v23 -; GFX11-NEXT: v_cndmask_b32_e32 v8, v23, v8, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_perm_b32 v1, v1, v21, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v22, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v24, v23 +; GFX11-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v25, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v10 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_perm_b32 v0, v8, v0, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v9, v12, v10, vcc_lo -; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v18 -; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x5040100 -; GFX11-NEXT: v_perm_b32 v2, v9, v2, 0x5040100 -; GFX11-NEXT: v_cndmask_b32_e32 v4, v18, v4, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v20, vcc_lo +; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v12 +; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x5040100 +; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v18, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_perm_b32 v4, v4, v15, 0x5040100 +; GFX11-NEXT: v_perm_b32 v4, v4, v14, 0x5040100 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_v16f16: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll index 0a9dc3d05676..1da2647fbd60 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll @@ -14,13 +14,7 @@ define float @v_minimum_f32(float %src0, float %src1) { ; GFX7-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX7-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_minimum_f32: @@ -29,13 +23,7 @@ define float @v_minimum_f32(float %src0, float %src1) { ; GFX8-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_f32: @@ -44,13 +32,7 @@ define float @v_minimum_f32(float %src0, float %src1) { ; GFX9-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_f32: @@ -60,16 +42,7 @@ define float @v_minimum_f32(float %src0, float %src1) { ; GFX940-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX940-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_f32: @@ -77,13 +50,7 @@ define float @v_minimum_f32(float %src0, float %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_f32: @@ -91,15 +58,8 @@ define float @v_minimum_f32(float %src0, float %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_f32: @@ -119,78 +79,37 @@ define float @v_minimum_f32__nnan(float %src0, float %src1) { ; GFX7-LABEL: v_minimum_f32__nnan: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_min_f32_e32 v2, v0, v1 -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_min_f32_e32 v0, v0, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_minimum_f32__nnan: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_min_f32_e32 v2, v0, v1 -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_min_f32_e32 v0, v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_f32__nnan: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_min_f32_e32 v2, v0, v1 -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_min_f32_e32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_f32__nnan: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_min_f32_e32 v2, v0, v1 -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_min_f32_e32 v0, v0, v1 ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_f32__nnan: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_min_f32_e32 v2, v0, v1 -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_min_f32_e32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_f32__nnan: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_min_f32_e32 v2, v0, v1 -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: v_min_f32_e32 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_f32__nnan: @@ -332,13 +251,7 @@ define float @v_minimum_f32__nnan_src0(float %arg0, float %src1) { ; GFX7-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX7-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_minimum_f32__nnan_src0: @@ -348,13 +261,7 @@ define float @v_minimum_f32__nnan_src0(float %arg0, float %src1) { ; GFX8-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_f32__nnan_src0: @@ -364,13 +271,7 @@ define float @v_minimum_f32__nnan_src0(float %arg0, float %src1) { ; GFX9-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_f32__nnan_src0: @@ -381,16 +282,7 @@ define float @v_minimum_f32__nnan_src0(float %arg0, float %src1) { ; GFX940-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX940-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_f32__nnan_src0: @@ -399,13 +291,7 @@ define float @v_minimum_f32__nnan_src0(float %arg0, float %src1) { ; GFX10-NEXT: v_add_f32_e32 v0, 1.0, v0 ; GFX10-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_f32__nnan_src0: @@ -415,15 +301,7 @@ define float @v_minimum_f32__nnan_src0(float %arg0, float %src1) { ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_f32__nnan_src0: @@ -450,13 +328,7 @@ define float @v_minimum_f32__nnan_src1(float %src0, float %arg1) { ; GFX7-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX7-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_minimum_f32__nnan_src1: @@ -466,13 +338,7 @@ define float @v_minimum_f32__nnan_src1(float %src0, float %arg1) { ; GFX8-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_f32__nnan_src1: @@ -482,13 +348,7 @@ define float @v_minimum_f32__nnan_src1(float %src0, float %arg1) { ; GFX9-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_f32__nnan_src1: @@ -499,16 +359,7 @@ define float @v_minimum_f32__nnan_src1(float %src0, float %arg1) { ; GFX940-NEXT: v_mov_b32_e32 v3, 0x7fc00000 ; GFX940-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, v1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX940-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_f32__nnan_src1: @@ -517,13 +368,7 @@ define float @v_minimum_f32__nnan_src1(float %src0, float %arg1) { ; GFX10-NEXT: v_add_f32_e32 v1, 1.0, v1 ; GFX10-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 32 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_f32__nnan_src1: @@ -533,15 +378,7 @@ define float @v_minimum_f32__nnan_src1(float %src0, float %arg1) { ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo -; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v1, 32 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_f32__nnan_src1: @@ -568,14 +405,7 @@ define void @s_minimum_f32(float inreg %src0, float inreg %src1) { ; GFX7-NEXT: v_min_f32_e32 v1, s4, v0 ; GFX7-NEXT: v_mov_b32_e32 v2, 0x7fc00000 ; GFX7-NEXT: v_cmp_o_f32_e32 vcc, s4, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX7-NEXT: v_mov_b32_e32 v2, s4 -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, s4, 32 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX7-NEXT: v_cmp_class_f32_e64 vcc, s5, 32 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX7-NEXT: ;;#ASMSTART ; GFX7-NEXT: ; use v0 ; GFX7-NEXT: ;;#ASMEND @@ -588,14 +418,7 @@ define void @s_minimum_f32(float inreg %src0, float inreg %src1) { ; GFX8-NEXT: v_min_f32_e32 v1, s4, v0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000 ; GFX8-NEXT: v_cmp_o_f32_e32 vcc, s4, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX8-NEXT: v_mov_b32_e32 v2, s4 -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, s4, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX8-NEXT: v_cmp_class_f32_e64 vcc, s5, 32 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use v0 ; GFX8-NEXT: ;;#ASMEND @@ -608,14 +431,7 @@ define void @s_minimum_f32(float inreg %src0, float inreg %src1) { ; GFX9-NEXT: v_min_f32_e32 v1, s4, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000 ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s4, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX9-NEXT: v_mov_b32_e32 v2, s4 -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, s4, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX9-NEXT: v_cmp_class_f32_e64 vcc, s5, 32 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; use v0 ; GFX9-NEXT: ;;#ASMEND @@ -629,17 +445,7 @@ define void @s_minimum_f32(float inreg %src0, float inreg %src1) { ; GFX940-NEXT: v_mov_b32_e32 v2, 0x7fc00000 ; GFX940-NEXT: v_cmp_o_f32_e32 vcc, s0, v0 ; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX940-NEXT: v_mov_b32_e32 v2, s0 -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, s0, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc -; GFX940-NEXT: v_cmp_class_f32_e64 vcc, s1, 32 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GFX940-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1 -; GFX940-NEXT: s_nop 1 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX940-NEXT: ;;#ASMSTART ; GFX940-NEXT: ; use v0 ; GFX940-NEXT: ;;#ASMEND @@ -650,13 +456,7 @@ define void @s_minimum_f32(float inreg %src0, float inreg %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_min_f32_e64 v0, s4, s5 ; GFX10-NEXT: v_cmp_o_f32_e64 vcc_lo, s4, s5 -; GFX10-NEXT: v_cmp_class_f32_e64 s6, s4, 32 ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v1, v0, s4, s6 -; GFX10-NEXT: v_cmp_class_f32_e64 s4, s5, 32 -; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s5, s4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use v0 ; GFX10-NEXT: ;;#ASMEND @@ -667,15 +467,8 @@ define void @s_minimum_f32(float inreg %src0, float inreg %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_min_f32_e64 v0, s0, s1 ; GFX11-NEXT: v_cmp_o_f32_e64 vcc_lo, s0, s1 -; GFX11-NEXT: v_cmp_class_f32_e64 s2, s0, 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v0, s0, s2 -; GFX11-NEXT: v_cmp_class_f32_e64 s0, s1, 32 -; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s1, s0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use v0 ; GFX11-NEXT: ;;#ASMEND diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll index 2387cd9bc7a9..7013c60bada5 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll @@ -13,18 +13,9 @@ define double @v_minimum_f64(double %src0, double %src1) { ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000 -; GFX7-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 32 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX7-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX7-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_minimum_f64: @@ -32,18 +23,9 @@ define double @v_minimum_f64(double %src0, double %src1) { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000 -; GFX8-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 32 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX8-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX8-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_f64: @@ -51,39 +33,20 @@ define double @v_minimum_f64(double %src0, double %src1) { ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000 -; GFX9-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 32 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX9-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX9-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_f64: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX940-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] -; GFX940-NEXT: v_mov_b32_e32 v6, 0x7ff80000 ; GFX940-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX940-NEXT: v_cmp_class_f64_e64 s[0:1], v[2:3], 32 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX940-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX940-NEXT: v_cmp_eq_f64_e64 s[2:3], 0, v[4:5] +; GFX940-NEXT: v_mov_b32_e32 v1, 0x7ff80000 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[2:3] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[2:3] ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_f64: @@ -91,17 +54,8 @@ define double @v_minimum_f64(double %src0, double %src1) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3] -; GFX10-NEXT: v_cmp_class_f64_e64 s4, v[2:3], 32 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo -; GFX10-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 32 -; GFX10-NEXT: v_cmp_eq_f64_e64 s5, 0, v[4:5] -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_f64: @@ -109,20 +63,9 @@ define double @v_minimum_f64(double %src0, double %src1) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3] -; GFX11-NEXT: v_cmp_class_f64_e64 s0, v[2:3], 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo -; GFX11-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cmp_eq_f64_e64 s1, 0, v[4:5] -; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v0, s1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, v1, s1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_f64: @@ -142,93 +85,37 @@ define double @v_minimum_f64__nnan(double %src0, double %src1) { ; GFX7-LABEL: v_minimum_f64__nnan: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] -; GFX7-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX7-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 32 -; GFX7-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] +; GFX7-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_minimum_f64__nnan: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] -; GFX8-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX8-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 32 -; GFX8-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] +; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_f64__nnan: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] -; GFX9-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX9-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 32 -; GFX9-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] +; GFX9-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_f64__nnan: ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX940-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] -; GFX940-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX940-NEXT: v_cmp_class_f64_e64 s[0:1], v[2:3], 32 -; GFX940-NEXT: v_cmp_eq_f64_e64 s[2:3], 0, v[4:5] -; GFX940-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[2:3] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[2:3] +; GFX940-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_f64__nnan: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] -; GFX10-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 32 -; GFX10-NEXT: v_cmp_class_f64_e64 s4, v[2:3], 32 -; GFX10-NEXT: v_cmp_eq_f64_e64 s5, 0, v[4:5] -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s5 +; GFX10-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_f64__nnan: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] -; GFX11-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 32 -; GFX11-NEXT: v_cmp_class_f64_e64 s0, v[2:3], 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cmp_eq_f64_e64 s1, 0, v[4:5] -; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v0, s1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, v1, s1 +; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_f64__nnan: @@ -373,60 +260,33 @@ define double @v_minimum_f64__nnan_src0(double %arg0, double %src1) { ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000 -; GFX7-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 32 ; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX7-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX7-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_minimum_f64__nnan_src0: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000 -; GFX8-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 32 ; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX8-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX8-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_f64__nnan_src0: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000 -; GFX9-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 32 ; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX9-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX9-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_f64__nnan_src0: @@ -434,62 +294,33 @@ define double @v_minimum_f64__nnan_src0(double %arg0, double %src1) { ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX940-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 ; GFX940-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] -; GFX940-NEXT: v_mov_b32_e32 v6, 0x7ff80000 ; GFX940-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX940-NEXT: v_cmp_class_f64_e64 s[0:1], v[2:3], 32 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX940-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX940-NEXT: v_cmp_eq_f64_e64 s[2:3], 0, v[4:5] +; GFX940-NEXT: v_mov_b32_e32 v1, 0x7ff80000 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[2:3] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[2:3] ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_f64__nnan_src0: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; GFX10-NEXT: v_cmp_class_f64_e64 s4, v[2:3], 32 ; GFX10-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3] -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo -; GFX10-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 32 -; GFX10-NEXT: v_cmp_eq_f64_e64 s5, 0, v[4:5] -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_f64__nnan_src0: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; GFX11-NEXT: v_cmp_class_f64_e64 s0, v[2:3], 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3] -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo -; GFX11-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 32 -; GFX11-NEXT: v_cmp_eq_f64_e64 s1, 0, v[4:5] -; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v0, s1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, v1, s1 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_f64__nnan_src0: @@ -513,60 +344,33 @@ define double @v_minimum_f64__nnan_src1(double %src0, double %arg1) { ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 -; GFX7-NEXT: v_mov_b32_e32 v6, 0x7ff80000 ; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX7-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 32 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX7-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX7-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX7-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX7-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_minimum_f64__nnan_src1: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 -; GFX8-NEXT: v_mov_b32_e32 v6, 0x7ff80000 ; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX8-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 32 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX8-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX8-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimum_f64__nnan_src1: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 -; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000 ; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX9-NEXT: v_cmp_class_f64_e64 s[4:5], v[2:3], 32 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX9-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX9-NEXT: v_cmp_eq_f64_e64 s[6:7], 0, v[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[6:7] -; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[6:7] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX940-LABEL: v_minimum_f64__nnan_src1: @@ -574,21 +378,11 @@ define double @v_minimum_f64__nnan_src1(double %src0, double %arg1) { ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX940-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 ; GFX940-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] -; GFX940-NEXT: v_mov_b32_e32 v6, 0x7ff80000 ; GFX940-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] -; GFX940-NEXT: v_cmp_class_f64_e64 s[0:1], v[2:3], 32 -; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc -; GFX940-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 32 -; GFX940-NEXT: v_cmp_eq_f64_e64 s[2:3], 0, v[4:5] +; GFX940-NEXT: v_mov_b32_e32 v1, 0x7ff80000 ; GFX940-NEXT: s_nop 0 -; GFX940-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc ; GFX940-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc -; GFX940-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GFX940-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[2:3] -; GFX940-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[2:3] ; GFX940-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_minimum_f64__nnan_src1: @@ -597,39 +391,20 @@ define double @v_minimum_f64__nnan_src1(double %src0, double %arg1) { ; GFX10-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 ; GFX10-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3] -; GFX10-NEXT: v_cmp_class_f64_e64 s4, v[2:3], 32 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo -; GFX10-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 32 -; GFX10-NEXT: v_cmp_eq_f64_e64 s5, 0, v[4:5] -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s5 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s5 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_minimum_f64__nnan_src1: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3] ; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3] -; GFX11-NEXT: v_cmp_class_f64_e64 s0, v[2:3], 32 -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc_lo -; GFX11-NEXT: v_cmp_class_f64_e64 vcc_lo, v[0:1], 32 -; GFX11-NEXT: v_cmp_eq_f64_e64 s1, 0, v[4:5] -; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v0, s1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, v1, s1 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: v_minimum_f64__nnan_src1: @@ -654,30 +429,13 @@ define void @s_minimum_f64(double inreg %src0, double inreg %src1) { ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_mov_b32_e32 v0, s6 ; GFX7-NEXT: v_mov_b32_e32 v1, s7 -; GFX7-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[0:1] ; GFX7-NEXT: v_min_f64 v[2:3], s[4:5], v[0:1] -; GFX7-NEXT: v_cmp_class_f64_e64 s[8:9], s[4:5], 32 -; GFX7-NEXT: s_and_b64 s[10:11], vcc, exec -; GFX7-NEXT: v_readfirstlane_b32 s12, v3 -; GFX7-NEXT: v_readfirstlane_b32 s10, v2 -; GFX7-NEXT: s_cselect_b32 s11, 0x7ff80000, s12 -; GFX7-NEXT: v_cmp_class_f64_e64 s[12:13], s[6:7], 32 -; GFX7-NEXT: s_cselect_b32 s10, 0, s10 -; GFX7-NEXT: v_cmp_eq_f64_e64 s[14:15], s[10:11], 0 -; GFX7-NEXT: s_and_b64 s[16:17], s[8:9], exec -; GFX7-NEXT: s_cselect_b32 s5, s5, s11 -; GFX7-NEXT: s_and_b64 s[16:17], s[12:13], exec -; GFX7-NEXT: s_cselect_b32 s5, s7, s5 -; GFX7-NEXT: s_and_b64 s[16:17], s[14:15], exec -; GFX7-NEXT: s_cselect_b32 s5, s5, s11 -; GFX7-NEXT: s_and_b64 s[8:9], s[8:9], exec -; GFX7-NEXT: s_cselect_b32 s4, s4, s10 -; GFX7-NEXT: s_and_b64 s[8:9], s[12:13], exec -; GFX7-NEXT: s_cselect_b32 s4, s6, s4 -; GFX7-NEXT: s_and_b64 s[6:7], s[14:15], exec -; GFX7-NEXT: s_cselect_b32 s4, s4, s10 +; GFX7-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[0:1] +; GFX7-NEXT: v_mov_b32_e32 v4, 0x7ff80000 +; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc ; GFX7-NEXT: ;;#ASMSTART -; GFX7-NEXT: ; use s[4:5] +; GFX7-NEXT: ; use v[0:1] ; GFX7-NEXT: ;;#ASMEND ; GFX7-NEXT: s_setpc_b64 s[30:31] ; @@ -686,30 +444,13 @@ define void @s_minimum_f64(double inreg %src0, double inreg %src1) { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v1, s7 -; GFX8-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[0:1] ; GFX8-NEXT: v_min_f64 v[2:3], s[4:5], v[0:1] -; GFX8-NEXT: v_cmp_class_f64_e64 s[8:9], s[4:5], 32 -; GFX8-NEXT: s_and_b64 s[10:11], vcc, exec -; GFX8-NEXT: v_readfirstlane_b32 s12, v3 -; GFX8-NEXT: v_readfirstlane_b32 s10, v2 -; GFX8-NEXT: s_cselect_b32 s11, 0x7ff80000, s12 -; GFX8-NEXT: v_cmp_class_f64_e64 s[12:13], s[6:7], 32 -; GFX8-NEXT: s_cselect_b32 s10, 0, s10 -; GFX8-NEXT: v_cmp_eq_f64_e64 s[14:15], s[10:11], 0 -; GFX8-NEXT: s_and_b64 s[16:17], s[8:9], exec -; GFX8-NEXT: s_cselect_b32 s5, s5, s11 -; GFX8-NEXT: s_and_b64 s[16:17], s[12:13], exec -; GFX8-NEXT: s_cselect_b32 s5, s7, s5 -; GFX8-NEXT: s_and_b64 s[16:17], s[14:15], exec -; GFX8-NEXT: s_cselect_b32 s5, s5, s11 -; GFX8-NEXT: s_and_b64 s[8:9], s[8:9], exec -; GFX8-NEXT: s_cselect_b32 s4, s4, s10 -; GFX8-NEXT: s_and_b64 s[8:9], s[12:13], exec -; GFX8-NEXT: s_cselect_b32 s4, s6, s4 -; GFX8-NEXT: s_and_b64 s[6:7], s[14:15], exec -; GFX8-NEXT: s_cselect_b32 s4, s4, s10 +; GFX8-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v4, 0x7ff80000 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc ; GFX8-NEXT: ;;#ASMSTART -; GFX8-NEXT: ; use s[4:5] +; GFX8-NEXT: ; use v[0:1] ; GFX8-NEXT: ;;#ASMEND ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -718,30 +459,13 @@ define void @s_minimum_f64(double inreg %src0, double inreg %src1) { ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s7 -; GFX9-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[0:1] ; GFX9-NEXT: v_min_f64 v[2:3], s[4:5], v[0:1] -; GFX9-NEXT: v_cmp_class_f64_e64 s[8:9], s[4:5], 32 -; GFX9-NEXT: s_and_b64 s[10:11], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s12, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v2 -; GFX9-NEXT: s_cselect_b32 s11, 0x7ff80000, s12 -; GFX9-NEXT: v_cmp_class_f64_e64 s[12:13], s[6:7], 32 -; GFX9-NEXT: s_cselect_b32 s10, 0, s10 -; GFX9-NEXT: v_cmp_eq_f64_e64 s[14:15], s[10:11], 0 -; GFX9-NEXT: s_and_b64 s[16:17], s[8:9], exec -; GFX9-NEXT: s_cselect_b32 s5, s5, s11 -; GFX9-NEXT: s_and_b64 s[16:17], s[12:13], exec -; GFX9-NEXT: s_cselect_b32 s5, s7, s5 -; GFX9-NEXT: s_and_b64 s[16:17], s[14:15], exec -; GFX9-NEXT: s_cselect_b32 s5, s5, s11 -; GFX9-NEXT: s_and_b64 s[8:9], s[8:9], exec -; GFX9-NEXT: s_cselect_b32 s4, s4, s10 -; GFX9-NEXT: s_and_b64 s[8:9], s[12:13], exec -; GFX9-NEXT: s_cselect_b32 s4, s6, s4 -; GFX9-NEXT: s_and_b64 s[6:7], s[14:15], exec -; GFX9-NEXT: s_cselect_b32 s4, s4, s10 +; GFX9-NEXT: v_cmp_u_f64_e32 vcc, s[4:5], v[0:1] +; GFX9-NEXT: v_mov_b32_e32 v4, 0x7ff80000 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc ; GFX9-NEXT: ;;#ASMSTART -; GFX9-NEXT: ; use s[4:5] +; GFX9-NEXT: ; use v[0:1] ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -749,30 +473,14 @@ define void @s_minimum_f64(double inreg %src0, double inreg %src1) { ; GFX940: ; %bb.0: ; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX940-NEXT: v_mov_b64_e32 v[0:1], s[2:3] +; GFX940-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1] +; GFX940-NEXT: v_mov_b32_e32 v4, 0x7ff80000 ; GFX940-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1] -; GFX940-NEXT: v_min_f64 v[0:1], s[0:1], v[0:1] -; GFX940-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX940-NEXT: v_readfirstlane_b32 s6, v1 -; GFX940-NEXT: v_readfirstlane_b32 s4, v0 -; GFX940-NEXT: v_cmp_class_f64_e64 s[8:9], s[0:1], 32 -; GFX940-NEXT: s_cselect_b32 s5, 0x7ff80000, s6 -; GFX940-NEXT: s_cselect_b32 s4, 0, s4 -; GFX940-NEXT: s_and_b64 s[10:11], s[8:9], exec -; GFX940-NEXT: v_cmp_class_f64_e64 s[10:11], s[2:3], 32 -; GFX940-NEXT: v_cmp_eq_f64_e64 s[6:7], s[4:5], 0 -; GFX940-NEXT: s_cselect_b32 s1, s1, s5 -; GFX940-NEXT: s_and_b64 s[12:13], s[10:11], exec -; GFX940-NEXT: s_cselect_b32 s1, s3, s1 -; GFX940-NEXT: s_and_b64 s[12:13], s[6:7], exec -; GFX940-NEXT: s_cselect_b32 s1, s1, s5 -; GFX940-NEXT: s_and_b64 s[8:9], s[8:9], exec -; GFX940-NEXT: s_cselect_b32 s0, s0, s4 -; GFX940-NEXT: s_and_b64 s[8:9], s[10:11], exec -; GFX940-NEXT: s_cselect_b32 s0, s2, s0 -; GFX940-NEXT: s_and_b64 s[2:3], s[6:7], exec -; GFX940-NEXT: s_cselect_b32 s0, s0, s4 +; GFX940-NEXT: s_nop 1 +; GFX940-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX940-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc ; GFX940-NEXT: ;;#ASMSTART -; GFX940-NEXT: ; use s[0:1] +; GFX940-NEXT: ; use v[0:1] ; GFX940-NEXT: ;;#ASMEND ; GFX940-NEXT: s_setpc_b64 s[30:31] ; @@ -780,29 +488,11 @@ define void @s_minimum_f64(double inreg %src0, double inreg %src1) { ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_min_f64 v[0:1], s[4:5], s[6:7] -; GFX10-NEXT: v_cmp_u_f64_e64 s8, s[4:5], s[6:7] -; GFX10-NEXT: v_cmp_class_f64_e64 s11, s[4:5], 32 -; GFX10-NEXT: v_cmp_class_f64_e64 s12, s[6:7], 32 -; GFX10-NEXT: v_readfirstlane_b32 s9, v1 -; GFX10-NEXT: v_readfirstlane_b32 s10, v0 -; GFX10-NEXT: s_and_b32 s8, s8, exec_lo -; GFX10-NEXT: s_cselect_b32 s9, 0x7ff80000, s9 -; GFX10-NEXT: s_cselect_b32 s8, 0, s10 -; GFX10-NEXT: s_and_b32 s13, s11, exec_lo -; GFX10-NEXT: v_cmp_eq_f64_e64 s10, s[8:9], 0 -; GFX10-NEXT: s_cselect_b32 s5, s5, s9 -; GFX10-NEXT: s_and_b32 s13, s12, exec_lo -; GFX10-NEXT: s_cselect_b32 s5, s7, s5 -; GFX10-NEXT: s_and_b32 s7, s10, exec_lo -; GFX10-NEXT: s_cselect_b32 s5, s5, s9 -; GFX10-NEXT: s_and_b32 s7, s11, exec_lo -; GFX10-NEXT: s_cselect_b32 s4, s4, s8 -; GFX10-NEXT: s_and_b32 s7, s12, exec_lo -; GFX10-NEXT: s_cselect_b32 s4, s6, s4 -; GFX10-NEXT: s_and_b32 s6, s10, exec_lo -; GFX10-NEXT: s_cselect_b32 s4, s4, s8 +; GFX10-NEXT: v_cmp_u_f64_e64 s4, s[4:5], s[6:7] +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0, s4 ; GFX10-NEXT: ;;#ASMSTART -; GFX10-NEXT: ; use s[4:5] +; GFX10-NEXT: ; use v[0:1] ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: s_setpc_b64 s[30:31] ; @@ -810,32 +500,12 @@ define void @s_minimum_f64(double inreg %src0, double inreg %src1) { ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_min_f64 v[0:1], s[0:1], s[2:3] -; GFX11-NEXT: v_cmp_u_f64_e64 s4, s[0:1], s[2:3] -; GFX11-NEXT: v_cmp_class_f64_e64 s7, s[0:1], 32 -; GFX11-NEXT: v_cmp_class_f64_e64 s8, s[2:3], 32 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_readfirstlane_b32 s5, v1 -; GFX11-NEXT: v_readfirstlane_b32 s6, v0 -; GFX11-NEXT: s_and_b32 s4, s4, exec_lo -; GFX11-NEXT: s_cselect_b32 s5, 0x7ff80000, s5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: s_cselect_b32 s4, 0, s6 -; GFX11-NEXT: s_and_b32 s9, s7, exec_lo -; GFX11-NEXT: v_cmp_eq_f64_e64 s6, s[4:5], 0 -; GFX11-NEXT: s_cselect_b32 s1, s1, s5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: s_and_b32 s9, s8, exec_lo -; GFX11-NEXT: s_cselect_b32 s1, s3, s1 -; GFX11-NEXT: s_and_b32 s3, s6, exec_lo -; GFX11-NEXT: s_cselect_b32 s1, s1, s5 -; GFX11-NEXT: s_and_b32 s3, s7, exec_lo -; GFX11-NEXT: s_cselect_b32 s0, s0, s4 -; GFX11-NEXT: s_and_b32 s3, s8, exec_lo -; GFX11-NEXT: s_cselect_b32 s0, s2, s0 -; GFX11-NEXT: s_and_b32 s2, s6, exec_lo -; GFX11-NEXT: s_cselect_b32 s0, s0, s4 +; GFX11-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[2:3] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0 ; GFX11-NEXT: ;;#ASMSTART -; GFX11-NEXT: ; use s[0:1] +; GFX11-NEXT: ; use v[0:1] ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: s_setpc_b64 s[30:31] ; diff --git a/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll index c33875dbfee4..a99c25a4e447 100644 --- a/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll +++ b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll @@ -45,74 +45,26 @@ define float @f32_minimum(float %a, float %b) { ; ; VSX-LABEL: f32_minimum: ; VSX: # %bb.0: # %entry -; VSX-NEXT: xscvdpspn 0, 1 ; VSX-NEXT: fcmpu 0, 1, 2 -; VSX-NEXT: xscvdpspn 3, 2 -; VSX-NEXT: mffprwz 3, 0 ; VSX-NEXT: bc 12, 3, .LBB0_2 ; VSX-NEXT: # %bb.1: # %entry -; VSX-NEXT: xsmindp 0, 1, 2 -; VSX-NEXT: b .LBB0_3 +; VSX-NEXT: xsmindp 1, 1, 2 +; VSX-NEXT: blr ; VSX-NEXT: .LBB0_2: -; VSX-NEXT: addis 4, 2, .LCPI0_0@toc@ha -; VSX-NEXT: lfs 0, .LCPI0_0@toc@l(4) -; VSX-NEXT: .LBB0_3: # %entry -; VSX-NEXT: xoris 3, 3, 32768 -; VSX-NEXT: mffprwz 4, 3 -; VSX-NEXT: cmplwi 3, 0 -; VSX-NEXT: bc 12, 2, .LBB0_5 -; VSX-NEXT: # %bb.4: # %entry -; VSX-NEXT: fmr 1, 0 -; VSX-NEXT: .LBB0_5: # %entry -; VSX-NEXT: xoris 3, 4, 32768 -; VSX-NEXT: cmplwi 3, 0 -; VSX-NEXT: bc 12, 2, .LBB0_7 -; VSX-NEXT: # %bb.6: # %entry -; VSX-NEXT: fmr 2, 1 -; VSX-NEXT: .LBB0_7: # %entry -; VSX-NEXT: xxlxor 1, 1, 1 -; VSX-NEXT: fcmpu 0, 0, 1 -; VSX-NEXT: bc 12, 2, .LBB0_9 -; VSX-NEXT: # %bb.8: # %entry -; VSX-NEXT: fmr 2, 0 -; VSX-NEXT: .LBB0_9: # %entry -; VSX-NEXT: fmr 1, 2 +; VSX-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; VSX-NEXT: lfs 1, .LCPI0_0@toc@l(3) ; VSX-NEXT: blr ; ; AIX-LABEL: f32_minimum: ; AIX: # %bb.0: # %entry -; AIX-NEXT: xscvdpspn 0, 1 ; AIX-NEXT: fcmpu 0, 1, 2 -; AIX-NEXT: xscvdpspn 3, 2 -; AIX-NEXT: mffprwz 3, 0 ; AIX-NEXT: bc 12, 3, L..BB0_2 ; AIX-NEXT: # %bb.1: # %entry -; AIX-NEXT: xsmindp 0, 1, 2 -; AIX-NEXT: b L..BB0_3 +; AIX-NEXT: xsmindp 1, 1, 2 +; AIX-NEXT: blr ; AIX-NEXT: L..BB0_2: -; AIX-NEXT: ld 4, L..C0(2) # %const.0 -; AIX-NEXT: lfs 0, 0(4) -; AIX-NEXT: L..BB0_3: # %entry -; AIX-NEXT: xoris 3, 3, 32768 -; AIX-NEXT: mffprwz 4, 3 -; AIX-NEXT: cmplwi 3, 0 -; AIX-NEXT: bc 12, 2, L..BB0_5 -; AIX-NEXT: # %bb.4: # %entry -; AIX-NEXT: fmr 1, 0 -; AIX-NEXT: L..BB0_5: # %entry -; AIX-NEXT: xoris 3, 4, 32768 -; AIX-NEXT: cmplwi 3, 0 -; AIX-NEXT: bc 12, 2, L..BB0_7 -; AIX-NEXT: # %bb.6: # %entry -; AIX-NEXT: fmr 2, 1 -; AIX-NEXT: L..BB0_7: # %entry -; AIX-NEXT: xxlxor 1, 1, 1 -; AIX-NEXT: fcmpu 0, 0, 1 -; AIX-NEXT: bc 12, 2, L..BB0_9 -; AIX-NEXT: # %bb.8: # %entry -; AIX-NEXT: fmr 2, 0 -; AIX-NEXT: L..BB0_9: # %entry -; AIX-NEXT: fmr 1, 2 +; AIX-NEXT: ld 3, L..C0(2) # %const.0 +; AIX-NEXT: lfs 1, 0(3) ; AIX-NEXT: blr entry: %m = call float @llvm.minimum.f32(float %a, float %b) @@ -159,70 +111,26 @@ define float @f32_maximum(float %a, float %b) { ; ; VSX-LABEL: f32_maximum: ; VSX: # %bb.0: # %entry -; VSX-NEXT: xscvdpspn 0, 1 ; VSX-NEXT: fcmpu 0, 1, 2 -; VSX-NEXT: xscvdpspn 3, 2 -; VSX-NEXT: mffprwz 3, 0 ; VSX-NEXT: bc 12, 3, .LBB1_2 ; VSX-NEXT: # %bb.1: # %entry -; VSX-NEXT: xsmaxdp 0, 1, 2 -; VSX-NEXT: b .LBB1_3 +; VSX-NEXT: xsmaxdp 1, 1, 2 +; VSX-NEXT: blr ; VSX-NEXT: .LBB1_2: -; VSX-NEXT: addis 4, 2, .LCPI1_0@toc@ha -; VSX-NEXT: lfs 0, .LCPI1_0@toc@l(4) -; VSX-NEXT: .LBB1_3: # %entry -; VSX-NEXT: mffprwz 4, 3 -; VSX-NEXT: cmpwi 3, 0 -; VSX-NEXT: bc 12, 2, .LBB1_5 -; VSX-NEXT: # %bb.4: # %entry -; VSX-NEXT: fmr 1, 0 -; VSX-NEXT: .LBB1_5: # %entry -; VSX-NEXT: cmpwi 4, 0 -; VSX-NEXT: bc 12, 2, .LBB1_7 -; VSX-NEXT: # %bb.6: # %entry -; VSX-NEXT: fmr 2, 1 -; VSX-NEXT: .LBB1_7: # %entry -; VSX-NEXT: xxlxor 1, 1, 1 -; VSX-NEXT: fcmpu 0, 0, 1 -; VSX-NEXT: bc 12, 2, .LBB1_9 -; VSX-NEXT: # %bb.8: # %entry -; VSX-NEXT: fmr 2, 0 -; VSX-NEXT: .LBB1_9: # %entry -; VSX-NEXT: fmr 1, 2 +; VSX-NEXT: addis 3, 2, .LCPI1_0@toc@ha +; VSX-NEXT: lfs 1, .LCPI1_0@toc@l(3) ; VSX-NEXT: blr ; ; AIX-LABEL: f32_maximum: ; AIX: # %bb.0: # %entry -; AIX-NEXT: xscvdpspn 0, 1 ; AIX-NEXT: fcmpu 0, 1, 2 -; AIX-NEXT: xscvdpspn 3, 2 -; AIX-NEXT: mffprwz 3, 0 ; AIX-NEXT: bc 12, 3, L..BB1_2 ; AIX-NEXT: # %bb.1: # %entry -; AIX-NEXT: xsmaxdp 0, 1, 2 -; AIX-NEXT: b L..BB1_3 +; AIX-NEXT: xsmaxdp 1, 1, 2 +; AIX-NEXT: blr ; AIX-NEXT: L..BB1_2: -; AIX-NEXT: ld 4, L..C1(2) # %const.0 -; AIX-NEXT: lfs 0, 0(4) -; AIX-NEXT: L..BB1_3: # %entry -; AIX-NEXT: mffprwz 4, 3 -; AIX-NEXT: cmpwi 3, 0 -; AIX-NEXT: bc 12, 2, L..BB1_5 -; AIX-NEXT: # %bb.4: # %entry -; AIX-NEXT: fmr 1, 0 -; AIX-NEXT: L..BB1_5: # %entry -; AIX-NEXT: cmpwi 4, 0 -; AIX-NEXT: bc 12, 2, L..BB1_7 -; AIX-NEXT: # %bb.6: # %entry -; AIX-NEXT: fmr 2, 1 -; AIX-NEXT: L..BB1_7: # %entry -; AIX-NEXT: xxlxor 1, 1, 1 -; AIX-NEXT: fcmpu 0, 0, 1 -; AIX-NEXT: bc 12, 2, L..BB1_9 -; AIX-NEXT: # %bb.8: # %entry -; AIX-NEXT: fmr 2, 0 -; AIX-NEXT: L..BB1_9: # %entry -; AIX-NEXT: fmr 1, 2 +; AIX-NEXT: ld 3, L..C1(2) # %const.0 +; AIX-NEXT: lfs 1, 0(3) ; AIX-NEXT: blr entry: %m = call float @llvm.maximum.f32(float %a, float %b) @@ -272,69 +180,25 @@ define double @f64_minimum(double %a, double %b) { ; VSX-LABEL: f64_minimum: ; VSX: # %bb.0: # %entry ; VSX-NEXT: fcmpu 0, 1, 2 -; VSX-NEXT: mffprd 3, 1 ; VSX-NEXT: bc 12, 3, .LBB2_2 ; VSX-NEXT: # %bb.1: # %entry -; VSX-NEXT: xsmindp 0, 1, 2 -; VSX-NEXT: b .LBB2_3 +; VSX-NEXT: xsmindp 1, 1, 2 +; VSX-NEXT: blr ; VSX-NEXT: .LBB2_2: -; VSX-NEXT: addis 4, 2, .LCPI2_0@toc@ha -; VSX-NEXT: lfs 0, .LCPI2_0@toc@l(4) -; VSX-NEXT: .LBB2_3: # %entry -; VSX-NEXT: li 5, 1 -; VSX-NEXT: mffprd 4, 2 -; VSX-NEXT: rldic 5, 5, 63, 0 -; VSX-NEXT: cmpd 3, 5 -; VSX-NEXT: bc 12, 2, .LBB2_5 -; VSX-NEXT: # %bb.4: # %entry -; VSX-NEXT: fmr 1, 0 -; VSX-NEXT: .LBB2_5: # %entry -; VSX-NEXT: cmpd 4, 5 -; VSX-NEXT: bc 12, 2, .LBB2_7 -; VSX-NEXT: # %bb.6: # %entry -; VSX-NEXT: fmr 2, 1 -; VSX-NEXT: .LBB2_7: # %entry -; VSX-NEXT: xxlxor 1, 1, 1 -; VSX-NEXT: fcmpu 0, 0, 1 -; VSX-NEXT: bc 12, 2, .LBB2_9 -; VSX-NEXT: # %bb.8: # %entry -; VSX-NEXT: fmr 2, 0 -; VSX-NEXT: .LBB2_9: # %entry -; VSX-NEXT: fmr 1, 2 +; VSX-NEXT: addis 3, 2, .LCPI2_0@toc@ha +; VSX-NEXT: lfs 1, .LCPI2_0@toc@l(3) ; VSX-NEXT: blr ; ; AIX-LABEL: f64_minimum: ; AIX: # %bb.0: # %entry ; AIX-NEXT: fcmpu 0, 1, 2 -; AIX-NEXT: mffprd 3, 1 ; AIX-NEXT: bc 12, 3, L..BB2_2 ; AIX-NEXT: # %bb.1: # %entry -; AIX-NEXT: xsmindp 0, 1, 2 -; AIX-NEXT: b L..BB2_3 +; AIX-NEXT: xsmindp 1, 1, 2 +; AIX-NEXT: blr ; AIX-NEXT: L..BB2_2: -; AIX-NEXT: ld 4, L..C2(2) # %const.0 -; AIX-NEXT: lfs 0, 0(4) -; AIX-NEXT: L..BB2_3: # %entry -; AIX-NEXT: li 5, 1 -; AIX-NEXT: mffprd 4, 2 -; AIX-NEXT: rldic 5, 5, 63, 0 -; AIX-NEXT: cmpd 3, 5 -; AIX-NEXT: bc 12, 2, L..BB2_5 -; AIX-NEXT: # %bb.4: # %entry -; AIX-NEXT: fmr 1, 0 -; AIX-NEXT: L..BB2_5: # %entry -; AIX-NEXT: cmpd 4, 5 -; AIX-NEXT: bc 12, 2, L..BB2_7 -; AIX-NEXT: # %bb.6: # %entry -; AIX-NEXT: fmr 2, 1 -; AIX-NEXT: L..BB2_7: # %entry -; AIX-NEXT: xxlxor 1, 1, 1 -; AIX-NEXT: fcmpu 0, 0, 1 -; AIX-NEXT: bc 12, 2, L..BB2_9 -; AIX-NEXT: # %bb.8: # %entry -; AIX-NEXT: fmr 2, 0 -; AIX-NEXT: L..BB2_9: # %entry -; AIX-NEXT: fmr 1, 2 +; AIX-NEXT: ld 3, L..C2(2) # %const.0 +; AIX-NEXT: lfs 1, 0(3) ; AIX-NEXT: blr entry: %m = call double @llvm.minimum.f64(double %a, double %b) @@ -382,65 +246,25 @@ define double @f64_maximum(double %a, double %b) { ; VSX-LABEL: f64_maximum: ; VSX: # %bb.0: # %entry ; VSX-NEXT: fcmpu 0, 1, 2 -; VSX-NEXT: mffprd 3, 1 ; VSX-NEXT: bc 12, 3, .LBB3_2 ; VSX-NEXT: # %bb.1: # %entry -; VSX-NEXT: xsmaxdp 0, 1, 2 -; VSX-NEXT: b .LBB3_3 +; VSX-NEXT: xsmaxdp 1, 1, 2 +; VSX-NEXT: blr ; VSX-NEXT: .LBB3_2: -; VSX-NEXT: addis 4, 2, .LCPI3_0@toc@ha -; VSX-NEXT: lfs 0, .LCPI3_0@toc@l(4) -; VSX-NEXT: .LBB3_3: # %entry -; VSX-NEXT: mffprd 4, 2 -; VSX-NEXT: cmpdi 3, 0 -; VSX-NEXT: bc 12, 2, .LBB3_5 -; VSX-NEXT: # %bb.4: # %entry -; VSX-NEXT: fmr 1, 0 -; VSX-NEXT: .LBB3_5: # %entry -; VSX-NEXT: cmpdi 4, 0 -; VSX-NEXT: bc 12, 2, .LBB3_7 -; VSX-NEXT: # %bb.6: # %entry -; VSX-NEXT: fmr 2, 1 -; VSX-NEXT: .LBB3_7: # %entry -; VSX-NEXT: xxlxor 1, 1, 1 -; VSX-NEXT: fcmpu 0, 0, 1 -; VSX-NEXT: bc 12, 2, .LBB3_9 -; VSX-NEXT: # %bb.8: # %entry -; VSX-NEXT: fmr 2, 0 -; VSX-NEXT: .LBB3_9: # %entry -; VSX-NEXT: fmr 1, 2 +; VSX-NEXT: addis 3, 2, .LCPI3_0@toc@ha +; VSX-NEXT: lfs 1, .LCPI3_0@toc@l(3) ; VSX-NEXT: blr ; ; AIX-LABEL: f64_maximum: ; AIX: # %bb.0: # %entry ; AIX-NEXT: fcmpu 0, 1, 2 -; AIX-NEXT: mffprd 3, 1 ; AIX-NEXT: bc 12, 3, L..BB3_2 ; AIX-NEXT: # %bb.1: # %entry -; AIX-NEXT: xsmaxdp 0, 1, 2 -; AIX-NEXT: b L..BB3_3 +; AIX-NEXT: xsmaxdp 1, 1, 2 +; AIX-NEXT: blr ; AIX-NEXT: L..BB3_2: -; AIX-NEXT: ld 4, L..C3(2) # %const.0 -; AIX-NEXT: lfs 0, 0(4) -; AIX-NEXT: L..BB3_3: # %entry -; AIX-NEXT: mffprd 4, 2 -; AIX-NEXT: cmpdi 3, 0 -; AIX-NEXT: bc 12, 2, L..BB3_5 -; AIX-NEXT: # %bb.4: # %entry -; AIX-NEXT: fmr 1, 0 -; AIX-NEXT: L..BB3_5: # %entry -; AIX-NEXT: cmpdi 4, 0 -; AIX-NEXT: bc 12, 2, L..BB3_7 -; AIX-NEXT: # %bb.6: # %entry -; AIX-NEXT: fmr 2, 1 -; AIX-NEXT: L..BB3_7: # %entry -; AIX-NEXT: xxlxor 1, 1, 1 -; AIX-NEXT: fcmpu 0, 0, 1 -; AIX-NEXT: bc 12, 2, L..BB3_9 -; AIX-NEXT: # %bb.8: # %entry -; AIX-NEXT: fmr 2, 0 -; AIX-NEXT: L..BB3_9: # %entry -; AIX-NEXT: fmr 1, 2 +; AIX-NEXT: ld 3, L..C3(2) # %const.0 +; AIX-NEXT: lfs 1, 0(3) ; AIX-NEXT: blr entry: %m = call double @llvm.maximum.f64(double %a, double %b) -- GitLab From e2d17a053edff68c9761aceb8ff8303e3e37172c Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 9 May 2024 13:42:40 +0100 Subject: [PATCH 138/328] [AMDGPU] Build lane intrinsics in a mangling-agnostic way. NFC. (#91583) Use the form of CreateIntrinsic that takes an explicit return type and works out the mangling based on that and the types of the arguments. The advantage is that this still works if intrinsics are changed to have type mangling, e.g. if readlane/readfirstlane/writelane are changed to work on any type. --- .../Target/AMDGPU/AMDGPUAtomicOptimizer.cpp | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp index ad98f4f743ae..1d645002b1fe 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp @@ -493,8 +493,8 @@ Value *AMDGPUAtomicOptimizerImpl::buildScan(IRBuilder<> &B, if (!ST->isWave32()) { // Combine lane 31 into lanes 32..63. V = B.CreateBitCast(V, IntNTy); - Value *const Lane31 = B.CreateIntrinsic(Intrinsic::amdgcn_readlane, {}, - {V, B.getInt32(31)}); + Value *const Lane31 = B.CreateIntrinsic( + V->getType(), Intrinsic::amdgcn_readlane, {V, B.getInt32(31)}); Value *UpdateDPPCall = B.CreateCall( UpdateDPP, {Identity, Lane31, B.getInt32(DPP::QUAD_PERM_ID), @@ -598,8 +598,8 @@ std::pair AMDGPUAtomicOptimizerImpl::buildScanIteratively( // Get the value required for atomic operation V = B.CreateBitCast(V, IntNTy); - Value *LaneValue = - B.CreateIntrinsic(Intrinsic::amdgcn_readlane, {}, {V, LaneIdxInt}); + Value *LaneValue = B.CreateIntrinsic(V->getType(), Intrinsic::amdgcn_readlane, + {V, LaneIdxInt}); LaneValue = B.CreateBitCast(LaneValue, Ty); // Perform writelane if intermediate scan results are required later in the @@ -607,7 +607,7 @@ std::pair AMDGPUAtomicOptimizerImpl::buildScanIteratively( Value *OldValue = nullptr; if (NeedResult) { OldValue = - B.CreateIntrinsic(Intrinsic::amdgcn_writelane, {}, + B.CreateIntrinsic(IntNTy, Intrinsic::amdgcn_writelane, {B.CreateBitCast(Accumulator, IntNTy), LaneIdxInt, B.CreateBitCast(OldValuePhi, IntNTy)}); OldValue = B.CreateBitCast(OldValue, Ty); @@ -789,7 +789,7 @@ void AMDGPUAtomicOptimizerImpl::optimizeAtomic(Instruction &I, Value *const LastLaneIdx = B.getInt32(ST->getWavefrontSize() - 1); assert(TyBitWidth == 32); NewV = B.CreateBitCast(NewV, IntNTy); - NewV = B.CreateIntrinsic(Intrinsic::amdgcn_readlane, {}, + NewV = B.CreateIntrinsic(IntNTy, Intrinsic::amdgcn_readlane, {NewV, LastLaneIdx}); NewV = B.CreateBitCast(NewV, Ty); } @@ -936,10 +936,10 @@ void AMDGPUAtomicOptimizerImpl::optimizeAtomic(Instruction &I, Value *const ExtractLo = B.CreateTrunc(CastedPhi, Int32Ty); Value *const ExtractHi = B.CreateTrunc(B.CreateLShr(CastedPhi, 32), Int32Ty); - CallInst *const ReadFirstLaneLo = - B.CreateIntrinsic(Intrinsic::amdgcn_readfirstlane, {}, ExtractLo); - CallInst *const ReadFirstLaneHi = - B.CreateIntrinsic(Intrinsic::amdgcn_readfirstlane, {}, ExtractHi); + CallInst *const ReadFirstLaneLo = B.CreateIntrinsic( + Int32Ty, Intrinsic::amdgcn_readfirstlane, ExtractLo); + CallInst *const ReadFirstLaneHi = B.CreateIntrinsic( + Int32Ty, Intrinsic::amdgcn_readfirstlane, ExtractHi); Value *const PartialInsert = B.CreateInsertElement( PoisonValue::get(VecTy), ReadFirstLaneLo, B.getInt32(0)); Value *const Insert = @@ -948,7 +948,7 @@ void AMDGPUAtomicOptimizerImpl::optimizeAtomic(Instruction &I, } else if (TyBitWidth == 32) { Value *CastedPhi = B.CreateBitCast(PHI, IntNTy); BroadcastI = - B.CreateIntrinsic(Intrinsic::amdgcn_readfirstlane, {}, CastedPhi); + B.CreateIntrinsic(IntNTy, Intrinsic::amdgcn_readfirstlane, CastedPhi); BroadcastI = B.CreateBitCast(BroadcastI, Ty); } else { -- GitLab From d98e3d43e7943f0440013c9f491f323bcc864aa3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Danny=20M=C3=B6sch?= Date: Thu, 9 May 2024 14:52:03 +0200 Subject: [PATCH 139/328] [BOLT][NFC] Apply absorption rule to boolean expression (#91540) Fixes #91197. --- bolt/include/bolt/Passes/IndirectCallPromotion.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bolt/include/bolt/Passes/IndirectCallPromotion.h b/bolt/include/bolt/Passes/IndirectCallPromotion.h index adc58d70ec0f..8ec160b867cf 100644 --- a/bolt/include/bolt/Passes/IndirectCallPromotion.h +++ b/bolt/include/bolt/Passes/IndirectCallPromotion.h @@ -104,7 +104,7 @@ class IndirectCallPromotion : public BinaryFunctionPass { struct Location { MCSymbol *Sym{nullptr}; uint64_t Addr{0}; - bool isValid() const { return Sym || (!Sym && Addr != 0); } + bool isValid() const { return Sym || Addr != 0; } Location() {} explicit Location(MCSymbol *Sym) : Sym(Sym) {} explicit Location(uint64_t Addr) : Addr(Addr) {} -- GitLab From ed3a60c796c2ed3c9fc59efc83856913ab5860f5 Mon Sep 17 00:00:00 2001 From: Hongbin Jin Date: Thu, 9 May 2024 21:18:10 +0800 Subject: [PATCH 140/328] [RISCV][GlobalISel] Fix selectShiftMask when shift mask is created from G_AND (#89602) This patch fixes cases where G_AND creating the shift mask is eliminated if one of its source operands is a constant, resulting from an incorrect predicate. --- .../RISCV/GISel/RISCVInstructionSelector.cpp | 16 ++++- .../instruction-select/shift-rv32.mir | 56 +++++++++++++++++ .../instruction-select/shift-rv64.mir | 60 +++++++++++++++++++ 3 files changed, 131 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp index 3103992a86c0..791d364655e5 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -177,6 +177,20 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const { APInt AndMask; Register AndSrcReg; + // Try to combine the following pattern (applicable to other shift + // instructions as well as 32-bit ones): + // + // %4:gprb(s64) = G_AND %3, %2 + // %5:gprb(s64) = G_LSHR %1, %4(s64) + // + // According to RISC-V's ISA manual, SLL, SRL, and SRA ignore other bits than + // the lowest log2(XLEN) bits of register rs2. As for the above pattern, if + // the lowest log2(XLEN) bits of register rd and rs2 of G_AND are the same, + // then it can be eliminated. Given register rs1 or rs2 holding a constant + // (the and mask), there are two cases G_AND can be erased: + // + // 1. the lowest log2(XLEN) bits of the and mask are all set + // 2. the bits of the register being masked are already unset (zero set) if (mi_match(ShAmtReg, MRI, m_GAnd(m_Reg(AndSrcReg), m_ICst(AndMask)))) { APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); if (ShMask.isSubsetOf(AndMask)) { @@ -184,7 +198,7 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const { } else { // SimplifyDemandedBits may have optimized the mask so try restoring any // bits that are known zero. - KnownBits Known = KB->getKnownBits(ShAmtReg); + KnownBits Known = KB->getKnownBits(AndSrcReg); if (ShMask.isSubsetOf(AndMask | Known.Zero)) ShAmtReg = AndSrcReg; } diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv32.mir index 7d6c228c8086..4d0b5c2a2c86 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv32.mir @@ -188,3 +188,59 @@ body: | $x10 = COPY %4(s32) PseudoRET implicit $x10 ... + +--- +name: srl_and_needed +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: srl_and_needed + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 15 + ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SRL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 15 + %3:gprb(s32) = G_AND %0, %2 + %4:gprb(s32) = G_LSHR %1, %3(s32) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... + +--- +name: srl_and_eliminated +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: srl_and_eliminated + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 47 + ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SRL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 15 + %3:gprb(s32) = G_CONSTANT i32 47 + %4:gprb(s32) = G_AND %0, %3 + %5:gprb(s32) = G_AND %4, %2 + %6:gprb(s32) = G_LSHR %1, %5(s32) + $x10 = COPY %6(s32) + PseudoRET implicit $x10 +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv64.mir index 1e6890098498..5e2c60323fcb 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv64.mir @@ -241,3 +241,63 @@ body: | $x10 = COPY %6(s64) PseudoRET implicit $x10 ... + +--- +name: srl_and_needed +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: srl_and_needed + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 15 + ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SRL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 15 + %3:gprb(s32) = G_TRUNC %0(s64) + %4:gprb(s32) = G_AND %3, %2 + %5:gprb(s64) = nneg G_ZEXT %4(s32) + %6:gprb(s64) = G_LSHR %1, %5(s64) + $x10 = COPY %6(s64) + PseudoRET implicit $x10 +... + +--- +name: srl_and_eliminated +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: srl_and_eliminated + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 79 + ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SRL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 15 + %3:gprb(s32) = G_TRUNC %0(s64) + %7:gprb(s32) = G_CONSTANT i32 79 + %8:gprb(s32) = G_AND %3, %7 + %4:gprb(s32) = G_AND %8, %2 + %5:gprb(s64) = nneg G_ZEXT %4(s32) + %6:gprb(s64) = G_LSHR %1, %5(s64) + $x10 = COPY %6(s64) + PseudoRET implicit $x10 +... -- GitLab From 0c0fc9a7c6e298269871b4f1bf5fea7fa9048209 Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Thu, 9 May 2024 09:02:30 -0400 Subject: [PATCH 141/328] [gn build] Port d86b68afd7f0 (AMDGPUMCTests dependency mess) --- .../secondary/llvm/lib/Target/AMDGPU/BUILD.gn | 1 + .../llvm/lib/Target/AMDGPU/Utils/BUILD.gn | 5 ++++- .../gn/secondary/llvm/unittests/BUILD.gn | 2 +- .../llvm/unittests/MC/AMDGPU/BUILD.gn | 20 +++++++++++++++++-- 4 files changed, 24 insertions(+), 4 deletions(-) diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn index e1b867bf70ba..edd8d4f1840d 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn @@ -61,6 +61,7 @@ tablegen("AMDGPUGenRegisterBank") { visibility = [ ":LLVMAMDGPUCodeGen", "Utils", + "//llvm/unittests/MC/AMDGPU:AMDGPUMCTests", "//llvm/unittests/Target/AMDGPU:AMDGPUTests", ] args = [ "-gen-register-bank" ] diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/Utils/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/Utils/BUILD.gn index 631d1ef5c7b0..ec0d5fc767f7 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/Utils/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/Utils/BUILD.gn @@ -1,7 +1,10 @@ import("//llvm/utils/TableGen/tablegen.gni") tablegen("AMDGPUGenSearchableTables") { - visibility = [ ":Utils" ] + visibility = [ + ":Utils", + "//llvm/unittests/MC/AMDGPU:AMDGPUMCTests", + ] args = [ "-gen-searchable-tables" ] td_file = "../AMDGPU.td" } diff --git a/llvm/utils/gn/secondary/llvm/unittests/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/BUILD.gn index 6cc3848c1114..2db5b9603f21 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/BUILD.gn @@ -77,7 +77,7 @@ group("unittests") { } if (llvm_build_AMDGPU) { deps += [ - "MC/AMDGPU:AMDGPUDwarfTests", + "MC/AMDGPU:AMDGPUMCTests", "Target/AMDGPU:AMDGPUTests", ] } diff --git a/llvm/utils/gn/secondary/llvm/unittests/MC/AMDGPU/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/MC/AMDGPU/BUILD.gn index 603753abec35..4a7f829d6d8e 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/MC/AMDGPU/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/MC/AMDGPU/BUILD.gn @@ -1,13 +1,29 @@ import("//third-party/unittest/unittest.gni") -unittest("AMDGPUDwarfTests") { +unittest("AMDGPUMCTests") { deps = [ + "//llvm/lib/CodeGen", + "//llvm/lib/IR", "//llvm/lib/MC", "//llvm/lib/Support", "//llvm/lib/Target/AMDGPU:LLVMAMDGPUCodeGen", "//llvm/lib/Target/AMDGPU/MCTargetDesc", "//llvm/lib/Target/AMDGPU/TargetInfo", "//llvm/lib/TargetParser", + + # SIProgramInfoMCExprs.cpp includes AMDGPUTargetMachine.h, which includes + # the generated AMDGPUGenRegisterBank.inc file :/ + "//llvm/lib/Target/AMDGPU:AMDGPUGenRegisterBank", + + # SIProgramInfoMCExprs.cpp includes AMDGPUTargetMachine.h, which includes + # the generated AMDGPUGenSearchableTables.inc file :/ + "//llvm/lib/Target/AMDGPU/Utils:AMDGPUGenSearchableTables", + ] + + # AMDGPUMCTests heavily reaches into lib/Target/AMDGPU internals. + include_dirs = [ "//llvm/lib/Target/AMDGPU" ] + sources = [ + "DwarfRegMappings.cpp", + "SIProgramInfoMCExprs.cpp", ] - sources = [ "DwarfRegMappings.cpp" ] } -- GitLab From c73516af10f800d0d5641651eefce128b866a155 Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Thu, 9 May 2024 23:18:19 +1000 Subject: [PATCH 142/328] [ORC] Add tests for error handling paths in suspended generators. Test that (1) errors returned from a manually suspended generator are propagated as expected, and (2) automatic suspension does not interfere with our ability to resume (and return errors from) a generator. --- .../ExecutionEngine/Orc/CoreAPIsTest.cpp | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp b/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp index 3b24e29e1ed3..a6fa69f97fcb 100644 --- a/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp +++ b/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp @@ -1132,6 +1132,71 @@ TEST_F(CoreAPIsStandardTest, SimpleAsynchronousGeneratorTest) { EXPECT_TRUE(LookupCompleted); } +TEST_F(CoreAPIsStandardTest, ErrorFromSuspendedAsynchronousGeneratorTest) { + + auto &G = JD.addGenerator(std::make_unique()); + + bool LookupCompleted = false; + + ES.lookup( + LookupKind::Static, makeJITDylibSearchOrder(&JD), SymbolLookupSet(Foo), + SymbolState::Ready, + [&](Expected Result) { + LookupCompleted = true; + EXPECT_THAT_EXPECTED(Result, Failed()); + }, + NoDependenciesToRegister); + + EXPECT_FALSE(LookupCompleted); + + G.takeLookup().LS.continueLookup( + make_error("boom", inconvertibleErrorCode())); + + EXPECT_TRUE(LookupCompleted); +} + +TEST_F(CoreAPIsStandardTest, ErrorFromAutoSuspendedAsynchronousGeneratorTest) { + + auto &G = JD.addGenerator(std::make_unique()); + + std::atomic_size_t LookupsCompleted = 0; + + ES.lookup( + LookupKind::Static, makeJITDylibSearchOrder(&JD), SymbolLookupSet(Foo), + SymbolState::Ready, + [&](Expected Result) { + ++LookupsCompleted; + EXPECT_THAT_EXPECTED(Result, Failed()); + }, + NoDependenciesToRegister); + + EXPECT_EQ(LookupsCompleted, 0); + + // Suspend the first lookup. + auto LS1 = std::move(G.takeLookup().LS); + + // Start a second lookup that should be auto-suspended. + ES.lookup( + LookupKind::Static, makeJITDylibSearchOrder(&JD), SymbolLookupSet(Foo), + SymbolState::Ready, + [&](Expected Result) { + ++LookupsCompleted; + EXPECT_THAT_EXPECTED(Result, Failed()); + }, + NoDependenciesToRegister); + + EXPECT_EQ(LookupsCompleted, 0); + + // Unsuspend the first lookup. + LS1.continueLookup(make_error("boom", inconvertibleErrorCode())); + + // Unsuspend the second. + G.takeLookup().LS.continueLookup( + make_error("boom", inconvertibleErrorCode())); + + EXPECT_EQ(LookupsCompleted, 2); +} + TEST_F(CoreAPIsStandardTest, BlockedGeneratorAutoSuspensionTest) { // Test that repeated lookups while a generator is in use cause automatic // lookup suspension / resumption. -- GitLab From cbf1535cc813b2f226498d974c43675832abc233 Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Thu, 9 May 2024 23:20:31 +1000 Subject: [PATCH 143/328] [ORC] Fix fall-through in error case in EPCGenericDylibManager::lookupAsync. In the event of a serialization error (e.g. due to a network dropout) we should only run the Complete handler once, passing the serialization error value. No test-case: This would require a deliberately injected failure in a remote-JIT test and we don't have the infrastructure for that at the moment. rdar://126772381 --- llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp b/llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp index 6a7cab4a5510..7c0d89012922 100644 --- a/llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp +++ b/llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp @@ -109,6 +109,7 @@ void EPCGenericDylibManager::lookupAsync(tpctypes::DylibHandle H, if (SerializationErr) { cantFail(Result.takeError()); Complete(std::move(SerializationErr)); + return; } Complete(std::move(Result)); }, -- GitLab From e88ba6d975d887ca001cae30bfa0c53d91165148 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Thu, 9 May 2024 14:30:53 +0100 Subject: [PATCH 144/328] [AArch64] Add intrinsics for multi-vector to ZA array vector accumulators (#88266) According to the specification in https://github.com/ARM-software/acle/pull/309 this adds the intrinsics void_svadd_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za"); void_svadd_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za"); void_svsub_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za"); void_svsub_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za"); as well as the corresponding `bf16` variants. --- clang/include/clang/Basic/arm_sme.td | 10 + .../acle_sme2_add_sub_za16.c | 193 ++++++++++++++++++ .../acle_sme2_add_sub_za16.c | 29 +++ llvm/include/llvm/IR/IntrinsicsAArch64.td | 2 +- .../lib/Target/AArch64/AArch64SMEInstrInfo.td | 16 +- .../AArch64/sme2-intrinsics-add-sub-za16.ll | 148 ++++++++++++++ 6 files changed, 389 insertions(+), 9 deletions(-) create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c create mode 100644 clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c create mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index 1ac6d5170ea2..000bd97a4b25 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -298,6 +298,16 @@ multiclass ZAAddSub { def NAME # _ZA64_VG1X2_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsInOutZA], []>; def NAME # _ZA64_VG1X4_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsInOutZA], []>; } + + let TargetGuard = "sme-f16f16|sme-f8f16" in { + def NAME # _ZA16_VG1X2_F16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x2", "vm2", "h", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _ZA16_VG1X4_F16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x4", "vm4", "h", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x4", [IsStreaming, IsInOutZA], []>; + } + + let TargetGuard = "sme2,b16b16" in { + def NAME # _ZA16_VG1X2_BF16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x2", "vm2", "b", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _ZA16_VG1X4_BF16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x4", "vm4", "b", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x4", [IsStreaming, IsInOutZA], []>; + } } defm SVADD : ZAAddSub<"add">; diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c new file mode 100644 index 000000000000..d98427fac610 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c @@ -0,0 +1,193 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s | FileCheck %s -check-prefix CHECK-CXX +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s | FileCheck %s -check-prefix CHECK-CXX + +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -o /dev/null + +// REQUIRES: aarch64-registered-target + +#include + +#ifdef SVE_OVERLOADED_FORMS +#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3 +#else +#define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A3 +#endif + +// CHECK-LABEL: define dso_local void @test_svadd_za16_vg1x2_f16( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z25test_svadd_za16_vg1x2_f16j13svfloat16x2_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) +// CHECK-CXX-NEXT: ret void +// +void test_svadd_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za") { + SVE_ACLE_FUNC(svadd_za16,_f16,_vg1x2)(slice, zn); +} + +// CHECK-LABEL: define dso_local void @test_svadd_za16_vg1x4_f16( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z25test_svadd_za16_vg1x4_f16j13svfloat16x4_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-CXX-NEXT: ret void +// +void test_svadd_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za") { + SVE_ACLE_FUNC(svadd_za16,_f16,_vg1x4)(slice, zn); +} + +// CHECK-LABEL: define dso_local void @test_svsub_za16_vg1x2_f16( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z25test_svsub_za16_vg1x2_f16j13svfloat16x2_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) +// CHECK-CXX-NEXT: ret void +// +void test_svsub_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za") { + SVE_ACLE_FUNC(svsub_za16,_f16,_vg1x2)(slice, zn); +} + +// CHECK-LABEL: define dso_local void @test_svsub_za16_vg1x4_f16( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z25test_svsub_za16_vg1x4_f16j13svfloat16x4_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-CXX-NEXT: ret void +// +void test_svsub_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za") { + SVE_ACLE_FUNC(svsub_za16,_f16,_vg1x4)(slice, zn); +} + +// CHECK-LABEL: define dso_local void @test_svadd_za16_vg1x2_bf16( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svadd_za16_vg1x2_bf16j14svbfloat16x2_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) +// CHECK-CXX-NEXT: ret void +// +void test_svadd_za16_vg1x2_bf16(uint32_t slice, svbfloat16x2_t zn) __arm_streaming __arm_inout("za") { + SVE_ACLE_FUNC(svadd_za16,_bf16,_vg1x2)(slice, zn); +} + +// CHECK-LABEL: define dso_local void @test_svadd_za16_vg1x4_bf16( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svadd_za16_vg1x4_bf16j14svbfloat16x4_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-CXX-NEXT: ret void +// +void test_svadd_za16_vg1x4_bf16(uint32_t slice, svbfloat16x4_t zn) __arm_streaming __arm_inout("za") { + SVE_ACLE_FUNC(svadd_za16,_bf16,_vg1x4)(slice, zn); +} + +// CHECK-LABEL: define dso_local void @test_svsub_za16_vg1x2_bf16( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svsub_za16_vg1x2_bf16j14svbfloat16x2_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) +// CHECK-CXX-NEXT: ret void +// +void test_svsub_za16_vg1x2_bf16(uint32_t slice, svbfloat16x2_t zn) __arm_streaming __arm_inout("za") { + SVE_ACLE_FUNC(svsub_za16,_bf16,_vg1x2)(slice, zn); +} + +// CHECK-LABEL: define dso_local void @test_svsub_za16_vg1x4_bf16( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svsub_za16_vg1x4_bf16j14svbfloat16x4_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-CXX-NEXT: ret void +// +void test_svsub_za16_vg1x4_bf16(uint32_t slice, svbfloat16x4_t zn) __arm_streaming __arm_inout("za") { + SVE_ACLE_FUNC(svsub_za16,_bf16,_vg1x4)(slice, zn); +} diff --git a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c new file mode 100644 index 000000000000..0eeeac5a5046 --- /dev/null +++ b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c @@ -0,0 +1,29 @@ +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -fsyntax-only -verify -emit-llvm %s + +// REQUIRES: aarch64-registered-target + +#include + +void test_features(uint32_t slice, svfloat16x2_t zn2, svfloat16x4_t zn4, + svbfloat16x2_t bzn2, svbfloat16x4_t bzn4) __arm_streaming __arm_inout("za") { + // expected-error@+1 {{'svadd_za16_f16_vg1x2' needs target feature sme-f16f16|sme-f8f16}} + svadd_za16_f16_vg1x2(slice, zn2); + // expected-error@+1 {{'svadd_za16_f16_vg1x4' needs target feature sme-f16f16|sme-f8f16}} + svadd_za16_f16_vg1x4(slice, zn4); + // expected-error@+1 {{'svsub_za16_f16_vg1x2' needs target feature sme-f16f16|sme-f8f16}} + svsub_za16_f16_vg1x2(slice, zn2); + // expected-error@+1 {{'svsub_za16_f16_vg1x4' needs target feature sme-f16f16|sme-f8f16}} + svsub_za16_f16_vg1x4(slice, zn4); + + // expected-error@+1 {{'svadd_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svadd_za16_bf16_vg1x2(slice, bzn2); + // expected-error@+1 {{'svadd_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svadd_za16_bf16_vg1x4(slice, bzn4); + // expected-error@+1 {{'svsub_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svsub_za16_bf16_vg1x2(slice, bzn2); + // expected-error@+1 {{'svsub_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svsub_za16_bf16_vg1x4(slice, bzn4); +} + + + diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index e31e00a9c76f..04571faf1306 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -3481,7 +3481,7 @@ let TargetPrefix = "aarch64" in { // Multi-vector add/sub and accumulate into ZA // foreach intr = ["add", "sub"] in { - foreach za = ["za32", "za64"] in { + foreach za = ["za16","za32", "za64"] in { def int_aarch64_sme_ # intr # _ # za # _vg1x2 : SME2_ZA_Write_VG2_Intrinsic; def int_aarch64_sme_ # intr # _ # za # _vg1x4 : SME2_ZA_Write_VG4_Intrinsic; } diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index 574178c8d524..5102c602d54e 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -793,10 +793,10 @@ defm LUTI4_S_4ZTZI : sme2p1_luti4_vector_vg4_index<"luti4">; } let Predicates = [HasSMEF16F16orSMEF8F16] in { -defm FADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fadd", 0b0100, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>; -defm FADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fadd", 0b0100, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; -defm FSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fsub", 0b0101, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>; -defm FSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fsub", 0b0101, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; +defm FADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fadd", 0b0100, MatrixOp16, ZZ_h_mul_r, nxv8f16, int_aarch64_sme_add_za16_vg1x2>; +defm FADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fadd", 0b0100, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, int_aarch64_sme_add_za16_vg1x4>; +defm FSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fsub", 0b0101, MatrixOp16, ZZ_h_mul_r, nxv8f16, int_aarch64_sme_sub_za16_vg1x2>; +defm FSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fsub", 0b0101, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, int_aarch64_sme_sub_za16_vg1x4>; } let Predicates = [HasSMEF16F16] in { @@ -822,10 +822,10 @@ defm FMOPS_MPPZZ_H : sme2p1_fmop_tile_fp16<"fmops", 0b0, 0b1, 0b11, ZPR16>; } let Predicates = [HasSME2, HasB16B16] in { -defm BFADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"bfadd", 0b1100, MatrixOp16, ZZ_h_mul_r, nxv8bf16, null_frag>; -defm BFADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"bfadd", 0b1100, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, null_frag>; -defm BFSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"bfsub", 0b1101, MatrixOp16, ZZ_h_mul_r, nxv8bf16, null_frag>; -defm BFSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"bfsub", 0b1101, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, null_frag>; +defm BFADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"bfadd", 0b1100, MatrixOp16, ZZ_h_mul_r, nxv8bf16, int_aarch64_sme_add_za16_vg1x2>; +defm BFADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"bfadd", 0b1100, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, int_aarch64_sme_add_za16_vg1x4>; +defm BFSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"bfsub", 0b1101, MatrixOp16, ZZ_h_mul_r, nxv8bf16, int_aarch64_sme_sub_za16_vg1x2>; +defm BFSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"bfsub", 0b1101, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, int_aarch64_sme_sub_za16_vg1x4>; defm BFMLA_VG2_M2ZZI : sme2p1_multi_vec_array_vg2_index_16b<"bfmla", 0b00, 0b110, ZZ_h_mul_r, ZPR4b16>; defm BFMLA_VG4_M4ZZI : sme2p1_multi_vec_array_vg4_index_16b<"bfmla", 0b010, ZZZZ_h_mul_r, ZPR4b16>; diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll new file mode 100644 index 000000000000..e7a6c0d6c549 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll @@ -0,0 +1,148 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -verify-machineinstrs < %s | FileCheck %s + +target triple = "aarch64-linux" + +define void @add_f16_vg1x2(i32 %slice, %zn0, %zn1) #0 { +; CHECK-LABEL: add_f16_vg1x2: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: mov w8, w0 +; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: fadd za.h[w8, 0, vgx2], { z0.h, z1.h } +; CHECK-NEXT: fadd za.h[w8, 7, vgx2], { z0.h, z1.h } +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32 %slice, %zn0, %zn1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32 %slice.7, %zn0, %zn1) + ret void +} + +define void @add_f16_vg1x4(i32 %slice, %zn0, %zn1, +; CHECK-LABEL: add_f16_vg1x4: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: mov w8, w0 +; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: fadd za.h[w8, 0, vgx4], { z0.h - z3.h } +; CHECK-NEXT: fadd za.h[w8, 7, vgx4], { z0.h - z3.h } +; CHECK-NEXT: ret + %zn2, %zn3) #1 { + call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8f16(i32 %slice, %zn0, %zn1, + %zn2, %zn3); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8f16(i32 %slice.7, %zn0, %zn1, + %zn2, %zn3); + ret void +} + +define void @sub_f16_vg1x2(i32 %slice, %zn0, %zn1) #1 { +; CHECK-LABEL: sub_f16_vg1x2: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: mov w8, w0 +; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: fsub za.h[w8, 0, vgx2], { z0.h, z1.h } +; CHECK-NEXT: fsub za.h[w8, 7, vgx2], { z0.h, z1.h } +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8f16(i32 %slice, %zn0, %zn1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8f16(i32 %slice.7, %zn0, %zn1) + ret void +} + +define void @sub_f16_vg1x4(i32 %slice, %zn0, %zn1, +; CHECK-LABEL: sub_f16_vg1x4: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: mov w8, w0 +; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: fsub za.h[w8, 0, vgx4], { z0.h - z3.h } +; CHECK-NEXT: fsub za.h[w8, 7, vgx4], { z0.h - z3.h } +; CHECK-NEXT: ret + %zn2, %zn3) #0 { + call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8f16(i32 %slice, %zn0, %zn1, + %zn2, %zn3); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8f16(i32 %slice.7, %zn0, %zn1, + %zn2, %zn3); + ret void +} + +define void @add_bf16_vg1x2(i32 %slice, %zn0, %zn1) #2 { +; CHECK-LABEL: add_bf16_vg1x2: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: mov w8, w0 +; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: bfadd za.h[w8, 0, vgx2], { z0.h, z1.h } +; CHECK-NEXT: bfadd za.h[w8, 7, vgx2], { z0.h, z1.h } +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8bf16(i32 %slice, %zn0, %zn1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8bf16(i32 %slice.7, %zn0, %zn1) + ret void +} + +define void @add_bf16_vg1x4(i32 %slice, %zn0, %zn1, +; CHECK-LABEL: add_bf16_vg1x4: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: mov w8, w0 +; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: bfadd za.h[w8, 0, vgx4], { z0.h - z3.h } +; CHECK-NEXT: bfadd za.h[w8, 7, vgx4], { z0.h - z3.h } +; CHECK-NEXT: ret + %zn2, %zn3) #2 { + call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8bf16(i32 %slice, %zn0, %zn1, + %zn2, %zn3); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8bf16(i32 %slice.7, %zn0, %zn1, + %zn2, %zn3); + ret void +} + +define void @sub_bf16_vg1x2(i32 %slice, %zn0, %zn1) #2 { +; CHECK-LABEL: sub_bf16_vg1x2: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: mov w8, w0 +; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: bfsub za.h[w8, 0, vgx2], { z0.h, z1.h } +; CHECK-NEXT: bfsub za.h[w8, 7, vgx2], { z0.h, z1.h } +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8bf16(i32 %slice, %zn0, %zn1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8bf16(i32 %slice.7, %zn0, %zn1) + ret void +} + +define void @sub_bf16_vg1x4(i32 %slice, %zn0, %zn1, +; CHECK-LABEL: sub_bf16_vg1x4: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: mov w8, w0 +; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 +; CHECK-NEXT: bfsub za.h[w8, 0, vgx4], { z0.h - z3.h } +; CHECK-NEXT: bfsub za.h[w8, 7, vgx4], { z0.h - z3.h } +; CHECK-NEXT: ret + %zn2, %zn3) #2 { + call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8bf16(i32 %slice, %zn0, %zn1, + %zn2, %zn3); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8bf16(i32 %slice.7, %zn0, %zn1, + %zn2, %zn3); + ret void +} + +attributes #0 = { nounwind "target-features"="+sme-f16f16" } +attributes #1 = { nounwind "target-features"="+sme-f8f16" } +attributes #2 = { nounwind "target-features"="+sme2,+bf16,+b16b16" } -- GitLab From 6f1013a5b3f92d3ae6e378d6706584a2a44e6964 Mon Sep 17 00:00:00 2001 From: lntue <35648136+lntue@users.noreply.github.com> Date: Thu, 9 May 2024 09:31:06 -0400 Subject: [PATCH 145/328] [libc] Add template deduction guide for cpp::lock_guard. (#91589) Fix ctad-maybe-unsupported warnings for `cpp::lock_guard`. --- libc/src/__support/CPP/mutex.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libc/src/__support/CPP/mutex.h b/libc/src/__support/CPP/mutex.h index 345816fae233..ff9c9f43a43c 100644 --- a/libc/src/__support/CPP/mutex.h +++ b/libc/src/__support/CPP/mutex.h @@ -40,6 +40,9 @@ public: lock_guard(const lock_guard &) = delete; }; +// Deduction guide for lock_guard to suppress CTAD warnings. +template lock_guard(T &) -> lock_guard; + } // namespace cpp } // namespace LIBC_NAMESPACE -- GitLab From 8d2ab2a0ec168673696930ba3e3c403656cdfe55 Mon Sep 17 00:00:00 2001 From: erichkeane Date: Wed, 8 May 2024 11:38:00 -0700 Subject: [PATCH 146/328] [OpenACC][NFC] Fix EndLoc behavior of optional clause params It was discovered while writing the 'wait' clause ast tests that the 'endloc' wasn't set correctly when there was no arguments. This patch ensures we set it right, and adds an assert to prevent us from messing it up in the future. --- clang/include/clang/AST/OpenACCClause.h | 5 ++++- clang/lib/Parse/ParseOpenACC.cpp | 4 ++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/AST/OpenACCClause.h b/clang/include/clang/AST/OpenACCClause.h index e7b0b411b654..125c2af79330 100644 --- a/clang/include/clang/AST/OpenACCClause.h +++ b/clang/include/clang/AST/OpenACCClause.h @@ -26,7 +26,10 @@ class OpenACCClause { protected: OpenACCClause(OpenACCClauseKind K, SourceLocation BeginLoc, SourceLocation EndLoc) - : Kind(K), Location(BeginLoc, EndLoc) {} + : Kind(K), Location(BeginLoc, EndLoc) { + assert(!BeginLoc.isInvalid() && !EndLoc.isInvalid() && + "Begin and end location must be valid for OpenACCClause"); + } public: OpenACCClauseKind getClauseKind() const { return Kind; } diff --git a/clang/lib/Parse/ParseOpenACC.cpp b/clang/lib/Parse/ParseOpenACC.cpp index 8c8330a5fad7..727854db9be1 100644 --- a/clang/lib/Parse/ParseOpenACC.cpp +++ b/clang/lib/Parse/ParseOpenACC.cpp @@ -1112,6 +1112,10 @@ Parser::OpenACCClauseParseResult Parser::ParseOpenACCClauseParams( ParsedClause.setEndLoc(getCurToken().getLocation()); if (Parens.consumeClose()) return OpenACCCannotContinue(); + } else { + // If we have optional parens, make sure we set the end-location to the + // clause, as we are a 'single token' clause. + ParsedClause.setEndLoc(ClauseLoc); } } return OpenACCSuccess( -- GitLab From b1b465218d1fd3e1abe9332ed9ec535c49061425 Mon Sep 17 00:00:00 2001 From: erichkeane Date: Tue, 7 May 2024 13:30:07 -0700 Subject: [PATCH 147/328] [OpenACC] 'wait' clause for compute construct sema 'wait' takes a few int-exprs (well, a series of async-arguments, but those are effectively just an int-expr), plus a pair of tags. This patch adds the support for this to the AST, and does the appropriate semantic analysis for them. --- clang/include/clang/AST/OpenACCClause.h | 40 +++ clang/include/clang/Basic/OpenACCClauses.def | 1 + clang/include/clang/Parse/Parser.h | 10 +- clang/include/clang/Sema/SemaOpenACC.h | 52 +++- .../clang/Serialization/ASTRecordReader.h | 3 + .../clang/Serialization/ASTRecordWriter.h | 2 + clang/lib/AST/OpenACCClause.cpp | 31 +++ clang/lib/AST/StmtProfile.cpp | 7 + clang/lib/AST/TextNodeDumper.cpp | 7 + clang/lib/Parse/ParseOpenACC.cpp | 56 +++-- clang/lib/Sema/SemaOpenACC.cpp | 28 +++ clang/lib/Sema/TreeTransform.h | 45 ++++ clang/lib/Serialization/ASTReader.cpp | 18 +- clang/lib/Serialization/ASTWriter.cpp | 18 +- .../ast-print-openacc-compute-construct.cpp | 24 ++ clang/test/ParserOpenACC/parse-wait-clause.c | 48 ++-- .../compute-construct-intexpr-clause-ast.cpp | 229 ++++++++++++++++++ .../compute-construct-wait-clause.c | 38 +++ .../compute-construct-wait-clause.cpp | 104 ++++++++ clang/tools/libclang/CIndex.cpp | 6 + 20 files changed, 711 insertions(+), 56 deletions(-) create mode 100644 clang/test/SemaOpenACC/compute-construct-wait-clause.c create mode 100644 clang/test/SemaOpenACC/compute-construct-wait-clause.cpp diff --git a/clang/include/clang/AST/OpenACCClause.h b/clang/include/clang/AST/OpenACCClause.h index 125c2af79330..d8332816a499 100644 --- a/clang/include/clang/AST/OpenACCClause.h +++ b/clang/include/clang/AST/OpenACCClause.h @@ -192,6 +192,46 @@ public: } }; +// Represents the 'devnum' and expressions lists for the 'wait' clause. +class OpenACCWaitClause final + : public OpenACCClauseWithExprs, + public llvm::TrailingObjects { + SourceLocation QueuesLoc; + OpenACCWaitClause(SourceLocation BeginLoc, SourceLocation LParenLoc, + Expr *DevNumExpr, SourceLocation QueuesLoc, + ArrayRef QueueIdExprs, SourceLocation EndLoc) + : OpenACCClauseWithExprs(OpenACCClauseKind::Wait, BeginLoc, LParenLoc, + EndLoc), + QueuesLoc(QueuesLoc) { + // The first element of the trailing storage is always the devnum expr, + // whether it is used or not. + std::uninitialized_copy(&DevNumExpr, &DevNumExpr + 1, + getTrailingObjects()); + std::uninitialized_copy(QueueIdExprs.begin(), QueueIdExprs.end(), + getTrailingObjects() + 1); + setExprs( + MutableArrayRef(getTrailingObjects(), QueueIdExprs.size() + 1)); + } + +public: + static OpenACCWaitClause *Create(const ASTContext &C, SourceLocation BeginLoc, + SourceLocation LParenLoc, Expr *DevNumExpr, + SourceLocation QueuesLoc, + ArrayRef QueueIdExprs, + SourceLocation EndLoc); + + bool hasQueuesTag() const { return !QueuesLoc.isInvalid(); } + SourceLocation getQueuesLoc() const { return QueuesLoc; } + bool hasDevNumExpr() const { return getExprs()[0]; } + Expr *getDevNumExpr() const { return getExprs()[0]; } + llvm::ArrayRef getQueueIdExprs() { + return OpenACCClauseWithExprs::getExprs().drop_front(); + } + llvm::ArrayRef getQueueIdExprs() const { + return OpenACCClauseWithExprs::getExprs().drop_front(); + } +}; + class OpenACCNumGangsClause final : public OpenACCClauseWithExprs, public llvm::TrailingObjects { diff --git a/clang/include/clang/Basic/OpenACCClauses.def b/clang/include/clang/Basic/OpenACCClauses.def index 8933e09b44f9..afb7b30b7465 100644 --- a/clang/include/clang/Basic/OpenACCClauses.def +++ b/clang/include/clang/Basic/OpenACCClauses.def @@ -46,6 +46,7 @@ VISIT_CLAUSE(Present) VISIT_CLAUSE(Private) VISIT_CLAUSE(Self) VISIT_CLAUSE(VectorLength) +VISIT_CLAUSE(Wait) #undef VISIT_CLAUSE #undef CLAUSE_ALIAS diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h index 532b5c125ef5..60d59732269b 100644 --- a/clang/include/clang/Parse/Parser.h +++ b/clang/include/clang/Parse/Parser.h @@ -3632,6 +3632,13 @@ private: // Wait constructs, we likely want to put that information in here as well. }; + struct OpenACCWaitParseInfo { + bool Failed = false; + Expr *DevNumExpr = nullptr; + SourceLocation QueuesLoc; + SmallVector QueueIdExprs; + }; + /// Represents the 'error' state of parsing an OpenACC Clause, and stores /// whether we can continue parsing, or should give up on the directive. enum class OpenACCParseCanContinue { Cannot = 0, Can = 1 }; @@ -3674,7 +3681,8 @@ private: /// Parses the clause-list for an OpenACC directive. SmallVector ParseOpenACCClauseList(OpenACCDirectiveKind DirKind); - bool ParseOpenACCWaitArgument(SourceLocation Loc, bool IsDirective); + OpenACCWaitParseInfo ParseOpenACCWaitArgument(SourceLocation Loc, + bool IsDirective); /// Parses the clause of the 'bind' argument, which can be a string literal or /// an ID expression. ExprResult ParseOpenACCBindClauseArgument(); diff --git a/clang/include/clang/Sema/SemaOpenACC.h b/clang/include/clang/Sema/SemaOpenACC.h index 2cec2b73e918..e684ee6b2be1 100644 --- a/clang/include/clang/Sema/SemaOpenACC.h +++ b/clang/include/clang/Sema/SemaOpenACC.h @@ -54,8 +54,14 @@ public: bool IsZero; }; + struct WaitDetails { + Expr *DevNumExpr; + SourceLocation QueuesLoc; + SmallVector QueueIdExprs; + }; + std::variant + IntExprDetails, VarListDetails, WaitDetails> Details = std::monostate{}; public: @@ -104,14 +110,45 @@ public: ClauseKind == OpenACCClauseKind::Async || ClauseKind == OpenACCClauseKind::VectorLength) && "Parsed clause kind does not have a int exprs"); - // - // 'async' has an optional IntExpr, so be tolerant of that. - if (ClauseKind == OpenACCClauseKind::Async && + + // 'async' and 'wait' have an optional IntExpr, so be tolerant of that. + if ((ClauseKind == OpenACCClauseKind::Async || + ClauseKind == OpenACCClauseKind::Wait) && std::holds_alternative(Details)) return 0; return std::get(Details).IntExprs.size(); } + SourceLocation getQueuesLoc() const { + assert(ClauseKind == OpenACCClauseKind::Wait && + "Parsed clause kind does not have a queues location"); + + if (std::holds_alternative(Details)) + return SourceLocation{}; + + return std::get(Details).QueuesLoc; + } + + Expr *getDevNumExpr() const { + assert(ClauseKind == OpenACCClauseKind::Wait && + "Parsed clause kind does not have a device number expr"); + + if (std::holds_alternative(Details)) + return nullptr; + + return std::get(Details).DevNumExpr; + } + + ArrayRef getQueueIdExprs() const { + assert(ClauseKind == OpenACCClauseKind::Wait && + "Parsed clause kind does not have a queue id expr list"); + + if (std::holds_alternative(Details)) + return ArrayRef{std::nullopt}; + + return std::get(Details).QueueIdExprs; + } + ArrayRef getIntExprs() { assert((ClauseKind == OpenACCClauseKind::NumGangs || ClauseKind == OpenACCClauseKind::NumWorkers || @@ -282,6 +319,13 @@ public: "zero: tag only valid on copyout/create"); Details = VarListDetails{std::move(VarList), IsReadOnly, IsZero}; } + + void setWaitDetails(Expr *DevNum, SourceLocation QueuesLoc, + llvm::SmallVector &&IntExprs) { + assert(ClauseKind == OpenACCClauseKind::Wait && + "Parsed clause kind does not have a wait-details"); + Details = WaitDetails{DevNum, QueuesLoc, std::move(IntExprs)}; + } }; SemaOpenACC(Sema &S); diff --git a/clang/include/clang/Serialization/ASTRecordReader.h b/clang/include/clang/Serialization/ASTRecordReader.h index 1e11d2d5e42f..d00fb182f05f 100644 --- a/clang/include/clang/Serialization/ASTRecordReader.h +++ b/clang/include/clang/Serialization/ASTRecordReader.h @@ -272,6 +272,9 @@ public: /// Read a list of Exprs used for a var-list. llvm::SmallVector readOpenACCVarList(); + /// Read a list of Exprs used for a int-expr-list. + llvm::SmallVector readOpenACCIntExprList(); + /// Read an OpenACC clause, advancing Idx. OpenACCClause *readOpenACCClause(); diff --git a/clang/include/clang/Serialization/ASTRecordWriter.h b/clang/include/clang/Serialization/ASTRecordWriter.h index 8b1da49bd4c5..0c8ac75fc40f 100644 --- a/clang/include/clang/Serialization/ASTRecordWriter.h +++ b/clang/include/clang/Serialization/ASTRecordWriter.h @@ -296,6 +296,8 @@ public: void writeOpenACCVarList(const OpenACCClauseWithVarList *C); + void writeOpenACCIntExprList(ArrayRef Exprs); + /// Writes out a single OpenACC Clause. void writeOpenACCClause(const OpenACCClause *C); diff --git a/clang/lib/AST/OpenACCClause.cpp b/clang/lib/AST/OpenACCClause.cpp index ffa90884cef5..be079556a87a 100644 --- a/clang/lib/AST/OpenACCClause.cpp +++ b/clang/lib/AST/OpenACCClause.cpp @@ -147,6 +147,18 @@ OpenACCAsyncClause *OpenACCAsyncClause::Create(const ASTContext &C, return new (Mem) OpenACCAsyncClause(BeginLoc, LParenLoc, IntExpr, EndLoc); } +OpenACCWaitClause *OpenACCWaitClause::Create( + const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, + Expr *DevNumExpr, SourceLocation QueuesLoc, ArrayRef QueueIdExprs, + SourceLocation EndLoc) { + // Allocates enough room in trailing storage for all the int-exprs, plus a + // placeholder for the devnum. + void *Mem = C.Allocate( + OpenACCWaitClause::totalSizeToAlloc(QueueIdExprs.size() + 1)); + return new (Mem) OpenACCWaitClause(BeginLoc, LParenLoc, DevNumExpr, QueuesLoc, + QueueIdExprs, EndLoc); +} + OpenACCNumGangsClause *OpenACCNumGangsClause::Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, @@ -393,3 +405,22 @@ void OpenACCClausePrinter::VisitCreateClause(const OpenACCCreateClause &C) { [&](const Expr *E) { printExpr(E); }); OS << ")"; } + +void OpenACCClausePrinter::VisitWaitClause(const OpenACCWaitClause &C) { + OS << "wait"; + if (!C.getLParenLoc().isInvalid()) { + OS << "("; + if (C.hasDevNumExpr()) { + OS << "devnum: "; + printExpr(C.getDevNumExpr()); + OS << " : "; + } + + if (C.hasQueuesTag()) + OS << "queues: "; + + llvm::interleaveComma(C.getQueueIdExprs(), OS, + [&](const Expr *E) { printExpr(E); }); + OS << ")"; + } +} diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp index 0910471098c9..8fb8940142eb 100644 --- a/clang/lib/AST/StmtProfile.cpp +++ b/clang/lib/AST/StmtProfile.cpp @@ -2578,6 +2578,13 @@ void OpenACCClauseProfiler::VisitAsyncClause(const OpenACCAsyncClause &Clause) { if (Clause.hasIntExpr()) Profiler.VisitStmt(Clause.getIntExpr()); } + +void OpenACCClauseProfiler::VisitWaitClause(const OpenACCWaitClause &Clause) { + if (Clause.hasDevNumExpr()) + Profiler.VisitStmt(Clause.getDevNumExpr()); + for (auto *E : Clause.getQueueIdExprs()) + Profiler.VisitStmt(E); +} } // namespace void StmtProfiler::VisitOpenACCComputeConstruct( diff --git a/clang/lib/AST/TextNodeDumper.cpp b/clang/lib/AST/TextNodeDumper.cpp index bf02d9545f84..12aa5858b798 100644 --- a/clang/lib/AST/TextNodeDumper.cpp +++ b/clang/lib/AST/TextNodeDumper.cpp @@ -437,6 +437,13 @@ void TextNodeDumper::Visit(const OpenACCClause *C) { if (cast(C)->isZero()) OS << " : zero"; break; + case OpenACCClauseKind::Wait: + OS << " clause"; + if (cast(C)->hasDevNumExpr()) + OS << " has devnum"; + if (cast(C)->hasQueuesTag()) + OS << " has queues tag"; + break; default: // Nothing to do here. break; diff --git a/clang/lib/Parse/ParseOpenACC.cpp b/clang/lib/Parse/ParseOpenACC.cpp index 727854db9be1..90dfea6f5f5c 100644 --- a/clang/lib/Parse/ParseOpenACC.cpp +++ b/clang/lib/Parse/ParseOpenACC.cpp @@ -867,7 +867,6 @@ Parser::OpenACCClauseParseResult Parser::ParseOpenACCClauseParams( SemaOpenACC::OpenACCParsedClause ParsedClause(DirKind, ClauseKind, ClauseLoc); if (ClauseHasRequiredParens(DirKind, ClauseKind)) { - ParsedClause.setLParenLoc(getCurToken().getLocation()); if (Parens.expectAndConsume()) { // We are missing a paren, so assume that the person just forgot the // parameter. Return 'false' so we try to continue on and parse the next @@ -876,6 +875,7 @@ Parser::OpenACCClauseParseResult Parser::ParseOpenACCClauseParams( Parser::StopBeforeMatch); return OpenACCCanContinue(); } + ParsedClause.setLParenLoc(Parens.getOpenLocation()); switch (ClauseKind) { case OpenACCClauseKind::Default: { @@ -1048,8 +1048,8 @@ Parser::OpenACCClauseParseResult Parser::ParseOpenACCClauseParams( return OpenACCCannotContinue(); } else if (ClauseHasOptionalParens(DirKind, ClauseKind)) { - ParsedClause.setLParenLoc(getCurToken().getLocation()); if (!Parens.consumeOpen()) { + ParsedClause.setLParenLoc(Parens.getOpenLocation()); switch (ClauseKind) { case OpenACCClauseKind::Self: { assert(DirKind != OpenACCDirectiveKind::Update); @@ -1099,13 +1099,19 @@ Parser::OpenACCClauseParseResult Parser::ParseOpenACCClauseParams( return OpenACCCanContinue(); } break; - case OpenACCClauseKind::Wait: - if (ParseOpenACCWaitArgument(ClauseLoc, - /*IsDirective=*/false)) { + case OpenACCClauseKind::Wait: { + OpenACCWaitParseInfo Info = + ParseOpenACCWaitArgument(ClauseLoc, + /*IsDirective=*/false); + if (Info.Failed) { Parens.skipToEnd(); return OpenACCCanContinue(); } + + ParsedClause.setWaitDetails(Info.DevNumExpr, Info.QueuesLoc, + std::move(Info.QueueIdExprs)); break; + } default: llvm_unreachable("Not an optional parens type?"); } @@ -1139,7 +1145,9 @@ Parser::ParseOpenACCAsyncArgument(OpenACCDirectiveKind DK, OpenACCClauseKind CK, /// In this section and throughout the specification, the term wait-argument /// means: /// [ devnum : int-expr : ] [ queues : ] async-argument-list -bool Parser::ParseOpenACCWaitArgument(SourceLocation Loc, bool IsDirective) { +Parser::OpenACCWaitParseInfo +Parser::ParseOpenACCWaitArgument(SourceLocation Loc, bool IsDirective) { + OpenACCWaitParseInfo Result; // [devnum : int-expr : ] if (isOpenACCSpecialToken(OpenACCSpecialTokenKind::DevNum, Tok) && NextToken().is(tok::colon)) { @@ -1153,18 +1161,25 @@ bool Parser::ParseOpenACCWaitArgument(SourceLocation Loc, bool IsDirective) { : OpenACCDirectiveKind::Invalid, IsDirective ? OpenACCClauseKind::Invalid : OpenACCClauseKind::Wait, Loc); - if (Res.first.isInvalid() && Res.second == OpenACCParseCanContinue::Cannot) - return true; + if (Res.first.isInvalid() && + Res.second == OpenACCParseCanContinue::Cannot) { + Result.Failed = true; + return Result; + } - if (ExpectAndConsume(tok::colon)) - return true; + if (ExpectAndConsume(tok::colon)) { + Result.Failed = true; + return Result; + } + + Result.DevNumExpr = Res.first.get(); } // [ queues : ] if (isOpenACCSpecialToken(OpenACCSpecialTokenKind::Queues, Tok) && NextToken().is(tok::colon)) { // Consume queues. - ConsumeToken(); + Result.QueuesLoc = ConsumeToken(); // Consume colon. ConsumeToken(); } @@ -1176,8 +1191,10 @@ bool Parser::ParseOpenACCWaitArgument(SourceLocation Loc, bool IsDirective) { bool FirstArg = true; while (!getCurToken().isOneOf(tok::r_paren, tok::annot_pragma_openacc_end)) { if (!FirstArg) { - if (ExpectAndConsume(tok::comma)) - return true; + if (ExpectAndConsume(tok::comma)) { + Result.Failed = true; + return Result; + } } FirstArg = false; @@ -1187,11 +1204,16 @@ bool Parser::ParseOpenACCWaitArgument(SourceLocation Loc, bool IsDirective) { IsDirective ? OpenACCClauseKind::Invalid : OpenACCClauseKind::Wait, Loc); - if (Res.first.isInvalid() && Res.second == OpenACCParseCanContinue::Cannot) - return true; + if (Res.first.isInvalid() && + Res.second == OpenACCParseCanContinue::Cannot) { + Result.Failed = true; + return Result; + } + + Result.QueueIdExprs.push_back(Res.first.get()); } - return false; + return Result; } ExprResult Parser::ParseOpenACCIDExpression() { @@ -1360,7 +1382,7 @@ Parser::OpenACCDirectiveParseInfo Parser::ParseOpenACCDirective() { break; case OpenACCDirectiveKind::Wait: // OpenACC has an optional paren-wrapped 'wait-argument'. - if (ParseOpenACCWaitArgument(StartLoc, /*IsDirective=*/true)) + if (ParseOpenACCWaitArgument(StartLoc, /*IsDirective=*/true).Failed) T.skipToEnd(); else T.consumeClose(); diff --git a/clang/lib/Sema/SemaOpenACC.cpp b/clang/lib/Sema/SemaOpenACC.cpp index b1086baa3ae2..656d30947a8d 100644 --- a/clang/lib/Sema/SemaOpenACC.cpp +++ b/clang/lib/Sema/SemaOpenACC.cpp @@ -216,6 +216,22 @@ bool doesClauseApplyToDirective(OpenACCDirectiveKind DirectiveKind, default: return false; } + case OpenACCClauseKind::Wait: + switch (DirectiveKind) { + case OpenACCDirectiveKind::Parallel: + case OpenACCDirectiveKind::Serial: + case OpenACCDirectiveKind::Kernels: + case OpenACCDirectiveKind::Data: + case OpenACCDirectiveKind::EnterData: + case OpenACCDirectiveKind::ExitData: + case OpenACCDirectiveKind::Update: + case OpenACCDirectiveKind::ParallelLoop: + case OpenACCDirectiveKind::SerialLoop: + case OpenACCDirectiveKind::KernelsLoop: + return true; + default: + return false; + } default: // Do nothing so we can go to the 'unimplemented' diagnostic instead. @@ -623,6 +639,18 @@ SemaOpenACC::ActOnClause(ArrayRef ExistingClauses, getASTContext(), Clause.getBeginLoc(), Clause.getLParenLoc(), Clause.getVarList(), Clause.getEndLoc()); } + case OpenACCClauseKind::Wait: { + // Restrictions only properly implemented on 'compute' constructs, and + // 'compute' constructs are the only construct that can do anything with + // this yet, so skip/treat as unimplemented in this case. + if (!isOpenACCComputeDirectiveKind(Clause.getDirectiveKind())) + break; + + return OpenACCWaitClause::Create( + getASTContext(), Clause.getBeginLoc(), Clause.getLParenLoc(), + Clause.getDevNumExpr(), Clause.getQueuesLoc(), Clause.getQueueIdExprs(), + Clause.getEndLoc()); + } default: break; } diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index 2d6d6dae680c..0b3cf566e3a7 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -11425,6 +11425,51 @@ void OpenACCClauseTransform::VisitAsyncClause( : nullptr, ParsedClause.getEndLoc()); } +template +void OpenACCClauseTransform::VisitWaitClause( + const OpenACCWaitClause &C) { + if (!C.getLParenLoc().isInvalid()) { + Expr *DevNumExpr = nullptr; + llvm::SmallVector InstantiatedQueueIdExprs; + + // Instantiate devnum expr if it exists. + if (C.getDevNumExpr()) { + ExprResult Res = Self.TransformExpr(C.getDevNumExpr()); + if (!Res.isUsable()) + return; + Res = Self.getSema().OpenACC().ActOnIntExpr(OpenACCDirectiveKind::Invalid, + C.getClauseKind(), + C.getBeginLoc(), Res.get()); + if (!Res.isUsable()) + return; + + DevNumExpr = Res.get(); + } + + // Instantiate queue ids. + for (Expr *CurQueueIdExpr : C.getQueueIdExprs()) { + ExprResult Res = Self.TransformExpr(CurQueueIdExpr); + if (!Res.isUsable()) + return; + Res = Self.getSema().OpenACC().ActOnIntExpr(OpenACCDirectiveKind::Invalid, + C.getClauseKind(), + C.getBeginLoc(), Res.get()); + if (!Res.isUsable()) + return; + + InstantiatedQueueIdExprs.push_back(Res.get()); + } + + ParsedClause.setWaitDetails(DevNumExpr, C.getQueuesLoc(), + std::move(InstantiatedQueueIdExprs)); + } + + NewClause = OpenACCWaitClause::Create( + Self.getSema().getASTContext(), ParsedClause.getBeginLoc(), + ParsedClause.getLParenLoc(), ParsedClause.getDevNumExpr(), + ParsedClause.getQueuesLoc(), ParsedClause.getQueueIdExprs(), + ParsedClause.getEndLoc()); +} } // namespace template OpenACCClause *TreeTransform::TransformOpenACCClause( diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index 856c743086c5..78e4df440641 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -11766,6 +11766,14 @@ SmallVector ASTRecordReader::readOpenACCVarList() { return VarList; } +SmallVector ASTRecordReader::readOpenACCIntExprList() { + unsigned NumExprs = readInt(); + llvm::SmallVector ExprList; + for (unsigned I = 0; I < NumExprs; ++I) + ExprList.push_back(readSubExpr()); + return ExprList; +} + OpenACCClause *ASTRecordReader::readOpenACCClause() { OpenACCClauseKind ClauseKind = readEnum(); SourceLocation BeginLoc = readSourceLocation(); @@ -11888,6 +11896,15 @@ OpenACCClause *ASTRecordReader::readOpenACCClause() { return OpenACCAsyncClause::Create(getContext(), BeginLoc, LParenLoc, AsyncExpr, EndLoc); } + case OpenACCClauseKind::Wait: { + SourceLocation LParenLoc = readSourceLocation(); + Expr *DevNumExpr = readBool() ? readSubExpr() : nullptr; + SourceLocation QueuesLoc = readSourceLocation(); + llvm::SmallVector QueueIdExprs = readOpenACCIntExprList(); + return OpenACCWaitClause::Create(getContext(), BeginLoc, LParenLoc, + DevNumExpr, QueuesLoc, QueueIdExprs, + EndLoc); + } case OpenACCClauseKind::Finalize: case OpenACCClauseKind::IfPresent: @@ -11913,7 +11930,6 @@ OpenACCClause *ASTRecordReader::readOpenACCClause() { case OpenACCClauseKind::DType: case OpenACCClauseKind::Tile: case OpenACCClauseKind::Gang: - case OpenACCClauseKind::Wait: case OpenACCClauseKind::Invalid: llvm_unreachable("Clause serialization not yet implemented"); } diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index ce2ea4e3d614..e7b9050165bb 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -7791,6 +7791,12 @@ void ASTRecordWriter::writeOpenACCVarList(const OpenACCClauseWithVarList *C) { AddStmt(E); } +void ASTRecordWriter::writeOpenACCIntExprList(ArrayRef Exprs) { + writeUInt32(Exprs.size()); + for (Expr *E : Exprs) + AddStmt(E); +} + void ASTRecordWriter::writeOpenACCClause(const OpenACCClause *C) { writeEnum(C->getClauseKind()); writeSourceLocation(C->getBeginLoc()); @@ -7916,6 +7922,17 @@ void ASTRecordWriter::writeOpenACCClause(const OpenACCClause *C) { AddStmt(const_cast(AC->getIntExpr())); return; } + case OpenACCClauseKind::Wait: { + const auto *WC = cast(C); + writeSourceLocation(WC->getLParenLoc()); + writeBool(WC->getDevNumExpr()); + if (const Expr *DNE = WC->getDevNumExpr()) + AddStmt(const_cast(DNE)); + writeSourceLocation(WC->getQueuesLoc()); + + writeOpenACCIntExprList(WC->getQueueIdExprs()); + return; + } case OpenACCClauseKind::Finalize: case OpenACCClauseKind::IfPresent: @@ -7941,7 +7958,6 @@ void ASTRecordWriter::writeOpenACCClause(const OpenACCClause *C) { case OpenACCClauseKind::DType: case OpenACCClauseKind::Tile: case OpenACCClauseKind::Gang: - case OpenACCClauseKind::Wait: case OpenACCClauseKind::Invalid: llvm_unreachable("Clause serialization not yet implemented"); } diff --git a/clang/test/AST/ast-print-openacc-compute-construct.cpp b/clang/test/AST/ast-print-openacc-compute-construct.cpp index 13597543e9b6..0bfb90bcb587 100644 --- a/clang/test/AST/ast-print-openacc-compute-construct.cpp +++ b/clang/test/AST/ast-print-openacc-compute-construct.cpp @@ -83,5 +83,29 @@ void foo() { // CHECK: #pragma acc kernels async #pragma acc kernels async while(true); + +// CHECK: #pragma acc parallel wait +#pragma acc parallel wait + while(true); + +// CHECK: #pragma acc parallel wait() +#pragma acc parallel wait() + while(true); + +// CHECK: #pragma acc parallel wait(*iPtr, i) +#pragma acc parallel wait(*iPtr, i) + while(true); + +// CHECK: #pragma acc parallel wait(queues: *iPtr, i) +#pragma acc parallel wait(queues:*iPtr, i) + while(true); + +// CHECK: #pragma acc parallel wait(devnum: i : *iPtr, i) +#pragma acc parallel wait(devnum:i:*iPtr, i) + while(true); + +// CHECK: #pragma acc parallel wait(devnum: i : queues: *iPtr, i) +#pragma acc parallel wait(devnum:i:queues:*iPtr, i) + while(true); } diff --git a/clang/test/ParserOpenACC/parse-wait-clause.c b/clang/test/ParserOpenACC/parse-wait-clause.c index 64f5b9c8fd73..9c7faa5c02eb 100644 --- a/clang/test/ParserOpenACC/parse-wait-clause.c +++ b/clang/test/ParserOpenACC/parse-wait-clause.c @@ -3,12 +3,10 @@ void func() { int i, j; - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} #pragma acc parallel wait {} - // expected-error@+2{{invalid OpenACC clause 'clause'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+1{{invalid OpenACC clause 'clause'}} #pragma acc parallel wait clause-list {} @@ -17,12 +15,10 @@ void func() { #pragma acc parallel wait ( {} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} #pragma acc parallel wait () {} - // expected-error@+2{{invalid OpenACC clause 'clause'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+1{{invalid OpenACC clause 'clause'}} #pragma acc parallel wait () clause-list {} @@ -61,12 +57,10 @@ void func() { #pragma acc parallel wait (queues: {} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} #pragma acc parallel wait (queues:) {} - // expected-error@+2{{invalid OpenACC clause 'clause'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+1{{invalid OpenACC clause 'clause'}} #pragma acc parallel wait (queues:) clause-list {} @@ -75,12 +69,10 @@ void func() { #pragma acc parallel wait (devnum: i + j:queues: {} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} #pragma acc parallel wait (devnum: i + j:queues:) {} - // expected-error@+2{{invalid OpenACC clause 'clause'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+1{{invalid OpenACC clause 'clause'}} #pragma acc parallel wait (devnum: i + j:queues:) clause-list {} @@ -108,13 +100,11 @@ void func() { #pragma acc parallel wait(i, j, 1+1, 3.3 {} - // expected-error@+2{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+1{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} #pragma acc parallel wait(i, j, 1+1, 3.3) {} - // expected-error@+3{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} - // expected-error@+2{{invalid OpenACC clause 'clause'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} + // expected-error@+1{{invalid OpenACC clause 'clause'}} #pragma acc parallel wait(i, j, 1+1, 3.3) clause-list {} @@ -146,14 +136,12 @@ void func() { #pragma acc parallel wait(queues:i, j, 1+1, 3.3, {} - // expected-error@+2{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+1{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} #pragma acc parallel wait(queues:i, j, 1+1, 3.3) {} - // expected-error@+3{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} - // expected-error@+2{{invalid OpenACC clause 'clause'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} + // expected-error@+1{{invalid OpenACC clause 'clause'}} #pragma acc parallel wait(queues:i, j, 1+1, 3.3) clause-list {} @@ -162,13 +150,11 @@ void func() { // expected-note@+1{{to match this '('}} #pragma acc parallel wait(devnum:3:i, j, 1+1, 3.3 {} - // expected-error@+2{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+1{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} #pragma acc parallel wait(devnum:3:i, j, 1+1, 3.3) {} - // expected-error@+3{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} - // expected-error@+2{{invalid OpenACC clause 'clause'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} + // expected-error@+1{{invalid OpenACC clause 'clause'}} #pragma acc parallel wait(devnum:3:i, j, 1+1, 3.3) clause-list {} @@ -177,13 +163,11 @@ void func() { // expected-note@+1{{to match this '('}} #pragma acc parallel wait(devnum:3:queues:i, j, 1+1, 3.3 {} - // expected-error@+2{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+1{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} #pragma acc parallel wait(devnum:3:queues:i, j, 1+1, 3.3) {} - // expected-error@+3{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} - // expected-error@+2{{invalid OpenACC clause 'clause'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{OpenACC clause 'wait' requires expression of integer type ('double' invalid)}} + // expected-error@+1{{invalid OpenACC clause 'clause'}} #pragma acc parallel wait(devnum:3:queues:i, j, 1+1, 3.3) clause-list {} } diff --git a/clang/test/SemaOpenACC/compute-construct-intexpr-clause-ast.cpp b/clang/test/SemaOpenACC/compute-construct-intexpr-clause-ast.cpp index b85de56c7ae9..56c3512dec3b 100644 --- a/clang/test/SemaOpenACC/compute-construct-intexpr-clause-ast.cpp +++ b/clang/test/SemaOpenACC/compute-construct-intexpr-clause-ast.cpp @@ -135,6 +135,93 @@ void NormalUses() { // CHECK-NEXT: WhileStmt // CHECK-NEXT: CXXBoolLiteralExpr // CHECK-NEXT: CompoundStmt + +#pragma acc parallel wait + while (true){} + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause + // CHECK-NEXT: <<>> + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt +#pragma acc parallel wait() + while (true){} + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause + // CHECK-NEXT: <<>> + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt +#pragma acc parallel wait(some_int(), some_long()) + while (true){} + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause + // CHECK-NEXT: <<>> + // CHECK-NEXT: CallExpr{{.*}}'int' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'int (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'int ()' lvalue Function{{.*}} 'some_int' 'int ()' + // CHECK-NEXT: CallExpr{{.*}}'long' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'long (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'long ()' lvalue Function{{.*}} 'some_long' 'long ()' + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt +#pragma acc parallel wait(queues:some_int(), some_long()) + while (true){} + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause has queues tag + // CHECK-NEXT: <<>> + // CHECK-NEXT: CallExpr{{.*}}'int' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'int (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'int ()' lvalue Function{{.*}} 'some_int' 'int ()' + // CHECK-NEXT: CallExpr{{.*}}'long' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'long (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'long ()' lvalue Function{{.*}} 'some_long' 'long ()' + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt +#pragma acc parallel wait(devnum: some_int() :some_int(), some_long()) + while (true){} + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause has devnum + // CHECK-NEXT: CallExpr{{.*}}'int' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'int (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'int ()' lvalue Function{{.*}} 'some_int' 'int ()' + // CHECK-NEXT: CallExpr{{.*}}'int' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'int (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'int ()' lvalue Function{{.*}} 'some_int' 'int ()' + // CHECK-NEXT: CallExpr{{.*}}'long' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'long (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'long ()' lvalue Function{{.*}} 'some_long' 'long ()' + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt +#pragma acc parallel wait(devnum: some_int() : queues :some_int(), some_long()) wait(devnum: some_int() : queues :some_int(), some_long()) + while (true){} + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause has devnum has queues tag + // CHECK-NEXT: CallExpr{{.*}}'int' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'int (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'int ()' lvalue Function{{.*}} 'some_int' 'int ()' + // CHECK-NEXT: CallExpr{{.*}}'int' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'int (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'int ()' lvalue Function{{.*}} 'some_int' 'int ()' + // CHECK-NEXT: CallExpr{{.*}}'long' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'long (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'long ()' lvalue Function{{.*}} 'some_long' 'long ()' + // CHECK-NEXT: wait clause has devnum has queues tag + // CHECK-NEXT: CallExpr{{.*}}'int' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'int (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'int ()' lvalue Function{{.*}} 'some_int' 'int ()' + // CHECK-NEXT: CallExpr{{.*}}'int' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'int (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'int ()' lvalue Function{{.*}} 'some_int' 'int ()' + // CHECK-NEXT: CallExpr{{.*}}'long' + // CHECK-NEXT: ImplicitCastExpr{{.*}}'long (*)()' + // CHECK-NEXT: DeclRefExpr{{.*}}'long ()' lvalue Function{{.*}} 'some_long' 'long ()' + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt } @@ -282,6 +369,72 @@ void TemplUses(T t, U u) { // CHECK-NEXT: CXXBoolLiteralExpr // CHECK-NEXT: CompoundStmt +#pragma acc parallel wait + while (true){} + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause + // CHECK-NEXT: <<>> + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt + +#pragma acc parallel wait() + while (true){} + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause + // CHECK-NEXT: <<>> + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt + +#pragma acc parallel wait(U::value, u) + while (true){} + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause + // CHECK-NEXT: <<>> + // CHECK-NEXT: DependentScopeDeclRefExpr{{.*}} '' lvalue + // CHECK-NEXT: NestedNameSpecifier TypeSpec 'U' + // CHECK-NEXT: DeclRefExpr{{.*}} 'U' lvalue ParmVar{{.*}} 'u' 'U' + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt + +#pragma acc parallel wait(queues: U::value, u) + while (true){} + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause has queues tag + // CHECK-NEXT: <<>> + // CHECK-NEXT: DependentScopeDeclRefExpr{{.*}} '' lvalue + // CHECK-NEXT: NestedNameSpecifier TypeSpec 'U' + // CHECK-NEXT: DeclRefExpr{{.*}} 'U' lvalue ParmVar{{.*}} 'u' 'U' + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt + +#pragma acc parallel wait(devnum:u:queues: U::value, u) + while (true){} + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause has devnum has queues tag + // CHECK-NEXT: DeclRefExpr{{.*}} 'U' lvalue ParmVar{{.*}} 'u' 'U' + // CHECK-NEXT: DependentScopeDeclRefExpr{{.*}} '' lvalue + // CHECK-NEXT: NestedNameSpecifier TypeSpec 'U' + // CHECK-NEXT: DeclRefExpr{{.*}} 'U' lvalue ParmVar{{.*}} 'u' 'U' + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt + +#pragma acc parallel wait(devnum:u: U::value, u) + while (true){} + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause has devnum + // CHECK-NEXT: DeclRefExpr{{.*}} 'U' lvalue ParmVar{{.*}} 'u' 'U' + // CHECK-NEXT: DependentScopeDeclRefExpr{{.*}} '' lvalue + // CHECK-NEXT: NestedNameSpecifier TypeSpec 'U' + // CHECK-NEXT: DeclRefExpr{{.*}} 'U' lvalue ParmVar{{.*}} 'u' 'U' + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt + // CHECK-NEXT: DeclStmt // CHECK-NEXT: VarDecl{{.*}}EndMarker @@ -437,6 +590,82 @@ void TemplUses(T t, U u) { // CHECK-NEXT: CXXBoolLiteralExpr // CHECK-NEXT: CompoundStmt + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause + // CHECK-NEXT: <<>> + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt + + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause + // CHECK-NEXT: <<>> + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt + + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause + // CHECK-NEXT: <<>> + // CHECK-NEXT: ImplicitCastExpr{{.*}} 'int' + // CHECK-NEXT: DeclRefExpr{{.*}} 'const int' lvalue Var{{.*}} 'value' 'const int' + // CHECK-NEXT: NestedNameSpecifier TypeSpec 'HasInt' + // CHECK-NEXT: ImplicitCastExpr{{.*}} 'char' + // CHECK-NEXT: CXXMemberCallExpr{{.*}}'char' + // CHECK-NEXT: MemberExpr{{.*}} '' .operator char + // CHECK-NEXT: DeclRefExpr{{.*}} 'HasInt' lvalue ParmVar + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt + + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause has queues tag + // CHECK-NEXT: <<>> + // CHECK-NEXT: ImplicitCastExpr{{.*}} 'int' + // CHECK-NEXT: DeclRefExpr{{.*}} 'const int' lvalue Var{{.*}} 'value' 'const int' + // CHECK-NEXT: NestedNameSpecifier TypeSpec 'HasInt' + // CHECK-NEXT: ImplicitCastExpr{{.*}} 'char' + // CHECK-NEXT: CXXMemberCallExpr{{.*}}'char' + // CHECK-NEXT: MemberExpr{{.*}} '' .operator char + // CHECK-NEXT: DeclRefExpr{{.*}} 'HasInt' lvalue ParmVar + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt + + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause has devnum has queues tag + // CHECK-NEXT: ImplicitCastExpr{{.*}} 'char' + // CHECK-NEXT: CXXMemberCallExpr{{.*}}'char' + // CHECK-NEXT: MemberExpr{{.*}} '' .operator char + // CHECK-NEXT: DeclRefExpr{{.*}} 'HasInt' lvalue ParmVar + // CHECK-NEXT: ImplicitCastExpr{{.*}} 'int' + // CHECK-NEXT: DeclRefExpr{{.*}} 'const int' lvalue Var{{.*}} 'value' 'const int' + // CHECK-NEXT: NestedNameSpecifier TypeSpec 'HasInt' + // CHECK-NEXT: ImplicitCastExpr{{.*}} 'char' + // CHECK-NEXT: CXXMemberCallExpr{{.*}}'char' + // CHECK-NEXT: MemberExpr{{.*}} '' .operator char + // CHECK-NEXT: DeclRefExpr{{.*}} 'HasInt' lvalue ParmVar + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt + + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: wait clause has devnum + // CHECK-NEXT: ImplicitCastExpr{{.*}} 'char' + // CHECK-NEXT: CXXMemberCallExpr{{.*}}'char' + // CHECK-NEXT: MemberExpr{{.*}} '' .operator char + // CHECK-NEXT: DeclRefExpr{{.*}} 'HasInt' lvalue ParmVar + // CHECK-NEXT: ImplicitCastExpr{{.*}} 'int' + // CHECK-NEXT: DeclRefExpr{{.*}} 'const int' lvalue Var{{.*}} 'value' 'const int' + // CHECK-NEXT: NestedNameSpecifier TypeSpec 'HasInt' + // CHECK-NEXT: ImplicitCastExpr{{.*}} 'char' + // CHECK-NEXT: CXXMemberCallExpr{{.*}}'char' + // CHECK-NEXT: MemberExpr{{.*}} '' .operator char + // CHECK-NEXT: DeclRefExpr{{.*}} 'HasInt' lvalue ParmVar + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: CompoundStmt + // CHECK-NEXT: DeclStmt // CHECK-NEXT: VarDecl{{.*}}EndMarker } diff --git a/clang/test/SemaOpenACC/compute-construct-wait-clause.c b/clang/test/SemaOpenACC/compute-construct-wait-clause.c new file mode 100644 index 000000000000..254aba8442fe --- /dev/null +++ b/clang/test/SemaOpenACC/compute-construct-wait-clause.c @@ -0,0 +1,38 @@ +// RUN: %clang_cc1 %s -fopenacc -verify + +struct NotConvertible{} NC; +short getS(); +int getI(); + +void uses() { + int arr[5]; + +#pragma acc parallel wait + while(1); + +#pragma acc serial wait() + while(1); + +#pragma acc kernels wait(getS(), getI()) + while(1); + +#pragma acc parallel wait(devnum:getS(): getI()) + while(1); + +#pragma acc parallel wait(devnum:getS(): queues: getI()) wait(devnum:getI(): queues: getS(), getI(), 5) + while(1); + + // expected-error@+1{{OpenACC clause 'wait' requires expression of integer type ('struct NotConvertible' invalid)}} +#pragma acc parallel wait(devnum:NC : 5) + while(1); + + // expected-error@+1{{OpenACC clause 'wait' requires expression of integer type ('struct NotConvertible' invalid)}} +#pragma acc parallel wait(devnum:5 : NC) + while(1); + + // expected-error@+3{{OpenACC clause 'wait' requires expression of integer type ('int[5]' invalid)}} + // expected-error@+2{{OpenACC clause 'wait' requires expression of integer type ('int[5]' invalid)}} + // expected-error@+1{{OpenACC clause 'wait' requires expression of integer type ('struct NotConvertible' invalid)}} +#pragma acc parallel wait(devnum:arr : queues: arr, NC, 5) + while(1); +} diff --git a/clang/test/SemaOpenACC/compute-construct-wait-clause.cpp b/clang/test/SemaOpenACC/compute-construct-wait-clause.cpp new file mode 100644 index 000000000000..94f669be0f67 --- /dev/null +++ b/clang/test/SemaOpenACC/compute-construct-wait-clause.cpp @@ -0,0 +1,104 @@ +// RUN: %clang_cc1 %s -fopenacc -verify + +struct ExplicitConvertOnly { + explicit operator int() const; // #EXPL_CONV +} Explicit; + +struct AmbiguousConvert{ + operator int(); // #AMBIG_INT + operator short(); // #AMBIG_SHORT + operator float(); +} Ambiguous; + +void Test() { + + // expected-error@+3{{multiple conversions from expression type 'struct AmbiguousConvert' to an integral type}} + // expected-note@#AMBIG_INT{{conversion to integral type 'int'}} + // expected-note@#AMBIG_SHORT{{conversion to integral type 'short'}} +#pragma acc parallel wait(Ambiguous) + while (true); + + // expected-error@+2{{OpenACC integer expression type 'struct ExplicitConvertOnly' requires explicit conversion to 'int'}} + // expected-note@#EXPL_CONV{{conversion to integral type 'int'}} +#pragma acc parallel wait(4, Explicit, 5) + while (true); + + // expected-error@+3{{multiple conversions from expression type 'struct AmbiguousConvert' to an integral type}} + // expected-note@#AMBIG_INT{{conversion to integral type 'int'}} + // expected-note@#AMBIG_SHORT{{conversion to integral type 'short'}} +#pragma acc parallel wait(queues: Ambiguous, 5) + while (true); + + // expected-error@+2{{OpenACC integer expression type 'struct ExplicitConvertOnly' requires explicit conversion to 'int'}} + // expected-note@#EXPL_CONV{{conversion to integral type 'int'}} +#pragma acc parallel wait(devnum: Explicit: 5) + while (true); + + // expected-error@+2{{OpenACC integer expression type 'struct ExplicitConvertOnly' requires explicit conversion to 'int'}} + // expected-note@#EXPL_CONV{{conversion to integral type 'int'}} +#pragma acc parallel wait(devnum: Explicit:queues: 5) + while (true); + + // expected-error@+1{{use of undeclared identifier 'queues'}} +#pragma acc parallel wait(devnum: queues: 5) + while (true); +} + +struct HasInt { + using IntTy = int; + using ShortTy = short; + static constexpr int value = 1; + static constexpr AmbiguousConvert ACValue; + static constexpr ExplicitConvertOnly EXValue; + + operator char(); +}; + +template +void TestInst() { + +#pragma acc parallel wait(T{}) + while (true); + +#pragma acc parallel wait(devnum:typename T::ShortTy{}:queues:typename T::IntTy{}) + while (true); + + // expected-error@+4{{multiple conversions from expression type 'const AmbiguousConvert' to an integral type}} + // expected-note@#INST{{in instantiation of function template specialization}} + // expected-note@#AMBIG_INT{{conversion to integral type 'int'}} + // expected-note@#AMBIG_SHORT{{conversion to integral type 'short'}} +#pragma acc parallel wait(devnum:T::value :queues:T::ACValue) + while (true); + + // expected-error@+5{{OpenACC integer expression type 'const ExplicitConvertOnly' requires explicit conversion to 'int'}} + // expected-note@#EXPL_CONV{{conversion to integral type 'int'}} + // expected-error@+3{{multiple conversions from expression type 'const AmbiguousConvert' to an integral type}} + // expected-note@#AMBIG_INT{{conversion to integral type 'int'}} + // expected-note@#AMBIG_SHORT{{conversion to integral type 'short'}} +#pragma acc parallel wait(devnum:T::EXValue :queues:T::ACValue) + while (true); + + // expected-error@+5{{OpenACC integer expression type 'const ExplicitConvertOnly' requires explicit conversion to 'int'}} + // expected-note@#EXPL_CONV{{conversion to integral type 'int'}} + // expected-error@+3{{multiple conversions from expression type 'const AmbiguousConvert' to an integral type}} + // expected-note@#AMBIG_INT{{conversion to integral type 'int'}} + // expected-note@#AMBIG_SHORT{{conversion to integral type 'short'}} +#pragma acc parallel wait(T::EXValue, T::ACValue) + while (true); + + // expected-error@+5{{OpenACC integer expression type 'const ExplicitConvertOnly' requires explicit conversion to 'int'}} + // expected-note@#EXPL_CONV{{conversion to integral type 'int'}} + // expected-error@+3{{multiple conversions from expression type 'const AmbiguousConvert' to an integral type}} + // expected-note@#AMBIG_INT{{conversion to integral type 'int'}} + // expected-note@#AMBIG_SHORT{{conversion to integral type 'short'}} +#pragma acc parallel wait(queues: T::EXValue, T::ACValue) + while (true); + + // expected-error@+1{{no member named 'Invalid' in 'HasInt'}} +#pragma acc parallel wait(queues: T::Invalid, T::Invalid2) + while (true); +} + +void Inst() { + TestInst(); // #INST +} diff --git a/clang/tools/libclang/CIndex.cpp b/clang/tools/libclang/CIndex.cpp index b845a381d63b..ae6659fe95e8 100644 --- a/clang/tools/libclang/CIndex.cpp +++ b/clang/tools/libclang/CIndex.cpp @@ -2851,6 +2851,12 @@ void OpenACCClauseEnqueue::VisitAsyncClause(const OpenACCAsyncClause &C) { if (C.hasIntExpr()) Visitor.AddStmt(C.getIntExpr()); } +void OpenACCClauseEnqueue::VisitWaitClause(const OpenACCWaitClause &C) { + if (const Expr *DevNumExpr = C.getDevNumExpr()) + Visitor.AddStmt(DevNumExpr); + for (Expr *QE : C.getQueueIdExprs()) + Visitor.AddStmt(QE); +} } // namespace void EnqueueVisitor::EnqueueChildren(const OpenACCClause *C) { -- GitLab From c416e43571cca78dea3ee75b2a9fec944c0c65a1 Mon Sep 17 00:00:00 2001 From: alx32 <103613512+alx32@users.noreply.github.com> Date: Thu, 9 May 2024 06:47:37 -0700 Subject: [PATCH 148/328] [lld-macho] Add support for non-lazy categories to ObjC category merger (#91548) In ObjC we can have categories that define a `+load` method that is called when the category is loaded. In such cases, we shouldn't optimize the category. These categories are present in the `__objc_nlcatlist` section. So we scan these section for such categories and ignore them from optimization. --- lld/MachO/ObjC.cpp | 24 ++++++++++ .../objc-category-merging-complete-test.s | 47 +++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/lld/MachO/ObjC.cpp b/lld/MachO/ObjC.cpp index 15b89a808b05..96ec646095be 100644 --- a/lld/MachO/ObjC.cpp +++ b/lld/MachO/ObjC.cpp @@ -428,6 +428,7 @@ public: static void doCleanup(); private: + DenseSet collectNlCategories(); void collectAndValidateCategoriesData(); void mergeCategoriesIntoSingleCategory(std::vector &categories); @@ -1060,7 +1061,27 @@ void ObjcCategoryMerger::createSymbolReference(Defined *refFrom, refFrom->isec()->relocs.push_back(r); } +// Get the list of categories in the '__objc_nlcatlist' section. We can't +// optimize these as they have a '+load' method that has to be called at +// runtime. +DenseSet ObjcCategoryMerger::collectNlCategories() { + DenseSet nlCategories; + + for (InputSection *sec : allInputSections) { + if (sec->getName() != section_names::objcNonLazyCatList) + continue; + + for (auto &r : sec->relocs) { + const Symbol *sym = r.referent.dyn_cast(); + nlCategories.insert(sym); + } + } + return nlCategories; +} + void ObjcCategoryMerger::collectAndValidateCategoriesData() { + auto nlCategories = collectNlCategories(); + for (InputSection *sec : allInputSections) { if (sec->getName() != section_names::objcCatList) continue; @@ -1074,6 +1095,9 @@ void ObjcCategoryMerger::collectAndValidateCategoriesData() { assert(categorySym && "Failed to get a valid category at __objc_catlit offset"); + if (nlCategories.count(categorySym)) + continue; + // We only support ObjC categories (no swift + @objc) // TODO: Support swift + @objc categories also if (!categorySym->getName().starts_with(objc::symbol_names::category)) diff --git a/lld/test/MachO/objc-category-merging-complete-test.s b/lld/test/MachO/objc-category-merging-complete-test.s index d2d264a3f26c..74400177b550 100644 --- a/lld/test/MachO/objc-category-merging-complete-test.s +++ b/lld/test/MachO/objc-category-merging-complete-test.s @@ -88,6 +88,7 @@ MERGE_CATS-NEXT: name {{.*}} MyProtocol02Prop MERGE_CATS-NEXT: attributes {{.*}} Ti,R,D MERGE_CATS-NEXT: name {{.*}} MyProtocol03Prop MERGE_CATS-NEXT: attributes {{.*}} Ti,R,D +MERGE_CATS: __OBJC_$_CATEGORY_MyBaseClass_$_Category04 NO_MERGE_CATS-NOT: __OBJC_$_CATEGORY_MyBaseClass(Category02|Category03) @@ -431,6 +432,15 @@ L_OBJC_IMAGE_INFO: ## @dynamic MyProtocol03Prop; ## @end ## +## // This category shouldn't be merged +## @interface MyBaseClass(Category04) +## + (void)load; +## @end +## +## @implementation MyBaseClass(Category04) +## + (void)load {} +## @end +## ## int main() { ## return 0; ## } @@ -493,6 +503,12 @@ L_OBJC_IMAGE_INFO: b _OUTLINED_FUNCTION_0 .cfi_endproc ; -- End function + .p2align 2 +"+[MyBaseClass(Category04) load]": + .cfi_startproc +; %bb.0: + ret + .cfi_endproc .globl _main ; -- Begin function main .p2align 2 _main: ; @main @@ -746,11 +762,42 @@ __OBJC_$_CATEGORY_MyBaseClass_$_Category03: .quad 0 .long 64 ; 0x40 .space 4 + .section __TEXT,__objc_classname,cstring_literals +l_OBJC_CLASS_NAME_.15: + .asciz "Category04" + .section __TEXT,__objc_methname,cstring_literals +l_OBJC_METH_VAR_NAME_.16: + .asciz "load" + .section __DATA,__objc_const + .p2align 3, 0x0 +__OBJC_$_CATEGORY_CLASS_METHODS_MyBaseClass_$_Category04: + .long 24 + .long 1 + .quad l_OBJC_METH_VAR_NAME_.16 + .quad l_OBJC_METH_VAR_TYPE_ + .quad "+[MyBaseClass(Category04) load]" + .p2align 3, 0x0 +__OBJC_$_CATEGORY_MyBaseClass_$_Category04: + .quad l_OBJC_CLASS_NAME_.15 + .quad _OBJC_CLASS_$_MyBaseClass + .quad 0 + .quad __OBJC_$_CATEGORY_CLASS_METHODS_MyBaseClass_$_Category04 + .quad 0 + .quad 0 + .quad 0 + .long 64 + .space 4 .section __DATA,__objc_catlist,regular,no_dead_strip .p2align 3, 0x0 ; @"OBJC_LABEL_CATEGORY_$" l_OBJC_LABEL_CATEGORY_$: .quad __OBJC_$_CATEGORY_MyBaseClass_$_Category02 .quad __OBJC_$_CATEGORY_MyBaseClass_$_Category03 + .quad __OBJC_$_CATEGORY_MyBaseClass_$_Category04 + .section __DATA,__objc_nlcatlist,regular,no_dead_strip + .p2align 3, 0x0 +l_OBJC_LABEL_NONLAZY_CATEGORY_$: + .quad __OBJC_$_CATEGORY_MyBaseClass_$_Category04 + .no_dead_strip __OBJC_LABEL_PROTOCOL_$_MyProtocol02 .no_dead_strip __OBJC_LABEL_PROTOCOL_$_MyProtocol03 .no_dead_strip __OBJC_PROTOCOL_$_MyProtocol02 -- GitLab From 4ad3de901e8acfafdeb59406064f24a3c2ea27e8 Mon Sep 17 00:00:00 2001 From: Jake Egan Date: Thu, 9 May 2024 09:53:57 -0400 Subject: [PATCH 149/328] [driver][test] Only check for unused plugin options (#91522) This fixes matching `clang: error: argument unused during compilation: '-Werror' [-Werror,-Wunused-command-line-argument]` on AIX. --------- Co-authored-by: Hubert Tong --- clang/test/Driver/plugin-driver-args.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/test/Driver/plugin-driver-args.cpp b/clang/test/Driver/plugin-driver-args.cpp index 6f0e6e2ba752..6efd859f9d08 100644 --- a/clang/test/Driver/plugin-driver-args.cpp +++ b/clang/test/Driver/plugin-driver-args.cpp @@ -23,5 +23,5 @@ // Plugins are only relevant for the -cc1 phase. No warning should be raised // when only using the assembler. See GH #88173. -// RUN: %clang -c -fpass-plugin=bar.so -fplugin=bar.so -fplugin-arg-bar-option -Werror -x assembler %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-PLUGIN-ASM -// CHECK-PLUGIN-ASM-NOT: argument unused during compilation +// RUN: %clang -c -fpass-plugin=bar.so -fplugin=bar.so -fplugin-arg-bar-option -Wunused-command-line-argument -x assembler %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-PLUGIN-ASM +// CHECK-PLUGIN-ASM-NOT: argument unused during compilation: '-f{{[a-z-]*plugin[^']*}}' -- GitLab From b54a5e7271e34530893ae374876e284a65d785d4 Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Thu, 9 May 2024 09:57:28 -0400 Subject: [PATCH 150/328] [gn] port d86b68afd7f0 more See my comments on https://github.com/llvm/llvm-project/pull/88257. (The AMDGPU target internal depencencies were among the messiest among all targets even before that.) --- llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn | 1 + .../gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/BUILD.gn | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn index edd8d4f1840d..dad4f028236d 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn @@ -60,6 +60,7 @@ tablegen("AMDGPUGenMCPseudoLowering") { tablegen("AMDGPUGenRegisterBank") { visibility = [ ":LLVMAMDGPUCodeGen", + "MCTargetDesc", "Utils", "//llvm/unittests/MC/AMDGPU:AMDGPUMCTests", "//llvm/unittests/Target/AMDGPU:AMDGPUTests", diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/BUILD.gn index 5ba91fcec83a..0df55cbc0826 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/BUILD.gn @@ -94,6 +94,10 @@ static_library("MCTargetDesc") { "//llvm/lib/Target/AMDGPU/TargetInfo", "//llvm/lib/Target/AMDGPU/Utils", "//llvm/lib/TargetParser", + + # AMDGPUMCExpr.cpp includes GCNSubtarget.h which after 490e348e679 + # includes the generated AMDGPUGenRegisterBank.inc file :/ + "//llvm/lib/Target/AMDGPU/:AMDGPUGenRegisterBank", ] include_dirs = [ ".." ] sources = [ -- GitLab From 139e0aa68dc23d2aeec05de1ae05ebf2aa5fa11e Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Thu, 9 May 2024 15:03:52 +0100 Subject: [PATCH 151/328] Revert "[AArch64] Add intrinsics for multi-vector to ZA array vector accumulators" (#91597) Reverts llvm/llvm-project#88266 due to test failures error: 'expected-error' diagnostics seen but not expected: (frontend): '-fsyntax-only' action ignored; '-emit-llvm' action specified previously --- clang/include/clang/Basic/arm_sme.td | 10 - .../acle_sme2_add_sub_za16.c | 193 ------------------ .../acle_sme2_add_sub_za16.c | 29 --- llvm/include/llvm/IR/IntrinsicsAArch64.td | 2 +- .../lib/Target/AArch64/AArch64SMEInstrInfo.td | 16 +- .../AArch64/sme2-intrinsics-add-sub-za16.ll | 148 -------------- 6 files changed, 9 insertions(+), 389 deletions(-) delete mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c delete mode 100644 clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c delete mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index 000bd97a4b25..1ac6d5170ea2 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -298,16 +298,6 @@ multiclass ZAAddSub { def NAME # _ZA64_VG1X2_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsInOutZA], []>; def NAME # _ZA64_VG1X4_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsInOutZA], []>; } - - let TargetGuard = "sme-f16f16|sme-f8f16" in { - def NAME # _ZA16_VG1X2_F16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x2", "vm2", "h", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x2", [IsStreaming, IsInOutZA], []>; - def NAME # _ZA16_VG1X4_F16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x4", "vm4", "h", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x4", [IsStreaming, IsInOutZA], []>; - } - - let TargetGuard = "sme2,b16b16" in { - def NAME # _ZA16_VG1X2_BF16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x2", "vm2", "b", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x2", [IsStreaming, IsInOutZA], []>; - def NAME # _ZA16_VG1X4_BF16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x4", "vm4", "b", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x4", [IsStreaming, IsInOutZA], []>; - } } defm SVADD : ZAAddSub<"add">; diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c deleted file mode 100644 index d98427fac610..000000000000 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c +++ /dev/null @@ -1,193 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s | FileCheck %s -check-prefix CHECK-CXX -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s | FileCheck %s -check-prefix CHECK-CXX - -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -o /dev/null - -// REQUIRES: aarch64-registered-target - -#include - -#ifdef SVE_OVERLOADED_FORMS -#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3 -#else -#define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A3 -#endif - -// CHECK-LABEL: define dso_local void @test_svadd_za16_vg1x2_f16( -// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) -// CHECK-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) -// CHECK-NEXT: ret void -// -// CHECK-CXX-LABEL: define dso_local void @_Z25test_svadd_za16_vg1x2_f16j13svfloat16x2_t( -// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { -// CHECK-CXX-NEXT: entry: -// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) -// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) -// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) -// CHECK-CXX-NEXT: ret void -// -void test_svadd_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za") { - SVE_ACLE_FUNC(svadd_za16,_f16,_vg1x2)(slice, zn); -} - -// CHECK-LABEL: define dso_local void @test_svadd_za16_vg1x4_f16( -// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) -// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) -// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) -// CHECK-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) -// CHECK-NEXT: ret void -// -// CHECK-CXX-LABEL: define dso_local void @_Z25test_svadd_za16_vg1x4_f16j13svfloat16x4_t( -// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-CXX-NEXT: entry: -// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) -// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) -// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) -// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) -// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) -// CHECK-CXX-NEXT: ret void -// -void test_svadd_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za") { - SVE_ACLE_FUNC(svadd_za16,_f16,_vg1x4)(slice, zn); -} - -// CHECK-LABEL: define dso_local void @test_svsub_za16_vg1x2_f16( -// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) -// CHECK-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) -// CHECK-NEXT: ret void -// -// CHECK-CXX-LABEL: define dso_local void @_Z25test_svsub_za16_vg1x2_f16j13svfloat16x2_t( -// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-CXX-NEXT: entry: -// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) -// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) -// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) -// CHECK-CXX-NEXT: ret void -// -void test_svsub_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming __arm_inout("za") { - SVE_ACLE_FUNC(svsub_za16,_f16,_vg1x2)(slice, zn); -} - -// CHECK-LABEL: define dso_local void @test_svsub_za16_vg1x4_f16( -// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) -// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) -// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) -// CHECK-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) -// CHECK-NEXT: ret void -// -// CHECK-CXX-LABEL: define dso_local void @_Z25test_svsub_za16_vg1x4_f16j13svfloat16x4_t( -// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-CXX-NEXT: entry: -// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) -// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) -// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) -// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) -// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) -// CHECK-CXX-NEXT: ret void -// -void test_svsub_za16_vg1x4_f16(uint32_t slice, svfloat16x4_t zn) __arm_streaming __arm_inout("za") { - SVE_ACLE_FUNC(svsub_za16,_f16,_vg1x4)(slice, zn); -} - -// CHECK-LABEL: define dso_local void @test_svadd_za16_vg1x2_bf16( -// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) -// CHECK-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) -// CHECK-NEXT: ret void -// -// CHECK-CXX-LABEL: define dso_local void @_Z26test_svadd_za16_vg1x2_bf16j14svbfloat16x2_t( -// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-CXX-NEXT: entry: -// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) -// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) -// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) -// CHECK-CXX-NEXT: ret void -// -void test_svadd_za16_vg1x2_bf16(uint32_t slice, svbfloat16x2_t zn) __arm_streaming __arm_inout("za") { - SVE_ACLE_FUNC(svadd_za16,_bf16,_vg1x2)(slice, zn); -} - -// CHECK-LABEL: define dso_local void @test_svadd_za16_vg1x4_bf16( -// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) -// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) -// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) -// CHECK-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) -// CHECK-NEXT: ret void -// -// CHECK-CXX-LABEL: define dso_local void @_Z26test_svadd_za16_vg1x4_bf16j14svbfloat16x4_t( -// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-CXX-NEXT: entry: -// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) -// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) -// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) -// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) -// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) -// CHECK-CXX-NEXT: ret void -// -void test_svadd_za16_vg1x4_bf16(uint32_t slice, svbfloat16x4_t zn) __arm_streaming __arm_inout("za") { - SVE_ACLE_FUNC(svadd_za16,_bf16,_vg1x4)(slice, zn); -} - -// CHECK-LABEL: define dso_local void @test_svsub_za16_vg1x2_bf16( -// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) -// CHECK-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) -// CHECK-NEXT: ret void -// -// CHECK-CXX-LABEL: define dso_local void @_Z26test_svsub_za16_vg1x2_bf16j14svbfloat16x2_t( -// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-CXX-NEXT: entry: -// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) -// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) -// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]]) -// CHECK-CXX-NEXT: ret void -// -void test_svsub_za16_vg1x2_bf16(uint32_t slice, svbfloat16x2_t zn) __arm_streaming __arm_inout("za") { - SVE_ACLE_FUNC(svsub_za16,_bf16,_vg1x2)(slice, zn); -} - -// CHECK-LABEL: define dso_local void @test_svsub_za16_vg1x4_bf16( -// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) -// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) -// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) -// CHECK-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) -// CHECK-NEXT: ret void -// -// CHECK-CXX-LABEL: define dso_local void @_Z26test_svsub_za16_vg1x4_bf16j14svbfloat16x4_t( -// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-CXX-NEXT: entry: -// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) -// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) -// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) -// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) -// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) -// CHECK-CXX-NEXT: ret void -// -void test_svsub_za16_vg1x4_bf16(uint32_t slice, svbfloat16x4_t zn) __arm_streaming __arm_inout("za") { - SVE_ACLE_FUNC(svsub_za16,_bf16,_vg1x4)(slice, zn); -} diff --git a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c deleted file mode 100644 index 0eeeac5a5046..000000000000 --- a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c +++ /dev/null @@ -1,29 +0,0 @@ -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -fsyntax-only -verify -emit-llvm %s - -// REQUIRES: aarch64-registered-target - -#include - -void test_features(uint32_t slice, svfloat16x2_t zn2, svfloat16x4_t zn4, - svbfloat16x2_t bzn2, svbfloat16x4_t bzn4) __arm_streaming __arm_inout("za") { - // expected-error@+1 {{'svadd_za16_f16_vg1x2' needs target feature sme-f16f16|sme-f8f16}} - svadd_za16_f16_vg1x2(slice, zn2); - // expected-error@+1 {{'svadd_za16_f16_vg1x4' needs target feature sme-f16f16|sme-f8f16}} - svadd_za16_f16_vg1x4(slice, zn4); - // expected-error@+1 {{'svsub_za16_f16_vg1x2' needs target feature sme-f16f16|sme-f8f16}} - svsub_za16_f16_vg1x2(slice, zn2); - // expected-error@+1 {{'svsub_za16_f16_vg1x4' needs target feature sme-f16f16|sme-f8f16}} - svsub_za16_f16_vg1x4(slice, zn4); - - // expected-error@+1 {{'svadd_za16_bf16_vg1x2' needs target feature sme2,b16b16}} - svadd_za16_bf16_vg1x2(slice, bzn2); - // expected-error@+1 {{'svadd_za16_bf16_vg1x4' needs target feature sme2,b16b16}} - svadd_za16_bf16_vg1x4(slice, bzn4); - // expected-error@+1 {{'svsub_za16_bf16_vg1x2' needs target feature sme2,b16b16}} - svsub_za16_bf16_vg1x2(slice, bzn2); - // expected-error@+1 {{'svsub_za16_bf16_vg1x4' needs target feature sme2,b16b16}} - svsub_za16_bf16_vg1x4(slice, bzn4); -} - - - diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index 04571faf1306..e31e00a9c76f 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -3481,7 +3481,7 @@ let TargetPrefix = "aarch64" in { // Multi-vector add/sub and accumulate into ZA // foreach intr = ["add", "sub"] in { - foreach za = ["za16","za32", "za64"] in { + foreach za = ["za32", "za64"] in { def int_aarch64_sme_ # intr # _ # za # _vg1x2 : SME2_ZA_Write_VG2_Intrinsic; def int_aarch64_sme_ # intr # _ # za # _vg1x4 : SME2_ZA_Write_VG4_Intrinsic; } diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index 5102c602d54e..574178c8d524 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -793,10 +793,10 @@ defm LUTI4_S_4ZTZI : sme2p1_luti4_vector_vg4_index<"luti4">; } let Predicates = [HasSMEF16F16orSMEF8F16] in { -defm FADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fadd", 0b0100, MatrixOp16, ZZ_h_mul_r, nxv8f16, int_aarch64_sme_add_za16_vg1x2>; -defm FADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fadd", 0b0100, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, int_aarch64_sme_add_za16_vg1x4>; -defm FSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fsub", 0b0101, MatrixOp16, ZZ_h_mul_r, nxv8f16, int_aarch64_sme_sub_za16_vg1x2>; -defm FSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fsub", 0b0101, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, int_aarch64_sme_sub_za16_vg1x4>; +defm FADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fadd", 0b0100, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>; +defm FADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fadd", 0b0100, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; +defm FSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fsub", 0b0101, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>; +defm FSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fsub", 0b0101, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; } let Predicates = [HasSMEF16F16] in { @@ -822,10 +822,10 @@ defm FMOPS_MPPZZ_H : sme2p1_fmop_tile_fp16<"fmops", 0b0, 0b1, 0b11, ZPR16>; } let Predicates = [HasSME2, HasB16B16] in { -defm BFADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"bfadd", 0b1100, MatrixOp16, ZZ_h_mul_r, nxv8bf16, int_aarch64_sme_add_za16_vg1x2>; -defm BFADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"bfadd", 0b1100, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, int_aarch64_sme_add_za16_vg1x4>; -defm BFSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"bfsub", 0b1101, MatrixOp16, ZZ_h_mul_r, nxv8bf16, int_aarch64_sme_sub_za16_vg1x2>; -defm BFSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"bfsub", 0b1101, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, int_aarch64_sme_sub_za16_vg1x4>; +defm BFADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"bfadd", 0b1100, MatrixOp16, ZZ_h_mul_r, nxv8bf16, null_frag>; +defm BFADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"bfadd", 0b1100, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, null_frag>; +defm BFSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"bfsub", 0b1101, MatrixOp16, ZZ_h_mul_r, nxv8bf16, null_frag>; +defm BFSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"bfsub", 0b1101, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, null_frag>; defm BFMLA_VG2_M2ZZI : sme2p1_multi_vec_array_vg2_index_16b<"bfmla", 0b00, 0b110, ZZ_h_mul_r, ZPR4b16>; defm BFMLA_VG4_M4ZZI : sme2p1_multi_vec_array_vg4_index_16b<"bfmla", 0b010, ZZZZ_h_mul_r, ZPR4b16>; diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll deleted file mode 100644 index e7a6c0d6c549..000000000000 --- a/llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll +++ /dev/null @@ -1,148 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -verify-machineinstrs < %s | FileCheck %s - -target triple = "aarch64-linux" - -define void @add_f16_vg1x2(i32 %slice, %zn0, %zn1) #0 { -; CHECK-LABEL: add_f16_vg1x2: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1 -; CHECK-NEXT: mov w8, w0 -; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1 -; CHECK-NEXT: fadd za.h[w8, 0, vgx2], { z0.h, z1.h } -; CHECK-NEXT: fadd za.h[w8, 7, vgx2], { z0.h, z1.h } -; CHECK-NEXT: ret - call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32 %slice, %zn0, %zn1) - %slice.7 = add i32 %slice, 7 - call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32 %slice.7, %zn0, %zn1) - ret void -} - -define void @add_f16_vg1x4(i32 %slice, %zn0, %zn1, -; CHECK-LABEL: add_f16_vg1x4: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: mov w8, w0 -; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: fadd za.h[w8, 0, vgx4], { z0.h - z3.h } -; CHECK-NEXT: fadd za.h[w8, 7, vgx4], { z0.h - z3.h } -; CHECK-NEXT: ret - %zn2, %zn3) #1 { - call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8f16(i32 %slice, %zn0, %zn1, - %zn2, %zn3); - %slice.7 = add i32 %slice, 7 - call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8f16(i32 %slice.7, %zn0, %zn1, - %zn2, %zn3); - ret void -} - -define void @sub_f16_vg1x2(i32 %slice, %zn0, %zn1) #1 { -; CHECK-LABEL: sub_f16_vg1x2: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1 -; CHECK-NEXT: mov w8, w0 -; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1 -; CHECK-NEXT: fsub za.h[w8, 0, vgx2], { z0.h, z1.h } -; CHECK-NEXT: fsub za.h[w8, 7, vgx2], { z0.h, z1.h } -; CHECK-NEXT: ret - call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8f16(i32 %slice, %zn0, %zn1) - %slice.7 = add i32 %slice, 7 - call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8f16(i32 %slice.7, %zn0, %zn1) - ret void -} - -define void @sub_f16_vg1x4(i32 %slice, %zn0, %zn1, -; CHECK-LABEL: sub_f16_vg1x4: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: mov w8, w0 -; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: fsub za.h[w8, 0, vgx4], { z0.h - z3.h } -; CHECK-NEXT: fsub za.h[w8, 7, vgx4], { z0.h - z3.h } -; CHECK-NEXT: ret - %zn2, %zn3) #0 { - call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8f16(i32 %slice, %zn0, %zn1, - %zn2, %zn3); - %slice.7 = add i32 %slice, 7 - call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8f16(i32 %slice.7, %zn0, %zn1, - %zn2, %zn3); - ret void -} - -define void @add_bf16_vg1x2(i32 %slice, %zn0, %zn1) #2 { -; CHECK-LABEL: add_bf16_vg1x2: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1 -; CHECK-NEXT: mov w8, w0 -; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1 -; CHECK-NEXT: bfadd za.h[w8, 0, vgx2], { z0.h, z1.h } -; CHECK-NEXT: bfadd za.h[w8, 7, vgx2], { z0.h, z1.h } -; CHECK-NEXT: ret - call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8bf16(i32 %slice, %zn0, %zn1) - %slice.7 = add i32 %slice, 7 - call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8bf16(i32 %slice.7, %zn0, %zn1) - ret void -} - -define void @add_bf16_vg1x4(i32 %slice, %zn0, %zn1, -; CHECK-LABEL: add_bf16_vg1x4: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: mov w8, w0 -; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: bfadd za.h[w8, 0, vgx4], { z0.h - z3.h } -; CHECK-NEXT: bfadd za.h[w8, 7, vgx4], { z0.h - z3.h } -; CHECK-NEXT: ret - %zn2, %zn3) #2 { - call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8bf16(i32 %slice, %zn0, %zn1, - %zn2, %zn3); - %slice.7 = add i32 %slice, 7 - call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8bf16(i32 %slice.7, %zn0, %zn1, - %zn2, %zn3); - ret void -} - -define void @sub_bf16_vg1x2(i32 %slice, %zn0, %zn1) #2 { -; CHECK-LABEL: sub_bf16_vg1x2: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1 -; CHECK-NEXT: mov w8, w0 -; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1 -; CHECK-NEXT: bfsub za.h[w8, 0, vgx2], { z0.h, z1.h } -; CHECK-NEXT: bfsub za.h[w8, 7, vgx2], { z0.h, z1.h } -; CHECK-NEXT: ret - call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8bf16(i32 %slice, %zn0, %zn1) - %slice.7 = add i32 %slice, 7 - call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8bf16(i32 %slice.7, %zn0, %zn1) - ret void -} - -define void @sub_bf16_vg1x4(i32 %slice, %zn0, %zn1, -; CHECK-LABEL: sub_bf16_vg1x4: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: mov w8, w0 -; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3 -; CHECK-NEXT: bfsub za.h[w8, 0, vgx4], { z0.h - z3.h } -; CHECK-NEXT: bfsub za.h[w8, 7, vgx4], { z0.h - z3.h } -; CHECK-NEXT: ret - %zn2, %zn3) #2 { - call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8bf16(i32 %slice, %zn0, %zn1, - %zn2, %zn3); - %slice.7 = add i32 %slice, 7 - call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8bf16(i32 %slice.7, %zn0, %zn1, - %zn2, %zn3); - ret void -} - -attributes #0 = { nounwind "target-features"="+sme-f16f16" } -attributes #1 = { nounwind "target-features"="+sme-f8f16" } -attributes #2 = { nounwind "target-features"="+sme2,+bf16,+b16b16" } -- GitLab From 673cfcd03b7b938b422fee07d8ca4a127d480b1f Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Thu, 9 May 2024 09:23:27 -0500 Subject: [PATCH 152/328] Revert "[Linker] Propagate `nobuiltin` attributes when linking known libcalls (#89431)" This apparently breaks AMDGPU offloading for unknown reasons. Reverting for now. This reverts commit aa16de6399a42421076ed642c3b4f7fb12c6d44b. --- llvm/include/llvm/Linker/IRMover.h | 33 +-------------- llvm/lib/Linker/CMakeLists.txt | 1 - llvm/lib/Linker/IRMover.cpp | 67 ++---------------------------- llvm/test/Linker/Inputs/strlen.ll | 21 ---------- llvm/test/Linker/libcalls.ll | 39 ----------------- 5 files changed, 5 insertions(+), 156 deletions(-) delete mode 100644 llvm/test/Linker/Inputs/strlen.ll delete mode 100644 llvm/test/Linker/libcalls.ll diff --git a/llvm/include/llvm/Linker/IRMover.h b/llvm/include/llvm/Linker/IRMover.h index 8e71c6080dff..1e3c5394ffa2 100644 --- a/llvm/include/llvm/Linker/IRMover.h +++ b/llvm/include/llvm/Linker/IRMover.h @@ -12,14 +12,11 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/FunctionExtras.h" -#include "llvm/ADT/StringSet.h" -#include "llvm/IR/GlobalValue.h" -#include "llvm/Support/StringSaver.h" -#include "llvm/TargetParser/Triple.h" #include namespace llvm { class Error; +class GlobalValue; class Metadata; class Module; class StructType; @@ -63,33 +60,6 @@ public: bool hasType(StructType *Ty); }; - /// Utility for handling linking of known libcall functions. If a merged - /// module contains a recognized library call we can no longer perform any - /// libcall related transformations. - class LibcallHandler { - bool HasLibcalls = false; - - StringSet<> Libcalls; - StringSet<> Triples; - - BumpPtrAllocator Alloc; - StringSaver Saver; - - public: - LibcallHandler() : Saver(Alloc) {} - - void updateLibcalls(const Triple &TheTriple); - - bool checkLibcalls(GlobalValue &GV) { - if (HasLibcalls) - return false; - return HasLibcalls = isa(&GV) && !GV.isDeclaration() && - Libcalls.count(GV.getName()); - } - - bool hasLibcalls() const { return HasLibcalls; } - }; - IRMover(Module &M); typedef std::function ValueAdder; @@ -114,7 +84,6 @@ private: Module &Composite; IdentifiedStructTypeSet IdentifiedStructTypes; MDMapT SharedMDs; ///< A Metadata map to use for all calls to \a move(). - LibcallHandler Libcalls; }; } // End llvm namespace diff --git a/llvm/lib/Linker/CMakeLists.txt b/llvm/lib/Linker/CMakeLists.txt index 25001c09a62d..5afb40f8b588 100644 --- a/llvm/lib/Linker/CMakeLists.txt +++ b/llvm/lib/Linker/CMakeLists.txt @@ -9,7 +9,6 @@ add_llvm_component_library(LLVMLinker intrinsics_gen LINK_COMPONENTS - Analysis Core Object Support diff --git a/llvm/lib/Linker/IRMover.cpp b/llvm/lib/Linker/IRMover.cpp index fe2b53183589..7a5aa0c80478 100644 --- a/llvm/lib/Linker/IRMover.cpp +++ b/llvm/lib/Linker/IRMover.cpp @@ -12,7 +12,6 @@ #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallString.h" -#include "llvm/Analysis/TargetLibraryInfo.h" #include "llvm/IR/AutoUpgrade.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DebugInfoMetadata.h" @@ -400,9 +399,6 @@ class IRLinker { /// A metadata map that's shared between IRLinker instances. MDMapT &SharedMDs; - /// A list of libcalls that the current target may call. - IRMover::LibcallHandler &Libcalls; - /// Mapping of values from what they used to be in Src, to what they are now /// in DstM. ValueToValueMapTy is a ValueMap, which involves some overhead /// due to the use of Value handles which the Linker doesn't actually need, @@ -544,12 +540,10 @@ public: IRLinker(Module &DstM, MDMapT &SharedMDs, IRMover::IdentifiedStructTypeSet &Set, std::unique_ptr SrcM, ArrayRef ValuesToLink, - IRMover::LibcallHandler &Libcalls, IRMover::LazyCallback AddLazyFor, - bool IsPerformingImport) + IRMover::LazyCallback AddLazyFor, bool IsPerformingImport) : DstM(DstM), SrcM(std::move(SrcM)), AddLazyFor(std::move(AddLazyFor)), TypeMap(Set), GValMaterializer(*this), LValMaterializer(*this), - SharedMDs(SharedMDs), Libcalls(Libcalls), - IsPerformingImport(IsPerformingImport), + SharedMDs(SharedMDs), IsPerformingImport(IsPerformingImport), Mapper(ValueMap, RF_ReuseAndMutateDistinctMDs | RF_IgnoreMissingLocals, &TypeMap, &GValMaterializer), IndirectSymbolMCID(Mapper.registerAlternateMappingContext( @@ -567,13 +561,6 @@ public: }; } -static void addNoBuiltinAttributes(Function &F) { - F.setAttributes( - F.getAttributes().addFnAttribute(F.getContext(), "no-builtins")); - F.setAttributes( - F.getAttributes().addFnAttribute(F.getContext(), Attribute::NoBuiltin)); -} - /// The LLVM SymbolTable class autorenames globals that conflict in the symbol /// table. This is good for all clients except for us. Go through the trouble /// to force this back. @@ -1618,26 +1605,14 @@ Error IRLinker::run() { DstM.setTargetTriple(SrcTriple.merge(DstTriple)); - // Update the target triple's libcall information if it was changed. - Libcalls.updateLibcalls(Triple(DstM.getTargetTriple())); - // Loop over all of the linked values to compute type mappings. computeTypeMapping(); - bool AddsLibcalls = false; std::reverse(Worklist.begin(), Worklist.end()); while (!Worklist.empty()) { GlobalValue *GV = Worklist.back(); Worklist.pop_back(); - // If the module already contains libcall functions we need every function - // linked in to have `nobuiltin` attributes. Otherwise check if this is a - // libcall definition. - if (Function *F = dyn_cast(GV); F && Libcalls.hasLibcalls()) - addNoBuiltinAttributes(*F); - else - AddsLibcalls = Libcalls.checkLibcalls(*GV); - // Already mapped. if (ValueMap.find(GV) != ValueMap.end() || IndirectSymbolValueMap.find(GV) != IndirectSymbolValueMap.end()) @@ -1700,13 +1675,6 @@ Error IRLinker::run() { } } - // If we have imported a recognized libcall function we can no longer make any - // reasonable optimizations based off of its semantics. Add the 'nobuiltin' - // attribute to every function to suppress libcall detection. - if (AddsLibcalls) - for (Function &F : DstM.functions()) - addNoBuiltinAttributes(F); - // Merge the module flags into the DstM module. return linkModuleFlagsMetadata(); } @@ -1789,22 +1757,6 @@ bool IRMover::IdentifiedStructTypeSet::hasType(StructType *Ty) { return I == NonOpaqueStructTypes.end() ? false : *I == Ty; } -void IRMover::LibcallHandler::updateLibcalls(const Triple &TheTriple) { - if (Triples.count(TheTriple.getTriple())) - return; - Triples.insert(Saver.save(TheTriple.getTriple())); - - // Collect the names of runtime functions that the target may want to call. - TargetLibraryInfoImpl TLII(TheTriple); - TargetLibraryInfo TLI(TLII); - for (unsigned I = 0, E = static_cast(LibFunc::NumLibFuncs); I != E; - ++I) { - LibFunc F = static_cast(I); - if (TLI.has(F)) - Libcalls.insert(TLI.getName(F)); - } -} - IRMover::IRMover(Module &M) : Composite(M) { TypeFinder StructTypes; StructTypes.run(M, /* OnlyNamed */ false); @@ -1820,25 +1772,14 @@ IRMover::IRMover(Module &M) : Composite(M) { for (const auto *MD : StructTypes.getVisitedMetadata()) { SharedMDs[MD].reset(const_cast(MD)); } - - // Check the composite module for any already present libcalls. If we define - // these then it is important to mark any imported functions as 'nobuiltin'. - Libcalls.updateLibcalls(Triple(Composite.getTargetTriple())); - for (Function &F : Composite.functions()) - if (Libcalls.checkLibcalls(F)) - break; - - if (Libcalls.hasLibcalls()) - for (Function &F : Composite.functions()) - addNoBuiltinAttributes(F); } Error IRMover::move(std::unique_ptr Src, ArrayRef ValuesToLink, LazyCallback AddLazyFor, bool IsPerformingImport) { IRLinker TheIRLinker(Composite, SharedMDs, IdentifiedStructTypes, - std::move(Src), ValuesToLink, Libcalls, - std::move(AddLazyFor), IsPerformingImport); + std::move(Src), ValuesToLink, std::move(AddLazyFor), + IsPerformingImport); Error E = TheIRLinker.run(); Composite.dropTriviallyDeadConstantArrays(); return E; diff --git a/llvm/test/Linker/Inputs/strlen.ll b/llvm/test/Linker/Inputs/strlen.ll deleted file mode 100644 index bc54aaf41e0c..000000000000 --- a/llvm/test/Linker/Inputs/strlen.ll +++ /dev/null @@ -1,21 +0,0 @@ -target triple = "x86_64-unknown-linux-gnu" - -define i64 @strlen(ptr %s) #0 { -entry: - br label %for.cond - -for.cond: - %s.addr.0 = phi ptr [ %s, %entry ], [ %incdec.ptr, %for.cond ] - %0 = load i8, ptr %s.addr.0, align 1 - %tobool.not = icmp eq i8 %0, 0 - %incdec.ptr = getelementptr inbounds i8, ptr %s.addr.0, i64 1 - br i1 %tobool.not, label %for.end, label %for.cond - -for.end: - %sub.ptr.lhs.cast = ptrtoint ptr %s.addr.0 to i64 - %sub.ptr.rhs.cast = ptrtoint ptr %s to i64 - %sub.ptr.sub = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast - ret i64 %sub.ptr.sub -} - -attributes #0 = { noinline } diff --git a/llvm/test/Linker/libcalls.ll b/llvm/test/Linker/libcalls.ll deleted file mode 100644 index ddc0d35e91d9..000000000000 --- a/llvm/test/Linker/libcalls.ll +++ /dev/null @@ -1,39 +0,0 @@ -; RUN: llvm-link %s %S/Inputs/strlen.ll -S -o - 2>%t.a.err | FileCheck %s --check-prefix=CHECK1 -; RUN: llvm-link %S/Inputs/strlen.ll %s -S -o - 2>%t.a.err | FileCheck %s --check-prefix=CHECK2 - -target triple = "x86_64-unknown-linux-gnu" - -@.str = private unnamed_addr constant [7 x i8] c"string\00", align 1 -@str = dso_local global ptr @.str, align 8 - -define void @foo() #0 { - ret void -} - -declare i64 @strlen(ptr) - -define void @bar() #0 { - ret void -} - -define i64 @baz() #0 { -entry: - %0 = load ptr, ptr @str, align 8 - %call = call i64 @strlen(ptr noundef %0) - ret i64 %call -} - -attributes #0 = { noinline } - -; CHECK1: define void @foo() #[[ATTR0:[0-9]+]] -; CHECK1: define void @bar() #[[ATTR0:[0-9]+]] -; CHECK1: define i64 @baz() #[[ATTR0:[0-9]+]] -; CHECK1: define i64 @strlen(ptr [[S:%.*]]) #[[ATTR0]] - -; CHECK2: define i64 @strlen(ptr [[S:%.*]]) #[[ATTR0:[0-9]+]] -; CHECK2: define void @foo() #[[ATTR0:[0-9]+]] -; CHECK2: define void @bar() #[[ATTR0:[0-9]+]] -; CHECK2: define i64 @baz() #[[ATTR0]] - -; CHECK1: attributes #[[ATTR0]] = { nobuiltin noinline "no-builtins" } -; CHECK2: attributes #[[ATTR0]] = { nobuiltin noinline "no-builtins" } -- GitLab From 846ffc7ac1a43dc83fc0ee1280a793988fae7ab0 Mon Sep 17 00:00:00 2001 From: Mehdi Amini Date: Thu, 9 May 2024 22:32:54 +0800 Subject: [PATCH 153/328] Disable flaky test: dfsan/release_shadow_space.c (#91493) The current pass rate on the bot is ~50%. https://github.com/llvm/llvm-project/issues/91287 --- compiler-rt/test/dfsan/release_shadow_space.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/compiler-rt/test/dfsan/release_shadow_space.c b/compiler-rt/test/dfsan/release_shadow_space.c index 675640a1c296..60dec98ebec4 100644 --- a/compiler-rt/test/dfsan/release_shadow_space.c +++ b/compiler-rt/test/dfsan/release_shadow_space.c @@ -3,6 +3,9 @@ // DFSAN_OPTIONS=no_huge_pages_for_shadow=false RUN: %clang_dfsan %s -DORIGIN_TRACKING -mllvm -dfsan-track-origins=1 -o %t && %run %t // DFSAN_OPTIONS=no_huge_pages_for_shadow=true RUN: %clang_dfsan %s -DORIGIN_TRACKING -mllvm -dfsan-track-origins=1 -o %t && %run %t +// This test is flaky right now: https://github.com/llvm/llvm-project/issues/91287 +// UNSUPPORTED: target={{.*}} + #include #include #include -- GitLab From fa9e90f5d23312587b3a17920941334e0d1a58a1 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Thu, 9 May 2024 06:35:54 -0500 Subject: [PATCH 154/328] [Reland][Libomptarget] Statically link all plugin runtimes (#87009) This patch overhauls the `libomptarget` and plugin interface. Currently, we define a C API and compile each plugin as a separate shared library. Then, `libomptarget` loads these API functions and forwards its internal calls to them. This was originally designed to allow multiple implementations of a library to be live. However, since then no one has used this functionality and it prevents us from using much nicer interfaces. If the old behavior is desired it should instead be implemented as a separate plugin. This patch replaces the `PluginAdaptorTy` interface with the `GenericPluginTy` that is used by the plugins. Each plugin exports a `createPlugin_` function that is used to get the specific implementation. This code is now shared with `libomptarget`. There are some notable improvements to this. 1. Massively improved lifetimes of life runtime objects 2. The plugins can use a C++ interface 3. Global state does not need to be duplicated for each plugin + libomptarget 4. Easier to use and add features and improve error handling 5. Less function call overhead / Improved LTO performance. Additional changes in this plugin are related to contending with the fact that state is now shared. Initialization and deinitialization is now handled correctly and in phase with the underlying runtime, allowing us to actually know when something is getting deallocated. Depends on https://github.com/llvm/llvm-project/pull/86971 https://github.com/llvm/llvm-project/pull/86875 https://github.com/llvm/llvm-project/pull/86868 --- clang/test/Driver/linker-wrapper-image.c | 2 +- .../Frontend/Offloading/OffloadWrapper.cpp | 7 +- offload/include/PluginManager.h | 61 ++---- offload/include/device.h | 8 +- offload/plugins-nextgen/CMakeLists.txt | 19 +- offload/plugins-nextgen/amdgpu/CMakeLists.txt | 5 - offload/plugins-nextgen/amdgpu/src/rtl.cpp | 14 +- offload/plugins-nextgen/common/CMakeLists.txt | 4 +- .../common/include/PluginInterface.h | 94 +------- .../common/include/Utils/ELF.h | 2 - offload/plugins-nextgen/common/src/JIT.cpp | 40 ++-- .../common/src/PluginInterface.cpp | 205 ------------------ offload/plugins-nextgen/cuda/CMakeLists.txt | 5 - offload/plugins-nextgen/cuda/src/rtl.cpp | 14 +- offload/plugins-nextgen/host/CMakeLists.txt | 8 - offload/plugins-nextgen/host/src/rtl.cpp | 14 +- offload/src/CMakeLists.txt | 4 + offload/src/OffloadRTL.cpp | 1 + offload/src/OpenMP/InteropAPI.cpp | 4 +- offload/src/PluginManager.cpp | 129 ++++------- offload/src/device.cpp | 3 +- offload/src/interface.cpp | 2 - .../kernelreplay/llvm-omp-kernel-replay.cpp | 2 - .../unittests/Plugins/NextgenPluginsTest.cpp | 1 - 24 files changed, 125 insertions(+), 523 deletions(-) diff --git a/clang/test/Driver/linker-wrapper-image.c b/clang/test/Driver/linker-wrapper-image.c index d01445e3aed0..5d5d62805e17 100644 --- a/clang/test/Driver/linker-wrapper-image.c +++ b/clang/test/Driver/linker-wrapper-image.c @@ -30,8 +30,8 @@ // OPENMP: define internal void @.omp_offloading.descriptor_reg() section ".text.startup" { // OPENMP-NEXT: entry: -// OPENMP-NEXT: %0 = call i32 @atexit(ptr @.omp_offloading.descriptor_unreg) // OPENMP-NEXT: call void @__tgt_register_lib(ptr @.omp_offloading.descriptor) +// OPENMP-NEXT: %0 = call i32 @atexit(ptr @.omp_offloading.descriptor_unreg) // OPENMP-NEXT: ret void // OPENMP-NEXT: } diff --git a/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp b/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp index 7241d15ed1c6..8b6f9ea1f4cc 100644 --- a/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp +++ b/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp @@ -232,12 +232,13 @@ void createRegisterFunction(Module &M, GlobalVariable *BinDesc, // Construct function body IRBuilder<> Builder(BasicBlock::Create(C, "entry", Func)); + Builder.CreateCall(RegFuncC, BinDesc); + // Register the destructors with 'atexit'. This is expected by the CUDA // runtime and ensures that we clean up before dynamic objects are destroyed. - // This needs to be done before the runtime is called and registers its own. + // This needs to be done after plugin initialization to ensure that it is + // called before the plugin runtime is destroyed. Builder.CreateCall(AtExit, UnregFunc); - - Builder.CreateCall(RegFuncC, BinDesc); Builder.CreateRetVoid(); // Add this function to constructors. diff --git a/offload/include/PluginManager.h b/offload/include/PluginManager.h index eece7525e25e..1d6804da75d9 100644 --- a/offload/include/PluginManager.h +++ b/offload/include/PluginManager.h @@ -13,10 +13,11 @@ #ifndef OMPTARGET_PLUGIN_MANAGER_H #define OMPTARGET_PLUGIN_MANAGER_H +#include "PluginInterface.h" + #include "DeviceImage.h" #include "ExclusiveAccess.h" #include "Shared/APITypes.h" -#include "Shared/PluginAPI.h" #include "Shared/Requirements.h" #include "device.h" @@ -34,38 +35,7 @@ #include #include -struct PluginManager; - -/// Plugin adaptors should be created via `PluginAdaptorTy::create` which will -/// invoke the constructor and call `PluginAdaptorTy::init`. Eventual errors are -/// reported back to the caller, otherwise a valid and initialized adaptor is -/// returned. -struct PluginAdaptorTy { - /// Try to create a plugin adaptor from a filename. - static llvm::Expected> - create(const std::string &Name); - - /// Name of the shared object file representing the plugin. - std::string Name; - - /// Access to the shared object file representing the plugin. - std::unique_ptr LibraryHandler; - -#define PLUGIN_API_HANDLE(NAME) \ - using NAME##_ty = decltype(__tgt_rtl_##NAME); \ - NAME##_ty *NAME = nullptr; - -#include "Shared/PluginAPI.inc" -#undef PLUGIN_API_HANDLE - - /// Create a plugin adaptor for filename \p Name with a dynamic library \p DL. - PluginAdaptorTy(const std::string &Name, - std::unique_ptr DL); - - /// Initialize the plugin adaptor, this can fail in which case the adaptor is - /// useless. - llvm::Error init(); -}; +using GenericPluginTy = llvm::omp::target::plugin::GenericPluginTy; /// Struct for the data required to handle plugins struct PluginManager { @@ -80,6 +50,8 @@ struct PluginManager { void init(); + void deinit(); + // Register a shared library with all (compatible) RTLs. void registerLib(__tgt_bin_desc *Desc); @@ -92,10 +64,9 @@ struct PluginManager { std::make_unique(TgtBinDesc, TgtDeviceImage)); } - /// Initialize as many devices as possible for this plugin adaptor. Devices - /// that fail to initialize are ignored. Returns the offset the devices were - /// registered at. - void initDevices(PluginAdaptorTy &RTL); + /// Initialize as many devices as possible for this plugin. Devices that fail + /// to initialize are ignored. + void initDevices(GenericPluginTy &RTL); /// Return the device presented to the user as device \p DeviceNo if it is /// initialized and ready. Otherwise return an error explaining the problem. @@ -151,8 +122,8 @@ struct PluginManager { // Initialize all plugins. void initAllPlugins(); - /// Iterator range for all plugin adaptors (in use or not, but always valid). - auto pluginAdaptors() { return llvm::make_pointee_range(PluginAdaptors); } + /// Iterator range for all plugins (in use or not, but always valid). + auto plugins() { return llvm::make_pointee_range(Plugins); } /// Return the user provided requirements. int64_t getRequirements() const { return Requirements.getRequirements(); } @@ -164,14 +135,14 @@ private: bool RTLsLoaded = false; llvm::SmallVector<__tgt_bin_desc *> DelayedBinDesc; - // List of all plugin adaptors, in use or not. - llvm::SmallVector> PluginAdaptors; + // List of all plugins, in use or not. + llvm::SmallVector> Plugins; - // Mapping of plugin adaptors to offsets in the device table. - llvm::DenseMap DeviceOffsets; + // Mapping of plugins to offsets in the device table. + llvm::DenseMap DeviceOffsets; - // Mapping of plugin adaptors to the number of used devices. - llvm::DenseMap DeviceUsed; + // Mapping of plugins to the number of used devices. + llvm::DenseMap DeviceUsed; // Set of all device images currently in use. llvm::DenseSet UsedImages; diff --git a/offload/include/device.h b/offload/include/device.h index bd2829722bb3..fd6e5fba5fc5 100644 --- a/offload/include/device.h +++ b/offload/include/device.h @@ -33,17 +33,19 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" +#include "PluginInterface.h" +using GenericPluginTy = llvm::omp::target::plugin::GenericPluginTy; + // Forward declarations. -struct PluginAdaptorTy; struct __tgt_bin_desc; struct __tgt_target_table; struct DeviceTy { int32_t DeviceID; - PluginAdaptorTy *RTL; + GenericPluginTy *RTL; int32_t RTLDeviceID; - DeviceTy(PluginAdaptorTy *RTL, int32_t DeviceID, int32_t RTLDeviceID); + DeviceTy(GenericPluginTy *RTL, int32_t DeviceID, int32_t RTLDeviceID); // DeviceTy is not copyable DeviceTy(const DeviceTy &D) = delete; DeviceTy &operator=(const DeviceTy &D) = delete; diff --git a/offload/plugins-nextgen/CMakeLists.txt b/offload/plugins-nextgen/CMakeLists.txt index df625e97c7eb..d1079f8a3e9c 100644 --- a/offload/plugins-nextgen/CMakeLists.txt +++ b/offload/plugins-nextgen/CMakeLists.txt @@ -14,7 +14,7 @@ set(common_dir ${CMAKE_CURRENT_SOURCE_DIR}/common) add_subdirectory(common) function(add_target_library target_name lib_name) - add_llvm_library(${target_name} SHARED + add_llvm_library(${target_name} STATIC LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD} AggressiveInstCombine @@ -46,27 +46,14 @@ function(add_target_library target_name lib_name) ) llvm_update_compile_flags(${target_name}) + target_include_directories(${target_name} PUBLIC ${common_dir}/include) target_link_libraries(${target_name} PRIVATE PluginCommon ${OPENMP_PTHREAD_LIB}) target_compile_definitions(${target_name} PRIVATE TARGET_NAME=${lib_name}) target_compile_definitions(${target_name} PRIVATE DEBUG_PREFIX="TARGET ${lib_name} RTL") - - if(CMAKE_SYSTEM_NAME MATCHES "FreeBSD") - # On FreeBSD, the 'environ' symbol is undefined at link time, but resolved by - # the dynamic linker at runtime. Therefore, allow the symbol to be undefined - # when creating a shared library. - target_link_libraries(${target_name} PRIVATE "-Wl,--allow-shlib-undefined") - else() - target_link_libraries(${target_name} PRIVATE "-Wl,-z,defs") - endif() - - if(LIBOMP_HAVE_VERSION_SCRIPT_FLAG) - target_link_libraries(${target_name} PRIVATE - "-Wl,--version-script=${common_dir}/../exports") - endif() - set_target_properties(${target_name} PROPERTIES CXX_VISIBILITY_PRESET protected) + set_target_properties(${target_name} PROPERTIES POSITION_INDEPENDENT_CODE ON) endfunction() foreach(plugin IN LISTS LIBOMPTARGET_PLUGINS_TO_BUILD) diff --git a/offload/plugins-nextgen/amdgpu/CMakeLists.txt b/offload/plugins-nextgen/amdgpu/CMakeLists.txt index f5f7096137c2..738183f8945e 100644 --- a/offload/plugins-nextgen/amdgpu/CMakeLists.txt +++ b/offload/plugins-nextgen/amdgpu/CMakeLists.txt @@ -57,8 +57,3 @@ else() libomptarget_say("Not generating AMDGPU tests, no supported devices detected." " Use 'LIBOMPTARGET_FORCE_AMDGPU_TESTS' to override.") endif() - -# Install plugin under the lib destination folder. -install(TARGETS omptarget.rtl.amdgpu LIBRARY DESTINATION "${OFFLOAD_INSTALL_LIBDIR}") -set_target_properties(omptarget.rtl.amdgpu PROPERTIES - INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/..") diff --git a/offload/plugins-nextgen/amdgpu/src/rtl.cpp b/offload/plugins-nextgen/amdgpu/src/rtl.cpp index 00650b801b42..295685fceaa4 100644 --- a/offload/plugins-nextgen/amdgpu/src/rtl.cpp +++ b/offload/plugins-nextgen/amdgpu/src/rtl.cpp @@ -3064,10 +3064,6 @@ struct AMDGPUPluginTy final : public GenericPluginTy { // HSA functions from now on, e.g., hsa_shut_down. Initialized = true; -#ifdef OMPT_SUPPORT - ompt::connectLibrary(); -#endif - // Register event handler to detect memory errors on the devices. Status = hsa_amd_register_system_event_handler(eventHandler, nullptr); if (auto Err = Plugin::check( @@ -3155,6 +3151,8 @@ struct AMDGPUPluginTy final : public GenericPluginTy { Triple::ArchType getTripleArch() const override { return Triple::amdgcn; } + const char *getName() const override { return GETNAME(TARGET_NAME); } + /// Get the ELF code for recognizing the compatible image binary. uint16_t getMagicElfBits() const override { return ELF::EM_AMDGPU; } @@ -3387,8 +3385,6 @@ Error AMDGPUKernelTy::printLaunchInfoDetails(GenericDeviceTy &GenericDevice, return Plugin::success(); } -GenericPluginTy *PluginTy::createPlugin() { return new AMDGPUPluginTy(); } - template static Error Plugin::check(int32_t Code, const char *ErrFmt, ArgsTy... Args) { hsa_status_t ResultCode = static_cast(Code); @@ -3476,3 +3472,9 @@ void *AMDGPUDeviceTy::allocate(size_t Size, void *, TargetAllocTy Kind) { } // namespace target } // namespace omp } // namespace llvm + +extern "C" { +llvm::omp::target::plugin::GenericPluginTy *createPlugin_amdgpu() { + return new llvm::omp::target::plugin::AMDGPUPluginTy(); +} +} diff --git a/offload/plugins-nextgen/common/CMakeLists.txt b/offload/plugins-nextgen/common/CMakeLists.txt index acf0af63f050..a470dcee6d85 100644 --- a/offload/plugins-nextgen/common/CMakeLists.txt +++ b/offload/plugins-nextgen/common/CMakeLists.txt @@ -66,6 +66,4 @@ target_include_directories(PluginCommon PUBLIC ${LIBOMPTARGET_INCLUDE_DIR} ) -set_target_properties(PluginCommon PROPERTIES - POSITION_INDEPENDENT_CODE ON - CXX_VISIBILITY_PRESET protected) +set_target_properties(PluginCommon PROPERTIES POSITION_INDEPENDENT_CODE ON) diff --git a/offload/plugins-nextgen/common/include/PluginInterface.h b/offload/plugins-nextgen/common/include/PluginInterface.h index 79e8464bfda5..e7a008f3a857 100644 --- a/offload/plugins-nextgen/common/include/PluginInterface.h +++ b/offload/plugins-nextgen/common/include/PluginInterface.h @@ -1010,6 +1010,9 @@ struct GenericPluginTy { /// Get the target triple of this plugin. virtual Triple::ArchType getTripleArch() const = 0; + /// Get the constant name identifier for this plugin. + virtual const char *getName() const = 0; + /// Allocate a structure using the internal allocator. template Ty *allocate() { return reinterpret_cast(Allocator.Allocate(sizeof(Ty), alignof(Ty))); @@ -1226,7 +1229,7 @@ namespace Plugin { /// Create a success error. This is the same as calling Error::success(), but /// it is recommended to use this one for consistency with Plugin::error() and /// Plugin::check(). -static Error success() { return Error::success(); } +static inline Error success() { return Error::success(); } /// Create a string error. template @@ -1246,95 +1249,6 @@ template static Error check(int32_t ErrorCode, const char *ErrFmt, ArgsTy... Args); } // namespace Plugin -/// Class for simplifying the getter operation of the plugin. Anywhere on the -/// code, the current plugin can be retrieved by Plugin::get(). The class also -/// declares functions to create plugin-specific object instances. The check(), -/// createPlugin(), createDevice() and createGlobalHandler() functions should be -/// defined by each plugin implementation. -class PluginTy { - // Reference to the plugin instance. - static GenericPluginTy *SpecificPlugin; - - PluginTy() { - if (auto Err = init()) - REPORT("Failed to initialize plugin: %s\n", - toString(std::move(Err)).data()); - } - - ~PluginTy() { - if (auto Err = deinit()) - REPORT("Failed to deinitialize plugin: %s\n", - toString(std::move(Err)).data()); - } - - PluginTy(const PluginTy &) = delete; - void operator=(const PluginTy &) = delete; - - /// Create and intialize the plugin instance. - static Error init() { - assert(!SpecificPlugin && "Plugin already created"); - - // Create the specific plugin. - SpecificPlugin = createPlugin(); - assert(SpecificPlugin && "Plugin was not created"); - - // Initialize the plugin. - return SpecificPlugin->init(); - } - - // Deinitialize and destroy the plugin instance. - static Error deinit() { - assert(SpecificPlugin && "Plugin no longer valid"); - - for (int32_t DevNo = 0, NumDev = SpecificPlugin->getNumDevices(); - DevNo < NumDev; ++DevNo) - if (auto Err = SpecificPlugin->deinitDevice(DevNo)) - return Err; - - // Deinitialize the plugin. - if (auto Err = SpecificPlugin->deinit()) - return Err; - - // Delete the plugin instance. - delete SpecificPlugin; - - // Invalidate the plugin reference. - SpecificPlugin = nullptr; - - return Plugin::success(); - } - -public: - /// Initialize the plugin if needed. The plugin could have been initialized by - /// a previous call to Plugin::get(). - static Error initIfNeeded() { - // Trigger the initialization if needed. - get(); - - return Error::success(); - } - - /// Get a reference (or create if it was not created) to the plugin instance. - static GenericPluginTy &get() { - // This static variable will initialize the underlying plugin instance in - // case there was no previous explicit initialization. The initialization is - // thread safe. - static PluginTy Plugin; - - assert(SpecificPlugin && "Plugin is not active"); - return *SpecificPlugin; - } - - /// Get a reference to the plugin with a specific plugin-specific type. - template static Ty &get() { return static_cast(get()); } - - /// Indicate whether the plugin is active. - static bool isActive() { return SpecificPlugin != nullptr; } - - /// Create a plugin instance. - static GenericPluginTy *createPlugin(); -}; - /// Auxiliary interface class for GenericDeviceResourceManagerTy. This class /// acts as a reference to a device resource, such as a stream, and requires /// some basic functions to be implemented. The derived class should define an diff --git a/offload/plugins-nextgen/common/include/Utils/ELF.h b/offload/plugins-nextgen/common/include/Utils/ELF.h index f87e0a5ed02b..dcfdb5bd7b03 100644 --- a/offload/plugins-nextgen/common/include/Utils/ELF.h +++ b/offload/plugins-nextgen/common/include/Utils/ELF.h @@ -13,8 +13,6 @@ #ifndef LLVM_OPENMP_LIBOMPTARGET_PLUGINS_ELF_UTILS_H #define LLVM_OPENMP_LIBOMPTARGET_PLUGINS_ELF_UTILS_H -#include "Shared/PluginAPI.h" - #include "llvm/Object/ELF.h" #include "llvm/Object/ELFObjectFile.h" diff --git a/offload/plugins-nextgen/common/src/JIT.cpp b/offload/plugins-nextgen/common/src/JIT.cpp index 9eb610cab4de..9d58e6060646 100644 --- a/offload/plugins-nextgen/common/src/JIT.cpp +++ b/offload/plugins-nextgen/common/src/JIT.cpp @@ -56,28 +56,6 @@ bool isImageBitcode(const __tgt_device_image &Image) { return identify_magic(Binary) == file_magic::bitcode; } -std::once_flag InitFlag; - -void init(Triple TT) { - codegen::RegisterCodeGenFlags(); -#ifdef LIBOMPTARGET_JIT_NVPTX - if (TT.isNVPTX()) { - LLVMInitializeNVPTXTargetInfo(); - LLVMInitializeNVPTXTarget(); - LLVMInitializeNVPTXTargetMC(); - LLVMInitializeNVPTXAsmPrinter(); - } -#endif -#ifdef LIBOMPTARGET_JIT_AMDGPU - if (TT.isAMDGPU()) { - LLVMInitializeAMDGPUTargetInfo(); - LLVMInitializeAMDGPUTarget(); - LLVMInitializeAMDGPUTargetMC(); - LLVMInitializeAMDGPUAsmPrinter(); - } -#endif -} - Expected> createModuleFromMemoryBuffer(std::unique_ptr &MB, LLVMContext &Context) { @@ -148,7 +126,23 @@ createTargetMachine(Module &M, std::string CPU, unsigned OptLevel) { } // namespace JITEngine::JITEngine(Triple::ArchType TA) : TT(Triple::getArchTypeName(TA)) { - std::call_once(InitFlag, init, TT); + codegen::RegisterCodeGenFlags(); +#ifdef LIBOMPTARGET_JIT_NVPTX + if (TT.isNVPTX()) { + LLVMInitializeNVPTXTargetInfo(); + LLVMInitializeNVPTXTarget(); + LLVMInitializeNVPTXTargetMC(); + LLVMInitializeNVPTXAsmPrinter(); + } +#endif +#ifdef LIBOMPTARGET_JIT_AMDGPU + if (TT.isAMDGPU()) { + LLVMInitializeAMDGPUTargetInfo(); + LLVMInitializeAMDGPUTarget(); + LLVMInitializeAMDGPUTargetMC(); + LLVMInitializeAMDGPUAsmPrinter(); + } +#endif } void JITEngine::opt(TargetMachine *TM, TargetLibraryInfoImpl *TLII, Module &M, diff --git a/offload/plugins-nextgen/common/src/PluginInterface.cpp b/offload/plugins-nextgen/common/src/PluginInterface.cpp index 8de93ba17a56..fae197527850 100644 --- a/offload/plugins-nextgen/common/src/PluginInterface.cpp +++ b/offload/plugins-nextgen/common/src/PluginInterface.cpp @@ -13,7 +13,6 @@ #include "Shared/APITypes.h" #include "Shared/Debug.h" #include "Shared/Environment.h" -#include "Shared/PluginAPI.h" #include "GlobalHandler.h" #include "JIT.h" @@ -39,8 +38,6 @@ using namespace omp; using namespace target; using namespace plugin; -GenericPluginTy *PluginTy::SpecificPlugin = nullptr; - // TODO: Fix any thread safety issues for multi-threaded kernel recording. struct RecordReplayTy { @@ -2035,205 +2032,3 @@ bool llvm::omp::target::plugin::libomptargetSupportsRPC() { return false; #endif } - -/// Exposed library API function, basically wrappers around the GenericDeviceTy -/// functionality with the same name. All non-async functions are redirected -/// to the async versions right away with a NULL AsyncInfoPtr. -#ifdef __cplusplus -extern "C" { -#endif - -int32_t __tgt_rtl_init_plugin() { - auto Err = PluginTy::initIfNeeded(); - if (Err) { - [[maybe_unused]] std::string ErrStr = toString(std::move(Err)); - DP("Failed to init plugin: %s", ErrStr.c_str()); - return OFFLOAD_FAIL; - } - - return OFFLOAD_SUCCESS; -} - -int32_t __tgt_rtl_is_valid_binary(__tgt_device_image *Image) { - if (!PluginTy::isActive()) - return false; - - return PluginTy::get().is_valid_binary(Image); -} - -int32_t __tgt_rtl_init_device(int32_t DeviceId) { - return PluginTy::get().init_device(DeviceId); -} - -int32_t __tgt_rtl_number_of_devices() { - return PluginTy::get().number_of_devices(); -} - -int64_t __tgt_rtl_init_requires(int64_t RequiresFlags) { - return PluginTy::get().init_requires(RequiresFlags); -} - -int32_t __tgt_rtl_is_data_exchangable(int32_t SrcDeviceId, - int32_t DstDeviceId) { - return PluginTy::get().is_data_exchangable(SrcDeviceId, DstDeviceId); -} - -int32_t __tgt_rtl_initialize_record_replay(int32_t DeviceId, int64_t MemorySize, - void *VAddr, bool isRecord, - bool SaveOutput, - uint64_t &ReqPtrArgOffset) { - return PluginTy::get().initialize_record_replay( - DeviceId, MemorySize, VAddr, isRecord, SaveOutput, ReqPtrArgOffset); -} - -int32_t __tgt_rtl_load_binary(int32_t DeviceId, __tgt_device_image *TgtImage, - __tgt_device_binary *Binary) { - return PluginTy::get().load_binary(DeviceId, TgtImage, Binary); -} - -void *__tgt_rtl_data_alloc(int32_t DeviceId, int64_t Size, void *HostPtr, - int32_t Kind) { - return PluginTy::get().data_alloc(DeviceId, Size, HostPtr, Kind); -} - -int32_t __tgt_rtl_data_delete(int32_t DeviceId, void *TgtPtr, int32_t Kind) { - return PluginTy::get().data_delete(DeviceId, TgtPtr, Kind); -} - -int32_t __tgt_rtl_data_lock(int32_t DeviceId, void *Ptr, int64_t Size, - void **LockedPtr) { - return PluginTy::get().data_lock(DeviceId, Ptr, Size, LockedPtr); -} - -int32_t __tgt_rtl_data_unlock(int32_t DeviceId, void *Ptr) { - return PluginTy::get().data_unlock(DeviceId, Ptr); -} - -int32_t __tgt_rtl_data_notify_mapped(int32_t DeviceId, void *HstPtr, - int64_t Size) { - return PluginTy::get().data_notify_mapped(DeviceId, HstPtr, Size); -} - -int32_t __tgt_rtl_data_notify_unmapped(int32_t DeviceId, void *HstPtr) { - return PluginTy::get().data_notify_unmapped(DeviceId, HstPtr); -} - -int32_t __tgt_rtl_data_submit(int32_t DeviceId, void *TgtPtr, void *HstPtr, - int64_t Size) { - return PluginTy::get().data_submit(DeviceId, TgtPtr, HstPtr, Size); -} - -int32_t __tgt_rtl_data_submit_async(int32_t DeviceId, void *TgtPtr, - void *HstPtr, int64_t Size, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().data_submit_async(DeviceId, TgtPtr, HstPtr, Size, - AsyncInfoPtr); -} - -int32_t __tgt_rtl_data_retrieve(int32_t DeviceId, void *HstPtr, void *TgtPtr, - int64_t Size) { - return PluginTy::get().data_retrieve(DeviceId, HstPtr, TgtPtr, Size); -} - -int32_t __tgt_rtl_data_retrieve_async(int32_t DeviceId, void *HstPtr, - void *TgtPtr, int64_t Size, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().data_retrieve_async(DeviceId, HstPtr, TgtPtr, Size, - AsyncInfoPtr); -} - -int32_t __tgt_rtl_data_exchange(int32_t SrcDeviceId, void *SrcPtr, - int32_t DstDeviceId, void *DstPtr, - int64_t Size) { - return PluginTy::get().data_exchange(SrcDeviceId, SrcPtr, DstDeviceId, DstPtr, - Size); -} - -int32_t __tgt_rtl_data_exchange_async(int32_t SrcDeviceId, void *SrcPtr, - int DstDeviceId, void *DstPtr, - int64_t Size, - __tgt_async_info *AsyncInfo) { - return PluginTy::get().data_exchange_async(SrcDeviceId, SrcPtr, DstDeviceId, - DstPtr, Size, AsyncInfo); -} - -int32_t __tgt_rtl_launch_kernel(int32_t DeviceId, void *TgtEntryPtr, - void **TgtArgs, ptrdiff_t *TgtOffsets, - KernelArgsTy *KernelArgs, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().launch_kernel(DeviceId, TgtEntryPtr, TgtArgs, - TgtOffsets, KernelArgs, AsyncInfoPtr); -} - -int32_t __tgt_rtl_synchronize(int32_t DeviceId, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().synchronize(DeviceId, AsyncInfoPtr); -} - -int32_t __tgt_rtl_query_async(int32_t DeviceId, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().query_async(DeviceId, AsyncInfoPtr); -} - -void __tgt_rtl_print_device_info(int32_t DeviceId) { - PluginTy::get().print_device_info(DeviceId); -} - -int32_t __tgt_rtl_create_event(int32_t DeviceId, void **EventPtr) { - return PluginTy::get().create_event(DeviceId, EventPtr); -} - -int32_t __tgt_rtl_record_event(int32_t DeviceId, void *EventPtr, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().record_event(DeviceId, EventPtr, AsyncInfoPtr); -} - -int32_t __tgt_rtl_wait_event(int32_t DeviceId, void *EventPtr, - __tgt_async_info *AsyncInfoPtr) { - return PluginTy::get().wait_event(DeviceId, EventPtr, AsyncInfoPtr); -} - -int32_t __tgt_rtl_sync_event(int32_t DeviceId, void *EventPtr) { - return PluginTy::get().sync_event(DeviceId, EventPtr); -} - -int32_t __tgt_rtl_destroy_event(int32_t DeviceId, void *EventPtr) { - return PluginTy::get().destroy_event(DeviceId, EventPtr); -} - -void __tgt_rtl_set_info_flag(uint32_t NewInfoLevel) { - return PluginTy::get().set_info_flag(NewInfoLevel); -} - -int32_t __tgt_rtl_init_async_info(int32_t DeviceId, - __tgt_async_info **AsyncInfoPtr) { - return PluginTy::get().init_async_info(DeviceId, AsyncInfoPtr); -} - -int32_t __tgt_rtl_init_device_info(int32_t DeviceId, - __tgt_device_info *DeviceInfo, - const char **ErrStr) { - return PluginTy::get().init_device_info(DeviceId, DeviceInfo, ErrStr); -} - -int32_t __tgt_rtl_set_device_offset(int32_t DeviceIdOffset) { - return PluginTy::get().set_device_offset(DeviceIdOffset); -} - -int32_t __tgt_rtl_use_auto_zero_copy(int32_t DeviceId) { - return PluginTy::get().use_auto_zero_copy(DeviceId); -} - -int32_t __tgt_rtl_get_global(__tgt_device_binary Binary, uint64_t Size, - const char *Name, void **DevicePtr) { - return PluginTy::get().get_global(Binary, Size, Name, DevicePtr); -} - -int32_t __tgt_rtl_get_function(__tgt_device_binary Binary, const char *Name, - void **KernelPtr) { - return PluginTy::get().get_function(Binary, Name, KernelPtr); -} - -#ifdef __cplusplus -} -#endif diff --git a/offload/plugins-nextgen/cuda/CMakeLists.txt b/offload/plugins-nextgen/cuda/CMakeLists.txt index 0284bd22d2a4..dd684bb22343 100644 --- a/offload/plugins-nextgen/cuda/CMakeLists.txt +++ b/offload/plugins-nextgen/cuda/CMakeLists.txt @@ -51,8 +51,3 @@ else() libomptarget_say("Not generating NVIDIA tests, no supported devices detected." " Use 'LIBOMPTARGET_FORCE_NVIDIA_TESTS' to override.") endif() - -# Install plugin under the lib destination folder. -install(TARGETS omptarget.rtl.cuda LIBRARY DESTINATION "${OFFLOAD_INSTALL_LIBDIR}") -set_target_properties(omptarget.rtl.cuda PROPERTIES - INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/..") diff --git a/offload/plugins-nextgen/cuda/src/rtl.cpp b/offload/plugins-nextgen/cuda/src/rtl.cpp index fc74c6aa23fd..b260334baa18 100644 --- a/offload/plugins-nextgen/cuda/src/rtl.cpp +++ b/offload/plugins-nextgen/cuda/src/rtl.cpp @@ -1342,10 +1342,6 @@ struct CUDAPluginTy final : public GenericPluginTy { return 0; } -#ifdef OMPT_SUPPORT - ompt::connectLibrary(); -#endif - if (Res == CUDA_ERROR_NO_DEVICE) { // Do not initialize if there are no devices. DP("There are no devices supporting CUDA.\n"); @@ -1390,6 +1386,8 @@ struct CUDAPluginTy final : public GenericPluginTy { return Triple::nvptx64; } + const char *getName() const override { return GETNAME(TARGET_NAME); } + /// Check whether the image is compatible with the available CUDA devices. Expected isELFCompatible(StringRef Image) const override { auto ElfOrErr = @@ -1495,8 +1493,6 @@ Error CUDADeviceTy::dataExchangeImpl(const void *SrcPtr, return Plugin::check(Res, "Error in cuMemcpyDtoDAsync: %s"); } -GenericPluginTy *PluginTy::createPlugin() { return new CUDAPluginTy(); } - template static Error Plugin::check(int32_t Code, const char *ErrFmt, ArgsTy... Args) { CUresult ResultCode = static_cast(Code); @@ -1516,3 +1512,9 @@ static Error Plugin::check(int32_t Code, const char *ErrFmt, ArgsTy... Args) { } // namespace target } // namespace omp } // namespace llvm + +extern "C" { +llvm::omp::target::plugin::GenericPluginTy *createPlugin_cuda() { + return new llvm::omp::target::plugin::CUDAPluginTy(); +} +} diff --git a/offload/plugins-nextgen/host/CMakeLists.txt b/offload/plugins-nextgen/host/CMakeLists.txt index 1d000442c84d..72b5681283fe 100644 --- a/offload/plugins-nextgen/host/CMakeLists.txt +++ b/offload/plugins-nextgen/host/CMakeLists.txt @@ -31,14 +31,6 @@ else() target_include_directories(omptarget.rtl.host PRIVATE dynamic_ffi) endif() -# Install plugin under the lib destination folder. -install(TARGETS omptarget.rtl.host - LIBRARY DESTINATION "${OFFLOAD_INSTALL_LIBDIR}") -set_target_properties(omptarget.rtl.host PROPERTIES - INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/.." - POSITION_INDEPENDENT_CODE ON - CXX_VISIBILITY_PRESET protected) - target_include_directories(omptarget.rtl.host PRIVATE ${LIBOMPTARGET_INCLUDE_DIR}) diff --git a/offload/plugins-nextgen/host/src/rtl.cpp b/offload/plugins-nextgen/host/src/rtl.cpp index 4bdcae3dd6a1..409b44b1640a 100644 --- a/offload/plugins-nextgen/host/src/rtl.cpp +++ b/offload/plugins-nextgen/host/src/rtl.cpp @@ -385,10 +385,6 @@ struct GenELF64PluginTy final : public GenericPluginTy { /// Initialize the plugin and return the number of devices. Expected initImpl() override { -#ifdef OMPT_SUPPORT - ompt::connectLibrary(); -#endif - #ifdef USES_DYNAMIC_FFI if (auto Err = Plugin::check(ffi_init(), "Failed to initialize libffi")) return std::move(Err); @@ -445,9 +441,9 @@ struct GenELF64PluginTy final : public GenericPluginTy { return llvm::Triple::UnknownArch; #endif } -}; -GenericPluginTy *PluginTy::createPlugin() { return new GenELF64PluginTy(); } + const char *getName() const override { return GETNAME(TARGET_NAME); } +}; template static Error Plugin::check(int32_t Code, const char *ErrMsg, ArgsTy... Args) { @@ -462,3 +458,9 @@ static Error Plugin::check(int32_t Code, const char *ErrMsg, ArgsTy... Args) { } // namespace target } // namespace omp } // namespace llvm + +extern "C" { +llvm::omp::target::plugin::GenericPluginTy *createPlugin_host() { + return new llvm::omp::target::plugin::GenELF64PluginTy(); +} +} diff --git a/offload/src/CMakeLists.txt b/offload/src/CMakeLists.txt index eda5a85ff1ab..8fe6d19d83eb 100644 --- a/offload/src/CMakeLists.txt +++ b/offload/src/CMakeLists.txt @@ -65,6 +65,10 @@ target_compile_definitions(omptarget PRIVATE DEBUG_PREFIX="omptarget" ) +foreach(plugin IN LISTS LIBOMPTARGET_PLUGINS_TO_BUILD) + target_link_libraries(omptarget PRIVATE omptarget.rtl.${plugin}) +endforeach() + target_compile_options(omptarget PUBLIC ${offload_compile_flags}) target_link_options(omptarget PUBLIC ${offload_link_flags}) diff --git a/offload/src/OffloadRTL.cpp b/offload/src/OffloadRTL.cpp index dd75b1b18150..29b573a27d08 100644 --- a/offload/src/OffloadRTL.cpp +++ b/offload/src/OffloadRTL.cpp @@ -50,6 +50,7 @@ void deinitRuntime() { if (RefCount == 1) { DP("Deinit offload library!\n"); + PM->deinit(); delete PM; PM = nullptr; } diff --git a/offload/src/OpenMP/InteropAPI.cpp b/offload/src/OpenMP/InteropAPI.cpp index 1a995cde7816..bdbc440c64a2 100644 --- a/offload/src/OpenMP/InteropAPI.cpp +++ b/offload/src/OpenMP/InteropAPI.cpp @@ -230,14 +230,14 @@ void __tgt_interop_init(ident_t *LocRef, int32_t Gtid, } DeviceTy &Device = *DeviceOrErr; - if (!Device.RTL || !Device.RTL->init_device_info || + if (!Device.RTL || Device.RTL->init_device_info(DeviceId, &(InteropPtr)->device_info, &(InteropPtr)->err_str)) { delete InteropPtr; InteropPtr = omp_interop_none; } if (InteropType == kmp_interop_type_tasksync) { - if (!Device.RTL || !Device.RTL->init_async_info || + if (!Device.RTL || Device.RTL->init_async_info(DeviceId, &(InteropPtr)->async_info)) { delete InteropPtr; InteropPtr = omp_interop_none; diff --git a/offload/src/PluginManager.cpp b/offload/src/PluginManager.cpp index dbb556c179e5..191afa345641 100644 --- a/offload/src/PluginManager.cpp +++ b/offload/src/PluginManager.cpp @@ -23,85 +23,25 @@ using namespace llvm::sys; PluginManager *PM = nullptr; -Expected> -PluginAdaptorTy::create(const std::string &Name) { - DP("Attempting to load library '%s'...\n", Name.c_str()); - TIMESCOPE_WITH_NAME_AND_IDENT(Name, (const ident_t *)nullptr); - - std::string ErrMsg; - auto LibraryHandler = std::make_unique( - DynamicLibrary::getPermanentLibrary(Name.c_str(), &ErrMsg)); - - if (!LibraryHandler->isValid()) { - // Library does not exist or cannot be found. - return createStringError(inconvertibleErrorCode(), - "Unable to load library '%s': %s!\n", Name.c_str(), - ErrMsg.c_str()); - } - - DP("Successfully loaded library '%s'!\n", Name.c_str()); - auto PluginAdaptor = std::unique_ptr( - new PluginAdaptorTy(Name, std::move(LibraryHandler))); - if (auto Err = PluginAdaptor->init()) - return Err; - return std::move(PluginAdaptor); -} - -PluginAdaptorTy::PluginAdaptorTy(const std::string &Name, - std::unique_ptr DL) - : Name(Name), LibraryHandler(std::move(DL)) {} - -Error PluginAdaptorTy::init() { - -#define PLUGIN_API_HANDLE(NAME) \ - NAME = reinterpret_cast( \ - LibraryHandler->getAddressOfSymbol(GETNAME(__tgt_rtl_##NAME))); \ - if (!NAME) { \ - return createStringError(inconvertibleErrorCode(), \ - "Invalid plugin as necessary interface function " \ - "(%s) was not found.\n", \ - std::string(#NAME).c_str()); \ - } - -#include "Shared/PluginAPI.inc" -#undef PLUGIN_API_HANDLE - - // Remove plugin on failure to call optional init_plugin - int32_t Rc = init_plugin(); - if (Rc != OFFLOAD_SUCCESS) { - return createStringError(inconvertibleErrorCode(), - "Unable to initialize library '%s': %u!\n", - Name.c_str(), Rc); - } - - // No devices are supported by this RTL? - int32_t NumberOfPluginDevices = number_of_devices(); - if (!NumberOfPluginDevices) { - return createStringError(inconvertibleErrorCode(), - "No devices supported in this RTL\n"); - } - - DP("Registered '%s' with %d plugin visible devices!\n", Name.c_str(), - NumberOfPluginDevices); - return Error::success(); -} +// Every plugin exports this method to create an instance of the plugin type. +#define PLUGIN_TARGET(Name) extern "C" GenericPluginTy *createPlugin_##Name(); +#include "Shared/Targets.def" void PluginManager::init() { TIMESCOPE(); DP("Loading RTLs...\n"); - // Attempt to open all the plugins and, if they exist, check if the interface - // is correct and if they are supporting any devices. + // Attempt to create an instance of each supported plugin. #define PLUGIN_TARGET(Name) \ do { \ - auto PluginAdaptorOrErr = \ - PluginAdaptorTy::create("libomptarget.rtl." #Name ".so"); \ - if (!PluginAdaptorOrErr) { \ - [[maybe_unused]] std::string InfoMsg = \ - toString(PluginAdaptorOrErr.takeError()); \ - DP("%s", InfoMsg.c_str()); \ + auto Plugin = std::unique_ptr(createPlugin_##Name()); \ + if (auto Err = Plugin->init()) { \ + [[maybe_unused]] std::string InfoMsg = toString(std::move(Err)); \ + DP("Failed to init plugin: %s\n", InfoMsg.c_str()); \ } else { \ - PluginAdaptors.push_back(std::move(*PluginAdaptorOrErr)); \ + DP("Registered plugin %s with %d visible device(s)\n", \ + Plugin->getName(), Plugin->number_of_devices()); \ + Plugins.emplace_back(std::move(Plugin)); \ } \ } while (false); #include "Shared/Targets.def" @@ -109,15 +49,29 @@ void PluginManager::init() { DP("RTLs loaded!\n"); } -void PluginManager::initDevices(PluginAdaptorTy &RTL) { +void PluginManager::deinit() { + TIMESCOPE(); + DP("Unloading RTLs...\n"); + + for (auto &Plugin : Plugins) { + if (auto Err = Plugin->deinit()) { + [[maybe_unused]] std::string InfoMsg = toString(std::move(Err)); + DP("Failed to deinit plugin: %s\n", InfoMsg.c_str()); + } + Plugin.release(); + } + + DP("RTLs unloaded!\n"); +} + +void PluginManager::initDevices(GenericPluginTy &RTL) { // If this RTL has already been initialized. if (PM->DeviceOffsets.contains(&RTL)) return; TIMESCOPE(); // If this RTL is not already in use, initialize it. - assert(RTL.number_of_devices() > 0 && - "Tried to initialize useless plugin adaptor"); + assert(RTL.number_of_devices() > 0 && "Tried to initialize useless plugin!"); // Initialize the device information for the RTL we are about to use. auto ExclusiveDevicesAccessor = getExclusiveDevicesAccessor(); @@ -157,13 +111,12 @@ void PluginManager::initDevices(PluginAdaptorTy &RTL) { DeviceOffsets[&RTL] = DeviceOffset; DeviceUsed[&RTL] = NumberOfUserDevices; - DP("Plugin adaptor " DPxMOD " has index %d, exposes %d out of %d devices!\n", - DPxPTR(RTL.LibraryHandler.get()), DeviceOffset, NumberOfUserDevices, - RTL.number_of_devices()); + DP("Plugin has index %d, exposes %d out of %d devices!\n", DeviceOffset, + NumberOfUserDevices, RTL.number_of_devices()); } void PluginManager::initAllPlugins() { - for (auto &R : PluginAdaptors) + for (auto &R : Plugins) initDevices(*R); } @@ -216,19 +169,22 @@ void PluginManager::registerLib(__tgt_bin_desc *Desc) { // Obtain the image and information that was previously extracted. __tgt_device_image *Img = &DI.getExecutableImage(); - PluginAdaptorTy *FoundRTL = nullptr; + GenericPluginTy *FoundRTL = nullptr; // Scan the RTLs that have associated images until we find one that supports // the current image. - for (auto &R : PM->pluginAdaptors()) { + for (auto &R : PM->plugins()) { + if (!R.number_of_devices()) + continue; + if (!R.is_valid_binary(Img)) { DP("Image " DPxMOD " is NOT compatible with RTL %s!\n", - DPxPTR(Img->ImageStart), R.Name.c_str()); + DPxPTR(Img->ImageStart), R.getName()); continue; } DP("Image " DPxMOD " is compatible with RTL %s!\n", - DPxPTR(Img->ImageStart), R.Name.c_str()); + DPxPTR(Img->ImageStart), R.getName()); PM->initDevices(R); @@ -247,7 +203,7 @@ void PluginManager::registerLib(__tgt_bin_desc *Desc) { (PM->HostEntriesBeginToTransTable)[Desc->HostEntriesBegin]; DP("Registering image " DPxMOD " with RTL %s!\n", DPxPTR(Img->ImageStart), - R.Name.c_str()); + R.getName()); registerImageIntoTranslationTable(TransTable, PM->DeviceOffsets[&R], PM->DeviceUsed[&R], Img); @@ -282,11 +238,11 @@ void PluginManager::unregisterLib(__tgt_bin_desc *Desc) { // Obtain the image and information that was previously extracted. __tgt_device_image *Img = &DI.getExecutableImage(); - PluginAdaptorTy *FoundRTL = NULL; + GenericPluginTy *FoundRTL = NULL; // Scan the RTLs that have associated images until we find one that supports // the current image. We only need to scan RTLs that are already being used. - for (auto &R : PM->pluginAdaptors()) { + for (auto &R : PM->plugins()) { if (!DeviceOffsets.contains(&R)) continue; @@ -296,8 +252,7 @@ void PluginManager::unregisterLib(__tgt_bin_desc *Desc) { FoundRTL = &R; - DP("Unregistered image " DPxMOD " from RTL " DPxMOD "!\n", - DPxPTR(Img->ImageStart), DPxPTR(R.LibraryHandler.get())); + DP("Unregistered image " DPxMOD " from RTL\n", DPxPTR(Img->ImageStart)); break; } diff --git a/offload/src/device.cpp b/offload/src/device.cpp index 44a2facc8d3d..749b4c567f8e 100644 --- a/offload/src/device.cpp +++ b/offload/src/device.cpp @@ -64,7 +64,7 @@ int HostDataToTargetTy::addEventIfNecessary(DeviceTy &Device, return OFFLOAD_SUCCESS; } -DeviceTy::DeviceTy(PluginAdaptorTy *RTL, int32_t DeviceID, int32_t RTLDeviceID) +DeviceTy::DeviceTy(GenericPluginTy *RTL, int32_t DeviceID, int32_t RTLDeviceID) : DeviceID(DeviceID), RTL(RTL), RTLDeviceID(RTLDeviceID), MappingInfo(*this) {} @@ -192,7 +192,6 @@ int32_t DeviceTy::dataExchange(void *SrcPtr, DeviceTy &DstDev, void *DstPtr, RTLDeviceID, SrcPtr, DstDev.RTLDeviceID, DstPtr, Size, /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) if (!AsyncInfo) { - assert(RTL->data_exchange && "RTL->data_exchange is nullptr"); return RTL->data_exchange(RTLDeviceID, SrcPtr, DstDev.RTLDeviceID, DstPtr, Size); } diff --git a/offload/src/interface.cpp b/offload/src/interface.cpp index 557703632c62..763b051cc6d7 100644 --- a/offload/src/interface.cpp +++ b/offload/src/interface.cpp @@ -456,8 +456,6 @@ EXTERN void __tgt_set_info_flag(uint32_t NewInfoLevel) { assert(PM && "Runtime not initialized"); std::atomic &InfoLevel = getInfoLevelInternal(); InfoLevel.store(NewInfoLevel); - for (auto &R : PM->pluginAdaptors()) - R.set_info_flag(NewInfoLevel); } EXTERN int __tgt_print_device_info(int64_t DeviceId) { diff --git a/offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp b/offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp index 761e04e4c7bb..1e9a6a84d805 100644 --- a/offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp +++ b/offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp @@ -13,8 +13,6 @@ #include "omptarget.h" -#include "Shared/PluginAPI.h" - #include "llvm/Support/CommandLine.h" #include "llvm/Support/JSON.h" #include "llvm/Support/MemoryBuffer.h" diff --git a/offload/unittests/Plugins/NextgenPluginsTest.cpp b/offload/unittests/Plugins/NextgenPluginsTest.cpp index 635bd1637c90..479b3f614aed 100644 --- a/offload/unittests/Plugins/NextgenPluginsTest.cpp +++ b/offload/unittests/Plugins/NextgenPluginsTest.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// -#include "Shared/PluginAPI.h" #include "omptarget.h" #include "gtest/gtest.h" -- GitLab From fdede92d435068f31e7ea3a1dddb46d50343dd8c Mon Sep 17 00:00:00 2001 From: Zequan Wu Date: Thu, 9 May 2024 10:42:53 -0400 Subject: [PATCH 155/328] [lldb][DWARF] Sort ranges list in dwarf 5. (#91343) Dwarf 5 says "There is no requirement that the entries be ordered in any particular way" in 2.17.3 Non-Contiguous Address Ranges for rnglist. Some places assume the ranges are already sorted but it's not. For example, when [parsing function info](https://github.com/llvm/llvm-project/blob/bc8a42762057d7036f6871211e62b1c3efb2738a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp#L922-L927), it validates low and hi address of the function: GetMinRangeBase returns the first range entry base and GetMaxRangeEnd returns the last range end. If low >= hi, it stops parsing this function. This causes missing inline stack frames for those functions. This change fixes it and updates the test `lldb/test/Shell/SymbolFile/DWARF/x86/debug_rnglists.s` so that two ranges in `.debug_rnglists` are out of order and `image lookup -v -s lookup_rnglists` is still able to produce sorted ranges for the inner block. --- lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp | 1 + lldb/test/Shell/SymbolFile/DWARF/x86/debug_rnglists.s | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp index dabc595427df..3a57ec970b07 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp @@ -1062,6 +1062,7 @@ DWARFUnit::FindRnglistFromOffset(dw_offset_t offset) { ranges.Append(DWARFRangeList::Entry(llvm_range.LowPC, llvm_range.HighPC - llvm_range.LowPC)); } + ranges.Sort(); return ranges; } diff --git a/lldb/test/Shell/SymbolFile/DWARF/x86/debug_rnglists.s b/lldb/test/Shell/SymbolFile/DWARF/x86/debug_rnglists.s index 89b5d94c68c3..af8a1796f3ab 100644 --- a/lldb/test/Shell/SymbolFile/DWARF/x86/debug_rnglists.s +++ b/lldb/test/Shell/SymbolFile/DWARF/x86/debug_rnglists.s @@ -124,12 +124,12 @@ lookup_rnglists2: .Lrnglists_table_base0: .long .Ldebug_ranges0-.Lrnglists_table_base0 .Ldebug_ranges0: - .byte 4 # DW_RLE_offset_pair - .uleb128 .Lblock1_begin-rnglists # starting offset - .uleb128 .Lblock1_end-rnglists # ending offset .byte 4 # DW_RLE_offset_pair .uleb128 .Lblock2_begin-rnglists # starting offset .uleb128 .Lblock2_end-rnglists # ending offset + .byte 4 # DW_RLE_offset_pair + .uleb128 .Lblock1_begin-rnglists # starting offset + .uleb128 .Lblock1_end-rnglists # ending offset .byte 0 # DW_RLE_end_of_list .Ldebug_rnglist_table_end0: -- GitLab From aa9d467abaeb440dc70b64c0f35b8d5e731f3a19 Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Thu, 9 May 2024 16:03:16 +0100 Subject: [PATCH 156/328] Revert "[AArch64] NFC: Add RUN lines for streaming-compatible code." (#91599) Reverts llvm/llvm-project#90617 --- ...streaming-mode-fixed-length-and-combine.ll | 83 - ...treaming-mode-fixed-length-bit-counting.ll | 457 --- ...sve-streaming-mode-fixed-length-bitcast.ll | 97 - ...e-streaming-mode-fixed-length-bitselect.ll | 12 - ...treaming-mode-fixed-length-build-vector.ll | 88 - .../sve-streaming-mode-fixed-length-concat.ll | 228 -- ...e-streaming-mode-fixed-length-ext-loads.ll | 138 - ...ing-mode-fixed-length-extract-subvector.ll | 136 - ...ng-mode-fixed-length-extract-vector-elt.ll | 53 - ...e-streaming-mode-fixed-length-fcopysign.ll | 171 -- ...ve-streaming-mode-fixed-length-fp-arith.ll | 989 ------- ...streaming-mode-fixed-length-fp-compares.ll | 2486 ----------------- ...-streaming-mode-fixed-length-fp-convert.ll | 12 - ...aming-mode-fixed-length-fp-extend-trunc.ll | 270 -- .../sve-streaming-mode-fixed-length-fp-fma.ll | 116 - ...e-streaming-mode-fixed-length-fp-minmax.ll | 965 ------- ...eaming-mode-fixed-length-fp-reduce-fa64.ll | 25 - ...e-streaming-mode-fixed-length-fp-reduce.ll | 1058 ------- ...streaming-mode-fixed-length-fp-rounding.ll | 547 ---- ...e-streaming-mode-fixed-length-fp-select.ll | 99 - ...e-streaming-mode-fixed-length-fp-to-int.ll | 925 ------ ...-streaming-mode-fixed-length-fp-vselect.ll | 199 -- ...ing-mode-fixed-length-insert-vector-elt.ll | 172 -- ...e-streaming-mode-fixed-length-int-arith.ll | 371 --- ...treaming-mode-fixed-length-int-compares.ll | 154 - ...sve-streaming-mode-fixed-length-int-div.ll | 1145 -------- ...streaming-mode-fixed-length-int-extends.ll | 763 ----- ...eaming-mode-fixed-length-int-immediates.ll | 546 ---- ...sve-streaming-mode-fixed-length-int-log.ll | 229 -- ...-streaming-mode-fixed-length-int-minmax.ll | 325 --- ...ing-mode-fixed-length-int-mla-neon-fa64.ll | 7 - ...ve-streaming-mode-fixed-length-int-mulh.ll | 291 -- ...-streaming-mode-fixed-length-int-reduce.ll | 415 --- ...sve-streaming-mode-fixed-length-int-rem.ll | 1631 ----------- ...-streaming-mode-fixed-length-int-select.ll | 137 - ...-streaming-mode-fixed-length-int-shifts.ll | 313 --- ...e-streaming-mode-fixed-length-int-to-fp.ll | 822 ------ ...streaming-mode-fixed-length-int-vselect.ll | 123 - ...reaming-mode-fixed-length-limit-duplane.ll | 27 - .../sve-streaming-mode-fixed-length-loads.ll | 127 - ...-streaming-mode-fixed-length-log-reduce.ll | 436 --- ...streaming-mode-fixed-length-masked-load.ll | 954 ------- ...treaming-mode-fixed-length-masked-store.ll | 774 ----- ...eaming-mode-fixed-length-optimize-ptrue.ll | 216 -- ...streaming-mode-fixed-length-permute-rev.ll | 127 - ...g-mode-fixed-length-permute-zip-uzp-trn.ll | 320 --- .../sve-streaming-mode-fixed-length-ptest.ll | 72 - .../sve-streaming-mode-fixed-length-rev.ll | 159 -- ...e-streaming-mode-fixed-length-sdiv-pow2.ll | 132 - ...treaming-mode-fixed-length-splat-vector.ll | 182 -- .../sve-streaming-mode-fixed-length-stores.ll | 136 - ...e-streaming-mode-fixed-length-subvector.ll | 133 - ...treaming-mode-fixed-length-trunc-stores.ll | 38 - .../sve-streaming-mode-fixed-length-trunc.ll | 389 --- ...eaming-mode-fixed-length-vector-shuffle.ll | 151 - .../sve-streaming-mode-test-register-mov.ll | 21 - 56 files changed, 20992 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll index fd9259048df5..d81f725eaefc 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -15,12 +14,6 @@ define <4 x i8> @vls_sve_and_4xi8(<4 x i8> %b) nounwind { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_4xi8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d1, #0xff000000ff0000 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %c = and <4 x i8> %b, ret <4 x i8> %c } @@ -34,12 +27,6 @@ define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b) nounwind { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_8xi8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d1, #0xff00ff00ff00ff00 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %c = and <8 x i8> %b, ret <8 x i8> %c } @@ -53,12 +40,6 @@ define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b) nounwind { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_16xi8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v1.2d, #0xff00ff00ff00ff00 -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %c = and <16 x i8> %b, ret <16 x i8> %c } @@ -75,13 +56,6 @@ define <32 x i8> @vls_sve_and_32xi8(<32 x i8> %ap) nounwind { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_32xi8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v2.2d, #0xff00ff00ff00ff00 -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: and v1.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %b = and <32 x i8> %ap, ret <32 x i8> %b @@ -99,13 +73,6 @@ define <2 x i16> @vls_sve_and_2xi16(<2 x i16> %b) nounwind { ; CHECK-NEXT: ldr d0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_2xi16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov v0.s[0], wzr -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %c = and <2 x i16> %b, ret <2 x i16> %c } @@ -119,12 +86,6 @@ define <4 x i16> @vls_sve_and_4xi16(<4 x i16> %b) nounwind { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_4xi16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d1, #0xffff0000ffff0000 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %c = and <4 x i16> %b, ret <4 x i16> %c } @@ -138,12 +99,6 @@ define <8 x i16> @vls_sve_and_8xi16(<8 x i16> %b) nounwind { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_8xi16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v1.2d, #0xffff0000ffff0000 -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %c = and <8 x i16> %b, ret <8 x i16> %c } @@ -160,13 +115,6 @@ define <16 x i16> @vls_sve_and_16xi16(<16 x i16> %b) nounwind { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_16xi16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v2.2d, #0xffff0000ffff0000 -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: and v1.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %c = and <16 x i16> %b, ret <16 x i16> %c } @@ -180,13 +128,6 @@ define <2 x i32> @vls_sve_and_2xi32(<2 x i32> %b) nounwind { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_2xi32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov v0.s[0], wzr -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %c = and <2 x i32> %b, ret <2 x i32> %c } @@ -200,12 +141,6 @@ define <4 x i32> @vls_sve_and_4xi32(<4 x i32> %b) nounwind { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_4xi32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v1.2d, #0xffffffff00000000 -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %c = and <4 x i32> %b, ret <4 x i32> %c } @@ -222,13 +157,6 @@ define <8 x i32> @vls_sve_and_8xi32(<8 x i32> %b) nounwind { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_8xi32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v2.2d, #0xffffffff00000000 -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: and v1.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %c = and <8 x i32> %b, ret <8 x i32> %c } @@ -242,11 +170,6 @@ define <2 x i64> @vls_sve_and_2xi64(<2 x i64> %b) nounwind { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_2xi64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov v0.d[0], xzr -; NONEON-NOSVE-NEXT: ret %c = and <2 x i64> %b, ret <2 x i64> %c } @@ -262,12 +185,6 @@ define <4 x i64> @vls_sve_and_4xi64(<4 x i64> %b) nounwind { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: vls_sve_and_4xi64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov v0.d[0], xzr -; NONEON-NOSVE-NEXT: mov v1.d[0], xzr -; NONEON-NOSVE-NEXT: ret %c = and <4 x i64> %b, ret <4 x i64> %c } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll index 8f0378252a54..d547f99a0230 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -19,16 +18,6 @@ define <4 x i8> @ctlz_v4i8(<4 x i8> %op) { ; CHECK-NEXT: sub z0.h, z0.h, #8 // =0x8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d1, #0xff00ff00ff00ff -; NONEON-NOSVE-NEXT: mov w8, #8 // =0x8 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: dup v1.4h, w8 -; NONEON-NOSVE-NEXT: clz v0.4h, v0.4h -; NONEON-NOSVE-NEXT: sub v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = call <4 x i8> @llvm.ctlz.v4i8(<4 x i8> %op) ret <4 x i8> %res } @@ -41,11 +30,6 @@ define <8 x i8> @ctlz_v8i8(<8 x i8> %op) { ; CHECK-NEXT: clz z0.b, p0/m, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: clz v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %op) ret <8 x i8> %res } @@ -58,11 +42,6 @@ define <16 x i8> @ctlz_v16i8(<16 x i8> %op) { ; CHECK-NEXT: clz z0.b, p0/m, z0.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: clz v0.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %op) ret <16 x i8> %res } @@ -76,14 +55,6 @@ define void @ctlz_v32i8(ptr %a) { ; CHECK-NEXT: clz z1.b, p0/m, z1.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: clz v0.16b, v0.16b -; NONEON-NOSVE-NEXT: clz v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %res = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %op) store <32 x i8> %res, ptr %a @@ -100,16 +71,6 @@ define <2 x i16> @ctlz_v2i16(<2 x i16> %op) { ; CHECK-NEXT: sub z0.s, z0.s, #16 // =0x10 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d1, #0x00ffff0000ffff -; NONEON-NOSVE-NEXT: mov w8, #16 // =0x10 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: dup v1.2s, w8 -; NONEON-NOSVE-NEXT: clz v0.2s, v0.2s -; NONEON-NOSVE-NEXT: sub v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i16> @llvm.ctlz.v2i16(<2 x i16> %op) ret <2 x i16> %res } @@ -122,11 +83,6 @@ define <4 x i16> @ctlz_v4i16(<4 x i16> %op) { ; CHECK-NEXT: clz z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: clz v0.4h, v0.4h -; NONEON-NOSVE-NEXT: ret %res = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %op) ret <4 x i16> %res } @@ -139,11 +95,6 @@ define <8 x i16> @ctlz_v8i16(<8 x i16> %op) { ; CHECK-NEXT: clz z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: clz v0.8h, v0.8h -; NONEON-NOSVE-NEXT: ret %res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %op) ret <8 x i16> %res } @@ -157,14 +108,6 @@ define void @ctlz_v16i16(ptr %a) { ; CHECK-NEXT: clz z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: clz v0.8h, v0.8h -; NONEON-NOSVE-NEXT: clz v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %op) store <16 x i16> %res, ptr %a @@ -179,11 +122,6 @@ define <2 x i32> @ctlz_v2i32(<2 x i32> %op) { ; CHECK-NEXT: clz z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: clz v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %op) ret <2 x i32> %res } @@ -196,11 +134,6 @@ define <4 x i32> @ctlz_v4i32(<4 x i32> %op) { ; CHECK-NEXT: clz z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: clz v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %op) ret <4 x i32> %res } @@ -214,14 +147,6 @@ define void @ctlz_v8i32(ptr %a) { ; CHECK-NEXT: clz z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: clz v0.4s, v0.4s -; NONEON-NOSVE-NEXT: clz v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> %op) store <8 x i32> %res, ptr %a @@ -236,27 +161,6 @@ define <1 x i64> @ctlz_v1i64(<1 x i64> %op) { ; CHECK-NEXT: clz z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushr d1, d0, #1 -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ushr d1, d0, #2 -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ushr d1, d0, #4 -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ushr d1, d0, #8 -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ushr d1, d0, #16 -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ushr d1, d0, #32 -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: mvn v0.8b, v0.8b -; NONEON-NOSVE-NEXT: cnt v0.8b, v0.8b -; NONEON-NOSVE-NEXT: uaddlp v0.4h, v0.8b -; NONEON-NOSVE-NEXT: uaddlp v0.2s, v0.4h -; NONEON-NOSVE-NEXT: uaddlp v0.1d, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %op) ret <1 x i64> %res } @@ -269,27 +173,6 @@ define <2 x i64> @ctlz_v2i64(<2 x i64> %op) { ; CHECK-NEXT: clz z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushr v1.2d, v0.2d, #1 -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ushr v1.2d, v0.2d, #2 -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ushr v1.2d, v0.2d, #4 -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ushr v1.2d, v0.2d, #8 -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ushr v1.2d, v0.2d, #16 -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ushr v1.2d, v0.2d, #32 -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: mvn v0.16b, v0.16b -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v0.8h, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v0.4s, v0.8h -; NONEON-NOSVE-NEXT: uaddlp v0.2d, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %op) ret <2 x i64> %res } @@ -303,46 +186,6 @@ define void @ctlz_v4i64(ptr %a) { ; CHECK-NEXT: clz z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctlz_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ushr v2.2d, v0.2d, #1 -; NONEON-NOSVE-NEXT: ushr v3.2d, v1.2d, #1 -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v3.16b -; NONEON-NOSVE-NEXT: ushr v2.2d, v0.2d, #2 -; NONEON-NOSVE-NEXT: ushr v3.2d, v1.2d, #2 -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v3.16b -; NONEON-NOSVE-NEXT: ushr v2.2d, v0.2d, #4 -; NONEON-NOSVE-NEXT: ushr v3.2d, v1.2d, #4 -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v3.16b -; NONEON-NOSVE-NEXT: ushr v2.2d, v0.2d, #8 -; NONEON-NOSVE-NEXT: ushr v3.2d, v1.2d, #8 -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v3.16b -; NONEON-NOSVE-NEXT: ushr v2.2d, v0.2d, #16 -; NONEON-NOSVE-NEXT: ushr v3.2d, v1.2d, #16 -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v3.16b -; NONEON-NOSVE-NEXT: ushr v2.2d, v0.2d, #32 -; NONEON-NOSVE-NEXT: ushr v3.2d, v1.2d, #32 -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v3.16b -; NONEON-NOSVE-NEXT: mvn v0.16b, v0.16b -; NONEON-NOSVE-NEXT: mvn v1.16b, v1.16b -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: cnt v1.16b, v1.16b -; NONEON-NOSVE-NEXT: uaddlp v0.8h, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v1.8h, v1.16b -; NONEON-NOSVE-NEXT: uaddlp v0.4s, v0.8h -; NONEON-NOSVE-NEXT: uaddlp v1.4s, v1.8h -; NONEON-NOSVE-NEXT: uaddlp v0.2d, v0.4s -; NONEON-NOSVE-NEXT: uaddlp v1.2d, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %op) store <4 x i64> %res, ptr %a @@ -362,14 +205,6 @@ define <4 x i8> @ctpop_v4i8(<4 x i8> %op) { ; CHECK-NEXT: cnt z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d1, #0xff00ff00ff00ff -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: cnt v0.8b, v0.8b -; NONEON-NOSVE-NEXT: uaddlp v0.4h, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <4 x i8> @llvm.ctpop.v4i8(<4 x i8> %op) ret <4 x i8> %res } @@ -382,11 +217,6 @@ define <8 x i8> @ctpop_v8i8(<8 x i8> %op) { ; CHECK-NEXT: cnt z0.b, p0/m, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cnt v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %op) ret <8 x i8> %res } @@ -399,11 +229,6 @@ define <16 x i8> @ctpop_v16i8(<16 x i8> %op) { ; CHECK-NEXT: cnt z0.b, p0/m, z0.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %res = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %op) ret <16 x i8> %res } @@ -417,14 +242,6 @@ define void @ctpop_v32i8(ptr %a) { ; CHECK-NEXT: cnt z1.b, p0/m, z1.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: cnt v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %res = call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %op) store <32 x i8> %res, ptr %a @@ -440,15 +257,6 @@ define <2 x i16> @ctpop_v2i16(<2 x i16> %op) { ; CHECK-NEXT: cnt z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d1, #0x00ffff0000ffff -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: cnt v0.8b, v0.8b -; NONEON-NOSVE-NEXT: uaddlp v0.4h, v0.8b -; NONEON-NOSVE-NEXT: uaddlp v0.2s, v0.4h -; NONEON-NOSVE-NEXT: ret %res = call <2 x i16> @llvm.ctpop.v2i16(<2 x i16> %op) ret <2 x i16> %res } @@ -461,12 +269,6 @@ define <4 x i16> @ctpop_v4i16(<4 x i16> %op) { ; CHECK-NEXT: cnt z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cnt v0.8b, v0.8b -; NONEON-NOSVE-NEXT: uaddlp v0.4h, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> %op) ret <4 x i16> %res } @@ -479,12 +281,6 @@ define <8 x i16> @ctpop_v8i16(<8 x i16> %op) { ; CHECK-NEXT: cnt z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v0.8h, v0.16b -; NONEON-NOSVE-NEXT: ret %res = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %op) ret <8 x i16> %res } @@ -498,16 +294,6 @@ define void @ctpop_v16i16(ptr %a) { ; CHECK-NEXT: cnt z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: cnt v1.16b, v1.16b -; NONEON-NOSVE-NEXT: uaddlp v0.8h, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v1.8h, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %op) store <16 x i16> %res, ptr %a @@ -522,13 +308,6 @@ define <2 x i32> @ctpop_v2i32(<2 x i32> %op) { ; CHECK-NEXT: cnt z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cnt v0.8b, v0.8b -; NONEON-NOSVE-NEXT: uaddlp v0.4h, v0.8b -; NONEON-NOSVE-NEXT: uaddlp v0.2s, v0.4h -; NONEON-NOSVE-NEXT: ret %res = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %op) ret <2 x i32> %res } @@ -541,13 +320,6 @@ define <4 x i32> @ctpop_v4i32(<4 x i32> %op) { ; CHECK-NEXT: cnt z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v0.8h, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v0.4s, v0.8h -; NONEON-NOSVE-NEXT: ret %res = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %op) ret <4 x i32> %res } @@ -561,18 +333,6 @@ define void @ctpop_v8i32(ptr %a) { ; CHECK-NEXT: cnt z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: cnt v1.16b, v1.16b -; NONEON-NOSVE-NEXT: uaddlp v0.8h, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v1.8h, v1.16b -; NONEON-NOSVE-NEXT: uaddlp v0.4s, v0.8h -; NONEON-NOSVE-NEXT: uaddlp v1.4s, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %op) store <8 x i32> %res, ptr %a @@ -587,14 +347,6 @@ define <1 x i64> @ctpop_v1i64(<1 x i64> %op) { ; CHECK-NEXT: cnt z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cnt v0.8b, v0.8b -; NONEON-NOSVE-NEXT: uaddlp v0.4h, v0.8b -; NONEON-NOSVE-NEXT: uaddlp v0.2s, v0.4h -; NONEON-NOSVE-NEXT: uaddlp v0.1d, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <1 x i64> @llvm.ctpop.v1i64(<1 x i64> %op) ret <1 x i64> %res } @@ -607,14 +359,6 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %op) { ; CHECK-NEXT: cnt z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v0.8h, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v0.4s, v0.8h -; NONEON-NOSVE-NEXT: uaddlp v0.2d, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %op) ret <2 x i64> %res } @@ -628,20 +372,6 @@ define void @ctpop_v4i64(ptr %a) { ; CHECK-NEXT: cnt z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ctpop_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: cnt v1.16b, v1.16b -; NONEON-NOSVE-NEXT: uaddlp v0.8h, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v1.8h, v1.16b -; NONEON-NOSVE-NEXT: uaddlp v0.4s, v0.8h -; NONEON-NOSVE-NEXT: uaddlp v1.4s, v1.8h -; NONEON-NOSVE-NEXT: uaddlp v0.2d, v0.4s -; NONEON-NOSVE-NEXT: uaddlp v1.2d, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %op) store <4 x i64> %res, ptr %a @@ -662,21 +392,6 @@ define <4 x i8> @cttz_v4i8(<4 x i8> %op) { ; CHECK-NEXT: clz z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #256 // =0x100 -; NONEON-NOSVE-NEXT: dup v1.4h, w8 -; NONEON-NOSVE-NEXT: mov w8, #1 // =0x1 -; NONEON-NOSVE-NEXT: dup v2.4h, w8 -; NONEON-NOSVE-NEXT: mov w8, #16 // =0x10 -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: sub v1.4h, v0.4h, v2.4h -; NONEON-NOSVE-NEXT: bic v0.8b, v1.8b, v0.8b -; NONEON-NOSVE-NEXT: dup v1.4h, w8 -; NONEON-NOSVE-NEXT: clz v0.4h, v0.4h -; NONEON-NOSVE-NEXT: sub v0.4h, v1.4h, v0.4h -; NONEON-NOSVE-NEXT: ret %res = call <4 x i8> @llvm.cttz.v4i8(<4 x i8> %op) ret <4 x i8> %res } @@ -690,14 +405,6 @@ define <8 x i8> @cttz_v8i8(<8 x i8> %op) { ; CHECK-NEXT: clz z0.b, p0/m, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v1.8b, #1 -; NONEON-NOSVE-NEXT: sub v1.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: bic v0.8b, v1.8b, v0.8b -; NONEON-NOSVE-NEXT: cnt v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <8 x i8> @llvm.cttz.v8i8(<8 x i8> %op) ret <8 x i8> %res } @@ -711,14 +418,6 @@ define <16 x i8> @cttz_v16i8(<16 x i8> %op) { ; CHECK-NEXT: clz z0.b, p0/m, z0.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v1.16b, #1 -; NONEON-NOSVE-NEXT: sub v1.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: bic v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %res = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %op) ret <16 x i8> %res } @@ -734,19 +433,6 @@ define void @cttz_v32i8(ptr %a) { ; CHECK-NEXT: clz z1.b, p0/m, z1.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #1 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: sub v3.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: sub v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: bic v1.16b, v3.16b, v1.16b -; NONEON-NOSVE-NEXT: bic v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: cnt v1.16b, v1.16b -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %res = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> %op) store <32 x i8> %res, ptr %a @@ -763,21 +449,6 @@ define <2 x i16> @cttz_v2i16(<2 x i16> %op) { ; CHECK-NEXT: clz z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #65536 // =0x10000 -; NONEON-NOSVE-NEXT: dup v1.2s, w8 -; NONEON-NOSVE-NEXT: mov w8, #1 // =0x1 -; NONEON-NOSVE-NEXT: dup v2.2s, w8 -; NONEON-NOSVE-NEXT: mov w8, #32 // =0x20 -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: sub v1.2s, v0.2s, v2.2s -; NONEON-NOSVE-NEXT: bic v0.8b, v1.8b, v0.8b -; NONEON-NOSVE-NEXT: dup v1.2s, w8 -; NONEON-NOSVE-NEXT: clz v0.2s, v0.2s -; NONEON-NOSVE-NEXT: sub v0.2s, v1.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i16> @llvm.cttz.v2i16(<2 x i16> %op) ret <2 x i16> %res } @@ -791,18 +462,6 @@ define <4 x i16> @cttz_v4i16(<4 x i16> %op) { ; CHECK-NEXT: clz z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #1 // =0x1 -; NONEON-NOSVE-NEXT: dup v1.4h, w8 -; NONEON-NOSVE-NEXT: mov w8, #16 // =0x10 -; NONEON-NOSVE-NEXT: sub v1.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: bic v0.8b, v1.8b, v0.8b -; NONEON-NOSVE-NEXT: dup v1.4h, w8 -; NONEON-NOSVE-NEXT: clz v0.4h, v0.4h -; NONEON-NOSVE-NEXT: sub v0.4h, v1.4h, v0.4h -; NONEON-NOSVE-NEXT: ret %res = call <4 x i16> @llvm.cttz.v4i16(<4 x i16> %op) ret <4 x i16> %res } @@ -816,18 +475,6 @@ define <8 x i16> @cttz_v8i16(<8 x i16> %op) { ; CHECK-NEXT: clz z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #1 // =0x1 -; NONEON-NOSVE-NEXT: dup v1.8h, w8 -; NONEON-NOSVE-NEXT: mov w8, #16 // =0x10 -; NONEON-NOSVE-NEXT: sub v1.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: bic v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: dup v1.8h, w8 -; NONEON-NOSVE-NEXT: clz v0.8h, v0.8h -; NONEON-NOSVE-NEXT: sub v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: ret %res = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %op) ret <8 x i16> %res } @@ -843,24 +490,6 @@ define void @cttz_v16i16(ptr %a) { ; CHECK-NEXT: clz z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #1 // =0x1 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: mov w8, #16 // =0x10 -; NONEON-NOSVE-NEXT: sub v3.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: sub v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: bic v1.16b, v3.16b, v1.16b -; NONEON-NOSVE-NEXT: bic v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: dup v2.8h, w8 -; NONEON-NOSVE-NEXT: clz v1.8h, v1.8h -; NONEON-NOSVE-NEXT: clz v0.8h, v0.8h -; NONEON-NOSVE-NEXT: sub v1.8h, v2.8h, v1.8h -; NONEON-NOSVE-NEXT: sub v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %op) store <16 x i16> %res, ptr %a @@ -876,18 +505,6 @@ define <2 x i32> @cttz_v2i32(<2 x i32> %op) { ; CHECK-NEXT: clz z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #1 // =0x1 -; NONEON-NOSVE-NEXT: dup v1.2s, w8 -; NONEON-NOSVE-NEXT: mov w8, #32 // =0x20 -; NONEON-NOSVE-NEXT: sub v1.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: bic v0.8b, v1.8b, v0.8b -; NONEON-NOSVE-NEXT: dup v1.2s, w8 -; NONEON-NOSVE-NEXT: clz v0.2s, v0.2s -; NONEON-NOSVE-NEXT: sub v0.2s, v1.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %op) ret <2 x i32> %res } @@ -901,18 +518,6 @@ define <4 x i32> @cttz_v4i32(<4 x i32> %op) { ; CHECK-NEXT: clz z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #1 // =0x1 -; NONEON-NOSVE-NEXT: dup v1.4s, w8 -; NONEON-NOSVE-NEXT: mov w8, #32 // =0x20 -; NONEON-NOSVE-NEXT: sub v1.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: bic v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: dup v1.4s, w8 -; NONEON-NOSVE-NEXT: clz v0.4s, v0.4s -; NONEON-NOSVE-NEXT: sub v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %op) ret <4 x i32> %res } @@ -928,24 +533,6 @@ define void @cttz_v8i32(ptr %a) { ; CHECK-NEXT: clz z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #1 // =0x1 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: mov w8, #32 // =0x20 -; NONEON-NOSVE-NEXT: sub v3.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: sub v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: bic v1.16b, v3.16b, v1.16b -; NONEON-NOSVE-NEXT: bic v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: dup v2.4s, w8 -; NONEON-NOSVE-NEXT: clz v1.4s, v1.4s -; NONEON-NOSVE-NEXT: clz v0.4s, v0.4s -; NONEON-NOSVE-NEXT: sub v1.4s, v2.4s, v1.4s -; NONEON-NOSVE-NEXT: sub v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %op) store <8 x i32> %res, ptr %a @@ -961,18 +548,6 @@ define <1 x i64> @cttz_v1i64(<1 x i64> %op) { ; CHECK-NEXT: clz z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #1 // =0x1 -; NONEON-NOSVE-NEXT: fmov d1, x8 -; NONEON-NOSVE-NEXT: sub d1, d0, d1 -; NONEON-NOSVE-NEXT: bic v0.8b, v1.8b, v0.8b -; NONEON-NOSVE-NEXT: cnt v0.8b, v0.8b -; NONEON-NOSVE-NEXT: uaddlp v0.4h, v0.8b -; NONEON-NOSVE-NEXT: uaddlp v0.2s, v0.4h -; NONEON-NOSVE-NEXT: uaddlp v0.1d, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <1 x i64> @llvm.cttz.v1i64(<1 x i64> %op) ret <1 x i64> %res } @@ -986,18 +561,6 @@ define <2 x i64> @cttz_v2i64(<2 x i64> %op) { ; CHECK-NEXT: clz z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #1 // =0x1 -; NONEON-NOSVE-NEXT: dup v1.2d, x8 -; NONEON-NOSVE-NEXT: sub v1.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: bic v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v0.8h, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v0.4s, v0.8h -; NONEON-NOSVE-NEXT: uaddlp v0.2d, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %op) ret <2 x i64> %res } @@ -1013,26 +576,6 @@ define void @cttz_v4i64(ptr %a) { ; CHECK-NEXT: clz z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: cttz_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #1 // =0x1 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: sub v3.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: sub v0.2d, v2.2d, v0.2d -; NONEON-NOSVE-NEXT: bic v1.16b, v3.16b, v1.16b -; NONEON-NOSVE-NEXT: bic v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: cnt v1.16b, v1.16b -; NONEON-NOSVE-NEXT: cnt v0.16b, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v1.8h, v1.16b -; NONEON-NOSVE-NEXT: uaddlp v0.8h, v0.16b -; NONEON-NOSVE-NEXT: uaddlp v1.4s, v1.8h -; NONEON-NOSVE-NEXT: uaddlp v0.4s, v0.8h -; NONEON-NOSVE-NEXT: uaddlp v1.2d, v1.4s -; NONEON-NOSVE-NEXT: uaddlp v0.2d, v0.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %op) store <4 x i64> %res, ptr %a diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll index 64dc7ae117d3..e3cc74f766ee 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -12,12 +11,6 @@ define void @bitcast_v4i8(ptr %a, ptr %b) { ; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0] ; CHECK-NEXT: st1b { z0.h }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr w8, [x0] -; NONEON-NOSVE-NEXT: str w8, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <4 x i8>, ptr %a %cast = bitcast <4 x i8> %load to <4 x i8> store volatile <4 x i8> %cast, ptr %b @@ -30,12 +23,6 @@ define void @bitcast_v8i8(ptr %a, ptr %b) { ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <8 x i8>, ptr %a %cast = bitcast <8 x i8> %load to <8 x i8> store volatile <8 x i8> %cast, ptr %b @@ -48,12 +35,6 @@ define void @bitcast_v16i8(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <16 x i8>, ptr %a %cast = bitcast <16 x i8> %load to <16 x i8> store volatile <16 x i8> %cast, ptr %b @@ -68,14 +49,6 @@ define void @bitcast_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: str q1, [x1, #16] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: str q1, [x1, #16] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <32 x i8>, ptr %a %cast = bitcast <32 x i8> %load to <32 x i8> store volatile <32 x i8> %cast, ptr %b @@ -99,16 +72,6 @@ define void @bitcast_v2i16(ptr %a, ptr %b) { ; CHECK-NEXT: str w8, [x1] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldrh w8, [x0] -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: add x8, x0, #2 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[2], [x8] -; NONEON-NOSVE-NEXT: uzp1 v0.4h, v0.4h, v0.4h -; NONEON-NOSVE-NEXT: str s0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <2 x i16>, ptr %a %cast = bitcast <2 x i16> %load to <2 x half> store volatile <2 x half> %cast, ptr %b @@ -121,12 +84,6 @@ define void @bitcast_v4i16(ptr %a, ptr %b) { ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <4 x i16>, ptr %a %cast = bitcast <4 x i16> %load to <4 x half> store volatile <4 x half> %cast, ptr %b @@ -139,12 +96,6 @@ define void @bitcast_v8i16(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <8 x i16>, ptr %a %cast = bitcast <8 x i16> %load to <8 x half> store volatile <8 x half> %cast, ptr %b @@ -159,14 +110,6 @@ define void @bitcast_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: str q1, [x1, #16] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: str q1, [x1, #16] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <16 x i16>, ptr %a %cast = bitcast <16 x i16> %load to <16 x half> store volatile <16 x half> %cast, ptr %b @@ -179,12 +122,6 @@ define void @bitcast_v2i32(ptr %a, ptr %b) { ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <2 x i32>, ptr %a %cast = bitcast <2 x i32> %load to <2 x float> store volatile <2 x float> %cast, ptr %b @@ -197,12 +134,6 @@ define void @bitcast_v4i32(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <4 x i32>, ptr %a %cast = bitcast <4 x i32> %load to <4 x float> store volatile <4 x float> %cast, ptr %b @@ -217,14 +148,6 @@ define void @bitcast_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: str q1, [x1, #16] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: str q1, [x1, #16] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <8 x i32>, ptr %a %cast = bitcast <8 x i32> %load to <8 x float> store volatile <8 x float> %cast, ptr %b @@ -237,12 +160,6 @@ define void @bitcast_v1i64(ptr %a, ptr %b) { ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <1 x i64>, ptr %a %cast = bitcast <1 x i64> %load to <1 x double> store volatile <1 x double> %cast, ptr %b @@ -255,12 +172,6 @@ define void @bitcast_v2i64(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <2 x i64>, ptr %a %cast = bitcast <2 x i64> %load to <2 x double> store volatile <2 x double> %cast, ptr %b @@ -275,14 +186,6 @@ define void @bitcast_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: str q1, [x1, #16] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitcast_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: str q1, [x1, #16] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %load = load volatile <4 x i64>, ptr %a %cast = bitcast <4 x i64> %load to <4 x double> store volatile <4 x double> %cast, ptr %b diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll index 5e06cd62118d..74a4aab15597 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64" @@ -31,17 +30,6 @@ define <8 x i32> @fixed_bitselect_v8i32(ptr %pre_cond_ptr, ptr %left_ptr, ptr %r ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fixed_bitselect_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x1] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x2] -; NONEON-NOSVE-NEXT: neg v1.4s, v1.4s -; NONEON-NOSVE-NEXT: neg v0.4s, v0.4s -; NONEON-NOSVE-NEXT: bsl v0.16b, v3.16b, v5.16b -; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v4.16b -; NONEON-NOSVE-NEXT: ret %pre_cond = load <8 x i32>, ptr %pre_cond_ptr %left = load <8 x i32>, ptr %left_ptr %right = load <8 x i32>, ptr %right_ptr diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll index 7a24430a3385..0c490a662a79 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -11,12 +10,6 @@ define void @build_vector_7_inc1_v4i1(ptr %a) { ; CHECK-NEXT: mov w8, #5 // =0x5 ; CHECK-NEXT: strb w8, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: build_vector_7_inc1_v4i1: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: strb w8, [x0] -; NONEON-NOSVE-NEXT: ret store <4 x i1> , ptr %a, align 1 ret void } @@ -30,15 +23,6 @@ define void @build_vector_7_inc1_v32i8(ptr %a) { ; CHECK-NEXT: add z1.b, z1.b, #23 // =0x17 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: build_vector_7_inc1_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: adrp x8, .LCPI1_0 -; NONEON-NOSVE-NEXT: adrp x9, .LCPI1_1 -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI1_0] -; NONEON-NOSVE-NEXT: ldr q1, [x9, :lo12:.LCPI1_1] -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <32 x i8> , ptr %a, align 1 ret void } @@ -51,15 +35,6 @@ define void @build_vector_0_inc2_v16i16(ptr %a) { ; CHECK-NEXT: add z0.h, z0.h, #16 // =0x10 ; CHECK-NEXT: str q0, [x0, #16] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: build_vector_0_inc2_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: adrp x8, .LCPI2_0 -; NONEON-NOSVE-NEXT: adrp x9, .LCPI2_1 -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI2_0] -; NONEON-NOSVE-NEXT: ldr q1, [x9, :lo12:.LCPI2_1] -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <16 x i16> , ptr %a, align 2 ret void } @@ -73,15 +48,6 @@ define void @build_vector_0_dec3_v8i32(ptr %a) { ; CHECK-NEXT: add z1.s, z0.s, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: build_vector_0_dec3_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: adrp x8, .LCPI3_0 -; NONEON-NOSVE-NEXT: adrp x9, .LCPI3_1 -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI3_0] -; NONEON-NOSVE-NEXT: ldr q1, [x9, :lo12:.LCPI3_1] -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <8 x i32> , ptr %a, align 4 ret void } @@ -98,15 +64,6 @@ define void @build_vector_minus2_dec32_v4i64(ptr %a) { ; CHECK-NEXT: add z0.d, z0.d, z2.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: build_vector_minus2_dec32_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: adrp x8, .LCPI4_0 -; NONEON-NOSVE-NEXT: adrp x9, .LCPI4_1 -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI4_0] -; NONEON-NOSVE-NEXT: ldr q1, [x9, :lo12:.LCPI4_1] -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <4 x i64> , ptr %a, align 8 ret void } @@ -119,15 +76,6 @@ define void @build_vector_no_stride_v4i64(ptr %a) { ; CHECK-NEXT: index z1.d, #0, #4 ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: build_vector_no_stride_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: adrp x8, .LCPI5_0 -; NONEON-NOSVE-NEXT: adrp x9, .LCPI5_1 -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI5_0] -; NONEON-NOSVE-NEXT: ldr q1, [x9, :lo12:.LCPI5_1] -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <4 x i64> , ptr %a, align 8 ret void } @@ -141,15 +89,6 @@ define void @build_vector_0_inc2_v16f16(ptr %a) { ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI6_1] ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: build_vector_0_inc2_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: adrp x8, .LCPI6_0 -; NONEON-NOSVE-NEXT: adrp x9, .LCPI6_1 -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI6_0] -; NONEON-NOSVE-NEXT: ldr q1, [x9, :lo12:.LCPI6_1] -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <16 x half> , ptr %a, align 2 ret void } @@ -164,15 +103,6 @@ define void @build_vector_0_dec3_v8f32(ptr %a) { ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI7_1] ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: build_vector_0_dec3_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: adrp x8, .LCPI7_0 -; NONEON-NOSVE-NEXT: adrp x9, .LCPI7_1 -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI7_0] -; NONEON-NOSVE-NEXT: ldr q1, [x9, :lo12:.LCPI7_1] -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <8 x float> , ptr %a, align 4 ret void } @@ -187,15 +117,6 @@ define void @build_vector_minus2_dec32_v4f64(ptr %a) { ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI8_1] ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: build_vector_minus2_dec32_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: adrp x8, .LCPI8_0 -; NONEON-NOSVE-NEXT: adrp x9, .LCPI8_1 -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI8_0] -; NONEON-NOSVE-NEXT: ldr q1, [x9, :lo12:.LCPI8_1] -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <4 x double> , ptr %a, align 8 ret void } @@ -210,15 +131,6 @@ define void @build_vector_no_stride_v4f64(ptr %a) { ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI9_1] ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: build_vector_no_stride_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: adrp x8, .LCPI9_0 -; NONEON-NOSVE-NEXT: adrp x9, .LCPI9_1 -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI9_0] -; NONEON-NOSVE-NEXT: ldr q1, [x9, :lo12:.LCPI9_1] -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <4 x double> , ptr %a, align 8 ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll index ee997228e453..86494c4be501 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -41,11 +40,6 @@ define <8 x i8> @concat_v8i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: ldr d0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: uzp1 v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = shufflevector <4 x i8> %op1, <4 x i8> %op2, <8 x i32> ret <8 x i8> %res } @@ -59,13 +53,6 @@ define <16 x i8> @concat_v16i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: mov v0.d[1], v1.d[0] -; NONEON-NOSVE-NEXT: ret %res = shufflevector <8 x i8> %op1, <8 x i8> %op2, <16 x i32> ret <16 x i8> %res @@ -78,13 +65,6 @@ define void @concat_v32i8(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: ldr q1, [x0] ; CHECK-NEXT: stp q1, q0, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x1] -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: stp q1, q0, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i8>, ptr %a %op2 = load <16 x i8>, ptr %b %res = shufflevector <16 x i8> %op1, <16 x i8> %op2, <32 x i32> , ptr %a %op2 = load <32 x i8>, ptr %b %res = shufflevector <32 x i8> %op1, <32 x i8> %op2, <64 x i32> @concat_v4i16(<2 x i16> %op1, <2 x i16> %op2) { ; CHECK-NEXT: ldr d0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: uzp1 v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = shufflevector <2 x i16> %op1, <2 x i16> %op2, <4 x i32> ret <4 x i16> %res } @@ -168,13 +135,6 @@ define <8 x i16> @concat_v8i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: mov v0.d[1], v1.d[0] -; NONEON-NOSVE-NEXT: ret %res = shufflevector <4 x i16> %op1, <4 x i16> %op2, <8 x i32> ret <8 x i16> %res } @@ -186,13 +146,6 @@ define void @concat_v16i16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: ldr q1, [x0] ; CHECK-NEXT: stp q1, q0, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x1] -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: stp q1, q0, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i16>, ptr %a %op2 = load <8 x i16>, ptr %b %res = shufflevector <8 x i16> %op1, <8 x i16> %op2, <16 x i32> , ptr %a %op2 = load <16 x i16>, ptr %b %res = shufflevector <16 x i16> %op1, <16 x i16> %op2, <32 x i32> @concat_v2i32(<1 x i32> %op1, <1 x i32> %op2) { ; CHECK-NEXT: zip1 z0.s, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: zip1 v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = shufflevector <1 x i32> %op1, <1 x i32> %op2, <2 x i32> ret <2 x i32> %res } @@ -259,13 +199,6 @@ define <4 x i32> @concat_v4i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: mov v0.d[1], v1.d[0] -; NONEON-NOSVE-NEXT: ret %res = shufflevector <2 x i32> %op1, <2 x i32> %op2, <4 x i32> ret <4 x i32> %res } @@ -277,13 +210,6 @@ define void @concat_v8i32(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: ldr q1, [x0] ; CHECK-NEXT: stp q1, q0, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x1] -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: stp q1, q0, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i32>, ptr %a %op2 = load <4 x i32>, ptr %b %res = shufflevector <4 x i32> %op1, <4 x i32> %op2, <8 x i32> @@ -299,14 +225,6 @@ define void @concat_v16i32(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: stp q0, q1, [x2, #32] ; CHECK-NEXT: stp q3, q2, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v16i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [x2, #32] -; NONEON-NOSVE-NEXT: stp q3, q2, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = shufflevector <8 x i32> %op1, <8 x i32> %op2, <16 x i32> @concat_v2i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: mov v0.d[1], v1.d[0] -; NONEON-NOSVE-NEXT: ret %res = shufflevector <1 x i64> %op1, <1 x i64> %op2, <2 x i32> ret <2 x i64> %res } @@ -347,13 +258,6 @@ define void @concat_v4i64(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: ldr q1, [x0] ; CHECK-NEXT: stp q1, q0, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x1] -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: stp q1, q0, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x i64>, ptr %a %op2 = load <2 x i64>, ptr %b %res = shufflevector <2 x i64> %op1, <2 x i64> %op2, <4 x i32> @@ -369,14 +273,6 @@ define void @concat_v8i64(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: stp q0, q1, [x2, #32] ; CHECK-NEXT: stp q3, q2, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v8i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [x2, #32] -; NONEON-NOSVE-NEXT: stp q3, q2, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = shufflevector <4 x i64> %op1, <4 x i64> %op2, <8 x i32> @@ -404,11 +300,6 @@ define <4 x half> @concat_v4f16(<2 x half> %op1, <2 x half> %op2) { ; CHECK-NEXT: ldr d0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: zip1 v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = shufflevector <2 x half> %op1, <2 x half> %op2, <4 x i32> ret <4 x half> %res } @@ -422,13 +313,6 @@ define <8 x half> @concat_v8f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: mov v0.d[1], v1.d[0] -; NONEON-NOSVE-NEXT: ret %res = shufflevector <4 x half> %op1, <4 x half> %op2, <8 x i32> ret <8 x half> %res } @@ -440,13 +324,6 @@ define void @concat_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: ldr q1, [x0] ; CHECK-NEXT: stp q1, q0, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x1] -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: stp q1, q0, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x half>, ptr %a %op2 = load <8 x half>, ptr %b %res = shufflevector <8 x half> %op1, <8 x half> %op2, <16 x i32> , ptr %a %op2 = load <16 x half>, ptr %b %res = shufflevector <16 x half> %op1, <16 x half> %op2, <32 x i32> @concat_v2f32(<1 x float> %op1, <1 x float> %op2) { ; CHECK-NEXT: zip1 z0.s, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: zip1 v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = shufflevector <1 x float> %op1, <1 x float> %op2, <2 x i32> ret <2 x float> %res } @@ -513,13 +377,6 @@ define <4 x float> @concat_v4f32(<2 x float> %op1, <2 x float> %op2) { ; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: mov v0.d[1], v1.d[0] -; NONEON-NOSVE-NEXT: ret %res = shufflevector <2 x float> %op1, <2 x float> %op2, <4 x i32> ret <4 x float> %res } @@ -531,13 +388,6 @@ define void @concat_v8f32(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: ldr q1, [x0] ; CHECK-NEXT: stp q1, q0, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x1] -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: stp q1, q0, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x float>, ptr %a %op2 = load <4 x float>, ptr %b %res = shufflevector <4 x float> %op1, <4 x float> %op2, <8 x i32> @@ -553,14 +403,6 @@ define void @concat_v16f32(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: stp q0, q1, [x2, #32] ; CHECK-NEXT: stp q3, q2, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v16f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [x2, #32] -; NONEON-NOSVE-NEXT: stp q3, q2, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %res = shufflevector <8 x float> %op1, <8 x float> %op2, <16 x i32> @concat_v2f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: mov v0.d[1], v1.d[0] -; NONEON-NOSVE-NEXT: ret %res = shufflevector <1 x double> %op1, <1 x double> %op2, <2 x i32> ret <2 x double> %res } @@ -601,13 +436,6 @@ define void @concat_v4f64(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: ldr q1, [x0] ; CHECK-NEXT: stp q1, q0, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x1] -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: stp q1, q0, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x double>, ptr %a %op2 = load <2 x double>, ptr %b %res = shufflevector <2 x double> %op1, <2 x double> %op2, <4 x i32> @@ -623,14 +451,6 @@ define void @concat_v8f64(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: stp q0, q1, [x2, #32] ; CHECK-NEXT: stp q3, q2, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v8f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [x2, #32] -; NONEON-NOSVE-NEXT: stp q3, q2, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %res = shufflevector <4 x double> %op1, <4 x double> %op2, <8 x i32> @@ -648,12 +468,6 @@ define void @concat_v32i8_undef(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v32i8_undef: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i8>, ptr %a %res = shufflevector <16 x i8> %op1, <16 x i8> undef, <32 x i32> , ptr %a %res = shufflevector <8 x i16> %op1, <8 x i16> undef, <16 x i32> @@ -688,12 +496,6 @@ define void @concat_v8i32_undef(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v8i32_undef: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i32>, ptr %a %res = shufflevector <4 x i32> %op1, <4 x i32> undef, <8 x i32> store <8 x i32> %res, ptr %b @@ -706,12 +508,6 @@ define void @concat_v4i64_undef(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v4i64_undef: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x i64>, ptr %a %res = shufflevector <2 x i64> %op1, <2 x i64> undef, <4 x i32> store <4 x i64> %res, ptr %b @@ -728,12 +524,6 @@ define void @concat_v32i8_4op(ptr %a, ptr %b) { ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v32i8_4op: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i8>, ptr %a %shuffle = shufflevector <8 x i8> %op1, <8 x i8> undef, <16 x i32> @@ -751,12 +541,6 @@ define void @concat_v16i16_4op(ptr %a, ptr %b) { ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v16i16_4op: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i16>, ptr %a %shuffle = shufflevector <4 x i16> %op1, <4 x i16> undef, <8 x i32> %res = shufflevector <8 x i16> %shuffle, <8 x i16> undef, <16 x i32> , ptr %a %shuffle = shufflevector <2 x i32> %op1, <2 x i32> undef, <4 x i32> %res = shufflevector <4 x i32> %shuffle, <4 x i32> undef, <8 x i32> @@ -790,12 +568,6 @@ define void @concat_v4i64_4op(ptr %a, ptr %b) { ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: concat_v4i64_4op: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <1 x i64>, ptr %a %shuffle = shufflevector <1 x i64> %op1, <1 x i64> undef, <2 x i32> %res = shufflevector <2 x i64> %shuffle, <2 x i64> undef, <4 x i32> diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll index 42aa67fb2ab8..0aefba2d4c6a 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -12,12 +11,6 @@ define <8 x i16> @load_zext_v8i8i16(ptr %ap) { ; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0] ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_zext_v8i8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: ret %a = load <8 x i8>, ptr %ap %val = zext <8 x i8> %a to <8 x i16> ret <8 x i16> %val @@ -30,12 +23,6 @@ define <4 x i32> @load_zext_v4i16i32(ptr %ap) { ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_zext_v4i16i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ret %a = load <4 x i16>, ptr %ap %val = zext <4 x i16> %a to <4 x i32> ret <4 x i32> %val @@ -48,12 +35,6 @@ define <2 x i64> @load_zext_v2i32i64(ptr %ap) { ; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0] ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_zext_v2i32i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ret %a = load <2 x i32>, ptr %ap %val = zext <2 x i32> %a to <2 x i64> ret <2 x i64> %val @@ -73,19 +54,6 @@ define <2 x i256> @load_zext_v2i64i256(ptr %ap) { ; CHECK-NEXT: mov x7, xzr ; CHECK-NEXT: fmov x4, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_zext_v2i64i256: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: mov x1, xzr -; NONEON-NOSVE-NEXT: mov x2, xzr -; NONEON-NOSVE-NEXT: mov x3, xzr -; NONEON-NOSVE-NEXT: mov x5, xzr -; NONEON-NOSVE-NEXT: mov x6, xzr -; NONEON-NOSVE-NEXT: mov x4, v0.d[1] -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: mov x7, xzr -; NONEON-NOSVE-NEXT: ret %a = load <2 x i64>, ptr %ap %val = zext <2 x i64> %a to <2 x i256> ret <2 x i256> %val @@ -107,24 +75,6 @@ define <16 x i32> @load_sext_v16i8i32(ptr %ap) { ; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2 ; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_sext_v16i8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: sshll v1.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-48]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v2.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: sshll v0.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q2, q1, [sp, #16] -; NONEON-NOSVE-NEXT: sshll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: ldr d3, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d4, [sp, #24] -; NONEON-NOSVE-NEXT: sshll v1.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: sshll v3.4s, v4.4h, #0 -; NONEON-NOSVE-NEXT: add sp, sp, #48 -; NONEON-NOSVE-NEXT: ret %a = load <16 x i8>, ptr %ap %val = sext <16 x i8> %a to <16 x i32> ret <16 x i32> %val @@ -140,17 +90,6 @@ define <8 x i32> @load_sext_v8i16i32(ptr %ap) { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_sext_v8i16i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %a = load <8 x i16>, ptr %ap %val = sext <8 x i16> %a to <8 x i32> ret <8 x i32> %val @@ -182,39 +121,6 @@ define <4 x i256> @load_sext_v4i32i256(ptr %ap) { ; CHECK-NEXT: stp x12, x12, [x8, #112] ; CHECK-NEXT: stp x11, x12, [x8, #96] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_sext_v4i32i256: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: add x10, x8, #32 -; NONEON-NOSVE-NEXT: add x11, x8, #96 -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: mov x9, v0.d[1] -; NONEON-NOSVE-NEXT: st1 { v0.d }[1], [x10] -; NONEON-NOSVE-NEXT: fmov x10, d0 -; NONEON-NOSVE-NEXT: st1 { v1.d }[1], [x11] -; NONEON-NOSVE-NEXT: mov x11, v1.d[1] -; NONEON-NOSVE-NEXT: asr x10, x10, #63 -; NONEON-NOSVE-NEXT: str d0, [x8] -; NONEON-NOSVE-NEXT: asr x9, x9, #63 -; NONEON-NOSVE-NEXT: str d1, [x8, #64] -; NONEON-NOSVE-NEXT: stp x10, x10, [x8, #16] -; NONEON-NOSVE-NEXT: stp x9, x9, [x8, #48] -; NONEON-NOSVE-NEXT: str x9, [x8, #40] -; NONEON-NOSVE-NEXT: fmov x9, d1 -; NONEON-NOSVE-NEXT: str x10, [x8, #8] -; NONEON-NOSVE-NEXT: asr x10, x11, #63 -; NONEON-NOSVE-NEXT: asr x9, x9, #63 -; NONEON-NOSVE-NEXT: stp x10, x10, [x8, #112] -; NONEON-NOSVE-NEXT: str x10, [x8, #104] -; NONEON-NOSVE-NEXT: stp x9, x9, [x8, #80] -; NONEON-NOSVE-NEXT: str x9, [x8, #72] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %a = load <4 x i32>, ptr %ap %val = sext <4 x i32> %a to <4 x i256> ret <4 x i256> %val @@ -248,22 +154,6 @@ define <2 x i256> @load_sext_v2i64i256(ptr %ap) { ; CHECK-NEXT: fmov x1, d6 ; CHECK-NEXT: fmov x5, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_sext_v2i64i256: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: mov x8, v0.d[1] -; NONEON-NOSVE-NEXT: dup v1.2d, v0.d[1] -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: asr x1, x0, #63 -; NONEON-NOSVE-NEXT: asr x5, x8, #63 -; NONEON-NOSVE-NEXT: mov x2, x1 -; NONEON-NOSVE-NEXT: mov x3, x1 -; NONEON-NOSVE-NEXT: mov v1.d[1], x5 -; NONEON-NOSVE-NEXT: mov x6, x5 -; NONEON-NOSVE-NEXT: mov x7, x5 -; NONEON-NOSVE-NEXT: fmov x4, d1 -; NONEON-NOSVE-NEXT: ret %a = load <2 x i64>, ptr %ap %val = sext <2 x i64> %a to <2 x i256> ret <2 x i256> %val @@ -297,34 +187,6 @@ define <16 x i64> @load_zext_v16i16i64(ptr %ap) { ; CHECK-NEXT: // kill: def $q6 killed $q6 killed $z6 ; CHECK-NEXT: // kill: def $q7 killed $q7 killed $z7 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_zext_v16i16i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ushll v2.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-96]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v3.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ushll v1.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #24] -; NONEON-NOSVE-NEXT: ushll v4.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: ushll v5.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v0.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: stp q1, q2, [sp, #32] -; NONEON-NOSVE-NEXT: ushll v2.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ldr d6, [sp, #56] -; NONEON-NOSVE-NEXT: ldr d7, [sp, #40] -; NONEON-NOSVE-NEXT: stp q5, q3, [sp, #64] -; NONEON-NOSVE-NEXT: ldr d16, [sp, #88] -; NONEON-NOSVE-NEXT: ldr d17, [sp, #72] -; NONEON-NOSVE-NEXT: ushll v1.2d, v6.2s, #0 -; NONEON-NOSVE-NEXT: ushll v3.2d, v7.2s, #0 -; NONEON-NOSVE-NEXT: ushll v6.2d, v5.2s, #0 -; NONEON-NOSVE-NEXT: ushll v5.2d, v16.2s, #0 -; NONEON-NOSVE-NEXT: ushll v7.2d, v17.2s, #0 -; NONEON-NOSVE-NEXT: add sp, sp, #96 -; NONEON-NOSVE-NEXT: ret %a = load <16 x i16>, ptr %ap %val = zext <16 x i16> %a to <16 x i64> ret <16 x i64> %val diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll index d050ddc77640..25ecd7a8d7e3 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -28,11 +27,6 @@ define <4 x i1> @extract_subvector_v8i1(<8 x i1> %op) { ; CHECK-NEXT: ldr d0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v8i1: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: zip2 v0.8b, v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %ret = call <4 x i1> @llvm.vector.extract.v4i1.v8i1(<8 x i1> %op, i64 4) ret <4 x i1> %ret } @@ -60,11 +54,6 @@ define <4 x i8> @extract_subvector_v8i8(<8 x i8> %op) { ; CHECK-NEXT: ldr d0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: zip2 v0.8b, v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %ret = call <4 x i8> @llvm.vector.extract.v4i8.v8i8(<8 x i8> %op, i64 4) ret <4 x i8> %ret } @@ -76,14 +65,6 @@ define <8 x i8> @extract_subvector_v16i8(<16 x i8> %op) { ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %ret = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %op, i64 8) ret <8 x i8> %ret } @@ -94,12 +75,6 @@ define void @extract_subvector_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0, #16] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %ret = call <16 x i8> @llvm.vector.extract.v16i8.v32i8(<32 x i8> %op, i64 16) store <16 x i8> %ret, ptr %b @@ -116,15 +91,6 @@ define <2 x i16> @extract_subvector_v4i16(<4 x i16> %op) { ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %ret = call <2 x i16> @llvm.vector.extract.v2i16.v4i16(<4 x i16> %op, i64 2) ret <2 x i16> %ret } @@ -136,14 +102,6 @@ define <4 x i16> @extract_subvector_v8i16(<8 x i16> %op) { ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %ret = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %op, i64 4) ret <4 x i16> %ret } @@ -154,12 +112,6 @@ define void @extract_subvector_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0, #16] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %ret = call <8 x i16> @llvm.vector.extract.v8i16.v16i16(<16 x i16> %op, i64 8) store <8 x i16> %ret, ptr %b @@ -175,12 +127,6 @@ define <1 x i32> @extract_subvector_v2i32(<2 x i32> %op) { ; CHECK-NEXT: mov z0.s, z0.s[1] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: dup v0.2s, v0.s[1] -; NONEON-NOSVE-NEXT: ret %ret = call <1 x i32> @llvm.vector.extract.v1i32.v2i32(<2 x i32> %op, i64 1) ret <1 x i32> %ret } @@ -192,14 +138,6 @@ define <2 x i32> @extract_subvector_v4i32(<4 x i32> %op) { ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %ret = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %op, i64 2) ret <2 x i32> %ret } @@ -210,12 +148,6 @@ define void @extract_subvector_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0, #16] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %ret = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %op, i64 4) store <4 x i32> %ret, ptr %b @@ -231,14 +163,6 @@ define <1 x i64> @extract_subvector_v2i64(<2 x i64> %op) { ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %ret = call <1 x i64> @llvm.vector.extract.v1i64.v2i64(<2 x i64> %op, i64 1) ret <1 x i64> %ret } @@ -249,12 +173,6 @@ define void @extract_subvector_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0, #16] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %ret = call <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64> %op, i64 2) store <2 x i64> %ret, ptr %b @@ -272,12 +190,6 @@ define <2 x half> @extract_subvector_v4f16(<4 x half> %op) { ; CHECK-NEXT: tbl z0.h, { z0.h }, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: dup v0.2s, v0.s[1] -; NONEON-NOSVE-NEXT: ret %ret = call <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half> %op, i64 2) ret <2 x half> %ret } @@ -289,14 +201,6 @@ define <4 x half> @extract_subvector_v8f16(<8 x half> %op) { ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %ret = call <4 x half> @llvm.vector.extract.v4f16.v8f16(<8 x half> %op, i64 4) ret <4 x half> %ret } @@ -307,12 +211,6 @@ define void @extract_subvector_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0, #16] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %ret = call <8 x half> @llvm.vector.extract.v8f16.v16f16(<16 x half> %op, i64 8) store <8 x half> %ret, ptr %b @@ -328,12 +226,6 @@ define <1 x float> @extract_subvector_v2f32(<2 x float> %op) { ; CHECK-NEXT: mov z0.s, z0.s[1] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: dup v0.2s, v0.s[1] -; NONEON-NOSVE-NEXT: ret %ret = call <1 x float> @llvm.vector.extract.v1f32.v2f32(<2 x float> %op, i64 1) ret <1 x float> %ret } @@ -345,14 +237,6 @@ define <2 x float> @extract_subvector_v4f32(<4 x float> %op) { ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %ret = call <2 x float> @llvm.vector.extract.v2f32.v4f32(<4 x float> %op, i64 2) ret <2 x float> %ret } @@ -363,12 +247,6 @@ define void @extract_subvector_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0, #16] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %ret = call <4 x float> @llvm.vector.extract.v4f32.v8f32(<8 x float> %op, i64 4) store <4 x float> %ret, ptr %b @@ -384,14 +262,6 @@ define <1 x double> @extract_subvector_v2f64(<2 x double> %op) { ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %ret = call <1 x double> @llvm.vector.extract.v1f64.v2f64(<2 x double> %op, i64 1) ret <1 x double> %ret } @@ -402,12 +272,6 @@ define void @extract_subvector_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q0, [x0, #16] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extract_subvector_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %ret = call <2 x double> @llvm.vector.extract.v2f64.v4f64(<4 x double> %op, i64 2) store <2 x double> %ret, ptr %b diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll index b2cf818e6e3c..a752e119b2fb 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -16,12 +15,6 @@ define half @extractelement_v2f16(<2 x half> %op1) { ; CHECK-NEXT: mov z0.h, z0.h[1] ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extractelement_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h0, v0.h[1] -; NONEON-NOSVE-NEXT: ret %r = extractelement <2 x half> %op1, i64 1 ret half %r } @@ -33,12 +26,6 @@ define half @extractelement_v4f16(<4 x half> %op1) { ; CHECK-NEXT: mov z0.h, z0.h[3] ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extractelement_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h0, v0.h[3] -; NONEON-NOSVE-NEXT: ret %r = extractelement <4 x half> %op1, i64 3 ret half %r } @@ -50,11 +37,6 @@ define half @extractelement_v8f16(<8 x half> %op1) { ; CHECK-NEXT: mov z0.h, z0.h[7] ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extractelement_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: ret %r = extractelement <8 x half> %op1, i64 7 ret half %r } @@ -66,11 +48,6 @@ define half @extractelement_v16f16(ptr %a) { ; CHECK-NEXT: mov z0.h, z0.h[7] ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extractelement_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr h0, [x0, #30] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %r = extractelement <16 x half> %op1, i64 15 ret half %r @@ -83,12 +60,6 @@ define float @extractelement_v2f32(<2 x float> %op1) { ; CHECK-NEXT: mov z0.s, z0.s[1] ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extractelement_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov s0, v0.s[1] -; NONEON-NOSVE-NEXT: ret %r = extractelement <2 x float> %op1, i64 1 ret float %r } @@ -100,11 +71,6 @@ define float @extractelement_v4f32(<4 x float> %op1) { ; CHECK-NEXT: mov z0.s, z0.s[3] ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extractelement_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov s0, v0.s[3] -; NONEON-NOSVE-NEXT: ret %r = extractelement <4 x float> %op1, i64 3 ret float %r } @@ -116,11 +82,6 @@ define float @extractelement_v8f32(ptr %a) { ; CHECK-NEXT: mov z0.s, z0.s[3] ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extractelement_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr s0, [x0, #28] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %r = extractelement <8 x float> %op1, i64 7 ret float %r @@ -130,10 +91,6 @@ define double @extractelement_v1f64(<1 x double> %op1) { ; CHECK-LABEL: extractelement_v1f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extractelement_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ret %r = extractelement <1 x double> %op1, i64 0 ret double %r } @@ -144,11 +101,6 @@ define double @extractelement_v2f64(<2 x double> %op1) { ; CHECK-NEXT: mov z0.d, z0.d[1] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extractelement_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov d0, v0.d[1] -; NONEON-NOSVE-NEXT: ret %r = extractelement <2 x double> %op1, i64 1 ret double %r } @@ -160,11 +112,6 @@ define double @extractelement_v4f64(ptr %a) { ; CHECK-NEXT: mov z0.d, z0.d[1] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extractelement_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0, #24] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %r = extractelement <4 x double> %op1, i64 3 ret double %r diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll index bed5dd53c519..0d6675def8b5 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll @@ -2,7 +2,6 @@ ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE ; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2 ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2 -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" @@ -29,16 +28,6 @@ define void @test_copysign_v4f16_v4f16(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z1.d, z1.d, z2.d, z0.d ; SVE2-NEXT: str d1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v4f16_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #32767 // =0x7fff -; NONEON-NOSVE-NEXT: ldr d1, [x0] -; NONEON-NOSVE-NEXT: ldr d2, [x1] -; NONEON-NOSVE-NEXT: dup v0.4h, w8 -; NONEON-NOSVE-NEXT: bsl v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <4 x half>, ptr %ap %b = load <4 x half>, ptr %bp %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b) @@ -65,16 +54,6 @@ define void @test_copysign_v8f16_v8f16(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z1.d, z1.d, z2.d, z0.d ; SVE2-NEXT: str q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v8f16_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #32767 // =0x7fff -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: ldr q2, [x1] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: bsl v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <8 x half>, ptr %ap %b = load <8 x half>, ptr %bp %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b) @@ -105,17 +84,6 @@ define void @test_copysign_v16f16_v16f16(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z3.d, z3.d, z4.d, z0.d ; SVE2-NEXT: stp q2, q3, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v16f16_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #32767 // =0x7fff -; NONEON-NOSVE-NEXT: ldp q1, q4, [x1] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: bit v1.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: bsl v0.16b, v3.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <16 x half>, ptr %ap %b = load <16 x half>, ptr %bp %r = call <16 x half> @llvm.copysign.v16f16(<16 x half> %a, <16 x half> %b) @@ -144,16 +112,6 @@ define void @test_copysign_v2f32_v2f32(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z1.d, z1.d, z2.d, z0.d ; SVE2-NEXT: str d1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v2f32_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d0, #0xffffffffffffffff -; NONEON-NOSVE-NEXT: ldr d1, [x0] -; NONEON-NOSVE-NEXT: ldr d2, [x1] -; NONEON-NOSVE-NEXT: fneg v0.2s, v0.2s -; NONEON-NOSVE-NEXT: bsl v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <2 x float>, ptr %ap %b = load <2 x float>, ptr %bp %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b) @@ -180,16 +138,6 @@ define void @test_copysign_v4f32_v4f32(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z1.d, z1.d, z2.d, z0.d ; SVE2-NEXT: str q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v4f32_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0xffffffffffffffff -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: ldr q2, [x1] -; NONEON-NOSVE-NEXT: fneg v0.4s, v0.4s -; NONEON-NOSVE-NEXT: bsl v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <4 x float>, ptr %ap %b = load <4 x float>, ptr %bp %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b) @@ -220,17 +168,6 @@ define void @test_copysign_v8f32_v8f32(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z3.d, z3.d, z4.d, z0.d ; SVE2-NEXT: stp q2, q3, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v8f32_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0xffffffffffffffff -; NONEON-NOSVE-NEXT: ldp q1, q4, [x1] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: fneg v0.4s, v0.4s -; NONEON-NOSVE-NEXT: bit v1.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: bsl v0.16b, v3.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <8 x float>, ptr %ap %b = load <8 x float>, ptr %bp %r = call <8 x float> @llvm.copysign.v8f32(<8 x float> %a, <8 x float> %b) @@ -259,16 +196,6 @@ define void @test_copysign_v2f64_v2f64(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z1.d, z1.d, z2.d, z0.d ; SVE2-NEXT: str q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v2f64_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0xffffffffffffffff -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: ldr q2, [x1] -; NONEON-NOSVE-NEXT: fneg v0.2d, v0.2d -; NONEON-NOSVE-NEXT: bsl v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <2 x double>, ptr %ap %b = load <2 x double>, ptr %bp %r = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b) @@ -299,17 +226,6 @@ define void @test_copysign_v4f64_v4f64(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z3.d, z3.d, z4.d, z0.d ; SVE2-NEXT: stp q2, q3, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v4f64_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0xffffffffffffffff -; NONEON-NOSVE-NEXT: ldp q1, q4, [x1] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: fneg v0.2d, v0.2d -; NONEON-NOSVE-NEXT: bit v1.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: bsl v0.16b, v3.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <4 x double>, ptr %ap %b = load <4 x double>, ptr %bp %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b) @@ -344,17 +260,6 @@ define void @test_copysign_v2f32_v2f64(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z2.d, z2.d, z0.d, z1.d ; SVE2-NEXT: str d2, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v2f32_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d0, #0xffffffffffffffff -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: ldr d2, [x0] -; NONEON-NOSVE-NEXT: fcvtn v1.2s, v1.2d -; NONEON-NOSVE-NEXT: fneg v0.2s, v0.2s -; NONEON-NOSVE-NEXT: bsl v0.8b, v2.8b, v1.8b -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <2 x float>, ptr %ap %b = load <2 x double>, ptr %bp %tmp0 = fptrunc <2 x double> %b to <2 x float> @@ -399,18 +304,6 @@ define void @test_copysign_v4f32_v4f64(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z2.d, z2.d, z0.d, z1.d ; SVE2-NEXT: str q2, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v4f32_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q2, [x1] -; NONEON-NOSVE-NEXT: movi v0.2d, #0xffffffffffffffff -; NONEON-NOSVE-NEXT: fcvtn v1.2s, v1.2d -; NONEON-NOSVE-NEXT: fneg v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v1.4s, v2.2d -; NONEON-NOSVE-NEXT: ldr q2, [x0] -; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v1.16b -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <4 x float>, ptr %ap %b = load <4 x double>, ptr %bp %tmp0 = fptrunc <4 x double> %b to <4 x float> @@ -444,17 +337,6 @@ define void @test_copysign_v2f64_v2f32(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z2.d, z2.d, z0.d, z1.d ; SVE2-NEXT: str q2, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v2f64_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0xffffffffffffffff -; NONEON-NOSVE-NEXT: ldr d1, [x1] -; NONEON-NOSVE-NEXT: ldr q2, [x0] -; NONEON-NOSVE-NEXT: fcvtl v1.2d, v1.2s -; NONEON-NOSVE-NEXT: fneg v0.2d, v0.2d -; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v1.16b -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <2 x double>, ptr %ap %b = load < 2 x float>, ptr %bp %tmp0 = fpext <2 x float> %b to <2 x double> @@ -499,23 +381,6 @@ define void @test_copysign_v4f64_v4f32(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z4.d, z4.d, z1.d, z2.d ; SVE2-NEXT: stp q3, q4, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v4f64_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: movi v0.2d, #0xffffffffffffffff -; NONEON-NOSVE-NEXT: str q1, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d4, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v1.2d, v1.2s -; NONEON-NOSVE-NEXT: fneg v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtl v4.2d, v4.2s -; NONEON-NOSVE-NEXT: bit v1.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: bsl v0.16b, v3.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %a = load <4 x double>, ptr %ap %b = load <4 x float>, ptr %bp %tmp0 = fpext <4 x float> %b to <4 x double> @@ -551,17 +416,6 @@ define void @test_copysign_v4f16_v4f32(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z2.d, z2.d, z0.d, z1.d ; SVE2-NEXT: str d2, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v4f16_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x1] -; NONEON-NOSVE-NEXT: mov w8, #32767 // =0x7fff -; NONEON-NOSVE-NEXT: ldr d2, [x0] -; NONEON-NOSVE-NEXT: dup v1.4h, w8 -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: bit v0.8b, v2.8b, v1.8b -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <4 x half>, ptr %ap %b = load <4 x float>, ptr %bp %tmp0 = fptrunc <4 x float> %b to <4 x half> @@ -603,19 +457,6 @@ define void @test_copysign_v4f16_v4f64(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z2.d, z2.d, z0.d, z1.d ; SVE2-NEXT: str d2, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v4f16_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: mov w8, #32767 // =0x7fff -; NONEON-NOSVE-NEXT: ldr d2, [x0] -; NONEON-NOSVE-NEXT: fcvtxn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: fcvtxn2 v0.4s, v1.2d -; NONEON-NOSVE-NEXT: dup v1.4h, w8 -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: bit v0.8b, v2.8b, v1.8b -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <4 x half>, ptr %ap %b = load <4 x double>, ptr %bp %tmp0 = fptrunc <4 x double> %b to <4 x half> @@ -659,18 +500,6 @@ define void @test_copysign_v8f16_v8f32(ptr %ap, ptr %bp) { ; SVE2-NEXT: bsl z2.d, z2.d, z0.d, z1.d ; SVE2-NEXT: str q2, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_copysign_v8f16_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: mov w8, #32767 // =0x7fff -; NONEON-NOSVE-NEXT: ldr q2, [x0] -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: dup v1.8h, w8 -; NONEON-NOSVE-NEXT: bit v0.16b, v2.16b, v1.16b -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %a = load <8 x half>, ptr %ap %b = load <8 x float>, ptr %bp %tmp0 = fptrunc <8 x float> %b to <8 x half> diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll index 662a8f2b55fd..c2d6ed4e9ccf 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -18,14 +17,6 @@ define <2 x half> @fadd_v2f16(<2 x half> %op1, <2 x half> %op2) { ; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fadd <2 x half> %op1, %op2 ret <2 x half> %res } @@ -39,14 +30,6 @@ define <4 x half> @fadd_v4f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fadd <4 x half> %op1, %op2 ret <4 x half> %res } @@ -60,18 +43,6 @@ define <8 x half> @fadd_v8f16(<8 x half> %op1, <8 x half> %op2) { ; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fadd v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: fadd v1.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %res = fadd <8 x half> %op1, %op2 ret <8 x half> %res } @@ -87,29 +58,6 @@ define void @fadd_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fcvtl v4.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v6.4s, v3.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl v5.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v7.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fcvtl2 v3.4s, v3.8h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v2.8h -; NONEON-NOSVE-NEXT: fadd v4.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: fadd v5.4s, v7.4s, v6.4s -; NONEON-NOSVE-NEXT: fadd v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fadd v2.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: fcvtn v1.4h, v4.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v5.4s -; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v2.4s -; NONEON-NOSVE-NEXT: stp q1, q3, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %res = fadd <16 x half> %op1, %op2 @@ -126,11 +74,6 @@ define <2 x float> @fadd_v2f32(<2 x float> %op1, <2 x float> %op2) { ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fadd v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = fadd <2 x float> %op1, %op2 ret <2 x float> %res } @@ -144,11 +87,6 @@ define <4 x float> @fadd_v4f32(<4 x float> %op1, <4 x float> %op2) { ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = fadd <4 x float> %op1, %op2 ret <4 x float> %res } @@ -164,15 +102,6 @@ define void @fadd_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fadd v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fadd v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %res = fadd <8 x float> %op1, %op2 @@ -189,11 +118,6 @@ define <2 x double> @fadd_v2f64(<2 x double> %op1, <2 x double> %op2) { ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fadd v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = fadd <2 x double> %op1, %op2 ret <2 x double> %res } @@ -209,15 +133,6 @@ define void @fadd_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fadd v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fadd v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %res = fadd <4 x double> %op1, %op2 @@ -238,14 +153,6 @@ define <2 x half> @fdiv_v2f16(<2 x half> %op1, <2 x half> %op2) { ; CHECK-NEXT: fdiv z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fdiv_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fdiv v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fdiv <2 x half> %op1, %op2 ret <2 x half> %res } @@ -259,14 +166,6 @@ define <4 x half> @fdiv_v4f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-NEXT: fdiv z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fdiv_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fdiv v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fdiv <4 x half> %op1, %op2 ret <4 x half> %res } @@ -280,18 +179,6 @@ define <8 x half> @fdiv_v8f16(<8 x half> %op1, <8 x half> %op2) { ; CHECK-NEXT: fdiv z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fdiv_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fdiv v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: fdiv v1.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %res = fdiv <8 x half> %op1, %op2 ret <8 x half> %res } @@ -307,30 +194,6 @@ define void @fdiv_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: fdiv z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fdiv_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q4, q1, [x1] -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl2 v5.4s, v4.8h -; NONEON-NOSVE-NEXT: fcvtl v4.4s, v4.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fdiv v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: ldr q3, [x0] -; NONEON-NOSVE-NEXT: fcvtl2 v6.4s, v3.8h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v3.4h -; NONEON-NOSVE-NEXT: fdiv v3.4s, v3.4s, v4.4s -; NONEON-NOSVE-NEXT: fcvtn v2.4h, v2.4s -; NONEON-NOSVE-NEXT: fdiv v5.4s, v6.4s, v5.4s -; NONEON-NOSVE-NEXT: fdiv v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v1.4h, v3.4s -; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v5.4s -; NONEON-NOSVE-NEXT: fcvtn2 v2.8h, v0.4s -; NONEON-NOSVE-NEXT: stp q1, q2, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %res = fdiv <16 x half> %op1, %op2 @@ -347,11 +210,6 @@ define <2 x float> @fdiv_v2f32(<2 x float> %op1, <2 x float> %op2) { ; CHECK-NEXT: fdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fdiv_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fdiv v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = fdiv <2 x float> %op1, %op2 ret <2 x float> %res } @@ -365,11 +223,6 @@ define <4 x float> @fdiv_v4f32(<4 x float> %op1, <4 x float> %op2) { ; CHECK-NEXT: fdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fdiv_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fdiv v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = fdiv <4 x float> %op1, %op2 ret <4 x float> %res } @@ -385,15 +238,6 @@ define void @fdiv_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: fdiv z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fdiv_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fdiv v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fdiv v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %res = fdiv <8 x float> %op1, %op2 @@ -410,11 +254,6 @@ define <2 x double> @fdiv_v2f64(<2 x double> %op1, <2 x double> %op2) { ; CHECK-NEXT: fdiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fdiv_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fdiv v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = fdiv <2 x double> %op1, %op2 ret <2 x double> %res } @@ -430,15 +269,6 @@ define void @fdiv_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fdiv z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fdiv_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fdiv v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fdiv v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %res = fdiv <4 x double> %op1, %op2 @@ -460,46 +290,6 @@ define <2 x half> @fma_v2f16(<2 x half> %op1, <2 x half> %op2, <2 x half> %op3) ; CHECK-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d2 killed $d2 def $q2 -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[1] -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: fcvt s16, h0 -; NONEON-NOSVE-NEXT: mov h17, v2.h[2] -; NONEON-NOSVE-NEXT: mov h18, v1.h[2] -; NONEON-NOSVE-NEXT: mov h19, v0.h[2] -; NONEON-NOSVE-NEXT: mov h2, v2.h[3] -; NONEON-NOSVE-NEXT: mov h1, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fmadd s6, s16, s7, s6 -; NONEON-NOSVE-NEXT: mov h16, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt s7, h19 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmadd s3, s5, s4, s3 -; NONEON-NOSVE-NEXT: fcvt s4, h17 -; NONEON-NOSVE-NEXT: fcvt s5, h18 -; NONEON-NOSVE-NEXT: fcvt h0, s6 -; NONEON-NOSVE-NEXT: fmadd s4, s7, s5, s4 -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h16 -; NONEON-NOSVE-NEXT: mov v0.h[1], v3.h[0] -; NONEON-NOSVE-NEXT: fcvt h3, s4 -; NONEON-NOSVE-NEXT: fmadd s1, s5, s1, s2 -; NONEON-NOSVE-NEXT: mov v0.h[2], v3.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: mov v0.h[3], v1.h[0] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = call <2 x half> @llvm.fma.v2f16(<2 x half> %op1, <2 x half> %op2, <2 x half> %op3) ret <2 x half> %res } @@ -514,46 +304,6 @@ define <4 x half> @fma_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3) ; CHECK-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d2 killed $d2 def $q2 -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[1] -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: fcvt s16, h0 -; NONEON-NOSVE-NEXT: mov h17, v2.h[2] -; NONEON-NOSVE-NEXT: mov h18, v1.h[2] -; NONEON-NOSVE-NEXT: mov h19, v0.h[2] -; NONEON-NOSVE-NEXT: mov h2, v2.h[3] -; NONEON-NOSVE-NEXT: mov h1, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fmadd s6, s16, s7, s6 -; NONEON-NOSVE-NEXT: mov h16, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt s7, h19 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmadd s3, s5, s4, s3 -; NONEON-NOSVE-NEXT: fcvt s4, h17 -; NONEON-NOSVE-NEXT: fcvt s5, h18 -; NONEON-NOSVE-NEXT: fcvt h0, s6 -; NONEON-NOSVE-NEXT: fmadd s4, s7, s5, s4 -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h16 -; NONEON-NOSVE-NEXT: mov v0.h[1], v3.h[0] -; NONEON-NOSVE-NEXT: fcvt h3, s4 -; NONEON-NOSVE-NEXT: fmadd s1, s5, s1, s2 -; NONEON-NOSVE-NEXT: mov v0.h[2], v3.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: mov v0.h[3], v1.h[0] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.fma.v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3) ret <4 x half> %res } @@ -568,79 +318,6 @@ define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3) ; CHECK-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h3, v2.h[1] -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: fcvt s16, h0 -; NONEON-NOSVE-NEXT: mov h17, v2.h[2] -; NONEON-NOSVE-NEXT: mov h18, v1.h[2] -; NONEON-NOSVE-NEXT: mov h19, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fmadd s6, s16, s7, s6 -; NONEON-NOSVE-NEXT: fcvt s7, h17 -; NONEON-NOSVE-NEXT: fcvt s16, h18 -; NONEON-NOSVE-NEXT: fcvt s17, h19 -; NONEON-NOSVE-NEXT: mov h18, v1.h[3] -; NONEON-NOSVE-NEXT: mov h19, v0.h[3] -; NONEON-NOSVE-NEXT: fmadd s4, s5, s4, s3 -; NONEON-NOSVE-NEXT: mov h5, v2.h[3] -; NONEON-NOSVE-NEXT: fcvt h3, s6 -; NONEON-NOSVE-NEXT: fmadd s6, s17, s16, s7 -; NONEON-NOSVE-NEXT: mov h17, v2.h[4] -; NONEON-NOSVE-NEXT: fcvt s7, h18 -; NONEON-NOSVE-NEXT: fcvt s16, h19 -; NONEON-NOSVE-NEXT: mov h18, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: mov h19, v0.h[4] -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: fcvt s18, h18 -; NONEON-NOSVE-NEXT: mov v3.h[1], v4.h[0] -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: fmadd s5, s16, s7, s5 -; NONEON-NOSVE-NEXT: mov h7, v1.h[5] -; NONEON-NOSVE-NEXT: mov h16, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s19, h19 -; NONEON-NOSVE-NEXT: mov v3.h[2], v6.h[0] -; NONEON-NOSVE-NEXT: mov h6, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: fcvt h5, s5 -; NONEON-NOSVE-NEXT: fmadd s17, s19, s18, s17 -; NONEON-NOSVE-NEXT: mov h18, v1.h[6] -; NONEON-NOSVE-NEXT: mov h19, v0.h[6] -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fmadd s4, s16, s7, s4 -; NONEON-NOSVE-NEXT: mov v3.h[3], v5.h[0] -; NONEON-NOSVE-NEXT: fcvt s5, h6 -; NONEON-NOSVE-NEXT: fcvt s6, h18 -; NONEON-NOSVE-NEXT: fcvt s7, h19 -; NONEON-NOSVE-NEXT: fcvt h16, s17 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fmadd s5, s7, s6, s5 -; NONEON-NOSVE-NEXT: mov v3.h[4], v16.h[0] -; NONEON-NOSVE-NEXT: fmadd s0, s0, s1, s2 -; NONEON-NOSVE-NEXT: mov v3.h[5], v4.h[0] -; NONEON-NOSVE-NEXT: fcvt h4, s5 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: mov v3.h[6], v4.h[0] -; NONEON-NOSVE-NEXT: mov v3.h[7], v0.h[0] -; NONEON-NOSVE-NEXT: mov v0.16b, v3.16b -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.fma.v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3) ret <8 x half> %res } @@ -657,150 +334,6 @@ define void @fma_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: fmla z1.h, p0/m, z3.h, z4.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q3, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q4, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q5, q2, [x2] -; NONEON-NOSVE-NEXT: mov h25, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s19, h0 -; NONEON-NOSVE-NEXT: mov h24, v0.h[2] -; NONEON-NOSVE-NEXT: mov h17, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt s18, h1 -; NONEON-NOSVE-NEXT: mov h22, v1.h[2] -; NONEON-NOSVE-NEXT: mov h16, v2.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: mov h20, v2.h[2] -; NONEON-NOSVE-NEXT: mov h26, v5.h[1] -; NONEON-NOSVE-NEXT: mov h27, v4.h[1] -; NONEON-NOSVE-NEXT: mov h28, v3.h[1] -; NONEON-NOSVE-NEXT: fcvt s25, h25 -; NONEON-NOSVE-NEXT: mov h7, v2.h[3] -; NONEON-NOSVE-NEXT: mov h29, v4.h[2] -; NONEON-NOSVE-NEXT: fcvt s23, h17 -; NONEON-NOSVE-NEXT: mov h17, v0.h[3] -; NONEON-NOSVE-NEXT: mov h30, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s21, h16 -; NONEON-NOSVE-NEXT: fmadd s6, s19, s18, s6 -; NONEON-NOSVE-NEXT: fcvt s18, h20 -; NONEON-NOSVE-NEXT: fcvt s19, h22 -; NONEON-NOSVE-NEXT: fcvt s20, h24 -; NONEON-NOSVE-NEXT: mov h16, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s22, h5 -; NONEON-NOSVE-NEXT: fcvt s24, h4 -; NONEON-NOSVE-NEXT: fcvt s26, h26 -; NONEON-NOSVE-NEXT: fcvt s27, h27 -; NONEON-NOSVE-NEXT: fcvt s28, h28 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fmadd s21, s25, s23, s21 -; NONEON-NOSVE-NEXT: fcvt s23, h3 -; NONEON-NOSVE-NEXT: mov h25, v5.h[2] -; NONEON-NOSVE-NEXT: fmadd s18, s20, s19, s18 -; NONEON-NOSVE-NEXT: mov h19, v3.h[2] -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: mov h31, v0.h[4] -; NONEON-NOSVE-NEXT: fmadd s26, s28, s27, s26 -; NONEON-NOSVE-NEXT: mov h27, v4.h[3] -; NONEON-NOSVE-NEXT: mov h28, v3.h[3] -; NONEON-NOSVE-NEXT: fmadd s22, s23, s24, s22 -; NONEON-NOSVE-NEXT: fcvt h20, s21 -; NONEON-NOSVE-NEXT: mov h21, v2.h[4] -; NONEON-NOSVE-NEXT: fcvt s23, h25 -; NONEON-NOSVE-NEXT: fcvt s24, h29 -; NONEON-NOSVE-NEXT: fcvt s19, h19 -; NONEON-NOSVE-NEXT: fmadd s16, s17, s16, s7 -; NONEON-NOSVE-NEXT: mov h25, v5.h[3] -; NONEON-NOSVE-NEXT: fcvt h18, s18 -; NONEON-NOSVE-NEXT: fcvt h26, s26 -; NONEON-NOSVE-NEXT: mov h29, v2.h[5] -; NONEON-NOSVE-NEXT: mov v6.h[1], v20.h[0] -; NONEON-NOSVE-NEXT: fcvt s17, h21 -; NONEON-NOSVE-NEXT: fcvt s20, h30 -; NONEON-NOSVE-NEXT: fmadd s19, s19, s24, s23 -; NONEON-NOSVE-NEXT: fcvt s21, h31 -; NONEON-NOSVE-NEXT: fcvt h7, s22 -; NONEON-NOSVE-NEXT: fcvt s22, h25 -; NONEON-NOSVE-NEXT: fcvt s23, h27 -; NONEON-NOSVE-NEXT: fcvt s24, h28 -; NONEON-NOSVE-NEXT: mov h25, v5.h[4] -; NONEON-NOSVE-NEXT: mov h27, v4.h[4] -; NONEON-NOSVE-NEXT: mov h28, v3.h[4] -; NONEON-NOSVE-NEXT: mov h30, v1.h[5] -; NONEON-NOSVE-NEXT: mov h31, v0.h[5] -; NONEON-NOSVE-NEXT: mov v6.h[2], v18.h[0] -; NONEON-NOSVE-NEXT: fmadd s17, s21, s20, s17 -; NONEON-NOSVE-NEXT: mov v7.h[1], v26.h[0] -; NONEON-NOSVE-NEXT: fcvt h18, s19 -; NONEON-NOSVE-NEXT: fmadd s19, s24, s23, s22 -; NONEON-NOSVE-NEXT: mov h26, v5.h[5] -; NONEON-NOSVE-NEXT: fcvt h16, s16 -; NONEON-NOSVE-NEXT: fcvt s20, h25 -; NONEON-NOSVE-NEXT: fcvt s21, h27 -; NONEON-NOSVE-NEXT: fcvt s22, h28 -; NONEON-NOSVE-NEXT: mov h27, v4.h[5] -; NONEON-NOSVE-NEXT: mov h28, v3.h[5] -; NONEON-NOSVE-NEXT: fcvt s23, h29 -; NONEON-NOSVE-NEXT: fcvt s24, h30 -; NONEON-NOSVE-NEXT: fcvt s25, h31 -; NONEON-NOSVE-NEXT: mov h29, v2.h[6] -; NONEON-NOSVE-NEXT: mov h30, v1.h[6] -; NONEON-NOSVE-NEXT: mov h31, v0.h[6] -; NONEON-NOSVE-NEXT: mov v7.h[2], v18.h[0] -; NONEON-NOSVE-NEXT: fcvt h18, s19 -; NONEON-NOSVE-NEXT: fmadd s19, s22, s21, s20 -; NONEON-NOSVE-NEXT: mov h20, v5.h[6] -; NONEON-NOSVE-NEXT: mov h21, v4.h[6] -; NONEON-NOSVE-NEXT: mov h22, v3.h[6] -; NONEON-NOSVE-NEXT: fcvt s26, h26 -; NONEON-NOSVE-NEXT: fmadd s23, s25, s24, s23 -; NONEON-NOSVE-NEXT: fcvt s27, h27 -; NONEON-NOSVE-NEXT: fcvt s28, h28 -; NONEON-NOSVE-NEXT: mov v6.h[3], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h16, s17 -; NONEON-NOSVE-NEXT: fcvt s17, h29 -; NONEON-NOSVE-NEXT: fcvt s24, h30 -; NONEON-NOSVE-NEXT: fcvt s25, h31 -; NONEON-NOSVE-NEXT: fcvt s20, h20 -; NONEON-NOSVE-NEXT: fcvt s21, h21 -; NONEON-NOSVE-NEXT: fcvt s22, h22 -; NONEON-NOSVE-NEXT: mov v7.h[3], v18.h[0] -; NONEON-NOSVE-NEXT: fmadd s26, s28, s27, s26 -; NONEON-NOSVE-NEXT: fcvt h18, s19 -; NONEON-NOSVE-NEXT: mov h5, v5.h[7] -; NONEON-NOSVE-NEXT: mov h4, v4.h[7] -; NONEON-NOSVE-NEXT: mov h3, v3.h[7] -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: fmadd s17, s25, s24, s17 -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fmadd s19, s22, s21, s20 -; NONEON-NOSVE-NEXT: mov v6.h[4], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h16, s23 -; NONEON-NOSVE-NEXT: mov v7.h[4], v18.h[0] -; NONEON-NOSVE-NEXT: fcvt h18, s26 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v6.h[5], v16.h[0] -; NONEON-NOSVE-NEXT: mov v7.h[5], v18.h[0] -; NONEON-NOSVE-NEXT: fmadd s3, s3, s4, s5 -; NONEON-NOSVE-NEXT: fcvt h4, s19 -; NONEON-NOSVE-NEXT: fcvt h5, s17 -; NONEON-NOSVE-NEXT: fmadd s0, s0, s1, s2 -; NONEON-NOSVE-NEXT: mov v7.h[6], v4.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s3 -; NONEON-NOSVE-NEXT: mov v6.h[6], v5.h[0] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: mov v7.h[7], v1.h[0] -; NONEON-NOSVE-NEXT: mov v6.h[7], v0.h[0] -; NONEON-NOSVE-NEXT: stp q7, q6, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %op3 = load <16 x half>, ptr %c @@ -819,12 +352,6 @@ define <2 x float> @fma_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %o ; CHECK-NEXT: fmad z0.s, p0/m, z1.s, z2.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmla v2.2s, v1.2s, v0.2s -; NONEON-NOSVE-NEXT: fmov d0, d2 -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.fma.v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %op3) ret <2 x float> %res } @@ -839,12 +366,6 @@ define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %o ; CHECK-NEXT: fmad z0.s, p0/m, z1.s, z2.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmla v2.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.fma.v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %op3) ret <4 x float> %res } @@ -861,16 +382,6 @@ define void @fma_v8f32(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: fmla z1.s, p0/m, z3.s, z4.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q4, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q5, [x2] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: fmla v1.4s, v0.4s, v2.4s -; NONEON-NOSVE-NEXT: fmla v5.4s, v4.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q1, q5, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %op3 = load <8 x float>, ptr %c @@ -889,12 +400,6 @@ define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double ; CHECK-NEXT: fmad z0.d, p0/m, z1.d, z2.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmla v2.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.fma.v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double> %op3) ret <2 x double> %res } @@ -911,16 +416,6 @@ define void @fma_v4f64(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: fmla z1.d, p0/m, z3.d, z4.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q4, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q5, [x2] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: fmla v1.2d, v0.2d, v2.2d -; NONEON-NOSVE-NEXT: fmla v5.2d, v4.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q1, q5, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %op3 = load <4 x double>, ptr %c @@ -942,14 +437,6 @@ define <2 x half> @fmul_v2f16(<2 x half> %op1, <2 x half> %op2) { ; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmul_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fmul v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fmul <2 x half> %op1, %op2 ret <2 x half> %res } @@ -963,14 +450,6 @@ define <4 x half> @fmul_v4f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmul_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fmul v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fmul <4 x half> %op1, %op2 ret <4 x half> %res } @@ -984,18 +463,6 @@ define <8 x half> @fmul_v8f16(<8 x half> %op1, <8 x half> %op2) { ; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmul_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fmul v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: fmul v1.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %res = fmul <8 x half> %op1, %op2 ret <8 x half> %res } @@ -1011,29 +478,6 @@ define void @fmul_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: fmul z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmul_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fcvtl v4.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v6.4s, v3.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl v5.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v7.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fcvtl2 v3.4s, v3.8h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v2.8h -; NONEON-NOSVE-NEXT: fmul v4.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: fmul v5.4s, v7.4s, v6.4s -; NONEON-NOSVE-NEXT: fmul v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fmul v2.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: fcvtn v1.4h, v4.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v5.4s -; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v2.4s -; NONEON-NOSVE-NEXT: stp q1, q3, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %res = fmul <16 x half> %op1, %op2 @@ -1050,11 +494,6 @@ define <2 x float> @fmul_v2f32(<2 x float> %op1, <2 x float> %op2) { ; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmul_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmul v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = fmul <2 x float> %op1, %op2 ret <2 x float> %res } @@ -1068,11 +507,6 @@ define <4 x float> @fmul_v4f32(<4 x float> %op1, <4 x float> %op2) { ; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmul_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmul v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = fmul <4 x float> %op1, %op2 ret <4 x float> %res } @@ -1088,15 +522,6 @@ define void @fmul_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: fmul z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmul_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fmul v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fmul v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %res = fmul <8 x float> %op1, %op2 @@ -1113,11 +538,6 @@ define <2 x double> @fmul_v2f64(<2 x double> %op1, <2 x double> %op2) { ; CHECK-NEXT: fmul z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmul_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmul v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = fmul <2 x double> %op1, %op2 ret <2 x double> %res } @@ -1133,15 +553,6 @@ define void @fmul_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fmul z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmul_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fmul v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fmul v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %res = fmul <4 x double> %op1, %op2 @@ -1161,12 +572,6 @@ define <2 x half> @fneg_v2f16(<2 x half> %op) { ; CHECK-NEXT: fneg z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fneg_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v1.4h, #128, lsl #8 -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = fneg <2 x half> %op ret <2 x half> %res } @@ -1179,12 +584,6 @@ define <4 x half> @fneg_v4f16(<4 x half> %op) { ; CHECK-NEXT: fneg z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fneg_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v1.4h, #128, lsl #8 -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = fneg <4 x half> %op ret <4 x half> %res } @@ -1197,12 +596,6 @@ define <8 x half> @fneg_v8f16(<8 x half> %op) { ; CHECK-NEXT: fneg z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fneg_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v1.8h, #128, lsl #8 -; NONEON-NOSVE-NEXT: eor v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = fneg <8 x half> %op ret <8 x half> %res } @@ -1216,15 +609,6 @@ define void @fneg_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: fneg z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fneg_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.8h, #128, lsl #8 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: eor v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: eor v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = fneg <16 x half> %op store <16 x half> %res, ptr %a @@ -1239,11 +623,6 @@ define <2 x float> @fneg_v2f32(<2 x float> %op) { ; CHECK-NEXT: fneg z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fneg_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fneg v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = fneg <2 x float> %op ret <2 x float> %res } @@ -1256,11 +635,6 @@ define <4 x float> @fneg_v4f32(<4 x float> %op) { ; CHECK-NEXT: fneg z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fneg_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fneg v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fneg <4 x float> %op ret <4 x float> %res } @@ -1274,14 +648,6 @@ define void @fneg_v8f32(ptr %a) { ; CHECK-NEXT: fneg z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fneg_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fneg v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fneg v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = fneg <8 x float> %op store <8 x float> %res, ptr %a @@ -1296,11 +662,6 @@ define <2 x double> @fneg_v2f64(<2 x double> %op) { ; CHECK-NEXT: fneg z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fneg_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fneg v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = fneg <2 x double> %op ret <2 x double> %res } @@ -1314,14 +675,6 @@ define void @fneg_v4f64(ptr %a) { ; CHECK-NEXT: fneg z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fneg_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fneg v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fneg v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = fneg <4 x double> %op store <4 x double> %res, ptr %a @@ -1340,30 +693,6 @@ define <2 x half> @fsqrt_v2f16(<2 x half> %op) { ; CHECK-NEXT: fsqrt z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsqrt_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: mov h3, v0.h[2] -; NONEON-NOSVE-NEXT: mov h0, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fsqrt s2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fsqrt s1, s1 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fsqrt s3, s3 -; NONEON-NOSVE-NEXT: fsqrt s4, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s2 -; NONEON-NOSVE-NEXT: mov v0.h[1], v1.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s3 -; NONEON-NOSVE-NEXT: mov v0.h[2], v1.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s4 -; NONEON-NOSVE-NEXT: mov v0.h[3], v1.h[0] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = call <2 x half> @llvm.sqrt.v2f16(<2 x half> %op) ret <2 x half> %res } @@ -1376,30 +705,6 @@ define <4 x half> @fsqrt_v4f16(<4 x half> %op) { ; CHECK-NEXT: fsqrt z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsqrt_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: mov h3, v0.h[2] -; NONEON-NOSVE-NEXT: mov h0, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fsqrt s2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fsqrt s1, s1 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fsqrt s3, s3 -; NONEON-NOSVE-NEXT: fsqrt s4, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s2 -; NONEON-NOSVE-NEXT: mov v0.h[1], v1.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s3 -; NONEON-NOSVE-NEXT: mov v0.h[2], v1.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s4 -; NONEON-NOSVE-NEXT: mov v0.h[3], v1.h[0] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.sqrt.v4f16(<4 x half> %op) ret <4 x half> %res } @@ -1412,48 +717,6 @@ define <8 x half> @fsqrt_v8f16(<8 x half> %op) { ; CHECK-NEXT: fsqrt z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsqrt_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: mov h3, v0.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[3] -; NONEON-NOSVE-NEXT: mov h5, v0.h[4] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: mov h7, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fsqrt s2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt s16, h0 -; NONEON-NOSVE-NEXT: fcvt h0, s2 -; NONEON-NOSVE-NEXT: fsqrt s1, s1 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: mov v0.h[1], v1.h[0] -; NONEON-NOSVE-NEXT: fsqrt s3, s3 -; NONEON-NOSVE-NEXT: fcvt h1, s3 -; NONEON-NOSVE-NEXT: mov v0.h[2], v1.h[0] -; NONEON-NOSVE-NEXT: fsqrt s4, s4 -; NONEON-NOSVE-NEXT: fcvt h1, s4 -; NONEON-NOSVE-NEXT: mov v0.h[3], v1.h[0] -; NONEON-NOSVE-NEXT: fsqrt s5, s5 -; NONEON-NOSVE-NEXT: fcvt h1, s5 -; NONEON-NOSVE-NEXT: mov v0.h[4], v1.h[0] -; NONEON-NOSVE-NEXT: fsqrt s6, s6 -; NONEON-NOSVE-NEXT: fcvt h1, s6 -; NONEON-NOSVE-NEXT: mov v0.h[5], v1.h[0] -; NONEON-NOSVE-NEXT: fsqrt s7, s7 -; NONEON-NOSVE-NEXT: fcvt h1, s7 -; NONEON-NOSVE-NEXT: mov v0.h[6], v1.h[0] -; NONEON-NOSVE-NEXT: fsqrt s2, s16 -; NONEON-NOSVE-NEXT: fcvt h1, s2 -; NONEON-NOSVE-NEXT: mov v0.h[7], v1.h[0] -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.sqrt.v8f16(<8 x half> %op) ret <8 x half> %res } @@ -1467,89 +730,6 @@ define void @fsqrt_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: fsqrt z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsqrt_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q16, [x0] -; NONEON-NOSVE-NEXT: mov h0, v1.h[1] -; NONEON-NOSVE-NEXT: mov h17, v16.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s18, h16 -; NONEON-NOSVE-NEXT: mov h19, v16.h[2] -; NONEON-NOSVE-NEXT: mov h4, v1.h[3] -; NONEON-NOSVE-NEXT: mov h20, v16.h[3] -; NONEON-NOSVE-NEXT: mov h5, v1.h[4] -; NONEON-NOSVE-NEXT: mov h21, v16.h[4] -; NONEON-NOSVE-NEXT: mov h6, v1.h[5] -; NONEON-NOSVE-NEXT: mov h22, v16.h[5] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: fsqrt s2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s19, h19 -; NONEON-NOSVE-NEXT: mov h7, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s20, h20 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s21, h21 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s22, h22 -; NONEON-NOSVE-NEXT: mov h23, v16.h[6] -; NONEON-NOSVE-NEXT: mov h16, v16.h[7] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt s23, h23 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fsqrt s0, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: mov v2.h[1], v0.h[0] -; NONEON-NOSVE-NEXT: fsqrt s17, s17 -; NONEON-NOSVE-NEXT: fcvt h17, s17 -; NONEON-NOSVE-NEXT: fsqrt s18, s18 -; NONEON-NOSVE-NEXT: fcvt h18, s18 -; NONEON-NOSVE-NEXT: mov v18.h[1], v17.h[0] -; NONEON-NOSVE-NEXT: fsqrt s3, s3 -; NONEON-NOSVE-NEXT: fcvt h0, s3 -; NONEON-NOSVE-NEXT: mov v2.h[2], v0.h[0] -; NONEON-NOSVE-NEXT: fsqrt s19, s19 -; NONEON-NOSVE-NEXT: fcvt h17, s19 -; NONEON-NOSVE-NEXT: mov v18.h[2], v17.h[0] -; NONEON-NOSVE-NEXT: fsqrt s4, s4 -; NONEON-NOSVE-NEXT: fcvt h0, s4 -; NONEON-NOSVE-NEXT: mov v2.h[3], v0.h[0] -; NONEON-NOSVE-NEXT: fsqrt s20, s20 -; NONEON-NOSVE-NEXT: fcvt h3, s20 -; NONEON-NOSVE-NEXT: mov v18.h[3], v3.h[0] -; NONEON-NOSVE-NEXT: fsqrt s5, s5 -; NONEON-NOSVE-NEXT: fcvt h0, s5 -; NONEON-NOSVE-NEXT: mov v2.h[4], v0.h[0] -; NONEON-NOSVE-NEXT: fsqrt s21, s21 -; NONEON-NOSVE-NEXT: fcvt h3, s21 -; NONEON-NOSVE-NEXT: mov v18.h[4], v3.h[0] -; NONEON-NOSVE-NEXT: fsqrt s6, s6 -; NONEON-NOSVE-NEXT: fcvt h0, s6 -; NONEON-NOSVE-NEXT: mov v2.h[5], v0.h[0] -; NONEON-NOSVE-NEXT: fsqrt s22, s22 -; NONEON-NOSVE-NEXT: fcvt h3, s22 -; NONEON-NOSVE-NEXT: mov v18.h[5], v3.h[0] -; NONEON-NOSVE-NEXT: fsqrt s7, s7 -; NONEON-NOSVE-NEXT: fcvt h0, s7 -; NONEON-NOSVE-NEXT: mov v2.h[6], v0.h[0] -; NONEON-NOSVE-NEXT: fsqrt s23, s23 -; NONEON-NOSVE-NEXT: fcvt h3, s23 -; NONEON-NOSVE-NEXT: mov v18.h[6], v3.h[0] -; NONEON-NOSVE-NEXT: fsqrt s16, s16 -; NONEON-NOSVE-NEXT: fcvt h3, s16 -; NONEON-NOSVE-NEXT: mov v18.h[7], v3.h[0] -; NONEON-NOSVE-NEXT: fsqrt s1, s1 -; NONEON-NOSVE-NEXT: fcvt h0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[7], v0.h[0] -; NONEON-NOSVE-NEXT: stp q18, q2, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.sqrt.v16f16(<16 x half> %op) store <16 x half> %res, ptr %a @@ -1564,11 +744,6 @@ define <2 x float> @fsqrt_v2f32(<2 x float> %op) { ; CHECK-NEXT: fsqrt z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsqrt_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fsqrt v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %op) ret <2 x float> %res } @@ -1581,11 +756,6 @@ define <4 x float> @fsqrt_v4f32(<4 x float> %op) { ; CHECK-NEXT: fsqrt z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsqrt_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fsqrt v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %op) ret <4 x float> %res } @@ -1599,14 +769,6 @@ define void @fsqrt_v8f32(ptr %a) { ; CHECK-NEXT: fsqrt z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsqrt_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fsqrt v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fsqrt v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.sqrt.v8f32(<8 x float> %op) store <8 x float> %res, ptr %a @@ -1621,11 +783,6 @@ define <2 x double> @fsqrt_v2f64(<2 x double> %op) { ; CHECK-NEXT: fsqrt z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsqrt_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fsqrt v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %op) ret <2 x double> %res } @@ -1639,14 +796,6 @@ define void @fsqrt_v4f64(ptr %a) { ; CHECK-NEXT: fsqrt z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsqrt_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fsqrt v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fsqrt v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %op) store <4 x double> %res, ptr %a @@ -1666,14 +815,6 @@ define <2 x half> @fsub_v2f16(<2 x half> %op1, <2 x half> %op2) { ; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsub_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fsub v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fsub <2 x half> %op1, %op2 ret <2 x half> %res } @@ -1687,14 +828,6 @@ define <4 x half> @fsub_v4f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsub_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fsub v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fsub <4 x half> %op1, %op2 ret <4 x half> %res } @@ -1708,18 +841,6 @@ define <8 x half> @fsub_v8f16(<8 x half> %op1, <8 x half> %op2) { ; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsub_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fsub v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: fsub v1.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %res = fsub <8 x half> %op1, %op2 ret <8 x half> %res } @@ -1735,29 +856,6 @@ define void @fsub_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: fsub z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsub_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fcvtl v4.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v6.4s, v3.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl v5.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v7.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fcvtl2 v3.4s, v3.8h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v2.8h -; NONEON-NOSVE-NEXT: fsub v4.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: fsub v5.4s, v7.4s, v6.4s -; NONEON-NOSVE-NEXT: fsub v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fsub v2.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: fcvtn v1.4h, v4.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v5.4s -; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v2.4s -; NONEON-NOSVE-NEXT: stp q1, q3, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %res = fsub <16 x half> %op1, %op2 @@ -1774,11 +872,6 @@ define <2 x float> @fsub_v2f32(<2 x float> %op1, <2 x float> %op2) { ; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsub_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fsub v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = fsub <2 x float> %op1, %op2 ret <2 x float> %res } @@ -1792,11 +885,6 @@ define <4 x float> @fsub_v4f32(<4 x float> %op1, <4 x float> %op2) { ; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsub_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fsub v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = fsub <4 x float> %op1, %op2 ret <4 x float> %res } @@ -1812,15 +900,6 @@ define void @fsub_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: fsub z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsub_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fsub v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fsub v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %res = fsub <8 x float> %op1, %op2 @@ -1837,11 +916,6 @@ define <2 x double> @fsub_v2f64(<2 x double> %op1, <2 x double> %op2) { ; CHECK-NEXT: fsub z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsub_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fsub v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = fsub <2 x double> %op1, %op2 ret <2 x double> %res } @@ -1857,15 +931,6 @@ define void @fsub_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fsub z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fsub_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fsub v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fsub v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %res = fsub <4 x double> %op1, %op2 @@ -1885,11 +950,6 @@ define <2 x half> @fabs_v2f16(<2 x half> %op) { ; CHECK-NEXT: fabs z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fabs_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: bic v0.4h, #128, lsl #8 -; NONEON-NOSVE-NEXT: ret %res = call <2 x half> @llvm.fabs.v2f16(<2 x half> %op) ret <2 x half> %res } @@ -1902,11 +962,6 @@ define <4 x half> @fabs_v4f16(<4 x half> %op) { ; CHECK-NEXT: fabs z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fabs_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: bic v0.4h, #128, lsl #8 -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.fabs.v4f16(<4 x half> %op) ret <4 x half> %res } @@ -1919,11 +974,6 @@ define <8 x half> @fabs_v8f16(<8 x half> %op) { ; CHECK-NEXT: fabs z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fabs_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: bic v0.8h, #128, lsl #8 -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.fabs.v8f16(<8 x half> %op) ret <8 x half> %res } @@ -1937,14 +987,6 @@ define void @fabs_v16f16(ptr %a) { ; CHECK-NEXT: fabs z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fabs_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: bic v0.8h, #128, lsl #8 -; NONEON-NOSVE-NEXT: bic v1.8h, #128, lsl #8 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.fabs.v16f16(<16 x half> %op) store <16 x half> %res, ptr %a @@ -1959,11 +1001,6 @@ define <2 x float> @fabs_v2f32(<2 x float> %op) { ; CHECK-NEXT: fabs z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fabs_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fabs v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.fabs.v2f32(<2 x float> %op) ret <2 x float> %res } @@ -1976,11 +1013,6 @@ define <4 x float> @fabs_v4f32(<4 x float> %op) { ; CHECK-NEXT: fabs z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fabs_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fabs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.fabs.v4f32(<4 x float> %op) ret <4 x float> %res } @@ -1994,14 +1026,6 @@ define void @fabs_v8f32(ptr %a) { ; CHECK-NEXT: fabs z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fabs_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fabs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fabs v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.fabs.v8f32(<8 x float> %op) store <8 x float> %res, ptr %a @@ -2016,11 +1040,6 @@ define <2 x double> @fabs_v2f64(<2 x double> %op) { ; CHECK-NEXT: fabs z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fabs_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fabs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.fabs.v2f64(<2 x double> %op) ret <2 x double> %res } @@ -2034,14 +1053,6 @@ define void @fabs_v4f64(ptr %a) { ; CHECK-NEXT: fabs z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fabs_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fabs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fabs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.fabs.v4f64(<4 x double> %op) store <4 x double> %res, ptr %a diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll index d4810c78cb53..465cc179a3b9 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -20,14 +19,6 @@ define <2 x i16> @fcmp_oeq_v2f16(<2 x half> %op1, <2 x half> %op2) { ; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_oeq_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcmeq v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %cmp = fcmp oeq <2 x half> %op1, %op2 %sext = sext <2 x i1> %cmp to <2 x i16> ret <2 x i16> %sext @@ -43,14 +34,6 @@ define <4 x i16> @fcmp_oeq_v4f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_oeq_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcmeq v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %cmp = fcmp oeq <4 x half> %op1, %op2 %sext = sext <4 x i1> %cmp to <4 x i16> ret <4 x i16> %sext @@ -66,65 +49,6 @@ define <8 x i16> @fcmp_oeq_v8f16(<8 x half> %op1, <8 x half> %op2) { ; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_oeq_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: mov h6, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcmp s3, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[2] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: fcvt s5, h6 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: mov h4, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov h6, v0.h[4] -; NONEON-NOSVE-NEXT: csetm w9, eq -; NONEON-NOSVE-NEXT: fcmp s2, s5 -; NONEON-NOSVE-NEXT: fmov s2, w9 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h5, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v2.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[5] -; NONEON-NOSVE-NEXT: mov h4, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[6] -; NONEON-NOSVE-NEXT: mov h6, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: fcvt s3, h5 -; NONEON-NOSVE-NEXT: fcvt s4, h6 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %cmp = fcmp oeq <8 x half> %op1, %op2 %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext @@ -142,123 +66,6 @@ define void @fcmp_oeq_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_oeq_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, eq -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, eq -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, eq -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, eq -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, eq -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, eq -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, eq -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, eq -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, eq -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp oeq <16 x half> %op1, %op2 @@ -277,11 +84,6 @@ define <2 x i32> @fcmp_oeq_v2f32(<2 x float> %op1, <2 x float> %op2) { ; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_oeq_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcmeq v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %cmp = fcmp oeq <2 x float> %op1, %op2 %sext = sext <2 x i1> %cmp to <2 x i32> ret <2 x i32> %sext @@ -297,11 +99,6 @@ define <4 x i32> @fcmp_oeq_v4f32(<4 x float> %op1, <4 x float> %op2) { ; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_oeq_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcmeq v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %cmp = fcmp oeq <4 x float> %op1, %op2 %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext @@ -319,15 +116,6 @@ define void @fcmp_oeq_v8f32(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_oeq_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fcmeq v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fcmeq v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %cmp = fcmp oeq <8 x float> %op1, %op2 @@ -344,11 +132,6 @@ define <1 x i64> @fcmp_oeq_v1f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK-NEXT: mov z0.d, x8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_oeq_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcmeq d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %cmp = fcmp oeq <1 x double> %op1, %op2 %sext = sext <1 x i1> %cmp to <1 x i64> ret <1 x i64> %sext @@ -364,11 +147,6 @@ define <2 x i64> @fcmp_oeq_v2f64(<2 x double> %op1, <2 x double> %op2) { ; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_oeq_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcmeq v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %cmp = fcmp oeq <2 x double> %op1, %op2 %sext = sext <2 x i1> %cmp to <2 x i64> ret <2 x i64> %sext @@ -386,15 +164,6 @@ define void @fcmp_oeq_v4f64(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.d, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_oeq_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fcmeq v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fcmeq v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %cmp = fcmp oeq <4 x double> %op1, %op2 @@ -423,139 +192,6 @@ define void @fcmp_ueq_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_ueq_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h2 -; NONEON-NOSVE-NEXT: mov h5, v2.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h1 -; NONEON-NOSVE-NEXT: mov h7, v1.h[2] -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s6, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[4] -; NONEON-NOSVE-NEXT: mov h6, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w9, eq -; NONEON-NOSVE-NEXT: csinv w12, w9, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s7, s5 -; NONEON-NOSVE-NEXT: mov h5, v2.h[5] -; NONEON-NOSVE-NEXT: mov h7, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w9, eq -; NONEON-NOSVE-NEXT: csinv w10, w9, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x1] -; NONEON-NOSVE-NEXT: csetm w9, eq -; NONEON-NOSVE-NEXT: csinv w11, w9, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s6, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[7] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s6, h16 -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w9, eq -; NONEON-NOSVE-NEXT: csinv w9, w9, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s7, s5 -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: mov h7, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w13, eq -; NONEON-NOSVE-NEXT: csinv w13, w13, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s6, s3 -; NONEON-NOSVE-NEXT: fcvt s3, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h7 -; NONEON-NOSVE-NEXT: mov h6, v0.h[2] -; NONEON-NOSVE-NEXT: mov h7, v1.h[2] -; NONEON-NOSVE-NEXT: csetm w14, eq -; NONEON-NOSVE-NEXT: csinv w14, w14, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s4, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w15, eq -; NONEON-NOSVE-NEXT: csinv w15, w15, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s5, s3 -; NONEON-NOSVE-NEXT: mov h3, v0.h[3] -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w16, eq -; NONEON-NOSVE-NEXT: csinv w16, w16, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s4, s2 -; NONEON-NOSVE-NEXT: fcvt s4, h3 -; NONEON-NOSVE-NEXT: fmov s2, w12 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w17, eq -; NONEON-NOSVE-NEXT: csinv w17, w17, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v0.h[4] -; NONEON-NOSVE-NEXT: fmov s3, w17 -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: mov v3.h[1], w16 -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v0.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: mov v2.h[2], w10 -; NONEON-NOSVE-NEXT: mov v3.h[2], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v0.h[6] -; NONEON-NOSVE-NEXT: mov h7, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w11 -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov v3.h[3], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: fcvt s4, h6 -; NONEON-NOSVE-NEXT: fcvt s5, h7 -; NONEON-NOSVE-NEXT: mov v2.h[4], w9 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v3.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov v2.h[5], w13 -; NONEON-NOSVE-NEXT: mov v3.h[5], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, vc -; NONEON-NOSVE-NEXT: fcmp s1, s0 -; NONEON-NOSVE-NEXT: mov v2.h[6], w14 -; NONEON-NOSVE-NEXT: mov v3.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, vc -; NONEON-NOSVE-NEXT: mov v2.h[7], w15 -; NONEON-NOSVE-NEXT: mov v3.h[7], w8 -; NONEON-NOSVE-NEXT: stp q3, q2, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp ueq <16 x half> %op1, %op2 @@ -584,139 +220,6 @@ define void @fcmp_one_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_one_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h2 -; NONEON-NOSVE-NEXT: mov h5, v2.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h1 -; NONEON-NOSVE-NEXT: mov h7, v1.h[2] -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, le -; NONEON-NOSVE-NEXT: fcmp s6, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[4] -; NONEON-NOSVE-NEXT: mov h6, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w9, mi -; NONEON-NOSVE-NEXT: csinv w12, w9, wzr, le -; NONEON-NOSVE-NEXT: fcmp s7, s5 -; NONEON-NOSVE-NEXT: mov h5, v2.h[5] -; NONEON-NOSVE-NEXT: mov h7, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w9, mi -; NONEON-NOSVE-NEXT: csinv w10, w9, wzr, le -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x1] -; NONEON-NOSVE-NEXT: csetm w9, mi -; NONEON-NOSVE-NEXT: csinv w11, w9, wzr, le -; NONEON-NOSVE-NEXT: fcmp s6, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[7] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s6, h16 -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w9, mi -; NONEON-NOSVE-NEXT: csinv w9, w9, wzr, le -; NONEON-NOSVE-NEXT: fcmp s7, s5 -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: mov h7, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w13, mi -; NONEON-NOSVE-NEXT: csinv w13, w13, wzr, le -; NONEON-NOSVE-NEXT: fcmp s6, s3 -; NONEON-NOSVE-NEXT: fcvt s3, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h7 -; NONEON-NOSVE-NEXT: mov h6, v0.h[2] -; NONEON-NOSVE-NEXT: mov h7, v1.h[2] -; NONEON-NOSVE-NEXT: csetm w14, mi -; NONEON-NOSVE-NEXT: csinv w14, w14, wzr, le -; NONEON-NOSVE-NEXT: fcmp s4, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w15, mi -; NONEON-NOSVE-NEXT: csinv w15, w15, wzr, le -; NONEON-NOSVE-NEXT: fcmp s5, s3 -; NONEON-NOSVE-NEXT: mov h3, v0.h[3] -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w16, mi -; NONEON-NOSVE-NEXT: csinv w16, w16, wzr, le -; NONEON-NOSVE-NEXT: fcmp s4, s2 -; NONEON-NOSVE-NEXT: fcvt s4, h3 -; NONEON-NOSVE-NEXT: fmov s2, w12 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w17, mi -; NONEON-NOSVE-NEXT: csinv w17, w17, wzr, le -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v0.h[4] -; NONEON-NOSVE-NEXT: fmov s3, w17 -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: mov v3.h[1], w16 -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, le -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v0.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: mov v2.h[2], w10 -; NONEON-NOSVE-NEXT: mov v3.h[2], w8 -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, le -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v0.h[6] -; NONEON-NOSVE-NEXT: mov h7, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w11 -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov v3.h[3], w8 -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, le -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: fcvt s4, h6 -; NONEON-NOSVE-NEXT: fcvt s5, h7 -; NONEON-NOSVE-NEXT: mov v2.h[4], w9 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v3.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, le -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov v2.h[5], w13 -; NONEON-NOSVE-NEXT: mov v3.h[5], w8 -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, le -; NONEON-NOSVE-NEXT: fcmp s1, s0 -; NONEON-NOSVE-NEXT: mov v2.h[6], w14 -; NONEON-NOSVE-NEXT: mov v3.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: csinv w8, w8, wzr, le -; NONEON-NOSVE-NEXT: mov v2.h[7], w15 -; NONEON-NOSVE-NEXT: mov v3.h[7], w8 -; NONEON-NOSVE-NEXT: stp q3, q2, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp one <16 x half> %op1, %op2 @@ -741,123 +244,6 @@ define void @fcmp_une_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_une_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, ne -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, ne -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, ne -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, ne -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, ne -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, ne -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, ne -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, ne -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, ne -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp une <16 x half> %op1, %op2 @@ -882,123 +268,6 @@ define void @fcmp_ogt_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_ogt_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, gt -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, gt -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, gt -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, gt -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, gt -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, gt -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, gt -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, gt -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, gt -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp ogt <16 x half> %op1, %op2 @@ -1026,123 +295,6 @@ define void @fcmp_ugt_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: eor z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_ugt_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, hi -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, hi -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, hi -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, hi -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, hi -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, hi -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, hi -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, hi -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, hi -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, hi -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, hi -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, hi -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, hi -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, hi -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, hi -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, hi -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp ugt <16 x half> %op1, %op2 @@ -1167,123 +319,6 @@ define void @fcmp_olt_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_olt_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, mi -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, mi -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, mi -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, mi -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, mi -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, mi -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, mi -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, mi -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, mi -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, mi -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp olt <16 x half> %op1, %op2 @@ -1311,123 +346,6 @@ define void @fcmp_ult_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: eor z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_ult_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, lt -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, lt -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, lt -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, lt -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, lt -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, lt -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, lt -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, lt -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, lt -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp ult <16 x half> %op1, %op2 @@ -1452,123 +370,6 @@ define void @fcmp_oge_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_oge_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, ge -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, ge -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, ge -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, ge -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, ge -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, ge -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, ge -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, ge -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, ge -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp oge <16 x half> %op1, %op2 @@ -1596,123 +397,6 @@ define void @fcmp_uge_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: eor z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_uge_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, pl -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, pl -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, pl -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, pl -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, pl -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, pl -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, pl -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, pl -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, pl -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, pl -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, pl -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, pl -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, pl -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, pl -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, pl -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, pl -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp uge <16 x half> %op1, %op2 @@ -1737,123 +421,6 @@ define void @fcmp_ole_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_ole_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, ls -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, ls -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, ls -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, ls -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, ls -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, ls -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, ls -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, ls -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, ls -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, ls -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, ls -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, ls -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, ls -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, ls -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, ls -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, ls -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp ole <16 x half> %op1, %op2 @@ -1881,123 +448,6 @@ define void @fcmp_ule_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: eor z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_ule_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, le -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, le -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, le -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, le -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, le -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, le -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, le -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, le -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, le -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp ule <16 x half> %op1, %op2 @@ -2022,123 +472,6 @@ define void @fcmp_uno_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_uno_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, vs -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, vs -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, vs -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, vs -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, vs -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, vs -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, vs -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, vs -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, vs -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, vs -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, vs -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, vs -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, vs -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, vs -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, vs -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, vs -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp uno <16 x half> %op1, %op2 @@ -2166,123 +499,6 @@ define void @fcmp_ord_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: eor z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_ord_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, vc -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, vc -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, vc -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, vc -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, vc -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, vc -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, vc -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, vc -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, vc -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, vc -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, vc -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, vc -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, vc -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, vc -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, vc -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, vc -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp ord <16 x half> %op1, %op2 @@ -2307,123 +523,6 @@ define void @fcmp_eq_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_eq_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, eq -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, eq -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, eq -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, eq -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, eq -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, eq -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, eq -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, eq -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, eq -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp fast oeq <16 x half> %op1, %op2 @@ -2448,123 +547,6 @@ define void @fcmp_ne_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_ne_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, ne -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, ne -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, ne -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, ne -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, ne -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, ne -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, ne -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, ne -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, ne -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp fast one <16 x half> %op1, %op2 @@ -2589,123 +571,6 @@ define void @fcmp_gt_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_gt_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, gt -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, gt -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, gt -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, gt -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, gt -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, gt -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, gt -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, gt -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, gt -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, gt -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp fast ogt <16 x half> %op1, %op2 @@ -2730,123 +595,6 @@ define void @fcmp_lt_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_lt_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, lt -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, lt -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, lt -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, lt -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, lt -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, lt -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, lt -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, lt -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, lt -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, lt -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp fast olt <16 x half> %op1, %op2 @@ -2871,123 +619,6 @@ define void @fcmp_ge_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_ge_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, ge -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, ge -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, ge -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, ge -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, ge -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, ge -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, ge -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, ge -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, ge -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, ge -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp fast oge <16 x half> %op1, %op2 @@ -3012,123 +643,6 @@ define void @fcmp_le_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x2] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcmp_le_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x1, #16] -; NONEON-NOSVE-NEXT: mov h0, v2.h[1] -; NONEON-NOSVE-NEXT: mov h3, v1.h[1] -; NONEON-NOSVE-NEXT: mov h4, v2.h[2] -; NONEON-NOSVE-NEXT: mov h5, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h2 -; NONEON-NOSVE-NEXT: fcvt s7, h1 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h0, v2.h[3] -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[4] -; NONEON-NOSVE-NEXT: mov h7, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w12, le -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v2.h[5] -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w11, le -; NONEON-NOSVE-NEXT: fcmp s3, s0 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w9, le -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: csetm w10, le -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[1] -; NONEON-NOSVE-NEXT: mov h5, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: csetm w13, le -; NONEON-NOSVE-NEXT: fcmp s7, s3 -; NONEON-NOSVE-NEXT: fmov s7, w12 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: csetm w14, le -; NONEON-NOSVE-NEXT: fcmp s6, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: mov v7.h[1], w8 -; NONEON-NOSVE-NEXT: csetm w15, le -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h4, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: mov v7.h[2], w11 -; NONEON-NOSVE-NEXT: csetm w16, le -; NONEON-NOSVE-NEXT: fcmp s5, s2 -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: csetm w17, le -; NONEON-NOSVE-NEXT: mov v7.h[3], w9 -; NONEON-NOSVE-NEXT: fmov s2, w17 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: mov h4, v0.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[1], w16 -; NONEON-NOSVE-NEXT: mov v7.h[4], w10 -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: mov h5, v1.h[5] -; NONEON-NOSVE-NEXT: mov h6, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: mov v7.h[5], w13 -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: mov h4, v0.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v7.h[6], w14 -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: fcmp s6, s5 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v7.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: fcmp s4, s3 -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: fcmp s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: csetm w8, le -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: stp q2, q7, [x2] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %cmp = fcmp fast ole <16 x half> %op1, %op2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll index ac0b6c0e0440..9bdde14e8d83 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -18,17 +17,6 @@ define void @fp_convert_combine_crash(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fp_convert_combine_crash: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov v0.4s, #8.00000000 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fmul v1.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fmul v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzs v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %f = load <8 x float>, ptr %a %mul.i = fmul <8 x float> %f, diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll index 16f30adbd14e..244a40510173 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -18,12 +17,6 @@ define void @fcvt_v2f16_to_v2f32(<2 x half> %a, ptr %b) { ; CHECK-NEXT: fcvt z0.s, p0/m, z0.h ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v2f16_to_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %res = fpext <2 x half> %a to <2 x float> store <2 x float> %res, ptr %b ret void @@ -38,12 +31,6 @@ define void @fcvt_v4f16_to_v4f32(<4 x half> %a, ptr %b) { ; CHECK-NEXT: fcvt z0.s, p0/m, z0.h ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v4f16_to_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %res = fpext <4 x half> %a to <4 x float> store <4 x float> %res, ptr %b ret void @@ -61,17 +48,6 @@ define void @fcvt_v8f16_to_v8f32(<8 x half> %a, ptr %b) { ; CHECK-NEXT: fcvt z0.s, p0/m, z0.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v8f16_to_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = fpext <8 x half> %a to <8 x float> store <8 x float> %res, ptr %b ret void @@ -96,21 +72,6 @@ define void @fcvt_v16f16_to_v16f32(<16 x half> %a, ptr %b) { ; CHECK-NEXT: stp q3, q0, [x0] ; CHECK-NEXT: stp q2, q1, [x0, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v16f16_to_v16f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v3.4h -; NONEON-NOSVE-NEXT: stp q0, q3, [x0] -; NONEON-NOSVE-NEXT: stp q1, q2, [x0, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %res = fpext <16 x half> %a to <16 x float> store <16 x float> %res, ptr %b ret void @@ -129,13 +90,6 @@ define void @fcvt_v2f16_v2f32(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt z0.s, p0/m, z0.h ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v2f16_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr s0, [x0] -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x half>, ptr %a %res = fpext <2 x half> %op1 to <2 x float> store <2 x float> %res, ptr %b @@ -150,13 +104,6 @@ define void @fcvt_v4f16_v4f32(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt z0.s, p0/m, z0.h ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v4f16_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x half>, ptr %a %res = fpext <4 x half> %op1 to <4 x float> store <4 x float> %res, ptr %b @@ -174,18 +121,6 @@ define void @fcvt_v8f16_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt z1.s, p0/m, z1.h ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v8f16_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x half>, ptr %a %res = fpext <8 x half> %op1 to <8 x float> store <8 x float> %res, ptr %b @@ -210,22 +145,6 @@ define void @fcvt_v16f16_v16f32(ptr %a, ptr %b) { ; CHECK-NEXT: stp q0, q1, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v16f16_v16f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v3.4h -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %res = fpext <16 x half> %op1 to <16 x float> store <16 x float> %res, ptr %b @@ -243,13 +162,6 @@ define void @fcvt_v1f16_v1f64(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt d0, h0 ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v1f16_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr h0, [x0] -; NONEON-NOSVE-NEXT: fcvt d0, h0 -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <1 x half>, ptr %a %res = fpext <1 x half> %op1 to <1 x double> store <1 x double> %res, ptr %b @@ -264,14 +176,6 @@ define void @fcvt_v2f16_v2f64(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt z0.d, p0/m, z0.h ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v2f16_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr s0, [x0] -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x half>, ptr %a %res = fpext <2 x half> %op1 to <2 x double> store <2 x double> %res, ptr %b @@ -289,19 +193,6 @@ define void @fcvt_v4f16_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt z1.d, p0/m, z1.h ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v4f16_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtl v1.2d, v1.2s -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x half>, ptr %a %res = fpext <4 x half> %op1 to <4 x double> store <4 x double> %res, ptr %b @@ -326,26 +217,6 @@ define void @fcvt_v8f16_v8f64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q0, q1, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v8f16_v8f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-48]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #16] -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtl v1.2d, v1.2s -; NONEON-NOSVE-NEXT: ldr d2, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: fcvtl v2.2d, v2.2s -; NONEON-NOSVE-NEXT: fcvtl v3.2d, v3.2s -; NONEON-NOSVE-NEXT: stp q0, q2, [x1] -; NONEON-NOSVE-NEXT: stp q1, q3, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #48 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x half>, ptr %a %res = fpext <8 x half> %op1 to <8 x double> store <8 x double> %res, ptr %b @@ -387,38 +258,6 @@ define void @fcvt_v16f16_v16f64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q4, q0, [x1, #32] ; CHECK-NEXT: stp q1, q2, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v16f16_v16f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-96]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v3.4h -; NONEON-NOSVE-NEXT: stp q2, q0, [sp, #32] -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtl v2.2d, v2.2s -; NONEON-NOSVE-NEXT: stp q3, q1, [sp, #64] -; NONEON-NOSVE-NEXT: ldr d5, [sp, #56] -; NONEON-NOSVE-NEXT: fcvtl v1.2d, v1.2s -; NONEON-NOSVE-NEXT: ldr d4, [sp, #88] -; NONEON-NOSVE-NEXT: ldr d6, [sp, #72] -; NONEON-NOSVE-NEXT: ldr d7, [sp, #40] -; NONEON-NOSVE-NEXT: fcvtl v5.2d, v5.2s -; NONEON-NOSVE-NEXT: fcvtl v3.2d, v3.2s -; NONEON-NOSVE-NEXT: fcvtl v4.2d, v4.2s -; NONEON-NOSVE-NEXT: stp q0, q5, [x1] -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v7.2s -; NONEON-NOSVE-NEXT: stp q1, q4, [x1, #64] -; NONEON-NOSVE-NEXT: fcvtl v1.2d, v6.2s -; NONEON-NOSVE-NEXT: stp q2, q0, [x1, #32] -; NONEON-NOSVE-NEXT: stp q3, q1, [x1, #96] -; NONEON-NOSVE-NEXT: add sp, sp, #96 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %res = fpext <16 x half> %op1 to <16 x double> store <16 x double> %res, ptr %b @@ -436,13 +275,6 @@ define void @fcvt_v1f32_v1f64(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt d0, s0 ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v1f32_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr s0, [x0] -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <1 x float>, ptr %a %res = fpext <1 x float> %op1 to <1 x double> store <1 x double> %res, ptr %b @@ -457,13 +289,6 @@ define void @fcvt_v2f32_v2f64(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt z0.d, p0/m, z0.s ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v2f32_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x float>, ptr %a %res = fpext <2 x float> %op1 to <2 x double> store <2 x double> %res, ptr %b @@ -481,18 +306,6 @@ define void @fcvt_v4f32_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt z1.d, p0/m, z1.s ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v4f32_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtl v1.2d, v1.2s -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x float>, ptr %a %res = fpext <4 x float> %op1 to <4 x double> store <4 x double> %res, ptr %b @@ -517,22 +330,6 @@ define void @fcvt_v8f32_v8f64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q0, q1, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v8f32_v8f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v1.2d, v1.2s -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtl v2.2d, v2.2s -; NONEON-NOSVE-NEXT: fcvtl v3.2d, v3.2s -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %res = fpext <8 x float> %op1 to <8 x double> store <8 x double> %res, ptr %b @@ -551,13 +348,6 @@ define void @fcvt_v2f32_v2f16(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt z0.h, p0/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v2f32_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: str s0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x float>, ptr %a %res = fptrunc <2 x float> %op1 to <2 x half> store <2 x half> %res, ptr %b @@ -572,13 +362,6 @@ define void @fcvt_v4f32_v4f16(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt z0.h, p0/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v4f32_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x float>, ptr %a %res = fptrunc <4 x float> %op1 to <4 x half> store <4 x half> %res, ptr %b @@ -596,14 +379,6 @@ define void @fcvt_v8f32_v8f16(ptr %a, ptr %b) { ; CHECK-NEXT: st1h { z0.s }, p0, [x1, x8, lsl #1] ; CHECK-NEXT: st1h { z1.s }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v8f32_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %res = fptrunc <8 x float> %op1 to <8 x half> store <8 x half> %res, ptr %b @@ -622,13 +397,6 @@ define void @fcvt_v1f64_v1f16(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt z0.h, p0/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v1f64_v1f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: fcvt h0, d0 -; NONEON-NOSVE-NEXT: str h0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <1 x double>, ptr %a %res = fptrunc <1 x double> %op1 to <1 x half> store <1 x half> %res, ptr %b @@ -643,14 +411,6 @@ define void @fcvt_v2f64_v2f16(ptr %a, ptr %b) { ; CHECK-NEXT: fcvt z0.h, p0/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v2f64_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: fcvtxn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: str s0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x double>, ptr %a %res = fptrunc <2 x double> %op1 to <2 x half> store <2 x half> %res, ptr %b @@ -668,15 +428,6 @@ define void @fcvt_v4f64_v4f16(ptr %a, ptr %b) { ; CHECK-NEXT: st1h { z0.d }, p0, [x1, x8, lsl #1] ; CHECK-NEXT: st1h { z1.d }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v4f64_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtxn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: fcvtxn2 v0.4s, v1.2d -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %res = fptrunc <4 x double> %op1 to <4 x half> store <4 x half> %res, ptr %b @@ -695,13 +446,6 @@ define void @fcvt_v1f64_v1f32(<1 x double> %op1, ptr %b) { ; CHECK-NEXT: fcvt z0.s, p0/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v1f64_v1f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fcvtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: str s0, [x0] -; NONEON-NOSVE-NEXT: ret %res = fptrunc <1 x double> %op1 to <1 x float> store <1 x float> %res, ptr %b ret void @@ -715,12 +459,6 @@ define void @fcvt_v2f64_v2f32(<2 x double> %op1, ptr %b) { ; CHECK-NEXT: fcvt z0.s, p0/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v2f64_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %res = fptrunc <2 x double> %op1 to <2 x float> store <2 x float> %res, ptr %b ret void @@ -737,14 +475,6 @@ define void @fcvt_v4f64_v4f32(ptr %a, ptr %b) { ; CHECK-NEXT: st1w { z0.d }, p0, [x1, x8, lsl #2] ; CHECK-NEXT: st1w { z1.d }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvt_v4f64_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: fcvtn2 v0.4s, v1.2d -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %res = fptrunc <4 x double> %op1 to <4 x float> store <4 x float> %res, ptr %b diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll index 44d7116e5f87..cbe71d715a8f 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -18,18 +17,6 @@ define <4 x half> @fma_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3) ; CHECK-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fmul v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %mul = fmul contract <4 x half> %op1, %op2 %res = fadd contract <4 x half> %mul, %op3 ret <4 x half> %res @@ -45,26 +32,6 @@ define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3) ; CHECK-NEXT: fmad z0.h, p0/m, z1.h, z2.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v4.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fmul v3.4s, v4.4s, v3.4s -; NONEON-NOSVE-NEXT: fmul v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v1.4h, v3.4s -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v2.8h -; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v3.4s -; NONEON-NOSVE-NEXT: fadd v1.4s, v1.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %mul = fmul contract <8 x half> %op1, %op2 %res = fadd contract <8 x half> %mul, %op3 ret <8 x half> %res @@ -82,46 +49,6 @@ define void @fma_v16f16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: fmla z1.h, p0/m, z3.h, z4.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x1] -; NONEON-NOSVE-NEXT: fcvtl v5.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v7.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl v4.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v6.4s, v3.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fcvtl2 v3.4s, v3.8h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v2.8h -; NONEON-NOSVE-NEXT: fmul v4.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: fmul v5.4s, v7.4s, v6.4s -; NONEON-NOSVE-NEXT: fmul v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fmul v2.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: fcvtn v1.4h, v4.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v5.4s -; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v2.4s -; NONEON-NOSVE-NEXT: ldp q0, q2, [x2] -; NONEON-NOSVE-NEXT: fcvtl v4.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v5.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v6.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl v7.4s, v3.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v2.8h -; NONEON-NOSVE-NEXT: fcvtl2 v3.4s, v3.8h -; NONEON-NOSVE-NEXT: fadd v4.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: fadd v5.4s, v7.4s, v6.4s -; NONEON-NOSVE-NEXT: fadd v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fadd v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtn v1.4h, v4.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v5.4s -; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v2.4s -; NONEON-NOSVE-NEXT: stp q1, q3, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %op3 = load <16 x half>, ptr %c @@ -141,12 +68,6 @@ define <2 x float> @fma_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %o ; CHECK-NEXT: fmad z0.s, p0/m, z1.s, z2.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmla v2.2s, v1.2s, v0.2s -; NONEON-NOSVE-NEXT: fmov d0, d2 -; NONEON-NOSVE-NEXT: ret %mul = fmul contract <2 x float> %op1, %op2 %res = fadd contract <2 x float> %mul, %op3 ret <2 x float> %res @@ -162,12 +83,6 @@ define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %o ; CHECK-NEXT: fmad z0.s, p0/m, z1.s, z2.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmla v2.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %mul = fmul contract <4 x float> %op1, %op2 %res = fadd contract <4 x float> %mul, %op3 ret <4 x float> %res @@ -185,16 +100,6 @@ define void @fma_v8f32(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: fmla z1.s, p0/m, z3.s, z4.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q4, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q5, [x2] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: fmla v1.4s, v0.4s, v2.4s -; NONEON-NOSVE-NEXT: fmla v5.4s, v4.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q1, q5, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %op3 = load <8 x float>, ptr %c @@ -209,11 +114,6 @@ define <1 x double> @fma_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x double ; CHECK: // %bb.0: ; CHECK-NEXT: fmadd d0, d0, d1, d2 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmadd d0, d0, d1, d2 -; NONEON-NOSVE-NEXT: ret %mul = fmul contract <1 x double> %op1, %op2 %res = fadd contract <1 x double> %mul, %op3 ret <1 x double> %res @@ -229,12 +129,6 @@ define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double ; CHECK-NEXT: fmad z0.d, p0/m, z1.d, z2.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmla v2.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %mul = fmul contract <2 x double> %op1, %op2 %res = fadd contract <2 x double> %mul, %op3 ret <2 x double> %res @@ -252,16 +146,6 @@ define void @fma_v4f64(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: fmla z1.d, p0/m, z3.d, z4.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fma_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q4, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q5, [x2] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: fmla v1.2d, v0.2d, v2.2d -; NONEON-NOSVE-NEXT: fmla v5.2d, v4.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q1, q5, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %op3 = load <4 x double>, ptr %c diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll index bc7659c06ad0..94a74763aa0e 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -18,38 +17,6 @@ define <4 x half> @fmaxnm_v4f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxnm_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: mov h4, v1.h[2] -; NONEON-NOSVE-NEXT: mov h5, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h1 -; NONEON-NOSVE-NEXT: fcvt s7, h0 -; NONEON-NOSVE-NEXT: mov h1, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmaxnm s2, s3, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fmaxnm s5, s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: fmaxnm s3, s4, s3 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt h0, s5 -; NONEON-NOSVE-NEXT: fcvt s4, h6 -; NONEON-NOSVE-NEXT: mov v0.h[1], v2.h[0] -; NONEON-NOSVE-NEXT: fcvt h2, s3 -; NONEON-NOSVE-NEXT: fmaxnm s1, s4, s1 -; NONEON-NOSVE-NEXT: mov v0.h[2], v2.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: mov v0.h[3], v1.h[0] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.maxnum.v4f16(<4 x half> %op1, <4 x half> %op2) ret <4 x half> %res } @@ -63,64 +30,6 @@ define <8 x half> @fmaxnm_v8f16(<8 x half> %op1, <8 x half> %op2) { ; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxnm_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: mov h6, v1.h[2] -; NONEON-NOSVE-NEXT: mov h7, v0.h[2] -; NONEON-NOSVE-NEXT: mov h16, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fmaxnm s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: fmaxnm s3, s3, s2 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s4 -; NONEON-NOSVE-NEXT: fmaxnm s4, s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[4] -; NONEON-NOSVE-NEXT: mov h7, v0.h[4] -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fmaxnm s5, s5, s16 -; NONEON-NOSVE-NEXT: mov h16, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: mov v2.h[1], v3.h[0] -; NONEON-NOSVE-NEXT: fcvt s3, h6 -; NONEON-NOSVE-NEXT: fcvt s6, h7 -; NONEON-NOSVE-NEXT: mov h7, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt h5, s5 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: mov v2.h[2], v4.h[0] -; NONEON-NOSVE-NEXT: mov h4, v1.h[6] -; NONEON-NOSVE-NEXT: fmaxnm s3, s6, s3 -; NONEON-NOSVE-NEXT: mov h6, v0.h[6] -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v2.h[3], v5.h[0] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h6 -; NONEON-NOSVE-NEXT: fmaxnm s6, s16, s7 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v2.h[4], v3.h[0] -; NONEON-NOSVE-NEXT: fmaxnm s4, s5, s4 -; NONEON-NOSVE-NEXT: fcvt h3, s6 -; NONEON-NOSVE-NEXT: fmaxnm s0, s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[5], v3.h[0] -; NONEON-NOSVE-NEXT: fcvt h3, s4 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: mov v2.h[6], v3.h[0] -; NONEON-NOSVE-NEXT: mov v2.h[7], v0.h[0] -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %op1, <8 x half> %op2) ret <8 x half> %res } @@ -136,119 +45,6 @@ define void @fmaxnm_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: fmaxnm z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxnm_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: mov h7, v0.h[1] -; NONEON-NOSVE-NEXT: mov h16, v0.h[2] -; NONEON-NOSVE-NEXT: mov h18, v2.h[1] -; NONEON-NOSVE-NEXT: mov h5, v1.h[1] -; NONEON-NOSVE-NEXT: mov h6, v1.h[2] -; NONEON-NOSVE-NEXT: mov h17, v3.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s19, h0 -; NONEON-NOSVE-NEXT: fcvt s20, h3 -; NONEON-NOSVE-NEXT: fcvt s21, h2 -; NONEON-NOSVE-NEXT: mov h22, v3.h[2] -; NONEON-NOSVE-NEXT: mov h23, v2.h[2] -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: fcvt s18, h18 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: fmaxnm s4, s19, s4 -; NONEON-NOSVE-NEXT: mov h19, v0.h[3] -; NONEON-NOSVE-NEXT: mov h24, v3.h[3] -; NONEON-NOSVE-NEXT: fmaxnm s20, s21, s20 -; NONEON-NOSVE-NEXT: fcvt s21, h22 -; NONEON-NOSVE-NEXT: fcvt s22, h23 -; NONEON-NOSVE-NEXT: mov h23, v2.h[3] -; NONEON-NOSVE-NEXT: mov h25, v2.h[6] -; NONEON-NOSVE-NEXT: fmaxnm s5, s7, s5 -; NONEON-NOSVE-NEXT: mov h7, v1.h[3] -; NONEON-NOSVE-NEXT: fmaxnm s6, s16, s6 -; NONEON-NOSVE-NEXT: fmaxnm s16, s18, s17 -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s18, h19 -; NONEON-NOSVE-NEXT: fcvt s19, h24 -; NONEON-NOSVE-NEXT: mov h24, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt h17, s5 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt h5, s20 -; NONEON-NOSVE-NEXT: fmaxnm s20, s22, s21 -; NONEON-NOSVE-NEXT: fcvt h16, s16 -; NONEON-NOSVE-NEXT: fcvt s21, h23 -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: mov h22, v0.h[4] -; NONEON-NOSVE-NEXT: mov h23, v2.h[4] -; NONEON-NOSVE-NEXT: mov v4.h[1], v17.h[0] -; NONEON-NOSVE-NEXT: mov h17, v1.h[4] -; NONEON-NOSVE-NEXT: fmaxnm s7, s18, s7 -; NONEON-NOSVE-NEXT: mov h18, v3.h[4] -; NONEON-NOSVE-NEXT: mov v5.h[1], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h16, s20 -; NONEON-NOSVE-NEXT: fmaxnm s19, s21, s19 -; NONEON-NOSVE-NEXT: fcvt s20, h23 -; NONEON-NOSVE-NEXT: mov h21, v1.h[5] -; NONEON-NOSVE-NEXT: mov h23, v2.h[5] -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: mov v4.h[2], v6.h[0] -; NONEON-NOSVE-NEXT: fcvt s6, h17 -; NONEON-NOSVE-NEXT: fcvt s17, h22 -; NONEON-NOSVE-NEXT: fcvt h7, s7 -; NONEON-NOSVE-NEXT: fcvt s18, h18 -; NONEON-NOSVE-NEXT: mov h22, v3.h[5] -; NONEON-NOSVE-NEXT: mov v5.h[2], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h16, s19 -; NONEON-NOSVE-NEXT: mov h19, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmaxnm s6, s17, s6 -; NONEON-NOSVE-NEXT: mov h17, v1.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fmaxnm s18, s20, s18 -; NONEON-NOSVE-NEXT: mov h20, v3.h[6] -; NONEON-NOSVE-NEXT: mov v4.h[3], v7.h[0] -; NONEON-NOSVE-NEXT: fcvt s7, h22 -; NONEON-NOSVE-NEXT: fcvt s22, h23 -; NONEON-NOSVE-NEXT: mov v5.h[3], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt s16, h21 -; NONEON-NOSVE-NEXT: fcvt s21, h24 -; NONEON-NOSVE-NEXT: fcvt s19, h19 -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: fcvt s23, h25 -; NONEON-NOSVE-NEXT: fcvt h18, s18 -; NONEON-NOSVE-NEXT: fcvt s20, h20 -; NONEON-NOSVE-NEXT: mov h3, v3.h[7] -; NONEON-NOSVE-NEXT: fmaxnm s7, s22, s7 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fmaxnm s16, s21, s16 -; NONEON-NOSVE-NEXT: mov v4.h[4], v6.h[0] -; NONEON-NOSVE-NEXT: fmaxnm s6, s19, s17 -; NONEON-NOSVE-NEXT: mov v5.h[4], v18.h[0] -; NONEON-NOSVE-NEXT: fmaxnm s17, s23, s20 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt h7, s7 -; NONEON-NOSVE-NEXT: fmaxnm s0, s0, s1 -; NONEON-NOSVE-NEXT: fcvt h16, s16 -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: fmaxnm s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h3, s17 -; NONEON-NOSVE-NEXT: mov v5.h[5], v7.h[0] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: mov v4.h[5], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s2 -; NONEON-NOSVE-NEXT: mov v5.h[6], v3.h[0] -; NONEON-NOSVE-NEXT: mov v4.h[6], v6.h[0] -; NONEON-NOSVE-NEXT: mov v5.h[7], v1.h[0] -; NONEON-NOSVE-NEXT: mov v4.h[7], v0.h[0] -; NONEON-NOSVE-NEXT: stp q5, q4, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %res = call <16 x half> @llvm.maxnum.v16f16(<16 x half> %op1, <16 x half> %op2) @@ -265,11 +61,6 @@ define <2 x float> @fmaxnm_v2f32(<2 x float> %op1, <2 x float> %op2) { ; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxnm_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmaxnm v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %op1, <2 x float> %op2) ret <2 x float> %res } @@ -283,11 +74,6 @@ define <4 x float> @fmaxnm_v4f32(<4 x float> %op1, <4 x float> %op2) { ; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxnm_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmaxnm v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %op1, <4 x float> %op2) ret <4 x float> %res } @@ -303,15 +89,6 @@ define void @fmaxnm_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: fmaxnm z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxnm_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fmaxnm v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fmaxnm v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %res = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %op1, <8 x float> %op2) @@ -324,11 +101,6 @@ define <1 x double> @fmaxnm_v1f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK: // %bb.0: ; CHECK-NEXT: fmaxnm d0, d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxnm_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmaxnm d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %res = call <1 x double> @llvm.maxnum.v1f64(<1 x double> %op1, <1 x double> %op2) ret <1 x double> %res } @@ -342,11 +114,6 @@ define <2 x double> @fmaxnm_v2f64(<2 x double> %op1, <2 x double> %op2) { ; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxnm_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmaxnm v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %op1, <2 x double> %op2) ret <2 x double> %res } @@ -362,15 +129,6 @@ define void @fmaxnm_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fmaxnm z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxnm_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fmaxnm v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fmaxnm v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %res = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %op1, <4 x double> %op2) @@ -391,38 +149,6 @@ define <4 x half> @fminnm_v4f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminnm_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: mov h4, v1.h[2] -; NONEON-NOSVE-NEXT: mov h5, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h1 -; NONEON-NOSVE-NEXT: fcvt s7, h0 -; NONEON-NOSVE-NEXT: mov h1, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fminnm s2, s3, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fminnm s5, s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: fminnm s3, s4, s3 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt h0, s5 -; NONEON-NOSVE-NEXT: fcvt s4, h6 -; NONEON-NOSVE-NEXT: mov v0.h[1], v2.h[0] -; NONEON-NOSVE-NEXT: fcvt h2, s3 -; NONEON-NOSVE-NEXT: fminnm s1, s4, s1 -; NONEON-NOSVE-NEXT: mov v0.h[2], v2.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: mov v0.h[3], v1.h[0] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.minnum.v4f16(<4 x half> %op1, <4 x half> %op2) ret <4 x half> %res } @@ -436,64 +162,6 @@ define <8 x half> @fminnm_v8f16(<8 x half> %op1, <8 x half> %op2) { ; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminnm_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: mov h6, v1.h[2] -; NONEON-NOSVE-NEXT: mov h7, v0.h[2] -; NONEON-NOSVE-NEXT: mov h16, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fminnm s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: fminnm s3, s3, s2 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s4 -; NONEON-NOSVE-NEXT: fminnm s4, s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[4] -; NONEON-NOSVE-NEXT: mov h7, v0.h[4] -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fminnm s5, s5, s16 -; NONEON-NOSVE-NEXT: mov h16, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: mov v2.h[1], v3.h[0] -; NONEON-NOSVE-NEXT: fcvt s3, h6 -; NONEON-NOSVE-NEXT: fcvt s6, h7 -; NONEON-NOSVE-NEXT: mov h7, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt h5, s5 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: mov v2.h[2], v4.h[0] -; NONEON-NOSVE-NEXT: mov h4, v1.h[6] -; NONEON-NOSVE-NEXT: fminnm s3, s6, s3 -; NONEON-NOSVE-NEXT: mov h6, v0.h[6] -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v2.h[3], v5.h[0] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h6 -; NONEON-NOSVE-NEXT: fminnm s6, s16, s7 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v2.h[4], v3.h[0] -; NONEON-NOSVE-NEXT: fminnm s4, s5, s4 -; NONEON-NOSVE-NEXT: fcvt h3, s6 -; NONEON-NOSVE-NEXT: fminnm s0, s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[5], v3.h[0] -; NONEON-NOSVE-NEXT: fcvt h3, s4 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: mov v2.h[6], v3.h[0] -; NONEON-NOSVE-NEXT: mov v2.h[7], v0.h[0] -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.minnum.v8f16(<8 x half> %op1, <8 x half> %op2) ret <8 x half> %res } @@ -509,119 +177,6 @@ define void @fminnm_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: fminnm z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminnm_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: mov h7, v0.h[1] -; NONEON-NOSVE-NEXT: mov h16, v0.h[2] -; NONEON-NOSVE-NEXT: mov h18, v2.h[1] -; NONEON-NOSVE-NEXT: mov h5, v1.h[1] -; NONEON-NOSVE-NEXT: mov h6, v1.h[2] -; NONEON-NOSVE-NEXT: mov h17, v3.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s19, h0 -; NONEON-NOSVE-NEXT: fcvt s20, h3 -; NONEON-NOSVE-NEXT: fcvt s21, h2 -; NONEON-NOSVE-NEXT: mov h22, v3.h[2] -; NONEON-NOSVE-NEXT: mov h23, v2.h[2] -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: fcvt s18, h18 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: fminnm s4, s19, s4 -; NONEON-NOSVE-NEXT: mov h19, v0.h[3] -; NONEON-NOSVE-NEXT: mov h24, v3.h[3] -; NONEON-NOSVE-NEXT: fminnm s20, s21, s20 -; NONEON-NOSVE-NEXT: fcvt s21, h22 -; NONEON-NOSVE-NEXT: fcvt s22, h23 -; NONEON-NOSVE-NEXT: mov h23, v2.h[3] -; NONEON-NOSVE-NEXT: mov h25, v2.h[6] -; NONEON-NOSVE-NEXT: fminnm s5, s7, s5 -; NONEON-NOSVE-NEXT: mov h7, v1.h[3] -; NONEON-NOSVE-NEXT: fminnm s6, s16, s6 -; NONEON-NOSVE-NEXT: fminnm s16, s18, s17 -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s18, h19 -; NONEON-NOSVE-NEXT: fcvt s19, h24 -; NONEON-NOSVE-NEXT: mov h24, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt h17, s5 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt h5, s20 -; NONEON-NOSVE-NEXT: fminnm s20, s22, s21 -; NONEON-NOSVE-NEXT: fcvt h16, s16 -; NONEON-NOSVE-NEXT: fcvt s21, h23 -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: mov h22, v0.h[4] -; NONEON-NOSVE-NEXT: mov h23, v2.h[4] -; NONEON-NOSVE-NEXT: mov v4.h[1], v17.h[0] -; NONEON-NOSVE-NEXT: mov h17, v1.h[4] -; NONEON-NOSVE-NEXT: fminnm s7, s18, s7 -; NONEON-NOSVE-NEXT: mov h18, v3.h[4] -; NONEON-NOSVE-NEXT: mov v5.h[1], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h16, s20 -; NONEON-NOSVE-NEXT: fminnm s19, s21, s19 -; NONEON-NOSVE-NEXT: fcvt s20, h23 -; NONEON-NOSVE-NEXT: mov h21, v1.h[5] -; NONEON-NOSVE-NEXT: mov h23, v2.h[5] -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: mov v4.h[2], v6.h[0] -; NONEON-NOSVE-NEXT: fcvt s6, h17 -; NONEON-NOSVE-NEXT: fcvt s17, h22 -; NONEON-NOSVE-NEXT: fcvt h7, s7 -; NONEON-NOSVE-NEXT: fcvt s18, h18 -; NONEON-NOSVE-NEXT: mov h22, v3.h[5] -; NONEON-NOSVE-NEXT: mov v5.h[2], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h16, s19 -; NONEON-NOSVE-NEXT: mov h19, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fminnm s6, s17, s6 -; NONEON-NOSVE-NEXT: mov h17, v1.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fminnm s18, s20, s18 -; NONEON-NOSVE-NEXT: mov h20, v3.h[6] -; NONEON-NOSVE-NEXT: mov v4.h[3], v7.h[0] -; NONEON-NOSVE-NEXT: fcvt s7, h22 -; NONEON-NOSVE-NEXT: fcvt s22, h23 -; NONEON-NOSVE-NEXT: mov v5.h[3], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt s16, h21 -; NONEON-NOSVE-NEXT: fcvt s21, h24 -; NONEON-NOSVE-NEXT: fcvt s19, h19 -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: fcvt s23, h25 -; NONEON-NOSVE-NEXT: fcvt h18, s18 -; NONEON-NOSVE-NEXT: fcvt s20, h20 -; NONEON-NOSVE-NEXT: mov h3, v3.h[7] -; NONEON-NOSVE-NEXT: fminnm s7, s22, s7 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fminnm s16, s21, s16 -; NONEON-NOSVE-NEXT: mov v4.h[4], v6.h[0] -; NONEON-NOSVE-NEXT: fminnm s6, s19, s17 -; NONEON-NOSVE-NEXT: mov v5.h[4], v18.h[0] -; NONEON-NOSVE-NEXT: fminnm s17, s23, s20 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt h7, s7 -; NONEON-NOSVE-NEXT: fminnm s0, s0, s1 -; NONEON-NOSVE-NEXT: fcvt h16, s16 -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: fminnm s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h3, s17 -; NONEON-NOSVE-NEXT: mov v5.h[5], v7.h[0] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: mov v4.h[5], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s2 -; NONEON-NOSVE-NEXT: mov v5.h[6], v3.h[0] -; NONEON-NOSVE-NEXT: mov v4.h[6], v6.h[0] -; NONEON-NOSVE-NEXT: mov v5.h[7], v1.h[0] -; NONEON-NOSVE-NEXT: mov v4.h[7], v0.h[0] -; NONEON-NOSVE-NEXT: stp q5, q4, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %res = call <16 x half> @llvm.minnum.v16f16(<16 x half> %op1, <16 x half> %op2) @@ -638,11 +193,6 @@ define <2 x float> @fminnm_v2f32(<2 x float> %op1, <2 x float> %op2) { ; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminnm_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fminnm v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.minnum.v2f32(<2 x float> %op1, <2 x float> %op2) ret <2 x float> %res } @@ -656,11 +206,6 @@ define <4 x float> @fminnm_v4f32(<4 x float> %op1, <4 x float> %op2) { ; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminnm_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fminnm v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.minnum.v4f32(<4 x float> %op1, <4 x float> %op2) ret <4 x float> %res } @@ -676,15 +221,6 @@ define void @fminnm_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: fminnm z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminnm_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fminnm v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fminnm v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %res = call <8 x float> @llvm.minnum.v8f32(<8 x float> %op1, <8 x float> %op2) @@ -697,11 +233,6 @@ define <1 x double> @fminnm_v1f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK: // %bb.0: ; CHECK-NEXT: fminnm d0, d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminnm_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fminnm d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %res = call <1 x double> @llvm.minnum.v1f64(<1 x double> %op1, <1 x double> %op2) ret <1 x double> %res } @@ -715,11 +246,6 @@ define <2 x double> @fminnm_v2f64(<2 x double> %op1, <2 x double> %op2) { ; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminnm_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fminnm v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.minnum.v2f64(<2 x double> %op1, <2 x double> %op2) ret <2 x double> %res } @@ -735,15 +261,6 @@ define void @fminnm_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fminnm z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminnm_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fminnm v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fminnm v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %res = call <4 x double> @llvm.minnum.v4f64(<4 x double> %op1, <4 x double> %op2) @@ -764,38 +281,6 @@ define <4 x half> @fmax_v4f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmax_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: mov h4, v1.h[2] -; NONEON-NOSVE-NEXT: mov h5, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h1 -; NONEON-NOSVE-NEXT: fcvt s7, h0 -; NONEON-NOSVE-NEXT: mov h1, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmax s2, s3, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fmax s5, s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: fmax s3, s4, s3 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt h0, s5 -; NONEON-NOSVE-NEXT: fcvt s4, h6 -; NONEON-NOSVE-NEXT: mov v0.h[1], v2.h[0] -; NONEON-NOSVE-NEXT: fcvt h2, s3 -; NONEON-NOSVE-NEXT: fmax s1, s4, s1 -; NONEON-NOSVE-NEXT: mov v0.h[2], v2.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: mov v0.h[3], v1.h[0] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.maximum.v4f16(<4 x half> %op1, <4 x half> %op2) ret <4 x half> %res } @@ -809,64 +294,6 @@ define <8 x half> @fmax_v8f16(<8 x half> %op1, <8 x half> %op2) { ; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmax_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: mov h6, v1.h[2] -; NONEON-NOSVE-NEXT: mov h7, v0.h[2] -; NONEON-NOSVE-NEXT: mov h16, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fmax s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: fmax s3, s3, s2 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s4 -; NONEON-NOSVE-NEXT: fmax s4, s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[4] -; NONEON-NOSVE-NEXT: mov h7, v0.h[4] -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fmax s5, s5, s16 -; NONEON-NOSVE-NEXT: mov h16, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: mov v2.h[1], v3.h[0] -; NONEON-NOSVE-NEXT: fcvt s3, h6 -; NONEON-NOSVE-NEXT: fcvt s6, h7 -; NONEON-NOSVE-NEXT: mov h7, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt h5, s5 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: mov v2.h[2], v4.h[0] -; NONEON-NOSVE-NEXT: mov h4, v1.h[6] -; NONEON-NOSVE-NEXT: fmax s3, s6, s3 -; NONEON-NOSVE-NEXT: mov h6, v0.h[6] -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v2.h[3], v5.h[0] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h6 -; NONEON-NOSVE-NEXT: fmax s6, s16, s7 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v2.h[4], v3.h[0] -; NONEON-NOSVE-NEXT: fmax s4, s5, s4 -; NONEON-NOSVE-NEXT: fcvt h3, s6 -; NONEON-NOSVE-NEXT: fmax s0, s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[5], v3.h[0] -; NONEON-NOSVE-NEXT: fcvt h3, s4 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: mov v2.h[6], v3.h[0] -; NONEON-NOSVE-NEXT: mov v2.h[7], v0.h[0] -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.maximum.v8f16(<8 x half> %op1, <8 x half> %op2) ret <8 x half> %res } @@ -882,119 +309,6 @@ define void @fmax_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: fmax z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmax_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: mov h7, v0.h[1] -; NONEON-NOSVE-NEXT: mov h16, v0.h[2] -; NONEON-NOSVE-NEXT: mov h18, v2.h[1] -; NONEON-NOSVE-NEXT: mov h5, v1.h[1] -; NONEON-NOSVE-NEXT: mov h6, v1.h[2] -; NONEON-NOSVE-NEXT: mov h17, v3.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s19, h0 -; NONEON-NOSVE-NEXT: fcvt s20, h3 -; NONEON-NOSVE-NEXT: fcvt s21, h2 -; NONEON-NOSVE-NEXT: mov h22, v3.h[2] -; NONEON-NOSVE-NEXT: mov h23, v2.h[2] -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: fcvt s18, h18 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: fmax s4, s19, s4 -; NONEON-NOSVE-NEXT: mov h19, v0.h[3] -; NONEON-NOSVE-NEXT: mov h24, v3.h[3] -; NONEON-NOSVE-NEXT: fmax s20, s21, s20 -; NONEON-NOSVE-NEXT: fcvt s21, h22 -; NONEON-NOSVE-NEXT: fcvt s22, h23 -; NONEON-NOSVE-NEXT: mov h23, v2.h[3] -; NONEON-NOSVE-NEXT: mov h25, v2.h[6] -; NONEON-NOSVE-NEXT: fmax s5, s7, s5 -; NONEON-NOSVE-NEXT: mov h7, v1.h[3] -; NONEON-NOSVE-NEXT: fmax s6, s16, s6 -; NONEON-NOSVE-NEXT: fmax s16, s18, s17 -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s18, h19 -; NONEON-NOSVE-NEXT: fcvt s19, h24 -; NONEON-NOSVE-NEXT: mov h24, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt h17, s5 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt h5, s20 -; NONEON-NOSVE-NEXT: fmax s20, s22, s21 -; NONEON-NOSVE-NEXT: fcvt h16, s16 -; NONEON-NOSVE-NEXT: fcvt s21, h23 -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: mov h22, v0.h[4] -; NONEON-NOSVE-NEXT: mov h23, v2.h[4] -; NONEON-NOSVE-NEXT: mov v4.h[1], v17.h[0] -; NONEON-NOSVE-NEXT: mov h17, v1.h[4] -; NONEON-NOSVE-NEXT: fmax s7, s18, s7 -; NONEON-NOSVE-NEXT: mov h18, v3.h[4] -; NONEON-NOSVE-NEXT: mov v5.h[1], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h16, s20 -; NONEON-NOSVE-NEXT: fmax s19, s21, s19 -; NONEON-NOSVE-NEXT: fcvt s20, h23 -; NONEON-NOSVE-NEXT: mov h21, v1.h[5] -; NONEON-NOSVE-NEXT: mov h23, v2.h[5] -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: mov v4.h[2], v6.h[0] -; NONEON-NOSVE-NEXT: fcvt s6, h17 -; NONEON-NOSVE-NEXT: fcvt s17, h22 -; NONEON-NOSVE-NEXT: fcvt h7, s7 -; NONEON-NOSVE-NEXT: fcvt s18, h18 -; NONEON-NOSVE-NEXT: mov h22, v3.h[5] -; NONEON-NOSVE-NEXT: mov v5.h[2], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h16, s19 -; NONEON-NOSVE-NEXT: mov h19, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmax s6, s17, s6 -; NONEON-NOSVE-NEXT: mov h17, v1.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fmax s18, s20, s18 -; NONEON-NOSVE-NEXT: mov h20, v3.h[6] -; NONEON-NOSVE-NEXT: mov v4.h[3], v7.h[0] -; NONEON-NOSVE-NEXT: fcvt s7, h22 -; NONEON-NOSVE-NEXT: fcvt s22, h23 -; NONEON-NOSVE-NEXT: mov v5.h[3], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt s16, h21 -; NONEON-NOSVE-NEXT: fcvt s21, h24 -; NONEON-NOSVE-NEXT: fcvt s19, h19 -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: fcvt s23, h25 -; NONEON-NOSVE-NEXT: fcvt h18, s18 -; NONEON-NOSVE-NEXT: fcvt s20, h20 -; NONEON-NOSVE-NEXT: mov h3, v3.h[7] -; NONEON-NOSVE-NEXT: fmax s7, s22, s7 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fmax s16, s21, s16 -; NONEON-NOSVE-NEXT: mov v4.h[4], v6.h[0] -; NONEON-NOSVE-NEXT: fmax s6, s19, s17 -; NONEON-NOSVE-NEXT: mov v5.h[4], v18.h[0] -; NONEON-NOSVE-NEXT: fmax s17, s23, s20 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt h7, s7 -; NONEON-NOSVE-NEXT: fmax s0, s0, s1 -; NONEON-NOSVE-NEXT: fcvt h16, s16 -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: fmax s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h3, s17 -; NONEON-NOSVE-NEXT: mov v5.h[5], v7.h[0] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: mov v4.h[5], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s2 -; NONEON-NOSVE-NEXT: mov v5.h[6], v3.h[0] -; NONEON-NOSVE-NEXT: mov v4.h[6], v6.h[0] -; NONEON-NOSVE-NEXT: mov v5.h[7], v1.h[0] -; NONEON-NOSVE-NEXT: mov v4.h[7], v0.h[0] -; NONEON-NOSVE-NEXT: stp q5, q4, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %res = call <16 x half> @llvm.maximum.v16f16(<16 x half> %op1, <16 x half> %op2) @@ -1011,11 +325,6 @@ define <2 x float> @fmax_v2f32(<2 x float> %op1, <2 x float> %op2) { ; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmax_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmax v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.maximum.v2f32(<2 x float> %op1, <2 x float> %op2) ret <2 x float> %res } @@ -1029,11 +338,6 @@ define <4 x float> @fmax_v4f32(<4 x float> %op1, <4 x float> %op2) { ; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmax_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmax v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.maximum.v4f32(<4 x float> %op1, <4 x float> %op2) ret <4 x float> %res } @@ -1049,15 +353,6 @@ define void @fmax_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: fmax z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmax_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fmax v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fmax v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %res = call <8 x float> @llvm.maximum.v8f32(<8 x float> %op1, <8 x float> %op2) @@ -1070,11 +365,6 @@ define <1 x double> @fmax_v1f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK: // %bb.0: ; CHECK-NEXT: fmax d0, d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmax_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmax d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %res = call <1 x double> @llvm.maximum.v1f64(<1 x double> %op1, <1 x double> %op2) ret <1 x double> %res } @@ -1088,11 +378,6 @@ define <2 x double> @fmax_v2f64(<2 x double> %op1, <2 x double> %op2) { ; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmax_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmax v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.maximum.v2f64(<2 x double> %op1, <2 x double> %op2) ret <2 x double> %res } @@ -1108,15 +393,6 @@ define void @fmax_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fmax z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmax_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fmax v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fmax v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %res = call <4 x double> @llvm.maximum.v4f64(<4 x double> %op1, <4 x double> %op2) @@ -1137,38 +413,6 @@ define <4 x half> @fmin_v4f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmin_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: mov h4, v1.h[2] -; NONEON-NOSVE-NEXT: mov h5, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h1 -; NONEON-NOSVE-NEXT: fcvt s7, h0 -; NONEON-NOSVE-NEXT: mov h1, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmin s2, s3, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h4 -; NONEON-NOSVE-NEXT: fcvt s4, h5 -; NONEON-NOSVE-NEXT: fmin s5, s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v0.h[3] -; NONEON-NOSVE-NEXT: fmin s3, s4, s3 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt h0, s5 -; NONEON-NOSVE-NEXT: fcvt s4, h6 -; NONEON-NOSVE-NEXT: mov v0.h[1], v2.h[0] -; NONEON-NOSVE-NEXT: fcvt h2, s3 -; NONEON-NOSVE-NEXT: fmin s1, s4, s1 -; NONEON-NOSVE-NEXT: mov v0.h[2], v2.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: mov v0.h[3], v1.h[0] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.minimum.v4f16(<4 x half> %op1, <4 x half> %op2) ret <4 x half> %res } @@ -1182,64 +426,6 @@ define <8 x half> @fmin_v8f16(<8 x half> %op1, <8 x half> %op2) { ; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmin_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: mov h6, v1.h[2] -; NONEON-NOSVE-NEXT: mov h7, v0.h[2] -; NONEON-NOSVE-NEXT: mov h16, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fmin s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: fmin s3, s3, s2 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s4 -; NONEON-NOSVE-NEXT: fmin s4, s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[4] -; NONEON-NOSVE-NEXT: mov h7, v0.h[4] -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fmin s5, s5, s16 -; NONEON-NOSVE-NEXT: mov h16, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: mov v2.h[1], v3.h[0] -; NONEON-NOSVE-NEXT: fcvt s3, h6 -; NONEON-NOSVE-NEXT: fcvt s6, h7 -; NONEON-NOSVE-NEXT: mov h7, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt h5, s5 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: mov v2.h[2], v4.h[0] -; NONEON-NOSVE-NEXT: mov h4, v1.h[6] -; NONEON-NOSVE-NEXT: fmin s3, s6, s3 -; NONEON-NOSVE-NEXT: mov h6, v0.h[6] -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: mov v2.h[3], v5.h[0] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h6 -; NONEON-NOSVE-NEXT: fmin s6, s16, s7 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov v2.h[4], v3.h[0] -; NONEON-NOSVE-NEXT: fmin s4, s5, s4 -; NONEON-NOSVE-NEXT: fcvt h3, s6 -; NONEON-NOSVE-NEXT: fmin s0, s0, s1 -; NONEON-NOSVE-NEXT: mov v2.h[5], v3.h[0] -; NONEON-NOSVE-NEXT: fcvt h3, s4 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: mov v2.h[6], v3.h[0] -; NONEON-NOSVE-NEXT: mov v2.h[7], v0.h[0] -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.minimum.v8f16(<8 x half> %op1, <8 x half> %op2) ret <8 x half> %res } @@ -1255,119 +441,6 @@ define void @fmin_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: fmin z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmin_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: mov h7, v0.h[1] -; NONEON-NOSVE-NEXT: mov h16, v0.h[2] -; NONEON-NOSVE-NEXT: mov h18, v2.h[1] -; NONEON-NOSVE-NEXT: mov h5, v1.h[1] -; NONEON-NOSVE-NEXT: mov h6, v1.h[2] -; NONEON-NOSVE-NEXT: mov h17, v3.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s19, h0 -; NONEON-NOSVE-NEXT: fcvt s20, h3 -; NONEON-NOSVE-NEXT: fcvt s21, h2 -; NONEON-NOSVE-NEXT: mov h22, v3.h[2] -; NONEON-NOSVE-NEXT: mov h23, v2.h[2] -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: fcvt s18, h18 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: fmin s4, s19, s4 -; NONEON-NOSVE-NEXT: mov h19, v0.h[3] -; NONEON-NOSVE-NEXT: mov h24, v3.h[3] -; NONEON-NOSVE-NEXT: fmin s20, s21, s20 -; NONEON-NOSVE-NEXT: fcvt s21, h22 -; NONEON-NOSVE-NEXT: fcvt s22, h23 -; NONEON-NOSVE-NEXT: mov h23, v2.h[3] -; NONEON-NOSVE-NEXT: mov h25, v2.h[6] -; NONEON-NOSVE-NEXT: fmin s5, s7, s5 -; NONEON-NOSVE-NEXT: mov h7, v1.h[3] -; NONEON-NOSVE-NEXT: fmin s6, s16, s6 -; NONEON-NOSVE-NEXT: fmin s16, s18, s17 -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s18, h19 -; NONEON-NOSVE-NEXT: fcvt s19, h24 -; NONEON-NOSVE-NEXT: mov h24, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt h17, s5 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcvt h5, s20 -; NONEON-NOSVE-NEXT: fmin s20, s22, s21 -; NONEON-NOSVE-NEXT: fcvt h16, s16 -; NONEON-NOSVE-NEXT: fcvt s21, h23 -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: mov h22, v0.h[4] -; NONEON-NOSVE-NEXT: mov h23, v2.h[4] -; NONEON-NOSVE-NEXT: mov v4.h[1], v17.h[0] -; NONEON-NOSVE-NEXT: mov h17, v1.h[4] -; NONEON-NOSVE-NEXT: fmin s7, s18, s7 -; NONEON-NOSVE-NEXT: mov h18, v3.h[4] -; NONEON-NOSVE-NEXT: mov v5.h[1], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h16, s20 -; NONEON-NOSVE-NEXT: fmin s19, s21, s19 -; NONEON-NOSVE-NEXT: fcvt s20, h23 -; NONEON-NOSVE-NEXT: mov h21, v1.h[5] -; NONEON-NOSVE-NEXT: mov h23, v2.h[5] -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: mov v4.h[2], v6.h[0] -; NONEON-NOSVE-NEXT: fcvt s6, h17 -; NONEON-NOSVE-NEXT: fcvt s17, h22 -; NONEON-NOSVE-NEXT: fcvt h7, s7 -; NONEON-NOSVE-NEXT: fcvt s18, h18 -; NONEON-NOSVE-NEXT: mov h22, v3.h[5] -; NONEON-NOSVE-NEXT: mov v5.h[2], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h16, s19 -; NONEON-NOSVE-NEXT: mov h19, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmin s6, s17, s6 -; NONEON-NOSVE-NEXT: mov h17, v1.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fmin s18, s20, s18 -; NONEON-NOSVE-NEXT: mov h20, v3.h[6] -; NONEON-NOSVE-NEXT: mov v4.h[3], v7.h[0] -; NONEON-NOSVE-NEXT: fcvt s7, h22 -; NONEON-NOSVE-NEXT: fcvt s22, h23 -; NONEON-NOSVE-NEXT: mov v5.h[3], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt s16, h21 -; NONEON-NOSVE-NEXT: fcvt s21, h24 -; NONEON-NOSVE-NEXT: fcvt s19, h19 -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: fcvt s23, h25 -; NONEON-NOSVE-NEXT: fcvt h18, s18 -; NONEON-NOSVE-NEXT: fcvt s20, h20 -; NONEON-NOSVE-NEXT: mov h3, v3.h[7] -; NONEON-NOSVE-NEXT: fmin s7, s22, s7 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fmin s16, s21, s16 -; NONEON-NOSVE-NEXT: mov v4.h[4], v6.h[0] -; NONEON-NOSVE-NEXT: fmin s6, s19, s17 -; NONEON-NOSVE-NEXT: mov v5.h[4], v18.h[0] -; NONEON-NOSVE-NEXT: fmin s17, s23, s20 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt h7, s7 -; NONEON-NOSVE-NEXT: fmin s0, s0, s1 -; NONEON-NOSVE-NEXT: fcvt h16, s16 -; NONEON-NOSVE-NEXT: fcvt h6, s6 -; NONEON-NOSVE-NEXT: fmin s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h3, s17 -; NONEON-NOSVE-NEXT: mov v5.h[5], v7.h[0] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: mov v4.h[5], v16.h[0] -; NONEON-NOSVE-NEXT: fcvt h1, s2 -; NONEON-NOSVE-NEXT: mov v5.h[6], v3.h[0] -; NONEON-NOSVE-NEXT: mov v4.h[6], v6.h[0] -; NONEON-NOSVE-NEXT: mov v5.h[7], v1.h[0] -; NONEON-NOSVE-NEXT: mov v4.h[7], v0.h[0] -; NONEON-NOSVE-NEXT: stp q5, q4, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %res = call <16 x half> @llvm.minimum.v16f16(<16 x half> %op1, <16 x half> %op2) @@ -1384,11 +457,6 @@ define <2 x float> @fmin_v2f32(<2 x float> %op1, <2 x float> %op2) { ; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmin_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmin v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.minimum.v2f32(<2 x float> %op1, <2 x float> %op2) ret <2 x float> %res } @@ -1402,11 +470,6 @@ define <4 x float> @fmin_v4f32(<4 x float> %op1, <4 x float> %op2) { ; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmin_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmin v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.minimum.v4f32(<4 x float> %op1, <4 x float> %op2) ret <4 x float> %res } @@ -1422,15 +485,6 @@ define void @fmin_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: fmin z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmin_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fmin v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fmin v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %res = call <8 x float> @llvm.minimum.v8f32(<8 x float> %op1, <8 x float> %op2) @@ -1443,11 +497,6 @@ define <1 x double> @fmin_v1f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK: // %bb.0: ; CHECK-NEXT: fmin d0, d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmin_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmin d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %res = call <1 x double> @llvm.minimum.v1f64(<1 x double> %op1, <1 x double> %op2) ret <1 x double> %res } @@ -1461,11 +510,6 @@ define <2 x double> @fmin_v2f64(<2 x double> %op1, <2 x double> %op2) { ; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmin_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmin v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.minimum.v2f64(<2 x double> %op1, <2 x double> %op2) ret <2 x double> %res } @@ -1481,15 +525,6 @@ define void @fmin_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fmin z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmin_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fmin v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fmin v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %res = call <4 x double> @llvm.minimum.v4f64(<4 x double> %op1, <4 x double> %op2) diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce-fa64.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce-fa64.ll index fdb81b8e5fe1..b56e67d95ba0 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce-fa64.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce-fa64.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sme-fa64 -force-streaming-compatible-sve < %s | FileCheck %s -check-prefix=FA64 ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s -check-prefix=NO-FA64 -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -27,30 +26,6 @@ define half @fadda_v4f16(half %start, <4 x half> %a) { ; NO-FA64-NEXT: fadd h0, h0, h2 ; NO-FA64-NEXT: fadd h0, h0, h1 ; NO-FA64-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadda_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[2] -; NONEON-NOSVE-NEXT: mov h1, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call half @llvm.vector.reduce.fadd.v4f16(half %start, <4 x half> %a) ret half %res } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll index 74a5db4b38e0..df9613a30e40 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -20,30 +19,6 @@ define half @fadda_v4f16(half %start, <4 x half> %a) { ; CHECK-NEXT: fadd h0, h0, h2 ; CHECK-NEXT: fadd h0, h0, h1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadda_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[2] -; NONEON-NOSVE-NEXT: mov h1, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call half @llvm.vector.reduce.fadd.v4f16(half %start, <4 x half> %a) ret half %res } @@ -68,49 +43,6 @@ define half @fadda_v8f16(half %start, <8 x half> %a) { ; CHECK-NEXT: fadd h0, h0, h2 ; CHECK-NEXT: fadd h0, h0, h1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadda_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call half @llvm.vector.reduce.fadd.v8f16(half %start, <8 x half> %a) ret half %res } @@ -151,90 +83,6 @@ define half @fadda_v16f16(half %start, ptr %a) { ; CHECK-NEXT: fadd h0, h0, h2 ; CHECK-NEXT: fadd h0, h0, h1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadda_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: fcvt s2, h1 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call half @llvm.vector.reduce.fadd.v16f16(half %start, <16 x half> %op) ret half %res @@ -248,14 +96,6 @@ define float @fadda_v2f32(float %start, <2 x float> %a) { ; CHECK-NEXT: mov z1.s, z1.s[1] ; CHECK-NEXT: fadd s0, s0, s1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadda_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: mov s2, v1.s[1] -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: ret %res = call float @llvm.vector.reduce.fadd.v2f32(float %start, <2 x float> %a) ret float %res } @@ -272,17 +112,6 @@ define float @fadda_v4f32(float %start, <4 x float> %a) { ; CHECK-NEXT: fadd s0, s0, s2 ; CHECK-NEXT: fadd s0, s0, s1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadda_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov s2, v1.s[1] -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: mov s3, v1.s[2] -; NONEON-NOSVE-NEXT: mov s1, v1.s[3] -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: fadd s0, s0, s3 -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: ret %res = call float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %a) ret float %res } @@ -307,26 +136,6 @@ define float @fadda_v8f32(float %start, ptr %a) { ; CHECK-NEXT: fadd s0, s0, s2 ; CHECK-NEXT: fadd s0, s0, s1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadda_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: mov s2, v1.s[1] -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: mov s3, v1.s[2] -; NONEON-NOSVE-NEXT: mov s1, v1.s[3] -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: fadd s0, s0, s3 -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: mov s2, v1.s[1] -; NONEON-NOSVE-NEXT: mov s3, v1.s[2] -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: mov s1, v1.s[3] -; NONEON-NOSVE-NEXT: fadd s0, s0, s2 -; NONEON-NOSVE-NEXT: fadd s0, s0, s3 -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %op) ret float %res @@ -337,11 +146,6 @@ define double @fadda_v1f64(double %start, <1 x double> %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: fadd d0, d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadda_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fadd d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %res = call double @llvm.vector.reduce.fadd.v1f64(double %start, <1 x double> %a) ret double %res } @@ -354,13 +158,6 @@ define double @fadda_v2f64(double %start, <2 x double> %a) { ; CHECK-NEXT: mov z1.d, z1.d[1] ; CHECK-NEXT: fadd d0, d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadda_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov d2, v1.d[1] -; NONEON-NOSVE-NEXT: fadd d0, d0, d1 -; NONEON-NOSVE-NEXT: fadd d0, d0, d2 -; NONEON-NOSVE-NEXT: ret %res = call double @llvm.vector.reduce.fadd.v2f64(double %start, <2 x double> %a) ret double %res } @@ -377,17 +174,6 @@ define double @fadda_v4f64(double %start, ptr %a) { ; CHECK-NEXT: mov z1.d, z1.d[1] ; CHECK-NEXT: fadd d0, d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadda_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q3, q1, [x0] -; NONEON-NOSVE-NEXT: mov d2, v3.d[1] -; NONEON-NOSVE-NEXT: fadd d0, d0, d3 -; NONEON-NOSVE-NEXT: fadd d0, d0, d2 -; NONEON-NOSVE-NEXT: mov d2, v1.d[1] -; NONEON-NOSVE-NEXT: fadd d0, d0, d1 -; NONEON-NOSVE-NEXT: fadd d0, d0, d2 -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call double @llvm.vector.reduce.fadd.v4f64(double %start, <4 x double> %op) ret double %res @@ -405,30 +191,6 @@ define half @faddv_v4f16(half %start, <4 x half> %a) { ; CHECK-NEXT: faddv h1, p0, z1.h ; CHECK-NEXT: fadd h0, h0, h1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: faddv_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt s3, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fadd s2, s3, s2 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: mov h1, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fadd s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fadd s1, s2, s1 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call fast half @llvm.vector.reduce.fadd.v4f16(half %start, <4 x half> %a) ret half %res } @@ -441,49 +203,6 @@ define half @faddv_v8f16(half %start, <8 x half> %a) { ; CHECK-NEXT: faddv h1, p0, z1.h ; CHECK-NEXT: fadd h0, h0, h1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: faddv_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt s3, h1 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fadd s2, s3, s2 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fadd s2, s2, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fadd s2, s2, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fadd s2, s2, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fadd s2, s2, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[6] -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fadd s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fadd s1, s2, s1 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call fast half @llvm.vector.reduce.fadd.v8f16(half %start, <8 x half> %a) ret half %res } @@ -497,58 +216,6 @@ define half @faddv_v16f16(half %start, ptr %a) { ; CHECK-NEXT: faddv h1, p0, z1.h ; CHECK-NEXT: fadd h0, h0, h1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: faddv_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl v4.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v2.8h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fadd v3.4s, v4.4s, v3.4s -; NONEON-NOSVE-NEXT: fadd v1.4s, v1.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtn v2.4h, v3.4s -; NONEON-NOSVE-NEXT: fcvtn2 v2.8h, v1.4s -; NONEON-NOSVE-NEXT: mov h1, v2.h[1] -; NONEON-NOSVE-NEXT: fcvt s3, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fadd s1, s3, s1 -; NONEON-NOSVE-NEXT: mov h3, v2.h[2] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fadd s1, s1, s3 -; NONEON-NOSVE-NEXT: mov h3, v2.h[3] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fadd s1, s1, s3 -; NONEON-NOSVE-NEXT: mov h3, v2.h[4] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fadd s1, s1, s3 -; NONEON-NOSVE-NEXT: mov h3, v2.h[5] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fadd s1, s1, s3 -; NONEON-NOSVE-NEXT: mov h3, v2.h[6] -; NONEON-NOSVE-NEXT: mov h2, v2.h[7] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fadd s1, s1, s3 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fadd s1, s1, s2 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call fast half @llvm.vector.reduce.fadd.v16f16(half %start, <16 x half> %op) ret half %res @@ -562,12 +229,6 @@ define float @faddv_v2f32(float %start, <2 x float> %a) { ; CHECK-NEXT: faddv s1, p0, z1.s ; CHECK-NEXT: fadd s0, s0, s1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: faddv_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: faddp s1, v1.2s -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: ret %res = call fast float @llvm.vector.reduce.fadd.v2f32(float %start, <2 x float> %a) ret float %res } @@ -580,13 +241,6 @@ define float @faddv_v4f32(float %start, <4 x float> %a) { ; CHECK-NEXT: faddv s1, p0, z1.s ; CHECK-NEXT: fadd s0, s0, s1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: faddv_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: faddp v1.4s, v1.4s, v1.4s -; NONEON-NOSVE-NEXT: faddp s1, v1.2s -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: ret %res = call fast float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %a) ret float %res } @@ -600,15 +254,6 @@ define float @faddv_v8f32(float %start, ptr %a) { ; CHECK-NEXT: faddv s1, p0, z1.s ; CHECK-NEXT: fadd s0, s0, s1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: faddv_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q1, [x0] -; NONEON-NOSVE-NEXT: fadd v1.4s, v2.4s, v1.4s -; NONEON-NOSVE-NEXT: faddp v1.4s, v1.4s, v1.4s -; NONEON-NOSVE-NEXT: faddp s1, v1.2s -; NONEON-NOSVE-NEXT: fadd s0, s0, s1 -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call fast float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %op) ret float %res @@ -619,11 +264,6 @@ define double @faddv_v1f64(double %start, <1 x double> %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: fadd d0, d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: faddv_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fadd d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %res = call fast double @llvm.vector.reduce.fadd.v1f64(double %start, <1 x double> %a) ret double %res } @@ -636,12 +276,6 @@ define double @faddv_v2f64(double %start, <2 x double> %a) { ; CHECK-NEXT: faddv d1, p0, z1.d ; CHECK-NEXT: fadd d0, d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: faddv_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: faddp d1, v1.2d -; NONEON-NOSVE-NEXT: fadd d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %res = call fast double @llvm.vector.reduce.fadd.v2f64(double %start, <2 x double> %a) ret double %res } @@ -655,14 +289,6 @@ define double @faddv_v4f64(double %start, ptr %a) { ; CHECK-NEXT: faddv d1, p0, z1.d ; CHECK-NEXT: fadd d0, d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: faddv_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q1, [x0] -; NONEON-NOSVE-NEXT: fadd v1.2d, v2.2d, v1.2d -; NONEON-NOSVE-NEXT: faddp d1, v1.2d -; NONEON-NOSVE-NEXT: fadd d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call fast double @llvm.vector.reduce.fadd.v4f64(double %start, <4 x double> %op) ret double %res @@ -680,26 +306,6 @@ define half @fmaxv_v4f16(<4 x half> %a) { ; CHECK-NEXT: fmaxnmv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxv_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmaxnm s1, s2, s1 -; NONEON-NOSVE-NEXT: mov h2, v0.h[2] -; NONEON-NOSVE-NEXT: mov h0, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmaxnm s1, s1, s2 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmaxnm s0, s1, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a) ret half %res } @@ -712,45 +318,6 @@ define half @fmaxv_v8f16(<8 x half> %a) { ; CHECK-NEXT: fmaxnmv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxv_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmaxnm s1, s2, s1 -; NONEON-NOSVE-NEXT: mov h2, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmaxnm s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmaxnm s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[4] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmaxnm s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmaxnm s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmaxnm s1, s1, s2 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmaxnm s0, s1, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %a) ret half %res } @@ -764,85 +331,6 @@ define half @fmaxv_v16f16(ptr %a) { ; CHECK-NEXT: fmaxnmv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxv_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fmaxnm s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[2] -; NONEON-NOSVE-NEXT: fmaxnm s2, s3, s2 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmaxnm s3, s5, s3 -; NONEON-NOSVE-NEXT: mov h5, v0.h[3] -; NONEON-NOSVE-NEXT: fmaxnm s2, s4, s2 -; NONEON-NOSVE-NEXT: mov h4, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmaxnm s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[4] -; NONEON-NOSVE-NEXT: fmaxnm s2, s2, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmaxnm s3, s5, s3 -; NONEON-NOSVE-NEXT: mov h5, v0.h[5] -; NONEON-NOSVE-NEXT: fmaxnm s2, s2, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmaxnm s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fmaxnm s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h3, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmaxnm s0, s0, s1 -; NONEON-NOSVE-NEXT: fmaxnm s2, s2, s3 -; NONEON-NOSVE-NEXT: fmaxnm s3, s5, s4 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fmaxnm s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h1, s2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmaxnm s0, s1, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %op) ret half %res @@ -856,11 +344,6 @@ define float @fmaxv_v2f32(<2 x float> %a) { ; CHECK-NEXT: fmaxnmv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxv_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmaxnmp s0, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %a) ret float %res } @@ -873,11 +356,6 @@ define float @fmaxv_v4f32(<4 x float> %a) { ; CHECK-NEXT: fmaxnmv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxv_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmaxnmv s0, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a) ret float %res } @@ -891,13 +369,6 @@ define float @fmaxv_v8f32(ptr %a) { ; CHECK-NEXT: fmaxnmv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxv_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: fmaxnm v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fmaxnmv s0, v0.4s -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %op) ret float %res @@ -907,10 +378,6 @@ define double @fmaxv_v1f64(<1 x double> %a) { ; CHECK-LABEL: fmaxv_v1f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxv_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ret %res = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a) ret double %res } @@ -923,11 +390,6 @@ define double @fmaxv_v2f64(<2 x double> %a) { ; CHECK-NEXT: fmaxnmv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxv_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmaxnmp d0, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a) ret double %res } @@ -941,13 +403,6 @@ define double @fmaxv_v4f64(ptr %a) { ; CHECK-NEXT: fmaxnmv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaxv_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: fmaxnm v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fmaxnmp d0, v0.2d -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %op) ret double %res @@ -965,26 +420,6 @@ define half @fminv_v4f16(<4 x half> %a) { ; CHECK-NEXT: fminnmv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminv_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fminnm s1, s2, s1 -; NONEON-NOSVE-NEXT: mov h2, v0.h[2] -; NONEON-NOSVE-NEXT: mov h0, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fminnm s1, s1, s2 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fminnm s0, s1, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a) ret half %res } @@ -997,45 +432,6 @@ define half @fminv_v8f16(<8 x half> %a) { ; CHECK-NEXT: fminnmv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminv_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fminnm s1, s2, s1 -; NONEON-NOSVE-NEXT: mov h2, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fminnm s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fminnm s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[4] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fminnm s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fminnm s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fminnm s1, s1, s2 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fminnm s0, s1, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call half @llvm.vector.reduce.fmin.v8f16(<8 x half> %a) ret half %res } @@ -1049,85 +445,6 @@ define half @fminv_v16f16(ptr %a) { ; CHECK-NEXT: fminnmv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminv_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fminnm s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[2] -; NONEON-NOSVE-NEXT: fminnm s2, s3, s2 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fminnm s3, s5, s3 -; NONEON-NOSVE-NEXT: mov h5, v0.h[3] -; NONEON-NOSVE-NEXT: fminnm s2, s4, s2 -; NONEON-NOSVE-NEXT: mov h4, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fminnm s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[4] -; NONEON-NOSVE-NEXT: fminnm s2, s2, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fminnm s3, s5, s3 -; NONEON-NOSVE-NEXT: mov h5, v0.h[5] -; NONEON-NOSVE-NEXT: fminnm s2, s2, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fminnm s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fminnm s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h3, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fminnm s0, s0, s1 -; NONEON-NOSVE-NEXT: fminnm s2, s2, s3 -; NONEON-NOSVE-NEXT: fminnm s3, s5, s4 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fminnm s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h1, s2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fminnm s0, s1, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %op) ret half %res @@ -1141,11 +458,6 @@ define float @fminv_v2f32(<2 x float> %a) { ; CHECK-NEXT: fminnmv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminv_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fminnmp s0, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a) ret float %res } @@ -1158,11 +470,6 @@ define float @fminv_v4f32(<4 x float> %a) { ; CHECK-NEXT: fminnmv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminv_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fminnmv s0, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a) ret float %res } @@ -1176,13 +483,6 @@ define float @fminv_v8f32(ptr %a) { ; CHECK-NEXT: fminnmv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminv_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: fminnm v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fminnmv s0, v0.4s -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> %op) ret float %res @@ -1192,10 +492,6 @@ define double @fminv_v1f64(<1 x double> %a) { ; CHECK-LABEL: fminv_v1f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminv_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ret %res = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a) ret double %res } @@ -1208,11 +504,6 @@ define double @fminv_v2f64(<2 x double> %a) { ; CHECK-NEXT: fminnmv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminv_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fminnmp d0, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a) ret double %res } @@ -1226,13 +517,6 @@ define double @fminv_v4f64(ptr %a) { ; CHECK-NEXT: fminnmv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminv_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: fminnm v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fminnmp d0, v0.2d -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %op) ret double %res @@ -1250,26 +534,6 @@ define half @fmaximumv_v4f16(<4 x half> %a) { ; CHECK-NEXT: fmaxv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaximumv_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmax s1, s2, s1 -; NONEON-NOSVE-NEXT: mov h2, v0.h[2] -; NONEON-NOSVE-NEXT: mov h0, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmax s1, s1, s2 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmax s0, s1, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call half @llvm.vector.reduce.fmaximum.v4f16(<4 x half> %a) ret half %res } @@ -1282,45 +546,6 @@ define half @fmaximumv_v8f16(<8 x half> %a) { ; CHECK-NEXT: fmaxv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaximumv_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmax s1, s2, s1 -; NONEON-NOSVE-NEXT: mov h2, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmax s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmax s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[4] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmax s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmax s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmax s1, s1, s2 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmax s0, s1, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call half @llvm.vector.reduce.fmaximum.v8f16(<8 x half> %a) ret half %res } @@ -1334,85 +559,6 @@ define half @fmaximumv_v16f16(ptr %a) { ; CHECK-NEXT: fmaxv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaximumv_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fmax s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[2] -; NONEON-NOSVE-NEXT: fmax s2, s3, s2 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmax s3, s5, s3 -; NONEON-NOSVE-NEXT: mov h5, v0.h[3] -; NONEON-NOSVE-NEXT: fmax s2, s4, s2 -; NONEON-NOSVE-NEXT: mov h4, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmax s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[4] -; NONEON-NOSVE-NEXT: fmax s2, s2, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmax s3, s5, s3 -; NONEON-NOSVE-NEXT: mov h5, v0.h[5] -; NONEON-NOSVE-NEXT: fmax s2, s2, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmax s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fmax s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h3, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmax s0, s0, s1 -; NONEON-NOSVE-NEXT: fmax s2, s2, s3 -; NONEON-NOSVE-NEXT: fmax s3, s5, s4 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fmax s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h1, s2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmax s0, s1, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call half @llvm.vector.reduce.fmaximum.v16f16(<16 x half> %op) ret half %res @@ -1426,11 +572,6 @@ define float @fmaximumv_v2f32(<2 x float> %a) { ; CHECK-NEXT: fmaxv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaximumv_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmaxp s0, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call float @llvm.vector.reduce.fmaximum.v2f32(<2 x float> %a) ret float %res } @@ -1443,11 +584,6 @@ define float @fmaximumv_v4f32(<4 x float> %a) { ; CHECK-NEXT: fmaxv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaximumv_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmaxv s0, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %a) ret float %res } @@ -1461,13 +597,6 @@ define float @fmaximumv_v8f32(ptr %a) { ; CHECK-NEXT: fmaxv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaximumv_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: fmax v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fmaxv s0, v0.4s -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> %op) ret float %res @@ -1477,10 +606,6 @@ define double @fmaximumv_v1f64(<1 x double> %a) { ; CHECK-LABEL: fmaximumv_v1f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaximumv_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ret %res = call double @llvm.vector.reduce.fmaximum.v1f64(<1 x double> %a) ret double %res } @@ -1493,11 +618,6 @@ define double @fmaximumv_v2f64(<2 x double> %a) { ; CHECK-NEXT: fmaxv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaximumv_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmaxp d0, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %a) ret double %res } @@ -1511,13 +631,6 @@ define double @fmaximumv_v4f64(ptr %a) { ; CHECK-NEXT: fmaxv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fmaximumv_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: fmax v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fmaxp d0, v0.2d -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %op) ret double %res @@ -1535,26 +648,6 @@ define half @fminimumv_v4f16(<4 x half> %a) { ; CHECK-NEXT: fminv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminimumv_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmin s1, s2, s1 -; NONEON-NOSVE-NEXT: mov h2, v0.h[2] -; NONEON-NOSVE-NEXT: mov h0, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmin s1, s1, s2 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmin s0, s1, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call half @llvm.vector.reduce.fminimum.v4f16(<4 x half> %a) ret half %res } @@ -1567,45 +660,6 @@ define half @fminimumv_v8f16(<8 x half> %a) { ; CHECK-NEXT: fminv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminimumv_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmin s1, s2, s1 -; NONEON-NOSVE-NEXT: mov h2, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmin s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmin s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[4] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmin s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmin s1, s1, s2 -; NONEON-NOSVE-NEXT: mov h2, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmin s1, s1, s2 -; NONEON-NOSVE-NEXT: fcvt h1, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmin s0, s1, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %res = call half @llvm.vector.reduce.fminimum.v8f16(<8 x half> %a) ret half %res } @@ -1619,85 +673,6 @@ define half @fminimumv_v16f16(ptr %a) { ; CHECK-NEXT: fminv h0, p0, z0.h ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminimumv_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s4, h1 -; NONEON-NOSVE-NEXT: fcvt s5, h0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fmin s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[2] -; NONEON-NOSVE-NEXT: fmin s2, s3, s2 -; NONEON-NOSVE-NEXT: mov h3, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmin s3, s5, s3 -; NONEON-NOSVE-NEXT: mov h5, v0.h[3] -; NONEON-NOSVE-NEXT: fmin s2, s4, s2 -; NONEON-NOSVE-NEXT: mov h4, v1.h[3] -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmin s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[4] -; NONEON-NOSVE-NEXT: fmin s2, s2, s3 -; NONEON-NOSVE-NEXT: mov h3, v1.h[4] -; NONEON-NOSVE-NEXT: fcvt h4, s4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmin s3, s5, s3 -; NONEON-NOSVE-NEXT: mov h5, v0.h[5] -; NONEON-NOSVE-NEXT: fmin s2, s2, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[5] -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmin s4, s5, s4 -; NONEON-NOSVE-NEXT: mov h5, v0.h[6] -; NONEON-NOSVE-NEXT: mov h0, v0.h[7] -; NONEON-NOSVE-NEXT: fmin s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h3, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[6] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: mov h1, v1.h[7] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fmin s0, s0, s1 -; NONEON-NOSVE-NEXT: fmin s2, s2, s3 -; NONEON-NOSVE-NEXT: fmin s3, s5, s4 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: fcvt h2, s2 -; NONEON-NOSVE-NEXT: fcvt h3, s3 -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fmin s2, s2, s3 -; NONEON-NOSVE-NEXT: fcvt h1, s2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fmin s0, s1, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call half @llvm.vector.reduce.fminimum.v16f16(<16 x half> %op) ret half %res @@ -1711,11 +686,6 @@ define float @fminimumv_v2f32(<2 x float> %a) { ; CHECK-NEXT: fminv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminimumv_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fminp s0, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call float @llvm.vector.reduce.fminimum.v2f32(<2 x float> %a) ret float %res } @@ -1728,11 +698,6 @@ define float @fminimumv_v4f32(<4 x float> %a) { ; CHECK-NEXT: fminv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminimumv_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fminv s0, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %a) ret float %res } @@ -1746,13 +711,6 @@ define float @fminimumv_v8f32(ptr %a) { ; CHECK-NEXT: fminv s0, p0, z0.s ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminimumv_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: fmin v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fminv s0, v0.4s -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call float @llvm.vector.reduce.fminimum.v8f32(<8 x float> %op) ret float %res @@ -1762,10 +720,6 @@ define double @fminimumv_v1f64(<1 x double> %a) { ; CHECK-LABEL: fminimumv_v1f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminimumv_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ret %res = call double @llvm.vector.reduce.fminimum.v1f64(<1 x double> %a) ret double %res } @@ -1778,11 +732,6 @@ define double @fminimumv_v2f64(<2 x double> %a) { ; CHECK-NEXT: fminv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminimumv_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fminp d0, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %a) ret double %res } @@ -1796,13 +745,6 @@ define double @fminimumv_v4f64(ptr %a) { ; CHECK-NEXT: fminv d0, p0, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fminimumv_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: fmin v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fminp d0, v0.2d -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %op) ret double %res diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll index 454683865eb9..7ddc641f366c 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -17,13 +16,6 @@ define <2 x half> @frintp_v2f16(<2 x half> %op) { ; CHECK-NEXT: frintp z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintp_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frintp v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <2 x half> @llvm.ceil.v2f16(<2 x half> %op) ret <2 x half> %res } @@ -36,13 +28,6 @@ define <4 x half> @frintp_v4f16(<4 x half> %op) { ; CHECK-NEXT: frintp z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintp_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frintp v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.ceil.v4f16(<4 x half> %op) ret <4 x half> %res } @@ -55,16 +40,6 @@ define <8 x half> @frintp_v8f16(<8 x half> %op) { ; CHECK-NEXT: frintp z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintp_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v0.8h -; NONEON-NOSVE-NEXT: frintp v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v1.4s -; NONEON-NOSVE-NEXT: frintp v1.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.ceil.v8f16(<8 x half> %op) ret <8 x half> %res } @@ -78,24 +53,6 @@ define void @frintp_v16f16(ptr %a) { ; CHECK-NEXT: frintp z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintp_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: frintp v2.4s, v2.4s -; NONEON-NOSVE-NEXT: frintp v3.4s, v3.4s -; NONEON-NOSVE-NEXT: frintp v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frintp v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v2.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v3.4s -; NONEON-NOSVE-NEXT: fcvtn2 v2.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v1.4s -; NONEON-NOSVE-NEXT: stp q2, q3, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.ceil.v16f16(<16 x half> %op) store <16 x half> %res, ptr %a @@ -110,11 +67,6 @@ define <2 x float> @frintp_v2f32(<2 x float> %op) { ; CHECK-NEXT: frintp z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintp_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintp v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.ceil.v2f32(<2 x float> %op) ret <2 x float> %res } @@ -127,11 +79,6 @@ define <4 x float> @frintp_v4f32(<4 x float> %op) { ; CHECK-NEXT: frintp z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintp_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintp v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.ceil.v4f32(<4 x float> %op) ret <4 x float> %res } @@ -145,14 +92,6 @@ define void @frintp_v8f32(ptr %a) { ; CHECK-NEXT: frintp z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintp_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frintp v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frintp v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.ceil.v8f32(<8 x float> %op) store <8 x float> %res, ptr %a @@ -164,11 +103,6 @@ define <1 x double> @frintp_v1f64(<1 x double> %op) { ; CHECK: // %bb.0: ; CHECK-NEXT: frintp d0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintp_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintp d0, d0 -; NONEON-NOSVE-NEXT: ret %res = call <1 x double> @llvm.ceil.v1f64(<1 x double> %op) ret <1 x double> %res } @@ -181,11 +115,6 @@ define <2 x double> @frintp_v2f64(<2 x double> %op) { ; CHECK-NEXT: frintp z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintp_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintp v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.ceil.v2f64(<2 x double> %op) ret <2 x double> %res } @@ -199,14 +128,6 @@ define void @frintp_v4f64(ptr %a) { ; CHECK-NEXT: frintp z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintp_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frintp v0.2d, v0.2d -; NONEON-NOSVE-NEXT: frintp v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.ceil.v4f64(<4 x double> %op) store <4 x double> %res, ptr %a @@ -225,13 +146,6 @@ define <2 x half> @frintm_v2f16(<2 x half> %op) { ; CHECK-NEXT: frintm z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintm_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frintm v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <2 x half> @llvm.floor.v2f16(<2 x half> %op) ret <2 x half> %res } @@ -244,13 +158,6 @@ define <4 x half> @frintm_v4f16(<4 x half> %op) { ; CHECK-NEXT: frintm z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintm_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frintm v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.floor.v4f16(<4 x half> %op) ret <4 x half> %res } @@ -263,16 +170,6 @@ define <8 x half> @frintm_v8f16(<8 x half> %op) { ; CHECK-NEXT: frintm z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintm_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v0.8h -; NONEON-NOSVE-NEXT: frintm v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v1.4s -; NONEON-NOSVE-NEXT: frintm v1.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.floor.v8f16(<8 x half> %op) ret <8 x half> %res } @@ -286,24 +183,6 @@ define void @frintm_v16f16(ptr %a) { ; CHECK-NEXT: frintm z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintm_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: frintm v2.4s, v2.4s -; NONEON-NOSVE-NEXT: frintm v3.4s, v3.4s -; NONEON-NOSVE-NEXT: frintm v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frintm v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v2.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v3.4s -; NONEON-NOSVE-NEXT: fcvtn2 v2.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v1.4s -; NONEON-NOSVE-NEXT: stp q2, q3, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.floor.v16f16(<16 x half> %op) store <16 x half> %res, ptr %a @@ -318,11 +197,6 @@ define <2 x float> @frintm_v2f32(<2 x float> %op) { ; CHECK-NEXT: frintm z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintm_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintm v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.floor.v2f32(<2 x float> %op) ret <2 x float> %res } @@ -335,11 +209,6 @@ define <4 x float> @frintm_v4f32(<4 x float> %op) { ; CHECK-NEXT: frintm z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintm_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintm v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.floor.v4f32(<4 x float> %op) ret <4 x float> %res } @@ -353,14 +222,6 @@ define void @frintm_v8f32(ptr %a) { ; CHECK-NEXT: frintm z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintm_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frintm v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frintm v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.floor.v8f32(<8 x float> %op) store <8 x float> %res, ptr %a @@ -372,11 +233,6 @@ define <1 x double> @frintm_v1f64(<1 x double> %op) { ; CHECK: // %bb.0: ; CHECK-NEXT: frintm d0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintm_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintm d0, d0 -; NONEON-NOSVE-NEXT: ret %res = call <1 x double> @llvm.floor.v1f64(<1 x double> %op) ret <1 x double> %res } @@ -389,11 +245,6 @@ define <2 x double> @frintm_v2f64(<2 x double> %op) { ; CHECK-NEXT: frintm z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintm_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintm v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.floor.v2f64(<2 x double> %op) ret <2 x double> %res } @@ -407,14 +258,6 @@ define void @frintm_v4f64(ptr %a) { ; CHECK-NEXT: frintm z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintm_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frintm v0.2d, v0.2d -; NONEON-NOSVE-NEXT: frintm v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.floor.v4f64(<4 x double> %op) store <4 x double> %res, ptr %a @@ -433,13 +276,6 @@ define <2 x half> @frinti_v2f16(<2 x half> %op) { ; CHECK-NEXT: frinti z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinti_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frinti v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <2 x half> @llvm.nearbyint.v2f16(<2 x half> %op) ret <2 x half> %res } @@ -452,13 +288,6 @@ define <4 x half> @frinti_v4f16(<4 x half> %op) { ; CHECK-NEXT: frinti z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinti_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frinti v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.nearbyint.v4f16(<4 x half> %op) ret <4 x half> %res } @@ -471,16 +300,6 @@ define <8 x half> @frinti_v8f16(<8 x half> %op) { ; CHECK-NEXT: frinti z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinti_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v0.8h -; NONEON-NOSVE-NEXT: frinti v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v1.4s -; NONEON-NOSVE-NEXT: frinti v1.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.nearbyint.v8f16(<8 x half> %op) ret <8 x half> %res } @@ -494,24 +313,6 @@ define void @frinti_v16f16(ptr %a) { ; CHECK-NEXT: frinti z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinti_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: frinti v2.4s, v2.4s -; NONEON-NOSVE-NEXT: frinti v3.4s, v3.4s -; NONEON-NOSVE-NEXT: frinti v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frinti v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v2.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v3.4s -; NONEON-NOSVE-NEXT: fcvtn2 v2.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v1.4s -; NONEON-NOSVE-NEXT: stp q2, q3, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.nearbyint.v16f16(<16 x half> %op) store <16 x half> %res, ptr %a @@ -526,11 +327,6 @@ define <2 x float> @frinti_v2f32(<2 x float> %op) { ; CHECK-NEXT: frinti z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinti_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frinti v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %op) ret <2 x float> %res } @@ -543,11 +339,6 @@ define <4 x float> @frinti_v4f32(<4 x float> %op) { ; CHECK-NEXT: frinti z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinti_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frinti v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %op) ret <4 x float> %res } @@ -561,14 +352,6 @@ define void @frinti_v8f32(ptr %a) { ; CHECK-NEXT: frinti z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinti_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frinti v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frinti v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %op) store <8 x float> %res, ptr %a @@ -580,11 +363,6 @@ define <1 x double> @frinti_v1f64(<1 x double> %op) { ; CHECK: // %bb.0: ; CHECK-NEXT: frinti d0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinti_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frinti d0, d0 -; NONEON-NOSVE-NEXT: ret %res = call <1 x double> @llvm.nearbyint.v1f64(<1 x double> %op) ret <1 x double> %res } @@ -597,11 +375,6 @@ define <2 x double> @frinti_v2f64(<2 x double> %op) { ; CHECK-NEXT: frinti z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinti_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frinti v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %op) ret <2 x double> %res } @@ -615,14 +388,6 @@ define void @frinti_v4f64(ptr %a) { ; CHECK-NEXT: frinti z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinti_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frinti v0.2d, v0.2d -; NONEON-NOSVE-NEXT: frinti v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %op) store <4 x double> %res, ptr %a @@ -641,13 +406,6 @@ define <2 x half> @frintx_v2f16(<2 x half> %op) { ; CHECK-NEXT: frintx z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintx_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frintx v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <2 x half> @llvm.rint.v2f16(<2 x half> %op) ret <2 x half> %res } @@ -660,13 +418,6 @@ define <4 x half> @frintx_v4f16(<4 x half> %op) { ; CHECK-NEXT: frintx z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintx_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frintx v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.rint.v4f16(<4 x half> %op) ret <4 x half> %res } @@ -679,16 +430,6 @@ define <8 x half> @frintx_v8f16(<8 x half> %op) { ; CHECK-NEXT: frintx z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintx_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v0.8h -; NONEON-NOSVE-NEXT: frintx v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v1.4s -; NONEON-NOSVE-NEXT: frintx v1.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.rint.v8f16(<8 x half> %op) ret <8 x half> %res } @@ -702,24 +443,6 @@ define void @frintx_v16f16(ptr %a) { ; CHECK-NEXT: frintx z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintx_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: frintx v2.4s, v2.4s -; NONEON-NOSVE-NEXT: frintx v3.4s, v3.4s -; NONEON-NOSVE-NEXT: frintx v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frintx v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v2.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v3.4s -; NONEON-NOSVE-NEXT: fcvtn2 v2.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v1.4s -; NONEON-NOSVE-NEXT: stp q2, q3, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.rint.v16f16(<16 x half> %op) store <16 x half> %res, ptr %a @@ -734,11 +457,6 @@ define <2 x float> @frintx_v2f32(<2 x float> %op) { ; CHECK-NEXT: frintx z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintx_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintx v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.rint.v2f32(<2 x float> %op) ret <2 x float> %res } @@ -751,11 +469,6 @@ define <4 x float> @frintx_v4f32(<4 x float> %op) { ; CHECK-NEXT: frintx z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintx_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintx v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.rint.v4f32(<4 x float> %op) ret <4 x float> %res } @@ -769,14 +482,6 @@ define void @frintx_v8f32(ptr %a) { ; CHECK-NEXT: frintx z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintx_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frintx v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frintx v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.rint.v8f32(<8 x float> %op) store <8 x float> %res, ptr %a @@ -788,11 +493,6 @@ define <1 x double> @frintx_v1f64(<1 x double> %op) { ; CHECK: // %bb.0: ; CHECK-NEXT: frintx d0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintx_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintx d0, d0 -; NONEON-NOSVE-NEXT: ret %res = call <1 x double> @llvm.rint.v1f64(<1 x double> %op) ret <1 x double> %res } @@ -805,11 +505,6 @@ define <2 x double> @frintx_v2f64(<2 x double> %op) { ; CHECK-NEXT: frintx z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintx_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintx v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.rint.v2f64(<2 x double> %op) ret <2 x double> %res } @@ -823,14 +518,6 @@ define void @frintx_v4f64(ptr %a) { ; CHECK-NEXT: frintx z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintx_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frintx v0.2d, v0.2d -; NONEON-NOSVE-NEXT: frintx v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.rint.v4f64(<4 x double> %op) store <4 x double> %res, ptr %a @@ -849,13 +536,6 @@ define <2 x half> @frinta_v2f16(<2 x half> %op) { ; CHECK-NEXT: frinta z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinta_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frinta v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <2 x half> @llvm.round.v2f16(<2 x half> %op) ret <2 x half> %res } @@ -868,13 +548,6 @@ define <4 x half> @frinta_v4f16(<4 x half> %op) { ; CHECK-NEXT: frinta z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinta_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frinta v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.round.v4f16(<4 x half> %op) ret <4 x half> %res } @@ -887,16 +560,6 @@ define <8 x half> @frinta_v8f16(<8 x half> %op) { ; CHECK-NEXT: frinta z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinta_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v0.8h -; NONEON-NOSVE-NEXT: frinta v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v1.4s -; NONEON-NOSVE-NEXT: frinta v1.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.round.v8f16(<8 x half> %op) ret <8 x half> %res } @@ -910,24 +573,6 @@ define void @frinta_v16f16(ptr %a) { ; CHECK-NEXT: frinta z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinta_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: frinta v2.4s, v2.4s -; NONEON-NOSVE-NEXT: frinta v3.4s, v3.4s -; NONEON-NOSVE-NEXT: frinta v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frinta v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v2.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v3.4s -; NONEON-NOSVE-NEXT: fcvtn2 v2.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v1.4s -; NONEON-NOSVE-NEXT: stp q2, q3, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.round.v16f16(<16 x half> %op) store <16 x half> %res, ptr %a @@ -942,11 +587,6 @@ define <2 x float> @frinta_v2f32(<2 x float> %op) { ; CHECK-NEXT: frinta z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinta_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frinta v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.round.v2f32(<2 x float> %op) ret <2 x float> %res } @@ -959,11 +599,6 @@ define <4 x float> @frinta_v4f32(<4 x float> %op) { ; CHECK-NEXT: frinta z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinta_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frinta v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.round.v4f32(<4 x float> %op) ret <4 x float> %res } @@ -977,14 +612,6 @@ define void @frinta_v8f32(ptr %a) { ; CHECK-NEXT: frinta z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinta_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frinta v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frinta v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.round.v8f32(<8 x float> %op) store <8 x float> %res, ptr %a @@ -996,11 +623,6 @@ define <1 x double> @frinta_v1f64(<1 x double> %op) { ; CHECK: // %bb.0: ; CHECK-NEXT: frinta d0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinta_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frinta d0, d0 -; NONEON-NOSVE-NEXT: ret %res = call <1 x double> @llvm.round.v1f64(<1 x double> %op) ret <1 x double> %res } @@ -1013,11 +635,6 @@ define <2 x double> @frinta_v2f64(<2 x double> %op) { ; CHECK-NEXT: frinta z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinta_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frinta v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.round.v2f64(<2 x double> %op) ret <2 x double> %res } @@ -1031,14 +648,6 @@ define void @frinta_v4f64(ptr %a) { ; CHECK-NEXT: frinta z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frinta_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frinta v0.2d, v0.2d -; NONEON-NOSVE-NEXT: frinta v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.round.v4f64(<4 x double> %op) store <4 x double> %res, ptr %a @@ -1057,13 +666,6 @@ define <2 x half> @frintn_v2f16(<2 x half> %op) { ; CHECK-NEXT: frintn z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintn_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frintn v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <2 x half> @llvm.roundeven.v2f16(<2 x half> %op) ret <2 x half> %res } @@ -1076,13 +678,6 @@ define <4 x half> @frintn_v4f16(<4 x half> %op) { ; CHECK-NEXT: frintn z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintn_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frintn v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.roundeven.v4f16(<4 x half> %op) ret <4 x half> %res } @@ -1095,16 +690,6 @@ define <8 x half> @frintn_v8f16(<8 x half> %op) { ; CHECK-NEXT: frintn z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintn_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v0.8h -; NONEON-NOSVE-NEXT: frintn v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v1.4s -; NONEON-NOSVE-NEXT: frintn v1.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %op) ret <8 x half> %res } @@ -1118,24 +703,6 @@ define void @frintn_v16f16(ptr %a) { ; CHECK-NEXT: frintn z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintn_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: frintn v2.4s, v2.4s -; NONEON-NOSVE-NEXT: frintn v3.4s, v3.4s -; NONEON-NOSVE-NEXT: frintn v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frintn v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v2.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v3.4s -; NONEON-NOSVE-NEXT: fcvtn2 v2.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v1.4s -; NONEON-NOSVE-NEXT: stp q2, q3, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.roundeven.v16f16(<16 x half> %op) store <16 x half> %res, ptr %a @@ -1150,11 +717,6 @@ define <2 x float> @frintn_v2f32(<2 x float> %op) { ; CHECK-NEXT: frintn z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintn_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintn v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %op) ret <2 x float> %res } @@ -1167,11 +729,6 @@ define <4 x float> @frintn_v4f32(<4 x float> %op) { ; CHECK-NEXT: frintn z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintn_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintn v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %op) ret <4 x float> %res } @@ -1185,14 +742,6 @@ define void @frintn_v8f32(ptr %a) { ; CHECK-NEXT: frintn z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintn_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frintn v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frintn v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.roundeven.v8f32(<8 x float> %op) store <8 x float> %res, ptr %a @@ -1204,11 +753,6 @@ define <1 x double> @frintn_v1f64(<1 x double> %op) { ; CHECK: // %bb.0: ; CHECK-NEXT: frintn d0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintn_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintn d0, d0 -; NONEON-NOSVE-NEXT: ret %res = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %op) ret <1 x double> %res } @@ -1221,11 +765,6 @@ define <2 x double> @frintn_v2f64(<2 x double> %op) { ; CHECK-NEXT: frintn z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintn_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintn v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %op) ret <2 x double> %res } @@ -1239,14 +778,6 @@ define void @frintn_v4f64(ptr %a) { ; CHECK-NEXT: frintn z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintn_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frintn v0.2d, v0.2d -; NONEON-NOSVE-NEXT: frintn v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.roundeven.v4f64(<4 x double> %op) store <4 x double> %res, ptr %a @@ -1265,13 +796,6 @@ define <2 x half> @frintz_v2f16(<2 x half> %op) { ; CHECK-NEXT: frintz z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintz_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frintz v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <2 x half> @llvm.trunc.v2f16(<2 x half> %op) ret <2 x half> %res } @@ -1284,13 +808,6 @@ define <4 x half> @frintz_v4f16(<4 x half> %op) { ; CHECK-NEXT: frintz z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintz_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: frintz v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x half> @llvm.trunc.v4f16(<4 x half> %op) ret <4 x half> %res } @@ -1303,16 +820,6 @@ define <8 x half> @frintz_v8f16(<8 x half> %op) { ; CHECK-NEXT: frintz z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintz_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v0.8h -; NONEON-NOSVE-NEXT: frintz v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v1.4s -; NONEON-NOSVE-NEXT: frintz v1.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <8 x half> @llvm.trunc.v8f16(<8 x half> %op) ret <8 x half> %res } @@ -1326,24 +833,6 @@ define void @frintz_v16f16(ptr %a) { ; CHECK-NEXT: frintz z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintz_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: frintz v2.4s, v2.4s -; NONEON-NOSVE-NEXT: frintz v3.4s, v3.4s -; NONEON-NOSVE-NEXT: frintz v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frintz v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v2.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v3.4s -; NONEON-NOSVE-NEXT: fcvtn2 v2.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v1.4s -; NONEON-NOSVE-NEXT: stp q2, q3, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x half>, ptr %a %res = call <16 x half> @llvm.trunc.v16f16(<16 x half> %op) store <16 x half> %res, ptr %a @@ -1358,11 +847,6 @@ define <2 x float> @frintz_v2f32(<2 x float> %op) { ; CHECK-NEXT: frintz z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintz_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintz v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x float> @llvm.trunc.v2f32(<2 x float> %op) ret <2 x float> %res } @@ -1375,11 +859,6 @@ define <4 x float> @frintz_v4f32(<4 x float> %op) { ; CHECK-NEXT: frintz z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintz_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintz v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x float> @llvm.trunc.v4f32(<4 x float> %op) ret <4 x float> %res } @@ -1393,14 +872,6 @@ define void @frintz_v8f32(ptr %a) { ; CHECK-NEXT: frintz z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintz_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frintz v0.4s, v0.4s -; NONEON-NOSVE-NEXT: frintz v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x float>, ptr %a %res = call <8 x float> @llvm.trunc.v8f32(<8 x float> %op) store <8 x float> %res, ptr %a @@ -1412,11 +883,6 @@ define <1 x double> @frintz_v1f64(<1 x double> %op) { ; CHECK: // %bb.0: ; CHECK-NEXT: frintz d0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintz_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintz d0, d0 -; NONEON-NOSVE-NEXT: ret %res = call <1 x double> @llvm.trunc.v1f64(<1 x double> %op) ret <1 x double> %res } @@ -1429,11 +895,6 @@ define <2 x double> @frintz_v2f64(<2 x double> %op) { ; CHECK-NEXT: frintz z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintz_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: frintz v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x double> @llvm.trunc.v2f64(<2 x double> %op) ret <2 x double> %res } @@ -1447,14 +908,6 @@ define void @frintz_v4f64(ptr %a) { ; CHECK-NEXT: frintz z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: frintz_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: frintz v0.2d, v0.2d -; NONEON-NOSVE-NEXT: frintz v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x double>, ptr %a %res = call <4 x double> @llvm.trunc.v4f64(<4 x double> %op) store <4 x double> %res, ptr %a diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll index 0268dd1b5d31..7d36925fdc57 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -17,14 +16,6 @@ define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.4h, w8 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <2 x half> %op1, <2 x half> %op2 ret <2 x half> %sel } @@ -41,14 +32,6 @@ define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.4h, w8 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <4 x half> %op1, <4 x half> %op2 ret <4 x half> %sel } @@ -65,14 +48,6 @@ define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.8h, w8 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <8 x half> %op1, <8 x half> %op2 ret <8 x half> %sel } @@ -92,20 +67,6 @@ define void @select_v16f16(ptr %a, ptr %b, i1 %mask) { ; CHECK-NEXT: sel z1.h, p0, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w2, #0x1 -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: ldr q2, [x0, #16] -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: ldr q4, [x1, #16] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: bif v1.16b, v3.16b, v0.16b -; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load volatile <16 x half>, ptr %a %op2 = load volatile <16 x half>, ptr %b %sel = select i1 %mask, <16 x half> %op1, <16 x half> %op2 @@ -125,14 +86,6 @@ define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.2s, w8 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <2 x float> %op1, <2 x float> %op2 ret <2 x float> %sel } @@ -149,14 +102,6 @@ define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.4s, w8 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <4 x float> %op1, <4 x float> %op2 ret <4 x float> %sel } @@ -176,20 +121,6 @@ define void @select_v8f32(ptr %a, ptr %b, i1 %mask) { ; CHECK-NEXT: sel z1.s, p0, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w2, #0x1 -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: ldr q2, [x0, #16] -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: ldr q4, [x1, #16] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: bif v1.16b, v3.16b, v0.16b -; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load volatile <8 x float>, ptr %a %op2 = load volatile <8 x float>, ptr %b %sel = select i1 %mask, <8 x float> %op1, <8 x float> %op2 @@ -203,14 +134,6 @@ define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask ; CHECK-NEXT: tst w0, #0x1 ; CHECK-NEXT: fcsel d0, d0, d1, ne ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm x8, ne -; NONEON-NOSVE-NEXT: fmov d2, x8 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <1 x double> %op1, <1 x double> %op2 ret <1 x double> %sel } @@ -228,14 +151,6 @@ define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, i1 %mask ; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm x8, ne -; NONEON-NOSVE-NEXT: dup v2.2d, x8 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <2 x double> %op1, <2 x double> %op2 ret <2 x double> %sel } @@ -256,20 +171,6 @@ define void @select_v4f64(ptr %a, ptr %b, i1 %mask) { ; CHECK-NEXT: sel z1.d, p0, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w2, #0x1 -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: ldr q2, [x0, #16] -; NONEON-NOSVE-NEXT: csetm x8, ne -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: ldr q4, [x1, #16] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: bif v1.16b, v3.16b, v0.16b -; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load volatile <4 x double>, ptr %a %op2 = load volatile <4 x double>, ptr %b %sel = select i1 %mask, <4 x double> %op1, <4 x double> %op2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll index 1c63a3870d68..bf8a335a8503 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -16,13 +15,6 @@ define <4 x i16> @fcvtzu_v4f16_v4i16(<4 x half> %op1) { ; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v4f16_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtzu v0.4s, v0.4s -; NONEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fptoui <4 x half> %op1 to <4 x i16> ret <4 x i16> %res } @@ -35,21 +27,6 @@ define void @fcvtzu_v8f16_v8i16(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v8f16_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtzu v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzu v1.4s, v1.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x half>, ptr %a %res = fptoui <8 x half> %op1 to <8 x i16> store <8 x i16> %res, ptr %b @@ -65,27 +42,6 @@ define void @fcvtzu_v16f16_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzu z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v16f16_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v3.4h -; NONEON-NOSVE-NEXT: fcvtzu v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtzu v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzu v2.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtzu v3.4s, v3.4s -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v1.8h, v2.8h -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %res = fptoui <16 x half> %op1 to <16 x i16> store <16 x i16> %res, ptr %b @@ -105,13 +61,6 @@ define <2 x i32> @fcvtzu_v2f16_v2i32(<2 x half> %op1) { ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v2f16_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtzu v0.4s, v0.4s -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = fptoui <2 x half> %op1 to <2 x i32> ret <2 x i32> %res } @@ -125,12 +74,6 @@ define <4 x i32> @fcvtzu_v4f16_v4i32(<4 x half> %op1) { ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v4f16_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtzu v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fptoui <4 x half> %op1 to <4 x i32> ret <4 x i32> %res } @@ -147,20 +90,6 @@ define void @fcvtzu_v8f16_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v8f16_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtzu v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzu v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x half>, ptr %a %res = fptoui <8 x half> %op1 to <8 x i32> store <8 x i32> %res, ptr %b @@ -185,26 +114,6 @@ define void @fcvtzu_v16f16_v16i32(ptr %a, ptr %b) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v16f16_v16i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v3.4h -; NONEON-NOSVE-NEXT: fcvtzu v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtzu v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzu v2.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtzu v3.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %res = fptoui <16 x half> %op1 to <16 x i32> store <16 x i32> %res, ptr %b @@ -221,13 +130,6 @@ define <1 x i64> @fcvtzu_v1f16_v1i64(<1 x half> %op1) { ; CHECK-NEXT: fcvtzu x8, h0 ; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v1f16_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvtzu x8, s0 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %res = fptoui <1 x half> %op1 to <1 x i64> ret <1 x i64> %res } @@ -243,18 +145,6 @@ define <2 x i64> @fcvtzu_v2f16_v2i64(<2 x half> %op1) { ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: ldr q0, [sp], #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v2f16_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvtzu x8, s0 -; NONEON-NOSVE-NEXT: fcvtzu x9, s1 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: mov v0.d[1], x9 -; NONEON-NOSVE-NEXT: ret %res = fptoui <2 x half> %op1 to <2 x i64> ret <2 x i64> %res } @@ -277,27 +167,6 @@ define void @fcvtzu_v4f16_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v4f16_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: mov h1, v0.h[2] -; NONEON-NOSVE-NEXT: mov h2, v0.h[3] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvtzu x9, s0 -; NONEON-NOSVE-NEXT: fcvtzu x8, s1 -; NONEON-NOSVE-NEXT: fcvtzu x10, s2 -; NONEON-NOSVE-NEXT: fcvtzu x11, s3 -; NONEON-NOSVE-NEXT: fmov d1, x9 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: mov v1.d[1], x11 -; NONEON-NOSVE-NEXT: mov v0.d[1], x10 -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x half>, ptr %a %res = fptoui <4 x half> %op1 to <4 x i64> store <4 x i64> %res, ptr %b @@ -335,47 +204,6 @@ define void @fcvtzu_v8f16_v8i64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q1, q0, [x1, #32] ; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v8f16_v8i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: mov h1, v0.h[2] -; NONEON-NOSVE-NEXT: mov h3, v0.h[3] -; NONEON-NOSVE-NEXT: mov h4, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov h5, v2.h[2] -; NONEON-NOSVE-NEXT: mov h6, v2.h[3] -; NONEON-NOSVE-NEXT: mov h7, v2.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvtzu x9, s0 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvtzu x13, s2 -; NONEON-NOSVE-NEXT: fcvtzu x8, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h7 -; NONEON-NOSVE-NEXT: fcvtzu x10, s3 -; NONEON-NOSVE-NEXT: fcvtzu x11, s4 -; NONEON-NOSVE-NEXT: fcvtzu x12, s5 -; NONEON-NOSVE-NEXT: fcvtzu x14, s6 -; NONEON-NOSVE-NEXT: fmov d3, x13 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: fcvtzu x8, s1 -; NONEON-NOSVE-NEXT: fmov d1, x9 -; NONEON-NOSVE-NEXT: fmov d2, x12 -; NONEON-NOSVE-NEXT: mov v0.d[1], x10 -; NONEON-NOSVE-NEXT: mov v1.d[1], x11 -; NONEON-NOSVE-NEXT: mov v3.d[1], x8 -; NONEON-NOSVE-NEXT: mov v2.d[1], x14 -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: stp q3, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x half>, ptr %a %res = fptoui <8 x half> %op1 to <8 x i64> store <8 x i64> %res, ptr %b @@ -436,80 +264,6 @@ define void @fcvtzu_v16f16_v16i64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q5, q2, [x1, #96] ; CHECK-NEXT: add sp, sp, #128 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v16f16_v16i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: mov h2, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s3, h1 -; NONEON-NOSVE-NEXT: ldr d4, [sp, #24] -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: mov h7, v0.h[2] -; NONEON-NOSVE-NEXT: mov h16, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt s6, h0 -; NONEON-NOSVE-NEXT: mov h0, v0.h[1] -; NONEON-NOSVE-NEXT: mov h1, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt s17, h4 -; NONEON-NOSVE-NEXT: mov h18, v4.h[2] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvtzu x8, s3 -; NONEON-NOSVE-NEXT: fcvt s3, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h7 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: mov h16, v4.h[3] -; NONEON-NOSVE-NEXT: fcvtzu x9, s6 -; NONEON-NOSVE-NEXT: ldr d6, [sp, #8] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: mov h4, v4.h[1] -; NONEON-NOSVE-NEXT: fcvtzu x11, s2 -; NONEON-NOSVE-NEXT: mov h2, v6.h[2] -; NONEON-NOSVE-NEXT: fcvtzu x10, s17 -; NONEON-NOSVE-NEXT: fcvtzu x13, s5 -; NONEON-NOSVE-NEXT: fcvtzu x12, s3 -; NONEON-NOSVE-NEXT: mov h3, v6.h[3] -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: mov h5, v6.h[1] -; NONEON-NOSVE-NEXT: fcvt s17, h18 -; NONEON-NOSVE-NEXT: fcvtzu x14, s7 -; NONEON-NOSVE-NEXT: fmov d7, x8 -; NONEON-NOSVE-NEXT: fcvtzu x8, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fmov d0, x11 -; NONEON-NOSVE-NEXT: fcvtzu x11, s1 -; NONEON-NOSVE-NEXT: fmov d1, x13 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvtzu x13, s16 -; NONEON-NOSVE-NEXT: fmov d16, x9 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvtzu x15, s17 -; NONEON-NOSVE-NEXT: mov v0.d[1], x12 -; NONEON-NOSVE-NEXT: mov v1.d[1], x14 -; NONEON-NOSVE-NEXT: fcvtzu x9, s2 -; NONEON-NOSVE-NEXT: mov v16.d[1], x8 -; NONEON-NOSVE-NEXT: fcvtzu x8, s6 -; NONEON-NOSVE-NEXT: fcvtzu x14, s4 -; NONEON-NOSVE-NEXT: fcvtzu x12, s3 -; NONEON-NOSVE-NEXT: mov v7.d[1], x11 -; NONEON-NOSVE-NEXT: fmov d3, x10 -; NONEON-NOSVE-NEXT: fcvtzu x11, s5 -; NONEON-NOSVE-NEXT: fmov d2, x15 -; NONEON-NOSVE-NEXT: stp q16, q1, [x1, #64] -; NONEON-NOSVE-NEXT: fmov d1, x9 -; NONEON-NOSVE-NEXT: fmov d4, x8 -; NONEON-NOSVE-NEXT: stp q7, q0, [x1] -; NONEON-NOSVE-NEXT: mov v2.d[1], x13 -; NONEON-NOSVE-NEXT: mov v3.d[1], x14 -; NONEON-NOSVE-NEXT: mov v1.d[1], x12 -; NONEON-NOSVE-NEXT: mov v4.d[1], x11 -; NONEON-NOSVE-NEXT: stp q3, q2, [x1, #96] -; NONEON-NOSVE-NEXT: stp q4, q1, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %res = fptoui <16 x half> %op1 to <16 x i64> store <16 x i64> %res, ptr %b @@ -528,11 +282,6 @@ define <2 x i16> @fcvtzu_v2f32_v2i16(<2 x float> %op1) { ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v2f32_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzs v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = fptoui <2 x float> %op1 to <2 x i16> ret <2 x i16> %res } @@ -546,12 +295,6 @@ define <4 x i16> @fcvtzu_v4f32_v4i16(<4 x float> %op1) { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v4f32_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzu v0.4s, v0.4s -; NONEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fptoui <4 x float> %op1 to <4 x i16> ret <4 x i16> %res } @@ -569,14 +312,6 @@ define <8 x i16> @fcvtzu_v8f32_v8i16(ptr %a) { ; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v8f32_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtzu v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtzu v0.4s, v0.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %res = fptoui <8 x float> %op1 to <8 x i16> ret <8 x i16> %res @@ -601,19 +336,6 @@ define void @fcvtzu_v16f32_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h ; CHECK-NEXT: stp q2, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v16f32_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: fcvtzu v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtzu v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzu v3.4s, v3.4s -; NONEON-NOSVE-NEXT: fcvtzu v2.4s, v2.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x float>, ptr %a %res = fptoui <16 x float> %op1 to <16 x i16> store <16 x i16> %res, ptr %b @@ -632,11 +354,6 @@ define <2 x i32> @fcvtzu_v2f32_v2i32(<2 x float> %op1) { ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v2f32_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzu v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = fptoui <2 x float> %op1 to <2 x i32> ret <2 x i32> %res } @@ -649,11 +366,6 @@ define <4 x i32> @fcvtzu_v4f32_v4i32(<4 x float> %op1) { ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v4f32_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzu v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fptoui <4 x float> %op1 to <4 x i32> ret <4 x i32> %res } @@ -667,14 +379,6 @@ define void @fcvtzu_v8f32_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v8f32_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtzu v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzu v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %res = fptoui <8 x float> %op1 to <8 x i32> store <8 x i32> %res, ptr %b @@ -694,13 +398,6 @@ define <1 x i64> @fcvtzu_v1f32_v1i64(<1 x float> %op1) { ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v1f32_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtzu v0.2d, v0.2d -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = fptoui <1 x float> %op1 to <1 x i64> ret <1 x i64> %res } @@ -714,12 +411,6 @@ define <2 x i64> @fcvtzu_v2f32_v2i64(<2 x float> %op1) { ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v2f32_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtzu v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = fptoui <2 x float> %op1 to <2 x i64> ret <2 x i64> %res } @@ -736,20 +427,6 @@ define void @fcvtzu_v4f32_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v4f32_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtl v1.2d, v1.2s -; NONEON-NOSVE-NEXT: fcvtzu v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtzu v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x float>, ptr %a %res = fptoui <4 x float> %op1 to <4 x i64> store <4 x i64> %res, ptr %b @@ -774,26 +451,6 @@ define void @fcvtzu_v8f32_v8i64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v8f32_v8i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v1.2d, v1.2s -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtl v2.2d, v2.2s -; NONEON-NOSVE-NEXT: fcvtl v3.2d, v3.2s -; NONEON-NOSVE-NEXT: fcvtzu v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtzu v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtzu v2.2d, v2.2d -; NONEON-NOSVE-NEXT: fcvtzu v3.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %res = fptoui <8 x float> %op1 to <8 x i64> store <8 x i64> %res, ptr %b @@ -811,12 +468,6 @@ define <1 x i16> @fcvtzu_v1f64_v1i16(<1 x double> %op1) { ; CHECK-NEXT: mov z0.h, w8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v1f64_v1i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzs w8, d0 -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: ret %res = fptoui <1 x double> %op1 to <1 x i16> ret <1 x i16> %res } @@ -830,12 +481,6 @@ define <2 x i16> @fcvtzu_v2f64_v2i16(<2 x double> %op1) { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v2f64_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: xtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: ret %res = fptoui <2 x double> %op1 to <2 x i16> ret <2 x i16> %res } @@ -864,15 +509,6 @@ define <4 x i16> @fcvtzu_v4f64_v4i16(ptr %a) { ; CHECK-NEXT: ldr d0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v4f64_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtzs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %res = fptoui <4 x double> %op1 to <4 x i16> ret <4 x i16> %res @@ -916,23 +552,6 @@ define <8 x i16> @fcvtzu_v8f64_v8i16(ptr %a) { ; CHECK-NEXT: strh w8, [sp, #2] ; CHECK-NEXT: ldr q0, [sp], #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v8f64_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #32] -; NONEON-NOSVE-NEXT: adrp x8, .LCPI26_0 -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtzs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtzs v2.2d, v2.2d -; NONEON-NOSVE-NEXT: fcvtzs v3.2d, v3.2d -; NONEON-NOSVE-NEXT: xtn v7.2s, v0.2d -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI26_0] -; NONEON-NOSVE-NEXT: xtn v6.2s, v1.2d -; NONEON-NOSVE-NEXT: xtn v5.2s, v2.2d -; NONEON-NOSVE-NEXT: xtn v4.2s, v3.2d -; NONEON-NOSVE-NEXT: tbl v0.16b, { v4.16b, v5.16b, v6.16b, v7.16b }, v0.16b -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x double>, ptr %a %res = fptoui <8 x double> %op1 to <8 x i16> ret <8 x i16> %res @@ -1009,35 +628,6 @@ define void @fcvtzu_v16f64_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v16f64_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #96] -; NONEON-NOSVE-NEXT: adrp x8, .LCPI27_0 -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q4, q5, [x0, #64] -; NONEON-NOSVE-NEXT: ldp q7, q6, [x0] -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtzs v3.2d, v3.2d -; NONEON-NOSVE-NEXT: fcvtzs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtzs v2.2d, v2.2d -; NONEON-NOSVE-NEXT: fcvtzs v5.2d, v5.2d -; NONEON-NOSVE-NEXT: fcvtzs v4.2d, v4.2d -; NONEON-NOSVE-NEXT: fcvtzs v6.2d, v6.2d -; NONEON-NOSVE-NEXT: fcvtzs v7.2d, v7.2d -; NONEON-NOSVE-NEXT: xtn v19.2s, v0.2d -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI27_0] -; NONEON-NOSVE-NEXT: xtn v23.2s, v3.2d -; NONEON-NOSVE-NEXT: xtn v18.2s, v1.2d -; NONEON-NOSVE-NEXT: xtn v22.2s, v2.2d -; NONEON-NOSVE-NEXT: xtn v17.2s, v5.2d -; NONEON-NOSVE-NEXT: xtn v21.2s, v6.2d -; NONEON-NOSVE-NEXT: xtn v16.2s, v4.2d -; NONEON-NOSVE-NEXT: xtn v20.2s, v7.2d -; NONEON-NOSVE-NEXT: tbl v1.16b, { v16.16b, v17.16b, v18.16b, v19.16b }, v0.16b -; NONEON-NOSVE-NEXT: tbl v0.16b, { v20.16b, v21.16b, v22.16b, v23.16b }, v0.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x double>, ptr %a %res = fptoui <16 x double> %op1 to <16 x i16> store <16 x i16> %res, ptr %b @@ -1057,13 +647,6 @@ define <1 x i32> @fcvtzu_v1f64_v1i32(<1 x double> %op1) { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v1f64_v1i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fcvtzu v0.2d, v0.2d -; NONEON-NOSVE-NEXT: xtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: ret %res = fptoui <1 x double> %op1 to <1 x i32> ret <1 x i32> %res } @@ -1077,12 +660,6 @@ define <2 x i32> @fcvtzu_v2f64_v2i32(<2 x double> %op1) { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v2f64_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzu v0.2d, v0.2d -; NONEON-NOSVE-NEXT: xtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: ret %res = fptoui <2 x double> %op1 to <2 x i32> ret <2 x i32> %res } @@ -1100,14 +677,6 @@ define <4 x i32> @fcvtzu_v4f64_v4i32(ptr %a) { ; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v4f64_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtzu v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtzu v0.2d, v0.2d -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %res = fptoui <4 x double> %op1 to <4 x i32> ret <4 x i32> %res @@ -1132,19 +701,6 @@ define void @fcvtzu_v8f64_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s ; CHECK-NEXT: stp q2, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v8f64_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: fcvtzu v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtzu v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtzu v3.2d, v3.2d -; NONEON-NOSVE-NEXT: fcvtzu v2.2d, v2.2d -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: uzp1 v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x double>, ptr %a %res = fptoui <8 x double> %op1 to <8 x i32> store <8 x i32> %res, ptr %b @@ -1163,12 +719,6 @@ define <1 x i64> @fcvtzu_v1f64_v1i64(<1 x double> %op1) { ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v1f64_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzu x8, d0 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %res = fptoui <1 x double> %op1 to <1 x i64> ret <1 x i64> %res } @@ -1181,11 +731,6 @@ define <2 x i64> @fcvtzu_v2f64_v2i64(<2 x double> %op1) { ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v2f64_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzu v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = fptoui <2 x double> %op1 to <2 x i64> ret <2 x i64> %res } @@ -1199,14 +744,6 @@ define void @fcvtzu_v4f64_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzu_v4f64_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtzu v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtzu v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %res = fptoui <4 x double> %op1 to <4 x i64> store <4 x i64> %res, ptr %b @@ -1225,13 +762,6 @@ define <4 x i16> @fcvtzs_v4f16_v4i16(<4 x half> %op1) { ; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v4f16_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fptosi <4 x half> %op1 to <4 x i16> ret <4 x i16> %res } @@ -1244,21 +774,6 @@ define void @fcvtzs_v8f16_v8i16(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v8f16_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzs v1.4s, v1.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x half>, ptr %a %res = fptosi <8 x half> %op1 to <8 x i16> store <8 x i16> %res, ptr %b @@ -1274,27 +789,6 @@ define void @fcvtzs_v16f16_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzs z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v16f16_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v3.4h -; NONEON-NOSVE-NEXT: fcvtzs v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzs v2.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtzs v3.4s, v3.4s -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v1.8h, v2.8h -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %res = fptosi <16 x half> %op1 to <16 x i16> store <16 x i16> %res, ptr %b @@ -1314,13 +808,6 @@ define <2 x i32> @fcvtzs_v2f16_v2i32(<2 x half> %op1) { ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v2f16_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = fptosi <2 x half> %op1 to <2 x i32> ret <2 x i32> %res } @@ -1334,12 +821,6 @@ define <4 x i32> @fcvtzs_v4f16_v4i32(<4 x half> %op1) { ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v4f16_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fptosi <4 x half> %op1 to <4 x i32> ret <4 x i32> %res } @@ -1356,20 +837,6 @@ define void @fcvtzs_v8f16_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v8f16_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzs v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x half>, ptr %a %res = fptosi <8 x half> %op1 to <8 x i32> store <8 x i32> %res, ptr %b @@ -1394,26 +861,6 @@ define void @fcvtzs_v16f16_v16i32(ptr %a, ptr %b) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v16f16_v16i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v3.4h -; NONEON-NOSVE-NEXT: fcvtzs v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzs v2.4s, v2.4s -; NONEON-NOSVE-NEXT: fcvtzs v3.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %res = fptosi <16 x half> %op1 to <16 x i32> store <16 x i32> %res, ptr %b @@ -1430,13 +877,6 @@ define <1 x i64> @fcvtzs_v1f16_v1i64(<1 x half> %op1) { ; CHECK-NEXT: fcvtzs x8, h0 ; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v1f16_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvtzs x8, s0 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %res = fptosi <1 x half> %op1 to <1 x i64> ret <1 x i64> %res } @@ -1453,18 +893,6 @@ define <2 x i64> @fcvtzs_v2f16_v2i64(<2 x half> %op1) { ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: ldr q0, [sp], #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v2f16_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov h1, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvtzs x8, s0 -; NONEON-NOSVE-NEXT: fcvtzs x9, s1 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: mov v0.d[1], x9 -; NONEON-NOSVE-NEXT: ret %res = fptosi <2 x half> %op1 to <2 x i64> ret <2 x i64> %res } @@ -1487,27 +915,6 @@ define void @fcvtzs_v4f16_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v4f16_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: mov h1, v0.h[2] -; NONEON-NOSVE-NEXT: mov h2, v0.h[3] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvtzs x9, s0 -; NONEON-NOSVE-NEXT: fcvtzs x8, s1 -; NONEON-NOSVE-NEXT: fcvtzs x10, s2 -; NONEON-NOSVE-NEXT: fcvtzs x11, s3 -; NONEON-NOSVE-NEXT: fmov d1, x9 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: mov v1.d[1], x11 -; NONEON-NOSVE-NEXT: mov v0.d[1], x10 -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x half>, ptr %a %res = fptosi <4 x half> %op1 to <4 x i64> store <4 x i64> %res, ptr %b @@ -1545,47 +952,6 @@ define void @fcvtzs_v8f16_v8i64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q1, q0, [x1, #32] ; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v8f16_v8i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: mov h1, v0.h[2] -; NONEON-NOSVE-NEXT: mov h3, v0.h[3] -; NONEON-NOSVE-NEXT: mov h4, v0.h[1] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: mov h5, v2.h[2] -; NONEON-NOSVE-NEXT: mov h6, v2.h[3] -; NONEON-NOSVE-NEXT: mov h7, v2.h[1] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvtzs x9, s0 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvtzs x13, s2 -; NONEON-NOSVE-NEXT: fcvtzs x8, s1 -; NONEON-NOSVE-NEXT: fcvt s1, h7 -; NONEON-NOSVE-NEXT: fcvtzs x10, s3 -; NONEON-NOSVE-NEXT: fcvtzs x11, s4 -; NONEON-NOSVE-NEXT: fcvtzs x12, s5 -; NONEON-NOSVE-NEXT: fcvtzs x14, s6 -; NONEON-NOSVE-NEXT: fmov d3, x13 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: fcvtzs x8, s1 -; NONEON-NOSVE-NEXT: fmov d1, x9 -; NONEON-NOSVE-NEXT: fmov d2, x12 -; NONEON-NOSVE-NEXT: mov v0.d[1], x10 -; NONEON-NOSVE-NEXT: mov v1.d[1], x11 -; NONEON-NOSVE-NEXT: mov v3.d[1], x8 -; NONEON-NOSVE-NEXT: mov v2.d[1], x14 -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: stp q3, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x half>, ptr %a %res = fptosi <8 x half> %op1 to <8 x i64> store <8 x i64> %res, ptr %b @@ -1646,80 +1012,6 @@ define void @fcvtzs_v16f16_v16i64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q5, q2, [x1, #96] ; CHECK-NEXT: add sp, sp, #128 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v16f16_v16i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: mov h2, v1.h[2] -; NONEON-NOSVE-NEXT: fcvt s3, h1 -; NONEON-NOSVE-NEXT: ldr d4, [sp, #24] -; NONEON-NOSVE-NEXT: mov h5, v1.h[3] -; NONEON-NOSVE-NEXT: mov h7, v0.h[2] -; NONEON-NOSVE-NEXT: mov h16, v0.h[3] -; NONEON-NOSVE-NEXT: fcvt s6, h0 -; NONEON-NOSVE-NEXT: mov h0, v0.h[1] -; NONEON-NOSVE-NEXT: mov h1, v1.h[1] -; NONEON-NOSVE-NEXT: fcvt s17, h4 -; NONEON-NOSVE-NEXT: mov h18, v4.h[2] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvtzs x8, s3 -; NONEON-NOSVE-NEXT: fcvt s3, h5 -; NONEON-NOSVE-NEXT: fcvt s5, h7 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: mov h16, v4.h[3] -; NONEON-NOSVE-NEXT: fcvtzs x9, s6 -; NONEON-NOSVE-NEXT: ldr d6, [sp, #8] -; NONEON-NOSVE-NEXT: fcvt s0, h0 -; NONEON-NOSVE-NEXT: fcvt s1, h1 -; NONEON-NOSVE-NEXT: mov h4, v4.h[1] -; NONEON-NOSVE-NEXT: fcvtzs x11, s2 -; NONEON-NOSVE-NEXT: mov h2, v6.h[2] -; NONEON-NOSVE-NEXT: fcvtzs x10, s17 -; NONEON-NOSVE-NEXT: fcvtzs x13, s5 -; NONEON-NOSVE-NEXT: fcvtzs x12, s3 -; NONEON-NOSVE-NEXT: mov h3, v6.h[3] -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: mov h5, v6.h[1] -; NONEON-NOSVE-NEXT: fcvt s17, h18 -; NONEON-NOSVE-NEXT: fcvtzs x14, s7 -; NONEON-NOSVE-NEXT: fmov d7, x8 -; NONEON-NOSVE-NEXT: fcvtzs x8, s0 -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fmov d0, x11 -; NONEON-NOSVE-NEXT: fcvtzs x11, s1 -; NONEON-NOSVE-NEXT: fmov d1, x13 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvtzs x13, s16 -; NONEON-NOSVE-NEXT: fmov d16, x9 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvtzs x15, s17 -; NONEON-NOSVE-NEXT: mov v0.d[1], x12 -; NONEON-NOSVE-NEXT: mov v1.d[1], x14 -; NONEON-NOSVE-NEXT: fcvtzs x9, s2 -; NONEON-NOSVE-NEXT: mov v16.d[1], x8 -; NONEON-NOSVE-NEXT: fcvtzs x8, s6 -; NONEON-NOSVE-NEXT: fcvtzs x14, s4 -; NONEON-NOSVE-NEXT: fcvtzs x12, s3 -; NONEON-NOSVE-NEXT: mov v7.d[1], x11 -; NONEON-NOSVE-NEXT: fmov d3, x10 -; NONEON-NOSVE-NEXT: fcvtzs x11, s5 -; NONEON-NOSVE-NEXT: fmov d2, x15 -; NONEON-NOSVE-NEXT: stp q16, q1, [x1, #64] -; NONEON-NOSVE-NEXT: fmov d1, x9 -; NONEON-NOSVE-NEXT: fmov d4, x8 -; NONEON-NOSVE-NEXT: stp q7, q0, [x1] -; NONEON-NOSVE-NEXT: mov v2.d[1], x13 -; NONEON-NOSVE-NEXT: mov v3.d[1], x14 -; NONEON-NOSVE-NEXT: mov v1.d[1], x12 -; NONEON-NOSVE-NEXT: mov v4.d[1], x11 -; NONEON-NOSVE-NEXT: stp q3, q2, [x1, #96] -; NONEON-NOSVE-NEXT: stp q4, q1, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %res = fptosi <16 x half> %op1 to <16 x i64> store <16 x i64> %res, ptr %b @@ -1738,11 +1030,6 @@ define <2 x i16> @fcvtzs_v2f32_v2i16(<2 x float> %op1) { ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v2f32_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzs v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = fptosi <2 x float> %op1 to <2 x i16> ret <2 x i16> %res } @@ -1756,12 +1043,6 @@ define <4 x i16> @fcvtzs_v4f32_v4i16(<4 x float> %op1) { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v4f32_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fptosi <4 x float> %op1 to <4 x i16> ret <4 x i16> %res } @@ -1779,14 +1060,6 @@ define <8 x i16> @fcvtzs_v8f32_v8i16(ptr %a) { ; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v8f32_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtzs v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %res = fptosi <8 x float> %op1 to <8 x i16> ret <8 x i16> %res @@ -1811,19 +1084,6 @@ define void @fcvtzs_v16f32_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h ; CHECK-NEXT: stp q2, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v16f32_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: fcvtzs v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzs v3.4s, v3.4s -; NONEON-NOSVE-NEXT: fcvtzs v2.4s, v2.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x float>, ptr %a %res = fptosi <16 x float> %op1 to <16 x i16> store <16 x i16> %res, ptr %b @@ -1842,11 +1102,6 @@ define <2 x i32> @fcvtzs_v2f32_v2i32(<2 x float> %op1) { ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v2f32_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzs v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = fptosi <2 x float> %op1 to <2 x i32> ret <2 x i32> %res } @@ -1859,11 +1114,6 @@ define <4 x i32> @fcvtzs_v4f32_v4i32(<4 x float> %op1) { ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v4f32_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = fptosi <4 x float> %op1 to <4 x i32> ret <4 x i32> %res } @@ -1877,14 +1127,6 @@ define void @fcvtzs_v8f32_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v8f32_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtzs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtzs v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %res = fptosi <8 x float> %op1 to <8 x i32> store <8 x i32> %res, ptr %b @@ -1904,13 +1146,6 @@ define <1 x i64> @fcvtzs_v1f32_v1i64(<1 x float> %op1) { ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v1f32_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = fptosi <1 x float> %op1 to <1 x i64> ret <1 x i64> %res } @@ -1924,12 +1159,6 @@ define <2 x i64> @fcvtzs_v2f32_v2i64(<2 x float> %op1) { ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v2f32_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = fptosi <2 x float> %op1 to <2 x i64> ret <2 x i64> %res } @@ -1946,20 +1175,6 @@ define void @fcvtzs_v4f32_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v4f32_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtl v1.2d, v1.2s -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtzs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x float>, ptr %a %res = fptosi <4 x float> %op1 to <4 x i64> store <4 x i64> %res, ptr %b @@ -1984,26 +1199,6 @@ define void @fcvtzs_v8f32_v8i64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v8f32_v8i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: fcvtl v1.2d, v1.2s -; NONEON-NOSVE-NEXT: fcvtl v0.2d, v0.2s -; NONEON-NOSVE-NEXT: fcvtl v2.2d, v2.2s -; NONEON-NOSVE-NEXT: fcvtl v3.2d, v3.2s -; NONEON-NOSVE-NEXT: fcvtzs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtzs v2.2d, v2.2d -; NONEON-NOSVE-NEXT: fcvtzs v3.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %res = fptosi <8 x float> %op1 to <8 x i64> store <8 x i64> %res, ptr %b @@ -2023,12 +1218,6 @@ define <1 x i16> @fcvtzs_v1f64_v1i16(<1 x double> %op1) { ; CHECK-NEXT: mov z0.h, w8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v1f64_v1i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzs w8, d0 -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: ret %res = fptosi <1 x double> %op1 to <1 x i16> ret <1 x i16> %res } @@ -2042,12 +1231,6 @@ define <2 x i16> @fcvtzs_v2f64_v2i16(<2 x double> %op1) { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v2f64_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: xtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: ret %res = fptosi <2 x double> %op1 to <2 x i16> ret <2 x i16> %res } @@ -2076,15 +1259,6 @@ define <4 x i16> @fcvtzs_v4f64_v4i16(ptr %a) { ; CHECK-NEXT: ldr d0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v4f64_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtzs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %res = fptosi <4 x double> %op1 to <4 x i16> ret <4 x i16> %res @@ -2128,23 +1302,6 @@ define <8 x i16> @fcvtzs_v8f64_v8i16(ptr %a) { ; CHECK-NEXT: strh w8, [sp, #2] ; CHECK-NEXT: ldr q0, [sp], #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v8f64_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #32] -; NONEON-NOSVE-NEXT: adrp x8, .LCPI61_0 -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtzs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtzs v2.2d, v2.2d -; NONEON-NOSVE-NEXT: fcvtzs v3.2d, v3.2d -; NONEON-NOSVE-NEXT: xtn v7.2s, v0.2d -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI61_0] -; NONEON-NOSVE-NEXT: xtn v6.2s, v1.2d -; NONEON-NOSVE-NEXT: xtn v5.2s, v2.2d -; NONEON-NOSVE-NEXT: xtn v4.2s, v3.2d -; NONEON-NOSVE-NEXT: tbl v0.16b, { v4.16b, v5.16b, v6.16b, v7.16b }, v0.16b -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x double>, ptr %a %res = fptosi <8 x double> %op1 to <8 x i16> ret <8 x i16> %res @@ -2221,35 +1378,6 @@ define void @fcvtzs_v16f64_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v16f64_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #96] -; NONEON-NOSVE-NEXT: adrp x8, .LCPI62_0 -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q4, q5, [x0, #64] -; NONEON-NOSVE-NEXT: ldp q7, q6, [x0] -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtzs v3.2d, v3.2d -; NONEON-NOSVE-NEXT: fcvtzs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtzs v2.2d, v2.2d -; NONEON-NOSVE-NEXT: fcvtzs v5.2d, v5.2d -; NONEON-NOSVE-NEXT: fcvtzs v4.2d, v4.2d -; NONEON-NOSVE-NEXT: fcvtzs v6.2d, v6.2d -; NONEON-NOSVE-NEXT: fcvtzs v7.2d, v7.2d -; NONEON-NOSVE-NEXT: xtn v19.2s, v0.2d -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI62_0] -; NONEON-NOSVE-NEXT: xtn v23.2s, v3.2d -; NONEON-NOSVE-NEXT: xtn v18.2s, v1.2d -; NONEON-NOSVE-NEXT: xtn v22.2s, v2.2d -; NONEON-NOSVE-NEXT: xtn v17.2s, v5.2d -; NONEON-NOSVE-NEXT: xtn v21.2s, v6.2d -; NONEON-NOSVE-NEXT: xtn v16.2s, v4.2d -; NONEON-NOSVE-NEXT: xtn v20.2s, v7.2d -; NONEON-NOSVE-NEXT: tbl v1.16b, { v16.16b, v17.16b, v18.16b, v19.16b }, v0.16b -; NONEON-NOSVE-NEXT: tbl v0.16b, { v20.16b, v21.16b, v22.16b, v23.16b }, v0.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x double>, ptr %a %res = fptosi <16 x double> %op1 to <16 x i16> store <16 x i16> %res, ptr %b @@ -2269,13 +1397,6 @@ define <1 x i32> @fcvtzs_v1f64_v1i32(<1 x double> %op1) { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v1f64_v1i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: xtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: ret %res = fptosi <1 x double> %op1 to <1 x i32> ret <1 x i32> %res } @@ -2289,12 +1410,6 @@ define <2 x i32> @fcvtzs_v2f64_v2i32(<2 x double> %op1) { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v2f64_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: xtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: ret %res = fptosi <2 x double> %op1 to <2 x i32> ret <2 x i32> %res } @@ -2312,14 +1427,6 @@ define <4 x i32> @fcvtzs_v4f64_v4i32(ptr %a) { ; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v4f64_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtzs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %res = fptosi <4 x double> %op1 to <4 x i32> ret <4 x i32> %res @@ -2344,19 +1451,6 @@ define void @fcvtzs_v8f64_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s ; CHECK-NEXT: stp q2, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v8f64_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: fcvtzs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtzs v3.2d, v3.2d -; NONEON-NOSVE-NEXT: fcvtzs v2.2d, v2.2d -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: uzp1 v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x double>, ptr %a %res = fptosi <8 x double> %op1 to <8 x i32> store <8 x i32> %res, ptr %b @@ -2375,12 +1469,6 @@ define <1 x i64> @fcvtzs_v1f64_v1i64(<1 x double> %op1) { ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v1f64_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzs x8, d0 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %res = fptosi <1 x double> %op1 to <1 x i64> ret <1 x i64> %res } @@ -2393,11 +1481,6 @@ define <2 x i64> @fcvtzs_v2f64_v2i64(<2 x double> %op1) { ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v2f64_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = fptosi <2 x double> %op1 to <2 x i64> ret <2 x i64> %res } @@ -2411,14 +1494,6 @@ define void @fcvtzs_v4f64_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fcvtzs_v4f64_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fcvtzs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtzs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %res = fptosi <4 x double> %op1 to <4 x i64> store <4 x i64> %res, ptr %b diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll index 32fe74bbb65f..30a4f04a3d2b 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -28,14 +27,6 @@ define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, <2 x i1> %mask ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: uzp1 v2.4h, v2.4h, v0.4h -; NONEON-NOSVE-NEXT: shl v2.4h, v2.4h, #15 -; NONEON-NOSVE-NEXT: cmlt v2.4h, v2.4h, #0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select <2 x i1> %mask, <2 x half> %op1, <2 x half> %op2 ret <2 x half> %sel } @@ -54,13 +45,6 @@ define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x i1> %mask ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v2.4h, v2.4h, #15 -; NONEON-NOSVE-NEXT: cmlt v2.4h, v2.4h, #0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select <4 x i1> %mask, <4 x half> %op1, <4 x half> %op2 ret <4 x half> %sel } @@ -80,14 +64,6 @@ define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x i1> %mask ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v2.8h, v2.8b, #0 -; NONEON-NOSVE-NEXT: shl v2.8h, v2.8h, #15 -; NONEON-NOSVE-NEXT: cmlt v2.8h, v2.8h, #0 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select <8 x i1> %mask, <8 x half> %op1, <8 x half> %op2 ret <8 x half> %sel } @@ -104,126 +80,6 @@ define void @select_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: sel z1.h, p0, z2.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: mov h2, v1.h[1] -; NONEON-NOSVE-NEXT: mov h3, v0.h[1] -; NONEON-NOSVE-NEXT: mov h4, v1.h[2] -; NONEON-NOSVE-NEXT: mov h5, v0.h[2] -; NONEON-NOSVE-NEXT: fcvt s6, h1 -; NONEON-NOSVE-NEXT: fcvt s7, h0 -; NONEON-NOSVE-NEXT: mov h16, v1.h[6] -; NONEON-NOSVE-NEXT: mov h17, v0.h[6] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: fcmp s3, s2 -; NONEON-NOSVE-NEXT: mov h2, v1.h[3] -; NONEON-NOSVE-NEXT: mov h3, v0.h[3] -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[4] -; NONEON-NOSVE-NEXT: mov h7, v0.h[4] -; NONEON-NOSVE-NEXT: fcvt s2, h2 -; NONEON-NOSVE-NEXT: fcvt s3, h3 -; NONEON-NOSVE-NEXT: csetm w14, eq -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v1.h[5] -; NONEON-NOSVE-NEXT: mov h5, v0.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w12, eq -; NONEON-NOSVE-NEXT: fcmp s3, s2 -; NONEON-NOSVE-NEXT: ldr q2, [x0, #16] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: ldr q3, [x1, #16] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w11, eq -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v1.h[7] -; NONEON-NOSVE-NEXT: mov h7, v0.h[7] -; NONEON-NOSVE-NEXT: mov h18, v3.h[3] -; NONEON-NOSVE-NEXT: csetm w13, eq -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: mov h4, v3.h[1] -; NONEON-NOSVE-NEXT: mov h5, v2.h[1] -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: csetm w9, eq -; NONEON-NOSVE-NEXT: fcmp s17, s16 -; NONEON-NOSVE-NEXT: mov h16, v3.h[2] -; NONEON-NOSVE-NEXT: fcvt s4, h4 -; NONEON-NOSVE-NEXT: mov h17, v2.h[2] -; NONEON-NOSVE-NEXT: fcvt s5, h5 -; NONEON-NOSVE-NEXT: csetm w10, eq -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: fcvt s6, h3 -; NONEON-NOSVE-NEXT: fcvt s7, h2 -; NONEON-NOSVE-NEXT: csetm w15, eq -; NONEON-NOSVE-NEXT: fcmp s5, s4 -; NONEON-NOSVE-NEXT: fmov s4, w14 -; NONEON-NOSVE-NEXT: csetm w16, eq -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v2.h[3] -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: fcvt s16, h17 -; NONEON-NOSVE-NEXT: mov v4.h[1], w8 -; NONEON-NOSVE-NEXT: fcvt s17, h18 -; NONEON-NOSVE-NEXT: csetm w14, eq -; NONEON-NOSVE-NEXT: fmov s5, w14 -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcmp s16, s7 -; NONEON-NOSVE-NEXT: mov h7, v3.h[4] -; NONEON-NOSVE-NEXT: mov h16, v2.h[4] -; NONEON-NOSVE-NEXT: mov v4.h[2], w12 -; NONEON-NOSVE-NEXT: mov v5.h[1], w16 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s6, s17 -; NONEON-NOSVE-NEXT: mov h17, v2.h[5] -; NONEON-NOSVE-NEXT: fcvt s6, h7 -; NONEON-NOSVE-NEXT: fcvt s7, h16 -; NONEON-NOSVE-NEXT: mov h16, v3.h[5] -; NONEON-NOSVE-NEXT: mov v4.h[3], w11 -; NONEON-NOSVE-NEXT: mov v5.h[2], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcvt s17, h17 -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov h6, v3.h[6] -; NONEON-NOSVE-NEXT: mov h7, v2.h[6] -; NONEON-NOSVE-NEXT: fcvt s16, h16 -; NONEON-NOSVE-NEXT: mov v4.h[4], w13 -; NONEON-NOSVE-NEXT: mov v5.h[3], w8 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcvt s6, h6 -; NONEON-NOSVE-NEXT: fcvt s7, h7 -; NONEON-NOSVE-NEXT: fcmp s17, s16 -; NONEON-NOSVE-NEXT: mov h16, v3.h[7] -; NONEON-NOSVE-NEXT: mov h17, v2.h[7] -; NONEON-NOSVE-NEXT: mov v5.h[4], w8 -; NONEON-NOSVE-NEXT: mov v4.h[5], w9 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: fcvt s6, h16 -; NONEON-NOSVE-NEXT: fcvt s7, h17 -; NONEON-NOSVE-NEXT: mov v5.h[5], w8 -; NONEON-NOSVE-NEXT: mov v4.h[6], w10 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: fcmp s7, s6 -; NONEON-NOSVE-NEXT: mov v5.h[6], w8 -; NONEON-NOSVE-NEXT: mov v4.h[7], w15 -; NONEON-NOSVE-NEXT: csetm w8, eq -; NONEON-NOSVE-NEXT: mov v5.h[7], w8 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v4.16b -; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b -; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %mask = fcmp oeq <16 x half> %op1, %op2 @@ -246,13 +102,6 @@ define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x i1> %m ; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v2.2s, v2.2s, #31 -; NONEON-NOSVE-NEXT: cmlt v2.2s, v2.2s, #0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select <2 x i1> %mask, <2 x float> %op1, <2 x float> %op2 ret <2 x float> %sel } @@ -272,14 +121,6 @@ define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x i1> %m ; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: shl v2.4s, v2.4s, #31 -; NONEON-NOSVE-NEXT: cmlt v2.4s, v2.4s, #0 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select <4 x i1> %mask, <4 x float> %op1, <4 x float> %op2 ret <4 x float> %sel } @@ -296,18 +137,6 @@ define void @select_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: sel z1.s, p0, z2.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x1] -; NONEON-NOSVE-NEXT: fcmeq v4.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcmeq v5.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v4.16b -; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b -; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %mask = fcmp oeq <8 x float> %op1, %op2 @@ -322,14 +151,6 @@ define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1> ; CHECK-NEXT: tst w0, #0x1 ; CHECK-NEXT: fcsel d0, d0, d1, ne ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm x8, ne -; NONEON-NOSVE-NEXT: fmov d2, x8 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select <1 x i1> %mask, <1 x double> %op1, <1 x double> %op2 ret <1 x double> %sel } @@ -349,14 +170,6 @@ define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x i1> ; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: shl v2.2d, v2.2d, #63 -; NONEON-NOSVE-NEXT: cmlt v2.2d, v2.2d, #0 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select <2 x i1> %mask, <2 x double> %op1, <2 x double> %op2 ret <2 x double> %sel } @@ -373,18 +186,6 @@ define void @select_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: sel z1.d, p0, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x1] -; NONEON-NOSVE-NEXT: fcmeq v4.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: fcmeq v5.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v4.16b -; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b -; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %mask = fcmp oeq <4 x double> %op1, %op2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll index c85048ab72e0..4aa965777c74 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -22,14 +21,6 @@ define <4 x i8> @insertelement_v4i8(<4 x i8> %op1) { ; CHECK-NEXT: mov z0.h, p0/m, w8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v0.h[3], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %r = insertelement <4 x i8> %op1, i8 5, i64 3 ret <4 x i8> %r } @@ -47,14 +38,6 @@ define <8 x i8> @insertelement_v8i8(<8 x i8> %op1) { ; CHECK-NEXT: mov z0.b, p0/m, w8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v0.b[7], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %r = insertelement <8 x i8> %op1, i8 5, i64 7 ret <8 x i8> %r } @@ -72,12 +55,6 @@ define <16 x i8> @insertelement_v16i8(<16 x i8> %op1) { ; CHECK-NEXT: mov z0.b, p0/m, w8 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v0.b[15], w8 -; NONEON-NOSVE-NEXT: ret %r = insertelement <16 x i8> %op1, i8 5, i64 15 ret <16 x i8> %r } @@ -95,12 +72,6 @@ define <32 x i8> @insertelement_v32i8(<32 x i8> %op1) { ; CHECK-NEXT: mov z1.b, p0/m, w8 ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v1.b[15], w8 -; NONEON-NOSVE-NEXT: ret %r = insertelement <32 x i8> %op1, i8 5, i64 31 ret <32 x i8> %r } @@ -119,14 +90,6 @@ define <2 x i16> @insertelement_v2i16(<2 x i16> %op1) { ; CHECK-NEXT: mov z0.s, p0/m, w8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v0.s[1], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %r = insertelement <2 x i16> %op1, i16 5, i64 1 ret <2 x i16> %r } @@ -144,14 +107,6 @@ define <4 x i16> @insertelement_v4i16(<4 x i16> %op1) { ; CHECK-NEXT: mov z0.h, p0/m, w8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v0.h[3], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %r = insertelement <4 x i16> %op1, i16 5, i64 3 ret <4 x i16> %r } @@ -169,12 +124,6 @@ define <8 x i16> @insertelement_v8i16(<8 x i16> %op1) { ; CHECK-NEXT: mov z0.h, p0/m, w8 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v0.h[7], w8 -; NONEON-NOSVE-NEXT: ret %r = insertelement <8 x i16> %op1, i16 5, i64 7 ret <8 x i16> %r } @@ -192,12 +141,6 @@ define <16 x i16> @insertelement_v16i16(<16 x i16> %op1) { ; CHECK-NEXT: mov z1.h, p0/m, w8 ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v1.h[7], w8 -; NONEON-NOSVE-NEXT: ret %r = insertelement <16 x i16> %op1, i16 5, i64 15 ret <16 x i16> %r } @@ -216,14 +159,6 @@ define <2 x i32> @insertelement_v2i32(<2 x i32> %op1) { ; CHECK-NEXT: mov z0.s, p0/m, w8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v0.s[1], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %r = insertelement <2 x i32> %op1, i32 5, i64 1 ret <2 x i32> %r } @@ -241,12 +176,6 @@ define <4 x i32> @insertelement_v4i32(<4 x i32> %op1) { ; CHECK-NEXT: mov z0.s, p0/m, w8 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v0.s[3], w8 -; NONEON-NOSVE-NEXT: ret %r = insertelement <4 x i32> %op1, i32 5, i64 3 ret <4 x i32> %r } @@ -264,13 +193,6 @@ define <8 x i32> @insertelement_v8i32(ptr %a) { ; CHECK-NEXT: mov z1.s, p0/m, w8 ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v1.s[3], w8 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %r = insertelement <8 x i32> %op1, i32 5, i64 7 ret <8 x i32> %r @@ -283,12 +205,6 @@ define <1 x i64> @insertelement_v1i64(<1 x i64> %op1) { ; CHECK-NEXT: mov z0.d, #5 // =0x5 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %r = insertelement <1 x i64> %op1, i64 5, i64 0 ret <1 x i64> %r } @@ -306,12 +222,6 @@ define <2 x i64> @insertelement_v2i64(<2 x i64> %op1) { ; CHECK-NEXT: mov z0.d, p0/m, x8 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v0.d[1], x8 -; NONEON-NOSVE-NEXT: ret %r = insertelement <2 x i64> %op1, i64 5, i64 1 ret <2 x i64> %r } @@ -329,13 +239,6 @@ define <4 x i64> @insertelement_v4i64(ptr %a) { ; CHECK-NEXT: mov z1.d, p0/m, x8 ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: mov w8, #5 // =0x5 -; NONEON-NOSVE-NEXT: mov v1.d[1], x8 -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %r = insertelement <4 x i64> %op1, i64 5, i64 3 ret <4 x i64> %r @@ -354,16 +257,6 @@ define <2 x half> @insertelement_v2f16(<2 x half> %op1) { ; CHECK-NEXT: ldr d0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: adrp x8, .LCPI14_0 -; NONEON-NOSVE-NEXT: add x8, x8, :lo12:.LCPI14_0 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: ld1r { v1.4h }, [x8] -; NONEON-NOSVE-NEXT: mov v1.h[0], v0.h[0] -; NONEON-NOSVE-NEXT: fmov d0, d1 -; NONEON-NOSVE-NEXT: ret %r = insertelement <2 x half> %op1, half 5.0, i64 1 ret <2 x half> %r } @@ -381,15 +274,6 @@ define <4 x half> @insertelement_v4f16(<4 x half> %op1) { ; CHECK-NEXT: mov z0.h, p0/m, h1 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI15_0 -; NONEON-NOSVE-NEXT: add x8, x8, :lo12:.LCPI15_0 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[3], [x8] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %r = insertelement <4 x half> %op1, half 5.0, i64 3 ret <4 x half> %r } @@ -407,13 +291,6 @@ define <8 x half> @insertelement_v8f16(<8 x half> %op1) { ; CHECK-NEXT: mov z0.h, p0/m, h1 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: adrp x8, .LCPI16_0 -; NONEON-NOSVE-NEXT: add x8, x8, :lo12:.LCPI16_0 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[7], [x8] -; NONEON-NOSVE-NEXT: ret %r = insertelement <8 x half> %op1, half 5.0, i64 7 ret <8 x half> %r } @@ -431,14 +308,6 @@ define <16 x half> @insertelement_v16f16(ptr %a) { ; CHECK-NEXT: mov z1.h, p0/m, h2 ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: adrp x8, .LCPI17_0 -; NONEON-NOSVE-NEXT: add x8, x8, :lo12:.LCPI17_0 -; NONEON-NOSVE-NEXT: ld1 { v1.h }[7], [x8] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %r = insertelement <16 x half> %op1, half 5.0, i64 15 ret <16 x half> %r @@ -458,14 +327,6 @@ define <2 x float> @insertelement_v2f32(<2 x float> %op1) { ; CHECK-NEXT: mov z0.s, p0/m, s1 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov s1, #5.00000000 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: mov v0.s[1], v1.s[0] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %r = insertelement <2 x float> %op1, float 5.0, i64 1 ret <2 x float> %r } @@ -483,12 +344,6 @@ define <4 x float> @insertelement_v4f32(<4 x float> %op1) { ; CHECK-NEXT: mov z0.s, p0/m, s1 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov s1, #5.00000000 -; NONEON-NOSVE-NEXT: mov v0.s[3], v1.s[0] -; NONEON-NOSVE-NEXT: ret %r = insertelement <4 x float> %op1, float 5.0, i64 3 ret <4 x float> %r } @@ -506,13 +361,6 @@ define <8 x float> @insertelement_v8f32(ptr %a) { ; CHECK-NEXT: mov z1.s, p0/m, s2 ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov s2, #5.00000000 -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: mov v1.s[3], v2.s[0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %r = insertelement <8 x float> %op1, float 5.0, i64 7 ret <8 x float> %r @@ -524,12 +372,6 @@ define <1 x double> @insertelement_v1f64(<1 x double> %op1) { ; CHECK: // %bb.0: ; CHECK-NEXT: fmov d0, #5.00000000 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov x8, #4617315517961601024 // =0x4014000000000000 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %r = insertelement <1 x double> %op1, double 5.0, i64 0 ret <1 x double> %r } @@ -547,12 +389,6 @@ define <2 x double> @insertelement_v2f64(<2 x double> %op1) { ; CHECK-NEXT: mov z0.d, p0/m, d1 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov d1, #5.00000000 -; NONEON-NOSVE-NEXT: mov v0.d[1], v1.d[0] -; NONEON-NOSVE-NEXT: ret %r = insertelement <2 x double> %op1, double 5.0, i64 1 ret <2 x double> %r } @@ -570,14 +406,6 @@ define <4 x double> @insertelement_v4f64(ptr %a) { ; CHECK-NEXT: mov z1.d, p0/m, d2 ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: insertelement_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov d0, #5.00000000 -; NONEON-NOSVE-NEXT: ldr q1, [x0, #16] -; NONEON-NOSVE-NEXT: mov v1.d[1], v0.d[0] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %r = insertelement <4 x double> %op1, double 5.0, i64 3 ret <4 x double> %r diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll index da408a11e784..8baa87c6d686 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll @@ -2,7 +2,6 @@ ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE ; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2 ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2 -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -17,11 +16,6 @@ define <4 x i8> @add_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: add v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = add <4 x i8> %op1, %op2 ret <4 x i8> %res } @@ -34,11 +28,6 @@ define <8 x i8> @add_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: add z0.b, z0.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: add v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = add <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -51,11 +40,6 @@ define <16 x i8> @add_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: add z0.b, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = add <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -69,15 +53,6 @@ define void @add_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: add z1.b, z2.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: add v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = add <32 x i8> %op1, %op2 @@ -93,11 +68,6 @@ define <2 x i16> @add_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; CHECK-NEXT: add z0.s, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: add v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = add <2 x i16> %op1, %op2 ret <2 x i16> %res } @@ -110,11 +80,6 @@ define <4 x i16> @add_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: add v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = add <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -127,11 +92,6 @@ define <8 x i16> @add_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %res = add <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -145,15 +105,6 @@ define void @add_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: add z1.h, z2.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: add v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: add v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = add <16 x i16> %op1, %op2 @@ -169,11 +120,6 @@ define <2 x i32> @add_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: add z0.s, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: add v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = add <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -186,11 +132,6 @@ define <4 x i32> @add_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: add z0.s, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: add v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = add <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -204,15 +145,6 @@ define void @add_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: add z1.s, z2.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: add v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: add v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = add <8 x i32> %op1, %op2 @@ -228,11 +160,6 @@ define <1 x i64> @add_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: add z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: add d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %res = add <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -245,11 +172,6 @@ define <2 x i64> @add_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: add z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: add v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = add <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -263,15 +185,6 @@ define void @add_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: add z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: add v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: add v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = add <4 x i64> %op1, %op2 @@ -300,11 +213,6 @@ define <4 x i8> @mul_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; SVE2-NEXT: mul z0.h, z0.h, z1.h ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mul v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = mul <4 x i8> %op1, %op2 ret <4 x i8> %res } @@ -326,11 +234,6 @@ define <8 x i8> @mul_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; SVE2-NEXT: mul z0.b, z0.b, z1.b ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mul v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = mul <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -352,11 +255,6 @@ define <16 x i8> @mul_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; SVE2-NEXT: mul z0.b, z0.b, z1.b ; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mul v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = mul <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -381,15 +279,6 @@ define void @mul_v32i8(ptr %a, ptr %b) { ; SVE2-NEXT: mul z1.b, z2.b, z3.b ; SVE2-NEXT: stp q0, q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: mul v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: mul v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = mul <32 x i8> %op1, %op2 @@ -414,11 +303,6 @@ define <2 x i16> @mul_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; SVE2-NEXT: mul z0.s, z0.s, z1.s ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mul v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = mul <2 x i16> %op1, %op2 ret <2 x i16> %res } @@ -440,11 +324,6 @@ define <4 x i16> @mul_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; SVE2-NEXT: mul z0.h, z0.h, z1.h ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mul v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = mul <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -466,11 +345,6 @@ define <8 x i16> @mul_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; SVE2-NEXT: mul z0.h, z0.h, z1.h ; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mul v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %res = mul <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -495,15 +369,6 @@ define void @mul_v16i16(ptr %a, ptr %b) { ; SVE2-NEXT: mul z1.h, z2.h, z3.h ; SVE2-NEXT: stp q0, q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: mul v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: mul v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = mul <16 x i16> %op1, %op2 @@ -528,11 +393,6 @@ define <2 x i32> @mul_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; SVE2-NEXT: mul z0.s, z0.s, z1.s ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mul v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = mul <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -554,11 +414,6 @@ define <4 x i32> @mul_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; SVE2-NEXT: mul z0.s, z0.s, z1.s ; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mul v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = mul <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -583,15 +438,6 @@ define void @mul_v8i32(ptr %a, ptr %b) { ; SVE2-NEXT: mul z1.s, z2.s, z3.s ; SVE2-NEXT: stp q0, q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: mul v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: mul v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = mul <8 x i32> %op1, %op2 @@ -616,16 +462,6 @@ define <1 x i64> @mul_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; SVE2-NEXT: mul z0.d, z0.d, z1.d ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: mul x8, x9, x8 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %res = mul <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -647,18 +483,6 @@ define <2 x i64> @mul_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; SVE2-NEXT: mul z0.d, z0.d, z1.d ; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x10, d1 -; NONEON-NOSVE-NEXT: fmov x11, d0 -; NONEON-NOSVE-NEXT: mov x8, v1.d[1] -; NONEON-NOSVE-NEXT: mov x9, v0.d[1] -; NONEON-NOSVE-NEXT: mul x10, x11, x10 -; NONEON-NOSVE-NEXT: mul x8, x9, x8 -; NONEON-NOSVE-NEXT: fmov d0, x10 -; NONEON-NOSVE-NEXT: mov v0.d[1], x8 -; NONEON-NOSVE-NEXT: ret %res = mul <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -683,29 +507,6 @@ define void @mul_v4i64(ptr %a, ptr %b) { ; SVE2-NEXT: mul z1.d, z2.d, z3.d ; SVE2-NEXT: stp q0, q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: fmov x12, d2 -; NONEON-NOSVE-NEXT: mov x11, v2.d[1] -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: mov x10, v3.d[1] -; NONEON-NOSVE-NEXT: mov x13, v1.d[1] -; NONEON-NOSVE-NEXT: mov x14, v0.d[1] -; NONEON-NOSVE-NEXT: mul x8, x9, x8 -; NONEON-NOSVE-NEXT: fmov x9, d3 -; NONEON-NOSVE-NEXT: mul x10, x11, x10 -; NONEON-NOSVE-NEXT: mul x9, x12, x9 -; NONEON-NOSVE-NEXT: fmov d1, x8 -; NONEON-NOSVE-NEXT: mul x11, x14, x13 -; NONEON-NOSVE-NEXT: fmov d0, x9 -; NONEON-NOSVE-NEXT: mov v1.d[1], x11 -; NONEON-NOSVE-NEXT: mov v0.d[1], x10 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = mul <4 x i64> %op1, %op2 @@ -725,11 +526,6 @@ define <4 x i8> @sub_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: sub z0.h, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = sub <4 x i8> %op1, %op2 ret <4 x i8> %res } @@ -742,11 +538,6 @@ define <8 x i8> @sub_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: sub z0.b, z0.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = sub <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -759,11 +550,6 @@ define <16 x i8> @sub_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: sub z0.b, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = sub <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -777,15 +563,6 @@ define void @sub_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: sub z1.b, z2.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: sub v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: sub v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = sub <32 x i8> %op1, %op2 @@ -801,11 +578,6 @@ define <2 x i16> @sub_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; CHECK-NEXT: sub z0.s, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = sub <2 x i16> %op1, %op2 ret <2 x i16> %res } @@ -818,11 +590,6 @@ define <4 x i16> @sub_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: sub z0.h, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = sub <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -835,11 +602,6 @@ define <8 x i16> @sub_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: sub z0.h, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %res = sub <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -853,15 +615,6 @@ define void @sub_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: sub z1.h, z2.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: sub v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: sub v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = sub <16 x i16> %op1, %op2 @@ -877,11 +630,6 @@ define <2 x i32> @sub_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: sub z0.s, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = sub <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -894,11 +642,6 @@ define <4 x i32> @sub_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: sub z0.s, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = sub <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -912,15 +655,6 @@ define void @sub_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: sub z1.s, z2.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: sub v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: sub v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = sub <8 x i32> %op1, %op2 @@ -936,11 +670,6 @@ define <1 x i64> @sub_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: sub z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %res = sub <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -953,11 +682,6 @@ define <2 x i64> @sub_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: sub z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = sub <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -971,15 +695,6 @@ define void @sub_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: sub z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: sub v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: sub v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = sub <4 x i64> %op1, %op2 @@ -1000,13 +715,6 @@ define <4 x i8> @abs_v4i8(<4 x i8> %op1) { ; CHECK-NEXT: abs z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: abs v0.4h, v0.4h -; NONEON-NOSVE-NEXT: ret %res = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %op1, i1 false) ret <4 x i8> %res } @@ -1019,11 +727,6 @@ define <8 x i8> @abs_v8i8(<8 x i8> %op1) { ; CHECK-NEXT: abs z0.b, p0/m, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: abs v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %op1, i1 false) ret <8 x i8> %res } @@ -1036,11 +739,6 @@ define <16 x i8> @abs_v16i8(<16 x i8> %op1) { ; CHECK-NEXT: abs z0.b, p0/m, z0.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: abs v0.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %res = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %op1, i1 false) ret <16 x i8> %res } @@ -1054,14 +752,6 @@ define void @abs_v32i8(ptr %a) { ; CHECK-NEXT: abs z1.b, p0/m, z1.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: abs v0.16b, v0.16b -; NONEON-NOSVE-NEXT: abs v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %res = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %op1, i1 false) store <32 x i8> %res, ptr %a @@ -1077,13 +767,6 @@ define <2 x i16> @abs_v2i16(<2 x i16> %op1) { ; CHECK-NEXT: abs z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: abs v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %op1, i1 false) ret <2 x i16> %res } @@ -1096,11 +779,6 @@ define <4 x i16> @abs_v4i16(<4 x i16> %op1) { ; CHECK-NEXT: abs z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: abs v0.4h, v0.4h -; NONEON-NOSVE-NEXT: ret %res = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %op1, i1 false) ret <4 x i16> %res } @@ -1113,11 +791,6 @@ define <8 x i16> @abs_v8i16(<8 x i16> %op1) { ; CHECK-NEXT: abs z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: abs v0.8h, v0.8h -; NONEON-NOSVE-NEXT: ret %res = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %op1, i1 false) ret <8 x i16> %res } @@ -1131,14 +804,6 @@ define void @abs_v16i16(ptr %a) { ; CHECK-NEXT: abs z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: abs v0.8h, v0.8h -; NONEON-NOSVE-NEXT: abs v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %res = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %op1, i1 false) store <16 x i16> %res, ptr %a @@ -1153,11 +818,6 @@ define <2 x i32> @abs_v2i32(<2 x i32> %op1) { ; CHECK-NEXT: abs z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: abs v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %op1, i1 false) ret <2 x i32> %res } @@ -1170,11 +830,6 @@ define <4 x i32> @abs_v4i32(<4 x i32> %op1) { ; CHECK-NEXT: abs z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: abs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %op1, i1 false) ret <4 x i32> %res } @@ -1188,14 +843,6 @@ define void @abs_v8i32(ptr %a) { ; CHECK-NEXT: abs z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: abs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: abs v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %op1, i1 false) store <8 x i32> %res, ptr %a @@ -1210,11 +857,6 @@ define <1 x i64> @abs_v1i64(<1 x i64> %op1) { ; CHECK-NEXT: abs z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: abs d0, d0 -; NONEON-NOSVE-NEXT: ret %res = call <1 x i64> @llvm.abs.v1i64(<1 x i64> %op1, i1 false) ret <1 x i64> %res } @@ -1227,11 +869,6 @@ define <2 x i64> @abs_v2i64(<2 x i64> %op1) { ; CHECK-NEXT: abs z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: abs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %op1, i1 false) ret <2 x i64> %res } @@ -1245,14 +882,6 @@ define void @abs_v4i64(ptr %a) { ; CHECK-NEXT: abs z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: abs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: abs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %op1, i1 false) store <4 x i64> %res, ptr %a diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll index 3148d4f1677c..73c1eac99dd3 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -19,11 +18,6 @@ define <8 x i8> @icmp_eq_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmeq v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %cmp = icmp eq <8 x i8> %op1, %op2 %sext = sext <8 x i1> %cmp to <8 x i8> ret <8 x i8> %sext @@ -39,11 +33,6 @@ define <16 x i8> @icmp_eq_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmeq v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %cmp = icmp eq <16 x i8> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext @@ -61,15 +50,6 @@ define void @icmp_eq_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: mov z1.b, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: cmeq v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: cmeq v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %cmp = icmp eq <32 x i8> %op1, %op2 @@ -88,11 +68,6 @@ define <4 x i16> @icmp_eq_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmeq v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %cmp = icmp eq <4 x i16> %op1, %op2 %sext = sext <4 x i1> %cmp to <4 x i16> ret <4 x i16> %sext @@ -108,11 +83,6 @@ define <8 x i16> @icmp_eq_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmeq v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %cmp = icmp eq <8 x i16> %op1, %op2 %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext @@ -130,15 +100,6 @@ define void @icmp_eq_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: cmeq v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: cmeq v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %cmp = icmp eq <16 x i16> %op1, %op2 @@ -157,11 +118,6 @@ define <2 x i32> @icmp_eq_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmeq v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %cmp = icmp eq <2 x i32> %op1, %op2 %sext = sext <2 x i1> %cmp to <2 x i32> ret <2 x i32> %sext @@ -177,11 +133,6 @@ define <4 x i32> @icmp_eq_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmeq v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %cmp = icmp eq <4 x i32> %op1, %op2 %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext @@ -199,15 +150,6 @@ define void @icmp_eq_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: cmeq v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: cmeq v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %cmp = icmp eq <8 x i32> %op1, %op2 @@ -226,11 +168,6 @@ define <1 x i64> @icmp_eq_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmeq d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %cmp = icmp eq <1 x i64> %op1, %op2 %sext = sext <1 x i1> %cmp to <1 x i64> ret <1 x i64> %sext @@ -246,11 +183,6 @@ define <2 x i64> @icmp_eq_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmeq v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %cmp = icmp eq <2 x i64> %op1, %op2 %sext = sext <2 x i1> %cmp to <2 x i64> ret <2 x i64> %sext @@ -268,15 +200,6 @@ define void @icmp_eq_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: mov z1.d, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: cmeq v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: cmeq v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %cmp = icmp eq <4 x i64> %op1, %op2 @@ -301,17 +224,6 @@ define void @icmp_ne_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: mov z1.b, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_ne_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: cmeq v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: cmeq v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: mvn v0.16b, v0.16b -; NONEON-NOSVE-NEXT: mvn v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %cmp = icmp ne <32 x i8> %op1, %op2 @@ -334,14 +246,6 @@ define void @icmp_sge_v8i16(ptr %a, ptr %b) { ; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_sge_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: cmge v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i16>, ptr %a %op2 = load <8 x i16>, ptr %b %cmp = icmp sge <8 x i16> %op1, %op2 @@ -366,15 +270,6 @@ define void @icmp_sgt_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_sgt_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: cmgt v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: cmgt v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %cmp = icmp sgt <16 x i16> %op1, %op2 @@ -397,14 +292,6 @@ define void @icmp_sle_v4i32(ptr %a, ptr %b) { ; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_sle_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: cmge v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i32>, ptr %a %op2 = load <4 x i32>, ptr %b %cmp = icmp sle <4 x i32> %op1, %op2 @@ -429,15 +316,6 @@ define void @icmp_slt_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_slt_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: cmgt v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: cmgt v1.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %cmp = icmp slt <8 x i32> %op1, %op2 @@ -460,14 +338,6 @@ define void @icmp_uge_v2i64(ptr %a, ptr %b) { ; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_uge_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: cmhs v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x i64>, ptr %a %op2 = load <2 x i64>, ptr %b %cmp = icmp uge <2 x i64> %op1, %op2 @@ -490,14 +360,6 @@ define void @icmp_ugt_v2i64(ptr %a, ptr %b) { ; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_ugt_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: cmhi v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x i64>, ptr %a %op2 = load <2 x i64>, ptr %b %cmp = icmp ugt <2 x i64> %op1, %op2 @@ -520,14 +382,6 @@ define void @icmp_ule_v2i64(ptr %a, ptr %b) { ; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_ule_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: cmhs v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x i64>, ptr %a %op2 = load <2 x i64>, ptr %b %cmp = icmp ule <2 x i64> %op1, %op2 @@ -550,14 +404,6 @@ define void @icmp_ult_v2i64(ptr %a, ptr %b) { ; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_ult_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: cmhi v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x i64>, ptr %a %op2 = load <2 x i64>, ptr %b %cmp = icmp ult <2 x i64> %op1, %op2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll index 27a4924ea367..5158dda37a8b 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll @@ -2,7 +2,6 @@ ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE ; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2 ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2 -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -25,31 +24,6 @@ define <4 x i8> @sdiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: shl v1.4h, v1.4h, #8 -; NONEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: sshr v1.4h, v1.4h, #8 -; NONEON-NOSVE-NEXT: smov w8, v1.h[1] -; NONEON-NOSVE-NEXT: smov w9, v0.h[1] -; NONEON-NOSVE-NEXT: smov w10, v0.h[0] -; NONEON-NOSVE-NEXT: smov w11, v0.h[2] -; NONEON-NOSVE-NEXT: smov w12, v0.h[3] -; NONEON-NOSVE-NEXT: sdiv w8, w9, w8 -; NONEON-NOSVE-NEXT: smov w9, v1.h[0] -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: smov w10, v1.h[2] -; NONEON-NOSVE-NEXT: sdiv w10, w11, w10 -; NONEON-NOSVE-NEXT: smov w11, v1.h[3] -; NONEON-NOSVE-NEXT: fmov s0, w9 -; NONEON-NOSVE-NEXT: mov v0.h[1], w8 -; NONEON-NOSVE-NEXT: sdiv w8, w12, w11 -; NONEON-NOSVE-NEXT: mov v0.h[2], w10 -; NONEON-NOSVE-NEXT: mov v0.h[3], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = sdiv <4 x i8> %op1, %op2 ret <4 x i8> %res } @@ -77,45 +51,6 @@ define <8 x i8> @sdiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: smov w8, v1.b[1] -; NONEON-NOSVE-NEXT: smov w9, v0.b[1] -; NONEON-NOSVE-NEXT: smov w10, v0.b[0] -; NONEON-NOSVE-NEXT: smov w11, v0.b[2] -; NONEON-NOSVE-NEXT: smov w12, v0.b[3] -; NONEON-NOSVE-NEXT: smov w13, v0.b[4] -; NONEON-NOSVE-NEXT: smov w14, v0.b[5] -; NONEON-NOSVE-NEXT: sdiv w8, w9, w8 -; NONEON-NOSVE-NEXT: smov w9, v1.b[0] -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: smov w10, v1.b[2] -; NONEON-NOSVE-NEXT: sdiv w10, w11, w10 -; NONEON-NOSVE-NEXT: smov w11, v1.b[3] -; NONEON-NOSVE-NEXT: fmov s2, w9 -; NONEON-NOSVE-NEXT: smov w9, v1.b[6] -; NONEON-NOSVE-NEXT: mov v2.b[1], w8 -; NONEON-NOSVE-NEXT: sdiv w11, w12, w11 -; NONEON-NOSVE-NEXT: smov w12, v1.b[4] -; NONEON-NOSVE-NEXT: mov v2.b[2], w10 -; NONEON-NOSVE-NEXT: smov w10, v0.b[6] -; NONEON-NOSVE-NEXT: sdiv w12, w13, w12 -; NONEON-NOSVE-NEXT: smov w13, v1.b[5] -; NONEON-NOSVE-NEXT: mov v2.b[3], w11 -; NONEON-NOSVE-NEXT: smov w11, v0.b[7] -; NONEON-NOSVE-NEXT: sdiv w8, w14, w13 -; NONEON-NOSVE-NEXT: mov v2.b[4], w12 -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: smov w10, v1.b[7] -; NONEON-NOSVE-NEXT: mov v2.b[5], w8 -; NONEON-NOSVE-NEXT: sdiv w8, w11, w10 -; NONEON-NOSVE-NEXT: mov v2.b[6], w9 -; NONEON-NOSVE-NEXT: mov v2.b[7], w8 -; NONEON-NOSVE-NEXT: fmov d0, d2 -; NONEON-NOSVE-NEXT: ret %res = sdiv <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -163,75 +98,6 @@ define <16 x i8> @sdiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smov w8, v1.b[1] -; NONEON-NOSVE-NEXT: smov w9, v0.b[1] -; NONEON-NOSVE-NEXT: smov w10, v0.b[0] -; NONEON-NOSVE-NEXT: smov w11, v0.b[2] -; NONEON-NOSVE-NEXT: smov w12, v0.b[3] -; NONEON-NOSVE-NEXT: smov w13, v0.b[4] -; NONEON-NOSVE-NEXT: smov w14, v0.b[5] -; NONEON-NOSVE-NEXT: smov w15, v0.b[6] -; NONEON-NOSVE-NEXT: smov w16, v0.b[7] -; NONEON-NOSVE-NEXT: smov w17, v0.b[8] -; NONEON-NOSVE-NEXT: smov w18, v0.b[9] -; NONEON-NOSVE-NEXT: sdiv w8, w9, w8 -; NONEON-NOSVE-NEXT: smov w9, v1.b[0] -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: smov w10, v1.b[2] -; NONEON-NOSVE-NEXT: sdiv w10, w11, w10 -; NONEON-NOSVE-NEXT: smov w11, v1.b[3] -; NONEON-NOSVE-NEXT: fmov s2, w9 -; NONEON-NOSVE-NEXT: smov w9, v1.b[10] -; NONEON-NOSVE-NEXT: mov v2.b[1], w8 -; NONEON-NOSVE-NEXT: sdiv w11, w12, w11 -; NONEON-NOSVE-NEXT: smov w12, v1.b[4] -; NONEON-NOSVE-NEXT: mov v2.b[2], w10 -; NONEON-NOSVE-NEXT: smov w10, v0.b[10] -; NONEON-NOSVE-NEXT: sdiv w12, w13, w12 -; NONEON-NOSVE-NEXT: smov w13, v1.b[5] -; NONEON-NOSVE-NEXT: mov v2.b[3], w11 -; NONEON-NOSVE-NEXT: smov w11, v0.b[11] -; NONEON-NOSVE-NEXT: sdiv w13, w14, w13 -; NONEON-NOSVE-NEXT: smov w14, v1.b[6] -; NONEON-NOSVE-NEXT: mov v2.b[4], w12 -; NONEON-NOSVE-NEXT: smov w12, v0.b[12] -; NONEON-NOSVE-NEXT: sdiv w14, w15, w14 -; NONEON-NOSVE-NEXT: smov w15, v1.b[7] -; NONEON-NOSVE-NEXT: mov v2.b[5], w13 -; NONEON-NOSVE-NEXT: smov w13, v0.b[13] -; NONEON-NOSVE-NEXT: sdiv w15, w16, w15 -; NONEON-NOSVE-NEXT: smov w16, v1.b[8] -; NONEON-NOSVE-NEXT: mov v2.b[6], w14 -; NONEON-NOSVE-NEXT: sdiv w16, w17, w16 -; NONEON-NOSVE-NEXT: smov w17, v1.b[9] -; NONEON-NOSVE-NEXT: mov v2.b[7], w15 -; NONEON-NOSVE-NEXT: sdiv w8, w18, w17 -; NONEON-NOSVE-NEXT: mov v2.b[8], w16 -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: smov w10, v1.b[11] -; NONEON-NOSVE-NEXT: mov v2.b[9], w8 -; NONEON-NOSVE-NEXT: sdiv w10, w11, w10 -; NONEON-NOSVE-NEXT: smov w11, v1.b[12] -; NONEON-NOSVE-NEXT: mov v2.b[10], w9 -; NONEON-NOSVE-NEXT: smov w9, v1.b[14] -; NONEON-NOSVE-NEXT: sdiv w11, w12, w11 -; NONEON-NOSVE-NEXT: smov w12, v1.b[13] -; NONEON-NOSVE-NEXT: mov v2.b[11], w10 -; NONEON-NOSVE-NEXT: smov w10, v1.b[15] -; NONEON-NOSVE-NEXT: sdiv w8, w13, w12 -; NONEON-NOSVE-NEXT: smov w12, v0.b[14] -; NONEON-NOSVE-NEXT: mov v2.b[12], w11 -; NONEON-NOSVE-NEXT: smov w11, v0.b[15] -; NONEON-NOSVE-NEXT: sdiv w9, w12, w9 -; NONEON-NOSVE-NEXT: mov v2.b[13], w8 -; NONEON-NOSVE-NEXT: sdiv w8, w11, w10 -; NONEON-NOSVE-NEXT: mov v2.b[14], w9 -; NONEON-NOSVE-NEXT: mov v2.b[15], w8 -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = sdiv <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -312,163 +178,6 @@ define void @sdiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: splice z3.b, p0, z3.b, z1.b ; CHECK-NEXT: stp q3, q2, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str x27, [sp, #-80]! // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x26, x25, [sp, #16] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x24, x23, [sp, #32] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 80 -; NONEON-NOSVE-NEXT: .cfi_offset w19, -8 -; NONEON-NOSVE-NEXT: .cfi_offset w20, -16 -; NONEON-NOSVE-NEXT: .cfi_offset w21, -24 -; NONEON-NOSVE-NEXT: .cfi_offset w22, -32 -; NONEON-NOSVE-NEXT: .cfi_offset w23, -40 -; NONEON-NOSVE-NEXT: .cfi_offset w24, -48 -; NONEON-NOSVE-NEXT: .cfi_offset w25, -56 -; NONEON-NOSVE-NEXT: .cfi_offset w26, -64 -; NONEON-NOSVE-NEXT: .cfi_offset w27, -80 -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x0] -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: smov w8, v1.b[1] -; NONEON-NOSVE-NEXT: smov w9, v0.b[1] -; NONEON-NOSVE-NEXT: smov w10, v0.b[0] -; NONEON-NOSVE-NEXT: smov w11, v0.b[2] -; NONEON-NOSVE-NEXT: smov w12, v0.b[3] -; NONEON-NOSVE-NEXT: smov w13, v0.b[4] -; NONEON-NOSVE-NEXT: smov w14, v0.b[5] -; NONEON-NOSVE-NEXT: smov w15, v0.b[6] -; NONEON-NOSVE-NEXT: smov w17, v0.b[8] -; NONEON-NOSVE-NEXT: smov w2, v0.b[10] -; NONEON-NOSVE-NEXT: smov w3, v0.b[11] -; NONEON-NOSVE-NEXT: smov w4, v0.b[12] -; NONEON-NOSVE-NEXT: sdiv w8, w9, w8 -; NONEON-NOSVE-NEXT: smov w9, v1.b[0] -; NONEON-NOSVE-NEXT: smov w5, v0.b[13] -; NONEON-NOSVE-NEXT: smov w6, v0.b[14] -; NONEON-NOSVE-NEXT: smov w1, v3.b[1] -; NONEON-NOSVE-NEXT: smov w7, v2.b[0] -; NONEON-NOSVE-NEXT: smov w19, v2.b[2] -; NONEON-NOSVE-NEXT: smov w20, v2.b[3] -; NONEON-NOSVE-NEXT: smov w21, v2.b[4] -; NONEON-NOSVE-NEXT: smov w22, v2.b[5] -; NONEON-NOSVE-NEXT: smov w23, v2.b[6] -; NONEON-NOSVE-NEXT: smov w24, v2.b[7] -; NONEON-NOSVE-NEXT: smov w25, v2.b[8] -; NONEON-NOSVE-NEXT: smov w26, v2.b[9] -; NONEON-NOSVE-NEXT: smov w27, v2.b[10] -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: smov w10, v1.b[2] -; NONEON-NOSVE-NEXT: sdiv w11, w11, w10 -; NONEON-NOSVE-NEXT: smov w10, v1.b[3] -; NONEON-NOSVE-NEXT: fmov s5, w9 -; NONEON-NOSVE-NEXT: smov w9, v3.b[11] -; NONEON-NOSVE-NEXT: mov v5.b[1], w8 -; NONEON-NOSVE-NEXT: sdiv w10, w12, w10 -; NONEON-NOSVE-NEXT: smov w12, v1.b[4] -; NONEON-NOSVE-NEXT: mov v5.b[2], w11 -; NONEON-NOSVE-NEXT: smov w11, v2.b[11] -; NONEON-NOSVE-NEXT: sdiv w13, w13, w12 -; NONEON-NOSVE-NEXT: smov w12, v1.b[5] -; NONEON-NOSVE-NEXT: mov v5.b[3], w10 -; NONEON-NOSVE-NEXT: smov w10, v3.b[12] -; NONEON-NOSVE-NEXT: sdiv w12, w14, w12 -; NONEON-NOSVE-NEXT: smov w14, v1.b[6] -; NONEON-NOSVE-NEXT: mov v5.b[4], w13 -; NONEON-NOSVE-NEXT: smov w13, v2.b[14] -; NONEON-NOSVE-NEXT: sdiv w16, w15, w14 -; NONEON-NOSVE-NEXT: smov w14, v1.b[7] -; NONEON-NOSVE-NEXT: smov w15, v0.b[7] -; NONEON-NOSVE-NEXT: mov v5.b[5], w12 -; NONEON-NOSVE-NEXT: smov w12, v2.b[13] -; NONEON-NOSVE-NEXT: sdiv w14, w15, w14 -; NONEON-NOSVE-NEXT: smov w15, v1.b[8] -; NONEON-NOSVE-NEXT: mov v5.b[6], w16 -; NONEON-NOSVE-NEXT: sdiv w18, w17, w15 -; NONEON-NOSVE-NEXT: smov w15, v1.b[9] -; NONEON-NOSVE-NEXT: smov w17, v0.b[9] -; NONEON-NOSVE-NEXT: mov v5.b[7], w14 -; NONEON-NOSVE-NEXT: sdiv w17, w17, w15 -; NONEON-NOSVE-NEXT: smov w15, v1.b[10] -; NONEON-NOSVE-NEXT: mov v5.b[8], w18 -; NONEON-NOSVE-NEXT: sdiv w15, w2, w15 -; NONEON-NOSVE-NEXT: smov w2, v1.b[11] -; NONEON-NOSVE-NEXT: mov v5.b[9], w17 -; NONEON-NOSVE-NEXT: sdiv w2, w3, w2 -; NONEON-NOSVE-NEXT: smov w3, v1.b[12] -; NONEON-NOSVE-NEXT: mov v5.b[10], w15 -; NONEON-NOSVE-NEXT: sdiv w3, w4, w3 -; NONEON-NOSVE-NEXT: smov w4, v1.b[13] -; NONEON-NOSVE-NEXT: mov v5.b[11], w2 -; NONEON-NOSVE-NEXT: sdiv w4, w5, w4 -; NONEON-NOSVE-NEXT: smov w5, v1.b[14] -; NONEON-NOSVE-NEXT: mov v5.b[12], w3 -; NONEON-NOSVE-NEXT: sdiv w5, w6, w5 -; NONEON-NOSVE-NEXT: smov w6, v2.b[1] -; NONEON-NOSVE-NEXT: mov v5.b[13], w4 -; NONEON-NOSVE-NEXT: sdiv w1, w6, w1 -; NONEON-NOSVE-NEXT: smov w6, v3.b[0] -; NONEON-NOSVE-NEXT: mov v5.b[14], w5 -; NONEON-NOSVE-NEXT: sdiv w6, w7, w6 -; NONEON-NOSVE-NEXT: smov w7, v3.b[2] -; NONEON-NOSVE-NEXT: sdiv w7, w19, w7 -; NONEON-NOSVE-NEXT: smov w19, v3.b[3] -; NONEON-NOSVE-NEXT: fmov s4, w6 -; NONEON-NOSVE-NEXT: mov v4.b[1], w1 -; NONEON-NOSVE-NEXT: sdiv w19, w20, w19 -; NONEON-NOSVE-NEXT: smov w20, v3.b[4] -; NONEON-NOSVE-NEXT: mov v4.b[2], w7 -; NONEON-NOSVE-NEXT: sdiv w20, w21, w20 -; NONEON-NOSVE-NEXT: smov w21, v3.b[5] -; NONEON-NOSVE-NEXT: mov v4.b[3], w19 -; NONEON-NOSVE-NEXT: sdiv w21, w22, w21 -; NONEON-NOSVE-NEXT: smov w22, v3.b[6] -; NONEON-NOSVE-NEXT: mov v4.b[4], w20 -; NONEON-NOSVE-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w22, w23, w22 -; NONEON-NOSVE-NEXT: smov w23, v3.b[7] -; NONEON-NOSVE-NEXT: mov v4.b[5], w21 -; NONEON-NOSVE-NEXT: sdiv w23, w24, w23 -; NONEON-NOSVE-NEXT: smov w24, v3.b[8] -; NONEON-NOSVE-NEXT: mov v4.b[6], w22 -; NONEON-NOSVE-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w24, w25, w24 -; NONEON-NOSVE-NEXT: smov w25, v3.b[9] -; NONEON-NOSVE-NEXT: mov v4.b[7], w23 -; NONEON-NOSVE-NEXT: sdiv w25, w26, w25 -; NONEON-NOSVE-NEXT: smov w26, v3.b[10] -; NONEON-NOSVE-NEXT: mov v4.b[8], w24 -; NONEON-NOSVE-NEXT: ldp x24, x23, [sp, #32] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w8, w27, w26 -; NONEON-NOSVE-NEXT: mov v4.b[9], w25 -; NONEON-NOSVE-NEXT: ldp x26, x25, [sp, #16] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w9, w11, w9 -; NONEON-NOSVE-NEXT: smov w11, v2.b[12] -; NONEON-NOSVE-NEXT: mov v4.b[10], w8 -; NONEON-NOSVE-NEXT: smov w8, v3.b[15] -; NONEON-NOSVE-NEXT: sdiv w10, w11, w10 -; NONEON-NOSVE-NEXT: smov w11, v3.b[13] -; NONEON-NOSVE-NEXT: mov v4.b[11], w9 -; NONEON-NOSVE-NEXT: smov w9, v1.b[15] -; NONEON-NOSVE-NEXT: sdiv w11, w12, w11 -; NONEON-NOSVE-NEXT: smov w12, v3.b[14] -; NONEON-NOSVE-NEXT: mov v4.b[12], w10 -; NONEON-NOSVE-NEXT: smov w10, v0.b[15] -; NONEON-NOSVE-NEXT: sdiv w12, w13, w12 -; NONEON-NOSVE-NEXT: smov w13, v2.b[15] -; NONEON-NOSVE-NEXT: mov v4.b[13], w11 -; NONEON-NOSVE-NEXT: sdiv w8, w13, w8 -; NONEON-NOSVE-NEXT: mov v4.b[14], w12 -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: mov v4.b[15], w8 -; NONEON-NOSVE-NEXT: mov v5.b[15], w9 -; NONEON-NOSVE-NEXT: stp q4, q5, [x0] -; NONEON-NOSVE-NEXT: ldr x27, [sp], #80 // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = sdiv <32 x i8> %op1, %op2 @@ -487,23 +196,6 @@ define <2 x i16> @sdiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: shl v1.2s, v1.2s, #16 -; NONEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: sshr v1.2s, v1.2s, #16 -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: fmov w9, s0 -; NONEON-NOSVE-NEXT: mov w10, v0.s[1] -; NONEON-NOSVE-NEXT: sdiv w8, w9, w8 -; NONEON-NOSVE-NEXT: mov w9, v1.s[1] -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: mov v0.s[1], w9 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = sdiv <2 x i16> %op1, %op2 ret <2 x i16> %res } @@ -520,29 +212,6 @@ define <4 x i16> @sdiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: smov w8, v1.h[1] -; NONEON-NOSVE-NEXT: smov w9, v0.h[1] -; NONEON-NOSVE-NEXT: smov w10, v0.h[0] -; NONEON-NOSVE-NEXT: smov w11, v0.h[2] -; NONEON-NOSVE-NEXT: smov w12, v0.h[3] -; NONEON-NOSVE-NEXT: sdiv w8, w9, w8 -; NONEON-NOSVE-NEXT: smov w9, v1.h[0] -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: smov w10, v1.h[2] -; NONEON-NOSVE-NEXT: sdiv w10, w11, w10 -; NONEON-NOSVE-NEXT: smov w11, v1.h[3] -; NONEON-NOSVE-NEXT: fmov s0, w9 -; NONEON-NOSVE-NEXT: mov v0.h[1], w8 -; NONEON-NOSVE-NEXT: sdiv w8, w12, w11 -; NONEON-NOSVE-NEXT: mov v0.h[2], w10 -; NONEON-NOSVE-NEXT: mov v0.h[3], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = sdiv <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -569,43 +238,6 @@ define <8 x i16> @sdiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smov w8, v1.h[1] -; NONEON-NOSVE-NEXT: smov w9, v0.h[1] -; NONEON-NOSVE-NEXT: smov w10, v0.h[0] -; NONEON-NOSVE-NEXT: smov w11, v0.h[2] -; NONEON-NOSVE-NEXT: smov w12, v0.h[3] -; NONEON-NOSVE-NEXT: smov w13, v0.h[4] -; NONEON-NOSVE-NEXT: smov w14, v0.h[5] -; NONEON-NOSVE-NEXT: sdiv w8, w9, w8 -; NONEON-NOSVE-NEXT: smov w9, v1.h[0] -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: smov w10, v1.h[2] -; NONEON-NOSVE-NEXT: sdiv w10, w11, w10 -; NONEON-NOSVE-NEXT: smov w11, v1.h[3] -; NONEON-NOSVE-NEXT: fmov s2, w9 -; NONEON-NOSVE-NEXT: smov w9, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[1], w8 -; NONEON-NOSVE-NEXT: sdiv w11, w12, w11 -; NONEON-NOSVE-NEXT: smov w12, v1.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[2], w10 -; NONEON-NOSVE-NEXT: smov w10, v0.h[6] -; NONEON-NOSVE-NEXT: sdiv w12, w13, w12 -; NONEON-NOSVE-NEXT: smov w13, v1.h[5] -; NONEON-NOSVE-NEXT: mov v2.h[3], w11 -; NONEON-NOSVE-NEXT: smov w11, v0.h[7] -; NONEON-NOSVE-NEXT: sdiv w8, w14, w13 -; NONEON-NOSVE-NEXT: mov v2.h[4], w12 -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: smov w10, v1.h[7] -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: sdiv w8, w11, w10 -; NONEON-NOSVE-NEXT: mov v2.h[6], w9 -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = sdiv <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -646,79 +278,6 @@ define void @sdiv_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: splice z3.h, p0, z3.h, z1.h ; CHECK-NEXT: stp q3, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x0] -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: smov w8, v1.h[1] -; NONEON-NOSVE-NEXT: smov w9, v0.h[1] -; NONEON-NOSVE-NEXT: smov w10, v0.h[0] -; NONEON-NOSVE-NEXT: smov w11, v0.h[2] -; NONEON-NOSVE-NEXT: smov w12, v0.h[3] -; NONEON-NOSVE-NEXT: smov w13, v0.h[4] -; NONEON-NOSVE-NEXT: smov w14, v0.h[5] -; NONEON-NOSVE-NEXT: smov w15, v0.h[6] -; NONEON-NOSVE-NEXT: smov w16, v2.h[1] -; NONEON-NOSVE-NEXT: smov w17, v2.h[0] -; NONEON-NOSVE-NEXT: smov w18, v2.h[2] -; NONEON-NOSVE-NEXT: smov w1, v2.h[3] -; NONEON-NOSVE-NEXT: sdiv w8, w9, w8 -; NONEON-NOSVE-NEXT: smov w9, v1.h[0] -; NONEON-NOSVE-NEXT: smov w2, v2.h[4] -; NONEON-NOSVE-NEXT: smov w3, v2.h[5] -; NONEON-NOSVE-NEXT: smov w4, v2.h[6] -; NONEON-NOSVE-NEXT: sdiv w10, w10, w9 -; NONEON-NOSVE-NEXT: smov w9, v1.h[2] -; NONEON-NOSVE-NEXT: sdiv w9, w11, w9 -; NONEON-NOSVE-NEXT: smov w11, v1.h[3] -; NONEON-NOSVE-NEXT: fmov s5, w10 -; NONEON-NOSVE-NEXT: smov w10, v3.h[7] -; NONEON-NOSVE-NEXT: mov v5.h[1], w8 -; NONEON-NOSVE-NEXT: sdiv w11, w12, w11 -; NONEON-NOSVE-NEXT: smov w12, v1.h[4] -; NONEON-NOSVE-NEXT: mov v5.h[2], w9 -; NONEON-NOSVE-NEXT: smov w9, v2.h[7] -; NONEON-NOSVE-NEXT: sdiv w12, w13, w12 -; NONEON-NOSVE-NEXT: smov w13, v1.h[5] -; NONEON-NOSVE-NEXT: mov v5.h[3], w11 -; NONEON-NOSVE-NEXT: smov w11, v0.h[7] -; NONEON-NOSVE-NEXT: sdiv w13, w14, w13 -; NONEON-NOSVE-NEXT: smov w14, v1.h[6] -; NONEON-NOSVE-NEXT: mov v5.h[4], w12 -; NONEON-NOSVE-NEXT: sdiv w14, w15, w14 -; NONEON-NOSVE-NEXT: smov w15, v3.h[1] -; NONEON-NOSVE-NEXT: mov v5.h[5], w13 -; NONEON-NOSVE-NEXT: sdiv w15, w16, w15 -; NONEON-NOSVE-NEXT: smov w16, v3.h[0] -; NONEON-NOSVE-NEXT: mov v5.h[6], w14 -; NONEON-NOSVE-NEXT: sdiv w16, w17, w16 -; NONEON-NOSVE-NEXT: smov w17, v3.h[2] -; NONEON-NOSVE-NEXT: sdiv w17, w18, w17 -; NONEON-NOSVE-NEXT: smov w18, v3.h[3] -; NONEON-NOSVE-NEXT: fmov s4, w16 -; NONEON-NOSVE-NEXT: mov v4.h[1], w15 -; NONEON-NOSVE-NEXT: sdiv w18, w1, w18 -; NONEON-NOSVE-NEXT: smov w1, v3.h[4] -; NONEON-NOSVE-NEXT: mov v4.h[2], w17 -; NONEON-NOSVE-NEXT: sdiv w1, w2, w1 -; NONEON-NOSVE-NEXT: smov w2, v3.h[5] -; NONEON-NOSVE-NEXT: mov v4.h[3], w18 -; NONEON-NOSVE-NEXT: sdiv w2, w3, w2 -; NONEON-NOSVE-NEXT: smov w3, v3.h[6] -; NONEON-NOSVE-NEXT: mov v4.h[4], w1 -; NONEON-NOSVE-NEXT: sdiv w8, w4, w3 -; NONEON-NOSVE-NEXT: mov v4.h[5], w2 -; NONEON-NOSVE-NEXT: sdiv w9, w9, w10 -; NONEON-NOSVE-NEXT: smov w10, v1.h[7] -; NONEON-NOSVE-NEXT: mov v4.h[6], w8 -; NONEON-NOSVE-NEXT: sdiv w10, w11, w10 -; NONEON-NOSVE-NEXT: mov v4.h[7], w9 -; NONEON-NOSVE-NEXT: mov v5.h[7], w10 -; NONEON-NOSVE-NEXT: stp q4, q5, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = sdiv <16 x i16> %op1, %op2 @@ -735,21 +294,6 @@ define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: fmov w9, s0 -; NONEON-NOSVE-NEXT: mov w10, v0.s[1] -; NONEON-NOSVE-NEXT: sdiv w8, w9, w8 -; NONEON-NOSVE-NEXT: mov w9, v1.s[1] -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: mov v0.s[1], w9 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = sdiv <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -763,26 +307,6 @@ define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, v1.s[1] -; NONEON-NOSVE-NEXT: mov w9, v0.s[1] -; NONEON-NOSVE-NEXT: fmov w10, s0 -; NONEON-NOSVE-NEXT: mov w11, v0.s[2] -; NONEON-NOSVE-NEXT: mov w12, v0.s[3] -; NONEON-NOSVE-NEXT: sdiv w8, w9, w8 -; NONEON-NOSVE-NEXT: fmov w9, s1 -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: mov w10, v1.s[2] -; NONEON-NOSVE-NEXT: sdiv w10, w11, w10 -; NONEON-NOSVE-NEXT: mov w11, v1.s[3] -; NONEON-NOSVE-NEXT: fmov s0, w9 -; NONEON-NOSVE-NEXT: mov v0.s[1], w8 -; NONEON-NOSVE-NEXT: sdiv w8, w12, w11 -; NONEON-NOSVE-NEXT: mov v0.s[2], w10 -; NONEON-NOSVE-NEXT: mov v0.s[3], w8 -; NONEON-NOSVE-NEXT: ret %res = sdiv <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -798,45 +322,6 @@ define void @sdiv_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: sdiv z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: mov w9, v0.s[1] -; NONEON-NOSVE-NEXT: fmov w10, s0 -; NONEON-NOSVE-NEXT: mov w11, v0.s[2] -; NONEON-NOSVE-NEXT: mov w8, v1.s[1] -; NONEON-NOSVE-NEXT: mov w12, v2.s[1] -; NONEON-NOSVE-NEXT: fmov w13, s2 -; NONEON-NOSVE-NEXT: mov w14, v2.s[2] -; NONEON-NOSVE-NEXT: mov w15, v2.s[3] -; NONEON-NOSVE-NEXT: mov w16, v0.s[3] -; NONEON-NOSVE-NEXT: sdiv w8, w9, w8 -; NONEON-NOSVE-NEXT: fmov w9, s1 -; NONEON-NOSVE-NEXT: sdiv w9, w10, w9 -; NONEON-NOSVE-NEXT: mov w10, v1.s[2] -; NONEON-NOSVE-NEXT: sdiv w10, w11, w10 -; NONEON-NOSVE-NEXT: mov w11, v3.s[1] -; NONEON-NOSVE-NEXT: sdiv w11, w12, w11 -; NONEON-NOSVE-NEXT: fmov w12, s3 -; NONEON-NOSVE-NEXT: sdiv w12, w13, w12 -; NONEON-NOSVE-NEXT: mov w13, v3.s[2] -; NONEON-NOSVE-NEXT: sdiv w13, w14, w13 -; NONEON-NOSVE-NEXT: mov w14, v3.s[3] -; NONEON-NOSVE-NEXT: fmov s0, w12 -; NONEON-NOSVE-NEXT: mov v0.s[1], w11 -; NONEON-NOSVE-NEXT: sdiv w14, w15, w14 -; NONEON-NOSVE-NEXT: mov w15, v1.s[3] -; NONEON-NOSVE-NEXT: fmov s1, w9 -; NONEON-NOSVE-NEXT: mov v0.s[2], w13 -; NONEON-NOSVE-NEXT: mov v1.s[1], w8 -; NONEON-NOSVE-NEXT: mov v1.s[2], w10 -; NONEON-NOSVE-NEXT: sdiv w8, w16, w15 -; NONEON-NOSVE-NEXT: mov v0.s[3], w14 -; NONEON-NOSVE-NEXT: mov v1.s[3], w8 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = sdiv <8 x i32> %op1, %op2 @@ -853,16 +338,6 @@ define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: sdiv x8, x9, x8 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %res = sdiv <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -876,18 +351,6 @@ define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: mov x10, v0.d[1] -; NONEON-NOSVE-NEXT: sdiv x8, x9, x8 -; NONEON-NOSVE-NEXT: mov x9, v1.d[1] -; NONEON-NOSVE-NEXT: sdiv x9, x10, x9 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: mov v0.d[1], x9 -; NONEON-NOSVE-NEXT: ret %res = sdiv <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -903,29 +366,6 @@ define void @sdiv_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: sdiv z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: mov x10, v2.d[1] -; NONEON-NOSVE-NEXT: fmov x11, d2 -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: mov x12, v0.d[1] -; NONEON-NOSVE-NEXT: sdiv x8, x9, x8 -; NONEON-NOSVE-NEXT: mov x9, v3.d[1] -; NONEON-NOSVE-NEXT: sdiv x9, x10, x9 -; NONEON-NOSVE-NEXT: fmov x10, d3 -; NONEON-NOSVE-NEXT: sdiv x10, x11, x10 -; NONEON-NOSVE-NEXT: mov x11, v1.d[1] -; NONEON-NOSVE-NEXT: fmov d1, x8 -; NONEON-NOSVE-NEXT: sdiv x11, x12, x11 -; NONEON-NOSVE-NEXT: fmov d0, x10 -; NONEON-NOSVE-NEXT: mov v0.d[1], x9 -; NONEON-NOSVE-NEXT: mov v1.d[1], x11 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = sdiv <4 x i64> %op1, %op2 @@ -951,37 +391,6 @@ define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: umov w8, v1.h[1] -; NONEON-NOSVE-NEXT: umov w9, v0.h[1] -; NONEON-NOSVE-NEXT: umov w10, v0.h[0] -; NONEON-NOSVE-NEXT: umov w11, v0.h[2] -; NONEON-NOSVE-NEXT: umov w12, v0.h[3] -; NONEON-NOSVE-NEXT: and w8, w8, #0xff -; NONEON-NOSVE-NEXT: and w9, w9, #0xff -; NONEON-NOSVE-NEXT: and w10, w10, #0xff -; NONEON-NOSVE-NEXT: udiv w8, w9, w8 -; NONEON-NOSVE-NEXT: umov w9, v1.h[0] -; NONEON-NOSVE-NEXT: and w11, w11, #0xff -; NONEON-NOSVE-NEXT: and w9, w9, #0xff -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: umov w10, v1.h[2] -; NONEON-NOSVE-NEXT: and w10, w10, #0xff -; NONEON-NOSVE-NEXT: udiv w10, w11, w10 -; NONEON-NOSVE-NEXT: umov w11, v1.h[3] -; NONEON-NOSVE-NEXT: fmov s0, w9 -; NONEON-NOSVE-NEXT: mov v0.h[1], w8 -; NONEON-NOSVE-NEXT: and w9, w11, #0xff -; NONEON-NOSVE-NEXT: and w11, w12, #0xff -; NONEON-NOSVE-NEXT: udiv w8, w11, w9 -; NONEON-NOSVE-NEXT: mov v0.h[2], w10 -; NONEON-NOSVE-NEXT: mov v0.h[3], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = udiv <4 x i8> %op1, %op2 ret <4 x i8> %res } @@ -1009,45 +418,6 @@ define <8 x i8> @udiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: umov w8, v1.b[1] -; NONEON-NOSVE-NEXT: umov w9, v0.b[1] -; NONEON-NOSVE-NEXT: umov w10, v0.b[0] -; NONEON-NOSVE-NEXT: umov w11, v0.b[2] -; NONEON-NOSVE-NEXT: umov w12, v0.b[3] -; NONEON-NOSVE-NEXT: umov w13, v0.b[4] -; NONEON-NOSVE-NEXT: umov w14, v0.b[5] -; NONEON-NOSVE-NEXT: udiv w8, w9, w8 -; NONEON-NOSVE-NEXT: umov w9, v1.b[0] -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: umov w10, v1.b[2] -; NONEON-NOSVE-NEXT: udiv w10, w11, w10 -; NONEON-NOSVE-NEXT: umov w11, v1.b[3] -; NONEON-NOSVE-NEXT: fmov s2, w9 -; NONEON-NOSVE-NEXT: umov w9, v1.b[6] -; NONEON-NOSVE-NEXT: mov v2.b[1], w8 -; NONEON-NOSVE-NEXT: udiv w11, w12, w11 -; NONEON-NOSVE-NEXT: umov w12, v1.b[4] -; NONEON-NOSVE-NEXT: mov v2.b[2], w10 -; NONEON-NOSVE-NEXT: umov w10, v0.b[6] -; NONEON-NOSVE-NEXT: udiv w12, w13, w12 -; NONEON-NOSVE-NEXT: umov w13, v1.b[5] -; NONEON-NOSVE-NEXT: mov v2.b[3], w11 -; NONEON-NOSVE-NEXT: umov w11, v0.b[7] -; NONEON-NOSVE-NEXT: udiv w8, w14, w13 -; NONEON-NOSVE-NEXT: mov v2.b[4], w12 -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: umov w10, v1.b[7] -; NONEON-NOSVE-NEXT: mov v2.b[5], w8 -; NONEON-NOSVE-NEXT: udiv w8, w11, w10 -; NONEON-NOSVE-NEXT: mov v2.b[6], w9 -; NONEON-NOSVE-NEXT: mov v2.b[7], w8 -; NONEON-NOSVE-NEXT: fmov d0, d2 -; NONEON-NOSVE-NEXT: ret %res = udiv <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -1095,75 +465,6 @@ define <16 x i8> @udiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umov w8, v1.b[1] -; NONEON-NOSVE-NEXT: umov w9, v0.b[1] -; NONEON-NOSVE-NEXT: umov w10, v0.b[0] -; NONEON-NOSVE-NEXT: umov w11, v0.b[2] -; NONEON-NOSVE-NEXT: umov w12, v0.b[3] -; NONEON-NOSVE-NEXT: umov w13, v0.b[4] -; NONEON-NOSVE-NEXT: umov w14, v0.b[5] -; NONEON-NOSVE-NEXT: umov w15, v0.b[6] -; NONEON-NOSVE-NEXT: umov w16, v0.b[7] -; NONEON-NOSVE-NEXT: umov w17, v0.b[8] -; NONEON-NOSVE-NEXT: umov w18, v0.b[9] -; NONEON-NOSVE-NEXT: udiv w8, w9, w8 -; NONEON-NOSVE-NEXT: umov w9, v1.b[0] -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: umov w10, v1.b[2] -; NONEON-NOSVE-NEXT: udiv w10, w11, w10 -; NONEON-NOSVE-NEXT: umov w11, v1.b[3] -; NONEON-NOSVE-NEXT: fmov s2, w9 -; NONEON-NOSVE-NEXT: umov w9, v1.b[10] -; NONEON-NOSVE-NEXT: mov v2.b[1], w8 -; NONEON-NOSVE-NEXT: udiv w11, w12, w11 -; NONEON-NOSVE-NEXT: umov w12, v1.b[4] -; NONEON-NOSVE-NEXT: mov v2.b[2], w10 -; NONEON-NOSVE-NEXT: umov w10, v0.b[10] -; NONEON-NOSVE-NEXT: udiv w12, w13, w12 -; NONEON-NOSVE-NEXT: umov w13, v1.b[5] -; NONEON-NOSVE-NEXT: mov v2.b[3], w11 -; NONEON-NOSVE-NEXT: umov w11, v0.b[11] -; NONEON-NOSVE-NEXT: udiv w13, w14, w13 -; NONEON-NOSVE-NEXT: umov w14, v1.b[6] -; NONEON-NOSVE-NEXT: mov v2.b[4], w12 -; NONEON-NOSVE-NEXT: umov w12, v0.b[12] -; NONEON-NOSVE-NEXT: udiv w14, w15, w14 -; NONEON-NOSVE-NEXT: umov w15, v1.b[7] -; NONEON-NOSVE-NEXT: mov v2.b[5], w13 -; NONEON-NOSVE-NEXT: umov w13, v0.b[13] -; NONEON-NOSVE-NEXT: udiv w15, w16, w15 -; NONEON-NOSVE-NEXT: umov w16, v1.b[8] -; NONEON-NOSVE-NEXT: mov v2.b[6], w14 -; NONEON-NOSVE-NEXT: udiv w16, w17, w16 -; NONEON-NOSVE-NEXT: umov w17, v1.b[9] -; NONEON-NOSVE-NEXT: mov v2.b[7], w15 -; NONEON-NOSVE-NEXT: udiv w8, w18, w17 -; NONEON-NOSVE-NEXT: mov v2.b[8], w16 -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: umov w10, v1.b[11] -; NONEON-NOSVE-NEXT: mov v2.b[9], w8 -; NONEON-NOSVE-NEXT: udiv w10, w11, w10 -; NONEON-NOSVE-NEXT: umov w11, v1.b[12] -; NONEON-NOSVE-NEXT: mov v2.b[10], w9 -; NONEON-NOSVE-NEXT: umov w9, v1.b[14] -; NONEON-NOSVE-NEXT: udiv w11, w12, w11 -; NONEON-NOSVE-NEXT: umov w12, v1.b[13] -; NONEON-NOSVE-NEXT: mov v2.b[11], w10 -; NONEON-NOSVE-NEXT: umov w10, v1.b[15] -; NONEON-NOSVE-NEXT: udiv w8, w13, w12 -; NONEON-NOSVE-NEXT: umov w12, v0.b[14] -; NONEON-NOSVE-NEXT: mov v2.b[12], w11 -; NONEON-NOSVE-NEXT: umov w11, v0.b[15] -; NONEON-NOSVE-NEXT: udiv w9, w12, w9 -; NONEON-NOSVE-NEXT: mov v2.b[13], w8 -; NONEON-NOSVE-NEXT: udiv w8, w11, w10 -; NONEON-NOSVE-NEXT: mov v2.b[14], w9 -; NONEON-NOSVE-NEXT: mov v2.b[15], w8 -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = udiv <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -1244,163 +545,6 @@ define void @udiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: splice z3.b, p0, z3.b, z1.b ; CHECK-NEXT: stp q3, q2, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str x27, [sp, #-80]! // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x26, x25, [sp, #16] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x24, x23, [sp, #32] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 80 -; NONEON-NOSVE-NEXT: .cfi_offset w19, -8 -; NONEON-NOSVE-NEXT: .cfi_offset w20, -16 -; NONEON-NOSVE-NEXT: .cfi_offset w21, -24 -; NONEON-NOSVE-NEXT: .cfi_offset w22, -32 -; NONEON-NOSVE-NEXT: .cfi_offset w23, -40 -; NONEON-NOSVE-NEXT: .cfi_offset w24, -48 -; NONEON-NOSVE-NEXT: .cfi_offset w25, -56 -; NONEON-NOSVE-NEXT: .cfi_offset w26, -64 -; NONEON-NOSVE-NEXT: .cfi_offset w27, -80 -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x0] -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: umov w8, v1.b[1] -; NONEON-NOSVE-NEXT: umov w9, v0.b[1] -; NONEON-NOSVE-NEXT: umov w10, v0.b[0] -; NONEON-NOSVE-NEXT: umov w11, v0.b[2] -; NONEON-NOSVE-NEXT: umov w12, v0.b[3] -; NONEON-NOSVE-NEXT: umov w13, v0.b[4] -; NONEON-NOSVE-NEXT: umov w14, v0.b[5] -; NONEON-NOSVE-NEXT: umov w15, v0.b[6] -; NONEON-NOSVE-NEXT: umov w17, v0.b[8] -; NONEON-NOSVE-NEXT: umov w2, v0.b[10] -; NONEON-NOSVE-NEXT: umov w3, v0.b[11] -; NONEON-NOSVE-NEXT: umov w4, v0.b[12] -; NONEON-NOSVE-NEXT: udiv w8, w9, w8 -; NONEON-NOSVE-NEXT: umov w9, v1.b[0] -; NONEON-NOSVE-NEXT: umov w5, v0.b[13] -; NONEON-NOSVE-NEXT: umov w6, v0.b[14] -; NONEON-NOSVE-NEXT: umov w1, v3.b[1] -; NONEON-NOSVE-NEXT: umov w7, v2.b[0] -; NONEON-NOSVE-NEXT: umov w19, v2.b[2] -; NONEON-NOSVE-NEXT: umov w20, v2.b[3] -; NONEON-NOSVE-NEXT: umov w21, v2.b[4] -; NONEON-NOSVE-NEXT: umov w22, v2.b[5] -; NONEON-NOSVE-NEXT: umov w23, v2.b[6] -; NONEON-NOSVE-NEXT: umov w24, v2.b[7] -; NONEON-NOSVE-NEXT: umov w25, v2.b[8] -; NONEON-NOSVE-NEXT: umov w26, v2.b[9] -; NONEON-NOSVE-NEXT: umov w27, v2.b[10] -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: umov w10, v1.b[2] -; NONEON-NOSVE-NEXT: udiv w11, w11, w10 -; NONEON-NOSVE-NEXT: umov w10, v1.b[3] -; NONEON-NOSVE-NEXT: fmov s5, w9 -; NONEON-NOSVE-NEXT: umov w9, v3.b[11] -; NONEON-NOSVE-NEXT: mov v5.b[1], w8 -; NONEON-NOSVE-NEXT: udiv w10, w12, w10 -; NONEON-NOSVE-NEXT: umov w12, v1.b[4] -; NONEON-NOSVE-NEXT: mov v5.b[2], w11 -; NONEON-NOSVE-NEXT: umov w11, v2.b[11] -; NONEON-NOSVE-NEXT: udiv w13, w13, w12 -; NONEON-NOSVE-NEXT: umov w12, v1.b[5] -; NONEON-NOSVE-NEXT: mov v5.b[3], w10 -; NONEON-NOSVE-NEXT: umov w10, v3.b[12] -; NONEON-NOSVE-NEXT: udiv w12, w14, w12 -; NONEON-NOSVE-NEXT: umov w14, v1.b[6] -; NONEON-NOSVE-NEXT: mov v5.b[4], w13 -; NONEON-NOSVE-NEXT: umov w13, v2.b[14] -; NONEON-NOSVE-NEXT: udiv w16, w15, w14 -; NONEON-NOSVE-NEXT: umov w14, v1.b[7] -; NONEON-NOSVE-NEXT: umov w15, v0.b[7] -; NONEON-NOSVE-NEXT: mov v5.b[5], w12 -; NONEON-NOSVE-NEXT: umov w12, v2.b[13] -; NONEON-NOSVE-NEXT: udiv w14, w15, w14 -; NONEON-NOSVE-NEXT: umov w15, v1.b[8] -; NONEON-NOSVE-NEXT: mov v5.b[6], w16 -; NONEON-NOSVE-NEXT: udiv w18, w17, w15 -; NONEON-NOSVE-NEXT: umov w15, v1.b[9] -; NONEON-NOSVE-NEXT: umov w17, v0.b[9] -; NONEON-NOSVE-NEXT: mov v5.b[7], w14 -; NONEON-NOSVE-NEXT: udiv w17, w17, w15 -; NONEON-NOSVE-NEXT: umov w15, v1.b[10] -; NONEON-NOSVE-NEXT: mov v5.b[8], w18 -; NONEON-NOSVE-NEXT: udiv w15, w2, w15 -; NONEON-NOSVE-NEXT: umov w2, v1.b[11] -; NONEON-NOSVE-NEXT: mov v5.b[9], w17 -; NONEON-NOSVE-NEXT: udiv w2, w3, w2 -; NONEON-NOSVE-NEXT: umov w3, v1.b[12] -; NONEON-NOSVE-NEXT: mov v5.b[10], w15 -; NONEON-NOSVE-NEXT: udiv w3, w4, w3 -; NONEON-NOSVE-NEXT: umov w4, v1.b[13] -; NONEON-NOSVE-NEXT: mov v5.b[11], w2 -; NONEON-NOSVE-NEXT: udiv w4, w5, w4 -; NONEON-NOSVE-NEXT: umov w5, v1.b[14] -; NONEON-NOSVE-NEXT: mov v5.b[12], w3 -; NONEON-NOSVE-NEXT: udiv w5, w6, w5 -; NONEON-NOSVE-NEXT: umov w6, v2.b[1] -; NONEON-NOSVE-NEXT: mov v5.b[13], w4 -; NONEON-NOSVE-NEXT: udiv w1, w6, w1 -; NONEON-NOSVE-NEXT: umov w6, v3.b[0] -; NONEON-NOSVE-NEXT: mov v5.b[14], w5 -; NONEON-NOSVE-NEXT: udiv w6, w7, w6 -; NONEON-NOSVE-NEXT: umov w7, v3.b[2] -; NONEON-NOSVE-NEXT: udiv w7, w19, w7 -; NONEON-NOSVE-NEXT: umov w19, v3.b[3] -; NONEON-NOSVE-NEXT: fmov s4, w6 -; NONEON-NOSVE-NEXT: mov v4.b[1], w1 -; NONEON-NOSVE-NEXT: udiv w19, w20, w19 -; NONEON-NOSVE-NEXT: umov w20, v3.b[4] -; NONEON-NOSVE-NEXT: mov v4.b[2], w7 -; NONEON-NOSVE-NEXT: udiv w20, w21, w20 -; NONEON-NOSVE-NEXT: umov w21, v3.b[5] -; NONEON-NOSVE-NEXT: mov v4.b[3], w19 -; NONEON-NOSVE-NEXT: udiv w21, w22, w21 -; NONEON-NOSVE-NEXT: umov w22, v3.b[6] -; NONEON-NOSVE-NEXT: mov v4.b[4], w20 -; NONEON-NOSVE-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w22, w23, w22 -; NONEON-NOSVE-NEXT: umov w23, v3.b[7] -; NONEON-NOSVE-NEXT: mov v4.b[5], w21 -; NONEON-NOSVE-NEXT: udiv w23, w24, w23 -; NONEON-NOSVE-NEXT: umov w24, v3.b[8] -; NONEON-NOSVE-NEXT: mov v4.b[6], w22 -; NONEON-NOSVE-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w24, w25, w24 -; NONEON-NOSVE-NEXT: umov w25, v3.b[9] -; NONEON-NOSVE-NEXT: mov v4.b[7], w23 -; NONEON-NOSVE-NEXT: udiv w25, w26, w25 -; NONEON-NOSVE-NEXT: umov w26, v3.b[10] -; NONEON-NOSVE-NEXT: mov v4.b[8], w24 -; NONEON-NOSVE-NEXT: ldp x24, x23, [sp, #32] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w8, w27, w26 -; NONEON-NOSVE-NEXT: mov v4.b[9], w25 -; NONEON-NOSVE-NEXT: ldp x26, x25, [sp, #16] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w9, w11, w9 -; NONEON-NOSVE-NEXT: umov w11, v2.b[12] -; NONEON-NOSVE-NEXT: mov v4.b[10], w8 -; NONEON-NOSVE-NEXT: umov w8, v3.b[15] -; NONEON-NOSVE-NEXT: udiv w10, w11, w10 -; NONEON-NOSVE-NEXT: umov w11, v3.b[13] -; NONEON-NOSVE-NEXT: mov v4.b[11], w9 -; NONEON-NOSVE-NEXT: umov w9, v1.b[15] -; NONEON-NOSVE-NEXT: udiv w11, w12, w11 -; NONEON-NOSVE-NEXT: umov w12, v3.b[14] -; NONEON-NOSVE-NEXT: mov v4.b[12], w10 -; NONEON-NOSVE-NEXT: umov w10, v0.b[15] -; NONEON-NOSVE-NEXT: udiv w12, w13, w12 -; NONEON-NOSVE-NEXT: umov w13, v2.b[15] -; NONEON-NOSVE-NEXT: mov v4.b[13], w11 -; NONEON-NOSVE-NEXT: udiv w8, w13, w8 -; NONEON-NOSVE-NEXT: mov v4.b[14], w12 -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: mov v4.b[15], w8 -; NONEON-NOSVE-NEXT: mov v5.b[15], w9 -; NONEON-NOSVE-NEXT: stp q4, q5, [x0] -; NONEON-NOSVE-NEXT: ldr x27, [sp], #80 // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = udiv <32 x i8> %op1, %op2 @@ -1419,22 +563,6 @@ define <2 x i16> @udiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d2, #0x00ffff0000ffff -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v2.8b -; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: fmov w9, s0 -; NONEON-NOSVE-NEXT: mov w10, v0.s[1] -; NONEON-NOSVE-NEXT: udiv w8, w9, w8 -; NONEON-NOSVE-NEXT: mov w9, v1.s[1] -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: mov v0.s[1], w9 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = udiv <2 x i16> %op1, %op2 ret <2 x i16> %res } @@ -1451,29 +579,6 @@ define <4 x i16> @udiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: umov w8, v1.h[1] -; NONEON-NOSVE-NEXT: umov w9, v0.h[1] -; NONEON-NOSVE-NEXT: umov w10, v0.h[0] -; NONEON-NOSVE-NEXT: umov w11, v0.h[2] -; NONEON-NOSVE-NEXT: umov w12, v0.h[3] -; NONEON-NOSVE-NEXT: udiv w8, w9, w8 -; NONEON-NOSVE-NEXT: umov w9, v1.h[0] -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: umov w10, v1.h[2] -; NONEON-NOSVE-NEXT: udiv w10, w11, w10 -; NONEON-NOSVE-NEXT: umov w11, v1.h[3] -; NONEON-NOSVE-NEXT: fmov s0, w9 -; NONEON-NOSVE-NEXT: mov v0.h[1], w8 -; NONEON-NOSVE-NEXT: udiv w8, w12, w11 -; NONEON-NOSVE-NEXT: mov v0.h[2], w10 -; NONEON-NOSVE-NEXT: mov v0.h[3], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = udiv <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -1500,43 +605,6 @@ define <8 x i16> @udiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umov w8, v1.h[1] -; NONEON-NOSVE-NEXT: umov w9, v0.h[1] -; NONEON-NOSVE-NEXT: umov w10, v0.h[0] -; NONEON-NOSVE-NEXT: umov w11, v0.h[2] -; NONEON-NOSVE-NEXT: umov w12, v0.h[3] -; NONEON-NOSVE-NEXT: umov w13, v0.h[4] -; NONEON-NOSVE-NEXT: umov w14, v0.h[5] -; NONEON-NOSVE-NEXT: udiv w8, w9, w8 -; NONEON-NOSVE-NEXT: umov w9, v1.h[0] -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: umov w10, v1.h[2] -; NONEON-NOSVE-NEXT: udiv w10, w11, w10 -; NONEON-NOSVE-NEXT: umov w11, v1.h[3] -; NONEON-NOSVE-NEXT: fmov s2, w9 -; NONEON-NOSVE-NEXT: umov w9, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[1], w8 -; NONEON-NOSVE-NEXT: udiv w11, w12, w11 -; NONEON-NOSVE-NEXT: umov w12, v1.h[4] -; NONEON-NOSVE-NEXT: mov v2.h[2], w10 -; NONEON-NOSVE-NEXT: umov w10, v0.h[6] -; NONEON-NOSVE-NEXT: udiv w12, w13, w12 -; NONEON-NOSVE-NEXT: umov w13, v1.h[5] -; NONEON-NOSVE-NEXT: mov v2.h[3], w11 -; NONEON-NOSVE-NEXT: umov w11, v0.h[7] -; NONEON-NOSVE-NEXT: udiv w8, w14, w13 -; NONEON-NOSVE-NEXT: mov v2.h[4], w12 -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: umov w10, v1.h[7] -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: udiv w8, w11, w10 -; NONEON-NOSVE-NEXT: mov v2.h[6], w9 -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = udiv <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -1577,79 +645,6 @@ define void @udiv_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: splice z3.h, p0, z3.h, z1.h ; CHECK-NEXT: stp q3, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x0] -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: umov w8, v1.h[1] -; NONEON-NOSVE-NEXT: umov w9, v0.h[1] -; NONEON-NOSVE-NEXT: umov w10, v0.h[0] -; NONEON-NOSVE-NEXT: umov w11, v0.h[2] -; NONEON-NOSVE-NEXT: umov w12, v0.h[3] -; NONEON-NOSVE-NEXT: umov w13, v0.h[4] -; NONEON-NOSVE-NEXT: umov w14, v0.h[5] -; NONEON-NOSVE-NEXT: umov w15, v0.h[6] -; NONEON-NOSVE-NEXT: umov w16, v2.h[1] -; NONEON-NOSVE-NEXT: umov w17, v2.h[0] -; NONEON-NOSVE-NEXT: umov w18, v2.h[2] -; NONEON-NOSVE-NEXT: umov w1, v2.h[3] -; NONEON-NOSVE-NEXT: udiv w8, w9, w8 -; NONEON-NOSVE-NEXT: umov w9, v1.h[0] -; NONEON-NOSVE-NEXT: umov w2, v2.h[4] -; NONEON-NOSVE-NEXT: umov w3, v2.h[5] -; NONEON-NOSVE-NEXT: umov w4, v2.h[6] -; NONEON-NOSVE-NEXT: udiv w10, w10, w9 -; NONEON-NOSVE-NEXT: umov w9, v1.h[2] -; NONEON-NOSVE-NEXT: udiv w9, w11, w9 -; NONEON-NOSVE-NEXT: umov w11, v1.h[3] -; NONEON-NOSVE-NEXT: fmov s5, w10 -; NONEON-NOSVE-NEXT: umov w10, v3.h[7] -; NONEON-NOSVE-NEXT: mov v5.h[1], w8 -; NONEON-NOSVE-NEXT: udiv w11, w12, w11 -; NONEON-NOSVE-NEXT: umov w12, v1.h[4] -; NONEON-NOSVE-NEXT: mov v5.h[2], w9 -; NONEON-NOSVE-NEXT: umov w9, v2.h[7] -; NONEON-NOSVE-NEXT: udiv w12, w13, w12 -; NONEON-NOSVE-NEXT: umov w13, v1.h[5] -; NONEON-NOSVE-NEXT: mov v5.h[3], w11 -; NONEON-NOSVE-NEXT: umov w11, v0.h[7] -; NONEON-NOSVE-NEXT: udiv w13, w14, w13 -; NONEON-NOSVE-NEXT: umov w14, v1.h[6] -; NONEON-NOSVE-NEXT: mov v5.h[4], w12 -; NONEON-NOSVE-NEXT: udiv w14, w15, w14 -; NONEON-NOSVE-NEXT: umov w15, v3.h[1] -; NONEON-NOSVE-NEXT: mov v5.h[5], w13 -; NONEON-NOSVE-NEXT: udiv w15, w16, w15 -; NONEON-NOSVE-NEXT: umov w16, v3.h[0] -; NONEON-NOSVE-NEXT: mov v5.h[6], w14 -; NONEON-NOSVE-NEXT: udiv w16, w17, w16 -; NONEON-NOSVE-NEXT: umov w17, v3.h[2] -; NONEON-NOSVE-NEXT: udiv w17, w18, w17 -; NONEON-NOSVE-NEXT: umov w18, v3.h[3] -; NONEON-NOSVE-NEXT: fmov s4, w16 -; NONEON-NOSVE-NEXT: mov v4.h[1], w15 -; NONEON-NOSVE-NEXT: udiv w18, w1, w18 -; NONEON-NOSVE-NEXT: umov w1, v3.h[4] -; NONEON-NOSVE-NEXT: mov v4.h[2], w17 -; NONEON-NOSVE-NEXT: udiv w1, w2, w1 -; NONEON-NOSVE-NEXT: umov w2, v3.h[5] -; NONEON-NOSVE-NEXT: mov v4.h[3], w18 -; NONEON-NOSVE-NEXT: udiv w2, w3, w2 -; NONEON-NOSVE-NEXT: umov w3, v3.h[6] -; NONEON-NOSVE-NEXT: mov v4.h[4], w1 -; NONEON-NOSVE-NEXT: udiv w8, w4, w3 -; NONEON-NOSVE-NEXT: mov v4.h[5], w2 -; NONEON-NOSVE-NEXT: udiv w9, w9, w10 -; NONEON-NOSVE-NEXT: umov w10, v1.h[7] -; NONEON-NOSVE-NEXT: mov v4.h[6], w8 -; NONEON-NOSVE-NEXT: udiv w10, w11, w10 -; NONEON-NOSVE-NEXT: mov v4.h[7], w9 -; NONEON-NOSVE-NEXT: mov v5.h[7], w10 -; NONEON-NOSVE-NEXT: stp q4, q5, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = udiv <16 x i16> %op1, %op2 @@ -1666,21 +661,6 @@ define <2 x i32> @udiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: fmov w9, s0 -; NONEON-NOSVE-NEXT: mov w10, v0.s[1] -; NONEON-NOSVE-NEXT: udiv w8, w9, w8 -; NONEON-NOSVE-NEXT: mov w9, v1.s[1] -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: mov v0.s[1], w9 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = udiv <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -1694,26 +674,6 @@ define <4 x i32> @udiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, v1.s[1] -; NONEON-NOSVE-NEXT: mov w9, v0.s[1] -; NONEON-NOSVE-NEXT: fmov w10, s0 -; NONEON-NOSVE-NEXT: mov w11, v0.s[2] -; NONEON-NOSVE-NEXT: mov w12, v0.s[3] -; NONEON-NOSVE-NEXT: udiv w8, w9, w8 -; NONEON-NOSVE-NEXT: fmov w9, s1 -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: mov w10, v1.s[2] -; NONEON-NOSVE-NEXT: udiv w10, w11, w10 -; NONEON-NOSVE-NEXT: mov w11, v1.s[3] -; NONEON-NOSVE-NEXT: fmov s0, w9 -; NONEON-NOSVE-NEXT: mov v0.s[1], w8 -; NONEON-NOSVE-NEXT: udiv w8, w12, w11 -; NONEON-NOSVE-NEXT: mov v0.s[2], w10 -; NONEON-NOSVE-NEXT: mov v0.s[3], w8 -; NONEON-NOSVE-NEXT: ret %res = udiv <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -1729,45 +689,6 @@ define void @udiv_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: udiv z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: mov w9, v0.s[1] -; NONEON-NOSVE-NEXT: fmov w10, s0 -; NONEON-NOSVE-NEXT: mov w11, v0.s[2] -; NONEON-NOSVE-NEXT: mov w8, v1.s[1] -; NONEON-NOSVE-NEXT: mov w12, v2.s[1] -; NONEON-NOSVE-NEXT: fmov w13, s2 -; NONEON-NOSVE-NEXT: mov w14, v2.s[2] -; NONEON-NOSVE-NEXT: mov w15, v2.s[3] -; NONEON-NOSVE-NEXT: mov w16, v0.s[3] -; NONEON-NOSVE-NEXT: udiv w8, w9, w8 -; NONEON-NOSVE-NEXT: fmov w9, s1 -; NONEON-NOSVE-NEXT: udiv w9, w10, w9 -; NONEON-NOSVE-NEXT: mov w10, v1.s[2] -; NONEON-NOSVE-NEXT: udiv w10, w11, w10 -; NONEON-NOSVE-NEXT: mov w11, v3.s[1] -; NONEON-NOSVE-NEXT: udiv w11, w12, w11 -; NONEON-NOSVE-NEXT: fmov w12, s3 -; NONEON-NOSVE-NEXT: udiv w12, w13, w12 -; NONEON-NOSVE-NEXT: mov w13, v3.s[2] -; NONEON-NOSVE-NEXT: udiv w13, w14, w13 -; NONEON-NOSVE-NEXT: mov w14, v3.s[3] -; NONEON-NOSVE-NEXT: fmov s0, w12 -; NONEON-NOSVE-NEXT: mov v0.s[1], w11 -; NONEON-NOSVE-NEXT: udiv w14, w15, w14 -; NONEON-NOSVE-NEXT: mov w15, v1.s[3] -; NONEON-NOSVE-NEXT: fmov s1, w9 -; NONEON-NOSVE-NEXT: mov v0.s[2], w13 -; NONEON-NOSVE-NEXT: mov v1.s[1], w8 -; NONEON-NOSVE-NEXT: mov v1.s[2], w10 -; NONEON-NOSVE-NEXT: udiv w8, w16, w15 -; NONEON-NOSVE-NEXT: mov v0.s[3], w14 -; NONEON-NOSVE-NEXT: mov v1.s[3], w8 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = udiv <8 x i32> %op1, %op2 @@ -1784,16 +705,6 @@ define <1 x i64> @udiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: udiv x8, x9, x8 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %res = udiv <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -1807,18 +718,6 @@ define <2 x i64> @udiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: mov x10, v0.d[1] -; NONEON-NOSVE-NEXT: udiv x8, x9, x8 -; NONEON-NOSVE-NEXT: mov x9, v1.d[1] -; NONEON-NOSVE-NEXT: udiv x9, x10, x9 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: mov v0.d[1], x9 -; NONEON-NOSVE-NEXT: ret %res = udiv <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -1834,29 +733,6 @@ define void @udiv_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: udiv z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: mov x10, v2.d[1] -; NONEON-NOSVE-NEXT: fmov x11, d2 -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: mov x12, v0.d[1] -; NONEON-NOSVE-NEXT: udiv x8, x9, x8 -; NONEON-NOSVE-NEXT: mov x9, v3.d[1] -; NONEON-NOSVE-NEXT: udiv x9, x10, x9 -; NONEON-NOSVE-NEXT: fmov x10, d3 -; NONEON-NOSVE-NEXT: udiv x10, x11, x10 -; NONEON-NOSVE-NEXT: mov x11, v1.d[1] -; NONEON-NOSVE-NEXT: fmov d1, x8 -; NONEON-NOSVE-NEXT: udiv x11, x12, x11 -; NONEON-NOSVE-NEXT: fmov d0, x10 -; NONEON-NOSVE-NEXT: mov v0.d[1], x9 -; NONEON-NOSVE-NEXT: mov v1.d[1], x11 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = udiv <4 x i64> %op1, %op2 @@ -1902,27 +778,6 @@ define void @udiv_constantsplat_v8i32(ptr %a) { ; SVE2-NEXT: lsr z0.s, z0.s, #6 ; SVE2-NEXT: stp q1, q0, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: udiv_constantsplat_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #8969 // =0x2309 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: movk w8, #22765, lsl #16 -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: umull2 v3.2d, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: umull v4.2d, v1.2s, v0.2s -; NONEON-NOSVE-NEXT: umull2 v5.2d, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: umull v0.2d, v2.2s, v0.2s -; NONEON-NOSVE-NEXT: uzp2 v3.4s, v4.4s, v3.4s -; NONEON-NOSVE-NEXT: uzp2 v0.4s, v0.4s, v5.4s -; NONEON-NOSVE-NEXT: sub v1.4s, v1.4s, v3.4s -; NONEON-NOSVE-NEXT: sub v2.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: usra v3.4s, v1.4s, #1 -; NONEON-NOSVE-NEXT: usra v0.4s, v2.4s, #1 -; NONEON-NOSVE-NEXT: ushr v1.4s, v3.4s, #6 -; NONEON-NOSVE-NEXT: ushr v0.4s, v0.4s, #6 -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %res = udiv <8 x i32> %op1, store <8 x i32> %res, ptr %a diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll index e320fed2a498..c7a89612d278 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll @@ -2,7 +2,6 @@ ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE ; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2 ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2 -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -27,22 +26,6 @@ define void @sext_v8i1_v8i32(<8 x i1> %a, ptr %out) { ; CHECK-NEXT: asr z0.s, z0.s, #31 ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v8i1_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: shl v0.4s, v0.4s, #31 -; NONEON-NOSVE-NEXT: shl v1.4s, v1.4s, #31 -; NONEON-NOSVE-NEXT: cmlt v0.4s, v0.4s, #0 -; NONEON-NOSVE-NEXT: cmlt v1.4s, v1.4s, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = sext <8 x i1> %a to <8 x i32> store <8 x i32> %b, ptr %out ret void @@ -69,22 +52,6 @@ define void @sext_v4i3_v4i64(<4 x i3> %a, ptr %out) { ; CHECK-NEXT: asr z0.d, z0.d, #61 ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v4i3_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: shl v0.2d, v0.2d, #61 -; NONEON-NOSVE-NEXT: shl v1.2d, v1.2d, #61 -; NONEON-NOSVE-NEXT: sshr v0.2d, v0.2d, #61 -; NONEON-NOSVE-NEXT: sshr v1.2d, v1.2d, #61 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = sext <4 x i3> %a to <4 x i64> store <4 x i64> %b, ptr %out ret void @@ -103,17 +70,6 @@ define void @sext_v16i8_v16i16(<16 x i8> %a, ptr %out) { ; CHECK-NEXT: sunpklo z0.h, z0.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v16i8_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: sshll v1.8h, v1.8b, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = sext <16 x i8> %a to <16 x i16> store <16 x i16>%b, ptr %out ret void @@ -135,24 +91,6 @@ define void @sext_v32i8_v32i16(ptr %in, ptr %out) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v32i8_v32i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v1.8h, v1.8b, #0 -; NONEON-NOSVE-NEXT: sshll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: sshll v2.8h, v2.8b, #0 -; NONEON-NOSVE-NEXT: sshll v3.8h, v3.8b, #0 -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %a = load <32 x i8>, ptr %in %b = add <32 x i8> %a, %a %c = sext <32 x i8> %b to <32 x i16> @@ -174,18 +112,6 @@ define void @sext_v8i8_v8i32(<8 x i8> %a, ptr %out) { ; CHECK-NEXT: sunpklo z0.s, z0.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v8i8_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sshll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = sext <8 x i8> %a to <8 x i32> store <8 x i32>%b, ptr %out ret void @@ -207,25 +133,6 @@ define void @sext_v16i8_v16i32(<16 x i8> %a, ptr %out) { ; CHECK-NEXT: stp q2, q1, [x0] ; CHECK-NEXT: stp q3, q0, [x0, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v16i8_v16i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-48]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: sshll v1.8h, v1.8b, #0 -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #16] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: sshll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q2, [x0] -; NONEON-NOSVE-NEXT: stp q1, q3, [x0, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #48 -; NONEON-NOSVE-NEXT: ret %b = sext <16 x i8> %a to <16 x i32> store <16 x i32> %b, ptr %out ret void @@ -260,40 +167,6 @@ define void @sext_v32i8_v32i32(ptr %in, ptr %out) { ; CHECK-NEXT: stp q6, q0, [x1, #96] ; CHECK-NEXT: stp q7, q1, [x1, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v32i8_v32i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-96]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: sshll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: sshll v1.8h, v1.8b, #0 -; NONEON-NOSVE-NEXT: sshll v2.8h, v2.8b, #0 -; NONEON-NOSVE-NEXT: sshll v3.8h, v3.8b, #0 -; NONEON-NOSVE-NEXT: stp q2, q0, [sp, #32] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: stp q3, q1, [sp, #64] -; NONEON-NOSVE-NEXT: ldr d5, [sp, #56] -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ldr d4, [sp, #88] -; NONEON-NOSVE-NEXT: ldr d6, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d7, [sp, #72] -; NONEON-NOSVE-NEXT: sshll v5.4s, v5.4h, #0 -; NONEON-NOSVE-NEXT: sshll v4.4s, v4.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q5, [x1] -; NONEON-NOSVE-NEXT: sshll v0.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: sshll v2.4s, v6.4h, #0 -; NONEON-NOSVE-NEXT: stp q1, q4, [x1, #64] -; NONEON-NOSVE-NEXT: sshll v1.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: sshll v3.4s, v7.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q2, [x1, #32] -; NONEON-NOSVE-NEXT: stp q1, q3, [x1, #96] -; NONEON-NOSVE-NEXT: add sp, sp, #96 -; NONEON-NOSVE-NEXT: ret %a = load <32 x i8>, ptr %in %b = add <32 x i8> %a, %a %c = sext <32 x i8> %b to <32 x i32> @@ -321,22 +194,6 @@ define void @sext_v4i8_v4i64(<4 x i8> %a, ptr %out) { ; CHECK-NEXT: sxtb z0.d, p0/m, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v4i8_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: shl v0.2d, v0.2d, #56 -; NONEON-NOSVE-NEXT: shl v1.2d, v1.2d, #56 -; NONEON-NOSVE-NEXT: sshr v0.2d, v0.2d, #56 -; NONEON-NOSVE-NEXT: sshr v1.2d, v1.2d, #56 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = sext <4 x i8> %a to <4 x i64> store <4 x i64>%b, ptr %out ret void @@ -359,26 +216,6 @@ define void @sext_v8i8_v8i64(<8 x i8> %a, ptr %out) { ; CHECK-NEXT: stp q2, q1, [x0] ; CHECK-NEXT: stp q3, q0, [x0, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v8i8_v8i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sshll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-48]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #16] -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: sshll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: sshll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q2, [x0] -; NONEON-NOSVE-NEXT: stp q1, q3, [x0, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #48 -; NONEON-NOSVE-NEXT: ret %b = sext <8 x i8> %a to <8 x i64> store <8 x i64>%b, ptr %out ret void @@ -416,41 +253,6 @@ define void @sext_v16i8_v16i64(<16 x i8> %a, ptr %out) { ; CHECK-NEXT: stp q1, q4, [x0, #32] ; CHECK-NEXT: stp q0, q2, [x0, #96] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v16i8_v16i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-112]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 112 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: sshll v1.8h, v1.8b, #0 -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #16] -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #40] -; NONEON-NOSVE-NEXT: sshll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: stp q2, q1, [sp, #48] -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: stp q3, q0, [sp, #80] -; NONEON-NOSVE-NEXT: ldr d5, [sp, #72] -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ldr d4, [sp, #104] -; NONEON-NOSVE-NEXT: ldr d6, [sp, #56] -; NONEON-NOSVE-NEXT: ldr d7, [sp, #88] -; NONEON-NOSVE-NEXT: sshll v5.2d, v5.2s, #0 -; NONEON-NOSVE-NEXT: sshll v4.2d, v4.2s, #0 -; NONEON-NOSVE-NEXT: stp q1, q5, [x0, #64] -; NONEON-NOSVE-NEXT: sshll v1.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: sshll v2.2d, v6.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q4, [x0] -; NONEON-NOSVE-NEXT: sshll v0.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: sshll v3.2d, v7.2s, #0 -; NONEON-NOSVE-NEXT: stp q1, q2, [x0, #96] -; NONEON-NOSVE-NEXT: stp q0, q3, [x0, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #112 -; NONEON-NOSVE-NEXT: ret %b = sext <16 x i8> %a to <16 x i64> store <16 x i64> %b, ptr %out ret void @@ -519,73 +321,6 @@ define void @sext_v32i8_v32i64(ptr %in, ptr %out) { ; CHECK-NEXT: stp q0, q2, [x1, #224] ; CHECK-NEXT: stp q3, q1, [x1, #96] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v32i8_v32i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub sp, sp, #224 -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 224 -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [sp] -; NONEON-NOSVE-NEXT: sshll v5.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: sshll v6.8h, v1.8b, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v3.8h, v2.8b, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: sshll v4.8h, v2.8b, #0 -; NONEON-NOSVE-NEXT: stp q3, q5, [sp, #32] -; NONEON-NOSVE-NEXT: sshll v5.4s, v5.4h, #0 -; NONEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #56] -; NONEON-NOSVE-NEXT: ldr d0, [sp, #40] -; NONEON-NOSVE-NEXT: stp q4, q6, [sp, #64] -; NONEON-NOSVE-NEXT: sshll v6.4s, v6.4h, #0 -; NONEON-NOSVE-NEXT: sshll v4.4s, v4.4h, #0 -; NONEON-NOSVE-NEXT: ldr d7, [sp, #88] -; NONEON-NOSVE-NEXT: sshll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #72] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v7.4s, v7.4h, #0 -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q2, q5, [sp, #128] -; NONEON-NOSVE-NEXT: sshll v5.2d, v5.2s, #0 -; NONEON-NOSVE-NEXT: sshll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: ldr d19, [sp, #152] -; NONEON-NOSVE-NEXT: stp q0, q3, [sp, #96] -; NONEON-NOSVE-NEXT: ldr d20, [sp, #136] -; NONEON-NOSVE-NEXT: stp q1, q4, [sp, #160] -; NONEON-NOSVE-NEXT: ldr d17, [sp, #104] -; NONEON-NOSVE-NEXT: ldr d21, [sp, #120] -; NONEON-NOSVE-NEXT: stp q7, q6, [sp, #192] -; NONEON-NOSVE-NEXT: sshll v6.2d, v6.2s, #0 -; NONEON-NOSVE-NEXT: sshll v19.2d, v19.2s, #0 -; NONEON-NOSVE-NEXT: ldr d16, [sp, #216] -; NONEON-NOSVE-NEXT: ldr d22, [sp, #200] -; NONEON-NOSVE-NEXT: ldr d23, [sp, #184] -; NONEON-NOSVE-NEXT: ldr d18, [sp, #168] -; NONEON-NOSVE-NEXT: sshll v4.2d, v4.2s, #0 -; NONEON-NOSVE-NEXT: sshll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: sshll v16.2d, v16.2s, #0 -; NONEON-NOSVE-NEXT: stp q5, q19, [x1] -; NONEON-NOSVE-NEXT: sshll v5.2d, v7.2s, #0 -; NONEON-NOSVE-NEXT: sshll v7.2d, v22.2s, #0 -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: stp q6, q16, [x1, #128] -; NONEON-NOSVE-NEXT: sshll v6.2d, v23.2s, #0 -; NONEON-NOSVE-NEXT: stp q5, q7, [x1, #160] -; NONEON-NOSVE-NEXT: sshll v5.2d, v20.2s, #0 -; NONEON-NOSVE-NEXT: stp q4, q6, [x1, #192] -; NONEON-NOSVE-NEXT: sshll v4.2d, v21.2s, #0 -; NONEON-NOSVE-NEXT: stp q2, q5, [x1, #32] -; NONEON-NOSVE-NEXT: sshll v2.2d, v17.2s, #0 -; NONEON-NOSVE-NEXT: stp q3, q4, [x1, #64] -; NONEON-NOSVE-NEXT: sshll v3.2d, v18.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q2, [x1, #96] -; NONEON-NOSVE-NEXT: stp q1, q3, [x1, #224] -; NONEON-NOSVE-NEXT: add sp, sp, #224 -; NONEON-NOSVE-NEXT: ret %a = load <32 x i8>, ptr %in %b = add <32 x i8> %a, %a %c = sext <32 x i8> %b to <32 x i64> @@ -606,17 +341,6 @@ define void @sext_v8i16_v8i32(<8 x i16> %a, ptr %out) { ; CHECK-NEXT: sunpklo z0.s, z0.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v8i16_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = sext <8 x i16> %a to <8 x i32> store <8 x i32>%b, ptr %out ret void @@ -637,24 +361,6 @@ define void @sext_v16i16_v16i32(ptr %in, ptr %out) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v16i16_v16i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v0.8h -; NONEON-NOSVE-NEXT: add v1.8h, v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %a = load <16 x i16>, ptr %in %b = add <16 x i16> %a, %a %c = sext <16 x i16> %b to <16 x i32> @@ -676,18 +382,6 @@ define void @sext_v4i16_v4i64(<4 x i16> %a, ptr %out) { ; CHECK-NEXT: sunpklo z0.d, z0.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v4i16_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = sext <4 x i16> %a to <4 x i64> store <4 x i64>%b, ptr %out ret void @@ -709,25 +403,6 @@ define void @sext_v8i16_v8i64(<8 x i16> %a, ptr %out) { ; CHECK-NEXT: stp q2, q1, [x0] ; CHECK-NEXT: stp q3, q0, [x0, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v8i16_v8i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-48]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #16] -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: sshll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: sshll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q2, [x0] -; NONEON-NOSVE-NEXT: stp q1, q3, [x0, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #48 -; NONEON-NOSVE-NEXT: ret %b = sext <8 x i16> %a to <8 x i64> store <8 x i64>%b, ptr %out ret void @@ -762,40 +437,6 @@ define void @sext_v16i16_v16i64(ptr %in, ptr %out) { ; CHECK-NEXT: stp q6, q0, [x1, #96] ; CHECK-NEXT: stp q7, q1, [x1, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v16i16_v16i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v0.8h -; NONEON-NOSVE-NEXT: add v1.8h, v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-96]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: sshll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: stp q2, q0, [sp, #32] -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: stp q3, q1, [sp, #64] -; NONEON-NOSVE-NEXT: ldr d5, [sp, #56] -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ldr d4, [sp, #88] -; NONEON-NOSVE-NEXT: ldr d6, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d7, [sp, #72] -; NONEON-NOSVE-NEXT: sshll v5.2d, v5.2s, #0 -; NONEON-NOSVE-NEXT: sshll v4.2d, v4.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q5, [x1] -; NONEON-NOSVE-NEXT: sshll v0.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: sshll v2.2d, v6.2s, #0 -; NONEON-NOSVE-NEXT: stp q1, q4, [x1, #64] -; NONEON-NOSVE-NEXT: sshll v1.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: sshll v3.2d, v7.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q2, [x1, #32] -; NONEON-NOSVE-NEXT: stp q1, q3, [x1, #96] -; NONEON-NOSVE-NEXT: add sp, sp, #96 -; NONEON-NOSVE-NEXT: ret %a = load <16 x i16>, ptr %in %b = add <16 x i16> %a, %a %c = sext <16 x i16> %b to <16 x i64> @@ -816,17 +457,6 @@ define void @sext_v4i32_v4i64(<4 x i32> %a, ptr %out) { ; CHECK-NEXT: sunpklo z0.d, z0.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v4i32_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = sext <4 x i32> %a to <4 x i64> store <4 x i64>%b, ptr %out ret void @@ -847,24 +477,6 @@ define void @sext_v8i32_v8i64(ptr %in, ptr %out) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sext_v8i32_v8i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add v0.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: add v1.4s, v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: sshll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: sshll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %a = load <8 x i32>, ptr %in %b = add <8 x i32> %a, %a %c = sext <8 x i32> %b to <8 x i64> @@ -885,17 +497,6 @@ define void @zext_v16i8_v16i16(<16 x i8> %a, ptr %out) { ; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v16i8_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: ushll v1.8h, v1.8b, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = zext <16 x i8> %a to <16 x i16> store <16 x i16>%b, ptr %out ret void @@ -917,24 +518,6 @@ define void @zext_v32i8_v32i16(ptr %in, ptr %out) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v32i8_v32i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v1.8h, v1.8b, #0 -; NONEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: ushll v2.8h, v2.8b, #0 -; NONEON-NOSVE-NEXT: ushll v3.8h, v3.8b, #0 -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %a = load <32 x i8>, ptr %in %b = add <32 x i8> %a, %a %c = zext <32 x i8> %b to <32 x i16> @@ -956,18 +539,6 @@ define void @zext_v8i8_v8i32(<8 x i8> %a, ptr %out) { ; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v8i8_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = zext <8 x i8> %a to <8 x i32> store <8 x i32>%b, ptr %out ret void @@ -989,25 +560,6 @@ define void @zext_v16i8_v16i32(<16 x i8> %a, ptr %out) { ; CHECK-NEXT: stp q2, q1, [x0] ; CHECK-NEXT: stp q3, q0, [x0, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v16i8_v16i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-48]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: ushll v1.8h, v1.8b, #0 -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #16] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q2, [x0] -; NONEON-NOSVE-NEXT: stp q1, q3, [x0, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #48 -; NONEON-NOSVE-NEXT: ret %b = zext <16 x i8> %a to <16 x i32> store <16 x i32> %b, ptr %out ret void @@ -1042,40 +594,6 @@ define void @zext_v32i8_v32i32(ptr %in, ptr %out) { ; CHECK-NEXT: stp q6, q0, [x1, #96] ; CHECK-NEXT: stp q7, q1, [x1, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v32i8_v32i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-96]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: ushll v1.8h, v1.8b, #0 -; NONEON-NOSVE-NEXT: ushll v2.8h, v2.8b, #0 -; NONEON-NOSVE-NEXT: ushll v3.8h, v3.8b, #0 -; NONEON-NOSVE-NEXT: stp q2, q0, [sp, #32] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: stp q3, q1, [sp, #64] -; NONEON-NOSVE-NEXT: ldr d5, [sp, #56] -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ldr d4, [sp, #88] -; NONEON-NOSVE-NEXT: ldr d6, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d7, [sp, #72] -; NONEON-NOSVE-NEXT: ushll v5.4s, v5.4h, #0 -; NONEON-NOSVE-NEXT: ushll v4.4s, v4.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q5, [x1] -; NONEON-NOSVE-NEXT: ushll v0.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: ushll v2.4s, v6.4h, #0 -; NONEON-NOSVE-NEXT: stp q1, q4, [x1, #64] -; NONEON-NOSVE-NEXT: ushll v1.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: ushll v3.4s, v7.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q2, [x1, #32] -; NONEON-NOSVE-NEXT: stp q1, q3, [x1, #96] -; NONEON-NOSVE-NEXT: add sp, sp, #96 -; NONEON-NOSVE-NEXT: ret %a = load <32 x i8>, ptr %in %b = add <32 x i8> %a, %a %c = zext <32 x i8> %b to <32 x i32> @@ -1101,20 +619,6 @@ define void @zext_v4i8_v4i64(<4 x i8> %a, ptr %out) { ; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v4i8_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d1, #0xff00ff00ff00ff -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = zext <4 x i8> %a to <4 x i64> store <4 x i64>%b, ptr %out ret void @@ -1137,26 +641,6 @@ define void @zext_v8i8_v8i64(<8 x i8> %a, ptr %out) { ; CHECK-NEXT: stp q2, q1, [x0] ; CHECK-NEXT: stp q3, q0, [x0, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v8i8_v8i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-48]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #16] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: ushll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: ushll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q2, [x0] -; NONEON-NOSVE-NEXT: stp q1, q3, [x0, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #48 -; NONEON-NOSVE-NEXT: ret %b = zext <8 x i8> %a to <8 x i64> store <8 x i64>%b, ptr %out ret void @@ -1194,41 +678,6 @@ define void @zext_v16i8_v16i64(<16 x i8> %a, ptr %out) { ; CHECK-NEXT: stp q1, q4, [x0, #32] ; CHECK-NEXT: stp q0, q2, [x0, #96] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v16i8_v16i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-112]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 112 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: ushll v1.8h, v1.8b, #0 -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #16] -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #40] -; NONEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: stp q2, q1, [sp, #48] -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: stp q3, q0, [sp, #80] -; NONEON-NOSVE-NEXT: ldr d5, [sp, #72] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ldr d4, [sp, #104] -; NONEON-NOSVE-NEXT: ldr d6, [sp, #56] -; NONEON-NOSVE-NEXT: ldr d7, [sp, #88] -; NONEON-NOSVE-NEXT: ushll v5.2d, v5.2s, #0 -; NONEON-NOSVE-NEXT: ushll v4.2d, v4.2s, #0 -; NONEON-NOSVE-NEXT: stp q1, q5, [x0, #64] -; NONEON-NOSVE-NEXT: ushll v1.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: ushll v2.2d, v6.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q4, [x0] -; NONEON-NOSVE-NEXT: ushll v0.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: ushll v3.2d, v7.2s, #0 -; NONEON-NOSVE-NEXT: stp q1, q2, [x0, #96] -; NONEON-NOSVE-NEXT: stp q0, q3, [x0, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #112 -; NONEON-NOSVE-NEXT: ret %b = zext <16 x i8> %a to <16 x i64> store <16 x i64> %b, ptr %out ret void @@ -1297,73 +746,6 @@ define void @zext_v32i8_v32i64(ptr %in, ptr %out) { ; CHECK-NEXT: stp q0, q2, [x1, #224] ; CHECK-NEXT: stp q3, q1, [x1, #96] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v32i8_v32i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub sp, sp, #224 -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 224 -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [sp] -; NONEON-NOSVE-NEXT: ushll v5.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: ushll v6.8h, v1.8b, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v3.8h, v2.8b, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ushll v4.8h, v2.8b, #0 -; NONEON-NOSVE-NEXT: stp q3, q5, [sp, #32] -; NONEON-NOSVE-NEXT: ushll v5.4s, v5.4h, #0 -; NONEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #56] -; NONEON-NOSVE-NEXT: ldr d0, [sp, #40] -; NONEON-NOSVE-NEXT: stp q4, q6, [sp, #64] -; NONEON-NOSVE-NEXT: ushll v6.4s, v6.4h, #0 -; NONEON-NOSVE-NEXT: ushll v4.4s, v4.4h, #0 -; NONEON-NOSVE-NEXT: ldr d7, [sp, #88] -; NONEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #72] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v7.4s, v7.4h, #0 -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q2, q5, [sp, #128] -; NONEON-NOSVE-NEXT: ushll v5.2d, v5.2s, #0 -; NONEON-NOSVE-NEXT: ushll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: ldr d19, [sp, #152] -; NONEON-NOSVE-NEXT: stp q0, q3, [sp, #96] -; NONEON-NOSVE-NEXT: ldr d20, [sp, #136] -; NONEON-NOSVE-NEXT: stp q1, q4, [sp, #160] -; NONEON-NOSVE-NEXT: ldr d17, [sp, #104] -; NONEON-NOSVE-NEXT: ldr d21, [sp, #120] -; NONEON-NOSVE-NEXT: stp q7, q6, [sp, #192] -; NONEON-NOSVE-NEXT: ushll v6.2d, v6.2s, #0 -; NONEON-NOSVE-NEXT: ushll v19.2d, v19.2s, #0 -; NONEON-NOSVE-NEXT: ldr d16, [sp, #216] -; NONEON-NOSVE-NEXT: ldr d22, [sp, #200] -; NONEON-NOSVE-NEXT: ldr d23, [sp, #184] -; NONEON-NOSVE-NEXT: ldr d18, [sp, #168] -; NONEON-NOSVE-NEXT: ushll v4.2d, v4.2s, #0 -; NONEON-NOSVE-NEXT: ushll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: ushll v16.2d, v16.2s, #0 -; NONEON-NOSVE-NEXT: stp q5, q19, [x1] -; NONEON-NOSVE-NEXT: ushll v5.2d, v7.2s, #0 -; NONEON-NOSVE-NEXT: ushll v7.2d, v22.2s, #0 -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: stp q6, q16, [x1, #128] -; NONEON-NOSVE-NEXT: ushll v6.2d, v23.2s, #0 -; NONEON-NOSVE-NEXT: stp q5, q7, [x1, #160] -; NONEON-NOSVE-NEXT: ushll v5.2d, v20.2s, #0 -; NONEON-NOSVE-NEXT: stp q4, q6, [x1, #192] -; NONEON-NOSVE-NEXT: ushll v4.2d, v21.2s, #0 -; NONEON-NOSVE-NEXT: stp q2, q5, [x1, #32] -; NONEON-NOSVE-NEXT: ushll v2.2d, v17.2s, #0 -; NONEON-NOSVE-NEXT: stp q3, q4, [x1, #64] -; NONEON-NOSVE-NEXT: ushll v3.2d, v18.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q2, [x1, #96] -; NONEON-NOSVE-NEXT: stp q1, q3, [x1, #224] -; NONEON-NOSVE-NEXT: add sp, sp, #224 -; NONEON-NOSVE-NEXT: ret %a = load <32 x i8>, ptr %in %b = add <32 x i8> %a, %a %c = zext <32 x i8> %b to <32 x i64> @@ -1384,17 +766,6 @@ define void @zext_v8i16_v8i32(<8 x i16> %a, ptr %out) { ; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v8i16_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = zext <8 x i16> %a to <8 x i32> store <8 x i32>%b, ptr %out ret void @@ -1415,24 +786,6 @@ define void @zext_v16i16_v16i32(ptr %in, ptr %out) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v16i16_v16i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v0.8h -; NONEON-NOSVE-NEXT: add v1.8h, v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %a = load <16 x i16>, ptr %in %b = add <16 x i16> %a, %a %c = zext <16 x i16> %b to <16 x i32> @@ -1454,18 +807,6 @@ define void @zext_v4i16_v4i64(<4 x i16> %a, ptr %out) { ; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v4i16_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = zext <4 x i16> %a to <4 x i64> store <4 x i64>%b, ptr %out ret void @@ -1487,25 +828,6 @@ define void @zext_v8i16_v8i64(<8 x i16> %a, ptr %out) { ; CHECK-NEXT: stp q2, q1, [x0] ; CHECK-NEXT: stp q3, q0, [x0, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v8i16_v8i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-48]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #16] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: ushll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: ushll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q2, [x0] -; NONEON-NOSVE-NEXT: stp q1, q3, [x0, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #48 -; NONEON-NOSVE-NEXT: ret %b = zext <8 x i16> %a to <8 x i64> store <8 x i64>%b, ptr %out ret void @@ -1540,40 +862,6 @@ define void @zext_v16i16_v16i64(ptr %in, ptr %out) { ; CHECK-NEXT: stp q6, q0, [x1, #96] ; CHECK-NEXT: stp q7, q1, [x1, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v16i16_v16i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v0.8h -; NONEON-NOSVE-NEXT: add v1.8h, v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-96]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: stp q2, q0, [sp, #32] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: stp q3, q1, [sp, #64] -; NONEON-NOSVE-NEXT: ldr d5, [sp, #56] -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ldr d4, [sp, #88] -; NONEON-NOSVE-NEXT: ldr d6, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d7, [sp, #72] -; NONEON-NOSVE-NEXT: ushll v5.2d, v5.2s, #0 -; NONEON-NOSVE-NEXT: ushll v4.2d, v4.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q5, [x1] -; NONEON-NOSVE-NEXT: ushll v0.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: ushll v2.2d, v6.2s, #0 -; NONEON-NOSVE-NEXT: stp q1, q4, [x1, #64] -; NONEON-NOSVE-NEXT: ushll v1.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: ushll v3.2d, v7.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q2, [x1, #32] -; NONEON-NOSVE-NEXT: stp q1, q3, [x1, #96] -; NONEON-NOSVE-NEXT: add sp, sp, #96 -; NONEON-NOSVE-NEXT: ret %a = load <16 x i16>, ptr %in %b = add <16 x i16> %a, %a %c = zext <16 x i16> %b to <16 x i64> @@ -1594,17 +882,6 @@ define void @zext_v4i32_v4i64(<4 x i32> %a, ptr %out) { ; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v4i32_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %b = zext <4 x i32> %a to <4 x i64> store <4 x i64>%b, ptr %out ret void @@ -1625,24 +902,6 @@ define void @zext_v8i32_v8i64(ptr %in, ptr %out) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zext_v8i32_v8i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: add v0.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: add v1.4s, v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: ushll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %a = load <8 x i32>, ptr %in %b = add <8 x i32> %a, %a %c = zext <8 x i32> %b to <8 x i64> @@ -1669,21 +928,6 @@ define void @extend_and_mul(i32 %0, <2 x i64> %1, ptr %2) { ; SVE2-NEXT: mul z0.d, z1.d, z0.d ; SVE2-NEXT: str q0, [x1] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: extend_and_mul: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v1.2s, w0 -; NONEON-NOSVE-NEXT: fmov x10, d0 -; NONEON-NOSVE-NEXT: mov x8, v0.d[1] -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: fmov x11, d1 -; NONEON-NOSVE-NEXT: mov x9, v1.d[1] -; NONEON-NOSVE-NEXT: mul x10, x11, x10 -; NONEON-NOSVE-NEXT: mul x8, x9, x8 -; NONEON-NOSVE-NEXT: fmov d0, x10 -; NONEON-NOSVE-NEXT: mov v0.d[1], x8 -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %broadcast.splatinsert2 = insertelement <2 x i32> poison, i32 %0, i64 0 %broadcast.splat3 = shufflevector <2 x i32> %broadcast.splatinsert2, <2 x i32> poison, <2 x i32> zeroinitializer %4 = zext <2 x i32> %broadcast.splat3 to <2 x i64> @@ -1699,13 +943,6 @@ define void @extend_no_mul(i32 %0, <2 x i64> %1, ptr %2) { ; CHECK-NEXT: mov z0.d, x8 ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: extend_no_mul: -; NONEON-NOSVE: // %bb.0: // %entry -; NONEON-NOSVE-NEXT: dup v0.2s, w0 -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret entry: %broadcast.splatinsert2 = insertelement <2 x i32> poison, i32 %0, i64 0 %broadcast.splat3 = shufflevector <2 x i32> %broadcast.splatinsert2, <2 x i32> poison, <2 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll index d86cfcbfb4f6..f028b3eeca25 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -23,15 +22,6 @@ define void @add_v32i8(ptr %a) { ; CHECK-NEXT: add z1.b, z1.b, #7 // =0x7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #7 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: add v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i32 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -48,16 +38,6 @@ define void @add_v16i16(ptr %a) { ; CHECK-NEXT: add z1.h, z1.h, #15 // =0xf ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #15 // =0xf -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: add v1.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: add v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -74,16 +54,6 @@ define void @add_v8i32(ptr %a) { ; CHECK-NEXT: add z1.s, z1.s, #31 // =0x1f ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #31 // =0x1f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: add v1.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: add v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -100,16 +70,6 @@ define void @add_v4i64(ptr %a) { ; CHECK-NEXT: add z1.d, z1.d, #63 // =0x3f ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #63 // =0x3f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: add v1.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: add v0.2d, v2.2d, v0.2d -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -130,15 +90,6 @@ define void @and_v32i8(ptr %a) { ; CHECK-NEXT: and z1.b, z1.b, #0x7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #7 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: and v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: and v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i32 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -155,16 +106,6 @@ define void @and_v16i16(ptr %a) { ; CHECK-NEXT: and z1.h, z1.h, #0xf ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #15 // =0xf -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: and v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: and v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -181,16 +122,6 @@ define void @and_v8i32(ptr %a) { ; CHECK-NEXT: and z1.s, z1.s, #0x1f ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #31 // =0x1f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: and v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: and v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -207,16 +138,6 @@ define void @and_v4i64(ptr %a) { ; CHECK-NEXT: and z1.d, z1.d, #0x3f ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #63 // =0x3f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: and v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: and v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -237,14 +158,6 @@ define void @ashr_v32i8(ptr %a) { ; CHECK-NEXT: asr z1.b, z1.b, #7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cmlt v0.16b, v0.16b, #0 -; NONEON-NOSVE-NEXT: cmlt v1.16b, v1.16b, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i32 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -261,14 +174,6 @@ define void @ashr_v16i16(ptr %a) { ; CHECK-NEXT: asr z1.h, z1.h, #15 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cmlt v0.8h, v0.8h, #0 -; NONEON-NOSVE-NEXT: cmlt v1.8h, v1.8h, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -285,14 +190,6 @@ define void @ashr_v8i32(ptr %a) { ; CHECK-NEXT: asr z1.s, z1.s, #31 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cmlt v0.4s, v0.4s, #0 -; NONEON-NOSVE-NEXT: cmlt v1.4s, v1.4s, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -309,14 +206,6 @@ define void @ashr_v4i64(ptr %a) { ; CHECK-NEXT: asr z1.d, z1.d, #63 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cmlt v0.2d, v0.2d, #0 -; NONEON-NOSVE-NEXT: cmlt v1.2d, v1.2d, #0 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -340,15 +229,6 @@ define void @icmp_eq_v32i8(ptr %a) { ; CHECK-NEXT: mov z1.b, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_eq_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #7 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: cmeq v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: cmeq v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -369,16 +249,6 @@ define void @icmp_sge_v16i16(ptr %a) { ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_sge_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #15 // =0xf -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: cmge v1.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: cmge v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -399,16 +269,6 @@ define void @icmp_sgt_v8i32(ptr %a) { ; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_sgt_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #-8 // =0xfffffff8 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: cmgt v1.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: cmgt v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 -8, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -429,16 +289,6 @@ define void @icmp_ult_v4i64(ptr %a) { ; CHECK-NEXT: mov z1.d, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: icmp_ult_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #63 // =0x3f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: cmhi v1.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: cmhi v0.2d, v0.2d, v2.2d -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -460,14 +310,6 @@ define void @lshr_v32i8(ptr %a) { ; CHECK-NEXT: lsr z1.b, z1.b, #7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ushr v0.16b, v0.16b, #7 -; NONEON-NOSVE-NEXT: ushr v1.16b, v1.16b, #7 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -484,14 +326,6 @@ define void @lshr_v16i16(ptr %a) { ; CHECK-NEXT: lsr z1.h, z1.h, #15 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ushr v0.8h, v0.8h, #15 -; NONEON-NOSVE-NEXT: ushr v1.8h, v1.8h, #15 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -508,14 +342,6 @@ define void @lshr_v8i32(ptr %a) { ; CHECK-NEXT: lsr z1.s, z1.s, #31 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ushr v0.4s, v0.4s, #31 -; NONEON-NOSVE-NEXT: ushr v1.4s, v1.4s, #31 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -532,14 +358,6 @@ define void @lshr_v4i64(ptr %a) { ; CHECK-NEXT: lsr z1.d, z1.d, #63 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ushr v0.2d, v0.2d, #63 -; NONEON-NOSVE-NEXT: ushr v1.2d, v1.2d, #63 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -560,15 +378,6 @@ define void @mul_v32i8(ptr %a) { ; CHECK-NEXT: mul z1.b, z1.b, #7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #7 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: mul v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: mul v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -585,16 +394,6 @@ define void @mul_v16i16(ptr %a) { ; CHECK-NEXT: mul z1.h, z1.h, #15 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #15 // =0xf -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: mul v1.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: mul v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -611,16 +410,6 @@ define void @mul_v8i32(ptr %a) { ; CHECK-NEXT: mul z1.s, z1.s, #31 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #31 // =0x1f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: mul v1.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: mul v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -637,28 +426,6 @@ define void @mul_v4i64(ptr %a) { ; CHECK-NEXT: mul z1.d, z1.d, #63 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: mul_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: fmov x10, d0 -; NONEON-NOSVE-NEXT: fmov x11, d1 -; NONEON-NOSVE-NEXT: mov x8, v0.d[1] -; NONEON-NOSVE-NEXT: mov x9, v1.d[1] -; NONEON-NOSVE-NEXT: lsl x12, x10, #6 -; NONEON-NOSVE-NEXT: lsl x13, x11, #6 -; NONEON-NOSVE-NEXT: lsl x14, x8, #6 -; NONEON-NOSVE-NEXT: sub x10, x12, x10 -; NONEON-NOSVE-NEXT: sub x11, x13, x11 -; NONEON-NOSVE-NEXT: lsl x12, x9, #6 -; NONEON-NOSVE-NEXT: fmov d0, x10 -; NONEON-NOSVE-NEXT: fmov d1, x11 -; NONEON-NOSVE-NEXT: sub x8, x14, x8 -; NONEON-NOSVE-NEXT: sub x9, x12, x9 -; NONEON-NOSVE-NEXT: mov v0.d[1], x8 -; NONEON-NOSVE-NEXT: mov v1.d[1], x9 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -679,15 +446,6 @@ define void @or_v32i8(ptr %a) { ; CHECK-NEXT: orr z1.b, z1.b, #0x7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #7 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: orr v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -704,16 +462,6 @@ define void @or_v16i16(ptr %a) { ; CHECK-NEXT: orr z1.h, z1.h, #0xf ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #15 // =0xf -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: orr v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -730,16 +478,6 @@ define void @or_v8i32(ptr %a) { ; CHECK-NEXT: orr z1.s, z1.s, #0x1f ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #31 // =0x1f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: orr v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -756,16 +494,6 @@ define void @or_v4i64(ptr %a) { ; CHECK-NEXT: orr z1.d, z1.d, #0x3f ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #63 // =0x3f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: orr v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: orr v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -786,14 +514,6 @@ define void @shl_v32i8(ptr %a) { ; CHECK-NEXT: lsl z1.b, z1.b, #7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: shl v0.16b, v0.16b, #7 -; NONEON-NOSVE-NEXT: shl v1.16b, v1.16b, #7 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -810,14 +530,6 @@ define void @shl_v16i16(ptr %a) { ; CHECK-NEXT: lsl z1.h, z1.h, #15 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: shl v0.8h, v0.8h, #15 -; NONEON-NOSVE-NEXT: shl v1.8h, v1.8h, #15 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -834,14 +546,6 @@ define void @shl_v8i32(ptr %a) { ; CHECK-NEXT: lsl z1.s, z1.s, #31 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: shl v0.4s, v0.4s, #31 -; NONEON-NOSVE-NEXT: shl v1.4s, v1.4s, #31 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -858,14 +562,6 @@ define void @shl_v4i64(ptr %a) { ; CHECK-NEXT: lsl z1.d, z1.d, #63 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: shl v0.2d, v0.2d, #63 -; NONEON-NOSVE-NEXT: shl v1.2d, v1.2d, #63 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -886,15 +582,6 @@ define void @smax_v32i8(ptr %a) { ; CHECK-NEXT: smax z1.b, z1.b, #7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #7 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: smax v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: smax v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -911,16 +598,6 @@ define void @smax_v16i16(ptr %a) { ; CHECK-NEXT: smax z1.h, z1.h, #15 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #15 // =0xf -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: smax v1.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: smax v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -937,16 +614,6 @@ define void @smax_v8i32(ptr %a) { ; CHECK-NEXT: smax z1.s, z1.s, #31 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #31 // =0x1f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: smax v1.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: smax v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -963,18 +630,6 @@ define void @smax_v4i64(ptr %a) { ; CHECK-NEXT: smax z1.d, z1.d, #63 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #63 // =0x3f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: cmgt v3.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: cmgt v4.2d, v2.2d, v0.2d -; NONEON-NOSVE-NEXT: bif v1.16b, v0.16b, v3.16b -; NONEON-NOSVE-NEXT: bit v0.16b, v2.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -995,15 +650,6 @@ define void @smin_v32i8(ptr %a) { ; CHECK-NEXT: smin z1.b, z1.b, #7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #7 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: smin v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: smin v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -1020,16 +666,6 @@ define void @smin_v16i16(ptr %a) { ; CHECK-NEXT: smin z1.h, z1.h, #15 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #15 // =0xf -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: smin v1.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: smin v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -1046,16 +682,6 @@ define void @smin_v8i32(ptr %a) { ; CHECK-NEXT: smin z1.s, z1.s, #31 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #31 // =0x1f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: smin v1.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: smin v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -1072,18 +698,6 @@ define void @smin_v4i64(ptr %a) { ; CHECK-NEXT: smin z1.d, z1.d, #63 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #63 // =0x3f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: cmgt v3.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: cmgt v4.2d, v0.2d, v2.2d -; NONEON-NOSVE-NEXT: bif v1.16b, v0.16b, v3.16b -; NONEON-NOSVE-NEXT: bit v0.16b, v2.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -1104,15 +718,6 @@ define void @sub_v32i8(ptr %a) { ; CHECK-NEXT: sub z1.b, z1.b, #7 // =0x7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #7 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: sub v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: sub v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -1129,16 +734,6 @@ define void @sub_v16i16(ptr %a) { ; CHECK-NEXT: sub z1.h, z1.h, #15 // =0xf ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #15 // =0xf -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: sub v1.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: sub v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -1155,16 +750,6 @@ define void @sub_v8i32(ptr %a) { ; CHECK-NEXT: sub z1.s, z1.s, #31 // =0x1f ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #31 // =0x1f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: sub v1.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: sub v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -1181,16 +766,6 @@ define void @sub_v4i64(ptr %a) { ; CHECK-NEXT: sub z1.d, z1.d, #63 // =0x3f ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sub_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #63 // =0x3f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: sub v1.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: sub v0.2d, v2.2d, v0.2d -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -1211,15 +786,6 @@ define void @umax_v32i8(ptr %a) { ; CHECK-NEXT: umax z1.b, z1.b, #7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #7 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: umax v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: umax v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -1236,16 +802,6 @@ define void @umax_v16i16(ptr %a) { ; CHECK-NEXT: umax z1.h, z1.h, #15 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #15 // =0xf -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: umax v1.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: umax v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -1262,16 +818,6 @@ define void @umax_v8i32(ptr %a) { ; CHECK-NEXT: umax z1.s, z1.s, #31 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #31 // =0x1f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: umax v1.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: umax v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -1288,18 +834,6 @@ define void @umax_v4i64(ptr %a) { ; CHECK-NEXT: umax z1.d, z1.d, #63 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #63 // =0x3f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: cmhi v3.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: cmhi v4.2d, v2.2d, v0.2d -; NONEON-NOSVE-NEXT: bif v1.16b, v0.16b, v3.16b -; NONEON-NOSVE-NEXT: bit v0.16b, v2.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -1320,15 +854,6 @@ define void @umin_v32i8(ptr %a) { ; CHECK-NEXT: umin z1.b, z1.b, #7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #7 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: umin v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: umin v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -1345,16 +870,6 @@ define void @umin_v16i16(ptr %a) { ; CHECK-NEXT: umin z1.h, z1.h, #15 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #15 // =0xf -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: umin v1.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: umin v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -1371,16 +886,6 @@ define void @umin_v8i32(ptr %a) { ; CHECK-NEXT: umin z1.s, z1.s, #31 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #31 // =0x1f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: umin v1.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: umin v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -1397,18 +902,6 @@ define void @umin_v4i64(ptr %a) { ; CHECK-NEXT: umin z1.d, z1.d, #63 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #63 // =0x3f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: cmhi v3.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: cmhi v4.2d, v0.2d, v2.2d -; NONEON-NOSVE-NEXT: bif v1.16b, v0.16b, v3.16b -; NONEON-NOSVE-NEXT: bit v0.16b, v2.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer @@ -1429,15 +922,6 @@ define void @xor_v32i8(ptr %a) { ; CHECK-NEXT: eor z1.b, z1.b, #0x7 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #7 -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: eor v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: eor v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer @@ -1454,16 +938,6 @@ define void @xor_v16i16(ptr %a) { ; CHECK-NEXT: eor z1.h, z1.h, #0xf ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #15 // =0xf -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: eor v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: eor v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer @@ -1480,16 +954,6 @@ define void @xor_v8i32(ptr %a) { ; CHECK-NEXT: eor z1.s, z1.s, #0x1f ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #31 // =0x1f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: eor v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: eor v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer @@ -1506,16 +970,6 @@ define void @xor_v4i64(ptr %a) { ; CHECK-NEXT: eor z1.d, z1.d, #0x3f ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #63 // =0x3f -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: eor v1.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: eor v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll index f0b39b275614..4d70c1dd1c91 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -17,11 +16,6 @@ define <8 x i8> @and_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = and <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -34,11 +28,6 @@ define <16 x i8> @and_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = and <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -52,15 +41,6 @@ define void @and_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: and z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: and v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: and v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = and <32 x i8> %op1, %op2 @@ -76,11 +56,6 @@ define <4 x i16> @and_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = and <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -93,11 +68,6 @@ define <8 x i16> @and_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = and <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -111,15 +81,6 @@ define void @and_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: and z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: and v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: and v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = and <16 x i16> %op1, %op2 @@ -135,11 +96,6 @@ define <2 x i32> @and_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = and <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -152,11 +108,6 @@ define <4 x i32> @and_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = and <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -170,15 +121,6 @@ define void @and_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: and z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: and v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: and v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = and <8 x i32> %op1, %op2 @@ -194,11 +136,6 @@ define <1 x i64> @and_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = and <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -211,11 +148,6 @@ define <2 x i64> @and_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = and <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -229,15 +161,6 @@ define void @and_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: and z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: and_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: and v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: and v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = and <4 x i64> %op1, %op2 @@ -257,11 +180,6 @@ define <8 x i8> @or_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = or <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -274,11 +192,6 @@ define <16 x i8> @or_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = or <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -292,15 +205,6 @@ define void @or_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: orr z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: orr v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: orr v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = or <32 x i8> %op1, %op2 @@ -316,11 +220,6 @@ define <4 x i16> @or_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = or <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -333,11 +232,6 @@ define <8 x i16> @or_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = or <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -351,15 +245,6 @@ define void @or_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: orr z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: orr v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: orr v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = or <16 x i16> %op1, %op2 @@ -375,11 +260,6 @@ define <2 x i32> @or_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = or <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -392,11 +272,6 @@ define <4 x i32> @or_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = or <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -410,15 +285,6 @@ define void @or_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: orr z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: orr v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: orr v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = or <8 x i32> %op1, %op2 @@ -434,11 +300,6 @@ define <1 x i64> @or_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = or <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -451,11 +312,6 @@ define <2 x i64> @or_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = or <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -469,15 +325,6 @@ define void @or_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: orr z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: or_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: orr v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: orr v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = or <4 x i64> %op1, %op2 @@ -497,11 +344,6 @@ define <8 x i8> @xor_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = xor <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -514,11 +356,6 @@ define <16 x i8> @xor_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: eor v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = xor <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -532,15 +369,6 @@ define void @xor_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: eor z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: eor v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: eor v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = xor <32 x i8> %op1, %op2 @@ -556,11 +384,6 @@ define <4 x i16> @xor_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = xor <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -573,11 +396,6 @@ define <8 x i16> @xor_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: eor v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = xor <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -591,15 +409,6 @@ define void @xor_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: eor z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: eor v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: eor v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = xor <16 x i16> %op1, %op2 @@ -615,11 +424,6 @@ define <2 x i32> @xor_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = xor <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -632,11 +436,6 @@ define <4 x i32> @xor_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: eor v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = xor <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -650,15 +449,6 @@ define void @xor_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: eor z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: eor v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: eor v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = xor <8 x i32> %op1, %op2 @@ -674,11 +464,6 @@ define <1 x i64> @xor_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = xor <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -691,11 +476,6 @@ define <2 x i64> @xor_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: eor z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: eor v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = xor <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -709,15 +489,6 @@ define void @xor_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: eor z1.d, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: xor_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: eor v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: eor v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = xor <4 x i64> %op1, %op2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll index 51c404ece6cd..50cf9b73d9a7 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -18,11 +17,6 @@ define <8 x i8> @smax_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smax v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = call <8 x i8> @llvm.smax.v8i8(<8 x i8> %op1, <8 x i8> %op2) ret <8 x i8> %res } @@ -36,11 +30,6 @@ define <16 x i8> @smax_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smax v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %op1, <16 x i8> %op2) ret <16 x i8> %res } @@ -56,15 +45,6 @@ define void @smax_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: smax z1.b, p0/m, z1.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: smax v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: smax v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = call <32 x i8> @llvm.smax.v32i8(<32 x i8> %op1, <32 x i8> %op2) @@ -81,11 +61,6 @@ define <4 x i16> @smax_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smax v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = call <4 x i16> @llvm.smax.v4i16(<4 x i16> %op1, <4 x i16> %op2) ret <4 x i16> %res } @@ -99,11 +74,6 @@ define <8 x i16> @smax_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smax v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %res = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %op1, <8 x i16> %op2) ret <8 x i16> %res } @@ -119,15 +89,6 @@ define void @smax_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: smax z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: smax v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: smax v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = call <16 x i16> @llvm.smax.v16i16(<16 x i16> %op1, <16 x i16> %op2) @@ -144,11 +105,6 @@ define <2 x i32> @smax_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smax v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %op1, <2 x i32> %op2) ret <2 x i32> %res } @@ -162,11 +118,6 @@ define <4 x i32> @smax_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smax v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %op1, <4 x i32> %op2) ret <4 x i32> %res } @@ -182,15 +133,6 @@ define void @smax_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: smax z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: smax v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: smax v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %op1, <8 x i32> %op2) @@ -208,12 +150,6 @@ define <1 x i64> @smax_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmgt d2, d0, d1 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %res = call <1 x i64> @llvm.smax.v1i64(<1 x i64> %op1, <1 x i64> %op2) ret <1 x i64> %res } @@ -228,12 +164,6 @@ define <2 x i64> @smax_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmgt v2.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %op1, <2 x i64> %op2) ret <2 x i64> %res } @@ -249,18 +179,6 @@ define void @smax_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: smax z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smax_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: cmgt v4.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: cmgt v5.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: bit v0.16b, v1.16b, v4.16b -; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b -; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %op1, <4 x i64> %op2) @@ -281,11 +199,6 @@ define <8 x i8> @smin_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smin v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = call <8 x i8> @llvm.smin.v8i8(<8 x i8> %op1, <8 x i8> %op2) ret <8 x i8> %res } @@ -299,11 +212,6 @@ define <16 x i8> @smin_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smin v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %op1, <16 x i8> %op2) ret <16 x i8> %res } @@ -319,15 +227,6 @@ define void @smin_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: smin z1.b, p0/m, z1.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: smin v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: smin v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = call <32 x i8> @llvm.smin.v32i8(<32 x i8> %op1, <32 x i8> %op2) @@ -344,11 +243,6 @@ define <4 x i16> @smin_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smin v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = call <4 x i16> @llvm.smin.v4i16(<4 x i16> %op1, <4 x i16> %op2) ret <4 x i16> %res } @@ -362,11 +256,6 @@ define <8 x i16> @smin_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smin v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %res = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %op1, <8 x i16> %op2) ret <8 x i16> %res } @@ -382,15 +271,6 @@ define void @smin_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: smin z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: smin v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: smin v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = call <16 x i16> @llvm.smin.v16i16(<16 x i16> %op1, <16 x i16> %op2) @@ -407,11 +287,6 @@ define <2 x i32> @smin_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smin v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %op1, <2 x i32> %op2) ret <2 x i32> %res } @@ -425,11 +300,6 @@ define <4 x i32> @smin_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smin v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %op1, <4 x i32> %op2) ret <4 x i32> %res } @@ -445,15 +315,6 @@ define void @smin_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: smin z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: smin v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: smin v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %op1, <8 x i32> %op2) @@ -471,12 +332,6 @@ define <1 x i64> @smin_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmgt d2, d1, d0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %res = call <1 x i64> @llvm.smin.v1i64(<1 x i64> %op1, <1 x i64> %op2) ret <1 x i64> %res } @@ -491,12 +346,6 @@ define <2 x i64> @smin_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmgt v2.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %op1, <2 x i64> %op2) ret <2 x i64> %res } @@ -512,18 +361,6 @@ define void @smin_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: smin z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smin_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: cmgt v4.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: cmgt v5.2d, v3.2d, v2.2d -; NONEON-NOSVE-NEXT: bit v0.16b, v1.16b, v4.16b -; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b -; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %op1, <4 x i64> %op2) @@ -544,11 +381,6 @@ define <8 x i8> @umax_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umax v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = call <8 x i8> @llvm.umax.v8i8(<8 x i8> %op1, <8 x i8> %op2) ret <8 x i8> %res } @@ -562,11 +394,6 @@ define <16 x i8> @umax_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umax v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %op1, <16 x i8> %op2) ret <16 x i8> %res } @@ -582,15 +409,6 @@ define void @umax_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: umax z1.b, p0/m, z1.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: umax v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: umax v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = call <32 x i8> @llvm.umax.v32i8(<32 x i8> %op1, <32 x i8> %op2) @@ -607,11 +425,6 @@ define <4 x i16> @umax_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umax v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = call <4 x i16> @llvm.umax.v4i16(<4 x i16> %op1, <4 x i16> %op2) ret <4 x i16> %res } @@ -625,11 +438,6 @@ define <8 x i16> @umax_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umax v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %res = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %op1, <8 x i16> %op2) ret <8 x i16> %res } @@ -645,15 +453,6 @@ define void @umax_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: umax z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: umax v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: umax v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = call <16 x i16> @llvm.umax.v16i16(<16 x i16> %op1, <16 x i16> %op2) @@ -670,11 +469,6 @@ define <2 x i32> @umax_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umax v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i32> @llvm.umax.v2i32(<2 x i32> %op1, <2 x i32> %op2) ret <2 x i32> %res } @@ -688,11 +482,6 @@ define <4 x i32> @umax_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umax v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %op1, <4 x i32> %op2) ret <4 x i32> %res } @@ -708,15 +497,6 @@ define void @umax_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: umax z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: umax v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: umax v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = call <8 x i32> @llvm.umax.v8i32(<8 x i32> %op1, <8 x i32> %op2) @@ -734,12 +514,6 @@ define <1 x i64> @umax_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmhi d2, d0, d1 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %res = call <1 x i64> @llvm.umax.v1i64(<1 x i64> %op1, <1 x i64> %op2) ret <1 x i64> %res } @@ -754,12 +528,6 @@ define <2 x i64> @umax_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmhi v2.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %op1, <2 x i64> %op2) ret <2 x i64> %res } @@ -775,18 +543,6 @@ define void @umax_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: umax z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umax_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: cmhi v4.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: cmhi v5.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: bit v0.16b, v1.16b, v4.16b -; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b -; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %op1, <4 x i64> %op2) @@ -807,11 +563,6 @@ define <8 x i8> @umin_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umin v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = call <8 x i8> @llvm.umin.v8i8(<8 x i8> %op1, <8 x i8> %op2) ret <8 x i8> %res } @@ -825,11 +576,6 @@ define <16 x i8> @umin_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umin v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %op1, <16 x i8> %op2) ret <16 x i8> %res } @@ -845,15 +591,6 @@ define void @umin_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: umin z1.b, p0/m, z1.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: umin v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: umin v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = call <32 x i8> @llvm.umin.v32i8(<32 x i8> %op1, <32 x i8> %op2) @@ -870,11 +607,6 @@ define <4 x i16> @umin_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umin v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = call <4 x i16> @llvm.umin.v4i16(<4 x i16> %op1, <4 x i16> %op2) ret <4 x i16> %res } @@ -888,11 +620,6 @@ define <8 x i16> @umin_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umin v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %res = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %op1, <8 x i16> %op2) ret <8 x i16> %res } @@ -908,15 +635,6 @@ define void @umin_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: umin z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: umin v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: umin v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = call <16 x i16> @llvm.umin.v16i16(<16 x i16> %op1, <16 x i16> %op2) @@ -933,11 +651,6 @@ define <2 x i32> @umin_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umin v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %op1, <2 x i32> %op2) ret <2 x i32> %res } @@ -951,11 +664,6 @@ define <4 x i32> @umin_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umin v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %op1, <4 x i32> %op2) ret <4 x i32> %res } @@ -971,15 +679,6 @@ define void @umin_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: umin z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: umin v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: umin v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %op1, <8 x i32> %op2) @@ -997,12 +696,6 @@ define <1 x i64> @umin_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmhi d2, d1, d0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %res = call <1 x i64> @llvm.umin.v1i64(<1 x i64> %op1, <1 x i64> %op2) ret <1 x i64> %res } @@ -1017,12 +710,6 @@ define <2 x i64> @umin_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmhi v2.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %op1, <2 x i64> %op2) ret <2 x i64> %res } @@ -1038,18 +725,6 @@ define void @umin_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: umin z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umin_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: cmhi v4.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: cmhi v5.2d, v3.2d, v2.2d -; NONEON-NOSVE-NEXT: bit v0.16b, v1.16b, v4.16b -; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b -; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %op1, <4 x i64> %op2) diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mla-neon-fa64.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mla-neon-fa64.ll index 83714152c173..149ad6d1e267 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mla-neon-fa64.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mla-neon-fa64.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sme-fa64 -force-streaming-compatible-sve < %s | FileCheck %s -check-prefix=FA64 ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s -check-prefix=NO-FA64 -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -21,12 +20,6 @@ define <8 x i8> @mla8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) { ; NO-FA64-NEXT: mad z0.b, p0/m, z1.b, z2.b ; NO-FA64-NEXT: // kill: def $d0 killed $d0 killed $z0 ; NO-FA64-NEXT: ret -; -; NONEON-NOSVE-LABEL: mla8xi8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mla v2.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov d0, d2 -; NONEON-NOSVE-NEXT: ret %tmp1 = mul <8 x i8> %A, %B; %tmp2 = add <8 x i8> %C, %tmp1; ret <8 x i8> %tmp2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll index 6e6d40e2ea04..cb7fa53eac51 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll @@ -2,7 +2,6 @@ ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE ; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2 ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2 -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE ; This test only tests the legal types for a given vector width, as mulh nodes ; do not get generated for non-legal types. @@ -37,16 +36,6 @@ define <4 x i8> @smulh_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; SVE2-NEXT: lsr z0.h, z0.h, #4 ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: shl v1.4h, v1.4h, #8 -; NONEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: sshr v1.4h, v1.4h, #8 -; NONEON-NOSVE-NEXT: mul v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ushr v0.4h, v0.4h, #4 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <4 x i16> undef, i16 4, i64 0 %splat = shufflevector <4 x i16> %insert, <4 x i16> undef, <4 x i32> zeroinitializer %1 = sext <4 x i8> %op1 to <4 x i16> @@ -74,12 +63,6 @@ define <8 x i8> @smulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; SVE2-NEXT: smulh z0.b, z0.b, z1.b ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smull v0.8h, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: shrn v0.8b, v0.8h, #8 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <8 x i16> undef, i16 8, i64 0 %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer %1 = sext <8 x i8> %op1 to <8 x i16> @@ -107,13 +90,6 @@ define <16 x i8> @smulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; SVE2-NEXT: smulh z0.b, z0.b, z1.b ; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smull2 v2.8h, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: smull v0.8h, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: uzp2 v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %1 = sext <16 x i8> %op1 to <16 x i16> %2 = sext <16 x i8> %op2 to <16 x i16> %mul = mul <16 x i16> %1, %2 @@ -142,19 +118,6 @@ define void @smulh_v32i8(ptr %a, ptr %b) { ; SVE2-NEXT: smulh z1.b, z2.b, z3.b ; SVE2-NEXT: stp q0, q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: smull2 v4.8h, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: smull v0.8h, v1.8b, v0.8b -; NONEON-NOSVE-NEXT: smull2 v1.8h, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: smull v2.8h, v2.8b, v3.8b -; NONEON-NOSVE-NEXT: uzp2 v0.16b, v0.16b, v4.16b -; NONEON-NOSVE-NEXT: uzp2 v1.16b, v2.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %1 = sext <32 x i8> %op1 to <32 x i16> @@ -190,16 +153,6 @@ define <2 x i16> @smulh_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; SVE2-NEXT: lsr z0.s, z0.s, #16 ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: shl v1.2s, v1.2s, #16 -; NONEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: sshr v1.2s, v1.2s, #16 -; NONEON-NOSVE-NEXT: mul v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ushr v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: ret %1 = sext <2 x i16> %op1 to <2 x i32> %2 = sext <2 x i16> %op2 to <2 x i32> %mul = mul <2 x i32> %1, %2 @@ -225,12 +178,6 @@ define <4 x i16> @smulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; SVE2-NEXT: smulh z0.h, z0.h, z1.h ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smull v0.4s, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: shrn v0.4h, v0.4s, #16 -; NONEON-NOSVE-NEXT: ret %1 = sext <4 x i16> %op1 to <4 x i32> %2 = sext <4 x i16> %op2 to <4 x i32> %mul = mul <4 x i32> %1, %2 @@ -256,13 +203,6 @@ define <8 x i16> @smulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; SVE2-NEXT: smulh z0.h, z0.h, z1.h ; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smull2 v2.4s, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: smull v0.4s, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: uzp2 v0.8h, v0.8h, v2.8h -; NONEON-NOSVE-NEXT: ret %1 = sext <8 x i16> %op1 to <8 x i32> %2 = sext <8 x i16> %op2 to <8 x i32> %mul = mul <8 x i32> %1, %2 @@ -291,19 +231,6 @@ define void @smulh_v16i16(ptr %a, ptr %b) { ; SVE2-NEXT: smulh z1.h, z2.h, z3.h ; SVE2-NEXT: stp q0, q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: smull2 v4.4s, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: smull v0.4s, v1.4h, v0.4h -; NONEON-NOSVE-NEXT: smull2 v1.4s, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: smull v2.4s, v2.4h, v3.4h -; NONEON-NOSVE-NEXT: uzp2 v0.8h, v0.8h, v4.8h -; NONEON-NOSVE-NEXT: uzp2 v1.8h, v2.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %1 = sext <16 x i16> %op1 to <16 x i32> @@ -332,12 +259,6 @@ define <2 x i32> @smulh_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; SVE2-NEXT: smulh z0.s, z0.s, z1.s ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smull v0.2d, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: shrn v0.2s, v0.2d, #32 -; NONEON-NOSVE-NEXT: ret %1 = sext <2 x i32> %op1 to <2 x i64> %2 = sext <2 x i32> %op2 to <2 x i64> %mul = mul <2 x i64> %1, %2 @@ -363,13 +284,6 @@ define <4 x i32> @smulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; SVE2-NEXT: smulh z0.s, z0.s, z1.s ; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smull2 v2.2d, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: smull v0.2d, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: uzp2 v0.4s, v0.4s, v2.4s -; NONEON-NOSVE-NEXT: ret %1 = sext <4 x i32> %op1 to <4 x i64> %2 = sext <4 x i32> %op2 to <4 x i64> %mul = mul <4 x i64> %1, %2 @@ -398,19 +312,6 @@ define void @smulh_v8i32(ptr %a, ptr %b) { ; SVE2-NEXT: smulh z1.s, z2.s, z3.s ; SVE2-NEXT: stp q0, q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: smull2 v4.2d, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: smull v0.2d, v1.2s, v0.2s -; NONEON-NOSVE-NEXT: smull2 v1.2d, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: smull v2.2d, v2.2s, v3.2s -; NONEON-NOSVE-NEXT: uzp2 v0.4s, v0.4s, v4.4s -; NONEON-NOSVE-NEXT: uzp2 v1.4s, v2.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %1 = sext <8 x i32> %op1 to <8 x i64> @@ -439,16 +340,6 @@ define <1 x i64> @smulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; SVE2-NEXT: smulh z0.d, z0.d, z1.d ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: fmov x9, d1 -; NONEON-NOSVE-NEXT: smulh x8, x8, x9 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <1 x i128> undef, i128 64, i128 0 %splat = shufflevector <1 x i128> %insert, <1 x i128> undef, <1 x i32> zeroinitializer %1 = sext <1 x i64> %op1 to <1 x i128> @@ -476,19 +367,6 @@ define <2 x i64> @smulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; SVE2-NEXT: smulh z0.d, z0.d, z1.d ; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov x8, v0.d[1] -; NONEON-NOSVE-NEXT: mov x9, v1.d[1] -; NONEON-NOSVE-NEXT: fmov x10, d0 -; NONEON-NOSVE-NEXT: fmov x11, d1 -; NONEON-NOSVE-NEXT: smulh x10, x10, x11 -; NONEON-NOSVE-NEXT: smulh x8, x8, x9 -; NONEON-NOSVE-NEXT: fmov d0, x10 -; NONEON-NOSVE-NEXT: fmov d1, x8 -; NONEON-NOSVE-NEXT: mov v0.d[1], v1.d[0] -; NONEON-NOSVE-NEXT: ret %1 = sext <2 x i64> %op1 to <2 x i128> %2 = sext <2 x i64> %op2 to <2 x i128> %mul = mul <2 x i128> %1, %2 @@ -517,31 +395,6 @@ define void @smulh_v4i64(ptr %a, ptr %b) { ; SVE2-NEXT: smulh z1.d, z2.d, z3.d ; SVE2-NEXT: stp q0, q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: smulh_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: mov x11, v0.d[1] -; NONEON-NOSVE-NEXT: mov x14, v3.d[1] -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: mov x10, v1.d[1] -; NONEON-NOSVE-NEXT: mov x13, v2.d[1] -; NONEON-NOSVE-NEXT: fmov x12, d3 -; NONEON-NOSVE-NEXT: smulh x8, x8, x9 -; NONEON-NOSVE-NEXT: fmov x9, d2 -; NONEON-NOSVE-NEXT: smulh x10, x10, x11 -; NONEON-NOSVE-NEXT: smulh x9, x9, x12 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: smulh x11, x13, x14 -; NONEON-NOSVE-NEXT: fmov d1, x10 -; NONEON-NOSVE-NEXT: fmov d2, x9 -; NONEON-NOSVE-NEXT: mov v0.d[1], v1.d[0] -; NONEON-NOSVE-NEXT: fmov d3, x11 -; NONEON-NOSVE-NEXT: mov v2.d[1], v3.d[0] -; NONEON-NOSVE-NEXT: stp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %1 = sext <4 x i64> %op1 to <4 x i128> @@ -580,15 +433,6 @@ define <4 x i8> @umulh_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; SVE2-NEXT: lsr z0.h, z0.h, #4 ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d2, #0xff00ff00ff00ff -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v2.8b -; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: mul v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ushr v0.4h, v0.4h, #4 -; NONEON-NOSVE-NEXT: ret %1 = zext <4 x i8> %op1 to <4 x i16> %2 = zext <4 x i8> %op2 to <4 x i16> %mul = mul <4 x i16> %1, %2 @@ -614,12 +458,6 @@ define <8 x i8> @umulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; SVE2-NEXT: umulh z0.b, z0.b, z1.b ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umull v0.8h, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: shrn v0.8b, v0.8h, #8 -; NONEON-NOSVE-NEXT: ret %1 = zext <8 x i8> %op1 to <8 x i16> %2 = zext <8 x i8> %op2 to <8 x i16> %mul = mul <8 x i16> %1, %2 @@ -645,13 +483,6 @@ define <16 x i8> @umulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; SVE2-NEXT: umulh z0.b, z0.b, z1.b ; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umull2 v2.8h, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: umull v0.8h, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: uzp2 v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %1 = zext <16 x i8> %op1 to <16 x i16> %2 = zext <16 x i8> %op2 to <16 x i16> %mul = mul <16 x i16> %1, %2 @@ -680,19 +511,6 @@ define void @umulh_v32i8(ptr %a, ptr %b) { ; SVE2-NEXT: umulh z1.b, z2.b, z3.b ; SVE2-NEXT: stp q0, q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: umull2 v4.8h, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: umull v0.8h, v1.8b, v0.8b -; NONEON-NOSVE-NEXT: umull2 v1.8h, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: umull v2.8h, v2.8b, v3.8b -; NONEON-NOSVE-NEXT: uzp2 v0.16b, v0.16b, v4.16b -; NONEON-NOSVE-NEXT: uzp2 v1.16b, v2.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %1 = zext <32 x i8> %op1 to <32 x i16> @@ -727,15 +545,6 @@ define <2 x i16> @umulh_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; SVE2-NEXT: lsr z0.s, z0.s, #16 ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d2, #0x00ffff0000ffff -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v2.8b -; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: mul v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ushr v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: ret %1 = zext <2 x i16> %op1 to <2 x i32> %2 = zext <2 x i16> %op2 to <2 x i32> %mul = mul <2 x i32> %1, %2 @@ -761,12 +570,6 @@ define <4 x i16> @umulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; SVE2-NEXT: umulh z0.h, z0.h, z1.h ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umull v0.4s, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: shrn v0.4h, v0.4s, #16 -; NONEON-NOSVE-NEXT: ret %1 = zext <4 x i16> %op1 to <4 x i32> %2 = zext <4 x i16> %op2 to <4 x i32> %mul = mul <4 x i32> %1, %2 @@ -792,13 +595,6 @@ define <8 x i16> @umulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; SVE2-NEXT: umulh z0.h, z0.h, z1.h ; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umull2 v2.4s, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: umull v0.4s, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: uzp2 v0.8h, v0.8h, v2.8h -; NONEON-NOSVE-NEXT: ret %1 = zext <8 x i16> %op1 to <8 x i32> %2 = zext <8 x i16> %op2 to <8 x i32> %mul = mul <8 x i32> %1, %2 @@ -827,19 +623,6 @@ define void @umulh_v16i16(ptr %a, ptr %b) { ; SVE2-NEXT: umulh z1.h, z2.h, z3.h ; SVE2-NEXT: stp q0, q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: umull2 v4.4s, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: umull v0.4s, v1.4h, v0.4h -; NONEON-NOSVE-NEXT: umull2 v1.4s, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: umull v2.4s, v2.4h, v3.4h -; NONEON-NOSVE-NEXT: uzp2 v0.8h, v0.8h, v4.8h -; NONEON-NOSVE-NEXT: uzp2 v1.8h, v2.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %1 = zext <16 x i16> %op1 to <16 x i32> @@ -868,12 +651,6 @@ define <2 x i32> @umulh_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; SVE2-NEXT: umulh z0.s, z0.s, z1.s ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umull v0.2d, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: shrn v0.2s, v0.2d, #32 -; NONEON-NOSVE-NEXT: ret %1 = zext <2 x i32> %op1 to <2 x i64> %2 = zext <2 x i32> %op2 to <2 x i64> %mul = mul <2 x i64> %1, %2 @@ -899,13 +676,6 @@ define <4 x i32> @umulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; SVE2-NEXT: umulh z0.s, z0.s, z1.s ; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umull2 v2.2d, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: umull v0.2d, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: uzp2 v0.4s, v0.4s, v2.4s -; NONEON-NOSVE-NEXT: ret %1 = zext <4 x i32> %op1 to <4 x i64> %2 = zext <4 x i32> %op2 to <4 x i64> %mul = mul <4 x i64> %1, %2 @@ -934,19 +704,6 @@ define void @umulh_v8i32(ptr %a, ptr %b) { ; SVE2-NEXT: umulh z1.s, z2.s, z3.s ; SVE2-NEXT: stp q0, q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: umull2 v4.2d, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: umull v0.2d, v1.2s, v0.2s -; NONEON-NOSVE-NEXT: umull2 v1.2d, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: umull v2.2d, v2.2s, v3.2s -; NONEON-NOSVE-NEXT: uzp2 v0.4s, v0.4s, v4.4s -; NONEON-NOSVE-NEXT: uzp2 v1.4s, v2.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %insert = insertelement <8 x i64> undef, i64 32, i64 0 @@ -977,16 +734,6 @@ define <1 x i64> @umulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; SVE2-NEXT: umulh z0.d, z0.d, z1.d ; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: fmov x9, d1 -; NONEON-NOSVE-NEXT: umulh x8, x8, x9 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %1 = zext <1 x i64> %op1 to <1 x i128> %2 = zext <1 x i64> %op2 to <1 x i128> %mul = mul <1 x i128> %1, %2 @@ -1012,19 +759,6 @@ define <2 x i64> @umulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; SVE2-NEXT: umulh z0.d, z0.d, z1.d ; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov x8, v0.d[1] -; NONEON-NOSVE-NEXT: mov x9, v1.d[1] -; NONEON-NOSVE-NEXT: fmov x10, d0 -; NONEON-NOSVE-NEXT: fmov x11, d1 -; NONEON-NOSVE-NEXT: umulh x10, x10, x11 -; NONEON-NOSVE-NEXT: umulh x8, x8, x9 -; NONEON-NOSVE-NEXT: fmov d0, x10 -; NONEON-NOSVE-NEXT: fmov d1, x8 -; NONEON-NOSVE-NEXT: mov v0.d[1], v1.d[0] -; NONEON-NOSVE-NEXT: ret %1 = zext <2 x i64> %op1 to <2 x i128> %2 = zext <2 x i64> %op2 to <2 x i128> %mul = mul <2 x i128> %1, %2 @@ -1053,31 +787,6 @@ define void @umulh_v4i64(ptr %a, ptr %b) { ; SVE2-NEXT: umulh z1.d, z2.d, z3.d ; SVE2-NEXT: stp q0, q1, [x0] ; SVE2-NEXT: ret -; -; NONEON-NOSVE-LABEL: umulh_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: mov x11, v0.d[1] -; NONEON-NOSVE-NEXT: mov x14, v3.d[1] -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: mov x10, v1.d[1] -; NONEON-NOSVE-NEXT: mov x13, v2.d[1] -; NONEON-NOSVE-NEXT: fmov x12, d3 -; NONEON-NOSVE-NEXT: umulh x8, x8, x9 -; NONEON-NOSVE-NEXT: fmov x9, d2 -; NONEON-NOSVE-NEXT: umulh x10, x10, x11 -; NONEON-NOSVE-NEXT: umulh x9, x9, x12 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: umulh x11, x13, x14 -; NONEON-NOSVE-NEXT: fmov d1, x10 -; NONEON-NOSVE-NEXT: fmov d2, x9 -; NONEON-NOSVE-NEXT: mov v0.d[1], v1.d[0] -; NONEON-NOSVE-NEXT: fmov d3, x11 -; NONEON-NOSVE-NEXT: mov v2.d[1], v3.d[0] -; NONEON-NOSVE-NEXT: stp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %1 = zext <4 x i64> %op1 to <4 x i128> diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll index 50eaa6c12d71..751f43768a51 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -18,12 +17,6 @@ define i8 @uaddv_v8i8(<8 x i8> %a) { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uaddv_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: addv b0, v0.8b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %a) ret i8 %res } @@ -37,12 +30,6 @@ define i8 @uaddv_v16i8(<16 x i8> %a) { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uaddv_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: addv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %a) ret i8 %res } @@ -57,14 +44,6 @@ define i8 @uaddv_v32i8(ptr %a) { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uaddv_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: add v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: addv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %op) ret i8 %res @@ -79,12 +58,6 @@ define i16 @uaddv_v4i16(<4 x i16> %a) { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uaddv_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: addv h0, v0.4h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %a) ret i16 %res } @@ -98,12 +71,6 @@ define i16 @uaddv_v8i16(<8 x i16> %a) { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uaddv_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: addv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %a) ret i16 %res } @@ -118,14 +85,6 @@ define i16 @uaddv_v16i16(ptr %a) { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uaddv_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: add v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: addv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %op) ret i16 %res @@ -140,12 +99,6 @@ define i32 @uaddv_v2i32(<2 x i32> %a) { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uaddv_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: addp v0.2s, v0.2s, v0.2s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %a) ret i32 %res } @@ -159,12 +112,6 @@ define i32 @uaddv_v4i32(<4 x i32> %a) { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uaddv_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: addv s0, v0.4s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a) ret i32 %res } @@ -179,14 +126,6 @@ define i32 @uaddv_v8i32(ptr %a) { ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uaddv_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: add v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: addv s0, v0.4s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %op) ret i32 %res @@ -200,12 +139,6 @@ define i64 @uaddv_v2i64(<2 x i64> %a) { ; CHECK-NEXT: uaddv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uaddv_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: addp d0, v0.2d -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: ret %res = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a) ret i64 %res } @@ -219,14 +152,6 @@ define i64 @uaddv_v4i64(ptr %a) { ; CHECK-NEXT: uaddv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uaddv_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: add v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: addp d0, v0.2d -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %op) ret i64 %res @@ -244,12 +169,6 @@ define i8 @smaxv_v8i8(<8 x i8> %a) { ; CHECK-NEXT: smaxv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smaxv_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smaxv b0, v0.8b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %a) ret i8 %res } @@ -262,12 +181,6 @@ define i8 @smaxv_v16i8(<16 x i8> %a) { ; CHECK-NEXT: smaxv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smaxv_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smaxv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %a) ret i8 %res } @@ -281,14 +194,6 @@ define i8 @smaxv_v32i8(ptr %a) { ; CHECK-NEXT: smaxv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smaxv_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: smax v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: smaxv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %op) ret i8 %res @@ -302,12 +207,6 @@ define i16 @smaxv_v4i16(<4 x i16> %a) { ; CHECK-NEXT: smaxv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smaxv_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smaxv h0, v0.4h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %a) ret i16 %res } @@ -320,12 +219,6 @@ define i16 @smaxv_v8i16(<8 x i16> %a) { ; CHECK-NEXT: smaxv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smaxv_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smaxv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %a) ret i16 %res } @@ -339,14 +232,6 @@ define i16 @smaxv_v16i16(ptr %a) { ; CHECK-NEXT: smaxv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smaxv_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: smax v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: smaxv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %op) ret i16 %res @@ -360,12 +245,6 @@ define i32 @smaxv_v2i32(<2 x i32> %a) { ; CHECK-NEXT: smaxv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smaxv_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smaxp v0.2s, v0.2s, v0.2s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %a) ret i32 %res } @@ -378,12 +257,6 @@ define i32 @smaxv_v4i32(<4 x i32> %a) { ; CHECK-NEXT: smaxv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smaxv_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smaxv s0, v0.4s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %a) ret i32 %res } @@ -397,14 +270,6 @@ define i32 @smaxv_v8i32(ptr %a) { ; CHECK-NEXT: smaxv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smaxv_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: smax v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: smaxv s0, v0.4s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %op) ret i32 %res @@ -419,17 +284,6 @@ define i64 @smaxv_v2i64(<2 x i64> %a) { ; CHECK-NEXT: smaxv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smaxv_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: cmgt d2, d0, d1 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %a) ret i64 %res } @@ -443,20 +297,6 @@ define i64 @smaxv_v4i64(ptr %a) { ; CHECK-NEXT: smaxv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: smaxv_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: cmgt v2.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: bit v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: cmgt d2, d0, d1 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %op) ret i64 %res @@ -474,12 +314,6 @@ define i8 @sminv_v8i8(<8 x i8> %a) { ; CHECK-NEXT: sminv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sminv_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sminv b0, v0.8b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %a) ret i8 %res } @@ -492,12 +326,6 @@ define i8 @sminv_v16i8(<16 x i8> %a) { ; CHECK-NEXT: sminv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sminv_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sminv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %a) ret i8 %res } @@ -511,14 +339,6 @@ define i8 @sminv_v32i8(ptr %a) { ; CHECK-NEXT: sminv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sminv_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: smin v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: sminv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %op) ret i8 %res @@ -532,12 +352,6 @@ define i16 @sminv_v4i16(<4 x i16> %a) { ; CHECK-NEXT: sminv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sminv_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sminv h0, v0.4h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %a) ret i16 %res } @@ -550,12 +364,6 @@ define i16 @sminv_v8i16(<8 x i16> %a) { ; CHECK-NEXT: sminv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sminv_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sminv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %a) ret i16 %res } @@ -569,14 +377,6 @@ define i16 @sminv_v16i16(ptr %a) { ; CHECK-NEXT: sminv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sminv_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: smin v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: sminv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %op) ret i16 %res @@ -590,12 +390,6 @@ define i32 @sminv_v2i32(<2 x i32> %a) { ; CHECK-NEXT: sminv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sminv_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sminp v0.2s, v0.2s, v0.2s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %a) ret i32 %res } @@ -608,12 +402,6 @@ define i32 @sminv_v4i32(<4 x i32> %a) { ; CHECK-NEXT: sminv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sminv_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sminv s0, v0.4s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %a) ret i32 %res } @@ -627,14 +415,6 @@ define i32 @sminv_v8i32(ptr %a) { ; CHECK-NEXT: sminv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sminv_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: smin v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: sminv s0, v0.4s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %op) ret i32 %res @@ -649,17 +429,6 @@ define i64 @sminv_v2i64(<2 x i64> %a) { ; CHECK-NEXT: sminv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sminv_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: cmgt d2, d1, d0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %a) ret i64 %res } @@ -673,20 +442,6 @@ define i64 @sminv_v4i64(ptr %a) { ; CHECK-NEXT: sminv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sminv_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cmgt v2.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: cmgt d2, d1, d0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %op) ret i64 %res @@ -704,12 +459,6 @@ define i8 @umaxv_v8i8(<8 x i8> %a) { ; CHECK-NEXT: umaxv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umaxv_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umaxv b0, v0.8b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %a) ret i8 %res } @@ -722,12 +471,6 @@ define i8 @umaxv_v16i8(<16 x i8> %a) { ; CHECK-NEXT: umaxv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umaxv_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umaxv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %a) ret i8 %res } @@ -741,14 +484,6 @@ define i8 @umaxv_v32i8(ptr %a) { ; CHECK-NEXT: umaxv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umaxv_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: umax v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: umaxv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> %op) ret i8 %res @@ -762,12 +497,6 @@ define i16 @umaxv_v4i16(<4 x i16> %a) { ; CHECK-NEXT: umaxv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umaxv_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umaxv h0, v0.4h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %a) ret i16 %res } @@ -780,12 +509,6 @@ define i16 @umaxv_v8i16(<8 x i16> %a) { ; CHECK-NEXT: umaxv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umaxv_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umaxv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %a) ret i16 %res } @@ -799,14 +522,6 @@ define i16 @umaxv_v16i16(ptr %a) { ; CHECK-NEXT: umaxv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umaxv_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: umax v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: umaxv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %op) ret i16 %res @@ -820,12 +535,6 @@ define i32 @umaxv_v2i32(<2 x i32> %a) { ; CHECK-NEXT: umaxv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umaxv_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umaxp v0.2s, v0.2s, v0.2s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %a) ret i32 %res } @@ -838,12 +547,6 @@ define i32 @umaxv_v4i32(<4 x i32> %a) { ; CHECK-NEXT: umaxv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umaxv_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umaxv s0, v0.4s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %a) ret i32 %res } @@ -857,14 +560,6 @@ define i32 @umaxv_v8i32(ptr %a) { ; CHECK-NEXT: umaxv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umaxv_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: umax v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: umaxv s0, v0.4s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %op) ret i32 %res @@ -879,17 +574,6 @@ define i64 @umaxv_v2i64(<2 x i64> %a) { ; CHECK-NEXT: umaxv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umaxv_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: cmhi d2, d0, d1 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %a) ret i64 %res } @@ -903,20 +587,6 @@ define i64 @umaxv_v4i64(ptr %a) { ; CHECK-NEXT: umaxv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: umaxv_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: cmhi v2.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: bit v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: cmhi d2, d0, d1 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %op) ret i64 %res @@ -934,12 +604,6 @@ define i8 @uminv_v8i8(<8 x i8> %a) { ; CHECK-NEXT: uminv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uminv_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: uminv b0, v0.8b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %a) ret i8 %res } @@ -952,12 +616,6 @@ define i8 @uminv_v16i8(<16 x i8> %a) { ; CHECK-NEXT: uminv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uminv_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: uminv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %a) ret i8 %res } @@ -971,14 +629,6 @@ define i8 @uminv_v32i8(ptr %a) { ; CHECK-NEXT: uminv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uminv_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: umin v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: uminv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %op) ret i8 %res @@ -992,12 +642,6 @@ define i16 @uminv_v4i16(<4 x i16> %a) { ; CHECK-NEXT: uminv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uminv_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: uminv h0, v0.4h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %a) ret i16 %res } @@ -1010,12 +654,6 @@ define i16 @uminv_v8i16(<8 x i16> %a) { ; CHECK-NEXT: uminv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uminv_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: uminv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %a) ret i16 %res } @@ -1029,14 +667,6 @@ define i16 @uminv_v16i16(ptr %a) { ; CHECK-NEXT: uminv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uminv_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: umin v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: uminv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %op) ret i16 %res @@ -1050,12 +680,6 @@ define i32 @uminv_v2i32(<2 x i32> %a) { ; CHECK-NEXT: uminv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uminv_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: uminp v0.2s, v0.2s, v0.2s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %a) ret i32 %res } @@ -1068,12 +692,6 @@ define i32 @uminv_v4i32(<4 x i32> %a) { ; CHECK-NEXT: uminv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uminv_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: uminv s0, v0.4s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %a) ret i32 %res } @@ -1087,14 +705,6 @@ define i32 @uminv_v8i32(ptr %a) { ; CHECK-NEXT: uminv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uminv_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: umin v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: uminv s0, v0.4s -; NONEON-NOSVE-NEXT: fmov w0, s0 -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %op) ret i32 %res @@ -1109,17 +719,6 @@ define i64 @uminv_v2i64(<2 x i64> %a) { ; CHECK-NEXT: uminv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uminv_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: cmhi d2, d1, d0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %a) ret i64 %res } @@ -1133,20 +732,6 @@ define i64 @uminv_v4i64(ptr %a) { ; CHECK-NEXT: uminv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uminv_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cmhi v2.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: cmhi d2, d1, d0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %op) ret i64 %res diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll index 97bd76311b61..d373a9063f85 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -25,35 +24,6 @@ define <4 x i8> @srem_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: shl v1.4h, v1.4h, #8 -; NONEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: sshr v1.4h, v1.4h, #8 -; NONEON-NOSVE-NEXT: smov w11, v1.h[0] -; NONEON-NOSVE-NEXT: smov w12, v0.h[0] -; NONEON-NOSVE-NEXT: smov w8, v1.h[1] -; NONEON-NOSVE-NEXT: smov w9, v0.h[1] -; NONEON-NOSVE-NEXT: smov w14, v1.h[2] -; NONEON-NOSVE-NEXT: smov w15, v0.h[2] -; NONEON-NOSVE-NEXT: smov w17, v1.h[3] -; NONEON-NOSVE-NEXT: smov w18, v0.h[3] -; NONEON-NOSVE-NEXT: sdiv w13, w12, w11 -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: fmov s0, w11 -; NONEON-NOSVE-NEXT: sdiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: mov v0.h[1], w8 -; NONEON-NOSVE-NEXT: sdiv w9, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: mov v0.h[2], w8 -; NONEON-NOSVE-NEXT: msub w8, w9, w17, w18 -; NONEON-NOSVE-NEXT: mov v0.h[3], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = srem <4 x i8> %op1, %op2 ret <4 x i8> %res } @@ -83,53 +53,6 @@ define <8 x i8> @srem_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: smov w11, v1.b[0] -; NONEON-NOSVE-NEXT: smov w12, v0.b[0] -; NONEON-NOSVE-NEXT: smov w8, v1.b[1] -; NONEON-NOSVE-NEXT: smov w9, v0.b[1] -; NONEON-NOSVE-NEXT: smov w14, v1.b[2] -; NONEON-NOSVE-NEXT: smov w15, v0.b[2] -; NONEON-NOSVE-NEXT: smov w17, v1.b[3] -; NONEON-NOSVE-NEXT: smov w18, v0.b[3] -; NONEON-NOSVE-NEXT: smov w1, v1.b[4] -; NONEON-NOSVE-NEXT: smov w2, v0.b[4] -; NONEON-NOSVE-NEXT: smov w4, v1.b[5] -; NONEON-NOSVE-NEXT: smov w5, v0.b[5] -; NONEON-NOSVE-NEXT: sdiv w13, w12, w11 -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: smov w13, v1.b[7] -; NONEON-NOSVE-NEXT: fmov s2, w11 -; NONEON-NOSVE-NEXT: smov w11, v0.b[6] -; NONEON-NOSVE-NEXT: sdiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: smov w10, v1.b[6] -; NONEON-NOSVE-NEXT: mov v2.b[1], w8 -; NONEON-NOSVE-NEXT: sdiv w0, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: smov w14, v0.b[7] -; NONEON-NOSVE-NEXT: mov v2.b[2], w8 -; NONEON-NOSVE-NEXT: sdiv w3, w2, w1 -; NONEON-NOSVE-NEXT: msub w8, w0, w17, w18 -; NONEON-NOSVE-NEXT: mov v2.b[3], w8 -; NONEON-NOSVE-NEXT: sdiv w9, w5, w4 -; NONEON-NOSVE-NEXT: msub w8, w3, w1, w2 -; NONEON-NOSVE-NEXT: mov v2.b[4], w8 -; NONEON-NOSVE-NEXT: sdiv w12, w11, w10 -; NONEON-NOSVE-NEXT: msub w8, w9, w4, w5 -; NONEON-NOSVE-NEXT: mov v2.b[5], w8 -; NONEON-NOSVE-NEXT: sdiv w9, w14, w13 -; NONEON-NOSVE-NEXT: msub w8, w12, w10, w11 -; NONEON-NOSVE-NEXT: mov v2.b[6], w8 -; NONEON-NOSVE-NEXT: msub w8, w9, w13, w14 -; NONEON-NOSVE-NEXT: mov v2.b[7], w8 -; NONEON-NOSVE-NEXT: fmov d0, d2 -; NONEON-NOSVE-NEXT: ret %res = srem <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -179,112 +102,6 @@ define <16 x i8> @srem_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: mls z0.b, p0/m, z3.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: stp x28, x27, [sp, #-80]! // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x26, x25, [sp, #16] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x24, x23, [sp, #32] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 80 -; NONEON-NOSVE-NEXT: .cfi_offset w19, -8 -; NONEON-NOSVE-NEXT: .cfi_offset w20, -16 -; NONEON-NOSVE-NEXT: .cfi_offset w21, -24 -; NONEON-NOSVE-NEXT: .cfi_offset w22, -32 -; NONEON-NOSVE-NEXT: .cfi_offset w23, -40 -; NONEON-NOSVE-NEXT: .cfi_offset w24, -48 -; NONEON-NOSVE-NEXT: .cfi_offset w25, -56 -; NONEON-NOSVE-NEXT: .cfi_offset w26, -64 -; NONEON-NOSVE-NEXT: .cfi_offset w27, -72 -; NONEON-NOSVE-NEXT: .cfi_offset w28, -80 -; NONEON-NOSVE-NEXT: smov w11, v1.b[0] -; NONEON-NOSVE-NEXT: smov w12, v0.b[0] -; NONEON-NOSVE-NEXT: smov w8, v1.b[1] -; NONEON-NOSVE-NEXT: smov w9, v0.b[1] -; NONEON-NOSVE-NEXT: smov w14, v1.b[2] -; NONEON-NOSVE-NEXT: smov w15, v0.b[2] -; NONEON-NOSVE-NEXT: smov w17, v1.b[3] -; NONEON-NOSVE-NEXT: smov w18, v0.b[3] -; NONEON-NOSVE-NEXT: smov w1, v1.b[4] -; NONEON-NOSVE-NEXT: smov w2, v0.b[4] -; NONEON-NOSVE-NEXT: smov w4, v1.b[5] -; NONEON-NOSVE-NEXT: smov w5, v0.b[5] -; NONEON-NOSVE-NEXT: sdiv w13, w12, w11 -; NONEON-NOSVE-NEXT: smov w7, v1.b[6] -; NONEON-NOSVE-NEXT: smov w19, v0.b[6] -; NONEON-NOSVE-NEXT: smov w21, v1.b[7] -; NONEON-NOSVE-NEXT: smov w22, v0.b[7] -; NONEON-NOSVE-NEXT: smov w24, v1.b[8] -; NONEON-NOSVE-NEXT: smov w25, v0.b[8] -; NONEON-NOSVE-NEXT: smov w27, v1.b[9] -; NONEON-NOSVE-NEXT: smov w28, v0.b[9] -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: smov w13, v1.b[11] -; NONEON-NOSVE-NEXT: fmov s2, w11 -; NONEON-NOSVE-NEXT: smov w11, v0.b[10] -; NONEON-NOSVE-NEXT: sdiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: smov w10, v1.b[10] -; NONEON-NOSVE-NEXT: mov v2.b[1], w8 -; NONEON-NOSVE-NEXT: sdiv w0, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: smov w14, v0.b[11] -; NONEON-NOSVE-NEXT: smov w16, v1.b[12] -; NONEON-NOSVE-NEXT: mov v2.b[2], w8 -; NONEON-NOSVE-NEXT: sdiv w3, w2, w1 -; NONEON-NOSVE-NEXT: msub w8, w0, w17, w18 -; NONEON-NOSVE-NEXT: smov w17, v0.b[12] -; NONEON-NOSVE-NEXT: smov w0, v1.b[13] -; NONEON-NOSVE-NEXT: mov v2.b[3], w8 -; NONEON-NOSVE-NEXT: sdiv w6, w5, w4 -; NONEON-NOSVE-NEXT: msub w8, w3, w1, w2 -; NONEON-NOSVE-NEXT: smov w1, v0.b[13] -; NONEON-NOSVE-NEXT: mov v2.b[4], w8 -; NONEON-NOSVE-NEXT: sdiv w20, w19, w7 -; NONEON-NOSVE-NEXT: msub w8, w6, w4, w5 -; NONEON-NOSVE-NEXT: mov v2.b[5], w8 -; NONEON-NOSVE-NEXT: sdiv w23, w22, w21 -; NONEON-NOSVE-NEXT: msub w8, w20, w7, w19 -; NONEON-NOSVE-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v2.b[6], w8 -; NONEON-NOSVE-NEXT: sdiv w26, w25, w24 -; NONEON-NOSVE-NEXT: msub w8, w23, w21, w22 -; NONEON-NOSVE-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v2.b[7], w8 -; NONEON-NOSVE-NEXT: sdiv w9, w28, w27 -; NONEON-NOSVE-NEXT: msub w8, w26, w24, w25 -; NONEON-NOSVE-NEXT: ldp x24, x23, [sp, #32] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp x26, x25, [sp, #16] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v2.b[8], w8 -; NONEON-NOSVE-NEXT: sdiv w12, w11, w10 -; NONEON-NOSVE-NEXT: msub w8, w9, w27, w28 -; NONEON-NOSVE-NEXT: mov v2.b[9], w8 -; NONEON-NOSVE-NEXT: sdiv w15, w14, w13 -; NONEON-NOSVE-NEXT: msub w8, w12, w10, w11 -; NONEON-NOSVE-NEXT: smov w10, v1.b[14] -; NONEON-NOSVE-NEXT: smov w11, v0.b[14] -; NONEON-NOSVE-NEXT: mov v2.b[10], w8 -; NONEON-NOSVE-NEXT: sdiv w18, w17, w16 -; NONEON-NOSVE-NEXT: msub w8, w15, w13, w14 -; NONEON-NOSVE-NEXT: smov w13, v1.b[15] -; NONEON-NOSVE-NEXT: smov w14, v0.b[15] -; NONEON-NOSVE-NEXT: mov v2.b[11], w8 -; NONEON-NOSVE-NEXT: sdiv w9, w1, w0 -; NONEON-NOSVE-NEXT: msub w8, w18, w16, w17 -; NONEON-NOSVE-NEXT: mov v2.b[12], w8 -; NONEON-NOSVE-NEXT: sdiv w12, w11, w10 -; NONEON-NOSVE-NEXT: msub w8, w9, w0, w1 -; NONEON-NOSVE-NEXT: mov v2.b[13], w8 -; NONEON-NOSVE-NEXT: sdiv w9, w14, w13 -; NONEON-NOSVE-NEXT: msub w8, w12, w10, w11 -; NONEON-NOSVE-NEXT: mov v2.b[14], w8 -; NONEON-NOSVE-NEXT: msub w8, w9, w13, w14 -; NONEON-NOSVE-NEXT: mov v2.b[15], w8 -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ldp x28, x27, [sp], #80 // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: ret %res = srem <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -372,279 +189,6 @@ define void @srem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: mls z2.b, p0/m, z7.b, z4.b ; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub sp, sp, #320 -; NONEON-NOSVE-NEXT: stp x29, x30, [sp, #224] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x28, x27, [sp, #240] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x26, x25, [sp, #256] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x24, x23, [sp, #272] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x22, x21, [sp, #288] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x20, x19, [sp, #304] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 320 -; NONEON-NOSVE-NEXT: .cfi_offset w19, -8 -; NONEON-NOSVE-NEXT: .cfi_offset w20, -16 -; NONEON-NOSVE-NEXT: .cfi_offset w21, -24 -; NONEON-NOSVE-NEXT: .cfi_offset w22, -32 -; NONEON-NOSVE-NEXT: .cfi_offset w23, -40 -; NONEON-NOSVE-NEXT: .cfi_offset w24, -48 -; NONEON-NOSVE-NEXT: .cfi_offset w25, -56 -; NONEON-NOSVE-NEXT: .cfi_offset w26, -64 -; NONEON-NOSVE-NEXT: .cfi_offset w27, -72 -; NONEON-NOSVE-NEXT: .cfi_offset w28, -80 -; NONEON-NOSVE-NEXT: .cfi_offset w30, -88 -; NONEON-NOSVE-NEXT: .cfi_offset w29, -96 -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: ldr q2, [x0] -; NONEON-NOSVE-NEXT: str x0, [sp, #216] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: smov w8, v1.b[1] -; NONEON-NOSVE-NEXT: smov w9, v0.b[1] -; NONEON-NOSVE-NEXT: smov w4, v3.b[1] -; NONEON-NOSVE-NEXT: smov w1, v2.b[1] -; NONEON-NOSVE-NEXT: smov w7, v3.b[7] -; NONEON-NOSVE-NEXT: smov w5, v2.b[7] -; NONEON-NOSVE-NEXT: smov w6, v3.b[8] -; NONEON-NOSVE-NEXT: smov w3, v2.b[8] -; NONEON-NOSVE-NEXT: smov w22, v3.b[9] -; NONEON-NOSVE-NEXT: smov w20, v2.b[9] -; NONEON-NOSVE-NEXT: smov w13, v3.b[0] -; NONEON-NOSVE-NEXT: smov w17, v3.b[3] -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: str w8, [sp, #100] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: smov w8, v1.b[0] -; NONEON-NOSVE-NEXT: str w9, [sp, #108] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: smov w9, v0.b[0] -; NONEON-NOSVE-NEXT: smov w14, v2.b[3] -; NONEON-NOSVE-NEXT: smov w15, v3.b[4] -; NONEON-NOSVE-NEXT: smov w12, v2.b[4] -; NONEON-NOSVE-NEXT: smov w2, v3.b[5] -; NONEON-NOSVE-NEXT: smov w18, v2.b[5] -; NONEON-NOSVE-NEXT: smov w0, v3.b[6] -; NONEON-NOSVE-NEXT: smov w16, v2.b[6] -; NONEON-NOSVE-NEXT: smov w21, v3.b[10] -; NONEON-NOSVE-NEXT: smov w19, v2.b[10] -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #36] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: ldr w30, [sp, #36] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: str w10, [sp, #116] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[2] -; NONEON-NOSVE-NEXT: smov w9, v0.b[2] -; NONEON-NOSVE-NEXT: stp w10, w8, [sp, #44] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[3] -; NONEON-NOSVE-NEXT: stp w9, w10, [sp, #52] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: smov w9, v0.b[3] -; NONEON-NOSVE-NEXT: sdiv w26, w14, w17 -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #72] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w11, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[4] -; NONEON-NOSVE-NEXT: smov w9, v0.b[4] -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #60] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[5] -; NONEON-NOSVE-NEXT: smov w9, v0.b[5] -; NONEON-NOSVE-NEXT: str w8, [sp, #96] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w9, [sp, #104] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #68] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[6] -; NONEON-NOSVE-NEXT: smov w9, v0.b[6] -; NONEON-NOSVE-NEXT: stp w11, w8, [sp, #80] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #112] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[7] -; NONEON-NOSVE-NEXT: stp w9, w10, [sp, #88] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: smov w9, v0.b[7] -; NONEON-NOSVE-NEXT: sdiv w25, w12, w15 -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #132] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[8] -; NONEON-NOSVE-NEXT: smov w9, v0.b[8] -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #120] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #140] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[9] -; NONEON-NOSVE-NEXT: smov w9, v0.b[9] -; NONEON-NOSVE-NEXT: str w8, [sp, #148] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w9, [sp, #156] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w11, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[10] -; NONEON-NOSVE-NEXT: smov w9, v0.b[10] -; NONEON-NOSVE-NEXT: str w10, [sp, #128] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #204] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[11] -; NONEON-NOSVE-NEXT: smov w9, v0.b[11] -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #192] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #212] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[12] -; NONEON-NOSVE-NEXT: smov w9, v0.b[12] -; NONEON-NOSVE-NEXT: str w8, [sp, #172] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w9, [sp, #180] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #200] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[13] -; NONEON-NOSVE-NEXT: smov w9, v0.b[13] -; NONEON-NOSVE-NEXT: stp w11, w8, [sp, #164] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: smov w11, v3.b[2] -; NONEON-NOSVE-NEXT: str w9, [sp, #176] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #188] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.b[14] -; NONEON-NOSVE-NEXT: smov w9, v0.b[14] -; NONEON-NOSVE-NEXT: str w8, [sp, #144] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w9, [sp, #152] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #184] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w9, v2.b[2] -; NONEON-NOSVE-NEXT: sdiv w8, w1, w4 -; NONEON-NOSVE-NEXT: str w10, [sp, #160] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: smov w10, v2.b[0] -; NONEON-NOSVE-NEXT: str w8, [sp, #24] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w8, w5, w7 -; NONEON-NOSVE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w8, w3, w6 -; NONEON-NOSVE-NEXT: str w8, [sp, #20] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w8, w20, w22 -; NONEON-NOSVE-NEXT: sdiv w24, w10, w13 -; NONEON-NOSVE-NEXT: str w8, [sp, #32] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: ldp w29, w8, [sp, #40] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w8, w8, w30, w29 -; NONEON-NOSVE-NEXT: ldp x29, x30, [sp, #224] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: fmov s4, w8 -; NONEON-NOSVE-NEXT: sdiv w23, w9, w11 -; NONEON-NOSVE-NEXT: msub w10, w24, w13, w10 -; NONEON-NOSVE-NEXT: ldr w13, [sp, #24] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: ldr w24, [sp, #100] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w13, w13, w4, w1 -; NONEON-NOSVE-NEXT: ldr w1, [sp, #116] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: ldr w4, [sp, #108] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: fmov s5, w10 -; NONEON-NOSVE-NEXT: msub w1, w1, w24, w4 -; NONEON-NOSVE-NEXT: mov v5.b[1], w13 -; NONEON-NOSVE-NEXT: mov v4.b[1], w1 -; NONEON-NOSVE-NEXT: ldr w1, [sp, #120] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w8, w23, w11, w9 -; NONEON-NOSVE-NEXT: ldr w11, [sp, #48] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w28, w18, w2 -; NONEON-NOSVE-NEXT: ldp w10, w9, [sp, #52] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp x24, x23, [sp, #272] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[2], w8 -; NONEON-NOSVE-NEXT: msub w8, w26, w17, w14 -; NONEON-NOSVE-NEXT: ldr w14, [sp, #72] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w9, w9, w11, w10 -; NONEON-NOSVE-NEXT: ldr w17, [sp, #96] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: smov w10, v3.b[11] -; NONEON-NOSVE-NEXT: smov w11, v2.b[11] -; NONEON-NOSVE-NEXT: mov v4.b[2], w9 -; NONEON-NOSVE-NEXT: mov v5.b[3], w8 -; NONEON-NOSVE-NEXT: msub w8, w25, w15, w12 -; NONEON-NOSVE-NEXT: ldp w13, w9, [sp, #76] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w27, w16, w0 -; NONEON-NOSVE-NEXT: ldr w15, [sp, #104] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp x26, x25, [sp, #256] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w9, w9, w14, w13 -; NONEON-NOSVE-NEXT: ldr w14, [sp, #60] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[4], w8 -; NONEON-NOSVE-NEXT: msub w8, w28, w2, w18 -; NONEON-NOSVE-NEXT: ldr w2, [sp, #156] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.b[3], w9 -; NONEON-NOSVE-NEXT: ldp w12, w9, [sp, #64] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[5], w8 -; NONEON-NOSVE-NEXT: msub w8, w27, w0, w16 -; NONEON-NOSVE-NEXT: ldr w0, [sp, #132] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w4, w19, w21 -; NONEON-NOSVE-NEXT: msub w9, w9, w14, w12 -; NONEON-NOSVE-NEXT: smov w12, v3.b[12] -; NONEON-NOSVE-NEXT: smov w14, v2.b[12] -; NONEON-NOSVE-NEXT: ldp x28, x27, [sp, #240] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[6], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #28] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.b[4], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #112] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w8, w8, w7, w5 -; NONEON-NOSVE-NEXT: ldr w5, [sp, #204] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w9, w9, w17, w15 -; NONEON-NOSVE-NEXT: ldr w17, [sp, #84] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[7], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #20] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w13, w11, w10 -; NONEON-NOSVE-NEXT: mov v4.b[5], w9 -; NONEON-NOSVE-NEXT: ldp w16, w9, [sp, #88] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w8, w8, w6, w3 -; NONEON-NOSVE-NEXT: ldr w3, [sp, #148] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w9, w9, w17, w16 -; NONEON-NOSVE-NEXT: smov w16, v3.b[13] -; NONEON-NOSVE-NEXT: smov w17, v2.b[13] -; NONEON-NOSVE-NEXT: mov v5.b[8], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #32] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.b[6], w9 -; NONEON-NOSVE-NEXT: msub w8, w8, w22, w20 -; NONEON-NOSVE-NEXT: sdiv w15, w14, w12 -; NONEON-NOSVE-NEXT: ldp w18, w9, [sp, #136] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[9], w8 -; NONEON-NOSVE-NEXT: msub w8, w4, w21, w19 -; NONEON-NOSVE-NEXT: msub w9, w9, w0, w18 -; NONEON-NOSVE-NEXT: ldp x20, x19, [sp, #304] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp x22, x21, [sp, #288] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.b[7], w9 -; NONEON-NOSVE-NEXT: mov v5.b[10], w8 -; NONEON-NOSVE-NEXT: msub w8, w13, w10, w11 -; NONEON-NOSVE-NEXT: ldp w0, w9, [sp, #124] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp w11, w10, [sp, #196] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: ldr w13, [sp, #192] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w18, w17, w16 -; NONEON-NOSVE-NEXT: msub w9, w9, w1, w0 -; NONEON-NOSVE-NEXT: mov v5.b[11], w8 -; NONEON-NOSVE-NEXT: smov w0, v3.b[14] -; NONEON-NOSVE-NEXT: msub w10, w10, w13, w11 -; NONEON-NOSVE-NEXT: smov w1, v2.b[14] -; NONEON-NOSVE-NEXT: msub w8, w15, w12, w14 -; NONEON-NOSVE-NEXT: mov v4.b[8], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #164] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp w15, w13, [sp, #168] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w9, w9, w3, w2 -; NONEON-NOSVE-NEXT: mov v5.b[12], w8 -; NONEON-NOSVE-NEXT: ldp w4, w3, [sp, #208] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp w14, w12, [sp, #176] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.b[9], w9 -; NONEON-NOSVE-NEXT: sdiv w2, w1, w0 -; NONEON-NOSVE-NEXT: smov w9, v3.b[15] -; NONEON-NOSVE-NEXT: msub w3, w3, w5, w4 -; NONEON-NOSVE-NEXT: smov w4, v2.b[15] -; NONEON-NOSVE-NEXT: msub w8, w18, w16, w17 -; NONEON-NOSVE-NEXT: ldr w16, [sp, #144] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.b[10], w3 -; NONEON-NOSVE-NEXT: mov v5.b[13], w8 -; NONEON-NOSVE-NEXT: mov v4.b[11], w10 -; NONEON-NOSVE-NEXT: ldr w10, [sp, #188] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w11, w4, w9 -; NONEON-NOSVE-NEXT: msub w8, w2, w0, w1 -; NONEON-NOSVE-NEXT: msub w10, w10, w13, w12 -; NONEON-NOSVE-NEXT: smov w12, v1.b[15] -; NONEON-NOSVE-NEXT: smov w13, v0.b[15] -; NONEON-NOSVE-NEXT: mov v5.b[14], w8 -; NONEON-NOSVE-NEXT: mov v4.b[12], w10 -; NONEON-NOSVE-NEXT: ldr w10, [sp, #184] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w10, w10, w15, w14 -; NONEON-NOSVE-NEXT: ldr w15, [sp, #152] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w14, w13, w12 -; NONEON-NOSVE-NEXT: msub w8, w11, w9, w4 -; NONEON-NOSVE-NEXT: mov v4.b[13], w10 -; NONEON-NOSVE-NEXT: ldr w10, [sp, #160] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[15], w8 -; NONEON-NOSVE-NEXT: ldr x8, [sp, #216] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w10, w10, w16, w15 -; NONEON-NOSVE-NEXT: mov v4.b[14], w10 -; NONEON-NOSVE-NEXT: msub w9, w14, w12, w13 -; NONEON-NOSVE-NEXT: mov v4.b[15], w9 -; NONEON-NOSVE-NEXT: stp q5, q4, [x8] -; NONEON-NOSVE-NEXT: add sp, sp, #320 -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = srem <32 x i8> %op1, %op2 @@ -666,33 +210,6 @@ define <4 x i16> @srem_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: smov w11, v1.h[0] -; NONEON-NOSVE-NEXT: smov w12, v0.h[0] -; NONEON-NOSVE-NEXT: smov w8, v1.h[1] -; NONEON-NOSVE-NEXT: smov w9, v0.h[1] -; NONEON-NOSVE-NEXT: smov w14, v1.h[2] -; NONEON-NOSVE-NEXT: smov w15, v0.h[2] -; NONEON-NOSVE-NEXT: smov w17, v1.h[3] -; NONEON-NOSVE-NEXT: smov w18, v0.h[3] -; NONEON-NOSVE-NEXT: sdiv w13, w12, w11 -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: fmov s0, w11 -; NONEON-NOSVE-NEXT: sdiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: mov v0.h[1], w8 -; NONEON-NOSVE-NEXT: sdiv w9, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: mov v0.h[2], w8 -; NONEON-NOSVE-NEXT: msub w8, w9, w17, w18 -; NONEON-NOSVE-NEXT: mov v0.h[3], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = srem <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -721,51 +238,6 @@ define <8 x i16> @srem_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: mls z0.h, p0/m, z3.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: smov w11, v1.h[0] -; NONEON-NOSVE-NEXT: smov w12, v0.h[0] -; NONEON-NOSVE-NEXT: smov w8, v1.h[1] -; NONEON-NOSVE-NEXT: smov w9, v0.h[1] -; NONEON-NOSVE-NEXT: smov w14, v1.h[2] -; NONEON-NOSVE-NEXT: smov w15, v0.h[2] -; NONEON-NOSVE-NEXT: smov w17, v1.h[3] -; NONEON-NOSVE-NEXT: smov w18, v0.h[3] -; NONEON-NOSVE-NEXT: smov w1, v1.h[4] -; NONEON-NOSVE-NEXT: smov w2, v0.h[4] -; NONEON-NOSVE-NEXT: smov w4, v1.h[5] -; NONEON-NOSVE-NEXT: smov w5, v0.h[5] -; NONEON-NOSVE-NEXT: sdiv w13, w12, w11 -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: smov w13, v1.h[7] -; NONEON-NOSVE-NEXT: fmov s2, w11 -; NONEON-NOSVE-NEXT: smov w11, v0.h[6] -; NONEON-NOSVE-NEXT: sdiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: smov w10, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[1], w8 -; NONEON-NOSVE-NEXT: sdiv w0, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: smov w14, v0.h[7] -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: sdiv w3, w2, w1 -; NONEON-NOSVE-NEXT: msub w8, w0, w17, w18 -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: sdiv w9, w5, w4 -; NONEON-NOSVE-NEXT: msub w8, w3, w1, w2 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: sdiv w12, w11, w10 -; NONEON-NOSVE-NEXT: msub w8, w9, w4, w5 -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: sdiv w9, w14, w13 -; NONEON-NOSVE-NEXT: msub w8, w12, w10, w11 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: msub w8, w9, w13, w14 -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = srem <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -810,139 +282,6 @@ define void @srem_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: mls z0.h, p0/m, z7.h, z1.h ; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub sp, sp, #144 -; NONEON-NOSVE-NEXT: stp x29, x30, [sp, #48] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x28, x27, [sp, #64] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x26, x25, [sp, #80] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x24, x23, [sp, #96] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x22, x21, [sp, #112] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 144 -; NONEON-NOSVE-NEXT: .cfi_offset w19, -8 -; NONEON-NOSVE-NEXT: .cfi_offset w20, -16 -; NONEON-NOSVE-NEXT: .cfi_offset w21, -24 -; NONEON-NOSVE-NEXT: .cfi_offset w22, -32 -; NONEON-NOSVE-NEXT: .cfi_offset w23, -40 -; NONEON-NOSVE-NEXT: .cfi_offset w24, -48 -; NONEON-NOSVE-NEXT: .cfi_offset w25, -56 -; NONEON-NOSVE-NEXT: .cfi_offset w26, -64 -; NONEON-NOSVE-NEXT: .cfi_offset w27, -72 -; NONEON-NOSVE-NEXT: .cfi_offset w28, -80 -; NONEON-NOSVE-NEXT: .cfi_offset w30, -88 -; NONEON-NOSVE-NEXT: .cfi_offset w29, -96 -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x0] -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: smov w8, v1.h[1] -; NONEON-NOSVE-NEXT: smov w9, v0.h[1] -; NONEON-NOSVE-NEXT: smov w20, v1.h[0] -; NONEON-NOSVE-NEXT: smov w21, v0.h[0] -; NONEON-NOSVE-NEXT: smov w19, v0.h[3] -; NONEON-NOSVE-NEXT: smov w5, v1.h[4] -; NONEON-NOSVE-NEXT: smov w2, v0.h[4] -; NONEON-NOSVE-NEXT: smov w1, v3.h[1] -; NONEON-NOSVE-NEXT: smov w23, v2.h[1] -; NONEON-NOSVE-NEXT: smov w25, v3.h[0] -; NONEON-NOSVE-NEXT: smov w26, v2.h[0] -; NONEON-NOSVE-NEXT: smov w6, v1.h[5] -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #36] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: smov w8, v1.h[2] -; NONEON-NOSVE-NEXT: smov w9, v0.h[2] -; NONEON-NOSVE-NEXT: smov w3, v0.h[5] -; NONEON-NOSVE-NEXT: smov w4, v1.h[6] -; NONEON-NOSVE-NEXT: smov w7, v0.h[6] -; NONEON-NOSVE-NEXT: smov w28, v3.h[2] -; NONEON-NOSVE-NEXT: smov w29, v2.h[2] -; NONEON-NOSVE-NEXT: smov w15, v3.h[3] -; NONEON-NOSVE-NEXT: smov w13, v2.h[3] -; NONEON-NOSVE-NEXT: smov w12, v3.h[4] -; NONEON-NOSVE-NEXT: smov w14, v3.h[5] -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #24] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w11, w21, w20 -; NONEON-NOSVE-NEXT: str w10, [sp, #44] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: smov w8, v1.h[3] -; NONEON-NOSVE-NEXT: stp w8, w11, [sp] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: smov w11, v2.h[4] -; NONEON-NOSVE-NEXT: ldr w22, [sp, #4] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w20, w22, w20, w21 -; NONEON-NOSVE-NEXT: sdiv w9, w19, w8 -; NONEON-NOSVE-NEXT: str w10, [sp, #32] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: smov w10, v3.h[6] -; NONEON-NOSVE-NEXT: fmov s5, w20 -; NONEON-NOSVE-NEXT: smov w20, v3.h[7] -; NONEON-NOSVE-NEXT: sdiv w8, w2, w5 -; NONEON-NOSVE-NEXT: sdiv w24, w23, w1 -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #16] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: sdiv w27, w26, w25 -; NONEON-NOSVE-NEXT: msub w1, w24, w1, w23 -; NONEON-NOSVE-NEXT: ldp w24, w23, [sp, #40] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w9, w3, w6 -; NONEON-NOSVE-NEXT: msub w21, w27, w25, w26 -; NONEON-NOSVE-NEXT: ldr w25, [sp, #36] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w23, w23, w25, w24 -; NONEON-NOSVE-NEXT: ldr w25, [sp, #24] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: fmov s4, w21 -; NONEON-NOSVE-NEXT: mov v5.h[1], w23 -; NONEON-NOSVE-NEXT: ldp w23, w21, [sp, #28] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.h[1], w1 -; NONEON-NOSVE-NEXT: sdiv w8, w7, w4 -; NONEON-NOSVE-NEXT: msub w21, w21, w25, w23 -; NONEON-NOSVE-NEXT: smov w23, v2.h[7] -; NONEON-NOSVE-NEXT: ldp x26, x25, [sp, #80] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.h[2], w21 -; NONEON-NOSVE-NEXT: ldp x22, x21, [sp, #112] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: sdiv w30, w29, w28 -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #8] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: smov w9, v2.h[5] -; NONEON-NOSVE-NEXT: smov w8, v2.h[6] -; NONEON-NOSVE-NEXT: sdiv w18, w13, w15 -; NONEON-NOSVE-NEXT: msub w1, w30, w28, w29 -; NONEON-NOSVE-NEXT: ldp x28, x27, [sp, #64] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp x29, x30, [sp, #48] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.h[2], w1 -; NONEON-NOSVE-NEXT: sdiv w16, w11, w12 -; NONEON-NOSVE-NEXT: msub w13, w18, w15, w13 -; NONEON-NOSVE-NEXT: ldr w15, [sp, #20] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: ldr w18, [sp] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w15, w15, w18, w19 -; NONEON-NOSVE-NEXT: mov v4.h[3], w13 -; NONEON-NOSVE-NEXT: smov w13, v1.h[7] -; NONEON-NOSVE-NEXT: mov v5.h[3], w15 -; NONEON-NOSVE-NEXT: smov w15, v0.h[7] -; NONEON-NOSVE-NEXT: sdiv w17, w9, w14 -; NONEON-NOSVE-NEXT: msub w11, w16, w12, w11 -; NONEON-NOSVE-NEXT: ldr w12, [sp, #16] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w12, w12, w5, w2 -; NONEON-NOSVE-NEXT: mov v4.h[4], w11 -; NONEON-NOSVE-NEXT: ldr w11, [sp, #12] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.h[4], w12 -; NONEON-NOSVE-NEXT: msub w11, w11, w6, w3 -; NONEON-NOSVE-NEXT: sdiv w24, w8, w10 -; NONEON-NOSVE-NEXT: msub w9, w17, w14, w9 -; NONEON-NOSVE-NEXT: mov v5.h[5], w11 -; NONEON-NOSVE-NEXT: mov v4.h[5], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #8] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w9, w9, w4, w7 -; NONEON-NOSVE-NEXT: sdiv w18, w23, w20 -; NONEON-NOSVE-NEXT: msub w8, w24, w10, w8 -; NONEON-NOSVE-NEXT: mov v5.h[6], w9 -; NONEON-NOSVE-NEXT: mov v4.h[6], w8 -; NONEON-NOSVE-NEXT: sdiv w12, w15, w13 -; NONEON-NOSVE-NEXT: msub w8, w18, w20, w23 -; NONEON-NOSVE-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp x24, x23, [sp, #96] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.h[7], w8 -; NONEON-NOSVE-NEXT: msub w9, w12, w13, w15 -; NONEON-NOSVE-NEXT: mov v5.h[7], w9 -; NONEON-NOSVE-NEXT: stp q4, q5, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #144 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = srem <16 x i16> %op1, %op2 @@ -961,23 +300,6 @@ define <2 x i32> @srem_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: fmov w9, s0 -; NONEON-NOSVE-NEXT: mov w11, v1.s[1] -; NONEON-NOSVE-NEXT: mov w12, v0.s[1] -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: sdiv w13, w12, w11 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: msub w9, w13, w11, w12 -; NONEON-NOSVE-NEXT: mov v0.s[1], w9 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = srem <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -993,30 +315,6 @@ define <4 x i32> @srem_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov w11, s1 -; NONEON-NOSVE-NEXT: fmov w12, s0 -; NONEON-NOSVE-NEXT: mov w8, v1.s[1] -; NONEON-NOSVE-NEXT: mov w9, v0.s[1] -; NONEON-NOSVE-NEXT: mov w14, v1.s[2] -; NONEON-NOSVE-NEXT: mov w15, v0.s[2] -; NONEON-NOSVE-NEXT: mov w17, v1.s[3] -; NONEON-NOSVE-NEXT: mov w18, v0.s[3] -; NONEON-NOSVE-NEXT: sdiv w13, w12, w11 -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: fmov s0, w11 -; NONEON-NOSVE-NEXT: sdiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: mov v0.s[1], w8 -; NONEON-NOSVE-NEXT: sdiv w9, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: mov v0.s[2], w8 -; NONEON-NOSVE-NEXT: msub w8, w9, w17, w18 -; NONEON-NOSVE-NEXT: mov v0.s[3], w8 -; NONEON-NOSVE-NEXT: ret %res = srem <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -1036,65 +334,6 @@ define void @srem_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: mls z1.s, p0/m, z5.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str x23, [sp, #-48]! // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 -; NONEON-NOSVE-NEXT: .cfi_offset w19, -8 -; NONEON-NOSVE-NEXT: .cfi_offset w20, -16 -; NONEON-NOSVE-NEXT: .cfi_offset w21, -24 -; NONEON-NOSVE-NEXT: .cfi_offset w22, -32 -; NONEON-NOSVE-NEXT: .cfi_offset w23, -48 -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: fmov w12, s0 -; NONEON-NOSVE-NEXT: fmov w3, s2 -; NONEON-NOSVE-NEXT: mov w9, v0.s[1] -; NONEON-NOSVE-NEXT: fmov w11, s1 -; NONEON-NOSVE-NEXT: fmov w2, s3 -; NONEON-NOSVE-NEXT: mov w8, v1.s[1] -; NONEON-NOSVE-NEXT: mov w17, v3.s[1] -; NONEON-NOSVE-NEXT: mov w18, v2.s[1] -; NONEON-NOSVE-NEXT: mov w14, v1.s[2] -; NONEON-NOSVE-NEXT: mov w15, v0.s[2] -; NONEON-NOSVE-NEXT: mov w5, v3.s[2] -; NONEON-NOSVE-NEXT: mov w6, v2.s[2] -; NONEON-NOSVE-NEXT: sdiv w13, w12, w11 -; NONEON-NOSVE-NEXT: mov w19, v3.s[3] -; NONEON-NOSVE-NEXT: mov w20, v2.s[3] -; NONEON-NOSVE-NEXT: mov w22, v1.s[3] -; NONEON-NOSVE-NEXT: mov w23, v0.s[3] -; NONEON-NOSVE-NEXT: sdiv w4, w3, w2 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: fmov s1, w11 -; NONEON-NOSVE-NEXT: sdiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w12, w4, w2, w3 -; NONEON-NOSVE-NEXT: fmov s0, w12 -; NONEON-NOSVE-NEXT: sdiv w1, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: mov v1.s[1], w8 -; NONEON-NOSVE-NEXT: sdiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w13, w1, w17, w18 -; NONEON-NOSVE-NEXT: mov v0.s[1], w13 -; NONEON-NOSVE-NEXT: sdiv w7, w6, w5 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: mov v1.s[2], w8 -; NONEON-NOSVE-NEXT: sdiv w21, w20, w19 -; NONEON-NOSVE-NEXT: msub w10, w7, w5, w6 -; NONEON-NOSVE-NEXT: mov v0.s[2], w10 -; NONEON-NOSVE-NEXT: sdiv w9, w23, w22 -; NONEON-NOSVE-NEXT: msub w10, w21, w19, w20 -; NONEON-NOSVE-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v0.s[3], w10 -; NONEON-NOSVE-NEXT: msub w8, w9, w22, w23 -; NONEON-NOSVE-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v1.s[3], w8 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ldr x23, [sp], #48 // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = srem <8 x i32> %op1, %op2 @@ -1113,17 +352,6 @@ define <1 x i64> @srem_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: sdiv x10, x9, x8 -; NONEON-NOSVE-NEXT: msub x8, x10, x8, x9 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %res = srem <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -1139,20 +367,6 @@ define <2 x i64> @srem_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: mov x11, v1.d[1] -; NONEON-NOSVE-NEXT: mov x12, v0.d[1] -; NONEON-NOSVE-NEXT: sdiv x10, x9, x8 -; NONEON-NOSVE-NEXT: sdiv x13, x12, x11 -; NONEON-NOSVE-NEXT: msub x8, x10, x8, x9 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: msub x9, x13, x11, x12 -; NONEON-NOSVE-NEXT: mov v0.d[1], x9 -; NONEON-NOSVE-NEXT: ret %res = srem <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -1172,33 +386,6 @@ define void @srem_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: mls z1.d, p0/m, z5.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: srem_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: fmov x15, d2 -; NONEON-NOSVE-NEXT: mov x12, v2.d[1] -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: fmov x14, d3 -; NONEON-NOSVE-NEXT: mov x11, v3.d[1] -; NONEON-NOSVE-NEXT: mov x17, v1.d[1] -; NONEON-NOSVE-NEXT: mov x18, v0.d[1] -; NONEON-NOSVE-NEXT: sdiv x10, x9, x8 -; NONEON-NOSVE-NEXT: sdiv x16, x15, x14 -; NONEON-NOSVE-NEXT: msub x8, x10, x8, x9 -; NONEON-NOSVE-NEXT: fmov d1, x8 -; NONEON-NOSVE-NEXT: sdiv x13, x12, x11 -; NONEON-NOSVE-NEXT: msub x10, x16, x14, x15 -; NONEON-NOSVE-NEXT: fmov d0, x10 -; NONEON-NOSVE-NEXT: sdiv x1, x18, x17 -; NONEON-NOSVE-NEXT: msub x9, x13, x11, x12 -; NONEON-NOSVE-NEXT: mov v0.d[1], x9 -; NONEON-NOSVE-NEXT: msub x11, x1, x17, x18 -; NONEON-NOSVE-NEXT: mov v1.d[1], x11 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = srem <4 x i64> %op1, %op2 @@ -1226,41 +413,6 @@ define <4 x i8> @urem_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: umov w11, v1.h[0] -; NONEON-NOSVE-NEXT: umov w12, v0.h[0] -; NONEON-NOSVE-NEXT: umov w8, v1.h[1] -; NONEON-NOSVE-NEXT: umov w9, v0.h[1] -; NONEON-NOSVE-NEXT: umov w14, v1.h[2] -; NONEON-NOSVE-NEXT: umov w15, v0.h[2] -; NONEON-NOSVE-NEXT: umov w17, v1.h[3] -; NONEON-NOSVE-NEXT: umov w18, v0.h[3] -; NONEON-NOSVE-NEXT: and w11, w11, #0xff -; NONEON-NOSVE-NEXT: and w12, w12, #0xff -; NONEON-NOSVE-NEXT: and w8, w8, #0xff -; NONEON-NOSVE-NEXT: udiv w13, w12, w11 -; NONEON-NOSVE-NEXT: and w9, w9, #0xff -; NONEON-NOSVE-NEXT: and w14, w14, #0xff -; NONEON-NOSVE-NEXT: and w15, w15, #0xff -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: and w12, w17, #0xff -; NONEON-NOSVE-NEXT: and w13, w18, #0xff -; NONEON-NOSVE-NEXT: fmov s0, w11 -; NONEON-NOSVE-NEXT: udiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: mov v0.h[1], w8 -; NONEON-NOSVE-NEXT: udiv w9, w13, w12 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: mov v0.h[2], w8 -; NONEON-NOSVE-NEXT: msub w8, w9, w12, w13 -; NONEON-NOSVE-NEXT: mov v0.h[3], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = urem <4 x i8> %op1, %op2 ret <4 x i8> %res } @@ -1290,53 +442,6 @@ define <8 x i8> @urem_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: umov w11, v1.b[0] -; NONEON-NOSVE-NEXT: umov w12, v0.b[0] -; NONEON-NOSVE-NEXT: umov w8, v1.b[1] -; NONEON-NOSVE-NEXT: umov w9, v0.b[1] -; NONEON-NOSVE-NEXT: umov w14, v1.b[2] -; NONEON-NOSVE-NEXT: umov w15, v0.b[2] -; NONEON-NOSVE-NEXT: umov w17, v1.b[3] -; NONEON-NOSVE-NEXT: umov w18, v0.b[3] -; NONEON-NOSVE-NEXT: umov w1, v1.b[4] -; NONEON-NOSVE-NEXT: umov w2, v0.b[4] -; NONEON-NOSVE-NEXT: umov w4, v1.b[5] -; NONEON-NOSVE-NEXT: umov w5, v0.b[5] -; NONEON-NOSVE-NEXT: udiv w13, w12, w11 -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: umov w13, v1.b[7] -; NONEON-NOSVE-NEXT: fmov s2, w11 -; NONEON-NOSVE-NEXT: umov w11, v0.b[6] -; NONEON-NOSVE-NEXT: udiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: umov w10, v1.b[6] -; NONEON-NOSVE-NEXT: mov v2.b[1], w8 -; NONEON-NOSVE-NEXT: udiv w0, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: umov w14, v0.b[7] -; NONEON-NOSVE-NEXT: mov v2.b[2], w8 -; NONEON-NOSVE-NEXT: udiv w3, w2, w1 -; NONEON-NOSVE-NEXT: msub w8, w0, w17, w18 -; NONEON-NOSVE-NEXT: mov v2.b[3], w8 -; NONEON-NOSVE-NEXT: udiv w9, w5, w4 -; NONEON-NOSVE-NEXT: msub w8, w3, w1, w2 -; NONEON-NOSVE-NEXT: mov v2.b[4], w8 -; NONEON-NOSVE-NEXT: udiv w12, w11, w10 -; NONEON-NOSVE-NEXT: msub w8, w9, w4, w5 -; NONEON-NOSVE-NEXT: mov v2.b[5], w8 -; NONEON-NOSVE-NEXT: udiv w9, w14, w13 -; NONEON-NOSVE-NEXT: msub w8, w12, w10, w11 -; NONEON-NOSVE-NEXT: mov v2.b[6], w8 -; NONEON-NOSVE-NEXT: msub w8, w9, w13, w14 -; NONEON-NOSVE-NEXT: mov v2.b[7], w8 -; NONEON-NOSVE-NEXT: fmov d0, d2 -; NONEON-NOSVE-NEXT: ret %res = urem <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -1386,112 +491,6 @@ define <16 x i8> @urem_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: mls z0.b, p0/m, z3.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: stp x28, x27, [sp, #-80]! // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x26, x25, [sp, #16] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x24, x23, [sp, #32] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 80 -; NONEON-NOSVE-NEXT: .cfi_offset w19, -8 -; NONEON-NOSVE-NEXT: .cfi_offset w20, -16 -; NONEON-NOSVE-NEXT: .cfi_offset w21, -24 -; NONEON-NOSVE-NEXT: .cfi_offset w22, -32 -; NONEON-NOSVE-NEXT: .cfi_offset w23, -40 -; NONEON-NOSVE-NEXT: .cfi_offset w24, -48 -; NONEON-NOSVE-NEXT: .cfi_offset w25, -56 -; NONEON-NOSVE-NEXT: .cfi_offset w26, -64 -; NONEON-NOSVE-NEXT: .cfi_offset w27, -72 -; NONEON-NOSVE-NEXT: .cfi_offset w28, -80 -; NONEON-NOSVE-NEXT: umov w11, v1.b[0] -; NONEON-NOSVE-NEXT: umov w12, v0.b[0] -; NONEON-NOSVE-NEXT: umov w8, v1.b[1] -; NONEON-NOSVE-NEXT: umov w9, v0.b[1] -; NONEON-NOSVE-NEXT: umov w14, v1.b[2] -; NONEON-NOSVE-NEXT: umov w15, v0.b[2] -; NONEON-NOSVE-NEXT: umov w17, v1.b[3] -; NONEON-NOSVE-NEXT: umov w18, v0.b[3] -; NONEON-NOSVE-NEXT: umov w1, v1.b[4] -; NONEON-NOSVE-NEXT: umov w2, v0.b[4] -; NONEON-NOSVE-NEXT: umov w4, v1.b[5] -; NONEON-NOSVE-NEXT: umov w5, v0.b[5] -; NONEON-NOSVE-NEXT: udiv w13, w12, w11 -; NONEON-NOSVE-NEXT: umov w7, v1.b[6] -; NONEON-NOSVE-NEXT: umov w19, v0.b[6] -; NONEON-NOSVE-NEXT: umov w21, v1.b[7] -; NONEON-NOSVE-NEXT: umov w22, v0.b[7] -; NONEON-NOSVE-NEXT: umov w24, v1.b[8] -; NONEON-NOSVE-NEXT: umov w25, v0.b[8] -; NONEON-NOSVE-NEXT: umov w27, v1.b[9] -; NONEON-NOSVE-NEXT: umov w28, v0.b[9] -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: umov w13, v1.b[11] -; NONEON-NOSVE-NEXT: fmov s2, w11 -; NONEON-NOSVE-NEXT: umov w11, v0.b[10] -; NONEON-NOSVE-NEXT: udiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: umov w10, v1.b[10] -; NONEON-NOSVE-NEXT: mov v2.b[1], w8 -; NONEON-NOSVE-NEXT: udiv w0, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: umov w14, v0.b[11] -; NONEON-NOSVE-NEXT: umov w16, v1.b[12] -; NONEON-NOSVE-NEXT: mov v2.b[2], w8 -; NONEON-NOSVE-NEXT: udiv w3, w2, w1 -; NONEON-NOSVE-NEXT: msub w8, w0, w17, w18 -; NONEON-NOSVE-NEXT: umov w17, v0.b[12] -; NONEON-NOSVE-NEXT: umov w0, v1.b[13] -; NONEON-NOSVE-NEXT: mov v2.b[3], w8 -; NONEON-NOSVE-NEXT: udiv w6, w5, w4 -; NONEON-NOSVE-NEXT: msub w8, w3, w1, w2 -; NONEON-NOSVE-NEXT: umov w1, v0.b[13] -; NONEON-NOSVE-NEXT: mov v2.b[4], w8 -; NONEON-NOSVE-NEXT: udiv w20, w19, w7 -; NONEON-NOSVE-NEXT: msub w8, w6, w4, w5 -; NONEON-NOSVE-NEXT: mov v2.b[5], w8 -; NONEON-NOSVE-NEXT: udiv w23, w22, w21 -; NONEON-NOSVE-NEXT: msub w8, w20, w7, w19 -; NONEON-NOSVE-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v2.b[6], w8 -; NONEON-NOSVE-NEXT: udiv w26, w25, w24 -; NONEON-NOSVE-NEXT: msub w8, w23, w21, w22 -; NONEON-NOSVE-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v2.b[7], w8 -; NONEON-NOSVE-NEXT: udiv w9, w28, w27 -; NONEON-NOSVE-NEXT: msub w8, w26, w24, w25 -; NONEON-NOSVE-NEXT: ldp x24, x23, [sp, #32] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp x26, x25, [sp, #16] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v2.b[8], w8 -; NONEON-NOSVE-NEXT: udiv w12, w11, w10 -; NONEON-NOSVE-NEXT: msub w8, w9, w27, w28 -; NONEON-NOSVE-NEXT: mov v2.b[9], w8 -; NONEON-NOSVE-NEXT: udiv w15, w14, w13 -; NONEON-NOSVE-NEXT: msub w8, w12, w10, w11 -; NONEON-NOSVE-NEXT: umov w10, v1.b[14] -; NONEON-NOSVE-NEXT: umov w11, v0.b[14] -; NONEON-NOSVE-NEXT: mov v2.b[10], w8 -; NONEON-NOSVE-NEXT: udiv w18, w17, w16 -; NONEON-NOSVE-NEXT: msub w8, w15, w13, w14 -; NONEON-NOSVE-NEXT: umov w13, v1.b[15] -; NONEON-NOSVE-NEXT: umov w14, v0.b[15] -; NONEON-NOSVE-NEXT: mov v2.b[11], w8 -; NONEON-NOSVE-NEXT: udiv w9, w1, w0 -; NONEON-NOSVE-NEXT: msub w8, w18, w16, w17 -; NONEON-NOSVE-NEXT: mov v2.b[12], w8 -; NONEON-NOSVE-NEXT: udiv w12, w11, w10 -; NONEON-NOSVE-NEXT: msub w8, w9, w0, w1 -; NONEON-NOSVE-NEXT: mov v2.b[13], w8 -; NONEON-NOSVE-NEXT: udiv w9, w14, w13 -; NONEON-NOSVE-NEXT: msub w8, w12, w10, w11 -; NONEON-NOSVE-NEXT: mov v2.b[14], w8 -; NONEON-NOSVE-NEXT: msub w8, w9, w13, w14 -; NONEON-NOSVE-NEXT: mov v2.b[15], w8 -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ldp x28, x27, [sp], #80 // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: ret %res = urem <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -1579,279 +578,6 @@ define void @urem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: mls z2.b, p0/m, z7.b, z4.b ; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub sp, sp, #320 -; NONEON-NOSVE-NEXT: stp x29, x30, [sp, #224] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x28, x27, [sp, #240] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x26, x25, [sp, #256] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x24, x23, [sp, #272] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x22, x21, [sp, #288] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x20, x19, [sp, #304] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 320 -; NONEON-NOSVE-NEXT: .cfi_offset w19, -8 -; NONEON-NOSVE-NEXT: .cfi_offset w20, -16 -; NONEON-NOSVE-NEXT: .cfi_offset w21, -24 -; NONEON-NOSVE-NEXT: .cfi_offset w22, -32 -; NONEON-NOSVE-NEXT: .cfi_offset w23, -40 -; NONEON-NOSVE-NEXT: .cfi_offset w24, -48 -; NONEON-NOSVE-NEXT: .cfi_offset w25, -56 -; NONEON-NOSVE-NEXT: .cfi_offset w26, -64 -; NONEON-NOSVE-NEXT: .cfi_offset w27, -72 -; NONEON-NOSVE-NEXT: .cfi_offset w28, -80 -; NONEON-NOSVE-NEXT: .cfi_offset w30, -88 -; NONEON-NOSVE-NEXT: .cfi_offset w29, -96 -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: ldr q2, [x0] -; NONEON-NOSVE-NEXT: str x0, [sp, #216] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: umov w8, v1.b[1] -; NONEON-NOSVE-NEXT: umov w9, v0.b[1] -; NONEON-NOSVE-NEXT: umov w4, v3.b[1] -; NONEON-NOSVE-NEXT: umov w1, v2.b[1] -; NONEON-NOSVE-NEXT: umov w7, v3.b[7] -; NONEON-NOSVE-NEXT: umov w5, v2.b[7] -; NONEON-NOSVE-NEXT: umov w6, v3.b[8] -; NONEON-NOSVE-NEXT: umov w3, v2.b[8] -; NONEON-NOSVE-NEXT: umov w22, v3.b[9] -; NONEON-NOSVE-NEXT: umov w20, v2.b[9] -; NONEON-NOSVE-NEXT: umov w13, v3.b[0] -; NONEON-NOSVE-NEXT: umov w17, v3.b[3] -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: str w8, [sp, #100] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: umov w8, v1.b[0] -; NONEON-NOSVE-NEXT: str w9, [sp, #108] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: umov w9, v0.b[0] -; NONEON-NOSVE-NEXT: umov w14, v2.b[3] -; NONEON-NOSVE-NEXT: umov w15, v3.b[4] -; NONEON-NOSVE-NEXT: umov w12, v2.b[4] -; NONEON-NOSVE-NEXT: umov w2, v3.b[5] -; NONEON-NOSVE-NEXT: umov w18, v2.b[5] -; NONEON-NOSVE-NEXT: umov w0, v3.b[6] -; NONEON-NOSVE-NEXT: umov w16, v2.b[6] -; NONEON-NOSVE-NEXT: umov w21, v3.b[10] -; NONEON-NOSVE-NEXT: umov w19, v2.b[10] -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #36] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: ldr w30, [sp, #36] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: str w10, [sp, #116] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[2] -; NONEON-NOSVE-NEXT: umov w9, v0.b[2] -; NONEON-NOSVE-NEXT: stp w10, w8, [sp, #44] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[3] -; NONEON-NOSVE-NEXT: stp w9, w10, [sp, #52] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: umov w9, v0.b[3] -; NONEON-NOSVE-NEXT: udiv w26, w14, w17 -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #72] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w11, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[4] -; NONEON-NOSVE-NEXT: umov w9, v0.b[4] -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #60] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[5] -; NONEON-NOSVE-NEXT: umov w9, v0.b[5] -; NONEON-NOSVE-NEXT: str w8, [sp, #96] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w9, [sp, #104] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #68] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[6] -; NONEON-NOSVE-NEXT: umov w9, v0.b[6] -; NONEON-NOSVE-NEXT: stp w11, w8, [sp, #80] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #112] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[7] -; NONEON-NOSVE-NEXT: stp w9, w10, [sp, #88] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: umov w9, v0.b[7] -; NONEON-NOSVE-NEXT: udiv w25, w12, w15 -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #132] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[8] -; NONEON-NOSVE-NEXT: umov w9, v0.b[8] -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #120] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #140] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[9] -; NONEON-NOSVE-NEXT: umov w9, v0.b[9] -; NONEON-NOSVE-NEXT: str w8, [sp, #148] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w9, [sp, #156] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w11, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[10] -; NONEON-NOSVE-NEXT: umov w9, v0.b[10] -; NONEON-NOSVE-NEXT: str w10, [sp, #128] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #204] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[11] -; NONEON-NOSVE-NEXT: umov w9, v0.b[11] -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #192] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #212] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[12] -; NONEON-NOSVE-NEXT: umov w9, v0.b[12] -; NONEON-NOSVE-NEXT: str w8, [sp, #172] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w9, [sp, #180] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #200] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[13] -; NONEON-NOSVE-NEXT: umov w9, v0.b[13] -; NONEON-NOSVE-NEXT: stp w11, w8, [sp, #164] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: umov w11, v3.b[2] -; NONEON-NOSVE-NEXT: str w9, [sp, #176] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #188] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.b[14] -; NONEON-NOSVE-NEXT: umov w9, v0.b[14] -; NONEON-NOSVE-NEXT: str w8, [sp, #144] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w9, [sp, #152] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: str w10, [sp, #184] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w9, v2.b[2] -; NONEON-NOSVE-NEXT: udiv w8, w1, w4 -; NONEON-NOSVE-NEXT: str w10, [sp, #160] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: umov w10, v2.b[0] -; NONEON-NOSVE-NEXT: str w8, [sp, #24] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w8, w5, w7 -; NONEON-NOSVE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w8, w3, w6 -; NONEON-NOSVE-NEXT: str w8, [sp, #20] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w8, w20, w22 -; NONEON-NOSVE-NEXT: udiv w24, w10, w13 -; NONEON-NOSVE-NEXT: str w8, [sp, #32] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: ldp w29, w8, [sp, #40] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w8, w8, w30, w29 -; NONEON-NOSVE-NEXT: ldp x29, x30, [sp, #224] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: fmov s4, w8 -; NONEON-NOSVE-NEXT: udiv w23, w9, w11 -; NONEON-NOSVE-NEXT: msub w10, w24, w13, w10 -; NONEON-NOSVE-NEXT: ldr w13, [sp, #24] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: ldr w24, [sp, #100] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w13, w13, w4, w1 -; NONEON-NOSVE-NEXT: ldr w1, [sp, #116] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: ldr w4, [sp, #108] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: fmov s5, w10 -; NONEON-NOSVE-NEXT: msub w1, w1, w24, w4 -; NONEON-NOSVE-NEXT: mov v5.b[1], w13 -; NONEON-NOSVE-NEXT: mov v4.b[1], w1 -; NONEON-NOSVE-NEXT: ldr w1, [sp, #120] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w8, w23, w11, w9 -; NONEON-NOSVE-NEXT: ldr w11, [sp, #48] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w28, w18, w2 -; NONEON-NOSVE-NEXT: ldp w10, w9, [sp, #52] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp x24, x23, [sp, #272] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[2], w8 -; NONEON-NOSVE-NEXT: msub w8, w26, w17, w14 -; NONEON-NOSVE-NEXT: ldr w14, [sp, #72] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w9, w9, w11, w10 -; NONEON-NOSVE-NEXT: ldr w17, [sp, #96] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: umov w10, v3.b[11] -; NONEON-NOSVE-NEXT: umov w11, v2.b[11] -; NONEON-NOSVE-NEXT: mov v4.b[2], w9 -; NONEON-NOSVE-NEXT: mov v5.b[3], w8 -; NONEON-NOSVE-NEXT: msub w8, w25, w15, w12 -; NONEON-NOSVE-NEXT: ldp w13, w9, [sp, #76] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w27, w16, w0 -; NONEON-NOSVE-NEXT: ldr w15, [sp, #104] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp x26, x25, [sp, #256] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w9, w9, w14, w13 -; NONEON-NOSVE-NEXT: ldr w14, [sp, #60] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[4], w8 -; NONEON-NOSVE-NEXT: msub w8, w28, w2, w18 -; NONEON-NOSVE-NEXT: ldr w2, [sp, #156] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.b[3], w9 -; NONEON-NOSVE-NEXT: ldp w12, w9, [sp, #64] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[5], w8 -; NONEON-NOSVE-NEXT: msub w8, w27, w0, w16 -; NONEON-NOSVE-NEXT: ldr w0, [sp, #132] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w4, w19, w21 -; NONEON-NOSVE-NEXT: msub w9, w9, w14, w12 -; NONEON-NOSVE-NEXT: umov w12, v3.b[12] -; NONEON-NOSVE-NEXT: umov w14, v2.b[12] -; NONEON-NOSVE-NEXT: ldp x28, x27, [sp, #240] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[6], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #28] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.b[4], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #112] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w8, w8, w7, w5 -; NONEON-NOSVE-NEXT: ldr w5, [sp, #204] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w9, w9, w17, w15 -; NONEON-NOSVE-NEXT: ldr w17, [sp, #84] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[7], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #20] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w13, w11, w10 -; NONEON-NOSVE-NEXT: mov v4.b[5], w9 -; NONEON-NOSVE-NEXT: ldp w16, w9, [sp, #88] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w8, w8, w6, w3 -; NONEON-NOSVE-NEXT: ldr w3, [sp, #148] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w9, w9, w17, w16 -; NONEON-NOSVE-NEXT: umov w16, v3.b[13] -; NONEON-NOSVE-NEXT: umov w17, v2.b[13] -; NONEON-NOSVE-NEXT: mov v5.b[8], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #32] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.b[6], w9 -; NONEON-NOSVE-NEXT: msub w8, w8, w22, w20 -; NONEON-NOSVE-NEXT: udiv w15, w14, w12 -; NONEON-NOSVE-NEXT: ldp w18, w9, [sp, #136] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[9], w8 -; NONEON-NOSVE-NEXT: msub w8, w4, w21, w19 -; NONEON-NOSVE-NEXT: msub w9, w9, w0, w18 -; NONEON-NOSVE-NEXT: ldp x20, x19, [sp, #304] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp x22, x21, [sp, #288] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.b[7], w9 -; NONEON-NOSVE-NEXT: mov v5.b[10], w8 -; NONEON-NOSVE-NEXT: msub w8, w13, w10, w11 -; NONEON-NOSVE-NEXT: ldp w0, w9, [sp, #124] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp w11, w10, [sp, #196] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: ldr w13, [sp, #192] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w18, w17, w16 -; NONEON-NOSVE-NEXT: msub w9, w9, w1, w0 -; NONEON-NOSVE-NEXT: mov v5.b[11], w8 -; NONEON-NOSVE-NEXT: umov w0, v3.b[14] -; NONEON-NOSVE-NEXT: msub w10, w10, w13, w11 -; NONEON-NOSVE-NEXT: umov w1, v2.b[14] -; NONEON-NOSVE-NEXT: msub w8, w15, w12, w14 -; NONEON-NOSVE-NEXT: mov v4.b[8], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #164] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp w15, w13, [sp, #168] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w9, w9, w3, w2 -; NONEON-NOSVE-NEXT: mov v5.b[12], w8 -; NONEON-NOSVE-NEXT: ldp w4, w3, [sp, #208] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp w14, w12, [sp, #176] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.b[9], w9 -; NONEON-NOSVE-NEXT: udiv w2, w1, w0 -; NONEON-NOSVE-NEXT: umov w9, v3.b[15] -; NONEON-NOSVE-NEXT: msub w3, w3, w5, w4 -; NONEON-NOSVE-NEXT: umov w4, v2.b[15] -; NONEON-NOSVE-NEXT: msub w8, w18, w16, w17 -; NONEON-NOSVE-NEXT: ldr w16, [sp, #144] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.b[10], w3 -; NONEON-NOSVE-NEXT: mov v5.b[13], w8 -; NONEON-NOSVE-NEXT: mov v4.b[11], w10 -; NONEON-NOSVE-NEXT: ldr w10, [sp, #188] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w11, w4, w9 -; NONEON-NOSVE-NEXT: msub w8, w2, w0, w1 -; NONEON-NOSVE-NEXT: msub w10, w10, w13, w12 -; NONEON-NOSVE-NEXT: umov w12, v1.b[15] -; NONEON-NOSVE-NEXT: umov w13, v0.b[15] -; NONEON-NOSVE-NEXT: mov v5.b[14], w8 -; NONEON-NOSVE-NEXT: mov v4.b[12], w10 -; NONEON-NOSVE-NEXT: ldr w10, [sp, #184] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w10, w10, w15, w14 -; NONEON-NOSVE-NEXT: ldr w15, [sp, #152] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w14, w13, w12 -; NONEON-NOSVE-NEXT: msub w8, w11, w9, w4 -; NONEON-NOSVE-NEXT: mov v4.b[13], w10 -; NONEON-NOSVE-NEXT: ldr w10, [sp, #160] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.b[15], w8 -; NONEON-NOSVE-NEXT: ldr x8, [sp, #216] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w10, w10, w16, w15 -; NONEON-NOSVE-NEXT: mov v4.b[14], w10 -; NONEON-NOSVE-NEXT: msub w9, w14, w12, w13 -; NONEON-NOSVE-NEXT: mov v4.b[15], w9 -; NONEON-NOSVE-NEXT: stp q5, q4, [x8] -; NONEON-NOSVE-NEXT: add sp, sp, #320 -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = urem <32 x i8> %op1, %op2 @@ -1873,33 +599,6 @@ define <4 x i16> @urem_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: umov w11, v1.h[0] -; NONEON-NOSVE-NEXT: umov w12, v0.h[0] -; NONEON-NOSVE-NEXT: umov w8, v1.h[1] -; NONEON-NOSVE-NEXT: umov w9, v0.h[1] -; NONEON-NOSVE-NEXT: umov w14, v1.h[2] -; NONEON-NOSVE-NEXT: umov w15, v0.h[2] -; NONEON-NOSVE-NEXT: umov w17, v1.h[3] -; NONEON-NOSVE-NEXT: umov w18, v0.h[3] -; NONEON-NOSVE-NEXT: udiv w13, w12, w11 -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: fmov s0, w11 -; NONEON-NOSVE-NEXT: udiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: mov v0.h[1], w8 -; NONEON-NOSVE-NEXT: udiv w9, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: mov v0.h[2], w8 -; NONEON-NOSVE-NEXT: msub w8, w9, w17, w18 -; NONEON-NOSVE-NEXT: mov v0.h[3], w8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = urem <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -1928,51 +627,6 @@ define <8 x i16> @urem_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: mls z0.h, p0/m, z3.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: umov w11, v1.h[0] -; NONEON-NOSVE-NEXT: umov w12, v0.h[0] -; NONEON-NOSVE-NEXT: umov w8, v1.h[1] -; NONEON-NOSVE-NEXT: umov w9, v0.h[1] -; NONEON-NOSVE-NEXT: umov w14, v1.h[2] -; NONEON-NOSVE-NEXT: umov w15, v0.h[2] -; NONEON-NOSVE-NEXT: umov w17, v1.h[3] -; NONEON-NOSVE-NEXT: umov w18, v0.h[3] -; NONEON-NOSVE-NEXT: umov w1, v1.h[4] -; NONEON-NOSVE-NEXT: umov w2, v0.h[4] -; NONEON-NOSVE-NEXT: umov w4, v1.h[5] -; NONEON-NOSVE-NEXT: umov w5, v0.h[5] -; NONEON-NOSVE-NEXT: udiv w13, w12, w11 -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: umov w13, v1.h[7] -; NONEON-NOSVE-NEXT: fmov s2, w11 -; NONEON-NOSVE-NEXT: umov w11, v0.h[6] -; NONEON-NOSVE-NEXT: udiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: umov w10, v1.h[6] -; NONEON-NOSVE-NEXT: mov v2.h[1], w8 -; NONEON-NOSVE-NEXT: udiv w0, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: umov w14, v0.h[7] -; NONEON-NOSVE-NEXT: mov v2.h[2], w8 -; NONEON-NOSVE-NEXT: udiv w3, w2, w1 -; NONEON-NOSVE-NEXT: msub w8, w0, w17, w18 -; NONEON-NOSVE-NEXT: mov v2.h[3], w8 -; NONEON-NOSVE-NEXT: udiv w9, w5, w4 -; NONEON-NOSVE-NEXT: msub w8, w3, w1, w2 -; NONEON-NOSVE-NEXT: mov v2.h[4], w8 -; NONEON-NOSVE-NEXT: udiv w12, w11, w10 -; NONEON-NOSVE-NEXT: msub w8, w9, w4, w5 -; NONEON-NOSVE-NEXT: mov v2.h[5], w8 -; NONEON-NOSVE-NEXT: udiv w9, w14, w13 -; NONEON-NOSVE-NEXT: msub w8, w12, w10, w11 -; NONEON-NOSVE-NEXT: mov v2.h[6], w8 -; NONEON-NOSVE-NEXT: msub w8, w9, w13, w14 -; NONEON-NOSVE-NEXT: mov v2.h[7], w8 -; NONEON-NOSVE-NEXT: mov v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %res = urem <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -2017,139 +671,6 @@ define void @urem_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: mls z0.h, p0/m, z7.h, z1.h ; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub sp, sp, #144 -; NONEON-NOSVE-NEXT: stp x29, x30, [sp, #48] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x28, x27, [sp, #64] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x26, x25, [sp, #80] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x24, x23, [sp, #96] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x22, x21, [sp, #112] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 144 -; NONEON-NOSVE-NEXT: .cfi_offset w19, -8 -; NONEON-NOSVE-NEXT: .cfi_offset w20, -16 -; NONEON-NOSVE-NEXT: .cfi_offset w21, -24 -; NONEON-NOSVE-NEXT: .cfi_offset w22, -32 -; NONEON-NOSVE-NEXT: .cfi_offset w23, -40 -; NONEON-NOSVE-NEXT: .cfi_offset w24, -48 -; NONEON-NOSVE-NEXT: .cfi_offset w25, -56 -; NONEON-NOSVE-NEXT: .cfi_offset w26, -64 -; NONEON-NOSVE-NEXT: .cfi_offset w27, -72 -; NONEON-NOSVE-NEXT: .cfi_offset w28, -80 -; NONEON-NOSVE-NEXT: .cfi_offset w30, -88 -; NONEON-NOSVE-NEXT: .cfi_offset w29, -96 -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: ldr q2, [x0] -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: umov w8, v1.h[1] -; NONEON-NOSVE-NEXT: umov w9, v0.h[1] -; NONEON-NOSVE-NEXT: umov w20, v1.h[0] -; NONEON-NOSVE-NEXT: umov w21, v0.h[0] -; NONEON-NOSVE-NEXT: umov w19, v0.h[3] -; NONEON-NOSVE-NEXT: umov w5, v1.h[4] -; NONEON-NOSVE-NEXT: umov w2, v0.h[4] -; NONEON-NOSVE-NEXT: umov w1, v3.h[1] -; NONEON-NOSVE-NEXT: umov w23, v2.h[1] -; NONEON-NOSVE-NEXT: umov w25, v3.h[0] -; NONEON-NOSVE-NEXT: umov w26, v2.h[0] -; NONEON-NOSVE-NEXT: umov w6, v1.h[5] -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #36] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: umov w8, v1.h[2] -; NONEON-NOSVE-NEXT: umov w9, v0.h[2] -; NONEON-NOSVE-NEXT: umov w3, v0.h[5] -; NONEON-NOSVE-NEXT: umov w4, v1.h[6] -; NONEON-NOSVE-NEXT: umov w7, v0.h[6] -; NONEON-NOSVE-NEXT: umov w28, v3.h[2] -; NONEON-NOSVE-NEXT: umov w29, v2.h[2] -; NONEON-NOSVE-NEXT: umov w15, v3.h[3] -; NONEON-NOSVE-NEXT: umov w13, v2.h[3] -; NONEON-NOSVE-NEXT: umov w12, v3.h[4] -; NONEON-NOSVE-NEXT: umov w14, v3.h[5] -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #24] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w11, w21, w20 -; NONEON-NOSVE-NEXT: str w10, [sp, #44] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: umov w8, v1.h[3] -; NONEON-NOSVE-NEXT: stp w8, w11, [sp] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: umov w11, v2.h[4] -; NONEON-NOSVE-NEXT: ldr w22, [sp, #4] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w20, w22, w20, w21 -; NONEON-NOSVE-NEXT: udiv w9, w19, w8 -; NONEON-NOSVE-NEXT: str w10, [sp, #32] // 4-byte Folded Spill -; NONEON-NOSVE-NEXT: umov w10, v3.h[6] -; NONEON-NOSVE-NEXT: fmov s5, w20 -; NONEON-NOSVE-NEXT: umov w20, v3.h[7] -; NONEON-NOSVE-NEXT: udiv w8, w2, w5 -; NONEON-NOSVE-NEXT: udiv w24, w23, w1 -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #16] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: udiv w27, w26, w25 -; NONEON-NOSVE-NEXT: msub w1, w24, w1, w23 -; NONEON-NOSVE-NEXT: ldp w24, w23, [sp, #40] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w9, w3, w6 -; NONEON-NOSVE-NEXT: msub w21, w27, w25, w26 -; NONEON-NOSVE-NEXT: ldr w25, [sp, #36] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w23, w23, w25, w24 -; NONEON-NOSVE-NEXT: ldr w25, [sp, #24] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: fmov s4, w21 -; NONEON-NOSVE-NEXT: mov v5.h[1], w23 -; NONEON-NOSVE-NEXT: ldp w23, w21, [sp, #28] // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.h[1], w1 -; NONEON-NOSVE-NEXT: udiv w8, w7, w4 -; NONEON-NOSVE-NEXT: msub w21, w21, w25, w23 -; NONEON-NOSVE-NEXT: umov w23, v2.h[7] -; NONEON-NOSVE-NEXT: ldp x26, x25, [sp, #80] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.h[2], w21 -; NONEON-NOSVE-NEXT: ldp x22, x21, [sp, #112] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: udiv w30, w29, w28 -; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #8] // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: umov w9, v2.h[5] -; NONEON-NOSVE-NEXT: umov w8, v2.h[6] -; NONEON-NOSVE-NEXT: udiv w18, w13, w15 -; NONEON-NOSVE-NEXT: msub w1, w30, w28, w29 -; NONEON-NOSVE-NEXT: ldp x28, x27, [sp, #64] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp x29, x30, [sp, #48] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.h[2], w1 -; NONEON-NOSVE-NEXT: udiv w16, w11, w12 -; NONEON-NOSVE-NEXT: msub w13, w18, w15, w13 -; NONEON-NOSVE-NEXT: ldr w15, [sp, #20] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: ldr w18, [sp] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w15, w15, w18, w19 -; NONEON-NOSVE-NEXT: mov v4.h[3], w13 -; NONEON-NOSVE-NEXT: umov w13, v1.h[7] -; NONEON-NOSVE-NEXT: mov v5.h[3], w15 -; NONEON-NOSVE-NEXT: umov w15, v0.h[7] -; NONEON-NOSVE-NEXT: udiv w17, w9, w14 -; NONEON-NOSVE-NEXT: msub w11, w16, w12, w11 -; NONEON-NOSVE-NEXT: ldr w12, [sp, #16] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w12, w12, w5, w2 -; NONEON-NOSVE-NEXT: mov v4.h[4], w11 -; NONEON-NOSVE-NEXT: ldr w11, [sp, #12] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v5.h[4], w12 -; NONEON-NOSVE-NEXT: msub w11, w11, w6, w3 -; NONEON-NOSVE-NEXT: udiv w24, w8, w10 -; NONEON-NOSVE-NEXT: msub w9, w17, w14, w9 -; NONEON-NOSVE-NEXT: mov v5.h[5], w11 -; NONEON-NOSVE-NEXT: mov v4.h[5], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #8] // 4-byte Folded Reload -; NONEON-NOSVE-NEXT: msub w9, w9, w4, w7 -; NONEON-NOSVE-NEXT: udiv w18, w23, w20 -; NONEON-NOSVE-NEXT: msub w8, w24, w10, w8 -; NONEON-NOSVE-NEXT: mov v5.h[6], w9 -; NONEON-NOSVE-NEXT: mov v4.h[6], w8 -; NONEON-NOSVE-NEXT: udiv w12, w15, w13 -; NONEON-NOSVE-NEXT: msub w8, w18, w20, w23 -; NONEON-NOSVE-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: ldp x24, x23, [sp, #96] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v4.h[7], w8 -; NONEON-NOSVE-NEXT: msub w9, w12, w13, w15 -; NONEON-NOSVE-NEXT: mov v5.h[7], w9 -; NONEON-NOSVE-NEXT: stp q4, q5, [x0] -; NONEON-NOSVE-NEXT: add sp, sp, #144 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = urem <16 x i16> %op1, %op2 @@ -2168,23 +689,6 @@ define <2 x i32> @urem_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: fmov w9, s0 -; NONEON-NOSVE-NEXT: mov w11, v1.s[1] -; NONEON-NOSVE-NEXT: mov w12, v0.s[1] -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: udiv w13, w12, w11 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: msub w9, w13, w11, w12 -; NONEON-NOSVE-NEXT: mov v0.s[1], w9 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = urem <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -2200,30 +704,6 @@ define <4 x i32> @urem_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov w11, s1 -; NONEON-NOSVE-NEXT: fmov w12, s0 -; NONEON-NOSVE-NEXT: mov w8, v1.s[1] -; NONEON-NOSVE-NEXT: mov w9, v0.s[1] -; NONEON-NOSVE-NEXT: mov w14, v1.s[2] -; NONEON-NOSVE-NEXT: mov w15, v0.s[2] -; NONEON-NOSVE-NEXT: mov w17, v1.s[3] -; NONEON-NOSVE-NEXT: mov w18, v0.s[3] -; NONEON-NOSVE-NEXT: udiv w13, w12, w11 -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: fmov s0, w11 -; NONEON-NOSVE-NEXT: udiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: mov v0.s[1], w8 -; NONEON-NOSVE-NEXT: udiv w9, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: mov v0.s[2], w8 -; NONEON-NOSVE-NEXT: msub w8, w9, w17, w18 -; NONEON-NOSVE-NEXT: mov v0.s[3], w8 -; NONEON-NOSVE-NEXT: ret %res = urem <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -2243,65 +723,6 @@ define void @urem_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: mls z1.s, p0/m, z5.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str x23, [sp, #-48]! // 8-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 -; NONEON-NOSVE-NEXT: .cfi_offset w19, -8 -; NONEON-NOSVE-NEXT: .cfi_offset w20, -16 -; NONEON-NOSVE-NEXT: .cfi_offset w21, -24 -; NONEON-NOSVE-NEXT: .cfi_offset w22, -32 -; NONEON-NOSVE-NEXT: .cfi_offset w23, -48 -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: fmov w12, s0 -; NONEON-NOSVE-NEXT: fmov w3, s2 -; NONEON-NOSVE-NEXT: mov w9, v0.s[1] -; NONEON-NOSVE-NEXT: fmov w11, s1 -; NONEON-NOSVE-NEXT: fmov w2, s3 -; NONEON-NOSVE-NEXT: mov w8, v1.s[1] -; NONEON-NOSVE-NEXT: mov w17, v3.s[1] -; NONEON-NOSVE-NEXT: mov w18, v2.s[1] -; NONEON-NOSVE-NEXT: mov w14, v1.s[2] -; NONEON-NOSVE-NEXT: mov w15, v0.s[2] -; NONEON-NOSVE-NEXT: mov w5, v3.s[2] -; NONEON-NOSVE-NEXT: mov w6, v2.s[2] -; NONEON-NOSVE-NEXT: udiv w13, w12, w11 -; NONEON-NOSVE-NEXT: mov w19, v3.s[3] -; NONEON-NOSVE-NEXT: mov w20, v2.s[3] -; NONEON-NOSVE-NEXT: mov w22, v1.s[3] -; NONEON-NOSVE-NEXT: mov w23, v0.s[3] -; NONEON-NOSVE-NEXT: udiv w4, w3, w2 -; NONEON-NOSVE-NEXT: msub w11, w13, w11, w12 -; NONEON-NOSVE-NEXT: fmov s1, w11 -; NONEON-NOSVE-NEXT: udiv w10, w9, w8 -; NONEON-NOSVE-NEXT: msub w12, w4, w2, w3 -; NONEON-NOSVE-NEXT: fmov s0, w12 -; NONEON-NOSVE-NEXT: udiv w1, w18, w17 -; NONEON-NOSVE-NEXT: msub w8, w10, w8, w9 -; NONEON-NOSVE-NEXT: mov v1.s[1], w8 -; NONEON-NOSVE-NEXT: udiv w16, w15, w14 -; NONEON-NOSVE-NEXT: msub w13, w1, w17, w18 -; NONEON-NOSVE-NEXT: mov v0.s[1], w13 -; NONEON-NOSVE-NEXT: udiv w7, w6, w5 -; NONEON-NOSVE-NEXT: msub w8, w16, w14, w15 -; NONEON-NOSVE-NEXT: mov v1.s[2], w8 -; NONEON-NOSVE-NEXT: udiv w21, w20, w19 -; NONEON-NOSVE-NEXT: msub w10, w7, w5, w6 -; NONEON-NOSVE-NEXT: mov v0.s[2], w10 -; NONEON-NOSVE-NEXT: udiv w9, w23, w22 -; NONEON-NOSVE-NEXT: msub w10, w21, w19, w20 -; NONEON-NOSVE-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v0.s[3], w10 -; NONEON-NOSVE-NEXT: msub w8, w9, w22, w23 -; NONEON-NOSVE-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload -; NONEON-NOSVE-NEXT: mov v1.s[3], w8 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ldr x23, [sp], #48 // 8-byte Folded Reload -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = urem <8 x i32> %op1, %op2 @@ -2320,17 +741,6 @@ define <1 x i64> @urem_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $q1 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: udiv x10, x9, x8 -; NONEON-NOSVE-NEXT: msub x8, x10, x8, x9 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: ret %res = urem <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -2346,20 +756,6 @@ define <2 x i64> @urem_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: mov x11, v1.d[1] -; NONEON-NOSVE-NEXT: mov x12, v0.d[1] -; NONEON-NOSVE-NEXT: udiv x10, x9, x8 -; NONEON-NOSVE-NEXT: udiv x13, x12, x11 -; NONEON-NOSVE-NEXT: msub x8, x10, x8, x9 -; NONEON-NOSVE-NEXT: fmov d0, x8 -; NONEON-NOSVE-NEXT: msub x9, x13, x11, x12 -; NONEON-NOSVE-NEXT: mov v0.d[1], x9 -; NONEON-NOSVE-NEXT: ret %res = urem <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -2379,33 +775,6 @@ define void @urem_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: mls z1.d, p0/m, z5.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: urem_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q1, [x1] -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: fmov x15, d2 -; NONEON-NOSVE-NEXT: mov x12, v2.d[1] -; NONEON-NOSVE-NEXT: fmov x8, d1 -; NONEON-NOSVE-NEXT: fmov x14, d3 -; NONEON-NOSVE-NEXT: mov x11, v3.d[1] -; NONEON-NOSVE-NEXT: mov x17, v1.d[1] -; NONEON-NOSVE-NEXT: mov x18, v0.d[1] -; NONEON-NOSVE-NEXT: udiv x10, x9, x8 -; NONEON-NOSVE-NEXT: udiv x16, x15, x14 -; NONEON-NOSVE-NEXT: msub x8, x10, x8, x9 -; NONEON-NOSVE-NEXT: fmov d1, x8 -; NONEON-NOSVE-NEXT: udiv x13, x12, x11 -; NONEON-NOSVE-NEXT: msub x10, x16, x14, x15 -; NONEON-NOSVE-NEXT: fmov d0, x10 -; NONEON-NOSVE-NEXT: udiv x1, x18, x17 -; NONEON-NOSVE-NEXT: msub x9, x13, x11, x12 -; NONEON-NOSVE-NEXT: mov v0.d[1], x9 -; NONEON-NOSVE-NEXT: msub x11, x1, x17, x18 -; NONEON-NOSVE-NEXT: mov v1.d[1], x11 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = urem <4 x i64> %op1, %op2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll index b3adf4720ece..906112f7ac39 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -17,14 +16,6 @@ define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.4h, w8 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <4 x i8> %op1, <4 x i8> %op2 ret <4 x i8> %sel } @@ -40,14 +31,6 @@ define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.8b, w8 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <8 x i8> %op1, <8 x i8> %op2 ret <8 x i8> %sel } @@ -63,14 +46,6 @@ define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.16b, w8 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <16 x i8> %op1, <16 x i8> %op2 ret <16 x i8> %sel } @@ -89,20 +64,6 @@ define void @select_v32i8(ptr %a, ptr %b, i1 %mask) { ; CHECK-NEXT: sel z1.b, p0, z1.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w2, #0x1 -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: ldr q2, [x0, #16] -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: ldr q4, [x1, #16] -; NONEON-NOSVE-NEXT: dup v0.16b, w8 -; NONEON-NOSVE-NEXT: bif v1.16b, v3.16b, v0.16b -; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load volatile <32 x i8>, ptr %a %op2 = load volatile <32 x i8>, ptr %b %sel = select i1 %mask, <32 x i8> %op1, <32 x i8> %op2 @@ -122,14 +83,6 @@ define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.2s, w8 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <2 x i16> %op1, <2 x i16> %op2 ret <2 x i16> %sel } @@ -146,14 +99,6 @@ define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.4h, w8 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <4 x i16> %op1, <4 x i16> %op2 ret <4 x i16> %sel } @@ -170,14 +115,6 @@ define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.8h, w8 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <8 x i16> %op1, <8 x i16> %op2 ret <8 x i16> %sel } @@ -197,20 +134,6 @@ define void @select_v16i16(ptr %a, ptr %b, i1 %mask) { ; CHECK-NEXT: sel z1.h, p0, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w2, #0x1 -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: ldr q2, [x0, #16] -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: ldr q4, [x1, #16] -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: bif v1.16b, v3.16b, v0.16b -; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load volatile <16 x i16>, ptr %a %op2 = load volatile <16 x i16>, ptr %b %sel = select i1 %mask, <16 x i16> %op1, <16 x i16> %op2 @@ -230,14 +153,6 @@ define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.2s, w8 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <2 x i32> %op1, <2 x i32> %op2 ret <2 x i32> %sel } @@ -254,14 +169,6 @@ define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: dup v2.4s, w8 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <4 x i32> %op1, <4 x i32> %op2 ret <4 x i32> %sel } @@ -281,20 +188,6 @@ define void @select_v8i32(ptr %a, ptr %b, i1 %mask) { ; CHECK-NEXT: sel z1.s, p0, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w2, #0x1 -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: ldr q2, [x0, #16] -; NONEON-NOSVE-NEXT: csetm w8, ne -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: ldr q4, [x1, #16] -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: bif v1.16b, v3.16b, v0.16b -; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load volatile <8 x i32>, ptr %a %op2 = load volatile <8 x i32>, ptr %b %sel = select i1 %mask, <8 x i32> %op1, <8 x i32> %op2 @@ -315,14 +208,6 @@ define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm x8, ne -; NONEON-NOSVE-NEXT: fmov d2, x8 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <1 x i64> %op1, <1 x i64> %op2 ret <1 x i64> %sel } @@ -340,14 +225,6 @@ define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) { ; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm x8, ne -; NONEON-NOSVE-NEXT: dup v2.2d, x8 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select i1 %mask, <2 x i64> %op1, <2 x i64> %op2 ret <2 x i64> %sel } @@ -368,20 +245,6 @@ define void @select_v4i64(ptr %a, ptr %b, i1 %mask) { ; CHECK-NEXT: sel z1.d, p0, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w2, #0x1 -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: ldr q2, [x0, #16] -; NONEON-NOSVE-NEXT: csetm x8, ne -; NONEON-NOSVE-NEXT: ldr q3, [x1] -; NONEON-NOSVE-NEXT: ldr q4, [x1, #16] -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: bif v1.16b, v3.16b, v0.16b -; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v4.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load volatile <4 x i64>, ptr %a %op2 = load volatile <4 x i64>, ptr %b %sel = select i1 %mask, <4 x i64> %op1, <4 x i64> %op2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll index a429cd82a449..9ed52e321d9a 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -20,16 +19,6 @@ define <4 x i8> @ashr_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d2, #0xff00ff00ff00ff -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: neg v1.4h, v1.4h -; NONEON-NOSVE-NEXT: sshl v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = ashr <4 x i8> %op1, %op2 ret <4 x i8> %res } @@ -43,12 +32,6 @@ define <8 x i8> @ashr_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.8b, v1.8b -; NONEON-NOSVE-NEXT: sshl v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = ashr <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -62,12 +45,6 @@ define <16 x i8> @ashr_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.16b, v1.16b -; NONEON-NOSVE-NEXT: sshl v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = ashr <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -83,17 +60,6 @@ define void @ashr_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: asr z1.b, p0/m, z1.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: neg v0.16b, v0.16b -; NONEON-NOSVE-NEXT: neg v1.16b, v1.16b -; NONEON-NOSVE-NEXT: sshl v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: sshl v1.16b, v3.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = ashr <32 x i8> %op1, %op2 @@ -112,16 +78,6 @@ define <2 x i16> @ashr_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d2, #0x00ffff0000ffff -; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: neg v1.2s, v1.2s -; NONEON-NOSVE-NEXT: sshl v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = ashr <2 x i16> %op1, %op2 ret <2 x i16> %res } @@ -135,12 +91,6 @@ define <4 x i16> @ashr_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.4h, v1.4h -; NONEON-NOSVE-NEXT: sshl v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = ashr <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -154,12 +104,6 @@ define <8 x i16> @ashr_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.8h, v1.8h -; NONEON-NOSVE-NEXT: sshl v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %res = ashr <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -175,17 +119,6 @@ define void @ashr_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: asr z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: neg v0.8h, v0.8h -; NONEON-NOSVE-NEXT: neg v1.8h, v1.8h -; NONEON-NOSVE-NEXT: sshl v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: sshl v1.8h, v3.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = ashr <16 x i16> %op1, %op2 @@ -202,12 +135,6 @@ define <2 x i32> @ashr_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.2s, v1.2s -; NONEON-NOSVE-NEXT: sshl v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = ashr <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -221,12 +148,6 @@ define <4 x i32> @ashr_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.4s, v1.4s -; NONEON-NOSVE-NEXT: sshl v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = ashr <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -242,17 +163,6 @@ define void @ashr_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: asr z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: neg v0.4s, v0.4s -; NONEON-NOSVE-NEXT: neg v1.4s, v1.4s -; NONEON-NOSVE-NEXT: sshl v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: sshl v1.4s, v3.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = ashr <8 x i32> %op1, %op2 @@ -269,12 +179,6 @@ define <1 x i64> @ashr_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg d1, d1 -; NONEON-NOSVE-NEXT: sshl d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %res = ashr <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -288,12 +192,6 @@ define <2 x i64> @ashr_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.2d, v1.2d -; NONEON-NOSVE-NEXT: sshl v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = ashr <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -309,17 +207,6 @@ define void @ashr_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: asr z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ashr_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: neg v0.2d, v0.2d -; NONEON-NOSVE-NEXT: neg v1.2d, v1.2d -; NONEON-NOSVE-NEXT: sshl v0.2d, v2.2d, v0.2d -; NONEON-NOSVE-NEXT: sshl v1.2d, v3.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = ashr <4 x i64> %op1, %op2 @@ -342,15 +229,6 @@ define <4 x i8> @lshr_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d2, #0xff00ff00ff00ff -; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v2.8b -; NONEON-NOSVE-NEXT: neg v1.4h, v1.4h -; NONEON-NOSVE-NEXT: ushl v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = lshr <4 x i8> %op1, %op2 ret <4 x i8> %res } @@ -364,12 +242,6 @@ define <8 x i8> @lshr_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.8b, v1.8b -; NONEON-NOSVE-NEXT: ushl v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = lshr <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -383,12 +255,6 @@ define <16 x i8> @lshr_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.16b, v1.16b -; NONEON-NOSVE-NEXT: ushl v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = lshr <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -404,17 +270,6 @@ define void @lshr_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: lsr z1.b, p0/m, z1.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: neg v0.16b, v0.16b -; NONEON-NOSVE-NEXT: neg v1.16b, v1.16b -; NONEON-NOSVE-NEXT: ushl v0.16b, v2.16b, v0.16b -; NONEON-NOSVE-NEXT: ushl v1.16b, v3.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = lshr <32 x i8> %op1, %op2 @@ -433,15 +288,6 @@ define <2 x i16> @lshr_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d2, #0x00ffff0000ffff -; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v2.8b -; NONEON-NOSVE-NEXT: neg v1.2s, v1.2s -; NONEON-NOSVE-NEXT: ushl v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = lshr <2 x i16> %op1, %op2 ret <2 x i16> %res } @@ -455,12 +301,6 @@ define <4 x i16> @lshr_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.4h, v1.4h -; NONEON-NOSVE-NEXT: ushl v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = lshr <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -474,12 +314,6 @@ define <8 x i16> @lshr_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.8h, v1.8h -; NONEON-NOSVE-NEXT: ushl v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %res = lshr <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -495,17 +329,6 @@ define void @lshr_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: lsr z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: neg v0.8h, v0.8h -; NONEON-NOSVE-NEXT: neg v1.8h, v1.8h -; NONEON-NOSVE-NEXT: ushl v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: ushl v1.8h, v3.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = lshr <16 x i16> %op1, %op2 @@ -522,12 +345,6 @@ define <2 x i32> @lshr_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.2s, v1.2s -; NONEON-NOSVE-NEXT: ushl v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = lshr <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -541,12 +358,6 @@ define <4 x i32> @lshr_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.4s, v1.4s -; NONEON-NOSVE-NEXT: ushl v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = lshr <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -562,17 +373,6 @@ define void @lshr_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: lsr z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: neg v0.4s, v0.4s -; NONEON-NOSVE-NEXT: neg v1.4s, v1.4s -; NONEON-NOSVE-NEXT: ushl v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: ushl v1.4s, v3.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = lshr <8 x i32> %op1, %op2 @@ -589,12 +389,6 @@ define <1 x i64> @lshr_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg d1, d1 -; NONEON-NOSVE-NEXT: ushl d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %res = lshr <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -608,12 +402,6 @@ define <2 x i64> @lshr_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: neg v1.2d, v1.2d -; NONEON-NOSVE-NEXT: ushl v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = lshr <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -629,17 +417,6 @@ define void @lshr_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: lsr z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: lshr_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: neg v0.2d, v0.2d -; NONEON-NOSVE-NEXT: neg v1.2d, v1.2d -; NONEON-NOSVE-NEXT: ushl v0.2d, v2.2d, v0.2d -; NONEON-NOSVE-NEXT: ushl v1.2d, v3.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = lshr <4 x i64> %op1, %op2 @@ -661,13 +438,6 @@ define <2 x i8> @shl_v2i8(<2 x i8> %op1, <2 x i8> %op2) { ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v2i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d2, #0x0000ff000000ff -; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ushl v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = shl <2 x i8> %op1, %op2 ret <2 x i8> %res } @@ -682,13 +452,6 @@ define <4 x i8> @shl_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d2, #0xff00ff00ff00ff -; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ushl v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = shl <4 x i8> %op1, %op2 ret <4 x i8> %res } @@ -702,11 +465,6 @@ define <8 x i8> @shl_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushl v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ret %res = shl <8 x i8> %op1, %op2 ret <8 x i8> %res } @@ -720,11 +478,6 @@ define <16 x i8> @shl_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushl v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %res = shl <16 x i8> %op1, %op2 ret <16 x i8> %res } @@ -740,15 +493,6 @@ define void @shl_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: lsl z1.b, p0/m, z1.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: ushl v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: ushl v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = shl <32 x i8> %op1, %op2 @@ -765,11 +509,6 @@ define <4 x i16> @shl_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushl v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %res = shl <4 x i16> %op1, %op2 ret <4 x i16> %res } @@ -783,11 +522,6 @@ define <8 x i16> @shl_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushl v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: ret %res = shl <8 x i16> %op1, %op2 ret <8 x i16> %res } @@ -803,15 +537,6 @@ define void @shl_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: lsl z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: ushl v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: ushl v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = shl <16 x i16> %op1, %op2 @@ -828,11 +553,6 @@ define <2 x i32> @shl_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushl v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: ret %res = shl <2 x i32> %op1, %op2 ret <2 x i32> %res } @@ -846,11 +566,6 @@ define <4 x i32> @shl_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushl v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: ret %res = shl <4 x i32> %op1, %op2 ret <4 x i32> %res } @@ -866,15 +581,6 @@ define void @shl_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: lsl z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: ushl v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: ushl v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %res = shl <8 x i32> %op1, %op2 @@ -891,11 +597,6 @@ define <1 x i64> @shl_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushl d0, d0, d1 -; NONEON-NOSVE-NEXT: ret %res = shl <1 x i64> %op1, %op2 ret <1 x i64> %res } @@ -909,11 +610,6 @@ define <2 x i64> @shl_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushl v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: ret %res = shl <2 x i64> %op1, %op2 ret <2 x i64> %res } @@ -929,15 +625,6 @@ define void @shl_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shl_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: ushl v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: ushl v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %res = shl <4 x i64> %op1, %op2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll index d9ca19baea7d..b285659258f3 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -16,13 +15,6 @@ define <4 x half> @ucvtf_v4i16_v4f16(<4 x i16> %op1) { ; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v4i16_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ucvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = uitofp <4 x i16> %op1 to <4 x half> ret <4 x half> %res } @@ -35,22 +27,6 @@ define void @ucvtf_v8i16_v8f16(ptr %a, ptr %b) { ; CHECK-NEXT: ucvtf z0.h, p0/m, z0.h ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v8i16_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ushll v1.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] -; NONEON-NOSVE-NEXT: ucvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: fcvtn v1.4h, v1.4s -; NONEON-NOSVE-NEXT: ucvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v0.4s -; NONEON-NOSVE-NEXT: str q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i16>, ptr %a %res = uitofp <8 x i16> %op1 to <8 x half> store <8 x half> %res, ptr %b @@ -66,29 +42,6 @@ define void @ucvtf_v16i16_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: ucvtf z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v16i16_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ushll v2.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v0.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ucvtf v2.4s, v2.4s -; NONEON-NOSVE-NEXT: ucvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: ucvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: ucvtf v3.4s, v3.4s -; NONEON-NOSVE-NEXT: fcvtn v2.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v2.8h, v1.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v3.4s -; NONEON-NOSVE-NEXT: stp q2, q0, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %res = uitofp <16 x i16> %op1 to <16 x half> store <16 x half> %res, ptr %b @@ -108,13 +61,6 @@ define <2 x float> @ucvtf_v2i16_v2f32(<2 x i16> %op1) { ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v2i16_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d1, #0x00ffff0000ffff -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ucvtf v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = uitofp <2 x i16> %op1 to <2 x float> ret <2 x float> %res } @@ -128,12 +74,6 @@ define <4 x float> @ucvtf_v4i16_v4f32(<4 x i16> %op1) { ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v4i16_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ucvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = uitofp <4 x i16> %op1 to <4 x float> ret <4 x float> %res } @@ -150,20 +90,6 @@ define void @ucvtf_v8i16_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v8i16_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ucvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ucvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i16>, ptr %a %res = uitofp <8 x i16> %op1 to <8 x float> store <8 x float> %res, ptr %b @@ -188,26 +114,6 @@ define void @ucvtf_v16i16_v16f32(ptr %a, ptr %b) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v16i16_v16f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: ucvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: ucvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ucvtf v2.4s, v2.4s -; NONEON-NOSVE-NEXT: ucvtf v3.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %res = uitofp <16 x i16> %op1 to <16 x float> store <16 x float> %res, ptr %b @@ -226,13 +132,6 @@ define <1 x double> @ucvtf_v1i16_v1f64(<1 x i16> %op1) { ; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: ucvtf d0, w8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v1i16_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: umov w8, v0.h[0] -; NONEON-NOSVE-NEXT: ucvtf d0, w8 -; NONEON-NOSVE-NEXT: ret %res = uitofp <1 x i16> %op1 to <1 x double> ret <1 x double> %res } @@ -247,14 +146,6 @@ define <2 x double> @ucvtf_v2i16_v2f64(<2 x i16> %op1) { ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v2i16_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d1, #0x00ffff0000ffff -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = uitofp <2 x i16> %op1 to <2 x double> ret <2 x double> %res } @@ -272,21 +163,6 @@ define void @ucvtf_v4i16_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v4i16_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ucvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i16>, ptr %a %res = uitofp <4 x i16> %op1 to <4 x double> store <4 x double> %res, ptr %b @@ -314,30 +190,6 @@ define void @ucvtf_v8i16_v8f64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q2, q1, [x1] ; CHECK-NEXT: stp q3, q0, [x1, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v8i16_v8f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-48]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #16] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: ushll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: ushll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ucvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: ucvtf v2.2d, v2.2d -; NONEON-NOSVE-NEXT: ucvtf v3.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q2, [x1] -; NONEON-NOSVE-NEXT: stp q1, q3, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #48 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i16>, ptr %a %res = uitofp <8 x i16> %op1 to <8 x double> store <8 x double> %res, ptr %b @@ -386,46 +238,6 @@ define void @ucvtf_v16i16_v16f64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q1, q2, [x1, #32] ; CHECK-NEXT: stp q3, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v16i16_v16f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-96]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: stp q2, q0, [sp, #32] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: stp q3, q1, [sp, #64] -; NONEON-NOSVE-NEXT: ldr d5, [sp, #56] -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ldr d4, [sp, #88] -; NONEON-NOSVE-NEXT: ldr d6, [sp, #72] -; NONEON-NOSVE-NEXT: ldr d7, [sp, #40] -; NONEON-NOSVE-NEXT: ushll v5.2d, v5.2s, #0 -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ushll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: ushll v4.2d, v4.2s, #0 -; NONEON-NOSVE-NEXT: ucvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: ushll v6.2d, v6.2s, #0 -; NONEON-NOSVE-NEXT: ushll v7.2d, v7.2s, #0 -; NONEON-NOSVE-NEXT: ucvtf v2.2d, v2.2d -; NONEON-NOSVE-NEXT: ucvtf v5.2d, v5.2d -; NONEON-NOSVE-NEXT: ucvtf v3.2d, v3.2d -; NONEON-NOSVE-NEXT: ucvtf v4.2d, v4.2d -; NONEON-NOSVE-NEXT: stp q0, q5, [x1] -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v7.2d -; NONEON-NOSVE-NEXT: stp q1, q4, [x1, #64] -; NONEON-NOSVE-NEXT: ucvtf v1.2d, v6.2d -; NONEON-NOSVE-NEXT: stp q2, q0, [x1, #32] -; NONEON-NOSVE-NEXT: stp q3, q1, [x1, #96] -; NONEON-NOSVE-NEXT: add sp, sp, #96 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %res = uitofp <16 x i16> %op1 to <16 x double> store <16 x double> %res, ptr %b @@ -445,13 +257,6 @@ define <2 x half> @ucvtf_v2i32_v2f16(<2 x i32> %op1) { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v2i32_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: ucvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = uitofp <2 x i32> %op1 to <2 x half> ret <2 x half> %res } @@ -465,12 +270,6 @@ define <4 x half> @ucvtf_v4i32_v4f16(<4 x i32> %op1) { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v4i32_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ucvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = uitofp <4 x i32> %op1 to <4 x half> ret <4 x half> %res } @@ -488,15 +287,6 @@ define <8 x half> @ucvtf_v8i32_v8f16(ptr %a) { ; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v8i32_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ucvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ucvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %res = uitofp <8 x i32> %op1 to <8 x half> ret <8 x half> %res @@ -521,21 +311,6 @@ define void @ucvtf_v16i32_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h ; CHECK-NEXT: stp q2, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v16i32_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x0] -; NONEON-NOSVE-NEXT: ucvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ucvtf v2.4s, v2.4s -; NONEON-NOSVE-NEXT: ucvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: ucvtf v3.4s, v3.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v1.4h, v1.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v3.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i32>, ptr %a %res = uitofp <16 x i32> %op1 to <16 x half> store <16 x half> %res, ptr %b @@ -554,11 +329,6 @@ define <2 x float> @ucvtf_v2i32_v2f32(<2 x i32> %op1) { ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v2i32_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ucvtf v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = uitofp <2 x i32> %op1 to <2 x float> ret <2 x float> %res } @@ -571,11 +341,6 @@ define <4 x float> @ucvtf_v4i32_v4f32(<4 x i32> %op1) { ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v4i32_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ucvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = uitofp <4 x i32> %op1 to <4 x float> ret <4 x float> %res } @@ -589,14 +354,6 @@ define void @ucvtf_v8i32_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: ucvtf z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v8i32_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ucvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ucvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %res = uitofp <8 x i32> %op1 to <8 x float> store <8 x float> %res, ptr %b @@ -616,12 +373,6 @@ define <2 x double> @ucvtf_v2i32_v2f64(<2 x i32> %op1) { ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v2i32_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = uitofp <2 x i32> %op1 to <2 x double> ret <2 x double> %res } @@ -638,20 +389,6 @@ define void @ucvtf_v4i32_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v4i32_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ucvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i32>, ptr %a %res = uitofp <4 x i32> %op1 to <4 x double> store <4 x double> %res, ptr %b @@ -676,26 +413,6 @@ define void @ucvtf_v8i32_v8f64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v8i32_v8f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: ushll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ushll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: ushll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: ushll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: ucvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ucvtf v2.2d, v2.2d -; NONEON-NOSVE-NEXT: ucvtf v3.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %res = uitofp <8 x i32> %op1 to <8 x double> store <8 x double> %res, ptr %b @@ -722,18 +439,6 @@ define <2 x half> @ucvtf_v2i64_v2f16(<2 x i64> %op1) { ; CHECK-NEXT: ldr d0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v2i64_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov x8, v0.d[1] -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: ucvtf s1, x9 -; NONEON-NOSVE-NEXT: ucvtf s0, x8 -; NONEON-NOSVE-NEXT: fcvt h2, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s1 -; NONEON-NOSVE-NEXT: mov v0.h[1], v2.h[0] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = uitofp <2 x i64> %op1 to <2 x half> ret <2 x half> %res } @@ -754,16 +459,6 @@ define <4 x half> @ucvtf_v4i64_v4f16(ptr %a) { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v4i64_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ucvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: fcvtn2 v0.4s, v1.2d -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %res = uitofp <4 x i64> %op1 to <4 x half> ret <4 x half> %res @@ -797,22 +492,6 @@ define <8 x half> @ucvtf_v8i64_v8f16(ptr %a) { ; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v8i64_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0, #32] -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ucvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: ucvtf v2.2d, v2.2d -; NONEON-NOSVE-NEXT: ucvtf v3.2d, v3.2d -; NONEON-NOSVE-NEXT: fcvtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: fcvtn v2.2s, v2.2d -; NONEON-NOSVE-NEXT: fcvtn2 v0.4s, v1.2d -; NONEON-NOSVE-NEXT: fcvtn2 v2.4s, v3.2d -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v2.4s -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i64>, ptr %a %res = uitofp <8 x i64> %op1 to <8 x half> ret <8 x half> %res @@ -831,12 +510,6 @@ define <2 x float> @ucvtf_v2i64_v2f32(<2 x i64> %op1) { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v2i64_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: ret %res = uitofp <2 x i64> %op1 to <2 x float> ret <2 x float> %res } @@ -854,15 +527,6 @@ define <4 x float> @ucvtf_v4i64_v4f32(ptr %a) { ; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v4i64_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ucvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: fcvtn2 v0.4s, v1.2d -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %res = uitofp <4 x i64> %op1 to <4 x float> ret <4 x float> %res @@ -887,21 +551,6 @@ define void @ucvtf_v8i64_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s ; CHECK-NEXT: stp q2, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v8i64_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x0] -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ucvtf v2.2d, v2.2d -; NONEON-NOSVE-NEXT: ucvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: ucvtf v3.2d, v3.2d -; NONEON-NOSVE-NEXT: fcvtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: fcvtn v1.2s, v1.2d -; NONEON-NOSVE-NEXT: fcvtn2 v0.4s, v2.2d -; NONEON-NOSVE-NEXT: fcvtn2 v1.4s, v3.2d -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i64>, ptr %a %res = uitofp <8 x i64> %op1 to <8 x float> store <8 x float> %res, ptr %b @@ -920,11 +569,6 @@ define <2 x double> @ucvtf_v2i64_v2f64(<2 x i64> %op1) { ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v2i64_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = uitofp <2 x i64> %op1 to <2 x double> ret <2 x double> %res } @@ -938,14 +582,6 @@ define void @ucvtf_v4i64_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: ucvtf z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_v4i64_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ucvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ucvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %res = uitofp <4 x i64> %op1 to <4 x double> store <4 x double> %res, ptr %b @@ -964,13 +600,6 @@ define <4 x half> @scvtf_v4i16_v4f16(<4 x i16> %op1) { ; CHECK-NEXT: scvtf z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v4i16_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: scvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = sitofp <4 x i16> %op1 to <4 x half> ret <4 x half> %res } @@ -983,22 +612,6 @@ define void @scvtf_v8i16_v8f16(ptr %a, ptr %b) { ; CHECK-NEXT: scvtf z0.h, p0/m, z0.h ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v8i16_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: sshll v1.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] -; NONEON-NOSVE-NEXT: scvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: fcvtn v1.4h, v1.4s -; NONEON-NOSVE-NEXT: scvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v0.4s -; NONEON-NOSVE-NEXT: str q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i16>, ptr %a %res = sitofp <8 x i16> %op1 to <8 x half> store <8 x half> %res, ptr %b @@ -1014,29 +627,6 @@ define void @scvtf_v16i16_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: scvtf z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v16i16_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: sshll v2.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v0.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: scvtf v2.4s, v2.4s -; NONEON-NOSVE-NEXT: scvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: scvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: scvtf v3.4s, v3.4s -; NONEON-NOSVE-NEXT: fcvtn v2.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v2.8h, v1.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v3.4s -; NONEON-NOSVE-NEXT: stp q2, q0, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %res = sitofp <16 x i16> %op1 to <16 x half> store <16 x half> %res, ptr %b @@ -1055,13 +645,6 @@ define <2 x float> @scvtf_v2i16_v2f32(<2 x i16> %op1) { ; CHECK-NEXT: scvtf z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v2i16_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: scvtf v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = sitofp <2 x i16> %op1 to <2 x float> ret <2 x float> %res } @@ -1075,12 +658,6 @@ define <4 x float> @scvtf_v4i16_v4f32(<4 x i16> %op1) { ; CHECK-NEXT: scvtf z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v4i16_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: scvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = sitofp <4 x i16> %op1 to <4 x float> ret <4 x float> %res } @@ -1097,20 +674,6 @@ define void @scvtf_v8i16_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: scvtf z0.s, p0/m, z0.s ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v8i16_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: scvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: scvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i16>, ptr %a %res = sitofp <8 x i16> %op1 to <8 x float> store <8 x float> %res, ptr %b @@ -1135,26 +698,6 @@ define void @scvtf_v16i16_v16f32(ptr %a, ptr %b) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v16i16_v16f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: scvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: scvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: scvtf v2.4s, v2.4s -; NONEON-NOSVE-NEXT: scvtf v3.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %res = sitofp <16 x i16> %op1 to <16 x float> store <16 x float> %res, ptr %b @@ -1176,14 +719,6 @@ define <2 x double> @scvtf_v2i16_v2f64(<2 x i16> %op1) { ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v2i16_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = sitofp <2 x i16> %op1 to <2 x double> ret <2 x double> %res } @@ -1201,21 +736,6 @@ define void @scvtf_v4i16_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v4i16_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: scvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i16>, ptr %a %res = sitofp <4 x i16> %op1 to <4 x double> store <4 x double> %res, ptr %b @@ -1243,30 +763,6 @@ define void @scvtf_v8i16_v8f64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q2, q1, [x1] ; CHECK-NEXT: stp q3, q0, [x1, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v8i16_v8f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-48]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #16] -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #40] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: sshll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: sshll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: scvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: scvtf v2.2d, v2.2d -; NONEON-NOSVE-NEXT: scvtf v3.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q2, [x1] -; NONEON-NOSVE-NEXT: stp q1, q3, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #48 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i16>, ptr %a %res = sitofp <8 x i16> %op1 to <8 x double> store <8 x double> %res, ptr %b @@ -1315,46 +811,6 @@ define void @scvtf_v16i16_v16f64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q1, q2, [x1, #32] ; CHECK-NEXT: stp q3, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v16i16_v16f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-96]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #8] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #24] -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NONEON-NOSVE-NEXT: sshll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NONEON-NOSVE-NEXT: stp q2, q0, [sp, #32] -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: sshll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: stp q3, q1, [sp, #64] -; NONEON-NOSVE-NEXT: ldr d5, [sp, #56] -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: ldr d4, [sp, #88] -; NONEON-NOSVE-NEXT: ldr d6, [sp, #72] -; NONEON-NOSVE-NEXT: ldr d7, [sp, #40] -; NONEON-NOSVE-NEXT: sshll v5.2d, v5.2s, #0 -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: sshll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: sshll v4.2d, v4.2s, #0 -; NONEON-NOSVE-NEXT: scvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: sshll v6.2d, v6.2s, #0 -; NONEON-NOSVE-NEXT: sshll v7.2d, v7.2s, #0 -; NONEON-NOSVE-NEXT: scvtf v2.2d, v2.2d -; NONEON-NOSVE-NEXT: scvtf v5.2d, v5.2d -; NONEON-NOSVE-NEXT: scvtf v3.2d, v3.2d -; NONEON-NOSVE-NEXT: scvtf v4.2d, v4.2d -; NONEON-NOSVE-NEXT: stp q0, q5, [x1] -; NONEON-NOSVE-NEXT: scvtf v0.2d, v7.2d -; NONEON-NOSVE-NEXT: stp q1, q4, [x1, #64] -; NONEON-NOSVE-NEXT: scvtf v1.2d, v6.2d -; NONEON-NOSVE-NEXT: stp q2, q0, [x1, #32] -; NONEON-NOSVE-NEXT: stp q3, q1, [x1, #96] -; NONEON-NOSVE-NEXT: add sp, sp, #96 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %res = sitofp <16 x i16> %op1 to <16 x double> store <16 x double> %res, ptr %b @@ -1374,13 +830,6 @@ define <2 x half> @scvtf_v2i32_v2f16(<2 x i32> %op1) { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v2i32_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: scvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = sitofp <2 x i32> %op1 to <2 x half> ret <2 x half> %res } @@ -1394,12 +843,6 @@ define <4 x half> @scvtf_v4i32_v4f16(<4 x i32> %op1) { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v4i32_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: scvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %res = sitofp <4 x i32> %op1 to <4 x half> ret <4 x half> %res } @@ -1417,15 +860,6 @@ define <8 x half> @scvtf_v8i32_v8f16(ptr %a) { ; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v8i32_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: scvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: scvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v0.8h, v1.4s -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %res = sitofp <8 x i32> %op1 to <8 x half> ret <8 x half> %res @@ -1443,11 +877,6 @@ define <2 x float> @scvtf_v2i32_v2f32(<2 x i32> %op1) { ; CHECK-NEXT: scvtf z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v2i32_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: scvtf v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %res = sitofp <2 x i32> %op1 to <2 x float> ret <2 x float> %res } @@ -1460,11 +889,6 @@ define <4 x float> @scvtf_v4i32_v4f32(<4 x i32> %op1) { ; CHECK-NEXT: scvtf z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v4i32_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: scvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %res = sitofp <4 x i32> %op1 to <4 x float> ret <4 x float> %res } @@ -1478,14 +902,6 @@ define void @scvtf_v8i32_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: scvtf z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v8i32_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: scvtf v0.4s, v0.4s -; NONEON-NOSVE-NEXT: scvtf v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %res = sitofp <8 x i32> %op1 to <8 x float> store <8 x float> %res, ptr %b @@ -1505,12 +921,6 @@ define <2 x double> @scvtf_v2i32_v2f64(<2 x i32> %op1) { ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v2i32_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = sitofp <2 x i32> %op1 to <2 x double> ret <2 x double> %res } @@ -1527,20 +937,6 @@ define void @scvtf_v4i32_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v4i32_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: scvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i32>, ptr %a %res = sitofp <4 x i32> %op1 to <4 x double> store <4 x double> %res, ptr %b @@ -1565,26 +961,6 @@ define void @scvtf_v8i32_v8f64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: stp q3, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v8i32_v8f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-32]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 -; NONEON-NOSVE-NEXT: ldr d2, [sp, #24] -; NONEON-NOSVE-NEXT: ldr d3, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: sshll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: sshll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: scvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: scvtf v2.2d, v2.2d -; NONEON-NOSVE-NEXT: scvtf v3.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add sp, sp, #32 -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %res = sitofp <8 x i32> %op1 to <8 x double> store <8 x double> %res, ptr %b @@ -1629,40 +1005,6 @@ define void @scvtf_v16i32_v16f64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q2, q1, [x1] ; CHECK-NEXT: stp q4, q0, [x1, #32] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v16i32_v16f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0, #32] -; NONEON-NOSVE-NEXT: stp q0, q2, [sp, #-64]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64 -; NONEON-NOSVE-NEXT: stp q1, q3, [sp, #32] -; NONEON-NOSVE-NEXT: ldr d4, [sp, #24] -; NONEON-NOSVE-NEXT: sshll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: ldr d5, [sp, #56] -; NONEON-NOSVE-NEXT: sshll v3.2d, v3.2s, #0 -; NONEON-NOSVE-NEXT: ldr d6, [sp, #40] -; NONEON-NOSVE-NEXT: sshll v4.2d, v4.2s, #0 -; NONEON-NOSVE-NEXT: ldr d7, [sp, #8] -; NONEON-NOSVE-NEXT: sshll v1.2d, v1.2s, #0 -; NONEON-NOSVE-NEXT: sshll v5.2d, v5.2s, #0 -; NONEON-NOSVE-NEXT: scvtf v2.2d, v2.2d -; NONEON-NOSVE-NEXT: sshll v6.2d, v6.2s, #0 -; NONEON-NOSVE-NEXT: scvtf v3.2d, v3.2d -; NONEON-NOSVE-NEXT: sshll v0.2d, v0.2s, #0 -; NONEON-NOSVE-NEXT: sshll v7.2d, v7.2s, #0 -; NONEON-NOSVE-NEXT: scvtf v4.2d, v4.2d -; NONEON-NOSVE-NEXT: scvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: scvtf v5.2d, v5.2d -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: stp q2, q4, [x1, #96] -; NONEON-NOSVE-NEXT: scvtf v2.2d, v6.2d -; NONEON-NOSVE-NEXT: stp q3, q5, [x1, #64] -; NONEON-NOSVE-NEXT: scvtf v3.2d, v7.2d -; NONEON-NOSVE-NEXT: stp q1, q2, [x1, #32] -; NONEON-NOSVE-NEXT: stp q0, q3, [x1] -; NONEON-NOSVE-NEXT: add sp, sp, #64 -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i32>, ptr %a %res = sitofp <16 x i32> %op1 to <16 x double> store <16 x double> %res, ptr %b @@ -1689,18 +1031,6 @@ define <2 x half> @scvtf_v2i64_v2f16(<2 x i64> %op1) { ; CHECK-NEXT: ldr d0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v2i64_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov x8, v0.d[1] -; NONEON-NOSVE-NEXT: fmov x9, d0 -; NONEON-NOSVE-NEXT: scvtf s1, x9 -; NONEON-NOSVE-NEXT: scvtf s0, x8 -; NONEON-NOSVE-NEXT: fcvt h2, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s1 -; NONEON-NOSVE-NEXT: mov v0.h[1], v2.h[0] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %res = sitofp <2 x i64> %op1 to <2 x half> ret <2 x half> %res } @@ -1721,16 +1051,6 @@ define <4 x half> @scvtf_v4i64_v4f16(ptr %a) { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v4i64_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: scvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: fcvtn2 v0.4s, v1.2d -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %res = sitofp <4 x i64> %op1 to <4 x half> ret <4 x half> %res @@ -1749,12 +1069,6 @@ define <2 x float> @scvtf_v2i64_v2f32(<2 x i64> %op1) { ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v2i64_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: fcvtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: ret %res = sitofp <2 x i64> %op1 to <2 x float> ret <2 x float> %res } @@ -1772,15 +1086,6 @@ define <4 x float> @scvtf_v4i64_v4f32(ptr %a) { ; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v4i64_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: scvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: fcvtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: fcvtn2 v0.4s, v1.2d -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %res = sitofp <4 x i64> %op1 to <4 x float> ret <4 x float> %res @@ -1798,11 +1103,6 @@ define <2 x double> @scvtf_v2i64_v2f64(<2 x i64> %op1) { ; CHECK-NEXT: scvtf z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v2i64_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: ret %res = sitofp <2 x i64> %op1 to <2 x double> ret <2 x double> %res } @@ -1816,14 +1116,6 @@ define void @scvtf_v4i64_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: scvtf z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_v4i64_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: scvtf v0.2d, v0.2d -; NONEON-NOSVE-NEXT: scvtf v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %res = sitofp <4 x i64> %op1 to <4 x double> store <4 x double> %res, ptr %b @@ -1836,13 +1128,6 @@ define half @scvtf_i16_f16(ptr %0) { ; CHECK-NEXT: ldrsh w8, [x0] ; CHECK-NEXT: scvtf h0, w8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_i16_f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldrsh w8, [x0] -; NONEON-NOSVE-NEXT: scvtf s0, w8 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %2 = load i16, ptr %0, align 64 %3 = sitofp i16 %2 to half ret half %3 @@ -1854,12 +1139,6 @@ define float @scvtf_i16_f32(ptr %0) { ; CHECK-NEXT: ldrsh w8, [x0] ; CHECK-NEXT: scvtf s0, w8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_i16_f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldrsh w8, [x0] -; NONEON-NOSVE-NEXT: scvtf s0, w8 -; NONEON-NOSVE-NEXT: ret %2 = load i16, ptr %0, align 64 %3 = sitofp i16 %2 to float ret float %3 @@ -1871,12 +1150,6 @@ define double @scvtf_i16_f64(ptr %0) { ; CHECK-NEXT: ldrsh w8, [x0] ; CHECK-NEXT: scvtf d0, w8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_i16_f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldrsh w8, [x0] -; NONEON-NOSVE-NEXT: scvtf d0, w8 -; NONEON-NOSVE-NEXT: ret %2 = load i16, ptr %0, align 64 %3 = sitofp i16 %2 to double ret double %3 @@ -1888,13 +1161,6 @@ define half @scvtf_i32_f16(ptr %0) { ; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: scvtf h0, w8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_i32_f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr w8, [x0] -; NONEON-NOSVE-NEXT: scvtf s0, w8 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %2 = load i32, ptr %0, align 64 %3 = sitofp i32 %2 to half ret half %3 @@ -1906,12 +1172,6 @@ define float @scvtf_i32_f32(ptr %0) { ; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: scvtf s0, w8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_i32_f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr w8, [x0] -; NONEON-NOSVE-NEXT: scvtf s0, w8 -; NONEON-NOSVE-NEXT: ret %2 = load i32, ptr %0, align 64 %3 = sitofp i32 %2 to float ret float %3 @@ -1923,12 +1183,6 @@ define double @scvtf_i32_f64(ptr %0) { ; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: scvtf d0, w8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_i32_f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr w8, [x0] -; NONEON-NOSVE-NEXT: scvtf d0, w8 -; NONEON-NOSVE-NEXT: ret %2 = load i32, ptr %0, align 64 %3 = sitofp i32 %2 to double ret double %3 @@ -1940,13 +1194,6 @@ define half @scvtf_i64_f16(ptr %0) { ; CHECK-NEXT: ldr x8, [x0] ; CHECK-NEXT: scvtf h0, x8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_i64_f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr x8, [x0] -; NONEON-NOSVE-NEXT: scvtf s0, x8 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %2 = load i64, ptr %0, align 64 %3 = sitofp i64 %2 to half ret half %3 @@ -1958,12 +1205,6 @@ define float @scvtf_i64_f32(ptr %0) { ; CHECK-NEXT: ldr x8, [x0] ; CHECK-NEXT: scvtf s0, x8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_i64_f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr x8, [x0] -; NONEON-NOSVE-NEXT: scvtf s0, x8 -; NONEON-NOSVE-NEXT: ret %2 = load i64, ptr %0, align 64 %3 = sitofp i64 %2 to float ret float %3 @@ -1975,12 +1216,6 @@ define double @scvtf_i64_f64(ptr %0) { ; CHECK-NEXT: ldr x8, [x0] ; CHECK-NEXT: scvtf d0, x8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: scvtf_i64_f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr x8, [x0] -; NONEON-NOSVE-NEXT: scvtf d0, x8 -; NONEON-NOSVE-NEXT: ret %2 = load i64, ptr %0, align 64 %3 = sitofp i64 %2 to double ret double %3 @@ -1992,13 +1227,6 @@ define half @ucvtf_i16_f16(ptr %0) { ; CHECK-NEXT: ldrh w8, [x0] ; CHECK-NEXT: ucvtf h0, w8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_i16_f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr h0, [x0] -; NONEON-NOSVE-NEXT: ucvtf s0, s0 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %2 = load i16, ptr %0, align 64 %3 = uitofp i16 %2 to half ret half %3 @@ -2010,12 +1238,6 @@ define float @ucvtf_i16_f32(ptr %0) { ; CHECK-NEXT: ldr h0, [x0] ; CHECK-NEXT: ucvtf s0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_i16_f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr h0, [x0] -; NONEON-NOSVE-NEXT: ucvtf s0, s0 -; NONEON-NOSVE-NEXT: ret %2 = load i16, ptr %0, align 64 %3 = uitofp i16 %2 to float ret float %3 @@ -2027,12 +1249,6 @@ define double @ucvtf_i16_f64(ptr %0) { ; CHECK-NEXT: ldr h0, [x0] ; CHECK-NEXT: ucvtf d0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_i16_f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr h0, [x0] -; NONEON-NOSVE-NEXT: ucvtf d0, d0 -; NONEON-NOSVE-NEXT: ret %2 = load i16, ptr %0, align 64 %3 = uitofp i16 %2 to double ret double %3 @@ -2044,13 +1260,6 @@ define half @ucvtf_i32_f16(ptr %0) { ; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: ucvtf h0, w8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_i32_f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr w8, [x0] -; NONEON-NOSVE-NEXT: ucvtf s0, w8 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %2 = load i32, ptr %0, align 64 %3 = uitofp i32 %2 to half ret half %3 @@ -2062,12 +1271,6 @@ define float @ucvtf_i32_f32(ptr %0) { ; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: ucvtf s0, w8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_i32_f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr w8, [x0] -; NONEON-NOSVE-NEXT: ucvtf s0, w8 -; NONEON-NOSVE-NEXT: ret %2 = load i32, ptr %0, align 64 %3 = uitofp i32 %2 to float ret float %3 @@ -2079,12 +1282,6 @@ define double @ucvtf_i32_f64(ptr %0) { ; CHECK-NEXT: ldr s0, [x0] ; CHECK-NEXT: ucvtf d0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_i32_f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr s0, [x0] -; NONEON-NOSVE-NEXT: ucvtf d0, d0 -; NONEON-NOSVE-NEXT: ret %2 = load i32, ptr %0, align 64 %3 = uitofp i32 %2 to double ret double %3 @@ -2096,13 +1293,6 @@ define half @ucvtf_i64_f16(ptr %0) { ; CHECK-NEXT: ldr x8, [x0] ; CHECK-NEXT: ucvtf h0, x8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_i64_f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr x8, [x0] -; NONEON-NOSVE-NEXT: ucvtf s0, x8 -; NONEON-NOSVE-NEXT: fcvt h0, s0 -; NONEON-NOSVE-NEXT: ret %2 = load i64, ptr %0, align 64 %3 = uitofp i64 %2 to half ret half %3 @@ -2114,12 +1304,6 @@ define float @ucvtf_i64_f32(ptr %0) { ; CHECK-NEXT: ldr x8, [x0] ; CHECK-NEXT: ucvtf s0, x8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_i64_f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr x8, [x0] -; NONEON-NOSVE-NEXT: ucvtf s0, x8 -; NONEON-NOSVE-NEXT: ret %2 = load i64, ptr %0, align 64 %3 = uitofp i64 %2 to float ret float %3 @@ -2131,12 +1315,6 @@ define double @ucvtf_i64_f64(ptr %0) { ; CHECK-NEXT: ldr x8, [x0] ; CHECK-NEXT: ucvtf d0, x8 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ucvtf_i64_f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr x8, [x0] -; NONEON-NOSVE-NEXT: ucvtf d0, x8 -; NONEON-NOSVE-NEXT: ret %2 = load i64, ptr %0, align 64 %3 = uitofp i64 %2 to double ret double %3 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll index 42daa4fedc94..81bbaa92d4b4 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -19,13 +18,6 @@ define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, <4 x i1> %mask) { ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v2.4h, v2.4h, #15 -; NONEON-NOSVE-NEXT: cmlt v2.4h, v2.4h, #0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select <4 x i1> %mask, <4 x i8> %op1, <4 x i8> %op2 ret <4 x i8> %sel } @@ -44,13 +36,6 @@ define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) { ; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v2.8b, v2.8b, #7 -; NONEON-NOSVE-NEXT: cmlt v2.8b, v2.8b, #0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select <8 x i1> %mask, <8 x i8> %op1, <8 x i8> %op2 ret <8 x i8> %sel } @@ -69,13 +54,6 @@ define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) ; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v2.16b, v2.16b, #7 -; NONEON-NOSVE-NEXT: cmlt v2.16b, v2.16b, #0 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select <16 x i1> %mask, <16 x i8> %op1, <16 x i8> %op2 ret <16 x i8> %sel } @@ -92,18 +70,6 @@ define void @select_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: sel z1.b, p0, z2.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x1] -; NONEON-NOSVE-NEXT: cmeq v4.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: cmeq v5.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v4.16b -; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b -; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %mask = icmp eq <32 x i8> %op1, %op2 @@ -126,13 +92,6 @@ define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) { ; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v2.2s, v2.2s, #31 -; NONEON-NOSVE-NEXT: cmlt v2.2s, v2.2s, #0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select <2 x i1> %mask, <2 x i16> %op1, <2 x i16> %op2 ret <2 x i16> %sel } @@ -151,13 +110,6 @@ define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) { ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v2.4h, v2.4h, #15 -; NONEON-NOSVE-NEXT: cmlt v2.4h, v2.4h, #0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select <4 x i1> %mask, <4 x i16> %op1, <4 x i16> %op2 ret <4 x i16> %sel } @@ -177,14 +129,6 @@ define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) { ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v2.8h, v2.8b, #0 -; NONEON-NOSVE-NEXT: shl v2.8h, v2.8h, #15 -; NONEON-NOSVE-NEXT: cmlt v2.8h, v2.8h, #0 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select <8 x i1> %mask, <8 x i16> %op1, <8 x i16> %op2 ret <8 x i16> %sel } @@ -201,18 +145,6 @@ define void @select_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: sel z1.h, p0, z2.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x1] -; NONEON-NOSVE-NEXT: cmeq v4.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: cmeq v5.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v4.16b -; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b -; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %mask = icmp eq <16 x i16> %op1, %op2 @@ -235,13 +167,6 @@ define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) { ; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v2.2s, v2.2s, #31 -; NONEON-NOSVE-NEXT: cmlt v2.2s, v2.2s, #0 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select <2 x i1> %mask, <2 x i32> %op1, <2 x i32> %op2 ret <2 x i32> %sel } @@ -261,14 +186,6 @@ define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) { ; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NONEON-NOSVE-NEXT: shl v2.4s, v2.4s, #31 -; NONEON-NOSVE-NEXT: cmlt v2.4s, v2.4s, #0 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select <4 x i1> %mask, <4 x i32> %op1, <4 x i32> %op2 ret <4 x i32> %sel } @@ -285,18 +202,6 @@ define void @select_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: sel z1.s, p0, z2.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x1] -; NONEON-NOSVE-NEXT: cmeq v4.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: cmeq v5.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v4.16b -; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b -; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %mask = icmp eq <8 x i32> %op1, %op2 @@ -318,14 +223,6 @@ define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) { ; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: tst w0, #0x1 -; NONEON-NOSVE-NEXT: csetm x8, ne -; NONEON-NOSVE-NEXT: fmov d2, x8 -; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: ret %sel = select <1 x i1> %mask, <1 x i64> %op1, <1 x i64> %op2 ret <1 x i64> %sel } @@ -345,14 +242,6 @@ define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) { ; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ushll v2.2d, v2.2s, #0 -; NONEON-NOSVE-NEXT: shl v2.2d, v2.2d, #63 -; NONEON-NOSVE-NEXT: cmlt v2.2d, v2.2d, #0 -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %sel = select <2 x i1> %mask, <2 x i64> %op1, <2 x i64> %op2 ret <2 x i64> %sel } @@ -369,18 +258,6 @@ define void @select_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: sel z1.d, p0, z2.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: select_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x1] -; NONEON-NOSVE-NEXT: cmeq v4.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: cmeq v5.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v4.16b -; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b -; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %mask = icmp eq <4 x i64> %op1, %op2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll index 01a7a5cafd26..885030861469 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -19,19 +18,6 @@ define <4 x i32> @test(ptr %arg1, ptr %arg2) { ; CHECK-NEXT: stp q2, q5, [x0, #32] ; CHECK-NEXT: stp q1, q3, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test: -; NONEON-NOSVE: // %bb.0: // %entry -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q3, q4, [x0] -; NONEON-NOSVE-NEXT: add v2.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: add v5.4s, v1.4s, v1.4s -; NONEON-NOSVE-NEXT: dup v0.4s, v1.s[2] -; NONEON-NOSVE-NEXT: add v1.4s, v3.4s, v3.4s -; NONEON-NOSVE-NEXT: add v3.4s, v4.4s, v4.4s -; NONEON-NOSVE-NEXT: stp q2, q5, [x0, #32] -; NONEON-NOSVE-NEXT: stp q1, q3, [x0] -; NONEON-NOSVE-NEXT: ret entry: %0 = load <16 x i32>, ptr %arg1, align 256 %1 = load <16 x i32>, ptr %arg2, align 256 @@ -56,19 +42,6 @@ define <2 x i32> @test2(ptr %arg1, ptr %arg2) { ; CHECK-NEXT: stp q3, q4, [x0] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test2: -; NONEON-NOSVE: // %bb.0: // %entry -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q3, q4, [x0] -; NONEON-NOSVE-NEXT: add v2.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: dup v0.2s, v1.s[2] -; NONEON-NOSVE-NEXT: add v1.4s, v1.4s, v1.4s -; NONEON-NOSVE-NEXT: add v3.4s, v3.4s, v3.4s -; NONEON-NOSVE-NEXT: add v4.4s, v4.4s, v4.4s -; NONEON-NOSVE-NEXT: stp q2, q1, [x0, #32] -; NONEON-NOSVE-NEXT: stp q3, q4, [x0] -; NONEON-NOSVE-NEXT: ret entry: %0 = load <16 x i32>, ptr %arg1, align 256 %1 = load <16 x i32>, ptr %arg2, align 256 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll index c57f3af0d4b6..8ca8e6980913 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -12,13 +11,6 @@ define <4 x i8> @load_v4i8(ptr %a) { ; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr s0, [x0] -; NONEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %load = load <4 x i8>, ptr %a ret <4 x i8> %load } @@ -28,11 +20,6 @@ define <8 x i8> @load_v8i8(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <8 x i8>, ptr %a ret <8 x i8> %load } @@ -42,11 +29,6 @@ define <16 x i8> @load_v16i8(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <16 x i8>, ptr %a ret <16 x i8> %load } @@ -56,11 +38,6 @@ define <32 x i8> @load_v32i8(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <32 x i8>, ptr %a ret <32 x i8> %load } @@ -72,15 +49,6 @@ define <2 x i16> @load_v2i16(ptr %a) { ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldrh w8, [x0] -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: add x8, x0, #2 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[2], [x8] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %load = load <2 x i16>, ptr %a ret <2 x i16> %load } @@ -90,11 +58,6 @@ define <2 x half> @load_v2f16(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr s0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr s0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <2 x half>, ptr %a ret <2 x half> %load } @@ -104,11 +67,6 @@ define <4 x i16> @load_v4i16(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <4 x i16>, ptr %a ret <4 x i16> %load } @@ -118,11 +76,6 @@ define <4 x half> @load_v4f16(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <4 x half>, ptr %a ret <4 x half> %load } @@ -132,11 +85,6 @@ define <8 x i16> @load_v8i16(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <8 x i16>, ptr %a ret <8 x i16> %load } @@ -146,11 +94,6 @@ define <8 x half> @load_v8f16(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <8 x half>, ptr %a ret <8 x half> %load } @@ -160,11 +103,6 @@ define <16 x i16> @load_v16i16(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <16 x i16>, ptr %a ret <16 x i16> %load } @@ -174,11 +112,6 @@ define <16 x half> @load_v16f16(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <16 x half>, ptr %a ret <16 x half> %load } @@ -188,11 +121,6 @@ define <2 x i32> @load_v2i32(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <2 x i32>, ptr %a ret <2 x i32> %load } @@ -202,11 +130,6 @@ define <2 x float> @load_v2f32(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <2 x float>, ptr %a ret <2 x float> %load } @@ -216,11 +139,6 @@ define <4 x i32> @load_v4i32(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <4 x i32>, ptr %a ret <4 x i32> %load } @@ -230,11 +148,6 @@ define <4 x float> @load_v4f32(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <4 x float>, ptr %a ret <4 x float> %load } @@ -244,11 +157,6 @@ define <8 x i32> @load_v8i32(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <8 x i32>, ptr %a ret <8 x i32> %load } @@ -258,11 +166,6 @@ define <8 x float> @load_v8f32(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <8 x float>, ptr %a ret <8 x float> %load } @@ -272,11 +175,6 @@ define <1 x i64> @load_v1i64(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <1 x i64>, ptr %a ret <1 x i64> %load } @@ -286,11 +184,6 @@ define <1 x double> @load_v1f64(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <1 x double>, ptr %a ret <1 x double> %load } @@ -300,11 +193,6 @@ define <2 x i64> @load_v2i64(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <2 x i64>, ptr %a ret <2 x i64> %load } @@ -314,11 +202,6 @@ define <2 x double> @load_v2f64(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <2 x double>, ptr %a ret <2 x double> %load } @@ -328,11 +211,6 @@ define <4 x i64> @load_v4i64(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <4 x i64>, ptr %a ret <4 x i64> %load } @@ -342,11 +220,6 @@ define <4 x double> @load_v4f64(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: load_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %load = load <4 x double>, ptr %a ret <4 x double> %load } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll index 65c45587e120..c4aeb4465c53 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -18,14 +17,6 @@ define i8 @andv_v4i8(<4 x i8> %a) { ; CHECK-NEXT: andv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: and x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: lsr x9, x8, #16 -; NONEON-NOSVE-NEXT: and w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %a) ret i8 %res } @@ -38,15 +29,6 @@ define i8 @andv_v8i8(<8 x i8> %a) { ; CHECK-NEXT: andv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: and x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: and x8, x8, x8, lsr #16 -; NONEON-NOSVE-NEXT: lsr x9, x8, #8 -; NONEON-NOSVE-NEXT: and w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %a) ret i8 %res } @@ -59,20 +41,6 @@ define i8 @andv_v16i8(<16 x i8> %a) { ; CHECK-NEXT: andv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: and x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: and x8, x8, x8, lsr #16 -; NONEON-NOSVE-NEXT: lsr x9, x8, #8 -; NONEON-NOSVE-NEXT: and w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %a) ret i8 %res } @@ -86,22 +54,6 @@ define i8 @andv_v32i8(ptr %a) { ; CHECK-NEXT: andv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: and v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: and x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: and x8, x8, x8, lsr #16 -; NONEON-NOSVE-NEXT: lsr x9, x8, #8 -; NONEON-NOSVE-NEXT: and w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %op) ret i8 %res @@ -115,13 +67,6 @@ define i16 @andv_v2i16(<2 x i16> %a) { ; CHECK-NEXT: andv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: lsr x9, x8, #32 -; NONEON-NOSVE-NEXT: and w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> %a) ret i16 %res } @@ -134,14 +79,6 @@ define i16 @andv_v4i16(<4 x i16> %a) { ; CHECK-NEXT: andv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: and x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: lsr x9, x8, #16 -; NONEON-NOSVE-NEXT: and w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %a) ret i16 %res } @@ -154,19 +91,6 @@ define i16 @andv_v8i16(<8 x i16> %a) { ; CHECK-NEXT: andv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: and x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: lsr x9, x8, #16 -; NONEON-NOSVE-NEXT: and w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %a) ret i16 %res } @@ -180,21 +104,6 @@ define i16 @andv_v16i16(ptr %a) { ; CHECK-NEXT: andv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: and v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: and x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: lsr x9, x8, #16 -; NONEON-NOSVE-NEXT: and w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %op) ret i16 %res @@ -208,13 +117,6 @@ define i32 @andv_v2i32(<2 x i32> %a) { ; CHECK-NEXT: andv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: lsr x9, x8, #32 -; NONEON-NOSVE-NEXT: and w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %a) ret i32 %res } @@ -227,18 +129,6 @@ define i32 @andv_v4i32(<4 x i32> %a) { ; CHECK-NEXT: andv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: lsr x9, x8, #32 -; NONEON-NOSVE-NEXT: and w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a) ret i32 %res } @@ -252,20 +142,6 @@ define i32 @andv_v8i32(ptr %a) { ; CHECK-NEXT: andv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: and v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: lsr x9, x8, #32 -; NONEON-NOSVE-NEXT: and w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %op) ret i32 %res @@ -279,16 +155,6 @@ define i64 @andv_v2i64(<2 x i64> %a) { ; CHECK-NEXT: andv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %a) ret i64 %res } @@ -302,18 +168,6 @@ define i64 @andv_v4i64(ptr %a) { ; CHECK-NEXT: andv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: andv_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: and v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %op) ret i64 %res @@ -331,14 +185,6 @@ define i8 @eorv_v4i8(<4 x i8> %a) { ; CHECK-NEXT: eorv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: eor x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: lsr x9, x8, #16 -; NONEON-NOSVE-NEXT: eor w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %a) ret i8 %res } @@ -351,15 +197,6 @@ define i8 @eorv_v8i8(<8 x i8> %a) { ; CHECK-NEXT: eorv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: eor x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: eor x8, x8, x8, lsr #16 -; NONEON-NOSVE-NEXT: lsr x9, x8, #8 -; NONEON-NOSVE-NEXT: eor w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %a) ret i8 %res } @@ -372,20 +209,6 @@ define i8 @eorv_v16i8(<16 x i8> %a) { ; CHECK-NEXT: eorv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: eor x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: eor x8, x8, x8, lsr #16 -; NONEON-NOSVE-NEXT: lsr x9, x8, #8 -; NONEON-NOSVE-NEXT: eor w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %a) ret i8 %res } @@ -399,22 +222,6 @@ define i8 @eorv_v32i8(ptr %a) { ; CHECK-NEXT: eorv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: eor v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: eor x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: eor x8, x8, x8, lsr #16 -; NONEON-NOSVE-NEXT: lsr x9, x8, #8 -; NONEON-NOSVE-NEXT: eor w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %op) ret i8 %res @@ -428,13 +235,6 @@ define i16 @eorv_v2i16(<2 x i16> %a) { ; CHECK-NEXT: eorv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: lsr x9, x8, #32 -; NONEON-NOSVE-NEXT: eor w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> %a) ret i16 %res } @@ -447,14 +247,6 @@ define i16 @eorv_v4i16(<4 x i16> %a) { ; CHECK-NEXT: eorv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: eor x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: lsr x9, x8, #16 -; NONEON-NOSVE-NEXT: eor w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %a) ret i16 %res } @@ -467,19 +259,6 @@ define i16 @eorv_v8i16(<8 x i16> %a) { ; CHECK-NEXT: eorv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: eor x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: lsr x9, x8, #16 -; NONEON-NOSVE-NEXT: eor w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %a) ret i16 %res } @@ -493,21 +272,6 @@ define i16 @eorv_v16i16(ptr %a) { ; CHECK-NEXT: eorv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: eor v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: eor x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: lsr x9, x8, #16 -; NONEON-NOSVE-NEXT: eor w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %op) ret i16 %res @@ -521,13 +285,6 @@ define i32 @eorv_v2i32(<2 x i32> %a) { ; CHECK-NEXT: eorv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: lsr x9, x8, #32 -; NONEON-NOSVE-NEXT: eor w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %a) ret i32 %res } @@ -540,18 +297,6 @@ define i32 @eorv_v4i32(<4 x i32> %a) { ; CHECK-NEXT: eorv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: lsr x9, x8, #32 -; NONEON-NOSVE-NEXT: eor w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a) ret i32 %res } @@ -565,20 +310,6 @@ define i32 @eorv_v8i32(ptr %a) { ; CHECK-NEXT: eorv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: eor v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: lsr x9, x8, #32 -; NONEON-NOSVE-NEXT: eor w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %op) ret i32 %res @@ -592,16 +323,6 @@ define i64 @eorv_v2i64(<2 x i64> %a) { ; CHECK-NEXT: eorv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %a) ret i64 %res } @@ -615,18 +336,6 @@ define i64 @eorv_v4i64(ptr %a) { ; CHECK-NEXT: eorv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: eorv_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: eor v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: eor v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %op) ret i64 %res @@ -644,14 +353,6 @@ define i8 @orv_v4i8(<4 x i8> %a) { ; CHECK-NEXT: orv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: orr x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: lsr x9, x8, #16 -; NONEON-NOSVE-NEXT: orr w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %a) ret i8 %res } @@ -664,15 +365,6 @@ define i8 @orv_v8i8(<8 x i8> %a) { ; CHECK-NEXT: orv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: orr x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: orr x8, x8, x8, lsr #16 -; NONEON-NOSVE-NEXT: lsr x9, x8, #8 -; NONEON-NOSVE-NEXT: orr w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %a) ret i8 %res } @@ -685,20 +377,6 @@ define i8 @orv_v16i8(<16 x i8> %a) { ; CHECK-NEXT: orv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: orr x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: orr x8, x8, x8, lsr #16 -; NONEON-NOSVE-NEXT: lsr x9, x8, #8 -; NONEON-NOSVE-NEXT: orr w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %a) ret i8 %res } @@ -712,22 +390,6 @@ define i8 @orv_v32i8(ptr %a) { ; CHECK-NEXT: orv b0, p0, z0.b ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: orr v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: orr x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: orr x8, x8, x8, lsr #16 -; NONEON-NOSVE-NEXT: lsr x9, x8, #8 -; NONEON-NOSVE-NEXT: orr w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %res = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %op) ret i8 %res @@ -741,13 +403,6 @@ define i16 @orv_v2i16(<2 x i16> %a) { ; CHECK-NEXT: orv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: lsr x9, x8, #32 -; NONEON-NOSVE-NEXT: orr w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> %a) ret i16 %res } @@ -760,14 +415,6 @@ define i16 @orv_v4i16(<4 x i16> %a) { ; CHECK-NEXT: orv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: orr x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: lsr x9, x8, #16 -; NONEON-NOSVE-NEXT: orr w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %a) ret i16 %res } @@ -780,19 +427,6 @@ define i16 @orv_v8i16(<8 x i16> %a) { ; CHECK-NEXT: orv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: orr x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: lsr x9, x8, #16 -; NONEON-NOSVE-NEXT: orr w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %a) ret i16 %res } @@ -806,21 +440,6 @@ define i16 @orv_v16i16(ptr %a) { ; CHECK-NEXT: orv h0, p0, z0.h ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: orr v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: orr x8, x8, x8, lsr #32 -; NONEON-NOSVE-NEXT: lsr x9, x8, #16 -; NONEON-NOSVE-NEXT: orr w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %op) ret i16 %res @@ -834,13 +453,6 @@ define i32 @orv_v2i32(<2 x i32> %a) { ; CHECK-NEXT: orv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: lsr x9, x8, #32 -; NONEON-NOSVE-NEXT: orr w0, w8, w9 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %a) ret i32 %res } @@ -853,18 +465,6 @@ define i32 @orv_v4i32(<4 x i32> %a) { ; CHECK-NEXT: orv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: lsr x9, x8, #32 -; NONEON-NOSVE-NEXT: orr w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a) ret i32 %res } @@ -878,20 +478,6 @@ define i32 @orv_v8i32(ptr %a) { ; CHECK-NEXT: orv s0, p0, z0.s ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: orr v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x8, d0 -; NONEON-NOSVE-NEXT: lsr x9, x8, #32 -; NONEON-NOSVE-NEXT: orr w0, w8, w9 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %op) ret i32 %res @@ -905,16 +491,6 @@ define i64 @orv_v2i64(<2 x i64> %a) { ; CHECK-NEXT: orv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %res = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %a) ret i64 %res } @@ -928,18 +504,6 @@ define i64 @orv_v4i64(ptr %a) { ; CHECK-NEXT: orv d0, p0, z0.d ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: orv_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: orr v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: str q0, [sp, #-16]! -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: ldr d1, [sp, #8] -; NONEON-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: fmov x0, d0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %op) ret i64 %res diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll index 886f97ed988d..ca58099244cf 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -20,44 +19,6 @@ define <4 x i8> @masked_load_v4i8(ptr %src, <4 x i1> %mask) { ; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #15 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI0_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI0_0] -; NONEON-NOSVE-NEXT: cmlt v0.4h, v0.4h, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addv h0, v0.4h -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbz w8, #0, .LBB0_2 -; NONEON-NOSVE-NEXT: // %bb.1: // %cond.load -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[0], [x0] -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB0_3 -; NONEON-NOSVE-NEXT: b .LBB0_4 -; NONEON-NOSVE-NEXT: .LBB0_2: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB0_4 -; NONEON-NOSVE-NEXT: .LBB0_3: // %cond.load1 -; NONEON-NOSVE-NEXT: add x9, x0, #1 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[2], [x9] -; NONEON-NOSVE-NEXT: .LBB0_4: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB0_7 -; NONEON-NOSVE-NEXT: // %bb.5: // %else5 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB0_8 -; NONEON-NOSVE-NEXT: .LBB0_6: // %else8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB0_7: // %cond.load4 -; NONEON-NOSVE-NEXT: add x9, x0, #2 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[4], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB0_6 -; NONEON-NOSVE-NEXT: .LBB0_8: // %cond.load7 -; NONEON-NOSVE-NEXT: add x8, x0, #3 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[6], [x8] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %load = call <4 x i8> @llvm.masked.load.v4i8(ptr %src, i32 8, <4 x i1> %mask, <4 x i8> zeroinitializer) ret <4 x i8> %load } @@ -73,67 +34,6 @@ define <8 x i8> @masked_load_v8i8(ptr %src, <8 x i1> %mask) { ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.8b, v0.8b, #7 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI1_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI1_0] -; NONEON-NOSVE-NEXT: cmlt v0.8b, v0.8b, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addv b0, v0.8b -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbz w8, #0, .LBB1_2 -; NONEON-NOSVE-NEXT: // %bb.1: // %cond.load -; NONEON-NOSVE-NEXT: ldr b0, [x0] -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB1_3 -; NONEON-NOSVE-NEXT: b .LBB1_4 -; NONEON-NOSVE-NEXT: .LBB1_2: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB1_4 -; NONEON-NOSVE-NEXT: .LBB1_3: // %cond.load1 -; NONEON-NOSVE-NEXT: add x9, x0, #1 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[1], [x9] -; NONEON-NOSVE-NEXT: .LBB1_4: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB1_11 -; NONEON-NOSVE-NEXT: // %bb.5: // %else5 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB1_12 -; NONEON-NOSVE-NEXT: .LBB1_6: // %else8 -; NONEON-NOSVE-NEXT: tbnz w8, #4, .LBB1_13 -; NONEON-NOSVE-NEXT: .LBB1_7: // %else11 -; NONEON-NOSVE-NEXT: tbnz w8, #5, .LBB1_14 -; NONEON-NOSVE-NEXT: .LBB1_8: // %else14 -; NONEON-NOSVE-NEXT: tbnz w8, #6, .LBB1_15 -; NONEON-NOSVE-NEXT: .LBB1_9: // %else17 -; NONEON-NOSVE-NEXT: tbnz w8, #7, .LBB1_16 -; NONEON-NOSVE-NEXT: .LBB1_10: // %else20 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB1_11: // %cond.load4 -; NONEON-NOSVE-NEXT: add x9, x0, #2 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[2], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB1_6 -; NONEON-NOSVE-NEXT: .LBB1_12: // %cond.load7 -; NONEON-NOSVE-NEXT: add x9, x0, #3 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[3], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #4, .LBB1_7 -; NONEON-NOSVE-NEXT: .LBB1_13: // %cond.load10 -; NONEON-NOSVE-NEXT: add x9, x0, #4 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[4], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #5, .LBB1_8 -; NONEON-NOSVE-NEXT: .LBB1_14: // %cond.load13 -; NONEON-NOSVE-NEXT: add x9, x0, #5 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[5], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #6, .LBB1_9 -; NONEON-NOSVE-NEXT: .LBB1_15: // %cond.load16 -; NONEON-NOSVE-NEXT: add x9, x0, #6 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[6], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #7, .LBB1_10 -; NONEON-NOSVE-NEXT: .LBB1_16: // %cond.load19 -; NONEON-NOSVE-NEXT: add x8, x0, #7 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[7], [x8] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %load = call <8 x i8> @llvm.masked.load.v8i8(ptr %src, i32 8, <8 x i1> %mask, <8 x i8> zeroinitializer) ret <8 x i8> %load } @@ -149,115 +49,6 @@ define <16 x i8> @masked_load_v16i8(ptr %src, <16 x i1> %mask) { ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0] ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.16b, v0.16b, #7 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI2_0 -; NONEON-NOSVE-NEXT: ldr q1, [x8, :lo12:.LCPI2_0] -; NONEON-NOSVE-NEXT: cmlt v0.16b, v0.16b, #0 -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; NONEON-NOSVE-NEXT: zip1 v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: addv h1, v0.8h -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB2_17 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB2_18 -; NONEON-NOSVE-NEXT: .LBB2_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB2_19 -; NONEON-NOSVE-NEXT: .LBB2_3: // %else5 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB2_20 -; NONEON-NOSVE-NEXT: .LBB2_4: // %else8 -; NONEON-NOSVE-NEXT: tbnz w8, #4, .LBB2_21 -; NONEON-NOSVE-NEXT: .LBB2_5: // %else11 -; NONEON-NOSVE-NEXT: tbnz w8, #5, .LBB2_22 -; NONEON-NOSVE-NEXT: .LBB2_6: // %else14 -; NONEON-NOSVE-NEXT: tbnz w8, #6, .LBB2_23 -; NONEON-NOSVE-NEXT: .LBB2_7: // %else17 -; NONEON-NOSVE-NEXT: tbnz w8, #7, .LBB2_24 -; NONEON-NOSVE-NEXT: .LBB2_8: // %else20 -; NONEON-NOSVE-NEXT: tbnz w8, #8, .LBB2_25 -; NONEON-NOSVE-NEXT: .LBB2_9: // %else23 -; NONEON-NOSVE-NEXT: tbnz w8, #9, .LBB2_26 -; NONEON-NOSVE-NEXT: .LBB2_10: // %else26 -; NONEON-NOSVE-NEXT: tbnz w8, #10, .LBB2_27 -; NONEON-NOSVE-NEXT: .LBB2_11: // %else29 -; NONEON-NOSVE-NEXT: tbnz w8, #11, .LBB2_28 -; NONEON-NOSVE-NEXT: .LBB2_12: // %else32 -; NONEON-NOSVE-NEXT: tbnz w8, #12, .LBB2_29 -; NONEON-NOSVE-NEXT: .LBB2_13: // %else35 -; NONEON-NOSVE-NEXT: tbnz w8, #13, .LBB2_30 -; NONEON-NOSVE-NEXT: .LBB2_14: // %else38 -; NONEON-NOSVE-NEXT: tbnz w8, #14, .LBB2_31 -; NONEON-NOSVE-NEXT: .LBB2_15: // %else41 -; NONEON-NOSVE-NEXT: tbnz w8, #15, .LBB2_32 -; NONEON-NOSVE-NEXT: .LBB2_16: // %else44 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB2_17: // %cond.load -; NONEON-NOSVE-NEXT: ldr b0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB2_2 -; NONEON-NOSVE-NEXT: .LBB2_18: // %cond.load1 -; NONEON-NOSVE-NEXT: add x9, x0, #1 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[1], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB2_3 -; NONEON-NOSVE-NEXT: .LBB2_19: // %cond.load4 -; NONEON-NOSVE-NEXT: add x9, x0, #2 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[2], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB2_4 -; NONEON-NOSVE-NEXT: .LBB2_20: // %cond.load7 -; NONEON-NOSVE-NEXT: add x9, x0, #3 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[3], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #4, .LBB2_5 -; NONEON-NOSVE-NEXT: .LBB2_21: // %cond.load10 -; NONEON-NOSVE-NEXT: add x9, x0, #4 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[4], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #5, .LBB2_6 -; NONEON-NOSVE-NEXT: .LBB2_22: // %cond.load13 -; NONEON-NOSVE-NEXT: add x9, x0, #5 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[5], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #6, .LBB2_7 -; NONEON-NOSVE-NEXT: .LBB2_23: // %cond.load16 -; NONEON-NOSVE-NEXT: add x9, x0, #6 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[6], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #7, .LBB2_8 -; NONEON-NOSVE-NEXT: .LBB2_24: // %cond.load19 -; NONEON-NOSVE-NEXT: add x9, x0, #7 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[7], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #8, .LBB2_9 -; NONEON-NOSVE-NEXT: .LBB2_25: // %cond.load22 -; NONEON-NOSVE-NEXT: add x9, x0, #8 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[8], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #9, .LBB2_10 -; NONEON-NOSVE-NEXT: .LBB2_26: // %cond.load25 -; NONEON-NOSVE-NEXT: add x9, x0, #9 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[9], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #10, .LBB2_11 -; NONEON-NOSVE-NEXT: .LBB2_27: // %cond.load28 -; NONEON-NOSVE-NEXT: add x9, x0, #10 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[10], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #11, .LBB2_12 -; NONEON-NOSVE-NEXT: .LBB2_28: // %cond.load31 -; NONEON-NOSVE-NEXT: add x9, x0, #11 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[11], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #12, .LBB2_13 -; NONEON-NOSVE-NEXT: .LBB2_29: // %cond.load34 -; NONEON-NOSVE-NEXT: add x9, x0, #12 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[12], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #13, .LBB2_14 -; NONEON-NOSVE-NEXT: .LBB2_30: // %cond.load37 -; NONEON-NOSVE-NEXT: add x9, x0, #13 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[13], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #14, .LBB2_15 -; NONEON-NOSVE-NEXT: .LBB2_31: // %cond.load40 -; NONEON-NOSVE-NEXT: add x9, x0, #14 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[14], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #15, .LBB2_16 -; NONEON-NOSVE-NEXT: .LBB2_32: // %cond.load43 -; NONEON-NOSVE-NEXT: add x8, x0, #15 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[15], [x8] -; NONEON-NOSVE-NEXT: ret %load = call <16 x i8> @llvm.masked.load.v16i8(ptr %src, i32 8, <16 x i1> %mask, <16 x i8> zeroinitializer) ret <16 x i8> %load } @@ -339,277 +130,6 @@ define <32 x i8> @masked_load_v32i8(ptr %src, <32 x i1> %mask) { ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr w8, [sp, #72] -; NONEON-NOSVE-NEXT: fmov s1, w1 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #80] -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #88] -; NONEON-NOSVE-NEXT: mov v1.b[1], w2 -; NONEON-NOSVE-NEXT: mov v0.b[1], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp] -; NONEON-NOSVE-NEXT: mov v1.b[2], w3 -; NONEON-NOSVE-NEXT: mov v0.b[2], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #96] -; NONEON-NOSVE-NEXT: mov v1.b[3], w4 -; NONEON-NOSVE-NEXT: mov v0.b[3], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #104] -; NONEON-NOSVE-NEXT: mov v1.b[4], w5 -; NONEON-NOSVE-NEXT: mov v0.b[4], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #112] -; NONEON-NOSVE-NEXT: mov v1.b[5], w6 -; NONEON-NOSVE-NEXT: mov v0.b[5], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #120] -; NONEON-NOSVE-NEXT: mov v1.b[6], w7 -; NONEON-NOSVE-NEXT: mov v0.b[6], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #128] -; NONEON-NOSVE-NEXT: mov v1.b[7], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #8] -; NONEON-NOSVE-NEXT: mov v0.b[7], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #136] -; NONEON-NOSVE-NEXT: mov v1.b[8], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #16] -; NONEON-NOSVE-NEXT: mov v0.b[8], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #144] -; NONEON-NOSVE-NEXT: mov v1.b[9], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #24] -; NONEON-NOSVE-NEXT: mov v0.b[9], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #152] -; NONEON-NOSVE-NEXT: mov v1.b[10], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #32] -; NONEON-NOSVE-NEXT: mov v0.b[10], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #160] -; NONEON-NOSVE-NEXT: mov v1.b[11], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #40] -; NONEON-NOSVE-NEXT: mov v0.b[11], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #168] -; NONEON-NOSVE-NEXT: mov v1.b[12], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #48] -; NONEON-NOSVE-NEXT: mov v0.b[12], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #176] -; NONEON-NOSVE-NEXT: mov v1.b[13], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #56] -; NONEON-NOSVE-NEXT: mov v0.b[13], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #184] -; NONEON-NOSVE-NEXT: mov v1.b[14], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #64] -; NONEON-NOSVE-NEXT: mov v0.b[14], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #192] -; NONEON-NOSVE-NEXT: mov v1.b[15], w9 -; NONEON-NOSVE-NEXT: mov v0.b[15], w8 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI3_0 -; NONEON-NOSVE-NEXT: ldr q2, [x8, :lo12:.LCPI3_0] -; NONEON-NOSVE-NEXT: shl v1.16b, v1.16b, #7 -; NONEON-NOSVE-NEXT: shl v0.16b, v0.16b, #7 -; NONEON-NOSVE-NEXT: cmlt v1.16b, v1.16b, #0 -; NONEON-NOSVE-NEXT: cmlt v0.16b, v0.16b, #0 -; NONEON-NOSVE-NEXT: and v1.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ext v3.16b, v1.16b, v1.16b, #8 -; NONEON-NOSVE-NEXT: ext v2.16b, v0.16b, v0.16b, #8 -; NONEON-NOSVE-NEXT: zip1 v1.16b, v1.16b, v3.16b -; NONEON-NOSVE-NEXT: zip1 v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: addv h1, v1.8h -; NONEON-NOSVE-NEXT: addv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: movi v1.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: fmov w9, s0 -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: bfi w8, w9, #16, #16 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB3_33 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB3_34 -; NONEON-NOSVE-NEXT: .LBB3_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB3_35 -; NONEON-NOSVE-NEXT: .LBB3_3: // %else5 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB3_36 -; NONEON-NOSVE-NEXT: .LBB3_4: // %else8 -; NONEON-NOSVE-NEXT: tbnz w8, #4, .LBB3_37 -; NONEON-NOSVE-NEXT: .LBB3_5: // %else11 -; NONEON-NOSVE-NEXT: tbnz w8, #5, .LBB3_38 -; NONEON-NOSVE-NEXT: .LBB3_6: // %else14 -; NONEON-NOSVE-NEXT: tbnz w8, #6, .LBB3_39 -; NONEON-NOSVE-NEXT: .LBB3_7: // %else17 -; NONEON-NOSVE-NEXT: tbnz w8, #7, .LBB3_40 -; NONEON-NOSVE-NEXT: .LBB3_8: // %else20 -; NONEON-NOSVE-NEXT: tbnz w8, #8, .LBB3_41 -; NONEON-NOSVE-NEXT: .LBB3_9: // %else23 -; NONEON-NOSVE-NEXT: tbnz w8, #9, .LBB3_42 -; NONEON-NOSVE-NEXT: .LBB3_10: // %else26 -; NONEON-NOSVE-NEXT: tbnz w8, #10, .LBB3_43 -; NONEON-NOSVE-NEXT: .LBB3_11: // %else29 -; NONEON-NOSVE-NEXT: tbnz w8, #11, .LBB3_44 -; NONEON-NOSVE-NEXT: .LBB3_12: // %else32 -; NONEON-NOSVE-NEXT: tbnz w8, #12, .LBB3_45 -; NONEON-NOSVE-NEXT: .LBB3_13: // %else35 -; NONEON-NOSVE-NEXT: tbnz w8, #13, .LBB3_46 -; NONEON-NOSVE-NEXT: .LBB3_14: // %else38 -; NONEON-NOSVE-NEXT: tbnz w8, #14, .LBB3_47 -; NONEON-NOSVE-NEXT: .LBB3_15: // %else41 -; NONEON-NOSVE-NEXT: tbnz w8, #15, .LBB3_48 -; NONEON-NOSVE-NEXT: .LBB3_16: // %else44 -; NONEON-NOSVE-NEXT: tbnz w8, #16, .LBB3_49 -; NONEON-NOSVE-NEXT: .LBB3_17: // %else47 -; NONEON-NOSVE-NEXT: tbnz w8, #17, .LBB3_50 -; NONEON-NOSVE-NEXT: .LBB3_18: // %else50 -; NONEON-NOSVE-NEXT: tbnz w8, #18, .LBB3_51 -; NONEON-NOSVE-NEXT: .LBB3_19: // %else53 -; NONEON-NOSVE-NEXT: tbnz w8, #19, .LBB3_52 -; NONEON-NOSVE-NEXT: .LBB3_20: // %else56 -; NONEON-NOSVE-NEXT: tbnz w8, #20, .LBB3_53 -; NONEON-NOSVE-NEXT: .LBB3_21: // %else59 -; NONEON-NOSVE-NEXT: tbnz w8, #21, .LBB3_54 -; NONEON-NOSVE-NEXT: .LBB3_22: // %else62 -; NONEON-NOSVE-NEXT: tbnz w8, #22, .LBB3_55 -; NONEON-NOSVE-NEXT: .LBB3_23: // %else65 -; NONEON-NOSVE-NEXT: tbnz w8, #23, .LBB3_56 -; NONEON-NOSVE-NEXT: .LBB3_24: // %else68 -; NONEON-NOSVE-NEXT: tbnz w8, #24, .LBB3_57 -; NONEON-NOSVE-NEXT: .LBB3_25: // %else71 -; NONEON-NOSVE-NEXT: tbnz w8, #25, .LBB3_58 -; NONEON-NOSVE-NEXT: .LBB3_26: // %else74 -; NONEON-NOSVE-NEXT: tbnz w8, #26, .LBB3_59 -; NONEON-NOSVE-NEXT: .LBB3_27: // %else77 -; NONEON-NOSVE-NEXT: tbnz w8, #27, .LBB3_60 -; NONEON-NOSVE-NEXT: .LBB3_28: // %else80 -; NONEON-NOSVE-NEXT: tbnz w8, #28, .LBB3_61 -; NONEON-NOSVE-NEXT: .LBB3_29: // %else83 -; NONEON-NOSVE-NEXT: tbnz w8, #29, .LBB3_62 -; NONEON-NOSVE-NEXT: .LBB3_30: // %else86 -; NONEON-NOSVE-NEXT: tbnz w8, #30, .LBB3_63 -; NONEON-NOSVE-NEXT: .LBB3_31: // %else89 -; NONEON-NOSVE-NEXT: tbnz w8, #31, .LBB3_64 -; NONEON-NOSVE-NEXT: .LBB3_32: // %else92 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB3_33: // %cond.load -; NONEON-NOSVE-NEXT: ldr b0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB3_2 -; NONEON-NOSVE-NEXT: .LBB3_34: // %cond.load1 -; NONEON-NOSVE-NEXT: add x9, x0, #1 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[1], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB3_3 -; NONEON-NOSVE-NEXT: .LBB3_35: // %cond.load4 -; NONEON-NOSVE-NEXT: add x9, x0, #2 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[2], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB3_4 -; NONEON-NOSVE-NEXT: .LBB3_36: // %cond.load7 -; NONEON-NOSVE-NEXT: add x9, x0, #3 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[3], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #4, .LBB3_5 -; NONEON-NOSVE-NEXT: .LBB3_37: // %cond.load10 -; NONEON-NOSVE-NEXT: add x9, x0, #4 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[4], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #5, .LBB3_6 -; NONEON-NOSVE-NEXT: .LBB3_38: // %cond.load13 -; NONEON-NOSVE-NEXT: add x9, x0, #5 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[5], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #6, .LBB3_7 -; NONEON-NOSVE-NEXT: .LBB3_39: // %cond.load16 -; NONEON-NOSVE-NEXT: add x9, x0, #6 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[6], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #7, .LBB3_8 -; NONEON-NOSVE-NEXT: .LBB3_40: // %cond.load19 -; NONEON-NOSVE-NEXT: add x9, x0, #7 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[7], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #8, .LBB3_9 -; NONEON-NOSVE-NEXT: .LBB3_41: // %cond.load22 -; NONEON-NOSVE-NEXT: add x9, x0, #8 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[8], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #9, .LBB3_10 -; NONEON-NOSVE-NEXT: .LBB3_42: // %cond.load25 -; NONEON-NOSVE-NEXT: add x9, x0, #9 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[9], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #10, .LBB3_11 -; NONEON-NOSVE-NEXT: .LBB3_43: // %cond.load28 -; NONEON-NOSVE-NEXT: add x9, x0, #10 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[10], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #11, .LBB3_12 -; NONEON-NOSVE-NEXT: .LBB3_44: // %cond.load31 -; NONEON-NOSVE-NEXT: add x9, x0, #11 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[11], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #12, .LBB3_13 -; NONEON-NOSVE-NEXT: .LBB3_45: // %cond.load34 -; NONEON-NOSVE-NEXT: add x9, x0, #12 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[12], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #13, .LBB3_14 -; NONEON-NOSVE-NEXT: .LBB3_46: // %cond.load37 -; NONEON-NOSVE-NEXT: add x9, x0, #13 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[13], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #14, .LBB3_15 -; NONEON-NOSVE-NEXT: .LBB3_47: // %cond.load40 -; NONEON-NOSVE-NEXT: add x9, x0, #14 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[14], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #15, .LBB3_16 -; NONEON-NOSVE-NEXT: .LBB3_48: // %cond.load43 -; NONEON-NOSVE-NEXT: add x9, x0, #15 -; NONEON-NOSVE-NEXT: ld1 { v0.b }[15], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #16, .LBB3_17 -; NONEON-NOSVE-NEXT: .LBB3_49: // %cond.load46 -; NONEON-NOSVE-NEXT: add x9, x0, #16 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[0], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #17, .LBB3_18 -; NONEON-NOSVE-NEXT: .LBB3_50: // %cond.load49 -; NONEON-NOSVE-NEXT: add x9, x0, #17 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[1], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #18, .LBB3_19 -; NONEON-NOSVE-NEXT: .LBB3_51: // %cond.load52 -; NONEON-NOSVE-NEXT: add x9, x0, #18 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[2], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #19, .LBB3_20 -; NONEON-NOSVE-NEXT: .LBB3_52: // %cond.load55 -; NONEON-NOSVE-NEXT: add x9, x0, #19 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[3], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #20, .LBB3_21 -; NONEON-NOSVE-NEXT: .LBB3_53: // %cond.load58 -; NONEON-NOSVE-NEXT: add x9, x0, #20 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[4], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #21, .LBB3_22 -; NONEON-NOSVE-NEXT: .LBB3_54: // %cond.load61 -; NONEON-NOSVE-NEXT: add x9, x0, #21 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[5], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #22, .LBB3_23 -; NONEON-NOSVE-NEXT: .LBB3_55: // %cond.load64 -; NONEON-NOSVE-NEXT: add x9, x0, #22 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[6], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #23, .LBB3_24 -; NONEON-NOSVE-NEXT: .LBB3_56: // %cond.load67 -; NONEON-NOSVE-NEXT: add x9, x0, #23 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[7], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #24, .LBB3_25 -; NONEON-NOSVE-NEXT: .LBB3_57: // %cond.load70 -; NONEON-NOSVE-NEXT: add x9, x0, #24 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[8], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #25, .LBB3_26 -; NONEON-NOSVE-NEXT: .LBB3_58: // %cond.load73 -; NONEON-NOSVE-NEXT: add x9, x0, #25 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[9], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #26, .LBB3_27 -; NONEON-NOSVE-NEXT: .LBB3_59: // %cond.load76 -; NONEON-NOSVE-NEXT: add x9, x0, #26 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[10], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #27, .LBB3_28 -; NONEON-NOSVE-NEXT: .LBB3_60: // %cond.load79 -; NONEON-NOSVE-NEXT: add x9, x0, #27 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[11], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #28, .LBB3_29 -; NONEON-NOSVE-NEXT: .LBB3_61: // %cond.load82 -; NONEON-NOSVE-NEXT: add x9, x0, #28 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[12], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #29, .LBB3_30 -; NONEON-NOSVE-NEXT: .LBB3_62: // %cond.load85 -; NONEON-NOSVE-NEXT: add x9, x0, #29 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[13], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #30, .LBB3_31 -; NONEON-NOSVE-NEXT: .LBB3_63: // %cond.load88 -; NONEON-NOSVE-NEXT: add x9, x0, #30 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[14], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #31, .LBB3_32 -; NONEON-NOSVE-NEXT: .LBB3_64: // %cond.load91 -; NONEON-NOSVE-NEXT: add x8, x0, #31 -; NONEON-NOSVE-NEXT: ld1 { v1.b }[15], [x8] -; NONEON-NOSVE-NEXT: ret %load = call <32 x i8> @llvm.masked.load.v32i8(ptr %src, i32 8, <32 x i1> %mask, <32 x i8> zeroinitializer) ret <32 x i8> %load } @@ -635,31 +155,6 @@ define <2 x half> @masked_load_v2f16(ptr %src, <2 x i1> %mask) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #31 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI4_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI4_0] -; NONEON-NOSVE-NEXT: cmlt v0.2s, v0.2s, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addp v1.2s, v0.2s, v0.2s -; NONEON-NOSVE-NEXT: movi d0, #0000000000000000 -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB4_3 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB4_4 -; NONEON-NOSVE-NEXT: .LBB4_2: // %else2 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB4_3: // %cond.load -; NONEON-NOSVE-NEXT: ldr h0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB4_2 -; NONEON-NOSVE-NEXT: .LBB4_4: // %cond.load1 -; NONEON-NOSVE-NEXT: add x8, x0, #2 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[1], [x8] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %load = call <2 x half> @llvm.masked.load.v2f16(ptr %src, i32 8, <2 x i1> %mask, <2 x half> zeroinitializer) ret <2 x half> %load } @@ -675,43 +170,6 @@ define <4 x half> @masked_load_v4f16(ptr %src, <4 x i1> %mask) { ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #15 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI5_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI5_0] -; NONEON-NOSVE-NEXT: cmlt v0.4h, v0.4h, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addv h1, v0.4h -; NONEON-NOSVE-NEXT: movi d0, #0000000000000000 -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB5_5 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB5_6 -; NONEON-NOSVE-NEXT: .LBB5_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB5_7 -; NONEON-NOSVE-NEXT: .LBB5_3: // %else5 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB5_8 -; NONEON-NOSVE-NEXT: .LBB5_4: // %else8 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB5_5: // %cond.load -; NONEON-NOSVE-NEXT: ldr h0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB5_2 -; NONEON-NOSVE-NEXT: .LBB5_6: // %cond.load1 -; NONEON-NOSVE-NEXT: add x9, x0, #2 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[1], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB5_3 -; NONEON-NOSVE-NEXT: .LBB5_7: // %cond.load4 -; NONEON-NOSVE-NEXT: add x9, x0, #4 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[2], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB5_4 -; NONEON-NOSVE-NEXT: .LBB5_8: // %cond.load7 -; NONEON-NOSVE-NEXT: add x8, x0, #6 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[3], [x8] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %load = call <4 x half> @llvm.masked.load.v4f16(ptr %src, i32 8, <4 x i1> %mask, <4 x half> zeroinitializer) ret <4 x half> %load } @@ -728,65 +186,6 @@ define <8 x half> @masked_load_v8f16(ptr %src, <8 x i1> %mask) { ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.8b, v0.8b, #7 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI6_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI6_0] -; NONEON-NOSVE-NEXT: cmlt v0.8b, v0.8b, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addv b1, v0.8b -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB6_9 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB6_10 -; NONEON-NOSVE-NEXT: .LBB6_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB6_11 -; NONEON-NOSVE-NEXT: .LBB6_3: // %else5 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB6_12 -; NONEON-NOSVE-NEXT: .LBB6_4: // %else8 -; NONEON-NOSVE-NEXT: tbnz w8, #4, .LBB6_13 -; NONEON-NOSVE-NEXT: .LBB6_5: // %else11 -; NONEON-NOSVE-NEXT: tbnz w8, #5, .LBB6_14 -; NONEON-NOSVE-NEXT: .LBB6_6: // %else14 -; NONEON-NOSVE-NEXT: tbnz w8, #6, .LBB6_15 -; NONEON-NOSVE-NEXT: .LBB6_7: // %else17 -; NONEON-NOSVE-NEXT: tbnz w8, #7, .LBB6_16 -; NONEON-NOSVE-NEXT: .LBB6_8: // %else20 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB6_9: // %cond.load -; NONEON-NOSVE-NEXT: ldr h0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB6_2 -; NONEON-NOSVE-NEXT: .LBB6_10: // %cond.load1 -; NONEON-NOSVE-NEXT: add x9, x0, #2 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[1], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB6_3 -; NONEON-NOSVE-NEXT: .LBB6_11: // %cond.load4 -; NONEON-NOSVE-NEXT: add x9, x0, #4 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[2], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB6_4 -; NONEON-NOSVE-NEXT: .LBB6_12: // %cond.load7 -; NONEON-NOSVE-NEXT: add x9, x0, #6 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[3], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #4, .LBB6_5 -; NONEON-NOSVE-NEXT: .LBB6_13: // %cond.load10 -; NONEON-NOSVE-NEXT: add x9, x0, #8 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[4], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #5, .LBB6_6 -; NONEON-NOSVE-NEXT: .LBB6_14: // %cond.load13 -; NONEON-NOSVE-NEXT: add x9, x0, #10 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[5], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #6, .LBB6_7 -; NONEON-NOSVE-NEXT: .LBB6_15: // %cond.load16 -; NONEON-NOSVE-NEXT: add x9, x0, #12 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[6], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #7, .LBB6_8 -; NONEON-NOSVE-NEXT: .LBB6_16: // %cond.load19 -; NONEON-NOSVE-NEXT: add x8, x0, #14 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[7], [x8] -; NONEON-NOSVE-NEXT: ret %load = call <8 x half> @llvm.masked.load.v8f16(ptr %src, i32 8, <8 x i1> %mask, <8 x half> zeroinitializer) ret <8 x half> %load } @@ -811,116 +210,6 @@ define <16 x half> @masked_load_v16f16(ptr %src, <16 x i1> %mask) { ; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0, x8, lsl #1] ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.16b, v0.16b, #7 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI7_0 -; NONEON-NOSVE-NEXT: ldr q1, [x8, :lo12:.LCPI7_0] -; NONEON-NOSVE-NEXT: cmlt v0.16b, v0.16b, #0 -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; NONEON-NOSVE-NEXT: zip1 v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: movi v1.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: addv h2, v0.8h -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: fmov w8, s2 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB7_17 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB7_18 -; NONEON-NOSVE-NEXT: .LBB7_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB7_19 -; NONEON-NOSVE-NEXT: .LBB7_3: // %else5 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB7_20 -; NONEON-NOSVE-NEXT: .LBB7_4: // %else8 -; NONEON-NOSVE-NEXT: tbnz w8, #4, .LBB7_21 -; NONEON-NOSVE-NEXT: .LBB7_5: // %else11 -; NONEON-NOSVE-NEXT: tbnz w8, #5, .LBB7_22 -; NONEON-NOSVE-NEXT: .LBB7_6: // %else14 -; NONEON-NOSVE-NEXT: tbnz w8, #6, .LBB7_23 -; NONEON-NOSVE-NEXT: .LBB7_7: // %else17 -; NONEON-NOSVE-NEXT: tbnz w8, #7, .LBB7_24 -; NONEON-NOSVE-NEXT: .LBB7_8: // %else20 -; NONEON-NOSVE-NEXT: tbnz w8, #8, .LBB7_25 -; NONEON-NOSVE-NEXT: .LBB7_9: // %else23 -; NONEON-NOSVE-NEXT: tbnz w8, #9, .LBB7_26 -; NONEON-NOSVE-NEXT: .LBB7_10: // %else26 -; NONEON-NOSVE-NEXT: tbnz w8, #10, .LBB7_27 -; NONEON-NOSVE-NEXT: .LBB7_11: // %else29 -; NONEON-NOSVE-NEXT: tbnz w8, #11, .LBB7_28 -; NONEON-NOSVE-NEXT: .LBB7_12: // %else32 -; NONEON-NOSVE-NEXT: tbnz w8, #12, .LBB7_29 -; NONEON-NOSVE-NEXT: .LBB7_13: // %else35 -; NONEON-NOSVE-NEXT: tbnz w8, #13, .LBB7_30 -; NONEON-NOSVE-NEXT: .LBB7_14: // %else38 -; NONEON-NOSVE-NEXT: tbnz w8, #14, .LBB7_31 -; NONEON-NOSVE-NEXT: .LBB7_15: // %else41 -; NONEON-NOSVE-NEXT: tbnz w8, #15, .LBB7_32 -; NONEON-NOSVE-NEXT: .LBB7_16: // %else44 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB7_17: // %cond.load -; NONEON-NOSVE-NEXT: ldr h0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB7_2 -; NONEON-NOSVE-NEXT: .LBB7_18: // %cond.load1 -; NONEON-NOSVE-NEXT: add x9, x0, #2 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[1], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB7_3 -; NONEON-NOSVE-NEXT: .LBB7_19: // %cond.load4 -; NONEON-NOSVE-NEXT: add x9, x0, #4 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[2], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB7_4 -; NONEON-NOSVE-NEXT: .LBB7_20: // %cond.load7 -; NONEON-NOSVE-NEXT: add x9, x0, #6 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[3], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #4, .LBB7_5 -; NONEON-NOSVE-NEXT: .LBB7_21: // %cond.load10 -; NONEON-NOSVE-NEXT: add x9, x0, #8 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[4], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #5, .LBB7_6 -; NONEON-NOSVE-NEXT: .LBB7_22: // %cond.load13 -; NONEON-NOSVE-NEXT: add x9, x0, #10 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[5], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #6, .LBB7_7 -; NONEON-NOSVE-NEXT: .LBB7_23: // %cond.load16 -; NONEON-NOSVE-NEXT: add x9, x0, #12 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[6], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #7, .LBB7_8 -; NONEON-NOSVE-NEXT: .LBB7_24: // %cond.load19 -; NONEON-NOSVE-NEXT: add x9, x0, #14 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[7], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #8, .LBB7_9 -; NONEON-NOSVE-NEXT: .LBB7_25: // %cond.load22 -; NONEON-NOSVE-NEXT: add x9, x0, #16 -; NONEON-NOSVE-NEXT: ld1 { v1.h }[0], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #9, .LBB7_10 -; NONEON-NOSVE-NEXT: .LBB7_26: // %cond.load25 -; NONEON-NOSVE-NEXT: add x9, x0, #18 -; NONEON-NOSVE-NEXT: ld1 { v1.h }[1], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #10, .LBB7_11 -; NONEON-NOSVE-NEXT: .LBB7_27: // %cond.load28 -; NONEON-NOSVE-NEXT: add x9, x0, #20 -; NONEON-NOSVE-NEXT: ld1 { v1.h }[2], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #11, .LBB7_12 -; NONEON-NOSVE-NEXT: .LBB7_28: // %cond.load31 -; NONEON-NOSVE-NEXT: add x9, x0, #22 -; NONEON-NOSVE-NEXT: ld1 { v1.h }[3], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #12, .LBB7_13 -; NONEON-NOSVE-NEXT: .LBB7_29: // %cond.load34 -; NONEON-NOSVE-NEXT: add x9, x0, #24 -; NONEON-NOSVE-NEXT: ld1 { v1.h }[4], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #13, .LBB7_14 -; NONEON-NOSVE-NEXT: .LBB7_30: // %cond.load37 -; NONEON-NOSVE-NEXT: add x9, x0, #26 -; NONEON-NOSVE-NEXT: ld1 { v1.h }[5], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #14, .LBB7_15 -; NONEON-NOSVE-NEXT: .LBB7_31: // %cond.load40 -; NONEON-NOSVE-NEXT: add x9, x0, #28 -; NONEON-NOSVE-NEXT: ld1 { v1.h }[6], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #15, .LBB7_16 -; NONEON-NOSVE-NEXT: .LBB7_32: // %cond.load43 -; NONEON-NOSVE-NEXT: add x8, x0, #30 -; NONEON-NOSVE-NEXT: ld1 { v1.h }[7], [x8] -; NONEON-NOSVE-NEXT: ret %load = call <16 x half> @llvm.masked.load.v16f16(ptr %src, i32 8, <16 x i1> %mask, <16 x half> zeroinitializer) ret <16 x half> %load } @@ -936,31 +225,6 @@ define <2 x float> @masked_load_v2f32(ptr %src, <2 x i1> %mask) { ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #31 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI8_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI8_0] -; NONEON-NOSVE-NEXT: cmlt v0.2s, v0.2s, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addp v1.2s, v0.2s, v0.2s -; NONEON-NOSVE-NEXT: movi d0, #0000000000000000 -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB8_3 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB8_4 -; NONEON-NOSVE-NEXT: .LBB8_2: // %else2 -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB8_3: // %cond.load -; NONEON-NOSVE-NEXT: ldr s0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB8_2 -; NONEON-NOSVE-NEXT: .LBB8_4: // %cond.load1 -; NONEON-NOSVE-NEXT: add x8, x0, #4 -; NONEON-NOSVE-NEXT: ld1 { v0.s }[1], [x8] -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0 -; NONEON-NOSVE-NEXT: ret %load = call <2 x float> @llvm.masked.load.v2f32(ptr %src, i32 8, <2 x i1> %mask, <2 x float> zeroinitializer) ret <2 x float> %load } @@ -977,41 +241,6 @@ define <4 x float> @masked_load_v4f32(ptr %src, <4 x i1> %mask) { ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #15 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI9_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI9_0] -; NONEON-NOSVE-NEXT: cmlt v0.4h, v0.4h, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addv h1, v0.4h -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB9_5 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB9_6 -; NONEON-NOSVE-NEXT: .LBB9_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB9_7 -; NONEON-NOSVE-NEXT: .LBB9_3: // %else5 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB9_8 -; NONEON-NOSVE-NEXT: .LBB9_4: // %else8 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB9_5: // %cond.load -; NONEON-NOSVE-NEXT: ldr s0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB9_2 -; NONEON-NOSVE-NEXT: .LBB9_6: // %cond.load1 -; NONEON-NOSVE-NEXT: add x9, x0, #4 -; NONEON-NOSVE-NEXT: ld1 { v0.s }[1], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB9_3 -; NONEON-NOSVE-NEXT: .LBB9_7: // %cond.load4 -; NONEON-NOSVE-NEXT: add x9, x0, #8 -; NONEON-NOSVE-NEXT: ld1 { v0.s }[2], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB9_4 -; NONEON-NOSVE-NEXT: .LBB9_8: // %cond.load7 -; NONEON-NOSVE-NEXT: add x8, x0, #12 -; NONEON-NOSVE-NEXT: ld1 { v0.s }[3], [x8] -; NONEON-NOSVE-NEXT: ret %load = call <4 x float> @llvm.masked.load.v4f32(ptr %src, i32 8, <4 x i1> %mask, <4 x float> zeroinitializer) ret <4 x float> %load } @@ -1061,66 +290,6 @@ define <8 x float> @masked_load_v8f32(ptr %src, <8 x i1> %mask) { ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.8b, v0.8b, #7 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI10_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI10_0] -; NONEON-NOSVE-NEXT: cmlt v0.8b, v0.8b, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: movi v1.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: addv b2, v0.8b -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: fmov w8, s2 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB10_9 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB10_10 -; NONEON-NOSVE-NEXT: .LBB10_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB10_11 -; NONEON-NOSVE-NEXT: .LBB10_3: // %else5 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB10_12 -; NONEON-NOSVE-NEXT: .LBB10_4: // %else8 -; NONEON-NOSVE-NEXT: tbnz w8, #4, .LBB10_13 -; NONEON-NOSVE-NEXT: .LBB10_5: // %else11 -; NONEON-NOSVE-NEXT: tbnz w8, #5, .LBB10_14 -; NONEON-NOSVE-NEXT: .LBB10_6: // %else14 -; NONEON-NOSVE-NEXT: tbnz w8, #6, .LBB10_15 -; NONEON-NOSVE-NEXT: .LBB10_7: // %else17 -; NONEON-NOSVE-NEXT: tbnz w8, #7, .LBB10_16 -; NONEON-NOSVE-NEXT: .LBB10_8: // %else20 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB10_9: // %cond.load -; NONEON-NOSVE-NEXT: ldr s0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB10_2 -; NONEON-NOSVE-NEXT: .LBB10_10: // %cond.load1 -; NONEON-NOSVE-NEXT: add x9, x0, #4 -; NONEON-NOSVE-NEXT: ld1 { v0.s }[1], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB10_3 -; NONEON-NOSVE-NEXT: .LBB10_11: // %cond.load4 -; NONEON-NOSVE-NEXT: add x9, x0, #8 -; NONEON-NOSVE-NEXT: ld1 { v0.s }[2], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB10_4 -; NONEON-NOSVE-NEXT: .LBB10_12: // %cond.load7 -; NONEON-NOSVE-NEXT: add x9, x0, #12 -; NONEON-NOSVE-NEXT: ld1 { v0.s }[3], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #4, .LBB10_5 -; NONEON-NOSVE-NEXT: .LBB10_13: // %cond.load10 -; NONEON-NOSVE-NEXT: add x9, x0, #16 -; NONEON-NOSVE-NEXT: ld1 { v1.s }[0], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #5, .LBB10_6 -; NONEON-NOSVE-NEXT: .LBB10_14: // %cond.load13 -; NONEON-NOSVE-NEXT: add x9, x0, #20 -; NONEON-NOSVE-NEXT: ld1 { v1.s }[1], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #6, .LBB10_7 -; NONEON-NOSVE-NEXT: .LBB10_15: // %cond.load16 -; NONEON-NOSVE-NEXT: add x9, x0, #24 -; NONEON-NOSVE-NEXT: ld1 { v1.s }[2], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #7, .LBB10_8 -; NONEON-NOSVE-NEXT: .LBB10_16: // %cond.load19 -; NONEON-NOSVE-NEXT: add x8, x0, #28 -; NONEON-NOSVE-NEXT: ld1 { v1.s }[3], [x8] -; NONEON-NOSVE-NEXT: ret %load = call <8 x float> @llvm.masked.load.v8f32(ptr %src, i32 8, <8 x i1> %mask, <8 x float> zeroinitializer) ret <8 x float> %load } @@ -1137,29 +306,6 @@ define <2 x double> @masked_load_v2f64(ptr %src, <2 x i1> %mask) { ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #31 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI11_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI11_0] -; NONEON-NOSVE-NEXT: cmlt v0.2s, v0.2s, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addp v1.2s, v0.2s, v0.2s -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB11_3 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB11_4 -; NONEON-NOSVE-NEXT: .LBB11_2: // %else2 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB11_3: // %cond.load -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB11_2 -; NONEON-NOSVE-NEXT: .LBB11_4: // %cond.load1 -; NONEON-NOSVE-NEXT: add x8, x0, #8 -; NONEON-NOSVE-NEXT: ld1 { v0.d }[1], [x8] -; NONEON-NOSVE-NEXT: ret %load = call <2 x double> @llvm.masked.load.v2f64(ptr %src, i32 8, <2 x i1> %mask, <2 x double> zeroinitializer) ret <2 x double> %load } @@ -1185,42 +331,6 @@ define <4 x double> @masked_load_v4f64(ptr %src, <4 x i1> %mask) { ; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, x8, lsl #3] ; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #15 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI12_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI12_0] -; NONEON-NOSVE-NEXT: cmlt v0.4h, v0.4h, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: movi v1.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: addv h2, v0.4h -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: fmov w8, s2 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB12_5 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB12_6 -; NONEON-NOSVE-NEXT: .LBB12_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB12_7 -; NONEON-NOSVE-NEXT: .LBB12_3: // %else5 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB12_8 -; NONEON-NOSVE-NEXT: .LBB12_4: // %else8 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB12_5: // %cond.load -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB12_2 -; NONEON-NOSVE-NEXT: .LBB12_6: // %cond.load1 -; NONEON-NOSVE-NEXT: add x9, x0, #8 -; NONEON-NOSVE-NEXT: ld1 { v0.d }[1], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB12_3 -; NONEON-NOSVE-NEXT: .LBB12_7: // %cond.load4 -; NONEON-NOSVE-NEXT: add x9, x0, #16 -; NONEON-NOSVE-NEXT: ld1 { v1.d }[0], [x9] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB12_4 -; NONEON-NOSVE-NEXT: .LBB12_8: // %cond.load7 -; NONEON-NOSVE-NEXT: add x8, x0, #24 -; NONEON-NOSVE-NEXT: ld1 { v1.d }[1], [x8] -; NONEON-NOSVE-NEXT: ret %load = call <4 x double> @llvm.masked.load.v4f64(ptr %src, i32 8, <4 x i1> %mask, <4 x double> zeroinitializer) ret <4 x double> %load } @@ -1246,38 +356,6 @@ define <3 x i32> @masked_load_zext_v3i32(ptr %load_ptr, <3 x i1> %pm) { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_zext_v3i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub sp, sp, #16 -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: and w8, w1, #0x1 -; NONEON-NOSVE-NEXT: bfi w8, w2, #1, #1 -; NONEON-NOSVE-NEXT: bfi w8, w3, #2, #1 -; NONEON-NOSVE-NEXT: tbz w8, #0, .LBB13_2 -; NONEON-NOSVE-NEXT: // %bb.1: // %cond.load -; NONEON-NOSVE-NEXT: ldr h0, [x0] -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB13_3 -; NONEON-NOSVE-NEXT: b .LBB13_4 -; NONEON-NOSVE-NEXT: .LBB13_2: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB13_4 -; NONEON-NOSVE-NEXT: .LBB13_3: // %cond.load1 -; NONEON-NOSVE-NEXT: mov v1.16b, v0.16b -; NONEON-NOSVE-NEXT: add x9, x0, #2 -; NONEON-NOSVE-NEXT: ld1 { v1.h }[1], [x9] -; NONEON-NOSVE-NEXT: mov v1.h[2], v0.h[2] -; NONEON-NOSVE-NEXT: fmov d0, d1 -; NONEON-NOSVE-NEXT: .LBB13_4: // %else2 -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB13_6 -; NONEON-NOSVE-NEXT: // %bb.5: // %cond.load4 -; NONEON-NOSVE-NEXT: mov v0.h[1], v0.h[1] -; NONEON-NOSVE-NEXT: add x8, x0, #4 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[2], [x8] -; NONEON-NOSVE-NEXT: .LBB13_6: // %else5 -; NONEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %load_value = tail call <3 x i16> @llvm.masked.load.v3i16.p0(ptr %load_ptr, i32 4, <3 x i1> %pm, <3 x i16> zeroinitializer) %extend = zext <3 x i16> %load_value to <3 x i32> ret <3 x i32> %extend; @@ -1304,38 +382,6 @@ define <3 x i32> @masked_load_sext_v3i32(ptr %load_ptr, <3 x i1> %pm) { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_load_sext_v3i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: sub sp, sp, #16 -; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 -; NONEON-NOSVE-NEXT: and w8, w1, #0x1 -; NONEON-NOSVE-NEXT: bfi w8, w2, #1, #1 -; NONEON-NOSVE-NEXT: bfi w8, w3, #2, #1 -; NONEON-NOSVE-NEXT: tbz w8, #0, .LBB14_2 -; NONEON-NOSVE-NEXT: // %bb.1: // %cond.load -; NONEON-NOSVE-NEXT: ldr h0, [x0] -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB14_3 -; NONEON-NOSVE-NEXT: b .LBB14_4 -; NONEON-NOSVE-NEXT: .LBB14_2: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB14_4 -; NONEON-NOSVE-NEXT: .LBB14_3: // %cond.load1 -; NONEON-NOSVE-NEXT: mov v1.16b, v0.16b -; NONEON-NOSVE-NEXT: add x9, x0, #2 -; NONEON-NOSVE-NEXT: ld1 { v1.h }[1], [x9] -; NONEON-NOSVE-NEXT: mov v1.h[2], v0.h[2] -; NONEON-NOSVE-NEXT: fmov d0, d1 -; NONEON-NOSVE-NEXT: .LBB14_4: // %else2 -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB14_6 -; NONEON-NOSVE-NEXT: // %bb.5: // %cond.load4 -; NONEON-NOSVE-NEXT: mov v0.h[1], v0.h[1] -; NONEON-NOSVE-NEXT: add x8, x0, #4 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[2], [x8] -; NONEON-NOSVE-NEXT: .LBB14_6: // %else5 -; NONEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NONEON-NOSVE-NEXT: add sp, sp, #16 -; NONEON-NOSVE-NEXT: ret %load_value = tail call <3 x i16> @llvm.masked.load.v3i16.p0(ptr %load_ptr, i32 4, <3 x i1> %pm, <3 x i16> zeroinitializer) %extend = sext <3 x i16> %load_value to <3 x i32> ret <3 x i32> %extend; diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll index b175dcf3e9a0..f2b3f9b12ea7 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -20,37 +19,6 @@ define void @masked_store_v4i8(ptr %dst, <4 x i1> %mask) { ; CHECK-NEXT: mov z0.h, #0 // =0x0 ; CHECK-NEXT: st1b { z0.h }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_store_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #15 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI0_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI0_0] -; NONEON-NOSVE-NEXT: cmlt v0.4h, v0.4h, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addv h0, v0.4h -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB0_5 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB0_6 -; NONEON-NOSVE-NEXT: .LBB0_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB0_7 -; NONEON-NOSVE-NEXT: .LBB0_3: // %else4 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB0_8 -; NONEON-NOSVE-NEXT: .LBB0_4: // %else6 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB0_5: // %cond.store -; NONEON-NOSVE-NEXT: strb wzr, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB0_2 -; NONEON-NOSVE-NEXT: .LBB0_6: // %cond.store1 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #1] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB0_3 -; NONEON-NOSVE-NEXT: .LBB0_7: // %cond.store3 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #2] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB0_4 -; NONEON-NOSVE-NEXT: .LBB0_8: // %cond.store5 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #3] -; NONEON-NOSVE-NEXT: ret call void @llvm.masked.store.v4i8(<4 x i8> zeroinitializer, ptr %dst, i32 8, <4 x i1> %mask) ret void } @@ -66,57 +34,6 @@ define void @masked_store_v8i8(ptr %dst, <8 x i1> %mask) { ; CHECK-NEXT: mov z0.b, #0 // =0x0 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_store_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.8b, v0.8b, #7 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI1_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI1_0] -; NONEON-NOSVE-NEXT: cmlt v0.8b, v0.8b, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addv b0, v0.8b -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB1_9 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB1_10 -; NONEON-NOSVE-NEXT: .LBB1_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB1_11 -; NONEON-NOSVE-NEXT: .LBB1_3: // %else4 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB1_12 -; NONEON-NOSVE-NEXT: .LBB1_4: // %else6 -; NONEON-NOSVE-NEXT: tbnz w8, #4, .LBB1_13 -; NONEON-NOSVE-NEXT: .LBB1_5: // %else8 -; NONEON-NOSVE-NEXT: tbnz w8, #5, .LBB1_14 -; NONEON-NOSVE-NEXT: .LBB1_6: // %else10 -; NONEON-NOSVE-NEXT: tbnz w8, #6, .LBB1_15 -; NONEON-NOSVE-NEXT: .LBB1_7: // %else12 -; NONEON-NOSVE-NEXT: tbnz w8, #7, .LBB1_16 -; NONEON-NOSVE-NEXT: .LBB1_8: // %else14 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB1_9: // %cond.store -; NONEON-NOSVE-NEXT: strb wzr, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB1_2 -; NONEON-NOSVE-NEXT: .LBB1_10: // %cond.store1 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #1] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB1_3 -; NONEON-NOSVE-NEXT: .LBB1_11: // %cond.store3 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #2] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB1_4 -; NONEON-NOSVE-NEXT: .LBB1_12: // %cond.store5 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #3] -; NONEON-NOSVE-NEXT: tbz w8, #4, .LBB1_5 -; NONEON-NOSVE-NEXT: .LBB1_13: // %cond.store7 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #4] -; NONEON-NOSVE-NEXT: tbz w8, #5, .LBB1_6 -; NONEON-NOSVE-NEXT: .LBB1_14: // %cond.store9 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #5] -; NONEON-NOSVE-NEXT: tbz w8, #6, .LBB1_7 -; NONEON-NOSVE-NEXT: .LBB1_15: // %cond.store11 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #6] -; NONEON-NOSVE-NEXT: tbz w8, #7, .LBB1_8 -; NONEON-NOSVE-NEXT: .LBB1_16: // %cond.store13 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #7] -; NONEON-NOSVE-NEXT: ret call void @llvm.masked.store.v8i8(<8 x i8> zeroinitializer, ptr %dst, i32 8, <8 x i1> %mask) ret void } @@ -132,99 +49,6 @@ define void @masked_store_v16i8(ptr %dst, <16 x i1> %mask) { ; CHECK-NEXT: mov z0.b, #0 // =0x0 ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_store_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.16b, v0.16b, #7 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI2_0 -; NONEON-NOSVE-NEXT: ldr q1, [x8, :lo12:.LCPI2_0] -; NONEON-NOSVE-NEXT: cmlt v0.16b, v0.16b, #0 -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; NONEON-NOSVE-NEXT: zip1 v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: addv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB2_17 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB2_18 -; NONEON-NOSVE-NEXT: .LBB2_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB2_19 -; NONEON-NOSVE-NEXT: .LBB2_3: // %else4 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB2_20 -; NONEON-NOSVE-NEXT: .LBB2_4: // %else6 -; NONEON-NOSVE-NEXT: tbnz w8, #4, .LBB2_21 -; NONEON-NOSVE-NEXT: .LBB2_5: // %else8 -; NONEON-NOSVE-NEXT: tbnz w8, #5, .LBB2_22 -; NONEON-NOSVE-NEXT: .LBB2_6: // %else10 -; NONEON-NOSVE-NEXT: tbnz w8, #6, .LBB2_23 -; NONEON-NOSVE-NEXT: .LBB2_7: // %else12 -; NONEON-NOSVE-NEXT: tbnz w8, #7, .LBB2_24 -; NONEON-NOSVE-NEXT: .LBB2_8: // %else14 -; NONEON-NOSVE-NEXT: tbnz w8, #8, .LBB2_25 -; NONEON-NOSVE-NEXT: .LBB2_9: // %else16 -; NONEON-NOSVE-NEXT: tbnz w8, #9, .LBB2_26 -; NONEON-NOSVE-NEXT: .LBB2_10: // %else18 -; NONEON-NOSVE-NEXT: tbnz w8, #10, .LBB2_27 -; NONEON-NOSVE-NEXT: .LBB2_11: // %else20 -; NONEON-NOSVE-NEXT: tbnz w8, #11, .LBB2_28 -; NONEON-NOSVE-NEXT: .LBB2_12: // %else22 -; NONEON-NOSVE-NEXT: tbnz w8, #12, .LBB2_29 -; NONEON-NOSVE-NEXT: .LBB2_13: // %else24 -; NONEON-NOSVE-NEXT: tbnz w8, #13, .LBB2_30 -; NONEON-NOSVE-NEXT: .LBB2_14: // %else26 -; NONEON-NOSVE-NEXT: tbnz w8, #14, .LBB2_31 -; NONEON-NOSVE-NEXT: .LBB2_15: // %else28 -; NONEON-NOSVE-NEXT: tbnz w8, #15, .LBB2_32 -; NONEON-NOSVE-NEXT: .LBB2_16: // %else30 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB2_17: // %cond.store -; NONEON-NOSVE-NEXT: strb wzr, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB2_2 -; NONEON-NOSVE-NEXT: .LBB2_18: // %cond.store1 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #1] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB2_3 -; NONEON-NOSVE-NEXT: .LBB2_19: // %cond.store3 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #2] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB2_4 -; NONEON-NOSVE-NEXT: .LBB2_20: // %cond.store5 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #3] -; NONEON-NOSVE-NEXT: tbz w8, #4, .LBB2_5 -; NONEON-NOSVE-NEXT: .LBB2_21: // %cond.store7 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #4] -; NONEON-NOSVE-NEXT: tbz w8, #5, .LBB2_6 -; NONEON-NOSVE-NEXT: .LBB2_22: // %cond.store9 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #5] -; NONEON-NOSVE-NEXT: tbz w8, #6, .LBB2_7 -; NONEON-NOSVE-NEXT: .LBB2_23: // %cond.store11 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #6] -; NONEON-NOSVE-NEXT: tbz w8, #7, .LBB2_8 -; NONEON-NOSVE-NEXT: .LBB2_24: // %cond.store13 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #7] -; NONEON-NOSVE-NEXT: tbz w8, #8, .LBB2_9 -; NONEON-NOSVE-NEXT: .LBB2_25: // %cond.store15 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #8] -; NONEON-NOSVE-NEXT: tbz w8, #9, .LBB2_10 -; NONEON-NOSVE-NEXT: .LBB2_26: // %cond.store17 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #9] -; NONEON-NOSVE-NEXT: tbz w8, #10, .LBB2_11 -; NONEON-NOSVE-NEXT: .LBB2_27: // %cond.store19 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #10] -; NONEON-NOSVE-NEXT: tbz w8, #11, .LBB2_12 -; NONEON-NOSVE-NEXT: .LBB2_28: // %cond.store21 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #11] -; NONEON-NOSVE-NEXT: tbz w8, #12, .LBB2_13 -; NONEON-NOSVE-NEXT: .LBB2_29: // %cond.store23 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #12] -; NONEON-NOSVE-NEXT: tbz w8, #13, .LBB2_14 -; NONEON-NOSVE-NEXT: .LBB2_30: // %cond.store25 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #13] -; NONEON-NOSVE-NEXT: tbz w8, #14, .LBB2_15 -; NONEON-NOSVE-NEXT: .LBB2_31: // %cond.store27 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #14] -; NONEON-NOSVE-NEXT: tbz w8, #15, .LBB2_16 -; NONEON-NOSVE-NEXT: .LBB2_32: // %cond.store29 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #15] -; NONEON-NOSVE-NEXT: ret call void @llvm.masked.store.v16i8(<16 x i8> zeroinitializer, ptr %dst, i32 8, <16 x i1> %mask) ret void } @@ -305,244 +129,6 @@ define void @masked_store_v32i8(ptr %dst, <32 x i1> %mask) { ; CHECK-NEXT: st1b { z0.b }, p0, [x0] ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_store_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr w8, [sp, #72] -; NONEON-NOSVE-NEXT: fmov s1, w1 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #80] -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #88] -; NONEON-NOSVE-NEXT: mov v1.b[1], w2 -; NONEON-NOSVE-NEXT: mov v0.b[1], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp] -; NONEON-NOSVE-NEXT: mov v1.b[2], w3 -; NONEON-NOSVE-NEXT: mov v0.b[2], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #96] -; NONEON-NOSVE-NEXT: mov v1.b[3], w4 -; NONEON-NOSVE-NEXT: mov v0.b[3], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #104] -; NONEON-NOSVE-NEXT: mov v1.b[4], w5 -; NONEON-NOSVE-NEXT: mov v0.b[4], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #112] -; NONEON-NOSVE-NEXT: mov v1.b[5], w6 -; NONEON-NOSVE-NEXT: mov v0.b[5], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #120] -; NONEON-NOSVE-NEXT: mov v1.b[6], w7 -; NONEON-NOSVE-NEXT: mov v0.b[6], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #128] -; NONEON-NOSVE-NEXT: mov v1.b[7], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #8] -; NONEON-NOSVE-NEXT: mov v0.b[7], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #136] -; NONEON-NOSVE-NEXT: mov v1.b[8], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #16] -; NONEON-NOSVE-NEXT: mov v0.b[8], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #144] -; NONEON-NOSVE-NEXT: mov v1.b[9], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #24] -; NONEON-NOSVE-NEXT: mov v0.b[9], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #152] -; NONEON-NOSVE-NEXT: mov v1.b[10], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #32] -; NONEON-NOSVE-NEXT: mov v0.b[10], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #160] -; NONEON-NOSVE-NEXT: mov v1.b[11], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #40] -; NONEON-NOSVE-NEXT: mov v0.b[11], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #168] -; NONEON-NOSVE-NEXT: mov v1.b[12], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #48] -; NONEON-NOSVE-NEXT: mov v0.b[12], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #176] -; NONEON-NOSVE-NEXT: mov v1.b[13], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #56] -; NONEON-NOSVE-NEXT: mov v0.b[13], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #184] -; NONEON-NOSVE-NEXT: mov v1.b[14], w9 -; NONEON-NOSVE-NEXT: ldr w9, [sp, #64] -; NONEON-NOSVE-NEXT: mov v0.b[14], w8 -; NONEON-NOSVE-NEXT: ldr w8, [sp, #192] -; NONEON-NOSVE-NEXT: mov v1.b[15], w9 -; NONEON-NOSVE-NEXT: mov v0.b[15], w8 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI3_0 -; NONEON-NOSVE-NEXT: ldr q2, [x8, :lo12:.LCPI3_0] -; NONEON-NOSVE-NEXT: shl v1.16b, v1.16b, #7 -; NONEON-NOSVE-NEXT: shl v0.16b, v0.16b, #7 -; NONEON-NOSVE-NEXT: cmlt v1.16b, v1.16b, #0 -; NONEON-NOSVE-NEXT: cmlt v0.16b, v0.16b, #0 -; NONEON-NOSVE-NEXT: and v1.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ext v3.16b, v1.16b, v1.16b, #8 -; NONEON-NOSVE-NEXT: ext v2.16b, v0.16b, v0.16b, #8 -; NONEON-NOSVE-NEXT: zip1 v1.16b, v1.16b, v3.16b -; NONEON-NOSVE-NEXT: zip1 v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: addv h1, v1.8h -; NONEON-NOSVE-NEXT: addv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w8, s1 -; NONEON-NOSVE-NEXT: fmov w9, s0 -; NONEON-NOSVE-NEXT: bfi w8, w9, #16, #16 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB3_33 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB3_34 -; NONEON-NOSVE-NEXT: .LBB3_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB3_35 -; NONEON-NOSVE-NEXT: .LBB3_3: // %else4 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB3_36 -; NONEON-NOSVE-NEXT: .LBB3_4: // %else6 -; NONEON-NOSVE-NEXT: tbnz w8, #4, .LBB3_37 -; NONEON-NOSVE-NEXT: .LBB3_5: // %else8 -; NONEON-NOSVE-NEXT: tbnz w8, #5, .LBB3_38 -; NONEON-NOSVE-NEXT: .LBB3_6: // %else10 -; NONEON-NOSVE-NEXT: tbnz w8, #6, .LBB3_39 -; NONEON-NOSVE-NEXT: .LBB3_7: // %else12 -; NONEON-NOSVE-NEXT: tbnz w8, #7, .LBB3_40 -; NONEON-NOSVE-NEXT: .LBB3_8: // %else14 -; NONEON-NOSVE-NEXT: tbnz w8, #8, .LBB3_41 -; NONEON-NOSVE-NEXT: .LBB3_9: // %else16 -; NONEON-NOSVE-NEXT: tbnz w8, #9, .LBB3_42 -; NONEON-NOSVE-NEXT: .LBB3_10: // %else18 -; NONEON-NOSVE-NEXT: tbnz w8, #10, .LBB3_43 -; NONEON-NOSVE-NEXT: .LBB3_11: // %else20 -; NONEON-NOSVE-NEXT: tbnz w8, #11, .LBB3_44 -; NONEON-NOSVE-NEXT: .LBB3_12: // %else22 -; NONEON-NOSVE-NEXT: tbnz w8, #12, .LBB3_45 -; NONEON-NOSVE-NEXT: .LBB3_13: // %else24 -; NONEON-NOSVE-NEXT: tbnz w8, #13, .LBB3_46 -; NONEON-NOSVE-NEXT: .LBB3_14: // %else26 -; NONEON-NOSVE-NEXT: tbnz w8, #14, .LBB3_47 -; NONEON-NOSVE-NEXT: .LBB3_15: // %else28 -; NONEON-NOSVE-NEXT: tbnz w8, #15, .LBB3_48 -; NONEON-NOSVE-NEXT: .LBB3_16: // %else30 -; NONEON-NOSVE-NEXT: tbnz w8, #16, .LBB3_49 -; NONEON-NOSVE-NEXT: .LBB3_17: // %else32 -; NONEON-NOSVE-NEXT: tbnz w8, #17, .LBB3_50 -; NONEON-NOSVE-NEXT: .LBB3_18: // %else34 -; NONEON-NOSVE-NEXT: tbnz w8, #18, .LBB3_51 -; NONEON-NOSVE-NEXT: .LBB3_19: // %else36 -; NONEON-NOSVE-NEXT: tbnz w8, #19, .LBB3_52 -; NONEON-NOSVE-NEXT: .LBB3_20: // %else38 -; NONEON-NOSVE-NEXT: tbnz w8, #20, .LBB3_53 -; NONEON-NOSVE-NEXT: .LBB3_21: // %else40 -; NONEON-NOSVE-NEXT: tbnz w8, #21, .LBB3_54 -; NONEON-NOSVE-NEXT: .LBB3_22: // %else42 -; NONEON-NOSVE-NEXT: tbnz w8, #22, .LBB3_55 -; NONEON-NOSVE-NEXT: .LBB3_23: // %else44 -; NONEON-NOSVE-NEXT: tbnz w8, #23, .LBB3_56 -; NONEON-NOSVE-NEXT: .LBB3_24: // %else46 -; NONEON-NOSVE-NEXT: tbnz w8, #24, .LBB3_57 -; NONEON-NOSVE-NEXT: .LBB3_25: // %else48 -; NONEON-NOSVE-NEXT: tbnz w8, #25, .LBB3_58 -; NONEON-NOSVE-NEXT: .LBB3_26: // %else50 -; NONEON-NOSVE-NEXT: tbnz w8, #26, .LBB3_59 -; NONEON-NOSVE-NEXT: .LBB3_27: // %else52 -; NONEON-NOSVE-NEXT: tbnz w8, #27, .LBB3_60 -; NONEON-NOSVE-NEXT: .LBB3_28: // %else54 -; NONEON-NOSVE-NEXT: tbnz w8, #28, .LBB3_61 -; NONEON-NOSVE-NEXT: .LBB3_29: // %else56 -; NONEON-NOSVE-NEXT: tbnz w8, #29, .LBB3_62 -; NONEON-NOSVE-NEXT: .LBB3_30: // %else58 -; NONEON-NOSVE-NEXT: tbnz w8, #30, .LBB3_63 -; NONEON-NOSVE-NEXT: .LBB3_31: // %else60 -; NONEON-NOSVE-NEXT: tbnz w8, #31, .LBB3_64 -; NONEON-NOSVE-NEXT: .LBB3_32: // %else62 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB3_33: // %cond.store -; NONEON-NOSVE-NEXT: strb wzr, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB3_2 -; NONEON-NOSVE-NEXT: .LBB3_34: // %cond.store1 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #1] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB3_3 -; NONEON-NOSVE-NEXT: .LBB3_35: // %cond.store3 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #2] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB3_4 -; NONEON-NOSVE-NEXT: .LBB3_36: // %cond.store5 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #3] -; NONEON-NOSVE-NEXT: tbz w8, #4, .LBB3_5 -; NONEON-NOSVE-NEXT: .LBB3_37: // %cond.store7 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #4] -; NONEON-NOSVE-NEXT: tbz w8, #5, .LBB3_6 -; NONEON-NOSVE-NEXT: .LBB3_38: // %cond.store9 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #5] -; NONEON-NOSVE-NEXT: tbz w8, #6, .LBB3_7 -; NONEON-NOSVE-NEXT: .LBB3_39: // %cond.store11 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #6] -; NONEON-NOSVE-NEXT: tbz w8, #7, .LBB3_8 -; NONEON-NOSVE-NEXT: .LBB3_40: // %cond.store13 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #7] -; NONEON-NOSVE-NEXT: tbz w8, #8, .LBB3_9 -; NONEON-NOSVE-NEXT: .LBB3_41: // %cond.store15 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #8] -; NONEON-NOSVE-NEXT: tbz w8, #9, .LBB3_10 -; NONEON-NOSVE-NEXT: .LBB3_42: // %cond.store17 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #9] -; NONEON-NOSVE-NEXT: tbz w8, #10, .LBB3_11 -; NONEON-NOSVE-NEXT: .LBB3_43: // %cond.store19 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #10] -; NONEON-NOSVE-NEXT: tbz w8, #11, .LBB3_12 -; NONEON-NOSVE-NEXT: .LBB3_44: // %cond.store21 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #11] -; NONEON-NOSVE-NEXT: tbz w8, #12, .LBB3_13 -; NONEON-NOSVE-NEXT: .LBB3_45: // %cond.store23 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #12] -; NONEON-NOSVE-NEXT: tbz w8, #13, .LBB3_14 -; NONEON-NOSVE-NEXT: .LBB3_46: // %cond.store25 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #13] -; NONEON-NOSVE-NEXT: tbz w8, #14, .LBB3_15 -; NONEON-NOSVE-NEXT: .LBB3_47: // %cond.store27 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #14] -; NONEON-NOSVE-NEXT: tbz w8, #15, .LBB3_16 -; NONEON-NOSVE-NEXT: .LBB3_48: // %cond.store29 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #15] -; NONEON-NOSVE-NEXT: tbz w8, #16, .LBB3_17 -; NONEON-NOSVE-NEXT: .LBB3_49: // %cond.store31 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #16] -; NONEON-NOSVE-NEXT: tbz w8, #17, .LBB3_18 -; NONEON-NOSVE-NEXT: .LBB3_50: // %cond.store33 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #17] -; NONEON-NOSVE-NEXT: tbz w8, #18, .LBB3_19 -; NONEON-NOSVE-NEXT: .LBB3_51: // %cond.store35 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #18] -; NONEON-NOSVE-NEXT: tbz w8, #19, .LBB3_20 -; NONEON-NOSVE-NEXT: .LBB3_52: // %cond.store37 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #19] -; NONEON-NOSVE-NEXT: tbz w8, #20, .LBB3_21 -; NONEON-NOSVE-NEXT: .LBB3_53: // %cond.store39 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #20] -; NONEON-NOSVE-NEXT: tbz w8, #21, .LBB3_22 -; NONEON-NOSVE-NEXT: .LBB3_54: // %cond.store41 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #21] -; NONEON-NOSVE-NEXT: tbz w8, #22, .LBB3_23 -; NONEON-NOSVE-NEXT: .LBB3_55: // %cond.store43 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #22] -; NONEON-NOSVE-NEXT: tbz w8, #23, .LBB3_24 -; NONEON-NOSVE-NEXT: .LBB3_56: // %cond.store45 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #23] -; NONEON-NOSVE-NEXT: tbz w8, #24, .LBB3_25 -; NONEON-NOSVE-NEXT: .LBB3_57: // %cond.store47 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #24] -; NONEON-NOSVE-NEXT: tbz w8, #25, .LBB3_26 -; NONEON-NOSVE-NEXT: .LBB3_58: // %cond.store49 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #25] -; NONEON-NOSVE-NEXT: tbz w8, #26, .LBB3_27 -; NONEON-NOSVE-NEXT: .LBB3_59: // %cond.store51 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #26] -; NONEON-NOSVE-NEXT: tbz w8, #27, .LBB3_28 -; NONEON-NOSVE-NEXT: .LBB3_60: // %cond.store53 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #27] -; NONEON-NOSVE-NEXT: tbz w8, #28, .LBB3_29 -; NONEON-NOSVE-NEXT: .LBB3_61: // %cond.store55 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #28] -; NONEON-NOSVE-NEXT: tbz w8, #29, .LBB3_30 -; NONEON-NOSVE-NEXT: .LBB3_62: // %cond.store57 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #29] -; NONEON-NOSVE-NEXT: tbz w8, #30, .LBB3_31 -; NONEON-NOSVE-NEXT: .LBB3_63: // %cond.store59 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #30] -; NONEON-NOSVE-NEXT: tbz w8, #31, .LBB3_32 -; NONEON-NOSVE-NEXT: .LBB3_64: // %cond.store61 -; NONEON-NOSVE-NEXT: strb wzr, [x0, #31] -; NONEON-NOSVE-NEXT: ret call void @llvm.masked.store.v32i8(<32 x i8> zeroinitializer, ptr %dst, i32 8, <32 x i1> %mask) ret void } @@ -568,29 +154,6 @@ define void @masked_store_v2f16(ptr %dst, <2 x i1> %mask) { ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_store_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #31 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI4_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI4_0] -; NONEON-NOSVE-NEXT: cmlt v0.2s, v0.2s, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addp v0.2s, v0.2s, v0.2s -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB4_3 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB4_4 -; NONEON-NOSVE-NEXT: .LBB4_2: // %else2 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB4_3: // %cond.store -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB4_2 -; NONEON-NOSVE-NEXT: .LBB4_4: // %cond.store1 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #2] -; NONEON-NOSVE-NEXT: ret call void @llvm.masked.store.v2f16(<2 x half> zeroinitializer, ptr %dst, i32 8, <2 x i1> %mask) ret void } @@ -606,41 +169,6 @@ define void @masked_store_v4f16(ptr %dst, <4 x i1> %mask) { ; CHECK-NEXT: mov z0.h, #0 // =0x0 ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_store_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #15 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI5_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI5_0] -; NONEON-NOSVE-NEXT: cmlt v0.4h, v0.4h, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addv h0, v0.4h -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB5_5 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB5_6 -; NONEON-NOSVE-NEXT: .LBB5_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB5_7 -; NONEON-NOSVE-NEXT: .LBB5_3: // %else4 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB5_8 -; NONEON-NOSVE-NEXT: .LBB5_4: // %else6 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB5_5: // %cond.store -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB5_2 -; NONEON-NOSVE-NEXT: .LBB5_6: // %cond.store1 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #2] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB5_3 -; NONEON-NOSVE-NEXT: .LBB5_7: // %cond.store3 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #4] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB5_4 -; NONEON-NOSVE-NEXT: .LBB5_8: // %cond.store5 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #6] -; NONEON-NOSVE-NEXT: ret call void @llvm.masked.store.v4f16(<4 x half> zeroinitializer, ptr %dst, i32 8, <4 x i1> %mask) ret void } @@ -657,65 +185,6 @@ define void @masked_store_v8f16(ptr %dst, <8 x i1> %mask) { ; CHECK-NEXT: mov z0.h, #0 // =0x0 ; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_store_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.8b, v0.8b, #7 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI6_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI6_0] -; NONEON-NOSVE-NEXT: cmlt v0.8b, v0.8b, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addv b0, v0.8b -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB6_9 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB6_10 -; NONEON-NOSVE-NEXT: .LBB6_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB6_11 -; NONEON-NOSVE-NEXT: .LBB6_3: // %else4 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB6_12 -; NONEON-NOSVE-NEXT: .LBB6_4: // %else6 -; NONEON-NOSVE-NEXT: tbnz w8, #4, .LBB6_13 -; NONEON-NOSVE-NEXT: .LBB6_5: // %else8 -; NONEON-NOSVE-NEXT: tbnz w8, #5, .LBB6_14 -; NONEON-NOSVE-NEXT: .LBB6_6: // %else10 -; NONEON-NOSVE-NEXT: tbnz w8, #6, .LBB6_15 -; NONEON-NOSVE-NEXT: .LBB6_7: // %else12 -; NONEON-NOSVE-NEXT: tbnz w8, #7, .LBB6_16 -; NONEON-NOSVE-NEXT: .LBB6_8: // %else14 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB6_9: // %cond.store -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB6_2 -; NONEON-NOSVE-NEXT: .LBB6_10: // %cond.store1 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #2] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB6_3 -; NONEON-NOSVE-NEXT: .LBB6_11: // %cond.store3 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #4] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB6_4 -; NONEON-NOSVE-NEXT: .LBB6_12: // %cond.store5 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #6] -; NONEON-NOSVE-NEXT: tbz w8, #4, .LBB6_5 -; NONEON-NOSVE-NEXT: .LBB6_13: // %cond.store7 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #8] -; NONEON-NOSVE-NEXT: tbz w8, #5, .LBB6_6 -; NONEON-NOSVE-NEXT: .LBB6_14: // %cond.store9 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #10] -; NONEON-NOSVE-NEXT: tbz w8, #6, .LBB6_7 -; NONEON-NOSVE-NEXT: .LBB6_15: // %cond.store11 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #12] -; NONEON-NOSVE-NEXT: tbz w8, #7, .LBB6_8 -; NONEON-NOSVE-NEXT: .LBB6_16: // %cond.store13 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #14] -; NONEON-NOSVE-NEXT: ret call void @llvm.masked.store.v8f16(<8 x half> zeroinitializer, ptr %dst, i32 8, <8 x i1> %mask) ret void } @@ -740,115 +209,6 @@ define void @masked_store_v16f16(ptr %dst, <16 x i1> %mask) { ; CHECK-NEXT: st1h { z1.h }, p1, [x0, x8, lsl #1] ; CHECK-NEXT: st1h { z1.h }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_store_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.16b, v0.16b, #7 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI7_0 -; NONEON-NOSVE-NEXT: ldr q1, [x8, :lo12:.LCPI7_0] -; NONEON-NOSVE-NEXT: cmlt v0.16b, v0.16b, #0 -; NONEON-NOSVE-NEXT: and v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; NONEON-NOSVE-NEXT: zip1 v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: addv h0, v0.8h -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB7_17 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB7_18 -; NONEON-NOSVE-NEXT: .LBB7_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB7_19 -; NONEON-NOSVE-NEXT: .LBB7_3: // %else4 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB7_20 -; NONEON-NOSVE-NEXT: .LBB7_4: // %else6 -; NONEON-NOSVE-NEXT: tbnz w8, #4, .LBB7_21 -; NONEON-NOSVE-NEXT: .LBB7_5: // %else8 -; NONEON-NOSVE-NEXT: tbnz w8, #5, .LBB7_22 -; NONEON-NOSVE-NEXT: .LBB7_6: // %else10 -; NONEON-NOSVE-NEXT: tbnz w8, #6, .LBB7_23 -; NONEON-NOSVE-NEXT: .LBB7_7: // %else12 -; NONEON-NOSVE-NEXT: tbnz w8, #7, .LBB7_24 -; NONEON-NOSVE-NEXT: .LBB7_8: // %else14 -; NONEON-NOSVE-NEXT: tbnz w8, #8, .LBB7_25 -; NONEON-NOSVE-NEXT: .LBB7_9: // %else16 -; NONEON-NOSVE-NEXT: tbnz w8, #9, .LBB7_26 -; NONEON-NOSVE-NEXT: .LBB7_10: // %else18 -; NONEON-NOSVE-NEXT: tbnz w8, #10, .LBB7_27 -; NONEON-NOSVE-NEXT: .LBB7_11: // %else20 -; NONEON-NOSVE-NEXT: tbnz w8, #11, .LBB7_28 -; NONEON-NOSVE-NEXT: .LBB7_12: // %else22 -; NONEON-NOSVE-NEXT: tbnz w8, #12, .LBB7_29 -; NONEON-NOSVE-NEXT: .LBB7_13: // %else24 -; NONEON-NOSVE-NEXT: tbnz w8, #13, .LBB7_30 -; NONEON-NOSVE-NEXT: .LBB7_14: // %else26 -; NONEON-NOSVE-NEXT: tbnz w8, #14, .LBB7_31 -; NONEON-NOSVE-NEXT: .LBB7_15: // %else28 -; NONEON-NOSVE-NEXT: tbnz w8, #15, .LBB7_32 -; NONEON-NOSVE-NEXT: .LBB7_16: // %else30 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB7_17: // %cond.store -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB7_2 -; NONEON-NOSVE-NEXT: .LBB7_18: // %cond.store1 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #2] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB7_3 -; NONEON-NOSVE-NEXT: .LBB7_19: // %cond.store3 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #4] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB7_4 -; NONEON-NOSVE-NEXT: .LBB7_20: // %cond.store5 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #6] -; NONEON-NOSVE-NEXT: tbz w8, #4, .LBB7_5 -; NONEON-NOSVE-NEXT: .LBB7_21: // %cond.store7 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #8] -; NONEON-NOSVE-NEXT: tbz w8, #5, .LBB7_6 -; NONEON-NOSVE-NEXT: .LBB7_22: // %cond.store9 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #10] -; NONEON-NOSVE-NEXT: tbz w8, #6, .LBB7_7 -; NONEON-NOSVE-NEXT: .LBB7_23: // %cond.store11 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #12] -; NONEON-NOSVE-NEXT: tbz w8, #7, .LBB7_8 -; NONEON-NOSVE-NEXT: .LBB7_24: // %cond.store13 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #14] -; NONEON-NOSVE-NEXT: tbz w8, #8, .LBB7_9 -; NONEON-NOSVE-NEXT: .LBB7_25: // %cond.store15 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #16] -; NONEON-NOSVE-NEXT: tbz w8, #9, .LBB7_10 -; NONEON-NOSVE-NEXT: .LBB7_26: // %cond.store17 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #18] -; NONEON-NOSVE-NEXT: tbz w8, #10, .LBB7_11 -; NONEON-NOSVE-NEXT: .LBB7_27: // %cond.store19 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #20] -; NONEON-NOSVE-NEXT: tbz w8, #11, .LBB7_12 -; NONEON-NOSVE-NEXT: .LBB7_28: // %cond.store21 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #22] -; NONEON-NOSVE-NEXT: tbz w8, #12, .LBB7_13 -; NONEON-NOSVE-NEXT: .LBB7_29: // %cond.store23 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #24] -; NONEON-NOSVE-NEXT: tbz w8, #13, .LBB7_14 -; NONEON-NOSVE-NEXT: .LBB7_30: // %cond.store25 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #26] -; NONEON-NOSVE-NEXT: tbz w8, #14, .LBB7_15 -; NONEON-NOSVE-NEXT: .LBB7_31: // %cond.store27 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #28] -; NONEON-NOSVE-NEXT: tbz w8, #15, .LBB7_16 -; NONEON-NOSVE-NEXT: .LBB7_32: // %cond.store29 -; NONEON-NOSVE-NEXT: fmov s0, wzr -; NONEON-NOSVE-NEXT: str h0, [x0, #30] -; NONEON-NOSVE-NEXT: ret call void @llvm.masked.store.v16f16(<16 x half> zeroinitializer, ptr %dst, i32 8, <16 x i1> %mask) ret void } @@ -865,37 +225,6 @@ define void @masked_store_v4f32(ptr %dst, <4 x i1> %mask) { ; CHECK-NEXT: mov z0.s, #0 // =0x0 ; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_store_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #15 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI8_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI8_0] -; NONEON-NOSVE-NEXT: cmlt v0.4h, v0.4h, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addv h0, v0.4h -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB8_5 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB8_6 -; NONEON-NOSVE-NEXT: .LBB8_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB8_7 -; NONEON-NOSVE-NEXT: .LBB8_3: // %else4 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB8_8 -; NONEON-NOSVE-NEXT: .LBB8_4: // %else6 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB8_5: // %cond.store -; NONEON-NOSVE-NEXT: str wzr, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB8_2 -; NONEON-NOSVE-NEXT: .LBB8_6: // %cond.store1 -; NONEON-NOSVE-NEXT: str wzr, [x0, #4] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB8_3 -; NONEON-NOSVE-NEXT: .LBB8_7: // %cond.store3 -; NONEON-NOSVE-NEXT: str wzr, [x0, #8] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB8_4 -; NONEON-NOSVE-NEXT: .LBB8_8: // %cond.store5 -; NONEON-NOSVE-NEXT: str wzr, [x0, #12] -; NONEON-NOSVE-NEXT: ret call void @llvm.masked.store.v4f32(<4 x float> zeroinitializer, ptr %dst, i32 8, <4 x i1> %mask) ret void } @@ -946,57 +275,6 @@ define void @masked_store_v8f32(ptr %dst, <8 x i1> %mask) { ; CHECK-NEXT: st1w { z1.s }, p0, [x0] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_store_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.8b, v0.8b, #7 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI9_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI9_0] -; NONEON-NOSVE-NEXT: cmlt v0.8b, v0.8b, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addv b0, v0.8b -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB9_9 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB9_10 -; NONEON-NOSVE-NEXT: .LBB9_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB9_11 -; NONEON-NOSVE-NEXT: .LBB9_3: // %else4 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB9_12 -; NONEON-NOSVE-NEXT: .LBB9_4: // %else6 -; NONEON-NOSVE-NEXT: tbnz w8, #4, .LBB9_13 -; NONEON-NOSVE-NEXT: .LBB9_5: // %else8 -; NONEON-NOSVE-NEXT: tbnz w8, #5, .LBB9_14 -; NONEON-NOSVE-NEXT: .LBB9_6: // %else10 -; NONEON-NOSVE-NEXT: tbnz w8, #6, .LBB9_15 -; NONEON-NOSVE-NEXT: .LBB9_7: // %else12 -; NONEON-NOSVE-NEXT: tbnz w8, #7, .LBB9_16 -; NONEON-NOSVE-NEXT: .LBB9_8: // %else14 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB9_9: // %cond.store -; NONEON-NOSVE-NEXT: str wzr, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB9_2 -; NONEON-NOSVE-NEXT: .LBB9_10: // %cond.store1 -; NONEON-NOSVE-NEXT: str wzr, [x0, #4] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB9_3 -; NONEON-NOSVE-NEXT: .LBB9_11: // %cond.store3 -; NONEON-NOSVE-NEXT: str wzr, [x0, #8] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB9_4 -; NONEON-NOSVE-NEXT: .LBB9_12: // %cond.store5 -; NONEON-NOSVE-NEXT: str wzr, [x0, #12] -; NONEON-NOSVE-NEXT: tbz w8, #4, .LBB9_5 -; NONEON-NOSVE-NEXT: .LBB9_13: // %cond.store7 -; NONEON-NOSVE-NEXT: str wzr, [x0, #16] -; NONEON-NOSVE-NEXT: tbz w8, #5, .LBB9_6 -; NONEON-NOSVE-NEXT: .LBB9_14: // %cond.store9 -; NONEON-NOSVE-NEXT: str wzr, [x0, #20] -; NONEON-NOSVE-NEXT: tbz w8, #6, .LBB9_7 -; NONEON-NOSVE-NEXT: .LBB9_15: // %cond.store11 -; NONEON-NOSVE-NEXT: str wzr, [x0, #24] -; NONEON-NOSVE-NEXT: tbz w8, #7, .LBB9_8 -; NONEON-NOSVE-NEXT: .LBB9_16: // %cond.store13 -; NONEON-NOSVE-NEXT: str wzr, [x0, #28] -; NONEON-NOSVE-NEXT: ret call void @llvm.masked.store.v8f32(<8 x float> zeroinitializer, ptr %dst, i32 8, <8 x i1> %mask) ret void } @@ -1013,27 +291,6 @@ define void @masked_store_v2f64(ptr %dst, <2 x i1> %mask) { ; CHECK-NEXT: mov z0.d, #0 // =0x0 ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_store_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #31 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI10_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI10_0] -; NONEON-NOSVE-NEXT: cmlt v0.2s, v0.2s, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addp v0.2s, v0.2s, v0.2s -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB10_3 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB10_4 -; NONEON-NOSVE-NEXT: .LBB10_2: // %else2 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB10_3: // %cond.store -; NONEON-NOSVE-NEXT: str xzr, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB10_2 -; NONEON-NOSVE-NEXT: .LBB10_4: // %cond.store1 -; NONEON-NOSVE-NEXT: str xzr, [x0, #8] -; NONEON-NOSVE-NEXT: ret call void @llvm.masked.store.v2f64(<2 x double> zeroinitializer, ptr %dst, i32 8, <2 x i1> %mask) ret void } @@ -1058,37 +315,6 @@ define void @masked_store_v4f64(ptr %dst, <4 x i1> %mask) { ; CHECK-NEXT: st1d { z0.d }, p1, [x0, x8, lsl #3] ; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: masked_store_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #15 -; NONEON-NOSVE-NEXT: adrp x8, .LCPI11_0 -; NONEON-NOSVE-NEXT: ldr d1, [x8, :lo12:.LCPI11_0] -; NONEON-NOSVE-NEXT: cmlt v0.4h, v0.4h, #0 -; NONEON-NOSVE-NEXT: and v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: addv h0, v0.4h -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB11_5 -; NONEON-NOSVE-NEXT: // %bb.1: // %else -; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB11_6 -; NONEON-NOSVE-NEXT: .LBB11_2: // %else2 -; NONEON-NOSVE-NEXT: tbnz w8, #2, .LBB11_7 -; NONEON-NOSVE-NEXT: .LBB11_3: // %else4 -; NONEON-NOSVE-NEXT: tbnz w8, #3, .LBB11_8 -; NONEON-NOSVE-NEXT: .LBB11_4: // %else6 -; NONEON-NOSVE-NEXT: ret -; NONEON-NOSVE-NEXT: .LBB11_5: // %cond.store -; NONEON-NOSVE-NEXT: str xzr, [x0] -; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB11_2 -; NONEON-NOSVE-NEXT: .LBB11_6: // %cond.store1 -; NONEON-NOSVE-NEXT: str xzr, [x0, #8] -; NONEON-NOSVE-NEXT: tbz w8, #2, .LBB11_3 -; NONEON-NOSVE-NEXT: .LBB11_7: // %cond.store3 -; NONEON-NOSVE-NEXT: str xzr, [x0, #16] -; NONEON-NOSVE-NEXT: tbz w8, #3, .LBB11_4 -; NONEON-NOSVE-NEXT: .LBB11_8: // %cond.store5 -; NONEON-NOSVE-NEXT: str xzr, [x0, #24] -; NONEON-NOSVE-NEXT: ret call void @llvm.masked.store.v4f64(<4 x double> zeroinitializer, ptr %dst, i32 8, <4 x i1> %mask) ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll index d7eaf766e7df..b5adea594242 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -15,15 +14,6 @@ define void @add_v4i8(ptr %a, ptr %b) { ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: st1b { z0.h }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr s0, [x0] -; NONEON-NOSVE-NEXT: ldr s1, [x1] -; NONEON-NOSVE-NEXT: uaddl v0.8h, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: uzp1 v0.8b, v0.8b, v0.8b -; NONEON-NOSVE-NEXT: str s0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i8>, ptr %a %op2 = load <4 x i8>, ptr %b %res = add <4 x i8> %op1, %op2 @@ -39,14 +29,6 @@ define void @add_v8i8(ptr %a, ptr %b) { ; CHECK-NEXT: add z0.b, z0.b, z1.b ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ldr d1, [x1] -; NONEON-NOSVE-NEXT: add v0.8b, v0.8b, v1.8b -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i8>, ptr %a %op2 = load <8 x i8>, ptr %b %res = add <8 x i8> %op1, %op2 @@ -62,14 +44,6 @@ define void @add_v16i8(ptr %a, ptr %b) { ; CHECK-NEXT: add z0.b, z0.b, z1.b ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i8>, ptr %a %op2 = load <16 x i8>, ptr %b %res = add <16 x i8> %op1, %op2 @@ -86,15 +60,6 @@ define void @add_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: add z1.b, z2.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: add v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %res = add <32 x i8> %op1, %op2 @@ -111,23 +76,6 @@ define void @add_v2i16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: add z0.s, z0.s, z1.s ; CHECK-NEXT: st1h { z0.s }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldrh w8, [x0] -; NONEON-NOSVE-NEXT: ldrh w9, [x1] -; NONEON-NOSVE-NEXT: fmov s0, w8 -; NONEON-NOSVE-NEXT: fmov s1, w9 -; NONEON-NOSVE-NEXT: add x8, x0, #2 -; NONEON-NOSVE-NEXT: add x9, x1, #2 -; NONEON-NOSVE-NEXT: ld1 { v0.h }[2], [x8] -; NONEON-NOSVE-NEXT: ld1 { v1.h }[2], [x9] -; NONEON-NOSVE-NEXT: add v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: mov w8, v0.s[1] -; NONEON-NOSVE-NEXT: fmov w9, s0 -; NONEON-NOSVE-NEXT: strh w9, [x0] -; NONEON-NOSVE-NEXT: strh w8, [x0, #2] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x i16>, ptr %a %op2 = load <2 x i16>, ptr %b %res = add <2 x i16> %op1, %op2 @@ -143,14 +91,6 @@ define void @add_v4i16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ldr d1, [x1] -; NONEON-NOSVE-NEXT: add v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i16>, ptr %a %op2 = load <4 x i16>, ptr %b %res = add <4 x i16> %op1, %op2 @@ -166,14 +106,6 @@ define void @add_v8i16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i16>, ptr %a %op2 = load <8 x i16>, ptr %b %res = add <8 x i16> %op1, %op2 @@ -190,15 +122,6 @@ define void @add_v16i16(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: add z1.h, z2.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: add_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: add v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: add v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %res = add <16 x i16> %op1, %op2 @@ -214,13 +137,6 @@ define void @abs_v2i32(ptr %a) { ; CHECK-NEXT: abs z0.s, p0/m, z0.s ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: abs v0.2s, v0.2s -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x i32>, ptr %a %res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %op1, i1 false) store <2 x i32> %res, ptr %a @@ -235,13 +151,6 @@ define void @abs_v4i32(ptr %a) { ; CHECK-NEXT: abs z0.s, p0/m, z0.s ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: abs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i32>, ptr %a %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %op1, i1 false) store <4 x i32> %res, ptr %a @@ -257,14 +166,6 @@ define void @abs_v8i32(ptr %a) { ; CHECK-NEXT: abs z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: abs v0.4s, v0.4s -; NONEON-NOSVE-NEXT: abs v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %op1, i1 false) store <8 x i32> %res, ptr %a @@ -279,13 +180,6 @@ define void @abs_v2i64(ptr %a) { ; CHECK-NEXT: abs z0.d, p0/m, z0.d ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: abs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x i64>, ptr %a %res = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %op1, i1 false) store <2 x i64> %res, ptr %a @@ -301,14 +195,6 @@ define void @abs_v4i64(ptr %a) { ; CHECK-NEXT: abs z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: abs_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: abs v0.2d, v0.2d -; NONEON-NOSVE-NEXT: abs v1.2d, v1.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %op1, i1 false) store <4 x i64> %res, ptr %a @@ -325,17 +211,6 @@ define void @fadd_v2f16(ptr %a, ptr %b) { ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: str w8, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr s0, [x0] -; NONEON-NOSVE-NEXT: ldr s1, [x1] -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: str s0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x half>, ptr %a %op2 = load <2 x half>, ptr %b %res = fadd <2 x half> %op1, %op2 @@ -352,17 +227,6 @@ define void @fadd_v4f16(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ldr d1, [x1] -; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h -; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x half>, ptr %a %op2 = load <4 x half>, ptr %b %res = fadd <4 x half> %op1, %op2 @@ -379,21 +243,6 @@ define void @fadd_v8f16(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fcvtl v2.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v3.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fadd v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fcvtn v1.4h, v2.4s -; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v0.4s -; NONEON-NOSVE-NEXT: str q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x half>, ptr %a %op2 = load <8 x half>, ptr %b %res = fadd <8 x half> %op1, %op2 @@ -412,29 +261,6 @@ define void @fadd_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fcvtl v4.4s, v0.4h -; NONEON-NOSVE-NEXT: fcvtl v6.4s, v3.4h -; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h -; NONEON-NOSVE-NEXT: fcvtl v5.4s, v1.4h -; NONEON-NOSVE-NEXT: fcvtl v7.4s, v2.4h -; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h -; NONEON-NOSVE-NEXT: fcvtl2 v3.4s, v3.8h -; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v2.8h -; NONEON-NOSVE-NEXT: fadd v4.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: fadd v5.4s, v7.4s, v6.4s -; NONEON-NOSVE-NEXT: fadd v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fadd v2.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: fcvtn v1.4h, v4.4s -; NONEON-NOSVE-NEXT: fcvtn v3.4h, v5.4s -; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v0.4s -; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v2.4s -; NONEON-NOSVE-NEXT: stp q1, q3, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %res = fadd <16 x half> %op1, %op2 @@ -451,14 +277,6 @@ define void @fadd_v2f32(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ldr d1, [x1] -; NONEON-NOSVE-NEXT: fadd v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x float>, ptr %a %op2 = load <2 x float>, ptr %b %res = fadd <2 x float> %op1, %op2 @@ -475,14 +293,6 @@ define void @fadd_v4f32(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x float>, ptr %a %op2 = load <4 x float>, ptr %b %res = fadd <4 x float> %op1, %op2 @@ -501,15 +311,6 @@ define void @fadd_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fadd v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: fadd v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %res = fadd <8 x float> %op1, %op2 @@ -526,14 +327,6 @@ define void @fadd_v2f64(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: fadd v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <2 x double>, ptr %a %op2 = load <2 x double>, ptr %b %res = fadd <2 x double> %op1, %op2 @@ -552,15 +345,6 @@ define void @fadd_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fadd_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NONEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NONEON-NOSVE-NEXT: fadd v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: fadd v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %res = fadd <4 x double> %op1, %op2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll index f595a4219cac..00413302798c 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -16,14 +15,6 @@ define void @test_revbv16i16(ptr %a) { ; CHECK-NEXT: revb z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revbv16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev16 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rev16 v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <32 x i8>, ptr %a %tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> store <32 x i8> %tmp2, ptr %a @@ -40,14 +31,6 @@ define void @test_revbv8i32(ptr %a) { ; CHECK-NEXT: revb z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revbv8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev32 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rev32 v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <32 x i8>, ptr %a %tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> store <32 x i8> %tmp2, ptr %a @@ -64,14 +47,6 @@ define void @test_revbv4i64(ptr %a) { ; CHECK-NEXT: revb z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revbv4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev64 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rev64 v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <32 x i8>, ptr %a %tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> store <32 x i8> %tmp2, ptr %a @@ -88,14 +63,6 @@ define void @test_revhv8i32(ptr %a) { ; CHECK-NEXT: revh z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revhv8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev32 v0.8h, v0.8h -; NONEON-NOSVE-NEXT: rev32 v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <16 x i16>, ptr %a %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> store <16 x i16> %tmp2, ptr %a @@ -112,14 +79,6 @@ define void @test_revhv8f32(ptr %a) { ; CHECK-NEXT: revh z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revhv8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev32 v0.8h, v0.8h -; NONEON-NOSVE-NEXT: rev32 v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <16 x half>, ptr %a %tmp2 = shufflevector <16 x half> %tmp1, <16 x half> undef, <16 x i32> store <16 x half> %tmp2, ptr %a @@ -136,14 +95,6 @@ define void @test_revhv4i64(ptr %a) { ; CHECK-NEXT: revh z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revhv4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev64 v0.8h, v0.8h -; NONEON-NOSVE-NEXT: rev64 v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <16 x i16>, ptr %a %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> store <16 x i16> %tmp2, ptr %a @@ -160,14 +111,6 @@ define void @test_revwv4i64(ptr %a) { ; CHECK-NEXT: revw z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revwv4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev64 v0.4s, v0.4s -; NONEON-NOSVE-NEXT: rev64 v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <8 x i32>, ptr %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> store <8 x i32> %tmp2, ptr %a @@ -184,14 +127,6 @@ define void @test_revwv4f64(ptr %a) { ; CHECK-NEXT: revw z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revwv4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev64 v0.4s, v0.4s -; NONEON-NOSVE-NEXT: rev64 v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <8 x float>, ptr %a %tmp2 = shufflevector <8 x float> %tmp1, <8 x float> undef, <8 x i32> store <8 x float> %tmp2, ptr %a @@ -206,12 +141,6 @@ define <16 x i8> @test_revv16i8(ptr %a) { ; CHECK-NEXT: revb z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revv16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: rev64 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %tmp1 = load <16 x i8>, ptr %a %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> ret <16 x i8> %tmp2 @@ -227,14 +156,6 @@ define void @test_revwv8i32v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: revw z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revwv8i32v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x1] -; NONEON-NOSVE-NEXT: rev64 v0.4s, v0.4s -; NONEON-NOSVE-NEXT: rev64 v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <8 x i32>, ptr %a %tmp2 = load <8 x i32>, ptr %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> @@ -255,18 +176,6 @@ define void @test_revhv32i16(ptr %a) { ; CHECK-NEXT: stp q0, q1, [x0, #32] ; CHECK-NEXT: stp q2, q3, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revhv32i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: rev64 v0.8h, v0.8h -; NONEON-NOSVE-NEXT: rev64 v1.8h, v1.8h -; NONEON-NOSVE-NEXT: rev64 v2.8h, v2.8h -; NONEON-NOSVE-NEXT: rev64 v3.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0, #32] -; NONEON-NOSVE-NEXT: stp q2, q3, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <32 x i16>, ptr %a %tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <32 x i32> store <32 x i16> %tmp2, ptr %a @@ -282,14 +191,6 @@ define void @test_rev_elts_fail(ptr %a) { ; CHECK-NEXT: tbl z0.d, { z2.d }, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_rev_elts_fail: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v0.16b, #8 -; NONEON-NOSVE-NEXT: ext v1.16b, v1.16b, v1.16b, #8 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <4 x i64>, ptr %a %tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> store <4 x i64> %tmp2, ptr %a @@ -307,15 +208,6 @@ define void @test_revdv4i64_sve2p1(ptr %a) #1 { ; CHECK-NEXT: revd z1.q, p0/m, z1.q ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revdv4i64_sve2p1: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ptrue p0.d, vl2 -; NONEON-NOSVE-NEXT: revd z0.q, p0/m, z0.q -; NONEON-NOSVE-NEXT: revd z1.q, p0/m, z1.q -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <4 x i64>, ptr %a %tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> store <4 x i64> %tmp2, ptr %a @@ -331,15 +223,6 @@ define void @test_revdv4f64_sve2p1(ptr %a) #1 { ; CHECK-NEXT: revd z1.q, p0/m, z1.q ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revdv4f64_sve2p1: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ptrue p0.d -; NONEON-NOSVE-NEXT: revd z0.q, p0/m, z0.q -; NONEON-NOSVE-NEXT: revd z1.q, p0/m, z1.q -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <4 x double>, ptr %a %tmp2 = shufflevector <4 x double> %tmp1, <4 x double> undef, <4 x i32> store <4 x double> %tmp2, ptr %a @@ -355,16 +238,6 @@ define void @test_revv8i32(ptr %a) { ; CHECK-NEXT: tbl z0.s, { z2.s }, z0.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_revv8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: rev64 v0.4s, v0.4s -; NONEON-NOSVE-NEXT: rev64 v1.4s, v1.4s -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v0.16b, #8 -; NONEON-NOSVE-NEXT: ext v1.16b, v1.16b, v1.16b, #8 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <8 x i32>, ptr %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> store <8 x i32> %tmp2, ptr %a diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll index df786933da88..cb73030306b0 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -69,18 +68,6 @@ define void @zip1_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: str q1, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zip1_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: zip2 v2.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: zip1 v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: str q2, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load volatile <32 x i8>, ptr %a %tmp2 = load volatile <32 x i8>, ptr %b %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> @@ -209,28 +196,6 @@ define void @zip_v32i16(ptr %a, ptr %b) { ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zip_v32i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q4, q0, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q5, q1, [x0] -; NONEON-NOSVE-NEXT: ldp q6, q2, [x1, #32] -; NONEON-NOSVE-NEXT: ldp q7, q3, [x1] -; NONEON-NOSVE-NEXT: zip1 v17.8h, v0.8h, v2.8h -; NONEON-NOSVE-NEXT: zip2 v0.8h, v0.8h, v2.8h -; NONEON-NOSVE-NEXT: zip1 v16.8h, v1.8h, v3.8h -; NONEON-NOSVE-NEXT: zip2 v1.8h, v1.8h, v3.8h -; NONEON-NOSVE-NEXT: zip1 v2.8h, v5.8h, v7.8h -; NONEON-NOSVE-NEXT: zip1 v3.8h, v4.8h, v6.8h -; NONEON-NOSVE-NEXT: zip2 v5.8h, v5.8h, v7.8h -; NONEON-NOSVE-NEXT: zip2 v4.8h, v4.8h, v6.8h -; NONEON-NOSVE-NEXT: add v6.8h, v16.8h, v17.8h -; NONEON-NOSVE-NEXT: add v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: add v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: add v2.8h, v5.8h, v4.8h -; NONEON-NOSVE-NEXT: stp q6, q0, [x0, #32] -; NONEON-NOSVE-NEXT: stp q1, q2, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <32 x i16>, ptr %a %tmp2 = load <32 x i16>, ptr %b %tmp3 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> @@ -279,18 +244,6 @@ define void @zip1_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: str q1, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zip1_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: zip2 v2.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: zip1 v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: str q2, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load volatile <16 x i16>, ptr %a %tmp2 = load volatile <16 x i16>, ptr %b %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> @@ -323,18 +276,6 @@ define void @zip1_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: str q1, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zip1_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: zip2 v2.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: zip1 v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: str q2, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load volatile <8 x i32>, ptr %a %tmp2 = load volatile <8 x i32>, ptr %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> @@ -357,19 +298,6 @@ define void @zip_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zip_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x1] -; NONEON-NOSVE-NEXT: zip1 v4.2d, v1.2d, v3.2d -; NONEON-NOSVE-NEXT: zip1 v5.2d, v0.2d, v2.2d -; NONEON-NOSVE-NEXT: zip2 v1.2d, v1.2d, v3.2d -; NONEON-NOSVE-NEXT: zip2 v0.2d, v0.2d, v2.2d -; NONEON-NOSVE-NEXT: fadd v2.2d, v4.2d, v5.2d -; NONEON-NOSVE-NEXT: fadd v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: stp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <4 x double>, ptr %a %tmp2 = load <4 x double>, ptr %b %tmp3 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> @@ -402,16 +330,6 @@ define void @zip_v4i32(ptr %a, ptr %b) { ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zip_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: zip1 v2.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: zip2 v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: add v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <4 x i32>, ptr %a %tmp2 = load <4 x i32>, ptr %b %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> @@ -433,16 +351,6 @@ define void @zip1_v8i32_undef(ptr %a) { ; CHECK-NEXT: str q1, [x0, #16] ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zip1_v8i32_undef: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: zip2 v1.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: zip1 v0.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: str q1, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load volatile <8 x i32>, ptr %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> store volatile <8 x i32> %tmp2, ptr %a @@ -462,19 +370,6 @@ define void @trn_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: add z1.b, z1.b, z2.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trn_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x1] -; NONEON-NOSVE-NEXT: trn1 v4.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: trn2 v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: trn1 v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: trn2 v2.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: add v0.16b, v4.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <32 x i8>, ptr %a %tmp2 = load <32 x i8>, ptr %b %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> @@ -497,19 +392,6 @@ define void @trn_v8i16(ptr %a, ptr %b) { ; CHECK-NEXT: add z0.h, z1.h, z0.h ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trn_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: adrp x8, .LCPI8_0 -; NONEON-NOSVE-NEXT: adrp x9, .LCPI8_1 -; NONEON-NOSVE-NEXT: ldr q1, [x0] -; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI8_0] -; NONEON-NOSVE-NEXT: ldr q2, [x9, :lo12:.LCPI8_1] -; NONEON-NOSVE-NEXT: tbl v0.16b, { v1.16b }, v0.16b -; NONEON-NOSVE-NEXT: tbl v1.16b, { v1.16b }, v2.16b -; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <8 x i16>, ptr %a %tmp2 = load <8 x i16>, ptr %b %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> @@ -532,19 +414,6 @@ define void @trn_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: add z1.h, z1.h, z2.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trn_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x1] -; NONEON-NOSVE-NEXT: trn1 v4.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: trn2 v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: trn1 v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: trn2 v2.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: add v0.8h, v4.8h, v0.8h -; NONEON-NOSVE-NEXT: add v1.8h, v1.8h, v2.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <16 x i16>, ptr %a %tmp2 = load <16 x i16>, ptr %b %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> @@ -567,19 +436,6 @@ define void @trn_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: add z1.s, z1.s, z2.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trn_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x1] -; NONEON-NOSVE-NEXT: zip1 v4.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: trn2 v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: trn1 v1.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: trn2 v2.4s, v2.4s, v3.4s -; NONEON-NOSVE-NEXT: add v0.4s, v4.4s, v0.4s -; NONEON-NOSVE-NEXT: add v1.4s, v1.4s, v2.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <8 x i32>, ptr %a %tmp2 = load <8 x i32>, ptr %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> @@ -603,19 +459,6 @@ define void @trn_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z1.d, p0/m, z1.d, z2.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trn_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q1, q3, [x1] -; NONEON-NOSVE-NEXT: zip1 v4.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: zip2 v0.2d, v0.2d, v1.2d -; NONEON-NOSVE-NEXT: zip1 v1.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: zip2 v2.2d, v2.2d, v3.2d -; NONEON-NOSVE-NEXT: fadd v0.2d, v4.2d, v0.2d -; NONEON-NOSVE-NEXT: fadd v1.2d, v1.2d, v2.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <4 x double>, ptr %a %tmp2 = load <4 x double>, ptr %b %tmp3 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> @@ -636,16 +479,6 @@ define void @trn_v4f32(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z2.s ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trn_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: trn1 v2.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: trn2 v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: fadd v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <4 x float>, ptr %a %tmp2 = load <4 x float>, ptr %b %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> @@ -667,18 +500,6 @@ define void @trn_v8i32_undef(ptr %a) { ; CHECK-NEXT: add z1.s, z3.s, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trn_v8i32_undef: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: trn1 v2.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: trn2 v0.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: trn1 v3.4s, v1.4s, v1.4s -; NONEON-NOSVE-NEXT: trn2 v1.4s, v1.4s, v1.4s -; NONEON-NOSVE-NEXT: add v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: add v1.4s, v3.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <8 x i32>, ptr %a %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> %tmp4 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> @@ -750,18 +571,6 @@ define void @zip2_v32i8(ptr %a, ptr %b) #0{ ; CHECK-NEXT: str q1, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zip2_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: zip2 v2.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: zip1 v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: str q2, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load volatile <32 x i8>, ptr %a %tmp2 = load volatile <32 x i8>, ptr %b %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> @@ -808,18 +617,6 @@ define void @zip2_v16i16(ptr %a, ptr %b) #0{ ; CHECK-NEXT: str q1, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zip2_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: zip2 v2.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: zip1 v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: str q2, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load volatile <16 x i16>, ptr %a %tmp2 = load volatile <16 x i16>, ptr %b %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> @@ -852,18 +649,6 @@ define void @zip2_v8i32(ptr %a, ptr %b) #0{ ; CHECK-NEXT: str q1, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zip2_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: zip2 v2.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: zip1 v0.4s, v0.4s, v1.4s -; NONEON-NOSVE-NEXT: str q2, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load volatile <8 x i32>, ptr %a %tmp2 = load volatile <8 x i32>, ptr %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> @@ -883,16 +668,6 @@ define void @zip2_v8i32_undef(ptr %a) #0{ ; CHECK-NEXT: str q1, [x0, #16] ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zip2_v8i32_undef: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: zip2 v1.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: zip1 v0.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: str q1, [x0, #16] -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load volatile <8 x i32>, ptr %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> store volatile <8 x i32> %tmp2, ptr %a @@ -1094,19 +869,6 @@ define void @uzp_v32i8(ptr %a, ptr %b) #0{ ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uzp_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x1] -; NONEON-NOSVE-NEXT: uzp1 v4.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: uzp2 v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: uzp1 v1.16b, v3.16b, v2.16b -; NONEON-NOSVE-NEXT: uzp2 v2.16b, v3.16b, v2.16b -; NONEON-NOSVE-NEXT: add v0.16b, v4.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v2.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <32 x i8>, ptr %a %tmp2 = load <32 x i8>, ptr %b %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> @@ -1129,17 +891,6 @@ define void @uzp_v4i16(ptr %a, ptr %b) #0{ ; CHECK-NEXT: add z0.h, z1.h, z0.h ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uzp_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: ext v1.8b, v0.8b, v0.8b, #6 -; NONEON-NOSVE-NEXT: ext v2.8b, v0.8b, v0.8b, #2 -; NONEON-NOSVE-NEXT: trn1 v1.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: zip1 v0.4h, v2.4h, v0.4h -; NONEON-NOSVE-NEXT: add v0.4h, v1.4h, v0.4h -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <4 x i16>, ptr %a %tmp2 = load <4 x i16>, ptr %b %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> @@ -1257,19 +1008,6 @@ define void @uzp_v16i16(ptr %a, ptr %b) #0{ ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uzp_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x1] -; NONEON-NOSVE-NEXT: uzp1 v4.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: uzp2 v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v3.8h, v2.8h -; NONEON-NOSVE-NEXT: uzp2 v2.8h, v3.8h, v2.8h -; NONEON-NOSVE-NEXT: add v0.8h, v4.8h, v0.8h -; NONEON-NOSVE-NEXT: add v1.8h, v1.8h, v2.8h -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <16 x i16>, ptr %a %tmp2 = load <16 x i16>, ptr %b %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> @@ -1309,19 +1047,6 @@ define void @uzp_v8f32(ptr %a, ptr %b) #0{ ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: add sp, sp, #48 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uzp_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x1] -; NONEON-NOSVE-NEXT: uzp1 v4.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: uzp2 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: uzp1 v1.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: uzp2 v2.4s, v3.4s, v0.4s -; NONEON-NOSVE-NEXT: fadd v0.4s, v4.4s, v0.4s -; NONEON-NOSVE-NEXT: fadd v1.4s, v1.4s, v2.4s -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <8 x float>, ptr %a %tmp2 = load <8 x float>, ptr %b %tmp3 = shufflevector <8 x float> %tmp1, <8 x float> %tmp2, <8 x i32> @@ -1344,19 +1069,6 @@ define void @uzp_v4i64(ptr %a, ptr %b) #0{ ; CHECK-NEXT: add z1.d, z1.d, z2.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uzp_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x1] -; NONEON-NOSVE-NEXT: zip1 v4.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: zip2 v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: zip1 v1.2d, v3.2d, v2.2d -; NONEON-NOSVE-NEXT: zip2 v2.2d, v3.2d, v2.2d -; NONEON-NOSVE-NEXT: add v0.2d, v4.2d, v0.2d -; NONEON-NOSVE-NEXT: add v1.2d, v1.2d, v2.2d -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <4 x i64>, ptr %a %tmp2 = load <4 x i64>, ptr %b %tmp3 = shufflevector <4 x i64> %tmp1, <4 x i64> %tmp2, <4 x i32> @@ -1424,16 +1136,6 @@ define void @uzp_v8i16(ptr %a, ptr %b) #0{ ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uzp_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: uzp1 v2.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: uzp2 v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: add v0.8h, v2.8h, v0.8h -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <8 x i16>, ptr %a %tmp2 = load <8 x i16>, ptr %b %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> @@ -1472,15 +1174,6 @@ define void @uzp_v8i32_undef(ptr %a) #0{ ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: uzp_v8i32_undef: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: uzp1 v2.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: uzp2 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: add v0.4s, v2.4s, v0.4s -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <8 x i32>, ptr %a %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> %tmp4 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> @@ -1504,19 +1197,6 @@ define void @zip_vscale2_4(ptr %a, ptr %b) { ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: zip_vscale2_4: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x1] -; NONEON-NOSVE-NEXT: zip1 v4.2d, v1.2d, v3.2d -; NONEON-NOSVE-NEXT: zip1 v5.2d, v0.2d, v2.2d -; NONEON-NOSVE-NEXT: zip2 v1.2d, v1.2d, v3.2d -; NONEON-NOSVE-NEXT: zip2 v0.2d, v0.2d, v2.2d -; NONEON-NOSVE-NEXT: fadd v2.2d, v4.2d, v5.2d -; NONEON-NOSVE-NEXT: fadd v0.2d, v1.2d, v0.2d -; NONEON-NOSVE-NEXT: stp q2, q0, [x0] -; NONEON-NOSVE-NEXT: ret %tmp1 = load <4 x double>, ptr %a %tmp2 = load <4 x double>, ptr %b %tmp3 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll index 6b3c85f59357..ab7c42b3e9e3 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -36,23 +35,6 @@ define i1 @ptest_v16i1(ptr %a, ptr %b) { ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ptest_v16i1: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: fcmeq v0.4s, v0.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v1.4s, v1.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v3.4s, v3.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v2.4s, v2.4s, #0.0 -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: mvn v0.16b, v0.16b -; NONEON-NOSVE-NEXT: umaxv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: and w0, w8, #0x1 -; NONEON-NOSVE-NEXT: ret %v0 = bitcast ptr %a to ptr %v1 = load <16 x float>, ptr %v0, align 4 %v2 = fcmp une <16 x float> %v1, zeroinitializer @@ -110,33 +92,6 @@ define i1 @ptest_or_v16i1(ptr %a, ptr %b) { ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ptest_or_v16i1: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x1, #32] -; NONEON-NOSVE-NEXT: fcmeq v1.4s, v1.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v0.4s, v0.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v3.4s, v3.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v2.4s, v2.4s, #0.0 -; NONEON-NOSVE-NEXT: ldp q6, q7, [x1] -; NONEON-NOSVE-NEXT: fcmeq v4.4s, v4.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v5.4s, v5.4s, #0.0 -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: fcmeq v7.4s, v7.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v6.4s, v6.4s, #0.0 -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: uzp1 v2.8h, v5.8h, v4.8h -; NONEON-NOSVE-NEXT: uzp1 v3.8h, v6.8h, v7.8h -; NONEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: uzp1 v1.16b, v3.16b, v2.16b -; NONEON-NOSVE-NEXT: mvn v0.16b, v0.16b -; NONEON-NOSVE-NEXT: orn v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: umaxv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: and w0, w8, #0x1 -; NONEON-NOSVE-NEXT: ret %v0 = bitcast ptr %a to ptr %v1 = load <16 x float>, ptr %v0, align 4 %v2 = fcmp une <16 x float> %v1, zeroinitializer @@ -204,33 +159,6 @@ define i1 @ptest_and_v16i1(ptr %a, ptr %b) { ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: ptest_and_v16i1: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q2, q3, [x0] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x1, #32] -; NONEON-NOSVE-NEXT: fcmeq v1.4s, v1.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v0.4s, v0.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v3.4s, v3.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v2.4s, v2.4s, #0.0 -; NONEON-NOSVE-NEXT: ldp q6, q7, [x1] -; NONEON-NOSVE-NEXT: fcmeq v4.4s, v4.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v5.4s, v5.4s, #0.0 -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v1.8h -; NONEON-NOSVE-NEXT: fcmeq v7.4s, v7.4s, #0.0 -; NONEON-NOSVE-NEXT: fcmeq v6.4s, v6.4s, #0.0 -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v3.8h -; NONEON-NOSVE-NEXT: uzp1 v2.8h, v5.8h, v4.8h -; NONEON-NOSVE-NEXT: uzp1 v3.8h, v6.8h, v7.8h -; NONEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: uzp1 v1.16b, v3.16b, v2.16b -; NONEON-NOSVE-NEXT: mvn v0.16b, v0.16b -; NONEON-NOSVE-NEXT: bic v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: uminv b0, v0.16b -; NONEON-NOSVE-NEXT: fmov w8, s0 -; NONEON-NOSVE-NEXT: and w0, w8, #0x1 -; NONEON-NOSVE-NEXT: ret %v0 = bitcast ptr %a to ptr %v1 = load <16 x float>, ptr %v0, align 4 %v2 = fcmp une <16 x float> %v1, zeroinitializer diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll index 0a7352bf4944..bfa931044bc5 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -19,13 +18,6 @@ define <4 x i8> @bitreverse_v4i8(<4 x i8> %op) { ; CHECK-NEXT: lsr z0.h, z0.h, #8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev16 v0.8b, v0.8b -; NONEON-NOSVE-NEXT: rbit v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ushr v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: ret %res = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %op) ret <4 x i8> %res } @@ -38,11 +30,6 @@ define <8 x i8> @bitreverse_v8i8(<8 x i8> %op) { ; CHECK-NEXT: rbit z0.b, p0/m, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rbit v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %op) ret <8 x i8> %res } @@ -55,11 +42,6 @@ define <16 x i8> @bitreverse_v16i8(<16 x i8> %op) { ; CHECK-NEXT: rbit z0.b, p0/m, z0.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %res = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> %op) ret <16 x i8> %res } @@ -73,14 +55,6 @@ define void @bitreverse_v32i8(ptr %a) { ; CHECK-NEXT: rbit z1.b, p0/m, z1.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rbit v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <32 x i8>, ptr %a %res = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %op) store <32 x i8> %res, ptr %a @@ -96,13 +70,6 @@ define <2 x i16> @bitreverse_v2i16(<2 x i16> %op) { ; CHECK-NEXT: lsr z0.s, z0.s, #16 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev32 v0.8b, v0.8b -; NONEON-NOSVE-NEXT: rbit v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ushr v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: ret %res = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %op) ret <2 x i16> %res } @@ -115,12 +82,6 @@ define <4 x i16> @bitreverse_v4i16(<4 x i16> %op) { ; CHECK-NEXT: rbit z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev16 v0.8b, v0.8b -; NONEON-NOSVE-NEXT: rbit v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <4 x i16> @llvm.bitreverse.v4i16(<4 x i16> %op) ret <4 x i16> %res } @@ -133,12 +94,6 @@ define <8 x i16> @bitreverse_v8i16(<8 x i16> %op) { ; CHECK-NEXT: rbit z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev16 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %res = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %op) ret <8 x i16> %res } @@ -152,16 +107,6 @@ define void @bitreverse_v16i16(ptr %a) { ; CHECK-NEXT: rbit z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev16 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rev16 v1.16b, v1.16b -; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rbit v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %op) store <16 x i16> %res, ptr %a @@ -176,12 +121,6 @@ define <2 x i32> @bitreverse_v2i32(<2 x i32> %op) { ; CHECK-NEXT: rbit z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev32 v0.8b, v0.8b -; NONEON-NOSVE-NEXT: rbit v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %op) ret <2 x i32> %res } @@ -194,12 +133,6 @@ define <4 x i32> @bitreverse_v4i32(<4 x i32> %op) { ; CHECK-NEXT: rbit z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev32 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %res = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %op) ret <4 x i32> %res } @@ -213,16 +146,6 @@ define void @bitreverse_v8i32(ptr %a) { ; CHECK-NEXT: rbit z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev32 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rev32 v1.16b, v1.16b -; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rbit v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %op) store <8 x i32> %res, ptr %a @@ -237,12 +160,6 @@ define <1 x i64> @bitreverse_v1i64(<1 x i64> %op) { ; CHECK-NEXT: rbit z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev64 v0.8b, v0.8b -; NONEON-NOSVE-NEXT: rbit v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <1 x i64> @llvm.bitreverse.v1i64(<1 x i64> %op) ret <1 x i64> %res } @@ -255,12 +172,6 @@ define <2 x i64> @bitreverse_v2i64(<2 x i64> %op) { ; CHECK-NEXT: rbit z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev64 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %res = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %op) ret <2 x i64> %res } @@ -274,16 +185,6 @@ define void @bitreverse_v4i64(ptr %a) { ; CHECK-NEXT: rbit z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bitreverse_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev64 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rev64 v1.16b, v1.16b -; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rbit v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %op) store <4 x i64> %res, ptr %a @@ -303,12 +204,6 @@ define <2 x i16> @bswap_v2i16(<2 x i16> %op) { ; CHECK-NEXT: lsr z0.s, z0.s, #16 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bswap_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev32 v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ushr v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: ret %res = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %op) ret <2 x i16> %res } @@ -321,11 +216,6 @@ define <4 x i16> @bswap_v4i16(<4 x i16> %op) { ; CHECK-NEXT: revb z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bswap_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev16 v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %op) ret <4 x i16> %res } @@ -338,11 +228,6 @@ define <8 x i16> @bswap_v8i16(<8 x i16> %op) { ; CHECK-NEXT: revb z0.h, p0/m, z0.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bswap_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev16 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %res = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %op) ret <8 x i16> %res } @@ -356,14 +241,6 @@ define void @bswap_v16i16(ptr %a) { ; CHECK-NEXT: revb z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bswap_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev16 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rev16 v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <16 x i16>, ptr %a %res = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %op) store <16 x i16> %res, ptr %a @@ -378,11 +255,6 @@ define <2 x i32> @bswap_v2i32(<2 x i32> %op) { ; CHECK-NEXT: revb z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bswap_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev32 v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %op) ret <2 x i32> %res } @@ -395,11 +267,6 @@ define <4 x i32> @bswap_v4i32(<4 x i32> %op) { ; CHECK-NEXT: revb z0.s, p0/m, z0.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bswap_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev32 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %res = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %op) ret <4 x i32> %res } @@ -413,14 +280,6 @@ define void @bswap_v8i32(ptr %a) { ; CHECK-NEXT: revb z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bswap_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev32 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rev32 v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <8 x i32>, ptr %a %res = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %op) store <8 x i32> %res, ptr %a @@ -435,11 +294,6 @@ define <1 x i64> @bswap_v1i64(<1 x i64> %op) { ; CHECK-NEXT: revb z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bswap_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev64 v0.8b, v0.8b -; NONEON-NOSVE-NEXT: ret %res = call <1 x i64> @llvm.bswap.v1i64(<1 x i64> %op) ret <1 x i64> %res } @@ -452,11 +306,6 @@ define <2 x i64> @bswap_v2i64(<2 x i64> %op) { ; CHECK-NEXT: revb z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bswap_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev64 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %res = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %op) ret <2 x i64> %res } @@ -470,14 +319,6 @@ define void @bswap_v4i64(ptr %a) { ; CHECK-NEXT: revb z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: bswap_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: rev64 v0.16b, v0.16b -; NONEON-NOSVE-NEXT: rev64 v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op = load <4 x i64>, ptr %a %res = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %op) store <4 x i64> %res, ptr %a diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll index d86c7d36a104..9dd42e7831e0 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -15,19 +14,6 @@ define <4 x i8> @sdiv_v4i8(<4 x i8> %op1) { ; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v1.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: movi d2, #0xff00ff00ff00ff -; NONEON-NOSVE-NEXT: sshr v1.4h, v1.4h, #8 -; NONEON-NOSVE-NEXT: sshr v1.4h, v1.4h, #7 -; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: usra v0.4h, v1.4h, #3 -; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #8 -; NONEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #5 -; NONEON-NOSVE-NEXT: ret %res = sdiv <4 x i8> %op1, shufflevector (<4 x i8> insertelement (<4 x i8> poison, i8 32, i32 0), <4 x i8> poison, <4 x i32> zeroinitializer) ret <4 x i8> %res } @@ -40,13 +26,6 @@ define <8 x i8> @sdiv_v8i8(<8 x i8> %op1) { ; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #5 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmlt v1.8b, v0.8b, #0 -; NONEON-NOSVE-NEXT: usra v0.8b, v1.8b, #3 -; NONEON-NOSVE-NEXT: sshr v0.8b, v0.8b, #5 -; NONEON-NOSVE-NEXT: ret %res = sdiv <8 x i8> %op1, shufflevector (<8 x i8> insertelement (<8 x i8> poison, i8 32, i32 0), <8 x i8> poison, <8 x i32> zeroinitializer) ret <8 x i8> %res } @@ -59,13 +38,6 @@ define <16 x i8> @sdiv_v16i8(<16 x i8> %op1) { ; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #5 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmlt v1.16b, v0.16b, #0 -; NONEON-NOSVE-NEXT: usra v0.16b, v1.16b, #3 -; NONEON-NOSVE-NEXT: sshr v0.16b, v0.16b, #5 -; NONEON-NOSVE-NEXT: ret %res = sdiv <16 x i8> %op1, shufflevector (<16 x i8> insertelement (<16 x i8> poison, i8 32, i32 0), <16 x i8> poison, <16 x i32> zeroinitializer) ret <16 x i8> %res } @@ -79,18 +51,6 @@ define void @sdiv_v32i8(ptr %a) { ; CHECK-NEXT: asrd z1.b, p0/m, z1.b, #5 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cmlt v2.16b, v0.16b, #0 -; NONEON-NOSVE-NEXT: cmlt v3.16b, v1.16b, #0 -; NONEON-NOSVE-NEXT: usra v0.16b, v2.16b, #3 -; NONEON-NOSVE-NEXT: usra v1.16b, v3.16b, #3 -; NONEON-NOSVE-NEXT: sshr v0.16b, v0.16b, #5 -; NONEON-NOSVE-NEXT: sshr v1.16b, v1.16b, #5 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %res = sdiv <32 x i8> %op1, shufflevector (<32 x i8> insertelement (<32 x i8> poison, i8 32, i32 0), <32 x i8> poison, <32 x i32> zeroinitializer) store <32 x i8> %res, ptr %a @@ -106,20 +66,6 @@ define <2 x i16> @sdiv_v2i16(<2 x i16> %op1) { ; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: shl v1.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: mov w8, #31 // =0x1f -; NONEON-NOSVE-NEXT: dup v2.2s, w8 -; NONEON-NOSVE-NEXT: sshr v1.2s, v1.2s, #16 -; NONEON-NOSVE-NEXT: ushr v1.2s, v1.2s, #26 -; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NONEON-NOSVE-NEXT: add v0.2s, v0.2s, v1.2s -; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #16 -; NONEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #5 -; NONEON-NOSVE-NEXT: ret %res = sdiv <2 x i16> %op1, shufflevector (<2 x i16> insertelement (<2 x i16> poison, i16 32, i32 0), <2 x i16> poison, <2 x i32> zeroinitializer) ret <2 x i16> %res } @@ -132,13 +78,6 @@ define <4 x i16> @sdiv_v4i16(<4 x i16> %op1) { ; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmlt v1.4h, v0.4h, #0 -; NONEON-NOSVE-NEXT: usra v0.4h, v1.4h, #11 -; NONEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #5 -; NONEON-NOSVE-NEXT: ret %res = sdiv <4 x i16> %op1, shufflevector (<4 x i16> insertelement (<4 x i16> poison, i16 32, i32 0), <4 x i16> poison, <4 x i32> zeroinitializer) ret <4 x i16> %res } @@ -151,13 +90,6 @@ define <8 x i16> @sdiv_v8i16(<8 x i16> %op1) { ; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmlt v1.8h, v0.8h, #0 -; NONEON-NOSVE-NEXT: usra v0.8h, v1.8h, #11 -; NONEON-NOSVE-NEXT: sshr v0.8h, v0.8h, #5 -; NONEON-NOSVE-NEXT: ret %res = sdiv <8 x i16> %op1, shufflevector (<8 x i16> insertelement (<8 x i16> poison, i16 32, i32 0), <8 x i16> poison, <8 x i32> zeroinitializer) ret <8 x i16> %res } @@ -171,18 +103,6 @@ define void @sdiv_v16i16(ptr %a) { ; CHECK-NEXT: asrd z1.h, p0/m, z1.h, #5 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cmlt v2.8h, v0.8h, #0 -; NONEON-NOSVE-NEXT: cmlt v3.8h, v1.8h, #0 -; NONEON-NOSVE-NEXT: usra v0.8h, v2.8h, #11 -; NONEON-NOSVE-NEXT: usra v1.8h, v3.8h, #11 -; NONEON-NOSVE-NEXT: sshr v0.8h, v0.8h, #5 -; NONEON-NOSVE-NEXT: sshr v1.8h, v1.8h, #5 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %res = sdiv <16 x i16> %op1, shufflevector (<16 x i16> insertelement (<16 x i16> poison, i16 32, i32 0), <16 x i16> poison, <16 x i32> zeroinitializer) store <16 x i16> %res, ptr %a @@ -197,13 +117,6 @@ define <2 x i32> @sdiv_v2i32(<2 x i32> %op1) { ; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmlt v1.2s, v0.2s, #0 -; NONEON-NOSVE-NEXT: usra v0.2s, v1.2s, #27 -; NONEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #5 -; NONEON-NOSVE-NEXT: ret %res = sdiv <2 x i32> %op1, shufflevector (<2 x i32> insertelement (<2 x i32> poison, i32 32, i32 0), <2 x i32> poison, <2 x i32> zeroinitializer) ret <2 x i32> %res } @@ -216,13 +129,6 @@ define <4 x i32> @sdiv_v4i32(<4 x i32> %op1) { ; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmlt v1.4s, v0.4s, #0 -; NONEON-NOSVE-NEXT: usra v0.4s, v1.4s, #27 -; NONEON-NOSVE-NEXT: sshr v0.4s, v0.4s, #5 -; NONEON-NOSVE-NEXT: ret %res = sdiv <4 x i32> %op1, shufflevector (<4 x i32> insertelement (<4 x i32> poison, i32 32, i32 0), <4 x i32> poison, <4 x i32> zeroinitializer) ret <4 x i32> %res } @@ -236,18 +142,6 @@ define void @sdiv_v8i32(ptr %a) { ; CHECK-NEXT: asrd z1.s, p0/m, z1.s, #5 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cmlt v2.4s, v0.4s, #0 -; NONEON-NOSVE-NEXT: cmlt v3.4s, v1.4s, #0 -; NONEON-NOSVE-NEXT: usra v0.4s, v2.4s, #27 -; NONEON-NOSVE-NEXT: usra v1.4s, v3.4s, #27 -; NONEON-NOSVE-NEXT: sshr v0.4s, v0.4s, #5 -; NONEON-NOSVE-NEXT: sshr v1.4s, v1.4s, #5 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %res = sdiv <8 x i32> %op1, shufflevector (<8 x i32> insertelement (<8 x i32> poison, i32 32, i32 0), <8 x i32> poison, <8 x i32> zeroinitializer) store <8 x i32> %res, ptr %a @@ -262,13 +156,6 @@ define <1 x i64> @sdiv_v1i64(<1 x i64> %op1) { ; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #5 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmlt d1, d0, #0 -; NONEON-NOSVE-NEXT: usra d0, d1, #59 -; NONEON-NOSVE-NEXT: sshr d0, d0, #5 -; NONEON-NOSVE-NEXT: ret %res = sdiv <1 x i64> %op1, shufflevector (<1 x i64> insertelement (<1 x i64> poison, i64 32, i32 0), <1 x i64> poison, <1 x i32> zeroinitializer) ret <1 x i64> %res } @@ -282,13 +169,6 @@ define <2 x i64> @sdiv_v2i64(<2 x i64> %op1) { ; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #5 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: cmlt v1.2d, v0.2d, #0 -; NONEON-NOSVE-NEXT: usra v0.2d, v1.2d, #59 -; NONEON-NOSVE-NEXT: sshr v0.2d, v0.2d, #5 -; NONEON-NOSVE-NEXT: ret %res = sdiv <2 x i64> %op1, shufflevector (<2 x i64> insertelement (<2 x i64> poison, i64 32, i32 0), <2 x i64> poison, <2 x i32> zeroinitializer) ret <2 x i64> %res } @@ -302,18 +182,6 @@ define void @sdiv_v4i64(ptr %a) { ; CHECK-NEXT: asrd z1.d, p0/m, z1.d, #5 ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: sdiv_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: cmlt v2.2d, v0.2d, #0 -; NONEON-NOSVE-NEXT: cmlt v3.2d, v1.2d, #0 -; NONEON-NOSVE-NEXT: usra v0.2d, v2.2d, #59 -; NONEON-NOSVE-NEXT: usra v1.2d, v3.2d, #59 -; NONEON-NOSVE-NEXT: sshr v0.2d, v0.2d, #5 -; NONEON-NOSVE-NEXT: sshr v1.2d, v1.2d, #5 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %res = sdiv <4 x i64> %op1, shufflevector (<4 x i64> insertelement (<4 x i64> poison, i64 32, i32 0), <4 x i64> poison, <4 x i32> zeroinitializer) store <4 x i64> %res, ptr %a diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll index 6489e8d94d31..323d5278592f 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE @@ -16,11 +15,6 @@ define <4 x i8> @splat_v4i8(i8 %a) { ; CHECK-NEXT: mov z0.h, w0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.4h, w0 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <4 x i8> undef, i8 %a, i64 0 %splat = shufflevector <4 x i8> %insert, <4 x i8> undef, <4 x i32> zeroinitializer ret <4 x i8> %splat @@ -32,11 +26,6 @@ define <8 x i8> @splat_v8i8(i8 %a) { ; CHECK-NEXT: mov z0.b, w0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.8b, w0 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <8 x i8> undef, i8 %a, i64 0 %splat = shufflevector <8 x i8> %insert, <8 x i8> undef, <8 x i32> zeroinitializer ret <8 x i8> %splat @@ -48,11 +37,6 @@ define <16 x i8> @splat_v16i8(i8 %a) { ; CHECK-NEXT: mov z0.b, w0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.16b, w0 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <16 x i8> undef, i8 %a, i64 0 %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer ret <16 x i8> %splat @@ -64,12 +48,6 @@ define void @splat_v32i8(i8 %a, ptr %b) { ; CHECK-NEXT: mov z0.b, w0 ; CHECK-NEXT: stp q0, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.16b, w0 -; NONEON-NOSVE-NEXT: stp q0, q0, [x1] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <32 x i8> undef, i8 %a, i64 0 %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer store <32 x i8> %splat, ptr %b @@ -82,11 +60,6 @@ define <2 x i16> @splat_v2i16(i16 %a) { ; CHECK-NEXT: mov z0.s, w0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.2s, w0 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <2 x i16> undef, i16 %a, i64 0 %splat = shufflevector <2 x i16> %insert, <2 x i16> undef, <2 x i32> zeroinitializer ret <2 x i16> %splat @@ -98,11 +71,6 @@ define <4 x i16> @splat_v4i16(i16 %a) { ; CHECK-NEXT: mov z0.h, w0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.4h, w0 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <4 x i16> undef, i16 %a, i64 0 %splat = shufflevector <4 x i16> %insert, <4 x i16> undef, <4 x i32> zeroinitializer ret <4 x i16> %splat @@ -114,11 +82,6 @@ define <8 x i16> @splat_v8i16(i16 %a) { ; CHECK-NEXT: mov z0.h, w0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.8h, w0 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <8 x i16> undef, i16 %a, i64 0 %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer ret <8 x i16> %splat @@ -130,12 +93,6 @@ define void @splat_v16i16(i16 %a, ptr %b) { ; CHECK-NEXT: mov z0.h, w0 ; CHECK-NEXT: stp q0, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.8h, w0 -; NONEON-NOSVE-NEXT: stp q0, q0, [x1] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <16 x i16> undef, i16 %a, i64 0 %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer store <16 x i16> %splat, ptr %b @@ -148,11 +105,6 @@ define <2 x i32> @splat_v2i32(i32 %a) { ; CHECK-NEXT: mov z0.s, w0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.2s, w0 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <2 x i32> undef, i32 %a, i64 0 %splat = shufflevector <2 x i32> %insert, <2 x i32> undef, <2 x i32> zeroinitializer ret <2 x i32> %splat @@ -164,11 +116,6 @@ define <4 x i32> @splat_v4i32(i32 %a) { ; CHECK-NEXT: mov z0.s, w0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.4s, w0 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <4 x i32> undef, i32 %a, i64 0 %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer ret <4 x i32> %splat @@ -180,12 +127,6 @@ define void @splat_v8i32(i32 %a, ptr %b) { ; CHECK-NEXT: mov z0.s, w0 ; CHECK-NEXT: stp q0, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.4s, w0 -; NONEON-NOSVE-NEXT: stp q0, q0, [x1] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <8 x i32> undef, i32 %a, i64 0 %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer store <8 x i32> %splat, ptr %b @@ -198,11 +139,6 @@ define <1 x i64> @splat_v1i64(i64 %a) { ; CHECK-NEXT: mov z0.d, x0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov d0, x0 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <1 x i64> undef, i64 %a, i64 0 %splat = shufflevector <1 x i64> %insert, <1 x i64> undef, <1 x i32> zeroinitializer ret <1 x i64> %splat @@ -214,11 +150,6 @@ define <2 x i64> @splat_v2i64(i64 %a) { ; CHECK-NEXT: mov z0.d, x0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.2d, x0 -; NONEON-NOSVE-NEXT: ret %insert = insertelement <2 x i64> undef, i64 %a, i64 0 %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer ret <2 x i64> %splat @@ -230,12 +161,6 @@ define void @splat_v4i64(i64 %a, ptr %b) { ; CHECK-NEXT: mov z0.d, x0 ; CHECK-NEXT: stp q0, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: dup v0.2d, x0 -; NONEON-NOSVE-NEXT: stp q0, q0, [x1] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <4 x i64> undef, i64 %a, i64 0 %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer store <4 x i64> %splat, ptr %b @@ -253,12 +178,6 @@ define <2 x half> @splat_v2f16(half %a) { ; CHECK-NEXT: mov z0.h, h0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $h0 killed $h0 def $q0 -; NONEON-NOSVE-NEXT: dup v0.4h, v0.h[0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <2 x half> undef, half %a, i64 0 %splat = shufflevector <2 x half> %insert, <2 x half> undef, <2 x i32> zeroinitializer ret <2 x half> %splat @@ -271,12 +190,6 @@ define <4 x half> @splat_v4f16(half %a) { ; CHECK-NEXT: mov z0.h, h0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $h0 killed $h0 def $q0 -; NONEON-NOSVE-NEXT: dup v0.4h, v0.h[0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <4 x half> undef, half %a, i64 0 %splat = shufflevector <4 x half> %insert, <4 x half> undef, <4 x i32> zeroinitializer ret <4 x half> %splat @@ -289,12 +202,6 @@ define <8 x half> @splat_v8f16(half %a) { ; CHECK-NEXT: mov z0.h, h0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $h0 killed $h0 def $q0 -; NONEON-NOSVE-NEXT: dup v0.8h, v0.h[0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <8 x half> undef, half %a, i64 0 %splat = shufflevector <8 x half> %insert, <8 x half> undef, <8 x i32> zeroinitializer ret <8 x half> %splat @@ -307,13 +214,6 @@ define void @splat_v16f16(half %a, ptr %b) { ; CHECK-NEXT: mov z0.h, h0 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $h0 killed $h0 def $q0 -; NONEON-NOSVE-NEXT: dup v0.8h, v0.h[0] -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <16 x half> undef, half %a, i64 0 %splat = shufflevector <16 x half> %insert, <16 x half> undef, <16 x i32> zeroinitializer store <16 x half> %splat, ptr %b @@ -327,12 +227,6 @@ define <2 x float> @splat_v2f32(float %a, <2 x float> %op2) { ; CHECK-NEXT: mov z0.s, s0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $s0 killed $s0 def $q0 -; NONEON-NOSVE-NEXT: dup v0.2s, v0.s[0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <2 x float> undef, float %a, i64 0 %splat = shufflevector <2 x float> %insert, <2 x float> undef, <2 x i32> zeroinitializer ret <2 x float> %splat @@ -345,12 +239,6 @@ define <4 x float> @splat_v4f32(float %a, <4 x float> %op2) { ; CHECK-NEXT: mov z0.s, s0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $s0 killed $s0 def $q0 -; NONEON-NOSVE-NEXT: dup v0.4s, v0.s[0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <4 x float> undef, float %a, i64 0 %splat = shufflevector <4 x float> %insert, <4 x float> undef, <4 x i32> zeroinitializer ret <4 x float> %splat @@ -363,13 +251,6 @@ define void @splat_v8f32(float %a, ptr %b) { ; CHECK-NEXT: mov z0.s, s0 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $s0 killed $s0 def $q0 -; NONEON-NOSVE-NEXT: dup v0.4s, v0.s[0] -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <8 x float> undef, float %a, i64 0 %splat = shufflevector <8 x float> %insert, <8 x float> undef, <8 x i32> zeroinitializer store <8 x float> %splat, ptr %b @@ -380,10 +261,6 @@ define <1 x double> @splat_v1f64(double %a, <1 x double> %op2) { ; CHECK-LABEL: splat_v1f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ret %insert = insertelement <1 x double> undef, double %a, i64 0 %splat = shufflevector <1 x double> %insert, <1 x double> undef, <1 x i32> zeroinitializer ret <1 x double> %splat @@ -396,12 +273,6 @@ define <2 x double> @splat_v2f64(double %a, <2 x double> %op2) { ; CHECK-NEXT: mov z0.d, d0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: dup v0.2d, v0.d[0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <2 x double> undef, double %a, i64 0 %splat = shufflevector <2 x double> %insert, <2 x double> undef, <2 x i32> zeroinitializer ret <2 x double> %splat @@ -414,13 +285,6 @@ define void @splat_v4f64(double %a, ptr %b) { ; CHECK-NEXT: mov z0.d, d0 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NONEON-NOSVE-NEXT: dup v0.2d, v0.d[0] -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <4 x double> undef, double %a, i64 0 %splat = shufflevector <4 x double> %insert, <4 x double> undef, <4 x i32> zeroinitializer store <4 x double> %splat, ptr %b @@ -437,12 +301,6 @@ define void @splat_imm_v32i8(ptr %a) { ; CHECK-NEXT: mov z0.b, #1 // =0x1 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_imm_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.16b, #1 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <32 x i8> undef, i8 1, i64 0 %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer store <32 x i8> %splat, ptr %a @@ -455,13 +313,6 @@ define void @splat_imm_v16i16(ptr %a) { ; CHECK-NEXT: mov z0.h, #2 // =0x2 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_imm_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #2 // =0x2 -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <16 x i16> undef, i16 2, i64 0 %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer store <16 x i16> %splat, ptr %a @@ -474,13 +325,6 @@ define void @splat_imm_v8i32(ptr %a) { ; CHECK-NEXT: mov z0.s, #3 // =0x3 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_imm_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #3 // =0x3 -; NONEON-NOSVE-NEXT: dup v0.4s, w8 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <8 x i32> undef, i32 3, i64 0 %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer store <8 x i32> %splat, ptr %a @@ -493,13 +337,6 @@ define void @splat_imm_v4i64(ptr %a) { ; CHECK-NEXT: mov z0.d, #4 // =0x4 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_imm_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #4 // =0x4 -; NONEON-NOSVE-NEXT: dup v0.2d, x8 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <4 x i64> undef, i64 4, i64 0 %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer store <4 x i64> %splat, ptr %a @@ -516,13 +353,6 @@ define void @splat_imm_v16f16(ptr %a) { ; CHECK-NEXT: fmov z0.h, #5.00000000 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_imm_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov w8, #17664 // =0x4500 -; NONEON-NOSVE-NEXT: dup v0.8h, w8 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <16 x half> undef, half 5.0, i64 0 %splat = shufflevector <16 x half> %insert, <16 x half> undef, <16 x i32> zeroinitializer store <16 x half> %splat, ptr %a @@ -535,12 +365,6 @@ define void @splat_imm_v8f32(ptr %a) { ; CHECK-NEXT: fmov z0.s, #6.00000000 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_imm_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov v0.4s, #6.00000000 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <8 x float> undef, float 6.0, i64 0 %splat = shufflevector <8 x float> %insert, <8 x float> undef, <8 x i32> zeroinitializer store <8 x float> %splat, ptr %a @@ -553,12 +377,6 @@ define void @splat_imm_v4f64(ptr %a) { ; CHECK-NEXT: fmov z0.d, #7.00000000 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: splat_imm_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov v0.2d, #7.00000000 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret %insert = insertelement <4 x double> undef, double 7.0, i64 0 %splat = shufflevector <4 x double> %insert, <4 x double> undef, <4 x i32> zeroinitializer store <4 x double> %splat, ptr %a diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll index 41449aa90ba0..06709ca3685c 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -13,11 +12,6 @@ define void @store_v4i8(ptr %a) { ; CHECK-NEXT: ptrue p0.h, vl4 ; CHECK-NEXT: st1b { z0.h }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str wzr, [x0] -; NONEON-NOSVE-NEXT: ret store <4 x i8> zeroinitializer, ptr %a ret void } @@ -28,12 +22,6 @@ define void @store_v8i8(ptr %a) { ; CHECK-NEXT: mov z0.b, #0 // =0x0 ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret store <8 x i8> zeroinitializer, ptr %a ret void } @@ -44,12 +32,6 @@ define void @store_v16i8(ptr %a) { ; CHECK-NEXT: mov z0.b, #0 // =0x0 ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret store <16 x i8> zeroinitializer, ptr %a ret void } @@ -60,12 +42,6 @@ define void @store_v32i8(ptr %a) { ; CHECK-NEXT: mov z0.b, #0 // =0x0 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <32 x i8> zeroinitializer, ptr %a ret void } @@ -77,11 +53,6 @@ define void @store_v2i16(ptr %a) { ; CHECK-NEXT: ptrue p0.s, vl2 ; CHECK-NEXT: st1h { z0.s }, p0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str wzr, [x0] -; NONEON-NOSVE-NEXT: ret store <2 x i16> zeroinitializer, ptr %a ret void } @@ -93,11 +64,6 @@ define void @store_v2f16(ptr %a) { ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: str w8, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v2f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str wzr, [x0] -; NONEON-NOSVE-NEXT: ret store <2 x half> zeroinitializer, ptr %a ret void } @@ -108,12 +74,6 @@ define void @store_v4i16(ptr %a) { ; CHECK-NEXT: mov z0.h, #0 // =0x0 ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret store <4 x i16> zeroinitializer, ptr %a ret void } @@ -124,12 +84,6 @@ define void @store_v4f16(ptr %a) { ; CHECK-NEXT: mov z0.h, #0 // =0x0 ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d0, #0000000000000000 -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret store <4 x half> zeroinitializer, ptr %a ret void } @@ -140,12 +94,6 @@ define void @store_v8i16(ptr %a) { ; CHECK-NEXT: mov z0.h, #0 // =0x0 ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret store <8 x i16> zeroinitializer, ptr %a ret void } @@ -156,12 +104,6 @@ define void @store_v8f16(ptr %a) { ; CHECK-NEXT: mov z0.h, #0 // =0x0 ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: str q0, [x0] -; NONEON-NOSVE-NEXT: ret store <8 x half> zeroinitializer, ptr %a ret void } @@ -172,12 +114,6 @@ define void @store_v16i16(ptr %a) { ; CHECK-NEXT: mov z0.h, #0 // =0x0 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <16 x i16> zeroinitializer, ptr %a ret void } @@ -188,12 +124,6 @@ define void @store_v16f16(ptr %a) { ; CHECK-NEXT: mov z0.h, #0 // =0x0 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <16 x half> zeroinitializer, ptr %a ret void } @@ -203,11 +133,6 @@ define void @store_v2i32(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: str xzr, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str xzr, [x0] -; NONEON-NOSVE-NEXT: ret store <2 x i32> zeroinitializer, ptr %a ret void } @@ -217,11 +142,6 @@ define void @store_v2f32(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: str xzr, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: str xzr, [x0] -; NONEON-NOSVE-NEXT: ret store <2 x float> zeroinitializer, ptr %a ret void } @@ -231,11 +151,6 @@ define void @store_v4i32(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: stp xzr, xzr, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: stp xzr, xzr, [x0] -; NONEON-NOSVE-NEXT: ret store <4 x i32> zeroinitializer, ptr %a ret void } @@ -245,11 +160,6 @@ define void @store_v4f32(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: stp xzr, xzr, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: stp xzr, xzr, [x0] -; NONEON-NOSVE-NEXT: ret store <4 x float> zeroinitializer, ptr %a ret void } @@ -260,12 +170,6 @@ define void @store_v8i32(ptr %a) { ; CHECK-NEXT: mov z0.s, #0 // =0x0 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <8 x i32> zeroinitializer, ptr %a ret void } @@ -276,12 +180,6 @@ define void @store_v8f32(ptr %a) { ; CHECK-NEXT: mov z0.s, #0 // =0x0 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <8 x float> zeroinitializer, ptr %a ret void } @@ -292,12 +190,6 @@ define void @store_v1i64(ptr %a) { ; CHECK-NEXT: mov z0.d, #0 // =0x0 ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v1i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret store <1 x i64> zeroinitializer, ptr %a ret void } @@ -308,12 +200,6 @@ define void @store_v1f64(ptr %a) { ; CHECK-NEXT: fmov d0, xzr ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v1f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi d0, #0000000000000000 -; NONEON-NOSVE-NEXT: str d0, [x0] -; NONEON-NOSVE-NEXT: ret store <1 x double> zeroinitializer, ptr %a ret void } @@ -323,11 +209,6 @@ define void @store_v2i64(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: stp xzr, xzr, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: stp xzr, xzr, [x0] -; NONEON-NOSVE-NEXT: ret store <2 x i64> zeroinitializer, ptr %a ret void } @@ -337,11 +218,6 @@ define void @store_v2f64(ptr %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: stp xzr, xzr, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: stp xzr, xzr, [x0] -; NONEON-NOSVE-NEXT: ret store <2 x double> zeroinitializer, ptr %a ret void } @@ -352,12 +228,6 @@ define void @store_v4i64(ptr %a) { ; CHECK-NEXT: mov z0.d, #0 // =0x0 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <4 x i64> zeroinitializer, ptr %a ret void } @@ -368,12 +238,6 @@ define void @store_v4f64(ptr %a) { ; CHECK-NEXT: mov z0.d, #0 // =0x0 ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: stp q0, q0, [x0] -; NONEON-NOSVE-NEXT: ret store <4 x double> zeroinitializer, ptr %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll index d1873f436815..838db0ce8185 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE ; Test we can code generater patterns of the form: @@ -24,12 +23,6 @@ define void @subvector_v4i8(ptr %in, ptr %out) { ; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0] ; CHECK-NEXT: st1b { z0.h }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v4i8: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr w8, [x0] -; NONEON-NOSVE-NEXT: str w8, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <4 x i8>, ptr %in br label %bb1 @@ -44,12 +37,6 @@ define void @subvector_v8i8(ptr %in, ptr %out) { ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v8i8: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <8 x i8>, ptr %in br label %bb1 @@ -64,12 +51,6 @@ define void @subvector_v16i8(ptr %in, ptr %out) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v16i8: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <16 x i8>, ptr %in br label %bb1 @@ -84,12 +65,6 @@ define void @subvector_v32i8(ptr %in, ptr %out) { ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v32i8: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <32 x i8>, ptr %in br label %bb1 @@ -106,12 +81,6 @@ define void @subvector_v2i16(ptr %in, ptr %out) { ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v2i16: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr w8, [x0] -; NONEON-NOSVE-NEXT: str w8, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <2 x i16>, ptr %in br label %bb1 @@ -126,12 +95,6 @@ define void @subvector_v4i16(ptr %in, ptr %out) { ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v4i16: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <4 x i16>, ptr %in br label %bb1 @@ -146,12 +109,6 @@ define void @subvector_v8i16(ptr %in, ptr %out) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v8i16: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <8 x i16>, ptr %in br label %bb1 @@ -166,12 +123,6 @@ define void @subvector_v16i16(ptr %in, ptr %out) { ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v16i16: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <16 x i16>, ptr %in br label %bb1 @@ -187,12 +138,6 @@ define void @subvector_v2i32(ptr %in, ptr %out) { ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v2i32: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <2 x i32>, ptr %in br label %bb1 @@ -207,12 +152,6 @@ define void @subvector_v4i32(ptr %in, ptr %out) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v4i32: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <4 x i32>, ptr %in br label %bb1 @@ -227,12 +166,6 @@ define void @subvector_v8i32(ptr %in, ptr %out) { ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v8i32: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <8 x i32>, ptr %in br label %bb1 @@ -248,12 +181,6 @@ define void @subvector_v2i64(ptr %in, ptr %out) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v2i64: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <2 x i64>, ptr %in br label %bb1 @@ -268,12 +195,6 @@ define void @subvector_v4i64(ptr %in, ptr %out) { ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v4i64: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <4 x i64>, ptr %in br label %bb1 @@ -289,12 +210,6 @@ define void @subvector_v2f16(ptr %in, ptr %out) { ; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: str w8, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v2f16: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr w8, [x0] -; NONEON-NOSVE-NEXT: str w8, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <2 x half>, ptr %in br label %bb1 @@ -309,12 +224,6 @@ define void @subvector_v4f16(ptr %in, ptr %out) { ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v4f16: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <4 x half>, ptr %in br label %bb1 @@ -329,12 +238,6 @@ define void @subvector_v8f16(ptr %in, ptr %out) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v8f16: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <8 x half>, ptr %in br label %bb1 @@ -349,12 +252,6 @@ define void @subvector_v16f16(ptr %in, ptr %out) { ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v16f16: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <16 x half>, ptr %in br label %bb1 @@ -370,12 +267,6 @@ define void @subvector_v2f32(ptr %in, ptr %out) { ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v2f32: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr d0, [x0] -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <2 x float>, ptr %in br label %bb1 @@ -390,12 +281,6 @@ define void @subvector_v4f32(ptr %in, ptr %out) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v4f32: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <4 x float>, ptr %in br label %bb1 @@ -410,12 +295,6 @@ define void @subvector_v8f32(ptr %in, ptr %out) { ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v8f32: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <8 x float>,ptr %in br label %bb1 @@ -431,12 +310,6 @@ define void @subvector_v2f64(ptr %in, ptr %out) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v2f64: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: str q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <2 x double>, ptr %in br label %bb1 @@ -451,12 +324,6 @@ define void @subvector_v4f64(ptr %in, ptr %out) { ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: subvector_v4f64: -; NONEON-NOSVE: // %bb.0: // %bb1 -; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] -; NONEON-NOSVE-NEXT: stp q0, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <4 x double>, ptr %in br label %bb1 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll index f0a4368da3ee..7e3a175c40d2 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -13,13 +12,6 @@ define void @store_trunc_v8i16i8(ptr %ap, ptr %dest) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: st1b { z0.h }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_trunc_v8i16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: xtn v0.8b, v0.8h -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <8 x i16>, ptr %ap %val = trunc <8 x i16> %a to <8 x i8> store <8 x i8> %val, ptr %dest @@ -33,14 +25,6 @@ define void @store_trunc_v4i32i8(ptr %ap, ptr %dest) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: st1b { z0.s }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_trunc_v4i32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8b, v0.8b, v0.8b -; NONEON-NOSVE-NEXT: str s0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <4 x i32>, ptr %ap %val = trunc <4 x i32> %a to <4 x i8> store <4 x i8> %val, ptr %dest @@ -54,13 +38,6 @@ define void @store_trunc_v4i32i16(ptr %ap, ptr %dest) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_trunc_v4i32i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <4 x i32>, ptr %ap %val = trunc <4 x i32> %a to <4 x i16> store <4 x i16> %val, ptr %dest @@ -74,13 +51,6 @@ define void @store_trunc_v2i64i8(ptr %ap, ptr %dest) { ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: st1w { z0.d }, p0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_trunc_v2i64i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0] -; NONEON-NOSVE-NEXT: xtn v0.2s, v0.2d -; NONEON-NOSVE-NEXT: str d0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <2 x i64>, ptr %ap %val = trunc <2 x i64> %a to <2 x i32> store <2 x i32> %val, ptr %dest @@ -96,14 +66,6 @@ define void @store_trunc_v2i256i64(ptr %ap, ptr %dest) { ; CHECK-NEXT: splice z1.d, p0, z1.d, z0.d ; CHECK-NEXT: str q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: store_trunc_v2i256i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr d0, [x0, #32] -; NONEON-NOSVE-NEXT: ldr d1, [x0] -; NONEON-NOSVE-NEXT: mov v1.d[1], v0.d[0] -; NONEON-NOSVE-NEXT: str q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <2 x i256>, ptr %ap %val = trunc <2 x i256> %a to <2 x i64> store <2 x i64> %val, ptr %dest diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll index 4895ffb6858e..70219dd30f76 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -20,12 +19,6 @@ define <16 x i8> @trunc_v16i16_v16i8(ptr %in) nounwind { ; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v16i16_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: ret %a = load <16 x i16>, ptr %in %b = trunc <16 x i16> %a to <16 x i8> ret <16 x i8> %b @@ -48,17 +41,6 @@ define void @trunc_v32i16_v32i8(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: add z1.b, z2.b, z2.b ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v32i16_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: uzp1 v1.16b, v3.16b, v2.16b -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <32 x i16>, ptr %in %b = trunc <32 x i16> %a to <32 x i8> %c = add <32 x i8> %b, %b @@ -94,24 +76,6 @@ define void @trunc_v64i16_v64i8(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: stp q0, q1, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v64i16_v64i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #64] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0, #96] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0] -; NONEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: ldp q6, q1, [x0, #32] -; NONEON-NOSVE-NEXT: uzp1 v2.16b, v3.16b, v2.16b -; NONEON-NOSVE-NEXT: uzp1 v3.16b, v5.16b, v4.16b -; NONEON-NOSVE-NEXT: uzp1 v1.16b, v6.16b, v1.16b -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v0.16b -; NONEON-NOSVE-NEXT: add v2.16b, v2.16b, v2.16b -; NONEON-NOSVE-NEXT: add v3.16b, v3.16b, v3.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q2, [x1, #32] -; NONEON-NOSVE-NEXT: stp q3, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <64 x i16>, ptr %in %b = trunc <64 x i16> %a to <64 x i8> %c = add <64 x i8> %b, %b @@ -169,38 +133,6 @@ define void @trunc_v128i16_v128i8(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: stp q2, q3, [x1, #32] ; CHECK-NEXT: stp q4, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v128i16_v128i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #192] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0, #224] -; NONEON-NOSVE-NEXT: ldp q7, q6, [x0, #128] -; NONEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: ldp q16, q1, [x0, #160] -; NONEON-NOSVE-NEXT: uzp1 v4.16b, v5.16b, v4.16b -; NONEON-NOSVE-NEXT: ldp q17, q5, [x0, #64] -; NONEON-NOSVE-NEXT: uzp1 v6.16b, v7.16b, v6.16b -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q18, q7, [x0, #96] -; NONEON-NOSVE-NEXT: uzp1 v1.16b, v16.16b, v1.16b -; NONEON-NOSVE-NEXT: uzp1 v5.16b, v17.16b, v5.16b -; NONEON-NOSVE-NEXT: ldp q17, q16, [x0, #32] -; NONEON-NOSVE-NEXT: uzp1 v2.16b, v3.16b, v2.16b -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v0.16b -; NONEON-NOSVE-NEXT: add v4.16b, v4.16b, v4.16b -; NONEON-NOSVE-NEXT: uzp1 v7.16b, v18.16b, v7.16b -; NONEON-NOSVE-NEXT: add v3.16b, v6.16b, v6.16b -; NONEON-NOSVE-NEXT: uzp1 v6.16b, v17.16b, v16.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q4, [x1, #96] -; NONEON-NOSVE-NEXT: add v0.16b, v5.16b, v5.16b -; NONEON-NOSVE-NEXT: add v2.16b, v2.16b, v2.16b -; NONEON-NOSVE-NEXT: add v4.16b, v7.16b, v7.16b -; NONEON-NOSVE-NEXT: stp q3, q1, [x1, #64] -; NONEON-NOSVE-NEXT: add v1.16b, v6.16b, v6.16b -; NONEON-NOSVE-NEXT: stp q0, q4, [x1, #32] -; NONEON-NOSVE-NEXT: stp q2, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <128 x i16>, ptr %in %b = trunc <128 x i16> %a to <128 x i8> %c = add <128 x i8> %b, %b @@ -223,13 +155,6 @@ define <8 x i8> @trunc_v8i32_v8i8(ptr %in) nounwind { ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v8i32_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: xtn v0.8b, v0.8h -; NONEON-NOSVE-NEXT: ret %a = load <8 x i32>, ptr %in %b = trunc <8 x i32> %a to <8 x i8> ret <8 x i8> %b @@ -253,15 +178,6 @@ define <16 x i8> @trunc_v16i32_v16i8(ptr %in) nounwind { ; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v16i32_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0, #32] -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: uzp1 v2.8h, v3.8h, v2.8h -; NONEON-NOSVE-NEXT: uzp1 v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: ret %a = load <16 x i32>, ptr %in %b = trunc <16 x i32> %a to <16 x i8> ret <16 x i8> %b @@ -299,23 +215,6 @@ define void @trunc_v32i32_v32i8(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: add z1.b, z3.b, z3.b ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v32i32_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #64] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0, #96] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0] -; NONEON-NOSVE-NEXT: ldp q7, q6, [x0, #32] -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: uzp1 v2.8h, v3.8h, v2.8h -; NONEON-NOSVE-NEXT: uzp1 v3.8h, v5.8h, v4.8h -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v7.8h, v6.8h -; NONEON-NOSVE-NEXT: uzp1 v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: uzp1 v1.16b, v3.16b, v1.16b -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <32 x i32>, ptr %in %b = trunc <32 x i32> %a to <32 x i8> %c = add <32 x i8> %b, %b @@ -380,36 +279,6 @@ define void @trunc_v64i32_v64i8(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: stp q1, q2, [x1, #32] ; CHECK-NEXT: stp q3, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v64i32_v64i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #128] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0, #160] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0, #192] -; NONEON-NOSVE-NEXT: ldp q7, q6, [x0, #224] -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: uzp1 v2.8h, v3.8h, v2.8h -; NONEON-NOSVE-NEXT: ldp q3, q1, [x0] -; NONEON-NOSVE-NEXT: uzp1 v4.8h, v5.8h, v4.8h -; NONEON-NOSVE-NEXT: ldp q17, q5, [x0, #64] -; NONEON-NOSVE-NEXT: uzp1 v6.8h, v7.8h, v6.8h -; NONEON-NOSVE-NEXT: ldp q16, q7, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q19, q18, [x0, #96] -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v3.8h, v1.8h -; NONEON-NOSVE-NEXT: uzp1 v5.8h, v17.8h, v5.8h -; NONEON-NOSVE-NEXT: uzp1 v0.16b, v0.16b, v2.16b -; NONEON-NOSVE-NEXT: uzp1 v7.8h, v16.8h, v7.8h -; NONEON-NOSVE-NEXT: uzp1 v3.8h, v19.8h, v18.8h -; NONEON-NOSVE-NEXT: uzp1 v2.16b, v4.16b, v6.16b -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v0.16b -; NONEON-NOSVE-NEXT: uzp1 v1.16b, v1.16b, v7.16b -; NONEON-NOSVE-NEXT: uzp1 v3.16b, v5.16b, v3.16b -; NONEON-NOSVE-NEXT: add v2.16b, v2.16b, v2.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q0, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add v3.16b, v3.16b, v3.16b -; NONEON-NOSVE-NEXT: stp q1, q3, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <64 x i32>, ptr %in %b = trunc <64 x i32> %a to <64 x i8> %c = add <64 x i8> %b, %b @@ -431,12 +300,6 @@ define <8 x i16> @trunc_v8i32_v8i16(ptr %in) nounwind { ; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v8i32_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: ret %a = load <8 x i32>, ptr %in %b = trunc <8 x i32> %a to <8 x i16> ret <8 x i16> %b @@ -459,17 +322,6 @@ define void @trunc_v16i32_v16i16(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: add z1.h, z2.h, z2.h ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v16i32_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v3.8h, v2.8h -; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v0.8h -; NONEON-NOSVE-NEXT: add v1.8h, v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <16 x i32>, ptr %in %b = trunc <16 x i32> %a to <16 x i16> %c = add <16 x i16> %b, %b @@ -505,24 +357,6 @@ define void @trunc_v32i32_v32i16(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: stp q0, q1, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v32i32_v32i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #64] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0, #96] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0] -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: ldp q6, q1, [x0, #32] -; NONEON-NOSVE-NEXT: uzp1 v2.8h, v3.8h, v2.8h -; NONEON-NOSVE-NEXT: uzp1 v3.8h, v5.8h, v4.8h -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v6.8h, v1.8h -; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v0.8h -; NONEON-NOSVE-NEXT: add v2.8h, v2.8h, v2.8h -; NONEON-NOSVE-NEXT: add v3.8h, v3.8h, v3.8h -; NONEON-NOSVE-NEXT: add v1.8h, v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q2, [x1, #32] -; NONEON-NOSVE-NEXT: stp q3, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <32 x i32>, ptr %in %b = trunc <32 x i32> %a to <32 x i16> %c = add <32 x i16> %b, %b @@ -580,38 +414,6 @@ define void @trunc_v64i32_v64i16(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: stp q2, q3, [x1, #32] ; CHECK-NEXT: stp q4, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v64i32_v64i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #192] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0, #224] -; NONEON-NOSVE-NEXT: ldp q7, q6, [x0, #128] -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: ldp q16, q1, [x0, #160] -; NONEON-NOSVE-NEXT: uzp1 v4.8h, v5.8h, v4.8h -; NONEON-NOSVE-NEXT: ldp q17, q5, [x0, #64] -; NONEON-NOSVE-NEXT: uzp1 v6.8h, v7.8h, v6.8h -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q18, q7, [x0, #96] -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v16.8h, v1.8h -; NONEON-NOSVE-NEXT: uzp1 v5.8h, v17.8h, v5.8h -; NONEON-NOSVE-NEXT: ldp q17, q16, [x0, #32] -; NONEON-NOSVE-NEXT: uzp1 v2.8h, v3.8h, v2.8h -; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v0.8h -; NONEON-NOSVE-NEXT: add v4.8h, v4.8h, v4.8h -; NONEON-NOSVE-NEXT: uzp1 v7.8h, v18.8h, v7.8h -; NONEON-NOSVE-NEXT: add v3.8h, v6.8h, v6.8h -; NONEON-NOSVE-NEXT: uzp1 v6.8h, v17.8h, v16.8h -; NONEON-NOSVE-NEXT: add v1.8h, v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q4, [x1, #96] -; NONEON-NOSVE-NEXT: add v0.8h, v5.8h, v5.8h -; NONEON-NOSVE-NEXT: add v2.8h, v2.8h, v2.8h -; NONEON-NOSVE-NEXT: add v4.8h, v7.8h, v7.8h -; NONEON-NOSVE-NEXT: stp q3, q1, [x1, #64] -; NONEON-NOSVE-NEXT: add v1.8h, v6.8h, v6.8h -; NONEON-NOSVE-NEXT: stp q0, q4, [x1, #32] -; NONEON-NOSVE-NEXT: stp q2, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <64 x i32>, ptr %in %b = trunc <64 x i32> %a to <64 x i16> %c = add <64 x i16> %b, %b @@ -635,13 +437,6 @@ define <4 x i8> @trunc_v4i64_v4i8(ptr %in) nounwind { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v4i64_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %a = load <4 x i64>, ptr %in %b = trunc <4 x i64> %a to <4 x i8> ret <4 x i8> %b @@ -666,16 +461,6 @@ define <8 x i8> @trunc_v8i64_v8i8(ptr %in) nounwind { ; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v8i64_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0, #32] -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: uzp1 v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NONEON-NOSVE-NEXT: xtn v0.8b, v0.8h -; NONEON-NOSVE-NEXT: ret %a = load <8 x i64>, ptr %in %b = trunc <8 x i64> %a to <8 x i8> ret <8 x i8> %b @@ -714,21 +499,6 @@ define <16 x i8> @trunc_v16i64_v16i8(ptr %in) nounwind { ; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v16i64_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0, #96] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q7, q6, [x0, #64] -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: uzp1 v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: uzp1 v4.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: uzp1 v3.4s, v7.4s, v6.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v4.8h -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v3.8h, v2.8h -; NONEON-NOSVE-NEXT: uzp1 v0.16b, v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret %a = load <16 x i64>, ptr %in %b = trunc <16 x i64> %a to <16 x i8> ret <16 x i8> %b @@ -795,35 +565,6 @@ define void @trunc_v32i64_v32i8(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: add z0.b, z0.b, z0.b ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v32i64_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #224] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0, #192] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q7, q6, [x0, #96] -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: uzp1 v1.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0, #128] -; NONEON-NOSVE-NEXT: ldp q17, q16, [x0, #160] -; NONEON-NOSVE-NEXT: uzp1 v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: ldp q19, q18, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q21, q20, [x0, #64] -; NONEON-NOSVE-NEXT: uzp1 v4.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: uzp1 v16.4s, v17.4s, v16.4s -; NONEON-NOSVE-NEXT: uzp1 v5.4s, v7.4s, v6.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NONEON-NOSVE-NEXT: uzp1 v7.4s, v19.4s, v18.4s -; NONEON-NOSVE-NEXT: uzp1 v6.4s, v21.4s, v20.4s -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v4.8h, v16.8h -; NONEON-NOSVE-NEXT: uzp1 v2.8h, v2.8h, v7.8h -; NONEON-NOSVE-NEXT: uzp1 v3.8h, v6.8h, v5.8h -; NONEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b -; NONEON-NOSVE-NEXT: uzp1 v1.16b, v2.16b, v3.16b -; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v0.16b -; NONEON-NOSVE-NEXT: add v1.16b, v1.16b, v1.16b -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <32 x i64>, ptr %in %b = trunc <32 x i64> %a to <32 x i8> %c = add <32 x i8> %b, %b @@ -846,13 +587,6 @@ define <4 x i16> @trunc_v4i64_v4i16(ptr %in) nounwind { ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v4i64_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NONEON-NOSVE-NEXT: ret %a = load <4 x i64>, ptr %in %b = trunc <4 x i64> %a to <4 x i16> ret <4 x i16> %b @@ -876,15 +610,6 @@ define <8 x i16> @trunc_v8i64_v8i16(ptr %in) nounwind { ; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v8i64_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0, #32] -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: uzp1 v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NONEON-NOSVE-NEXT: ret %a = load <8 x i64>, ptr %in %b = trunc <8 x i64> %a to <8 x i16> ret <8 x i16> %b @@ -922,23 +647,6 @@ define void @trunc_v16i64_v16i16(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: add z1.h, z3.h, z3.h ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v16i64_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #64] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0, #96] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0] -; NONEON-NOSVE-NEXT: ldp q7, q6, [x0, #32] -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: uzp1 v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: uzp1 v3.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: uzp1 v1.4s, v7.4s, v6.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v3.8h, v1.8h -; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v0.8h -; NONEON-NOSVE-NEXT: add v1.8h, v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <16 x i64>, ptr %in %b = trunc <16 x i64> %a to <16 x i16> %c = add <16 x i16> %b, %b @@ -1003,36 +711,6 @@ define void @trunc_v32i64_v32i16(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: stp q1, q2, [x1, #32] ; CHECK-NEXT: stp q3, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v32i64_v32i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #128] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0, #160] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0, #192] -; NONEON-NOSVE-NEXT: ldp q7, q6, [x0, #224] -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: uzp1 v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: ldp q3, q1, [x0] -; NONEON-NOSVE-NEXT: uzp1 v4.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: ldp q17, q5, [x0, #64] -; NONEON-NOSVE-NEXT: uzp1 v6.4s, v7.4s, v6.4s -; NONEON-NOSVE-NEXT: ldp q16, q7, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q19, q18, [x0, #96] -; NONEON-NOSVE-NEXT: uzp1 v1.4s, v3.4s, v1.4s -; NONEON-NOSVE-NEXT: uzp1 v5.4s, v17.4s, v5.4s -; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NONEON-NOSVE-NEXT: uzp1 v7.4s, v16.4s, v7.4s -; NONEON-NOSVE-NEXT: uzp1 v3.4s, v19.4s, v18.4s -; NONEON-NOSVE-NEXT: uzp1 v2.8h, v4.8h, v6.8h -; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v0.8h -; NONEON-NOSVE-NEXT: uzp1 v1.8h, v1.8h, v7.8h -; NONEON-NOSVE-NEXT: uzp1 v3.8h, v5.8h, v3.8h -; NONEON-NOSVE-NEXT: add v2.8h, v2.8h, v2.8h -; NONEON-NOSVE-NEXT: add v1.8h, v1.8h, v1.8h -; NONEON-NOSVE-NEXT: stp q0, q2, [x1, #32] -; NONEON-NOSVE-NEXT: add v3.8h, v3.8h, v3.8h -; NONEON-NOSVE-NEXT: stp q1, q3, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <32 x i64>, ptr %in %b = trunc <32 x i64> %a to <32 x i16> %c = add <32 x i16> %b, %b @@ -1054,12 +732,6 @@ define <4 x i32> @trunc_v4i64_v4i32(ptr %in) nounwind { ; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v4i64_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: ret %a = load <4 x i64>, ptr %in %b = trunc <4 x i64> %a to <4 x i32> ret <4 x i32> %b @@ -1082,17 +754,6 @@ define void @trunc_v8i64_v8i32(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: add z1.s, z2.s, z2.s ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v8i64_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #32] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: uzp1 v1.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: add v0.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: add v1.4s, v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q1, q0, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <8 x i64>, ptr %in %b = trunc <8 x i64> %a to <8 x i32> %c = add <8 x i32> %b, %b @@ -1128,24 +789,6 @@ define void @trunc_v16i64_v16i32(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: stp q0, q1, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v16i64_v16i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #64] -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0, #96] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0] -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: ldp q6, q1, [x0, #32] -; NONEON-NOSVE-NEXT: uzp1 v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: uzp1 v3.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: uzp1 v1.4s, v6.4s, v1.4s -; NONEON-NOSVE-NEXT: add v0.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: add v2.4s, v2.4s, v2.4s -; NONEON-NOSVE-NEXT: add v3.4s, v3.4s, v3.4s -; NONEON-NOSVE-NEXT: add v1.4s, v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q2, [x1, #32] -; NONEON-NOSVE-NEXT: stp q3, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <16 x i64>, ptr %in %b = trunc <16 x i64> %a to <16 x i32> %c = add <16 x i32> %b, %b @@ -1203,38 +846,6 @@ define void @trunc_v32i64_v32i32(ptr %in, ptr %out) nounwind { ; CHECK-NEXT: stp q2, q3, [x1, #32] ; CHECK-NEXT: stp q4, q0, [x1] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: trunc_v32i64_v32i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #192] -; NONEON-NOSVE-NEXT: ldp q5, q4, [x0, #224] -; NONEON-NOSVE-NEXT: ldp q7, q6, [x0, #128] -; NONEON-NOSVE-NEXT: uzp1 v0.4s, v1.4s, v0.4s -; NONEON-NOSVE-NEXT: ldp q16, q1, [x0, #160] -; NONEON-NOSVE-NEXT: uzp1 v4.4s, v5.4s, v4.4s -; NONEON-NOSVE-NEXT: ldp q17, q5, [x0, #64] -; NONEON-NOSVE-NEXT: uzp1 v6.4s, v7.4s, v6.4s -; NONEON-NOSVE-NEXT: ldp q3, q2, [x0] -; NONEON-NOSVE-NEXT: ldp q18, q7, [x0, #96] -; NONEON-NOSVE-NEXT: uzp1 v1.4s, v16.4s, v1.4s -; NONEON-NOSVE-NEXT: uzp1 v5.4s, v17.4s, v5.4s -; NONEON-NOSVE-NEXT: ldp q17, q16, [x0, #32] -; NONEON-NOSVE-NEXT: uzp1 v2.4s, v3.4s, v2.4s -; NONEON-NOSVE-NEXT: add v0.4s, v0.4s, v0.4s -; NONEON-NOSVE-NEXT: add v4.4s, v4.4s, v4.4s -; NONEON-NOSVE-NEXT: uzp1 v7.4s, v18.4s, v7.4s -; NONEON-NOSVE-NEXT: add v3.4s, v6.4s, v6.4s -; NONEON-NOSVE-NEXT: uzp1 v6.4s, v17.4s, v16.4s -; NONEON-NOSVE-NEXT: add v1.4s, v1.4s, v1.4s -; NONEON-NOSVE-NEXT: stp q0, q4, [x1, #96] -; NONEON-NOSVE-NEXT: add v0.4s, v5.4s, v5.4s -; NONEON-NOSVE-NEXT: add v2.4s, v2.4s, v2.4s -; NONEON-NOSVE-NEXT: add v4.4s, v7.4s, v7.4s -; NONEON-NOSVE-NEXT: stp q3, q1, [x1, #64] -; NONEON-NOSVE-NEXT: add v1.4s, v6.4s, v6.4s -; NONEON-NOSVE-NEXT: stp q0, q4, [x1, #32] -; NONEON-NOSVE-NEXT: stp q2, q1, [x1] -; NONEON-NOSVE-NEXT: ret %a = load <32 x i64>, ptr %in %b = trunc <32 x i64> %a to <32 x i32> %c = add <32 x i32> %b, %b diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll index dd308dfadd80..175731480407 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -15,12 +14,6 @@ define <4 x i8> @shuffle_ext_byone_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: tbl z0.h, { z0.h }, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v4i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v1.8b, v0.8b, v0.8b, #6 -; NONEON-NOSVE-NEXT: trn1 v0.4h, v0.4h, v1.4h -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <4 x i8> %op1, <4 x i8> %op2, <4 x i32> ret <4 x i8> %ret } @@ -35,11 +28,6 @@ define <8 x i8> @shuffle_ext_byone_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: insr z1.b, w8 ; CHECK-NEXT: fmov d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v8i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v0.8b, v0.8b, v1.8b, #7 -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <8 x i8> %op1, <8 x i8> %op2, <8 x i32> ret <8 x i8> %ret } @@ -54,11 +42,6 @@ define <16 x i8> @shuffle_ext_byone_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: insr z1.b, w8 ; CHECK-NEXT: mov z0.d, z1.d ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v16i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #15 -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <16 x i8> %op1, <16 x i8> %op2, <16 x i32> ret <16 x i8> %ret @@ -77,15 +60,6 @@ define void @shuffle_ext_byone_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: insr z3.b, w8 ; CHECK-NEXT: stp q1, q3, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v32i8: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q2, [x1] -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #15 -; NONEON-NOSVE-NEXT: ext v1.16b, v1.16b, v2.16b, #15 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <32 x i8>, ptr %a %op2 = load <32 x i8>, ptr %b %ret = shufflevector <32 x i8> %op1, <32 x i8> %op2, <32 x i32> @shuffle_ext_byone_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; CHECK-NEXT: revw z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v2i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: rev64 v0.2s, v0.2s -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <2 x i16> %op1, <2 x i16> %op2, <2 x i32> ret <2 x i16> %ret } @@ -123,11 +92,6 @@ define <4 x i16> @shuffle_ext_byone_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: insr z1.h, w8 ; CHECK-NEXT: fmov d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v4i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v0.8b, v0.8b, v1.8b, #6 -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <4 x i16> %op1, <4 x i16> %op2, <4 x i32> ret <4 x i16> %ret } @@ -142,11 +106,6 @@ define <8 x i16> @shuffle_ext_byone_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: insr z1.h, w8 ; CHECK-NEXT: mov z0.d, z1.d ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v8i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #14 -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <8 x i16> %op1, <8 x i16> %op2, <8 x i32> ret <8 x i16> %ret } @@ -164,15 +123,6 @@ define void @shuffle_ext_byone_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: insr z3.h, w8 ; CHECK-NEXT: stp q1, q3, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v16i16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q2, [x1] -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #14 -; NONEON-NOSVE-NEXT: ext v1.16b, v1.16b, v2.16b, #14 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x i16>, ptr %a %op2 = load <16 x i16>, ptr %b %ret = shufflevector <16 x i16> %op1, <16 x i16> %op2, <16 x i32> @shuffle_ext_byone_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: insr z1.s, w8 ; CHECK-NEXT: fmov d0, d1 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v2i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v0.8b, v0.8b, v1.8b, #4 -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <2 x i32> %op1, <2 x i32> %op2, <2 x i32> ret <2 x i32> %ret } @@ -210,11 +155,6 @@ define <4 x i32> @shuffle_ext_byone_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: insr z1.s, w8 ; CHECK-NEXT: mov z0.d, z1.d ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v4i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #12 -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <4 x i32> %op1, <4 x i32> %op2, <4 x i32> ret <4 x i32> %ret } @@ -232,15 +172,6 @@ define void @shuffle_ext_byone_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: insr z3.s, w8 ; CHECK-NEXT: stp q1, q3, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v8i32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q2, [x1] -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #12 -; NONEON-NOSVE-NEXT: ext v1.16b, v1.16b, v2.16b, #12 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x i32>, ptr %a %op2 = load <8 x i32>, ptr %b %ret = shufflevector <8 x i32> %op1, <8 x i32> %op2, <8 x i32> @@ -258,11 +189,6 @@ define <2 x i64> @shuffle_ext_byone_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: insr z1.d, x8 ; CHECK-NEXT: mov z0.d, z1.d ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v2i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #8 -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <2 x i64> %op1, <2 x i64> %op2, <2 x i32> ret <2 x i64> %ret } @@ -280,15 +206,6 @@ define void @shuffle_ext_byone_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: insr z3.d, x8 ; CHECK-NEXT: stp q1, q3, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v4i64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q2, [x1] -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #8 -; NONEON-NOSVE-NEXT: ext v1.16b, v1.16b, v2.16b, #8 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x i64>, ptr %a %op2 = load <4 x i64>, ptr %b %ret = shufflevector <4 x i64> %op1, <4 x i64> %op2, <4 x i32> @@ -306,11 +223,6 @@ define <4 x half> @shuffle_ext_byone_v4f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-NEXT: insr z0.h, h2 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v4f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v0.8b, v0.8b, v1.8b, #6 -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <4 x half> %op1, <4 x half> %op2, <4 x i32> ret <4 x half> %ret } @@ -324,11 +236,6 @@ define <8 x half> @shuffle_ext_byone_v8f16(<8 x half> %op1, <8 x half> %op2) { ; CHECK-NEXT: insr z0.h, h2 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v8f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #14 -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <8 x half> %op1, <8 x half> %op2, <8 x i32> ret <8 x half> %ret } @@ -344,15 +251,6 @@ define void @shuffle_ext_byone_v16f16(ptr %a, ptr %b) { ; CHECK-NEXT: insr z3.h, h2 ; CHECK-NEXT: stp q1, q3, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v16f16: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q2, [x1] -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #14 -; NONEON-NOSVE-NEXT: ext v1.16b, v1.16b, v2.16b, #14 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <16 x half>, ptr %a %op2 = load <16 x half>, ptr %b %ret = shufflevector <16 x half> %op1, <16 x half> %op2, <16 x i32> @shuffle_ext_byone_v2f32(<2 x float> %op1, <2 x float> %op2) ; CHECK-NEXT: insr z0.s, s2 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v2f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v0.8b, v0.8b, v1.8b, #4 -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <2 x float> %op1, <2 x float> %op2, <2 x i32> ret <2 x float> %ret } @@ -388,11 +281,6 @@ define <4 x float> @shuffle_ext_byone_v4f32(<4 x float> %op1, <4 x float> %op2) ; CHECK-NEXT: insr z0.s, s2 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v4f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #12 -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <4 x float> %op1, <4 x float> %op2, <4 x i32> ret <4 x float> %ret } @@ -408,15 +296,6 @@ define void @shuffle_ext_byone_v8f32(ptr %a, ptr %b) { ; CHECK-NEXT: insr z3.s, s2 ; CHECK-NEXT: stp q1, q3, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v8f32: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q2, [x1] -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #12 -; NONEON-NOSVE-NEXT: ext v1.16b, v1.16b, v2.16b, #12 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <8 x float>, ptr %a %op2 = load <8 x float>, ptr %b %ret = shufflevector <8 x float> %op1, <8 x float> %op2, <8 x i32> @@ -433,11 +312,6 @@ define <2 x double> @shuffle_ext_byone_v2f64(<2 x double> %op1, <2 x double> %op ; CHECK-NEXT: insr z0.d, d2 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v2f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #8 -; NONEON-NOSVE-NEXT: ret %ret = shufflevector <2 x double> %op1, <2 x double> %op2, <2 x i32> ret <2 x double> %ret } @@ -453,15 +327,6 @@ define void @shuffle_ext_byone_v4f64(ptr %a, ptr %b) { ; CHECK-NEXT: insr z3.d, d2 ; CHECK-NEXT: stp q1, q3, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_v4f64: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q1, q2, [x1] -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v1.16b, #8 -; NONEON-NOSVE-NEXT: ext v1.16b, v1.16b, v2.16b, #8 -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> @@ -480,15 +345,6 @@ define void @shuffle_ext_byone_reverse(ptr %a, ptr %b) { ; CHECK-NEXT: insr z3.d, d2 ; CHECK-NEXT: stp q1, q3, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_byone_reverse: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldp q0, q2, [x0] -; NONEON-NOSVE-NEXT: ldr q1, [x1, #16] -; NONEON-NOSVE-NEXT: ext v1.16b, v1.16b, v0.16b, #8 -; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v2.16b, #8 -; NONEON-NOSVE-NEXT: stp q1, q0, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> @@ -503,13 +359,6 @@ define void @shuffle_ext_invalid(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q1, [x1] ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: shuffle_ext_invalid: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NONEON-NOSVE-NEXT: ldr q1, [x1] -; NONEON-NOSVE-NEXT: stp q0, q1, [x0] -; NONEON-NOSVE-NEXT: ret %op1 = load <4 x double>, ptr %a %op2 = load <4 x double>, ptr %b %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll index 42f3f03a5ea0..337a2134de5b 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s -; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -12,11 +11,6 @@ define fp128 @test_streaming_compatible_register_mov(fp128 %q0, fp128 %q1) { ; CHECK: // %bb.0: ; CHECK-NEXT: mov z0.d, z1.d ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: test_streaming_compatible_register_mov: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: mov v0.16b, v1.16b -; NONEON-NOSVE-NEXT: ret ret fp128 %q1 } @@ -26,11 +20,6 @@ define double @fp_zero_constant() { ; CHECK: // %bb.0: ; CHECK-NEXT: fmov d0, xzr ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fp_zero_constant: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: fmov d0, xzr -; NONEON-NOSVE-NEXT: ret ret double 0.0 } @@ -40,11 +29,6 @@ define <2 x i64> @fixed_vec_zero_constant() { ; CHECK-NEXT: mov z0.d, #0 // =0x0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fixed_vec_zero_constant: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: ret ret <2 x i64> zeroinitializer } @@ -54,10 +38,5 @@ define <2 x double> @fixed_vec_fp_zero_constant() { ; CHECK-NEXT: mov z0.d, #0 // =0x0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret -; -; NONEON-NOSVE-LABEL: fixed_vec_fp_zero_constant: -; NONEON-NOSVE: // %bb.0: -; NONEON-NOSVE-NEXT: movi v0.2d, #0000000000000000 -; NONEON-NOSVE-NEXT: ret ret <2 x double> } -- GitLab From 87235fa9af06b639d7b4b1eb7ac5840fb56cc569 Mon Sep 17 00:00:00 2001 From: Yuxuan Chen Date: Thu, 9 May 2024 08:21:40 -0700 Subject: [PATCH 157/328] [NFC] CoroElide: Refactor `Lowerer` into `CoroIdElider` (#91539) This patch contains no functional changes. The main goal of this patch is to get better clarity out of the code, to make intentions and assumptions clear. One major design problem I had in the past were `Lowerer`. It previously inherited from `coro::LowererBase` but it doesn't use any of the fields or methods from `LowererBase`. It might be an artifact leftover from previous designs of this code. Furthermore, we should clarify that although one such instance is bound to the function, `Lowerer` was dedicated to one `CoroId` instruction at a time. We rely on a sequence of fragile constructs like `CoroBegins.clear(); DestroyAddr.clear()`. This doesn't help understand the code. What's worse is that we have confusing calls like `elideHeapAllocations(CoroId->getFunction(), ...` and it might get confused with `CoroId->getCoroutine()`. The new structure intends to make it clear that we always operate on one `CoroId` at a time, which may have multiple `CoroBegin`s. Such structure doesn't rely on frequent `.clear()` that's prone to miss. --- llvm/lib/Transforms/Coroutines/CoroElide.cpp | 318 ++++++++++--------- 1 file changed, 169 insertions(+), 149 deletions(-) diff --git a/llvm/lib/Transforms/Coroutines/CoroElide.cpp b/llvm/lib/Transforms/Coroutines/CoroElide.cpp index d356a6d2e575..bb244489e4c2 100644 --- a/llvm/lib/Transforms/Coroutines/CoroElide.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroElide.cpp @@ -33,24 +33,47 @@ static cl::opt CoroElideInfoOutputFilename( namespace { // Created on demand if the coro-elide pass has work to do. -struct Lowerer : coro::LowererBase { +class FunctionElideInfo { +public: + FunctionElideInfo(Function *F) : ContainingFunction(F) { + this->collectPostSplitCoroIds(); + } + + bool hasCoroIds() const { return !CoroIds.empty(); } + + const SmallVectorImpl &getCoroIds() const { return CoroIds; } + +private: + Function *ContainingFunction; SmallVector CoroIds; + // Used in canCoroBeginEscape to distinguish coro.suspend switchs. + SmallPtrSet CoroSuspendSwitches; + + void collectPostSplitCoroIds(); + friend class CoroIdElider; +}; + +class CoroIdElider { +public: + CoroIdElider(CoroIdInst *CoroId, FunctionElideInfo &FEI, AAResults &AA, + DominatorTree &DT, OptimizationRemarkEmitter &ORE); + void elideHeapAllocations(uint64_t FrameSize, Align FrameAlign); + bool lifetimeEligibleForElide() const; + bool attemptElide(); + bool canCoroBeginEscape(const CoroBeginInst *, + const SmallPtrSetImpl &) const; + +private: + CoroIdInst *CoroId; + FunctionElideInfo &FEI; + AAResults &AA; + DominatorTree &DT; + OptimizationRemarkEmitter &ORE; + SmallVector CoroBegins; SmallVector CoroAllocs; SmallVector ResumeAddr; DenseMap> DestroyAddr; - SmallPtrSet CoroSuspendSwitches; - - Lowerer(Module &M) : LowererBase(M) {} - - void elideHeapAllocations(Function *F, uint64_t FrameSize, Align FrameAlign, - AAResults &AA); - bool shouldElide(Function *F, DominatorTree &DT) const; - void collectPostSplitCoroIds(Function *F); - bool processCoroId(CoroIdInst *, AAResults &AA, DominatorTree &DT, - OptimizationRemarkEmitter &ORE); - bool hasEscapePath(const CoroBeginInst *, - const SmallPtrSetImpl &) const; }; } // end anonymous namespace @@ -136,14 +159,66 @@ static std::unique_ptr getOrCreateLogFile() { } #endif +void FunctionElideInfo::collectPostSplitCoroIds() { + for (auto &I : instructions(this->ContainingFunction)) { + if (auto *CII = dyn_cast(&I)) + if (CII->getInfo().isPostSplit()) + // If it is the coroutine itself, don't touch it. + if (CII->getCoroutine() != CII->getFunction()) + CoroIds.push_back(CII); + + // Consider case like: + // %0 = call i8 @llvm.coro.suspend(...) + // switch i8 %0, label %suspend [i8 0, label %resume + // i8 1, label %cleanup] + // and collect the SwitchInsts which are used by escape analysis later. + if (auto *CSI = dyn_cast(&I)) + if (CSI->hasOneUse() && isa(CSI->use_begin()->getUser())) { + SwitchInst *SWI = cast(CSI->use_begin()->getUser()); + if (SWI->getNumCases() == 2) + CoroSuspendSwitches.insert(SWI); + } + } +} + +CoroIdElider::CoroIdElider(CoroIdInst *CoroId, FunctionElideInfo &FEI, + AAResults &AA, DominatorTree &DT, + OptimizationRemarkEmitter &ORE) + : CoroId(CoroId), FEI(FEI), AA(AA), DT(DT), ORE(ORE) { + // Collect all coro.begin and coro.allocs associated with this coro.id. + for (User *U : CoroId->users()) { + if (auto *CB = dyn_cast(U)) + CoroBegins.push_back(CB); + else if (auto *CA = dyn_cast(U)) + CoroAllocs.push_back(CA); + } + + // Collect all coro.subfn.addrs associated with coro.begin. + // Note, we only devirtualize the calls if their coro.subfn.addr refers to + // coro.begin directly. If we run into cases where this check is too + // conservative, we can consider relaxing the check. + for (CoroBeginInst *CB : CoroBegins) { + for (User *U : CB->users()) + if (auto *II = dyn_cast(U)) + switch (II->getIndex()) { + case CoroSubFnInst::ResumeIndex: + ResumeAddr.push_back(II); + break; + case CoroSubFnInst::DestroyIndex: + DestroyAddr[CB].push_back(II); + break; + default: + llvm_unreachable("unexpected coro.subfn.addr constant"); + } + } +} + // To elide heap allocations we need to suppress code blocks guarded by // llvm.coro.alloc and llvm.coro.free instructions. -void Lowerer::elideHeapAllocations(Function *F, uint64_t FrameSize, - Align FrameAlign, AAResults &AA) { - LLVMContext &C = F->getContext(); +void CoroIdElider::elideHeapAllocations(uint64_t FrameSize, Align FrameAlign) { + LLVMContext &C = FEI.ContainingFunction->getContext(); BasicBlock::iterator InsertPt = - getFirstNonAllocaInTheEntryBlock(CoroIds.front()->getFunction()) - ->getIterator(); + getFirstNonAllocaInTheEntryBlock(FEI.ContainingFunction)->getIterator(); // Replacing llvm.coro.alloc with false will suppress dynamic // allocation as it is expected for the frontend to generate the code that @@ -161,7 +236,7 @@ void Lowerer::elideHeapAllocations(Function *F, uint64_t FrameSize, // is spilled into the coroutine frame and recreate the alignment information // here. Possibly we will need to do a mini SROA here and break the coroutine // frame into individual AllocaInst recreating the original alignment. - const DataLayout &DL = F->getParent()->getDataLayout(); + const DataLayout &DL = FEI.ContainingFunction->getParent()->getDataLayout(); auto FrameTy = ArrayType::get(Type::getInt8Ty(C), FrameSize); auto *Frame = new AllocaInst(FrameTy, DL.getAllocaAddrSpace(), "", InsertPt); Frame->setAlignment(FrameAlign); @@ -178,8 +253,8 @@ void Lowerer::elideHeapAllocations(Function *F, uint64_t FrameSize, removeTailCallAttribute(Frame, AA); } -bool Lowerer::hasEscapePath(const CoroBeginInst *CB, - const SmallPtrSetImpl &TIs) const { +bool CoroIdElider::canCoroBeginEscape( + const CoroBeginInst *CB, const SmallPtrSetImpl &TIs) const { const auto &It = DestroyAddr.find(CB); assert(It != DestroyAddr.end()); @@ -248,7 +323,7 @@ bool Lowerer::hasEscapePath(const CoroBeginInst *CB, // which means a escape path to normal terminator, it is reasonable to skip // it since coroutine frame doesn't change outside the coroutine body. if (isa(TI) && - CoroSuspendSwitches.count(cast(TI))) { + FEI.CoroSuspendSwitches.count(cast(TI))) { Worklist.push_back(cast(TI)->getSuccessor(1)); Worklist.push_back(cast(TI)->getSuccessor(2)); } else @@ -261,7 +336,7 @@ bool Lowerer::hasEscapePath(const CoroBeginInst *CB, return false; } -bool Lowerer::shouldElide(Function *F, DominatorTree &DT) const { +bool CoroIdElider::lifetimeEligibleForElide() const { // If no CoroAllocs, we cannot suppress allocation, so elision is not // possible. if (CoroAllocs.empty()) @@ -270,6 +345,7 @@ bool Lowerer::shouldElide(Function *F, DominatorTree &DT) const { // Check that for every coro.begin there is at least one coro.destroy directly // referencing the SSA value of that coro.begin along each // non-exceptional path. + // // If the value escaped, then coro.destroy would have been referencing a // memory location storing that value and not the virtual register. @@ -277,7 +353,7 @@ bool Lowerer::shouldElide(Function *F, DominatorTree &DT) const { // First gather all of the terminators for the function. // Consider the final coro.suspend as the real terminator when the current // function is a coroutine. - for (BasicBlock &B : *F) { + for (BasicBlock &B : *FEI.ContainingFunction) { auto *TI = B.getTerminator(); if (TI->getNumSuccessors() != 0 || isa(TI)) @@ -287,91 +363,43 @@ bool Lowerer::shouldElide(Function *F, DominatorTree &DT) const { } // Filter out the coro.destroy that lie along exceptional paths. - SmallPtrSet ReferencedCoroBegins; - for (const auto &It : DestroyAddr) { + for (const auto *CB : CoroBegins) { + auto It = DestroyAddr.find(CB); + + // FIXME: If we have not found any destroys for this coro.begin, we + // disqualify this elide. + if (It == DestroyAddr.end()) + return false; + + const auto &CorrespondingDestroyAddrs = It->second; + // If every terminators is dominated by coro.destroy, we could know the // corresponding coro.begin wouldn't escape. - // - // Otherwise hasEscapePath would decide whether there is any paths from + auto DominatesTerminator = [&](auto *TI) { + return llvm::any_of(CorrespondingDestroyAddrs, [&](auto *Destroy) { + return DT.dominates(Destroy, TI->getTerminator()); + }); + }; + + if (llvm::all_of(Terminators, DominatesTerminator)) + continue; + + // Otherwise canCoroBeginEscape would decide whether there is any paths from // coro.begin to Terminators which not pass through any of the - // coro.destroys. + // coro.destroys. This is a slower analysis. // - // hasEscapePath is relatively slow, so we avoid to run it as much as + // canCoroBeginEscape is relatively slow, so we avoid to run it as much as // possible. - if (llvm::all_of(Terminators, - [&](auto *TI) { - return llvm::any_of(It.second, [&](auto *DA) { - return DT.dominates(DA, TI->getTerminator()); - }); - }) || - !hasEscapePath(It.first, Terminators)) - ReferencedCoroBegins.insert(It.first); + if (canCoroBeginEscape(CB, Terminators)) + return false; } - // If size of the set is the same as total number of coro.begin, that means we - // found a coro.free or coro.destroy referencing each coro.begin, so we can - // perform heap elision. - return ReferencedCoroBegins.size() == CoroBegins.size(); -} - -void Lowerer::collectPostSplitCoroIds(Function *F) { - CoroIds.clear(); - CoroSuspendSwitches.clear(); - for (auto &I : instructions(F)) { - if (auto *CII = dyn_cast(&I)) - if (CII->getInfo().isPostSplit()) - // If it is the coroutine itself, don't touch it. - if (CII->getCoroutine() != CII->getFunction()) - CoroIds.push_back(CII); - - // Consider case like: - // %0 = call i8 @llvm.coro.suspend(...) - // switch i8 %0, label %suspend [i8 0, label %resume - // i8 1, label %cleanup] - // and collect the SwitchInsts which are used by escape analysis later. - if (auto *CSI = dyn_cast(&I)) - if (CSI->hasOneUse() && isa(CSI->use_begin()->getUser())) { - SwitchInst *SWI = cast(CSI->use_begin()->getUser()); - if (SWI->getNumCases() == 2) - CoroSuspendSwitches.insert(SWI); - } - } + // We have checked all CoroBegins and their paths to the terminators without + // finding disqualifying code patterns, so we can perform heap allocations. + return true; } -bool Lowerer::processCoroId(CoroIdInst *CoroId, AAResults &AA, - DominatorTree &DT, OptimizationRemarkEmitter &ORE) { - CoroBegins.clear(); - CoroAllocs.clear(); - ResumeAddr.clear(); - DestroyAddr.clear(); - - // Collect all coro.begin and coro.allocs associated with this coro.id. - for (User *U : CoroId->users()) { - if (auto *CB = dyn_cast(U)) - CoroBegins.push_back(CB); - else if (auto *CA = dyn_cast(U)) - CoroAllocs.push_back(CA); - } - - // Collect all coro.subfn.addrs associated with coro.begin. - // Note, we only devirtualize the calls if their coro.subfn.addr refers to - // coro.begin directly. If we run into cases where this check is too - // conservative, we can consider relaxing the check. - for (CoroBeginInst *CB : CoroBegins) { - for (User *U : CB->users()) - if (auto *II = dyn_cast(U)) - switch (II->getIndex()) { - case CoroSubFnInst::ResumeIndex: - ResumeAddr.push_back(II); - break; - case CoroSubFnInst::DestroyIndex: - DestroyAddr[CB].push_back(II); - break; - default: - llvm_unreachable("unexpected coro.subfn.addr constant"); - } - } - +bool CoroIdElider::attemptElide() { // PostSplit coro.id refers to an array of subfunctions in its Info // argument. ConstantArray *Resumers = CoroId->getInfo().Resumers; @@ -382,63 +410,55 @@ bool Lowerer::processCoroId(CoroIdInst *CoroId, AAResults &AA, replaceWithConstant(ResumeAddrConstant, ResumeAddr); - bool ShouldElide = shouldElide(CoroId->getFunction(), DT); - if (!ShouldElide) - ORE.emit([&]() { - if (auto FrameSizeAndAlign = - getFrameLayout(cast(ResumeAddrConstant))) - return OptimizationRemarkMissed(DEBUG_TYPE, "CoroElide", CoroId) - << "'" << ore::NV("callee", CoroId->getCoroutine()->getName()) - << "' not elided in '" - << ore::NV("caller", CoroId->getFunction()->getName()) - << "' (frame_size=" - << ore::NV("frame_size", FrameSizeAndAlign->first) << ", align=" - << ore::NV("align", FrameSizeAndAlign->second.value()) << ")"; - else - return OptimizationRemarkMissed(DEBUG_TYPE, "CoroElide", CoroId) - << "'" << ore::NV("callee", CoroId->getCoroutine()->getName()) - << "' not elided in '" - << ore::NV("caller", CoroId->getFunction()->getName()) - << "' (frame_size=unknown, align=unknown)"; - }); + bool EligibleForElide = lifetimeEligibleForElide(); auto *DestroyAddrConstant = Resumers->getAggregateElement( - ShouldElide ? CoroSubFnInst::CleanupIndex : CoroSubFnInst::DestroyIndex); + EligibleForElide ? CoroSubFnInst::CleanupIndex + : CoroSubFnInst::DestroyIndex); for (auto &It : DestroyAddr) replaceWithConstant(DestroyAddrConstant, It.second); - if (ShouldElide) { - if (auto FrameSizeAndAlign = - getFrameLayout(cast(ResumeAddrConstant))) { - elideHeapAllocations(CoroId->getFunction(), FrameSizeAndAlign->first, - FrameSizeAndAlign->second, AA); - coro::replaceCoroFree(CoroId, /*Elide=*/true); - NumOfCoroElided++; + auto FrameSizeAndAlign = getFrameLayout(cast(ResumeAddrConstant)); + + auto CallerFunctionName = FEI.ContainingFunction->getName(); + auto CalleeCoroutineName = CoroId->getCoroutine()->getName(); + + if (EligibleForElide && FrameSizeAndAlign) { + elideHeapAllocations(FrameSizeAndAlign->first, FrameSizeAndAlign->second); + coro::replaceCoroFree(CoroId, /*Elide=*/true); + NumOfCoroElided++; + #ifndef NDEBUG if (!CoroElideInfoOutputFilename.empty()) - *getOrCreateLogFile() - << "Elide " << CoroId->getCoroutine()->getName() << " in " - << CoroId->getFunction()->getName() << "\n"; + *getOrCreateLogFile() << "Elide " << CalleeCoroutineName << " in " + << FEI.ContainingFunction->getName() << "\n"; #endif + ORE.emit([&]() { return OptimizationRemark(DEBUG_TYPE, "CoroElide", CoroId) - << "'" << ore::NV("callee", CoroId->getCoroutine()->getName()) - << "' elided in '" - << ore::NV("caller", CoroId->getFunction()->getName()) + << "'" << ore::NV("callee", CalleeCoroutineName) + << "' elided in '" << ore::NV("caller", CallerFunctionName) << "' (frame_size=" << ore::NV("frame_size", FrameSizeAndAlign->first) << ", align=" << ore::NV("align", FrameSizeAndAlign->second.value()) << ")"; }); - } else { - ORE.emit([&]() { - return OptimizationRemarkMissed(DEBUG_TYPE, "CoroElide", CoroId) - << "'" << ore::NV("callee", CoroId->getCoroutine()->getName()) - << "' not elided in '" - << ore::NV("caller", CoroId->getFunction()->getName()) - << "' (frame_size=unknown, align=unknown)"; - }); - } + } else { + ORE.emit([&]() { + auto Remark = OptimizationRemarkMissed(DEBUG_TYPE, "CoroElide", CoroId) + << "'" << ore::NV("callee", CalleeCoroutineName) + << "' not elided in '" + << ore::NV("caller", CallerFunctionName); + + if (FrameSizeAndAlign) + return Remark << "' (frame_size=" + << ore::NV("frame_size", FrameSizeAndAlign->first) + << ", align=" + << ore::NV("align", FrameSizeAndAlign->second.value()) + << ")"; + else + return Remark << "' (frame_size=unknown, align=unknown)"; + }); } return true; @@ -453,11 +473,9 @@ PreservedAnalyses CoroElidePass::run(Function &F, FunctionAnalysisManager &AM) { if (!declaresCoroElideIntrinsics(M)) return PreservedAnalyses::all(); - Lowerer L(M); - L.CoroIds.clear(); - L.collectPostSplitCoroIds(&F); - // If we did not find any coro.id, there is nothing to do. - if (L.CoroIds.empty()) + FunctionElideInfo FEI{&F}; + // Elide is not necessary if there's no coro.id within the function. + if (!FEI.hasCoroIds()) return PreservedAnalyses::all(); AAResults &AA = AM.getResult(F); @@ -465,8 +483,10 @@ PreservedAnalyses CoroElidePass::run(Function &F, FunctionAnalysisManager &AM) { auto &ORE = AM.getResult(F); bool Changed = false; - for (auto *CII : L.CoroIds) - Changed |= L.processCoroId(CII, AA, DT, ORE); + for (auto *CII : FEI.getCoroIds()) { + CoroIdElider CIE(CII, FEI, AA, DT, ORE); + Changed |= CIE.attemptElide(); + } return Changed ? PreservedAnalyses::none() : PreservedAnalyses::all(); } -- GitLab From fe0b7983a2f510cdede22cdf6c9227e32ded6a15 Mon Sep 17 00:00:00 2001 From: Joe Nash Date: Thu, 9 May 2024 11:37:56 -0400 Subject: [PATCH 158/328] [AMDGPU] Create AMDGPUMnemonicAlias tablegen class (#89288) AMDGPUMnemonicAlias is a MnemonicAlias that inherits from GCNPredicateControl, so that we can set predicates on the alias the same way as Instructions. Use AssemblerPredicate instead of Requires on aliases NFC. --- llvm/lib/Target/AMDGPU/AMDGPU.td | 8 +++-- llvm/lib/Target/AMDGPU/BUFInstructions.td | 12 ++++++-- llvm/lib/Target/AMDGPU/DSInstructions.td | 34 ++++++++++++--------- llvm/lib/Target/AMDGPU/EXPInstructions.td | 6 +++- llvm/lib/Target/AMDGPU/FLATInstructions.td | 14 ++++++--- llvm/lib/Target/AMDGPU/MIMGInstructions.td | 21 ++++++++----- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 3 ++ llvm/lib/Target/AMDGPU/SMInstructions.td | 5 +-- llvm/lib/Target/AMDGPU/SOPInstructions.td | 28 ++++++++++++----- llvm/lib/Target/AMDGPU/VOP1Instructions.td | 13 ++++---- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 20 +++++++++--- llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 15 ++++++--- llvm/lib/Target/AMDGPU/VOPCInstructions.td | 26 +++++----------- llvm/lib/Target/AMDGPU/VOPInstructions.td | 10 ++++-- 14 files changed, 137 insertions(+), 78 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index 8abe9920c02c..35b0cb439bfa 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -1918,7 +1918,8 @@ def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">, def HasTrue16BitInsts : Predicate<"Subtarget->hasTrue16BitInsts()">, AssemblerPredicate<(all_of FeatureTrue16BitInsts)>; -def NotHasTrue16BitInsts : True16PredicateClass<"!Subtarget->hasTrue16BitInsts()">; +def NotHasTrue16BitInsts : True16PredicateClass<"!Subtarget->hasTrue16BitInsts()">, + AssemblerPredicate<(all_of (not FeatureTrue16BitInsts))>; // Control use of True16 instructions. The real True16 instructions are // True16 instructions as they are defined in the ISA. Fake True16 @@ -1927,7 +1928,10 @@ def NotHasTrue16BitInsts : True16PredicateClass<"!Subtarget->hasTrue16BitInsts() def UseRealTrue16Insts : True16PredicateClass<"Subtarget->useRealTrue16Insts()">, AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts)>; def UseFakeTrue16Insts : True16PredicateClass<"Subtarget->hasTrue16BitInsts() && " - "!Subtarget->useRealTrue16Insts()">; + "!Subtarget->useRealTrue16Insts()">, + AssemblerPredicate<(all_of FeatureTrue16BitInsts)>; + // FIXME When we default to RealTrue16 instead of Fake, change the line as follows. + // AssemblerPredicate<(all_of FeatureTrue16BitInsts, (not FeatureRealTrue16Insts))>; def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">, AssemblerPredicate<(all_of FeatureVOP3P)>; diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td index 8053d89aeb0a..8eaa113ac181 100644 --- a/llvm/lib/Target/AMDGPU/BUFInstructions.td +++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td @@ -2456,13 +2456,19 @@ class get_BUF_ps { // gfx11 instruction that accept both old and new assembler name. class Mnem_gfx11_gfx12 : - MnemonicAlias, Requires<[isGFX11Plus]>; + AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX11Plus; +} class Mnem_gfx11 : - MnemonicAlias, Requires<[isGFX11Only]>; + AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX11Only; +} class Mnem_gfx12 : - MnemonicAlias, Requires<[isGFX12Plus]>; + AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX12Plus; +} multiclass MUBUF_Real_AllAddr_gfx11_Impl2 op, string real_name> { defm _BOTHEN : MUBUF_Real_gfx11; diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td index d63f04ab6d4c..f2825c48fcec 100644 --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -1213,12 +1213,14 @@ class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12 op, DS_Pseudo ps, int ef, multiclass DS_Real_gfx12 op, string name = !tolower(NAME), bit needAlias = true> { defvar ps = !cast(NAME); - let AssemblerPredicate = isGFX12Plus, DecoderNamespace = "GFX12" in - def _gfx12 : - Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12; - if !and(needAlias, !ne(ps.Mnemonic, name)) then - def : MnemonicAlias, Requires<[isGFX12Plus]>; + if !and(needAlias, !ne(ps.Mnemonic, name)) then + def : AMDGPUMnemonicAlias; + } // End AssemblerPredicate } defm DS_MIN_F32 : DS_Real_gfx12<0x012, "ds_min_num_f32">; @@ -1239,10 +1241,12 @@ defm DS_PK_ADD_BF16 : DS_Real_gfx12<0x09b>; defm DS_PK_ADD_RTN_BF16 : DS_Real_gfx12<0x0ab>; // New aliases added in GFX12 without renaming the instructions. -def : MnemonicAlias<"ds_subrev_u32", "ds_rsub_u32">, Requires<[isGFX12Plus]>; -def : MnemonicAlias<"ds_subrev_rtn_u32", "ds_rsub_rtn_u32">, Requires<[isGFX12Plus]>; -def : MnemonicAlias<"ds_subrev_u64", "ds_rsub_u64">, Requires<[isGFX12Plus]>; -def : MnemonicAlias<"ds_subrev_rtn_u64", "ds_rsub_rtn_u64">, Requires<[isGFX12Plus]>; +let AssemblerPredicate = isGFX12Plus in { + def : AMDGPUMnemonicAlias<"ds_subrev_u32", "ds_rsub_u32">; + def : AMDGPUMnemonicAlias<"ds_subrev_rtn_u32", "ds_rsub_rtn_u32">; + def : AMDGPUMnemonicAlias<"ds_subrev_u64", "ds_rsub_u64">; + def : AMDGPUMnemonicAlias<"ds_subrev_rtn_u64", "ds_rsub_rtn_u64">; +} //===----------------------------------------------------------------------===// // GFX11. @@ -1250,12 +1254,14 @@ def : MnemonicAlias<"ds_subrev_rtn_u64", "ds_rsub_rtn_u64">, Requires<[isGFX12Pl multiclass DS_Real_gfx11 op, string name = !tolower(NAME)> { defvar ps = !cast(NAME); - let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in - def _gfx11 : - Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12; - if !ne(ps.Mnemonic, name) then - def : MnemonicAlias, Requires<[isGFX11Only]>; + if !ne(ps.Mnemonic, name) then + def : AMDGPUMnemonicAlias; + } // End AssemblerPredicate } multiclass DS_Real_gfx11_gfx12 op, string name = !tolower(NAME)> diff --git a/llvm/lib/Target/AMDGPU/EXPInstructions.td b/llvm/lib/Target/AMDGPU/EXPInstructions.td index b73b83031af0..e02652e62a57 100644 --- a/llvm/lib/Target/AMDGPU/EXPInstructions.td +++ b/llvm/lib/Target/AMDGPU/EXPInstructions.td @@ -117,12 +117,16 @@ multiclass EXP_Real_gfx11 { multiclass VEXPORT_Real_gfx12 { defvar ps = !cast(NAME); def _gfx12 : EXP_Real_Row, - EXPe_Row, MnemonicAlias<"exp", "export">, Requires<[isGFX12Plus, HasExportInsts]> { + EXPe_Row { let AssemblerPredicate = isGFX12Only; let DecoderNamespace = "GFX12"; let row = ps.row; let done = ps.done; } + def : AMDGPUMnemonicAlias<"exp", "export"> { + let AssemblerPredicate = isGFX12Plus; + let OtherPredicates = [HasExportInsts]; + } } defm EXP : EXP_Real_gfx11, VEXPORT_Real_gfx12; diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 27d5616565f2..377d48a48e9b 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -2357,7 +2357,9 @@ multiclass FLAT_Real_gfx11 op, multiclass FLAT_Aliases_gfx11 { defvar ps = get_FLAT_ps; if !ne(ps.Mnemonic, name) then - def : MnemonicAlias, Requires<[isGFX11Only]>; + def : AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX11Only; + } } multiclass FLAT_Real_Base_gfx11 op, @@ -2544,10 +2546,12 @@ multiclass VFLAT_Real_gfx12 op, string name = get_FLAT_ps.Mnemoni multiclass VFLAT_Aliases_gfx12 { defvar ps = get_FLAT_ps; - if !ne(ps.Mnemonic, name) then - def : MnemonicAlias, Requires<[isGFX12Only]>; - if !ne(alias, name) then - def : MnemonicAlias, Requires<[isGFX12Only]>; + let AssemblerPredicate = isGFX12Only in { + if !ne(ps.Mnemonic, name) then + def : AMDGPUMnemonicAlias; + if !ne(alias, name) then + def : AMDGPUMnemonicAlias; + } } multiclass VFLAT_Real_Base_gfx12 op, diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td index 23e8be0d5e45..9f6277f1257f 100644 --- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td +++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td @@ -963,11 +963,10 @@ class VIMAGE_Atomic_gfx12 - : VIMAGE_Atomic_gfx12, - MnemonicAlias, Requires<[isGFX12Plus, HasImageInsts]>; + : VIMAGE_Atomic_gfx12; multiclass MIMG_Atomic_Addr_Helper_m ; else - def _V1_gfx12 : VIMAGE_Atomic_gfx12_Renamed ; + def _V1_gfx12 : VIMAGE_Atomic_gfx12_Renamed ; } } let VAddrDwords = 2 in { @@ -1023,7 +1022,7 @@ multiclass MIMG_Atomic_Addr_Helper_m ; else - def _V2_gfx12 : VIMAGE_Atomic_gfx12_Renamed ; + def _V2_gfx12 : VIMAGE_Atomic_gfx12_Renamed ; } } let VAddrDwords = 3 in { @@ -1048,7 +1047,7 @@ multiclass MIMG_Atomic_Addr_Helper_m ; else - def _V3_gfx12 : VIMAGE_Atomic_gfx12_Renamed ; + def _V3_gfx12 : VIMAGE_Atomic_gfx12_Renamed ; } } let VAddrDwords = 4 in { @@ -1073,10 +1072,18 @@ multiclass MIMG_Atomic_Addr_Helper_m ; else - def _V4_gfx12 : VIMAGE_Atomic_gfx12_Renamed ; + def _V4_gfx12 : VIMAGE_Atomic_gfx12_Renamed ; } } } + if !and(op.HAS_GFX12, !not(!empty(renamed))) then + def : AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX12Plus; + let OtherPredicates = [HasImageInsts]; + bit IsAtomicRet; // Unused + MIMGBaseOpcode BaseOpcode; // Unused + int VDataDwords; // Unused + } } multiclass MIMG_Atomic + : MnemonicAlias, GCNPredicateControl; + // Except for the NONE field, this must be kept in sync with the // SIEncodingFamily enum in SIInstrInfo.cpp and the columns of the // getMCOpcodeGen table. diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td index afc9da07bc96..40ba47f88771 100644 --- a/llvm/lib/Target/AMDGPU/SMInstructions.td +++ b/llvm/lib/Target/AMDGPU/SMInstructions.td @@ -1332,8 +1332,9 @@ multiclass SM_Real_Loads_gfx11 op, string ps> { def _IMM_gfx11 : SMEM_Real_Load_gfx11; def _SGPR_gfx11 : SMEM_Real_Load_gfx11; def _SGPR_IMM_gfx11 : SMEM_Real_Load_gfx11; - def : MnemonicAlias(ps#"_IMM").Mnemonic, opName>, - Requires<[isGFX11Plus]>; + def : AMDGPUMnemonicAlias(ps#"_IMM").Mnemonic, opName> { + let AssemblerPredicate = isGFX11Plus; + } } defm S_LOAD_B32 : SM_Real_Loads_gfx11<0x000, "S_LOAD_DWORD">; diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index b05d0018201b..394a5ed991bc 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -1975,7 +1975,9 @@ multiclass SOP1_Real_gfx11 op, string name = !tolower(NAME)> { def _gfx11 : SOP1_Real, Select_gfx11; if !ne(ps.Mnemonic, name) then - def : MnemonicAlias, Requires<[isGFX11Only]>; + def : AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX11Only; + } } multiclass SOP1_Real_gfx12 op, string name = !tolower(NAME)> { @@ -1983,7 +1985,9 @@ multiclass SOP1_Real_gfx12 op, string name = !tolower(NAME)> { def _gfx12 : SOP1_Real, Select_gfx12; if !ne(ps.Mnemonic, name) then - def : MnemonicAlias, Requires<[isGFX12Plus]>; + def : AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX12Plus; + } } multiclass SOP1_M0_Real_gfx12 op> { @@ -2208,7 +2212,9 @@ multiclass SOP2_Real_gfx12 op, string name = !tolower(NAME)> { def _gfx12 : SOP2_Real32, Select_gfx12; if !ne(ps.Mnemonic, name) then - def : MnemonicAlias, Requires<[isGFX12Plus]>; + def : AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX12Plus; + } } defm S_MINIMUM_F32 : SOP2_Real_gfx12<0x04f>; @@ -2225,7 +2231,9 @@ multiclass SOP2_Real_gfx11 op, string name = !tolower(NAME)> { def _gfx11 : SOP2_Real32, Select_gfx11; if !ne(ps.Mnemonic, name) then - def : MnemonicAlias, Requires<[isGFX11Only]>; + def : AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX11Only; + } } multiclass SOP2_Real_gfx11_gfx12 op, string name = !tolower(NAME)> : @@ -2413,7 +2421,9 @@ multiclass SOPK_Real32_gfx12 op, string name = !tolower(NAME)> { def _gfx12 : SOPK_Real32, Select_gfx12; if !ne(ps.Mnemonic, name) then - def : MnemonicAlias, Requires<[isGFX12Plus]>; + def : AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX12Plus; + } } multiclass SOPK_Real32_gfx11 op> { @@ -2542,7 +2552,9 @@ multiclass SOPP_Real_32_gfx12 op, string name = !tolower(NAME)> { def _gfx12 : SOPP_Real_32, Select_gfx12; if !ne(ps.Mnemonic, name) then - def : MnemonicAlias, Requires<[isGFX12Plus]>; + def : AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX12Plus; + } } defm S_BARRIER_WAIT : SOPP_Real_32_gfx12<0x014>; @@ -2568,7 +2580,9 @@ multiclass SOPP_Real_32_gfx11 op, string name = !tolower(NAME)> { Select_gfx11, SOPPRelaxTable<0, ps.KeyName, "_gfx11">; if !ne(ps.Mnemonic, name) then - def : MnemonicAlias, Requires<[isGFX11Only]>; + def : AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX11Only; + } } multiclass SOPP_Real_64_gfx12 op> { diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td index 0efb95d7d15a..012dca22eb4f 100644 --- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -143,14 +143,14 @@ multiclass VOP1Inst ; } // End SubtargetPredicate = isGFX11Plus - def : MnemonicAlias, LetDummies; - def : MnemonicAlias, LetDummies; + def : LetDummies, AMDGPUMnemonicAlias; + def : LetDummies, AMDGPUMnemonicAlias; if P.HasExtSDWA then - def : MnemonicAlias, LetDummies; + def : LetDummies, AMDGPUMnemonicAlias; if P.HasExtDPP then - def : MnemonicAlias, LetDummies; + def : LetDummies, AMDGPUMnemonicAlias; } multiclass VOP1Inst_t16 op, string opName, VOP1_Real_dpp_with_name, VOP1_Real_dpp8_with_name; defvar ps = !cast(opName#"_e32"); - def gfx11_alias : MnemonicAlias, - Requires<[isGFX11Plus]>; + def gfx11_alias : AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX11Plus; + } } multiclass VOP1_Real_NO_VOP3_with_name_gfx12 op, string opName, diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index c001c5de81e0..d2af1753d550 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -1510,7 +1510,9 @@ multiclass VOP2_Real_NO_VOP3_with_name op, string opName, VOP2_Real_dpp_with_name, VOP2_Real_dpp8_with_name; defvar ps = !cast(opName#"_e32"); - def Gen.Suffix#"_alias" : MnemonicAlias, Requires<[Gen.AssemblerPredicate]>; + def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias { + let AssemblerPredicate = Gen.AssemblerPredicate; + } } multiclass VOP2_Real_FULL_with_name op, string opName, @@ -1523,13 +1525,17 @@ multiclass VOP2_Real_NO_DPP_with_name op, string opName, defm NAME : VOP2_Real_e32_with_name, VOP2_Real_e64_with_name; defvar ps = !cast(opName#"_e32"); - def Gen.Suffix#"_alias" : MnemonicAlias, Requires<[Gen.AssemblerPredicate]>; + def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias { + let AssemblerPredicate = Gen.AssemblerPredicate; + } } multiclass VOP2_Real_NO_DPP_with_alias op, string alias> { defm NAME : VOP2_Real_e32, VOP2_Real_e64; - def Gen.Suffix#"_alias" : MnemonicAlias, Requires<[Gen.AssemblerPredicate]>; + def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias { + let AssemblerPredicate = Gen.AssemblerPredicate; + } } //===----------------------------------------------------------------------===// @@ -1550,7 +1556,9 @@ multiclass VOP2_Real_FULL_with_name_gfx12 op, string opName, multiclass VOP2_Real_FULL_t16_with_name_gfx12 op, string opName, string asmName, string alias> { defm NAME : VOP2_Real_FULL_with_name; - def _gfx12_2nd_alias : MnemonicAlias, Requires<[isGFX12Only]>; + def _gfx12_2nd_alias : AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX12Only; + } } multiclass VOP2_Real_NO_DPP_with_name_gfx12 op, string opName, @@ -1609,7 +1617,9 @@ multiclass VOP2_Real_NO_VOP3_with_name_gfx11 op, string opName, VOP2_Real_dpp_with_name, VOP2_Real_dpp8_with_name; defvar ps = !cast(opName#"_e32"); - def _gfx11_alias : MnemonicAlias, Requires<[isGFX11Only]>; + def _gfx11_alias : AMDGPUMnemonicAlias { + let AssemblerPredicate = isGFX11Only; + } } multiclass VOP2_Real_NO_DPP_with_name_gfx11 op, string opName, diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index 71ce36647e45..c3bdbbfc3846 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -814,8 +814,8 @@ let isCommutable = 1, isReMaterializable = 1 in { defm V_PK_MOV_B32 : VOP3PInst<"v_pk_mov_b32", VOP3P_Profile>; } // End isCommutable = 1, isReMaterializable = 1 -def : MnemonicAlias<"v_accvgpr_read", "v_accvgpr_read_b32">; -def : MnemonicAlias<"v_accvgpr_write", "v_accvgpr_write_b32">; +def : AMDGPUMnemonicAlias<"v_accvgpr_read", "v_accvgpr_read_b32">; +def : AMDGPUMnemonicAlias<"v_accvgpr_write", "v_accvgpr_write_b32">; class VOPProfileWMMA : VOP3P_Profile

{ let DstRC = !if(!eq(Suffix, "_w32"), VDst_256, VDst_128); @@ -1481,8 +1481,11 @@ multiclass VOP3P_Real_with_name op, let AsmString = asmName # ps.AsmOperands in def Gen.Suffix : VOP3P_Real_Gen(backing_ps_name), Gen, asmName>, - VOP3Pe_gfx11_gfx12(backing_ps_name).Pfl>, - MnemonicAlias, Requires<[Gen.AssemblerPredicate]>; + VOP3Pe_gfx11_gfx12(backing_ps_name).Pfl>; + + def : AMDGPUMnemonicAlias { + let AssemblerPredicate = Gen.AssemblerPredicate; + } } multiclass VOP3P_Real_dpp op, string backing_ps_name = NAME, @@ -1661,7 +1664,9 @@ multiclass VOP3P_Real_SMFMAC op, string alias> { let AssemblerPredicate = isGFX940Plus; let DecoderNamespace = "GFX8"; } - def : MnemonicAlias(NAME#"_e64").Mnemonic>; + def : AMDGPUMnemonicAlias(NAME#"_e64").Mnemonic> { + let AssemblerPredicate = isGFX940Plus; + } } let SubtargetPredicate = isGFX8GFX9 in { diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td index a0d666b39b2b..ddd6d8b074aa 100644 --- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td @@ -1389,17 +1389,12 @@ multiclass VOPC_Real_with_name op, string OpName, defvar ps32 = !cast(OpName#"_e32"); defvar ps64 = !cast(OpName#"_e64"); let AssemblerPredicate = Gen.AssemblerPredicate in { - // MnemonicAlias and GCNPredicateControl both define the field Predicates, - // so GCNPredicateControl must come after MnemonicAlias because it contains - // the predicates we actually want. - def : MnemonicAlias, - GCNPredicateControl; - def : MnemonicAlias; + def : AMDGPUMnemonicAlias, - GCNPredicateControl; + asm_name, ps64.AsmVariantName>; let DecoderNamespace = Gen.DecoderNamespace in { def _e32#Gen.Suffix : @@ -1523,17 +1518,12 @@ multiclass VOPCX_Real_with_name op, string OpName, defvar ps32 = !cast(OpName#"_nosdst_e32"); defvar ps64 = !cast(OpName#"_nosdst_e64"); let AssemblerPredicate = Gen.AssemblerPredicate in { - // MnemonicAlias and GCNPredicateControl both define the field Predicates, - // so GCNPredicateControl must come after MnemonicAlias because it contains - // the predicates we actually want. - def : MnemonicAlias, - GCNPredicateControl; - def : MnemonicAlias; + def : AMDGPUMnemonicAlias, - GCNPredicateControl; + asm_name, ps64.AsmVariantName>; let DecoderNamespace = Gen.DecoderNamespace in { def _e32#Gen.Suffix diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td index d974aacd7d45..f45ab9bf46db 100644 --- a/llvm/lib/Target/AMDGPU/VOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td @@ -1455,7 +1455,9 @@ multiclass VOP3_Real_with_name op, string opName, VOP3e_gfx11_gfx12; } } - def Gen.Suffix#"_VOP3_alias" : MnemonicAlias, Requires<[Gen.AssemblerPredicate]>, LetDummies; + def Gen.Suffix#"_VOP3_alias" : LetDummies, AMDGPUMnemonicAlias { + let AssemblerPredicate = Gen.AssemblerPredicate; + } } // for READLANE/WRITELANE @@ -1628,8 +1630,10 @@ multiclass VOP3be_Real_with_name_gfx12 op, string opName, IsSingle = !or(isSingle, ps.Pfl.IsSingle) in def _e64_gfx12 : VOP3_Real_Gen, - VOP3be_gfx11_gfx12, - MnemonicAlias, Requires<[isGFX12Only]>; + VOP3be_gfx11_gfx12; + def : AMDGPUMnemonicAlias { + let AssemblerPredicate = GFX12Gen.AssemblerPredicate; + } } multiclass VOP3_Realtriple_with_name_gfx12 op, string opName, -- GitLab From b1cbf4a7c3174471690e20360c2adae173608ae0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20Warzy=C5=84ski?= Date: Thu, 9 May 2024 16:51:32 +0100 Subject: [PATCH 159/328] [mlir][ArmSME] Add comments in tile-spills-and-fills.mlir (#91450) * adds comments in tile-spills-and-fills.mlir * adds comments in ArmSMEIntrinsicOps.td * updates test in tile-spills-and-fills.mlir not to return 2D scalable vectors (e.g. vector<[4]x[4]xf32>) - that's not supported and not needed for that test --- .../Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td | 4 +- .../ArmSMEToLLVM/tile-spills-and-fills.mlir | 48 +++++++++++++++++-- 2 files changed, 45 insertions(+), 7 deletions(-) diff --git a/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td b/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td index f051e03efbcd..0e38325f9891 100644 --- a/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td +++ b/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td @@ -115,7 +115,7 @@ class ArmSME_IntrLoadStoreOp /*immArgPositions=*/[2], /*immArgAttrNames=*/["tile_id"]>; -// Loads +// Loads (from memory to ZA tile slice) class ArmSME_IntrLoadOp : ArmSME_IntrLoadStoreOp, Arguments<(ins Arg:$predicate, @@ -134,7 +134,7 @@ def LLVM_aarch64_sme_ld1w_vert : ArmSME_IntrLoadOp<"ld1w.vert">; def LLVM_aarch64_sme_ld1d_vert : ArmSME_IntrLoadOp<"ld1d.vert">; def LLVM_aarch64_sme_ld1q_vert : ArmSME_IntrLoadOp<"ld1q.vert">; -// Stores +// Stores (ZA tile slice to memory) class ArmSME_IntrStoreOp : ArmSME_IntrLoadStoreOp, Arguments<(ins Arg:$predicate, diff --git a/mlir/test/Conversion/ArmSMEToLLVM/tile-spills-and-fills.mlir b/mlir/test/Conversion/ArmSMEToLLVM/tile-spills-and-fills.mlir index 7a9e6b421575..a9c1a65a296f 100644 --- a/mlir/test/Conversion/ArmSMEToLLVM/tile-spills-and-fills.mlir +++ b/mlir/test/Conversion/ArmSMEToLLVM/tile-spills-and-fills.mlir @@ -72,17 +72,32 @@ func.func @use_too_many_tiles() { // AFTER-LLVM-LOWERING-DAG: %[[C8:.*]] = arith.constant 8 : index // AFTER-LLVM-LOWERING-DAG: %[[VSCALE:.*]] = vector.vscale // AFTER-LLVM-LOWERING-DAG: %[[SVL_H:.*]] = arith.muli %[[VSCALE]], %[[C8]] : index + +/// 0. Create an in-memory-tile +/// Note: 16 is an in-memory tile ID, that is a tile ID >= 16 + // AFTER-LLVM-LOWERING-DAG: %[[TILE_ALLOCA:.*]] = memref.alloca(%[[SVL_H]], %[[SVL_H]]) // AFTER-LLVM-LOWERING-SAME: {arm_sme.in_memory_tile_id = 16 : i32} : memref // // AFTER-LLVM-LOWERING-NOT: scf.for -// Note: 17 is the mask for the 32-bit tile 0. + +/// 1. The following instruciton corresponds to %0 after tile allocation +/// Note: 17 is the mask for the 32-bit tile 0. + // AFTER-LLVM-LOWERING: "arm_sme.intr.zero"() <{tile_mask = 17 : i32}> // // AFTER-LLVM-LOWERING-NOT: scf.for -// Note: 34 is the mask for the 32-bit tile 1. + +/// 2. The following instruciton corresponds to %1 after tile allocation +/// Note: 34 is the mask for the 32-bit tile 1. + // AFTER-LLVM-LOWERING: "arm_sme.intr.zero"() <{tile_mask = 34 : i32}> -// + +/// 3. swap(, tile 0). +/// This can be interpreted as spilling %0 (the 32-bit tile 0), so that +/// %2 can be allocated a tile (16 bit tile 0). Note that this is +/// swapping vector<[8]x[8]xi16> rather than vector<[4]x[4]xi32>. + // AFTER-LLVM-LOWERING: scf.for // AFTER-LLVM-LOWERING-SAME: %[[C0]] to %[[SVL_H]] step %[[C1]] { // AFTER-LLVM-LOWERING: %[[MEM_DESC:.*]] = builtin.unrealized_conversion_cast %[[TILE_ALLOCA]] @@ -92,8 +107,15 @@ func.func @use_too_many_tiles() { // AFTER-LLVM-LOWERING-NEXT: "arm_sme.intr.ld1h.horiz"({{.*}}, %[[SLICE_PTR]], {{.*}}) <{tile_id = 0 : i32}> // AFTER-LLVM-LOWERING-NEXT: vector.store %[[SLICE]], %[[TILE_ALLOCA]] // AFTER-LLVM-LOWERING-NEXT: } -// Note: 85 is the mask for the 16-bit tile 0. + +/// 4. The following instruciton corresponds to %3 after tile allocation +/// Note: 85 is the mask for the 16-bit tile 0. + // AFTER-LLVM-LOWERING: "arm_sme.intr.zero"() <{tile_mask = 85 : i32}> + +/// 5. swap(, tile 0) +/// This can be interpreted as restoring %0. + // AFTER-LLVM-LOWERING: scf.for // AFTER-LLVM-LOWERING-SAME: %[[C0]] to %[[SVL_H]] step %[[C1]] { // AFTER-LLVM-LOWERING: %[[MEM_DESC:.*]] = builtin.unrealized_conversion_cast %[[TILE_ALLOCA]] @@ -116,7 +138,7 @@ func.func @very_excessive_spills(%memref : memref) -> vector<[4]x[4]xf3 %tile = arm_sme.get_tile : vector<[4]x[4]xf32> %mask = vector.constant_mask [4] : vector<[4]xi1> %loadSlice = arm_sme.load_tile_slice %memref[%c0, %c0], %mask, %tile, %c0 : memref, vector<[4]xi1>, vector<[4]x[4]xf32> - return %loadSlice : vector<[4]x[4]xf32> + "test.some_use"(%loadSlice) : (vector<[4]x[4]xf32>) -> () } // AFTER-TILE-ALLOC-LABEL: @very_excessive_spills // AFTER-TILE-ALLOC: arm_sme.get_tile @@ -133,22 +155,38 @@ func.func @very_excessive_spills(%memref : memref) -> vector<[4]x[4]xf3 // AFTER-LLVM-LOWERING-DAG: %[[TILE_ALLOCA:.*]] = memref.alloca(%[[SVL_S]], %[[SVL_S]]) // AFTER-LLVM-LOWERING-SAME: {arm_sme.in_memory_tile_id = 16 : i32} : memref // + +/// 1. Swap %useAllTiles and %tile - note that this will only swap one 32-bit +/// tile (vector<[4]x[4]xf32>) + // AFTER-LLVM-LOWERING: scf.for // AFTER-LLVM-LOWERING-SAME: %[[C0]] to %[[SVL_S]] step %[[C1]] { // AFTER-LLVM-LOWERING: %[[MEM_DESC:.*]] = builtin.unrealized_conversion_cast %[[TILE_ALLOCA]] // AFTER-LLVM-LOWERING: %[[BASE_PTR:.*]] = llvm.extractvalue %[[MEM_DESC]][1] // AFTER-LLVM-LOWERING: %[[SLICE_PTR:.*]] = llvm.getelementptr %[[BASE_PTR]] +// Read ZA tile slice -> vector // AFTER-LLVM-LOWERING: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"{{.*}} <{tile_id = 0 : i32}> +/// Load vector from memory -> ZA tile // AFTER-LLVM-LOWERING-NEXT: "arm_sme.intr.ld1w.horiz"({{.*}}, %[[SLICE_PTR]], {{.*}}) <{tile_id = 0 : i32}> +/// Store ZA tile slice in memory // AFTER-LLVM-LOWERING-NEXT: vector.store %[[SLICE]], %[[TILE_ALLOCA]] // AFTER-LLVM-LOWERING-NEXT: } + +/// 2. Load into %tile // AFTER-LLVM-LOWERING: "arm_sme.intr.ld1w.horiz"{{.*}} <{tile_id = 0 : i32}> + +/// 3. Swap %useAllTiles and %tile - note that this will only swap one 32-bit +/// tile (vector<[4]x[4]xf32>) + // AFTER-LLVM-LOWERING: scf.for // AFTER-LLVM-LOWERING-SAME: %[[C0]] to %[[SVL_S]] step %[[C1]] { // AFTER-LLVM-LOWERING: %[[MEM_DESC:.*]] = builtin.unrealized_conversion_cast %[[TILE_ALLOCA]] // AFTER-LLVM-LOWERING: %[[BASE_PTR:.*]] = llvm.extractvalue %[[MEM_DESC]][1] // AFTER-LLVM-LOWERING: %[[SLICE_PTR:.*]] = llvm.getelementptr %[[BASE_PTR]] +/// Read ZA tile slice -> vector // AFTER-LLVM-LOWERING: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"{{.*}} <{tile_id = 0 : i32}> +/// Load vector from memory -> ZA tile // AFTER-LLVM-LOWERING-NEXT: "arm_sme.intr.ld1w.horiz"({{.*}}, %[[SLICE_PTR]], {{.*}}) <{tile_id = 0 : i32}> +/// Store ZA tile slice in memory // AFTER-LLVM-LOWERING-NEXT: vector.store %[[SLICE]], %[[TILE_ALLOCA]] // AFTER-LLVM-LOWERING-NEXT: } -- GitLab From aeab44d3861dbaac1eb8d68d818f432c86322759 Mon Sep 17 00:00:00 2001 From: Congcong Cai Date: Thu, 9 May 2024 23:59:11 +0800 Subject: [PATCH 160/328] [NFC][clang-tidy] remove magic-numbers-todo.cpp (#91577) This XFAIL test is written in 4 years ago and still todo. 4 is already in DefaultIgnoredIntegerValues so I do not think this XFAIL case can be passed. --- .../checkers/readability/magic-numbers-todo.cpp | 15 --------------- 1 file changed, 15 deletions(-) delete mode 100644 clang-tools-extra/test/clang-tidy/checkers/readability/magic-numbers-todo.cpp diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/magic-numbers-todo.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/magic-numbers-todo.cpp deleted file mode 100644 index 99d9be262a89..000000000000 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/magic-numbers-todo.cpp +++ /dev/null @@ -1,15 +0,0 @@ -// RUN: %check_clang_tidy %s readability-magic-numbers %t -- -// XFAIL: * - -int ProcessSomething(int input); - -int DoWork() -{ - if (((int)4) > ProcessSomething(10)) - // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: 4 is a magic number; consider replacing it with a named constant [readability-magic-numbers] - return 0; - - return 0; -} - - -- GitLab From df21ee4c62e97239560485abdcc42aa340de65f7 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 9 May 2024 17:02:17 +0100 Subject: [PATCH 161/328] [DAG] Add clang-format off/on wrappers around compact switch handlers. NFC. Avoids a problem identified in #90503 --- .../SelectionDAG/SelectionDAGBuilder.cpp | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 9ef02a792fd0..eac4297b89b5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -6700,22 +6700,24 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, case Intrinsic::roundeven: case Intrinsic::canonicalize: { unsigned Opcode; + // clang-format off switch (Intrinsic) { default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. - case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; - case Intrinsic::fabs: Opcode = ISD::FABS; break; - case Intrinsic::sin: Opcode = ISD::FSIN; break; - case Intrinsic::cos: Opcode = ISD::FCOS; break; - case Intrinsic::exp10: Opcode = ISD::FEXP10; break; - case Intrinsic::floor: Opcode = ISD::FFLOOR; break; - case Intrinsic::ceil: Opcode = ISD::FCEIL; break; - case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; - case Intrinsic::rint: Opcode = ISD::FRINT; break; - case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; - case Intrinsic::round: Opcode = ISD::FROUND; break; - case Intrinsic::roundeven: Opcode = ISD::FROUNDEVEN; break; + case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; + case Intrinsic::fabs: Opcode = ISD::FABS; break; + case Intrinsic::sin: Opcode = ISD::FSIN; break; + case Intrinsic::cos: Opcode = ISD::FCOS; break; + case Intrinsic::exp10: Opcode = ISD::FEXP10; break; + case Intrinsic::floor: Opcode = ISD::FFLOOR; break; + case Intrinsic::ceil: Opcode = ISD::FCEIL; break; + case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; + case Intrinsic::rint: Opcode = ISD::FRINT; break; + case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; + case Intrinsic::round: Opcode = ISD::FROUND; break; + case Intrinsic::roundeven: Opcode = ISD::FROUNDEVEN; break; case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break; } + // clang-format on setValue(&I, DAG.getNode(Opcode, sdl, getValue(I.getArgOperand(0)).getValueType(), @@ -6727,6 +6729,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, case Intrinsic::lrint: case Intrinsic::llrint: { unsigned Opcode; + // clang-format off switch (Intrinsic) { default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. case Intrinsic::lround: Opcode = ISD::LROUND; break; @@ -6734,6 +6737,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, case Intrinsic::lrint: Opcode = ISD::LRINT; break; case Intrinsic::llrint: Opcode = ISD::LLRINT; break; } + // clang-format on EVT RetVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); setValue(&I, DAG.getNode(Opcode, sdl, RetVT, -- GitLab From eb177803bfc31ea8ce784c6cf5a881a8bbce0bce Mon Sep 17 00:00:00 2001 From: Yinying Li Date: Thu, 9 May 2024 12:09:40 -0400 Subject: [PATCH 162/328] [mlir][sparse] Change sparse_tensor.print format (#91528) 1. Remove the trailing comma for the last element of memref and add closing parenthesis. 2. Change integration tests to use the new format. --- .../Transforms/SparseTensorRewriting.cpp | 12 +- .../Dialect/SparseTensor/CPU/block.mlir | 18 +- .../SparseTensor/CPU/block_majors.mlir | 24 +-- .../SparseTensor/CPU/concatenate_dim_0.mlir | 20 +-- .../CPU/concatenate_dim_0_permute.mlir | 20 +-- .../SparseTensor/CPU/concatenate_dim_1.mlir | 20 +-- .../CPU/concatenate_dim_1_permute.mlir | 20 +-- .../SparseTensor/CPU/dense_output.mlir | 2 +- .../SparseTensor/CPU/dense_output_bf16.mlir | 2 +- .../SparseTensor/CPU/dense_output_f16.mlir | 2 +- .../SparseTensor/CPU/dual_sparse_conv_2d.mlir | 28 +-- .../Dialect/SparseTensor/CPU/sparse_abs.mlir | 12 +- .../SparseTensor/CPU/sparse_binary.mlir | 106 +++++------ .../SparseTensor/CPU/sparse_block3d.mlir | 24 +-- .../Dialect/SparseTensor/CPU/sparse_cmp.mlir | 20 +-- .../CPU/sparse_collapse_shape.mlir | 52 +++--- .../SparseTensor/CPU/sparse_complex32.mlir | 12 +- .../SparseTensor/CPU/sparse_complex64.mlir | 12 +- .../SparseTensor/CPU/sparse_complex_ops.mlir | 42 ++--- .../CPU/sparse_constant_to_sparse_tensor.mlir | 10 +- .../CPU/sparse_conv_1d_nwc_wcf.mlir | 24 +-- .../SparseTensor/CPU/sparse_conv_2d.mlir | 38 ++-- .../CPU/sparse_conv_2d_nhwc_hwcf.mlir | 38 ++-- .../SparseTensor/CPU/sparse_conv_3d.mlir | 40 ++--- .../CPU/sparse_conv_3d_ndhwc_dhwcf.mlir | 36 ++-- .../SparseTensor/CPU/sparse_conversion.mlir | 168 +++++++++--------- .../CPU/sparse_conversion_block.mlir | 24 +-- .../CPU/sparse_conversion_dyn.mlir | 60 +++---- .../CPU/sparse_conversion_ptr.mlir | 56 +++--- .../SparseTensor/CPU/sparse_coo_test.mlir | 8 +- .../Dialect/SparseTensor/CPU/sparse_dot.mlir | 12 +- .../Dialect/SparseTensor/CPU/sparse_ds.mlir | 20 +-- .../SparseTensor/CPU/sparse_empty.mlir | 24 +-- .../SparseTensor/CPU/sparse_expand.mlir | 6 +- .../SparseTensor/CPU/sparse_expand_shape.mlir | 76 ++++---- .../CPU/sparse_filter_conv2d.mlir | 10 +- .../SparseTensor/CPU/sparse_index.mlir | 74 ++++---- .../SparseTensor/CPU/sparse_insert_1d.mlir | 12 +- .../SparseTensor/CPU/sparse_insert_2d.mlir | 32 ++-- .../SparseTensor/CPU/sparse_insert_3d.mlir | 36 ++-- .../SparseTensor/CPU/sparse_loose.mlir | 9 +- .../SparseTensor/CPU/sparse_matmul.mlir | 112 ++++++------ .../SparseTensor/CPU/sparse_matmul_slice.mlir | 34 ++-- .../SparseTensor/CPU/sparse_matrix_ops.mlir | 60 +++---- .../SparseTensor/CPU/sparse_out_mult_elt.mlir | 10 +- .../CPU/sparse_out_reduction.mlir | 10 +- .../SparseTensor/CPU/sparse_out_simple.mlir | 10 +- .../SparseTensor/CPU/sparse_pack_d.mlir | 26 +-- .../SparseTensor/CPU/sparse_pooling_nhwc.mlir | 18 +- .../SparseTensor/CPU/sparse_print.mlir | 102 +++++------ .../SparseTensor/CPU/sparse_print_3d.mlir | 10 +- .../SparseTensor/CPU/sparse_re_im.mlir | 12 +- .../CPU/sparse_reduce_custom.mlir | 24 +-- .../CPU/sparse_reduce_custom_prod.mlir | 24 +-- .../SparseTensor/CPU/sparse_reshape.mlir | 30 ++-- .../CPU/sparse_sampled_mm_fusion.mlir | 20 +-- .../SparseTensor/CPU/sparse_scale.mlir | 6 +- .../SparseTensor/CPU/sparse_scf_nested.mlir | 28 +-- .../SparseTensor/CPU/sparse_select.mlir | 24 +-- .../CPU/sparse_semiring_select.mlir | 10 +- .../Dialect/SparseTensor/CPU/sparse_sign.mlir | 6 +- .../SparseTensor/CPU/sparse_sorted_coo.mlir | 52 +++--- .../SparseTensor/CPU/sparse_storage.mlir | 46 ++--- .../Dialect/SparseTensor/CPU/sparse_tanh.mlir | 6 +- .../SparseTensor/CPU/sparse_tensor_mul.mlir | 14 +- .../SparseTensor/CPU/sparse_tensor_ops.mlir | 24 +-- .../SparseTensor/CPU/sparse_transpose.mlir | 20 +-- .../CPU/sparse_transpose_coo.mlir | 16 +- .../SparseTensor/CPU/sparse_unary.mlir | 44 ++--- .../SparseTensor/CPU/sparse_vector_ops.mlir | 38 ++-- .../GPU/CUDA/sparse-gemm-lib.mlir | 6 +- .../GPU/CUDA/sparse-sampled-matmul-lib.mlir | 12 +- .../GPU/CUDA/sparse-sddmm-lib.mlir | 12 +- 73 files changed, 1068 insertions(+), 1059 deletions(-) diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp index 025fd3331ba8..da635c257888 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp @@ -830,11 +830,17 @@ private: vector::PrintPunctuation::Comma); rewriter.create(loc, imag, vector::PrintPunctuation::Close); - rewriter.create(loc, vector::PrintPunctuation::Comma); } else { - rewriter.create(loc, val, - vector::PrintPunctuation::Comma); + rewriter.create( + loc, val, vector::PrintPunctuation::NoPunctuation); } + // Terminating comma (except at end). + auto bound = rewriter.create(loc, idxs.back(), step); + Value cond = rewriter.create(loc, arith::CmpIPredicate::ne, + bound, size); + scf::IfOp ifOp = rewriter.create(loc, cond, /*else*/ false); + rewriter.setInsertionPointToStart(&ifOp.getThenRegion().front()); + rewriter.create(loc, vector::PrintPunctuation::Comma); } idxs.pop_back(); rewriter.setInsertionPointAfter(forOp); diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/block.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/block.mlir index f79e7e68f382..ab4fd0e30d65 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/block.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/block.mlir @@ -93,9 +93,9 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 4, 6 ) // CHECK-NEXT: lvl = ( 2, 3, 2, 2 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 3, - // CHECK-NEXT: crd[1] : ( 0, 2, 1, - // CHECK-NEXT: values : ( 1, 2, 0, 3, 4, 0, 0, 5, 6, 7, 8, 0, + // CHECK-NEXT: pos[1] : ( 0, 2, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 1 ) + // CHECK-NEXT: values : ( 1, 2, 0, 3, 4, 0, 0, 5, 6, 7, 8, 0 ) // CHECK-NEXT: ---- sparse_tensor.print %A : tensor @@ -103,9 +103,9 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 2, 3, 2, 2 ) // CHECK-NEXT: lvl = ( 2, 3, 2, 2 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 3, - // CHECK-NEXT: crd[1] : ( 0, 2, 1 - // CHECK-NEXT: values : ( 1, 2, 0, 3, 4, 0, 0, 5, 6, 7, 8, 0, + // CHECK-NEXT: pos[1] : ( 0, 2, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 1 ) + // CHECK-NEXT: values : ( 1, 2, 0, 3, 4, 0, 0, 5, 6, 7, 8, 0 ) // CHECK-NEXT: ---- %t1 = sparse_tensor.reinterpret_map %A : tensor to tensor @@ -115,9 +115,9 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 4, 6 ) // CHECK-NEXT: lvl = ( 2, 3, 2, 2 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 3, - // CHECK-NEXT: crd[1] : ( 0, 2, 1, - // CHECK-NEXT: values : ( 3, 6, 0, 9, 12, 0, 0, 15, 18, 21, 24, 0, + // CHECK-NEXT: pos[1] : ( 0, 2, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 1 ) + // CHECK-NEXT: values : ( 3, 6, 0, 9, 12, 0, 0, 15, 18, 21, 24, 0 ) // CHECK-NEXT: ---- %As = call @scale(%A) : (tensor) -> (tensor) sparse_tensor.print %As : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/block_majors.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/block_majors.mlir index 3534e7d15207..caa0d6a71ed3 100755 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/block_majors.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/block_majors.mlir @@ -108,9 +108,9 @@ module { // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 6, 16 ) // CHECK-NEXT: lvl = ( 2, 4, 3, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 2, - // CHECK-NEXT: crd[1] : ( 0, 2, - // CHECK-NEXT: values : ( 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 5, 0, 0, 0, 0, 0, 0, 0, 0, 6, 7, + // CHECK-NEXT: pos[1] : ( 0, 1, 2 ) + // CHECK-NEXT: crd[1] : ( 0, 2 ) + // CHECK-NEXT: values : ( 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 5, 0, 0, 0, 0, 0, 0, 0, 0, 6, 7 ) // CHECK-NEXT: ---- // func.func @foo1() { @@ -134,9 +134,9 @@ module { // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 6, 16 ) // CHECK-NEXT: lvl = ( 2, 4, 4, 3 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 2, - // CHECK-NEXT: crd[1] : ( 0, 2, - // CHECK-NEXT: values : ( 1, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 5, 0, 0, 0, 0, 6, 0, 0, 7, + // CHECK-NEXT: pos[1] : ( 0, 1, 2 ) + // CHECK-NEXT: crd[1] : ( 0, 2 ) + // CHECK-NEXT: values : ( 1, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 5, 0, 0, 0, 0, 6, 0, 0, 7 ) // CHECK-NEXT: ---- // func.func @foo2() { @@ -160,9 +160,9 @@ module { // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 6, 16 ) // CHECK-NEXT: lvl = ( 4, 2, 3, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 1, 2, 2, - // CHECK-NEXT: crd[1] : ( 0, 1, - // CHECK-NEXT: values : ( 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 5, 0, 0, 0, 0, 0, 0, 0, 0, 6, 7, + // CHECK-NEXT: pos[1] : ( 0, 1, 1, 2, 2 ) + // CHECK-NEXT: crd[1] : ( 0, 1 ) + // CHECK-NEXT: values : ( 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 5, 0, 0, 0, 0, 0, 0, 0, 0, 6, 7 ) // CHECK-NEXT: ---- // func.func @foo3() { @@ -186,9 +186,9 @@ module { // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 6, 16 ) // CHECK-NEXT: lvl = ( 4, 2, 4, 3 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 1, 2, 2, - // CHECK-NEXT: crd[1] : ( 0, 1, - // CHECK-NEXT: values : ( 1, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 5, 0, 0, 0, 0, 6, 0, 0, 7, + // CHECK-NEXT: pos[1] : ( 0, 1, 1, 2, 2 ) + // CHECK-NEXT: crd[1] : ( 0, 1 ) + // CHECK-NEXT: values : ( 1, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 5, 0, 0, 0, 0, 6, 0, 0, 7 ) // CHECK-NEXT: ---- // func.func @foo4() { diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0.mlir index 6a4902057362..7edb76cc8045 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0.mlir @@ -111,11 +111,11 @@ module { // CHECK-NEXT: nse = 18 // CHECK-NEXT: dim = ( 9, 4 ) // CHECK-NEXT: lvl = ( 9, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 9, - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 7, 10, 12, 13, 16, 18, - // CHECK-NEXT: crd[1] : ( 0, 2, 1, 0, 2, 3, 1, 0, 1, 2, 2, 3, 1, 0, 1, 2, 0, 1, - // CHECK-NEXT: values : ( 1, 3, 2, 1, 1, 1, 0.5, 1, 5, 2, 1.5, 1, 3.5, 1, 5, 2, 1, 0.5, + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 7, 10, 12, 13, 16, 18 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 1, 0, 2, 3, 1, 0, 1, 2, 2, 3, 1, 0, 1, 2, 0, 1 ) + // CHECK-NEXT: values : ( 1, 3, 2, 1, 1, 1, 0.5, 1, 5, 2, 1.5, 1, 3.5, 1, 5, 2, 1, 0.5 ) // CHECK-NEXT: ---- // %0 = call @concat_sparse_sparse(%sm24cc, %sm34cd, %sm44dc) @@ -142,11 +142,11 @@ module { // CHECK-NEXT: nse = 18 // CHECK-NEXT: dim = ( 9, 4 ) // CHECK-NEXT: lvl = ( 9, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 9, - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 7, 10, 12, 13, 16, 18, - // CHECK-NEXT: crd[1] : ( 0, 2, 1, 0, 2, 3, 1, 0, 1, 2, 2, 3, 1, 0, 1, 2, 0, 1, - // CHECK-NEXT: values : ( 1, 3, 2, 1, 1, 1, 0.5, 1, 5, 2, 1.5, 1, 3.5, 1, 5, 2, 1, 0.5, + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 7, 10, 12, 13, 16, 18 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 1, 0, 2, 3, 1, 0, 1, 2, 2, 3, 1, 0, 1, 2, 0, 1 ) + // CHECK-NEXT: values : ( 1, 3, 2, 1, 1, 1, 0.5, 1, 5, 2, 1.5, 1, 3.5, 1, 5, 2, 1, 0.5 ) // CHECK-NEXT: ---- // %2 = call @concat_mix_sparse(%m24, %sm34cd, %sm44dc) diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0_permute.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0_permute.mlir index 9c9b0e3330c9..d17e110e2c2d 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0_permute.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0_permute.mlir @@ -144,11 +144,11 @@ module { // CHECK-NEXT: nse = 18 // CHECK-NEXT: dim = ( 9, 4 ) // CHECK-NEXT: lvl = ( 4, 9 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 5, 11, 16, 18 - // CHECK-NEXT: crd[1] : ( 0, 2, 4, 7, 8, 1, 3, 4, 6, 7, 8, 0, 2, 4, 5, 7, 2, 5 - // CHECK-NEXT: values : ( 1, 1, 1, 1, 1, 2, 0.5, 5, 3.5, 5, 0.5, 3, 1, 2, 1.5, 2, 1, 1 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 5, 11, 16, 18 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 4, 7, 8, 1, 3, 4, 6, 7, 8, 0, 2, 4, 5, 7, 2, 5 ) + // CHECK-NEXT: values : ( 1, 1, 1, 1, 1, 2, 0.5, 5, 3.5, 5, 0.5, 3, 1, 2, 1.5, 2, 1, 1 ) // CHECK-NEXT: ---- // %4 = call @concat_sparse_sparse_perm(%sm24ccp, %sm34cd, %sm44dc) @@ -173,11 +173,11 @@ module { // CHECK-NEXT: nse = 18 // CHECK-NEXT: dim = ( 9, 4 ) // CHECK-NEXT: lvl = ( 9, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 9 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 7, 10, 12, 13, 16, 18 - // CHECK-NEXT: crd[1] : ( 0, 2, 1, 0, 2, 3, 1, 0, 1, 2, 2, 3, 1, 0, 1, 2, 0, 1 - // CHECK-NEXT: values : ( 1, 3, 2, 1, 1, 1, 0.5, 1, 5, 2, 1.5, 1, 3.5, 1, 5, 2, 1, 0.5 + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 7, 10, 12, 13, 16, 18 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 1, 0, 2, 3, 1, 0, 1, 2, 2, 3, 1, 0, 1, 2, 0, 1 ) + // CHECK-NEXT: values : ( 1, 3, 2, 1, 1, 1, 0.5, 1, 5, 2, 1.5, 1, 3.5, 1, 5, 2, 1, 0.5 ) // CHECK-NEXT: ---- // %6 = call @concat_mix_sparse_perm(%m24, %sm34cdp, %sm44dc) diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1.mlir index ae067bf18527..c2a4e95e7922 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1.mlir @@ -116,11 +116,11 @@ module { // CHECK-NEXT: nse = 18 // CHECK-NEXT: dim = ( 4, 9 ) // CHECK-NEXT: lvl = ( 4, 9 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 5, 9, 14, 18 - // CHECK-NEXT: crd[1] : ( 0, 2, 4, 7, 8, 0, 2, 4, 6, 1, 4, 5, 6, 7, 2, 3, 5, 6 - // CHECK-NEXT: values : ( 1, 1, 1, 1.5, 1, 3.1, 1, 0.5, 3.5, 2, 1, 1, 5, 2, 5, 2, 1, 0.5 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 5, 9, 14, 18 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 4, 7, 8, 0, 2, 4, 6, 1, 4, 5, 6, 7, 2, 3, 5, 6 ) + // CHECK-NEXT: values : ( 1, 1, 1, 1.5, 1, 3.1, 1, 0.5, 3.5, 2, 1, 1, 5, 2, 5, 2, 1, 0.5 ) // CHECK-NEXT: ---- // %8 = call @concat_sparse_sparse_dim1(%sm42cc, %sm43cd, %sm44dc) @@ -140,11 +140,11 @@ module { // CHECK-NEXT: nse = 18 // CHECK-NEXT: dim = ( 4, 9 ) // CHECK-NEXT: lvl = ( 4, 9 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 5, 9, 14, 18 - // CHECK-NEXT: crd[1] : ( 0, 2, 4, 7, 8, 0, 2, 4, 6, 1, 4, 5, 6, 7, 2, 3, 5, 6 - // CHECK-NEXT: values : ( 1, 1, 1, 1.5, 1, 3.1, 1, 0.5, 3.5, 2, 1, 1, 5, 2, 5, 2, 1, 0.5 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 5, 9, 14, 18 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 4, 7, 8, 0, 2, 4, 6, 1, 4, 5, 6, 7, 2, 3, 5, 6 ) + // CHECK-NEXT: values : ( 1, 1, 1, 1.5, 1, 3.1, 1, 0.5, 3.5, 2, 1, 1, 5, 2, 5, 2, 1, 0.5 ) // CHECK-NEXT: ---- // %10 = call @concat_mix_sparse_dim1(%m42, %sm43cd, %sm44dc) diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1_permute.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1_permute.mlir index ce746f27c4d8..8fe7e08a66d3 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1_permute.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1_permute.mlir @@ -130,11 +130,11 @@ module { // CHECK-NEXT: nse = 18 // CHECK-NEXT: dim = ( 4, 9 ) // CHECK-NEXT: lvl = ( 9, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 9 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 7, 10, 12, 15, 17, 18 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 3, 3, 0, 1, 2, 2, 3, 1, 2, 3, 0, 2, 0 - // CHECK-NEXT: values : ( 1, 3.1, 2, 1, 1, 5, 2, 1, 0.5, 1, 1, 1, 3.5, 5, 0.5, 1.5, 2, 1 + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 7, 10, 12, 15, 17, 18 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 3, 3, 0, 1, 2, 2, 3, 1, 2, 3, 0, 2, 0 ) + // CHECK-NEXT: values : ( 1, 3.1, 2, 1, 1, 5, 2, 1, 0.5, 1, 1, 1, 3.5, 5, 0.5, 1.5, 2, 1 ) // CHECK-NEXT: ---- // %12 = call @concat_sparse_sparse_perm_dim1(%sm42ccp, %sm43cd, %sm44dc) @@ -154,11 +154,11 @@ module { // CHECK-NEXT: nse = 18 // CHECK-NEXT: dim = ( 4, 9 ) // CHECK-NEXT: lvl = ( 4, 9 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 5, 9, 14, 18 - // CHECK-NEXT: crd[1] : ( 0, 2, 4, 7, 8, 0, 2, 4, 6, 1, 4, 5, 6, 7, 2, 3, 5, 6 - // CHECK-NEXT: values : ( 1, 1, 1, 1.5, 1, 3.1, 1, 0.5, 3.5, 2, 1, 1, 5, 2, 5, 2, 1, 0.5 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 5, 9, 14, 18 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 4, 7, 8, 0, 2, 4, 6, 1, 4, 5, 6, 7, 2, 3, 5, 6 ) + // CHECK-NEXT: values : ( 1, 1, 1, 1.5, 1, 3.1, 1, 0.5, 3.5, 2, 1, 1, 5, 2, 5, 2, 1, 0.5 ) // CHECK-NEXT: ---- // %14 = call @concat_mix_sparse_perm_dim1(%m42, %sm43cdp, %sm44dc) diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output.mlir index b2bbc64f1688..d00d4c87f9bd 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output.mlir @@ -108,7 +108,7 @@ module { // CHECK-NEXT: nse = 25 // CHECK-NEXT: dim = ( 5, 5 ) // CHECK-NEXT: lvl = ( 5, 5 ) - // CHECK-NEXT: values : ( 2, 0, 0, 2.8, 0, 0, 4, 0, 0, 5, 0, 0, 6, 0, 0, 8.2, 0, 0, 8, 0, 0, 10.4, 0, 0, 10, + // CHECK-NEXT: values : ( 2, 0, 0, 2.8, 0, 0, 4, 0, 0, 5, 0, 0, 6, 0, 0, 8.2, 0, 0, 8, 0, 0, 10.4, 0, 0, 10 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_bf16.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_bf16.mlir index ca9df03c69ee..49f182ddb1d4 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_bf16.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_bf16.mlir @@ -95,7 +95,7 @@ module { // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: values : ( 1, 11, 0, 2, 13, 0, 0, 0, 0, 0, 14, 3, 0, 0, 0, 0, 15, 4, 16, 0, 5, 6, 0, 0, 0, 0, 0, 0, 7, 8, 0, 9, + // CHECK-NEXT: values : ( 1, 11, 0, 2, 13, 0, 0, 0, 0, 0, 14, 3, 0, 0, 0, 0, 15, 4, 16, 0, 5, 6, 0, 0, 0, 0, 0, 0, 7, 8, 0, 9 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_f16.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_f16.mlir index 4f5e6ddd48d8..cc2a3733c863 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_f16.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_f16.mlir @@ -96,7 +96,7 @@ module { // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: values : ( 1, 11, 0, 2, 13, 0, 0, 0, 0, 0, 14, 3, 0, 0, 0, 0, 15, 4, 16, 0, 5, 6, 0, 0, 0, 0, 0, 0, 7, 8, 0, 9, + // CHECK-NEXT: values : ( 1, 11, 0, 2, 13, 0, 0, 0, 0, 0, 14, 3, 0, 0, 0, 0, 15, 4, 16, 0, 5, 6, 0, 0, 0, 0, 0, 0, 7, 8, 0, 9 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/dual_sparse_conv_2d.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/dual_sparse_conv_2d.mlir index c645ca656720..f33a3abc7a5f 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/dual_sparse_conv_2d.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/dual_sparse_conv_2d.mlir @@ -161,11 +161,11 @@ module { // CHECK-NEXT: nse = 36 // CHECK-NEXT: dim = ( 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %2 : tensor<6x6xi32, #DCSR> @@ -177,9 +177,9 @@ module { // CHECK-NEXT: nse = 36 // CHECK-NEXT: dim = ( 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6 ) - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %3 : tensor<6x6xi32, #CSR> @@ -191,9 +191,9 @@ module { // CHECK-NEXT: nse = 36 // CHECK-NEXT: dim = ( 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %4 : tensor<6x6xi32, #CDR> @@ -205,9 +205,9 @@ module { // CHECK-NEXT: nse = 36 // CHECK-NEXT: dim = ( 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6 ) - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: values : ( 0, -1, 0, -1, 0, 2, 0, 0, -1, 0, 0, -1, -1, 1, 1, 0, 3, 3, -6, 0, 0, 0, 6, 0, -1, 1, 0, 0, -3, -3, 6, 0, 0, 0, -6, 0 + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: values : ( 0, -1, 0, -1, 0, 2, 0, 0, -1, 0, 0, -1, -1, 1, 1, 0, 3, 3, -6, 0, 0, 0, 6, 0, -1, 1, 0, 0, -3, -3, 6, 0, 0, 0, -6, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %5 : tensor<6x6xi32, #CSC> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_abs.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_abs.mlir index 4228bcdb1c0d..707c6c34d8dc 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_abs.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_abs.mlir @@ -120,18 +120,18 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 12, - // CHECK-NEXT: crd[0] : ( 0, 3, 5, 11, 13, 17, 18, 20, 21, 28, 29, 31, - // CHECK-NEXT: values : ( 1.5, 1.5, 10.2, 11.3, 1, 1, nan, nan, inf, inf, 0, 0, + // CHECK-NEXT: pos[0] : ( 0, 12 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 5, 11, 13, 17, 18, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 1.5, 1.5, 10.2, 11.3, 1, 1, nan, nan, inf, inf, 0, 0 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 9, - // CHECK-NEXT: crd[0] : ( 0, 3, 5, 11, 13, 17, 18, 21, 31, - // CHECK-NEXT: values : ( -2147483648, 2147483647, 1000, 1, 0, 1, 1000, 2147483646, 2147483647, + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 5, 11, 13, 17, 18, 21, 31 ) + // CHECK-NEXT: values : ( -2147483648, 2147483647, 1000, 1, 0, 1, 1000, 2147483646, 2147483647 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_binary.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_binary.mlir index 36701b4385a2..69be2ee75221 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_binary.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_binary.mlir @@ -453,131 +453,131 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 9, - // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31, - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 10 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 10, - // CHECK-NEXT: crd[0] : ( 1, 3, 4, 10, 16, 18, 21, 28, 29, 31, - // CHECK-NEXT: values : ( 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + // CHECK-NEXT: pos[0] : ( 0, 10 ) + // CHECK-NEXT: crd[0] : ( 1, 3, 4, 10, 16, 18, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 14 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 14, - // CHECK-NEXT: crd[0] : ( 0, 1, 3, 4, 10, 11, 16, 17, 18, 20, 21, 28, 29, 31, - // CHECK-NEXT: values : ( 1, 11, 2, 13, 14, 3, 15, 4, 16, 5, 6, 7, 8, 9, + // CHECK-NEXT: pos[0] : ( 0, 14 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 3, 4, 10, 11, 16, 17, 18, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 1, 11, 2, 13, 14, 3, 15, 4, 16, 5, 6, 7, 8, 9 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 9, - // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31, - // CHECK-NEXT: values : ( 0, 6, 3, 28, 0, 6, 56, 72, 9, + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 0, 6, 3, 28, 0, 6, 56, 72, 9 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 4, - // CHECK-NEXT: crd[0] : ( 0, 11, 17, 20, - // CHECK-NEXT: values : ( 1, 3, 4, 5, + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 11, 17, 20 ) + // CHECK-NEXT: values : ( 1, 3, 4, 5 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 9, - // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31, - // CHECK-NEXT: values : ( 0, 3, 11, 17, 20, 21, 28, 29, 31, + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 0, 1, 2, - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, - // CHECK-NEXT: crd[1] : ( 0, 7, 0, 6, 1, 7, - // CHECK-NEXT: values : ( 7, -5, -4, -3, -2, 7, + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 7, 0, 6, 1, 7 ) + // CHECK-NEXT: values : ( 7, -5, -4, -3, -2, 7 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 10 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 4, - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, - // CHECK-NEXT: pos[1] : ( 0, 3, 4, 8, 10, - // CHECK-NEXT: crd[1] : ( 0, 2, 3, 1, 0, 1, 2, 3, 0, 1, - // CHECK-NEXT: values : ( 2, 4, 1, 2.5, 1, 5, 2, 4, 5, 4, + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 4, 8, 10 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 3, 1, 0, 1, 2, 3, 0, 1 ) + // CHECK-NEXT: values : ( 2, 4, 1, 2.5, 1, 5, 2, 4, 5, 4 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 10 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 4, - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, - // CHECK-NEXT: pos[1] : ( 0, 3, 4, 8, 10, - // CHECK-NEXT: crd[1] : ( 0, 2, 3, 1, 0, 1, 2, 3, 0, 1, - // CHECK-NEXT: values : ( 2, 4, 1, 2.5, 1, 5, 2, 4, 5, 4, + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 4, 8, 10 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 3, 1, 0, 1, 2, 3, 0, 1 ) + // CHECK-NEXT: values : ( 2, 4, 1, 2.5, 1, 5, 2, 4, 5, 4 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 10 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 4, - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, - // CHECK-NEXT: pos[1] : ( 0, 3, 4, 8, 10, - // CHECK-NEXT: crd[1] : ( 0, 2, 3, 1, 0, 1, 2, 3, 0, 1, - // CHECK-NEXT: values : ( 2, 4, 1, 2.5, -1, -5, 2, 4, 1, 4, + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 4, 8, 10 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 3, 1, 0, 1, 2, 3, 0, 1 ) + // CHECK-NEXT: values : ( 2, 4, 1, 2.5, -1, -5, 2, 4, 1, 4 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 10 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 4, - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, - // CHECK-NEXT: pos[1] : ( 0, 3, 4, 8, 10, - // CHECK-NEXT: crd[1] : ( 0, 2, 3, 1, 0, 1, 2, 3, 0, 1, - // CHECK-NEXT: values : ( 0, 1, -1, 1, -1, -2, -2, 2, 1, 2, + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 4, 8, 10 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 3, 1, 0, 1, 2, 3, 0, 1 ) + // CHECK-NEXT: values : ( 0, 1, -1, 1, -1, -2, -2, 2, 1, 2 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 0, 1, 3, - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 4, - // CHECK-NEXT: crd[1] : ( 0, 2, 1, 0, - // CHECK-NEXT: values : ( 1, 0, 0, 0, + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 4 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 1, 0 ) + // CHECK-NEXT: values : ( 1, 0, 0, 0 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 0, 2, 3, - // CHECK-NEXT: pos[1] : ( 0, 1, 5, 6, - // CHECK-NEXT: crd[1] : ( 3, 0, 1, 2, 3, 1, - // CHECK-NEXT: values : ( -1, -1, -5, -2, 4, 4, + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 5, 6 ) + // CHECK-NEXT: crd[1] : ( 3, 0, 1, 2, 3, 1 ) + // CHECK-NEXT: values : ( -1, -1, -5, -2, 4, 4 ) // sparse_tensor.print %sv1 : tensor sparse_tensor.print %sv2 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_block3d.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_block3d.mlir index 467b671500e1..ac5f773d6718 100755 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_block3d.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_block3d.mlir @@ -98,11 +98,11 @@ module { // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 4, 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 3 - // CHECK-NEXT: pos[1] : ( 0, 1, 2 - // CHECK-NEXT: crd[1] : ( 0, 2 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 2 ) + // CHECK-NEXT: crd[1] : ( 0, 2 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8 ) // CHECK-NEXT: ---- // sparse_tensor.print %a : tensor<4x4x4xi32, #Sparse1> @@ -116,13 +116,13 @@ module { // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 4, 4, 4 ) // CHECK-NEXT: lvl = ( 2, 2, 2, 2, 2, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 1 - // CHECK-NEXT: pos[1] : ( 0, 2, 4 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1 - // CHECK-NEXT: pos[2] : ( 0, 1, 2, 3, 4 - // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1 - // CHECK-NEXT: values : ( 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 5, 0, 0, 0, 6, 0, 3, 0, 0, 0, 4, 0, 0, 0, 0, 0, 7, 0, 0, 0, 8, 0 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1 ) + // CHECK-NEXT: pos[2] : ( 0, 1, 2, 3, 4 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1 ) + // CHECK-NEXT: values : ( 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 5, 0, 0, 0, 6, 0, 3, 0, 0, 0, 4, 0, 0, 0, 0, 0, 7, 0, 0, 0, 8, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %b : tensor<4x4x4xi32, #Sparse2> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_cmp.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_cmp.mlir index 732bde55be91..edeffea21171 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_cmp.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_cmp.mlir @@ -132,22 +132,22 @@ module { // CHECK-NEXT: nse = 16 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12, 16 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12, 16 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 11 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 9, 11 - // CHECK-NEXT: crd[1] : ( 1, 2, 3, 0, 1, 0, 1, 2, 3, 0, 1 - // CHECK-NEXT: values : ( 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 0 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 9, 11 ) + // CHECK-NEXT: crd[1] : ( 1, 2, 3, 0, 1, 0, 1, 2, 3, 0, 1 ) + // CHECK-NEXT: values : ( 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 0 ) // CHECK-NEXT: ---- // %v = vector.transfer_read %all_dn_out[%c0, %c0], %d0 diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_collapse_shape.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_collapse_shape.mlir index cae599fa30ae..12132155e7cb 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_collapse_shape.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_collapse_shape.mlir @@ -162,18 +162,18 @@ module { // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 12 ) // CHECK-NEXT: lvl = ( 12 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 2, 4, 6, 8, 10 - // CHECK-NEXT: values : ( 1.1, 1.3, 2.1, 2.3, 3.1, 3.3 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 4, 6, 8, 10 ) + // CHECK-NEXT: values : ( 1.1, 1.3, 2.1, 2.3, 3.1, 3.3 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 12 ) // CHECK-NEXT: lvl = ( 12 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 2, 4, 6, 8, 10 - // CHECK-NEXT: values : ( 1.1, 1.3, 2.1, 2.3, 3.1, 3.3 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 4, 6, 8, 10 ) + // CHECK-NEXT: values : ( 1.1, 1.3, 2.1, 2.3, 3.1, 3.3 ) // CHECK-NEXT: ---- // // CHECK: ( ( 1, 0, 3, 0, 5, 0, 7, 0, 9, 0 ), ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ), ( 21, 0, 23, 0, 25, 0, 27, 0, 29, 0 ), ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ), ( 41, 0, 43, 0, 45, 0, 47, 0, 49, 0 ), ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ) ) @@ -183,22 +183,22 @@ module { // CHECK-NEXT: nse = 15 // CHECK-NEXT: dim = ( 6, 10 ) // CHECK-NEXT: lvl = ( 6, 10 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 2, 4 - // CHECK-NEXT: pos[1] : ( 0, 5, 10, 15 - // CHECK-NEXT: crd[1] : ( 0, 2, 4, 6, 8, 0, 2, 4, 6, 8, 0, 2, 4, 6, 8 - // CHECK-NEXT: values : ( 1, 3, 5, 7, 9, 21, 23, 25, 27, 29, 41, 43, 45, 47, 49 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 4 ) + // CHECK-NEXT: pos[1] : ( 0, 5, 10, 15 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 4, 6, 8, 0, 2, 4, 6, 8, 0, 2, 4, 6, 8 ) + // CHECK-NEXT: values : ( 1, 3, 5, 7, 9, 21, 23, 25, 27, 29, 41, 43, 45, 47, 49 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 15 // CHECK-NEXT: dim = ( 6, 10 ) // CHECK-NEXT: lvl = ( 6, 10 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 2, 4 - // CHECK-NEXT: pos[1] : ( 0, 5, 10, 15 - // CHECK-NEXT: crd[1] : ( 0, 2, 4, 6, 8, 0, 2, 4, 6, 8, 0, 2, 4, 6, 8 - // CHECK-NEXT: values : ( 1, 3, 5, 7, 9, 21, 23, 25, 27, 29, 41, 43, 45, 47, 49 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 4 ) + // CHECK-NEXT: pos[1] : ( 0, 5, 10, 15 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 4, 6, 8, 0, 2, 4, 6, 8, 0, 2, 4, 6, 8 ) + // CHECK-NEXT: values : ( 1, 3, 5, 7, 9, 21, 23, 25, 27, 29, 41, 43, 45, 47, 49 ) // CHECK-NEXT: ---- // // CHECK: ( ( 1, 0, 3, 0, 5, 0, 7, 0, 9, 0 ), ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ), ( 21, 0, 23, 0, 25, 0, 27, 0, 29, 0 ), ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ), ( 41, 0, 43, 0, 45, 0, 47, 0, 49, 0 ), ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ) ) @@ -208,22 +208,22 @@ module { // CHECK-NEXT: nse = 15 // CHECK-NEXT: dim = ( 6, 10 ) // CHECK-NEXT: lvl = ( 6, 10 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 2, 4 - // CHECK-NEXT: pos[1] : ( 0, 5, 10, 15 - // CHECK-NEXT: crd[1] : ( 0, 2, 4, 6, 8, 0, 2, 4, 6, 8, 0, 2, 4, 6, 8 - // CHECK-NEXT: values : ( 1, 3, 5, 7, 9, 21, 23, 25, 27, 29, 41, 43, 45, 47, 49 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 4 ) + // CHECK-NEXT: pos[1] : ( 0, 5, 10, 15 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 4, 6, 8, 0, 2, 4, 6, 8, 0, 2, 4, 6, 8 ) + // CHECK-NEXT: values : ( 1, 3, 5, 7, 9, 21, 23, 25, 27, 29, 41, 43, 45, 47, 49 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 15 // CHECK-NEXT: dim = ( 6, 10 ) // CHECK-NEXT: lvl = ( 6, 10 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 2, 4 - // CHECK-NEXT: pos[1] : ( 0, 5, 10, 15 - // CHECK-NEXT: crd[1] : ( 0, 2, 4, 6, 8, 0, 2, 4, 6, 8, 0, 2, 4, 6, 8 - // CHECK-NEXT: values : ( 1, 3, 5, 7, 9, 21, 23, 25, 27, 29, 41, 43, 45, 47, 49 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 4 ) + // CHECK-NEXT: pos[1] : ( 0, 5, 10, 15 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 4, 6, 8, 0, 2, 4, 6, 8, 0, 2, 4, 6, 8 ) + // CHECK-NEXT: values : ( 1, 3, 5, 7, 9, 21, 23, 25, 27, 29, 41, 43, 45, 47, 49 ) // CHECK-NEXT: ---- // %v0 = vector.transfer_read %collapse0[%c0], %df: tensor<12xf64>, vector<12xf64> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex32.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex32.mlir index 9747da27f9e9..087360f7a1ce 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex32.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex32.mlir @@ -104,18 +104,18 @@ module { // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 4, - // CHECK-NEXT: crd[0] : ( 0, 1, 28, 31, - // CHECK-NEXT: values : ( ( 511.13, 2 ), ( 1, 0 ), ( 5, 4 ), ( 8, 6 ), + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 28, 31 ) + // CHECK-NEXT: values : ( ( 511.13, 2 ), ( 1, 0 ), ( 5, 4 ), ( 8, 6 ) ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 2 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 2, - // CHECK-NEXT: crd[0] : ( 28, 31, - // CHECK-NEXT: values : ( ( 6, 8 ), ( 15, 18 ), + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 28, 31 ) + // CHECK-NEXT: values : ( ( 6, 8 ), ( 15, 18 ) ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor, #SparseVector> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex64.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex64.mlir index d4b43eb57676..3f748015c958 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex64.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex64.mlir @@ -101,18 +101,18 @@ module { // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 4, - // CHECK-NEXT: crd[0] : ( 0, 1, 28, 31, - // CHECK-NEXT: values : ( ( 511.13, 2 ), ( 1, 0 ), ( 5, 4 ), ( 8, 6 ), + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 28, 31 ) + // CHECK-NEXT: values : ( ( 511.13, 2 ), ( 1, 0 ), ( 5, 4 ), ( 8, 6 ) ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 2 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 2, - // CHECK-NEXT: crd[0] : ( 28, 31, - // CHECK-NEXT: values : ( ( 6, 8 ), ( 15, 18 ), + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 28, 31 ) + // CHECK-NEXT: values : ( ( 6, 8 ), ( 15, 18 ) ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor, #SparseVector> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex_ops.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex_ops.mlir index c4fc8b080787..2326234bc06c 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex_ops.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex_ops.mlir @@ -198,63 +198,63 @@ module { // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 4, - // CHECK-NEXT: crd[0] : ( 0, 1, 28, 31, - // CHECK-NEXT: values : ( ( -5.13, 2 ), ( 1, 0 ), ( 1, 4 ), ( 8, 6 ), + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 28, 31 ) + // CHECK-NEXT: values : ( ( -5.13, 2 ), ( 1, 0 ), ( 1, 4 ), ( 8, 6 ) ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 0, 28, 31, - // CHECK-NEXT: values : ( ( 3.43887, 1.47097 ), ( 3.85374, -27.0168 ), ( -193.43, 57.2184 ), + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 28, 31 ) + // CHECK-NEXT: values : ( ( 3.43887, 1.47097 ), ( 3.85374, -27.0168 ), ( -193.43, 57.2184 ) ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 0, 28, 31, - // CHECK-NEXT: values : ( ( 0.433635, 2.30609 ), ( 2, 1 ), ( 2.53083, 1.18538 ), + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 28, 31 ) + // CHECK-NEXT: values : ( ( 0.433635, 2.30609 ), ( 2, 1 ), ( 2.53083, 1.18538 ) ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 1, 28, 31, - // CHECK-NEXT: values : ( ( 0.761594, 0 ), ( -0.964028, 0 ), ( 0.995055, 0 ), + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 1, 28, 31 ) + // CHECK-NEXT: values : ( ( 0.761594, 0 ), ( -0.964028, 0 ), ( 0.995055, 0 ) ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 0, 28, 31, - // CHECK-NEXT: values : ( ( -5.13, 2 ), ( 3, 4 ), ( 5, 6 ), + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 28, 31 ) + // CHECK-NEXT: values : ( ( -5.13, 2 ), ( 3, 4 ), ( 5, 6 ) ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 0, 28, 31, - // CHECK-NEXT: values : ( ( -2.565, 1 ), ( 1.5, 2 ), ( 2.5, 3 ), + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 28, 31 ) + // CHECK-NEXT: values : ( ( -2.565, 1 ), ( 1.5, 2 ), ( 2.5, 3 ) ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 0, 28, 31, - // CHECK-NEXT: values : ( 5.50608, 5, 7.81025, + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 28, 31 ) + // CHECK-NEXT: values : ( 5.50608, 5, 7.81025 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor, #SparseVector> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_constant_to_sparse_tensor.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_constant_to_sparse_tensor.mlir index abdbf80d0bc4..51c13085cf3e 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_constant_to_sparse_tensor.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_constant_to_sparse_tensor.mlir @@ -56,11 +56,11 @@ module { // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 10, 8 ) // CHECK-NEXT: lvl = ( 10, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 1, 4, 5, 6, 9 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 4, 5, 7, 8 - // CHECK-NEXT: crd[1] : ( 0, 7, 2, 2, 3, 4, 6, 7 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 4, 5, 6, 9 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 4, 5, 7, 8 ) + // CHECK-NEXT: crd[1] : ( 0, 7, 2, 2, 3, 4, 6, 7 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8 ) // CHECK-NEXT: ---- // sparse_tensor.print %ts : tensor<10x8xf64, #Tensor1> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_1d_nwc_wcf.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_1d_nwc_wcf.mlir index 612e62bd34d2..3e46b6d65112 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_1d_nwc_wcf.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_1d_nwc_wcf.mlir @@ -116,13 +116,13 @@ func.func @main() { // CHECK-NEXT: nse = 18 // CHECK-NEXT: dim = ( 3, 6, 1 ) // CHECK-NEXT: lvl = ( 3, 6, 1 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: pos[2] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 - // CHECK-NEXT: crd[2] : ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - // CHECK-NEXT: values : ( 12, 28, 28, 28, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: pos[2] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 ) + // CHECK-NEXT: crd[2] : ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ) + // CHECK-NEXT: values : ( 12, 28, 28, 28, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12 ) // CHECK-NEXT: ---- // sparse_tensor.print %CCC_ret : tensor @@ -132,11 +132,11 @@ func.func @main() { // CHECK-NEXT: nse = 18 // CHECK-NEXT: dim = ( 3, 6, 1 ) // CHECK-NEXT: lvl = ( 3, 6, 1 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[2] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 - // CHECK-NEXT: crd[2] : ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - // CHECK-NEXT: values : ( 12, 28, 28, 28, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[2] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 ) + // CHECK-NEXT: crd[2] : ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ) + // CHECK-NEXT: values : ( 12, 28, 28, 28, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12 ) // CHECK-NEXT: ---- // sparse_tensor.print %CDC_ret : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d.mlir index 55d4caeb7eb3..97e9d1783f67 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d.mlir @@ -187,11 +187,11 @@ module { // CHECK-NEXT: nse = 36 // CHECK-NEXT: dim = ( 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %1 : tensor<6x6xi32, #DCSR> @@ -203,11 +203,11 @@ module { // CHECK-NEXT: nse = 36 // CHECK-NEXT: dim = ( 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %2 : tensor<6x6xi32, #DCSR> @@ -219,9 +219,9 @@ module { // CHECK-NEXT: nse = 36 // CHECK-NEXT: dim = ( 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6 ) - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %3 : tensor<6x6xi32, #CSR> @@ -233,9 +233,9 @@ module { // CHECK-NEXT: nse = 36 // CHECK-NEXT: dim = ( 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %4 : tensor<6x6xi32, #CDR> @@ -247,9 +247,9 @@ module { // CHECK-NEXT: nse = 36 // CHECK-NEXT: dim = ( 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6 ) - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: values : ( 0, -1, 0, -1, 0, 2, 0, 0, -1, 0, 0, -1, -1, 1, 1, 0, 3, 3, -6, 0, 0, 0, 6, 0, -1, 1, 0, 0, -3, -3, 6, 0, 0, 0, -6, 0 + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: values : ( 0, -1, 0, -1, 0, 2, 0, 0, -1, 0, 0, -1, -1, 1, 1, 0, 3, 3, -6, 0, 0, 0, 6, 0, -1, 1, 0, 0, -3, -3, 6, 0, 0, 0, -6, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %5 : tensor<6x6xi32, #CSC> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d_nhwc_hwcf.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d_nhwc_hwcf.mlir index d04311e59baf..429175c1a164 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d_nhwc_hwcf.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d_nhwc_hwcf.mlir @@ -147,27 +147,27 @@ func.func @main() { // CHECK-NEXT: nse = 108 // CHECK-NEXT: dim = ( 3, 6, 6, 1 ) // CHECK-NEXT: lvl = ( 3, 6, 6, 1 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, 90, 96, 102, 108 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, 90, 96, 102, 108 ) // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, // CHECK-SAME: 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, // CHECK-SAME: 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, - // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: pos[3] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, // CHECK-SAME: 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, // CHECK-SAME: 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, // CHECK-SAME: 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, // CHECK-SAME: 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, - // CHECK-SAME: 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108 + // CHECK-SAME: 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108 ) // CHECK-NEXT: crd[3] : ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0 + // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0 ) // CHECK-NEXT: values : ( 108, 124, 124, 124, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, @@ -175,7 +175,7 @@ func.func @main() { // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, - // CHECK-SAME: 108, 108, 108 + // CHECK-SAME: 108, 108, 108 ) // CHECK-NEXT: ---- // sparse_tensor.print %CCCC_ret : tensor @@ -185,14 +185,14 @@ func.func @main() { // CHECK-NEXT: nse = 108 // CHECK-NEXT: dim = ( 3, 6, 6, 1 ) // CHECK-NEXT: lvl = ( 3, 6, 6, 1 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, 90, 96, 102, 108 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, 90, 96, 102, 108 ) // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, // CHECK-SAME: 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, // CHECK-SAME: 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, - // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: values : ( 108, 124, 124, 124, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, @@ -200,7 +200,7 @@ func.func @main() { // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, - // CHECK-SAME: 108, 108, 108 + // CHECK-SAME: 108, 108, 108 ) // CHECK-NEXT: ---- // sparse_tensor.print %CDCD_ret : tensor @@ -210,14 +210,14 @@ func.func @main() { // CHECK-NEXT: nse = 108 // CHECK-NEXT: dim = ( 3, 6, 6, 1 ) // CHECK-NEXT: lvl = ( 3, 6, 6, 1 ) - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, 90, 96, 102, 108 + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, 90, 96, 102, 108 ) // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, // CHECK-SAME: 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, // CHECK-SAME: 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, - // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: values : ( 108, 124, 124, 124, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, @@ -225,7 +225,7 @@ func.func @main() { // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, - // CHECK-SAME: 108, 108, 108 + // CHECK-SAME: 108, 108, 108 ) // CHECK-NEXT: ---- // sparse_tensor.print %DCCD_ret : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d.mlir index 5e2d1707a249..b23b2dcc173d 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d.mlir @@ -171,14 +171,14 @@ func.func @main() { // CHECK-NEXT: nse = 216 // CHECK-NEXT: dim = ( 6, 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6, 6 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 ) // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, - // CHECK-SAME: 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, // CHECK-SAME: 84, 90, 96, 102, 108, 114, 120, 126, 132, 138, 144, 150, - // CHECK-SAME: 156, 162, 168, 174, 180, 186, 192, 198, 204, 210, 216 + // CHECK-SAME: 156, 162, 168, 174, 180, 186, 192, 198, 204, 210, 216 ) // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, // CHECK-SAME: 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, @@ -190,7 +190,7 @@ func.func @main() { // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, // CHECK-SAME: 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, - // CHECK-SAME: 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: values : ( 108, 108, 108, 108, 108, 108, 124, 108, 108, 108, 108, 108, // CHECK-SAME: 124, 108, 108, 108, 108, 108, 124, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, @@ -208,7 +208,7 @@ func.func @main() { // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, - // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108 + // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108 ) // CHECK-NEXT: ---- // sparse_tensor.print %CCC_ret : tensor @@ -218,11 +218,11 @@ func.func @main() { // CHECK-NEXT: nse = 216 // CHECK-NEXT: dim = ( 6, 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6, 6 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, // CHECK-SAME: 90, 96, 102, 108, 114, 120, 126, 132, 138, 144, 150, 156, - // CHECK-SAME: 162, 168, 174, 180, 186, 192, 198, 204, 210, 216 + // CHECK-SAME: 162, 168, 174, 180, 186, 192, 198, 204, 210, 216 ) // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, @@ -233,7 +233,7 @@ func.func @main() { // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, // CHECK-SAME: 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, - // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: values : ( 108, 108, 108, 108, 108, 108, 124, 108, 108, 108, 108, 108, // CHECK-SAME: 124, 108, 108, 108, 108, 108, 124, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, @@ -251,7 +251,7 @@ func.func @main() { // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, - // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108 + // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108 ) // CHECK-NEXT: ---- // sparse_tensor.print %CDC_ret : tensor @@ -263,7 +263,7 @@ func.func @main() { // CHECK-NEXT: lvl = ( 6, 6, 6 ) // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, 90, // CHECK-SAME: 96, 102, 108, 114, 120, 126, 132, 138, 144, 150, 156, 162, - // CHECK-SAME: 168, 174, 180, 186, 192, 198, 204, 210, 216 + // CHECK-SAME: 168, 174, 180, 186, 192, 198, 204, 210, 216 ) // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, @@ -274,7 +274,7 @@ func.func @main() { // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, // CHECK-SAME: 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, - // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: values : ( 108, 108, 108, 108, 108, 108, 124, 108, 108, 108, 108, 108, // CHECK-SAME: 124, 108, 108, 108, 108, 108, 124, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, @@ -292,7 +292,7 @@ func.func @main() { // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, - // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108 + // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108 ) // CHECK-NEXT: ---- // sparse_tensor.print %DDC_ret : tensor @@ -302,12 +302,12 @@ func.func @main() { // CHECK-NEXT: nse = 216 // CHECK-NEXT: dim = ( 6, 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6, 6 ) - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 ) // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, - // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, 90, // CHECK-SAME: 96, 102, 108, 114, 120, 126, 132, 138, 144, 150, 156, 162, - // CHECK-SAME: 168, 174, 180, 186, 192, 198, 204, 210, 216 + // CHECK-SAME: 168, 174, 180, 186, 192, 198, 204, 210, 216 ) // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, @@ -318,7 +318,7 @@ func.func @main() { // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, // CHECK-SAME: 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, - // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: values : ( 108, 108, 108, 108, 108, 108, 124, 108, 108, 108, 108, 108, // CHECK-SAME: 124, 108, 108, 108, 108, 108, 124, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, @@ -336,7 +336,7 @@ func.func @main() { // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, - // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108 + // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108 ) // CHECK-NEXT: ---- // sparse_tensor.print %DCC_ret : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d_ndhwc_dhwcf.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d_ndhwc_dhwcf.mlir index f68e429a3c82..8fb6704c7f50 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d_ndhwc_dhwcf.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d_ndhwc_dhwcf.mlir @@ -155,16 +155,16 @@ func.func @main() { // CHECK-NEXT: nse = 216 // CHECK-NEXT: dim = ( 1, 6, 6, 6, 1 ) // CHECK-NEXT: lvl = ( 1, 6, 6, 6, 1 ) - // CHECK-NEXT: pos[0] : ( 0, 1 - // CHECK-NEXT: crd[0] : ( 0 - // CHECK-NEXT: pos[1] : ( 0, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36 + // CHECK-NEXT: pos[0] : ( 0, 1 ) + // CHECK-NEXT: crd[0] : ( 0 ) + // CHECK-NEXT: pos[1] : ( 0, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36 ) // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, - // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: pos[3] : ( 0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, 90, 96, // CHECK-SAME: 102, 108, 114, 120, 126, 132, 138, 144, 150, 156, 162, 168, 174, - // CHECK-SAME: 180, 186, 192, 198, 204, 210, 216 + // CHECK-SAME: 180, 186, 192, 198, 204, 210, 216 ) // CHECK-NEXT: crd[3] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, @@ -174,7 +174,7 @@ func.func @main() { // CHECK-SAME: 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, // CHECK-SAME: 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, - // CHECK-SAME: 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: pos[4] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, // CHECK-SAME: 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, // CHECK-SAME: 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, @@ -189,7 +189,7 @@ func.func @main() { // CHECK-SAME: 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, // CHECK-SAME: 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, // CHECK-SAME: 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, - // CHECK-SAME: 215, 216 + // CHECK-SAME: 215, 216 ) // CHECK-NEXT: crd[4] : ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -199,7 +199,7 @@ func.func @main() { // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0 + // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0 ) // CHECK-NEXT: values : ( 108, 124, 124, 124, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, @@ -215,7 +215,7 @@ func.func @main() { // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, - // CHECK-SAME: 108, 108, 108, 108, 108, 108 + // CHECK-SAME: 108, 108, 108, 108, 108, 108 ) // CHECK-NEXT: ---- // sparse_tensor.print %CCCCC_ret : tensor @@ -229,11 +229,11 @@ func.func @main() { // CHECK-NEXT: nse = 216 // CHECK-NEXT: dim = ( 1, 6, 6, 6, 1 ) // CHECK-NEXT: lvl = ( 1, 6, 6, 6, 1 ) - // CHECK-NEXT: pos[0] : ( 0, 1 - // CHECK-NEXT: crd[0] : ( 0 - // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36 + // CHECK-NEXT: pos[0] : ( 0, 1 ) + // CHECK-NEXT: crd[0] : ( 0 ) + // CHECK-NEXT: pos[2] : ( 0, 6, 12, 18, 24, 30, 36 ) // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, - // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: pos[4] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, // CHECK-SAME: 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, // CHECK-SAME: 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, @@ -248,7 +248,7 @@ func.func @main() { // CHECK-SAME: 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, // CHECK-SAME: 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, // CHECK-SAME: 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, - // CHECK-SAME: 215, 216 + // CHECK-SAME: 215, 216 ) // CHECK-NEXT: crd[4] : ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -258,7 +258,7 @@ func.func @main() { // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0 + // CHECK-SAME: 0, 0, 0, 0, 0, 0, 0, 0, 0 ) // CHECK-NEXT: values : ( 108, 124, 124, 124, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, @@ -274,7 +274,7 @@ func.func @main() { // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, // CHECK-SAME: 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, - // CHECK-SAME: 108, 108, 108, 108, 108, 108 + // CHECK-SAME: 108, 108, 108, 108, 108, 108 ) // CHECK-NEXT: ---- // sparse_tensor.print %CDCDC_ret : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion.mlir index 8024c1281895..5de3aa0a2e97 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion.mlir @@ -98,156 +98,156 @@ module { // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 2, 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 1 - // CHECK-NEXT: pos[1] : ( 0, 3, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: pos[2] : ( 0, 4, 8, 12, 16, 20, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: pos[2] : ( 0, 4, 8, 12, 16, 20, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 3, 4, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: values : ( 1, 13, 2, 14, 3, 15, 4, 16, 5, 17, 6, 18, 7, 19, 8, 20, 9, 21, 10, 22, 11, 23, 12, 24 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: values : ( 1, 13, 2, 14, 3, 15, 4, 16, 5, 17, 6, 18, 7, 19, 8, 20, 9, 21, 10, 22, 11, 23, 12, 24 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 4, 2, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, 8 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: pos[2] : ( 0, 3, 6, 9, 12, 15, 18, 21, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: values : ( 1, 5, 9, 13, 17, 21, 2, 6, 10, 14, 18, 22, 3, 7, 11, 15, 19, 23, 4, 8, 12, 16, 20, 24 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, 8 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: pos[2] : ( 0, 3, 6, 9, 12, 15, 18, 21, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: values : ( 1, 5, 9, 13, 17, 21, 2, 6, 10, 14, 18, 22, 3, 7, 11, 15, 19, 23, 4, 8, 12, 16, 20, 24 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 2, 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 1 - // CHECK-NEXT: pos[1] : ( 0, 3, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: pos[2] : ( 0, 4, 8, 12, 16, 20, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: pos[2] : ( 0, 4, 8, 12, 16, 20, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 2, 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 1 - // CHECK-NEXT: pos[1] : ( 0, 3, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: pos[2] : ( 0, 4, 8, 12, 16, 20, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: pos[2] : ( 0, 4, 8, 12, 16, 20, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 2, 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 1 - // CHECK-NEXT: pos[1] : ( 0, 3, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: pos[2] : ( 0, 4, 8, 12, 16, 20, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: pos[2] : ( 0, 4, 8, 12, 16, 20, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 3, 4, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: values : ( 1, 13, 2, 14, 3, 15, 4, 16, 5, 17, 6, 18, 7, 19, 8, 20, 9, 21, 10, 22, 11, 23, 12, 24 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: values : ( 1, 13, 2, 14, 3, 15, 4, 16, 5, 17, 6, 18, 7, 19, 8, 20, 9, 21, 10, 22, 11, 23, 12, 24 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 3, 4, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: values : ( 1, 13, 2, 14, 3, 15, 4, 16, 5, 17, 6, 18, 7, 19, 8, 20, 9, 21, 10, 22, 11, 23, 12, 24 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: values : ( 1, 13, 2, 14, 3, 15, 4, 16, 5, 17, 6, 18, 7, 19, 8, 20, 9, 21, 10, 22, 11, 23, 12, 24 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 3, 4, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: values : ( 1, 13, 2, 14, 3, 15, 4, 16, 5, 17, 6, 18, 7, 19, 8, 20, 9, 21, 10, 22, 11, 23, 12, 24 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: values : ( 1, 13, 2, 14, 3, 15, 4, 16, 5, 17, 6, 18, 7, 19, 8, 20, 9, 21, 10, 22, 11, 23, 12, 24 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 4, 2, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, 8 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: pos[2] : ( 0, 3, 6, 9, 12, 15, 18, 21, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: values : ( 1, 5, 9, 13, 17, 21, 2, 6, 10, 14, 18, 22, 3, 7, 11, 15, 19, 23, 4, 8, 12, 16, 20, 24 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, 8 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: pos[2] : ( 0, 3, 6, 9, 12, 15, 18, 21, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: values : ( 1, 5, 9, 13, 17, 21, 2, 6, 10, 14, 18, 22, 3, 7, 11, 15, 19, 23, 4, 8, 12, 16, 20, 24 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 4, 2, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, 8 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: pos[2] : ( 0, 3, 6, 9, 12, 15, 18, 21, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: values : ( 1, 5, 9, 13, 17, 21, 2, 6, 10, 14, 18, 22, 3, 7, 11, 15, 19, 23, 4, 8, 12, 16, 20, 24 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, 8 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: pos[2] : ( 0, 3, 6, 9, 12, 15, 18, 21, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: values : ( 1, 5, 9, 13, 17, 21, 2, 6, 10, 14, 18, 22, 3, 7, 11, 15, 19, 23, 4, 8, 12, 16, 20, 24 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 4, 2, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, 8 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: pos[2] : ( 0, 3, 6, 9, 12, 15, 18, 21, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: values : ( 1, 5, 9, 13, 17, 21, 2, 6, 10, 14, 18, 22, 3, 7, 11, 15, 19, 23, 4, 8, 12, 16, 20, 24 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, 8 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: pos[2] : ( 0, 3, 6, 9, 12, 15, 18, 21, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: values : ( 1, 5, 9, 13, 17, 21, 2, 6, 10, 14, 18, 22, 3, 7, 11, 15, 19, 23, 4, 8, 12, 16, 20, 24 ) // CHECK-NEXT: ---- // sparse_tensor.print %1 : tensor<2x3x4xf64, #Tensor1> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_block.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_block.mlir index ff22283f43a7..66215a340a0b 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_block.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_block.mlir @@ -82,36 +82,36 @@ module { // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 2, 4 ) // CHECK-NEXT: lvl = ( 1, 2, 2, 2 ) - // CHECK-NEXT: pos[1] : ( 0, 2 - // CHECK-NEXT: crd[1] : ( 0, 1 - // CHECK-NEXT: values : ( 1, 2, 5, 6, 3, 4, 7, 8 + // CHECK-NEXT: pos[1] : ( 0, 2 ) + // CHECK-NEXT: crd[1] : ( 0, 1 ) + // CHECK-NEXT: values : ( 1, 2, 5, 6, 3, 4, 7, 8 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 2, 4 ) // CHECK-NEXT: lvl = ( 1, 2, 2, 2 ) - // CHECK-NEXT: pos[1] : ( 0, 2 - // CHECK-NEXT: crd[1] : ( 0, 1 - // CHECK-NEXT: values : ( 1, 2, 5, 6, 3, 4, 7, 8 + // CHECK-NEXT: pos[1] : ( 0, 2 ) + // CHECK-NEXT: crd[1] : ( 0, 1 ) + // CHECK-NEXT: values : ( 1, 2, 5, 6, 3, 4, 7, 8 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 2, 4 ) // CHECK-NEXT: lvl = ( 2, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 4, 8 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8 + // CHECK-NEXT: pos[1] : ( 0, 4, 8 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 2, 4 ) // CHECK-NEXT: lvl = ( 4, 2 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, 8 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: values : ( 1, 5, 2, 6, 3, 7, 4, 8 + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, 8 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: values : ( 1, 5, 2, 6, 3, 7, 4, 8 ) // CHECK-NEXT: ---- // sparse_tensor.print %1 : tensor<2x4xf64, #BSR> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_dyn.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_dyn.mlir index 11baf65e6350..0d9722cd37e6 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_dyn.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_dyn.mlir @@ -67,66 +67,66 @@ module { // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 32, 64 ) // CHECK-NEXT: lvl = ( 32, 64 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 31 - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 - // CHECK-NEXT: crd[1] : ( 0, 1, 63, 0, 1, 0, 63 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 31 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 63, 0, 1, 0, 63 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 32, 64 ) // CHECK-NEXT: lvl = ( 64, 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 63 - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 - // CHECK-NEXT: crd[1] : ( 0, 1, 31, 0, 1, 0, 31 - // CHECK-NEXT: values : ( 1, 4, 6, 2, 5, 3, 7 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 63 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 31, 0, 1, 0, 31 ) + // CHECK-NEXT: values : ( 1, 4, 6, 2, 5, 3, 7 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 32, 64 ) // CHECK-NEXT: lvl = ( 32, 64 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 31 - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 - // CHECK-NEXT: crd[1] : ( 0, 1, 63, 0, 1, 0, 63 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 31 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 63, 0, 1, 0, 63 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 32, 64 ) // CHECK-NEXT: lvl = ( 64, 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 63 - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 - // CHECK-NEXT: crd[1] : ( 0, 1, 31, 0, 1, 0, 31 - // CHECK-NEXT: values : ( 1, 4, 6, 2, 5, 3, 7 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 63 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 31, 0, 1, 0, 31 ) + // CHECK-NEXT: values : ( 1, 4, 6, 2, 5, 3, 7 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 32, 64 ) // CHECK-NEXT: lvl = ( 64, 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 63 - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 - // CHECK-NEXT: crd[1] : ( 0, 1, 31, 0, 1, 0, 31 - // CHECK-NEXT: values : ( 1, 4, 6, 2, 5, 3, 7 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 63 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 31, 0, 1, 0, 31 ) + // CHECK-NEXT: values : ( 1, 4, 6, 2, 5, 3, 7 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 32, 64 ) // CHECK-NEXT: lvl = ( 32, 64 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 31 - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 - // CHECK-NEXT: crd[1] : ( 0, 1, 63, 0, 1, 0, 63 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 31 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 63, 0, 1, 0, 63 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 ) // CHECK-NEXT: ---- // sparse_tensor.print %1 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_ptr.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_ptr.mlir index 6005aa6cfeae..531efb4f7f37 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_ptr.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_ptr.mlir @@ -78,64 +78,64 @@ module { // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 32, 64 ) // CHECK-NEXT: lvl = ( 32, 64 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 31 - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 - // CHECK-NEXT: crd[1] : ( 0, 1, 63, 0, 1, 0, 63 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 31 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 63, 0, 1, 0, 63 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 32, 64 ) // CHECK-NEXT: lvl = ( 64, 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 63 - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 - // CHECK-NEXT: crd[1] : ( 0, 1, 31, 0, 1, 0, 31 - // CHECK-NEXT: values : ( 1, 4, 6, 2, 5, 3, 7 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 63 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 31, 0, 1, 0, 31 ) + // CHECK-NEXT: values : ( 1, 4, 6, 2, 5, 3, 7 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 32, 64 ) // CHECK-NEXT: lvl = ( 64, 32 ) - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 7 - // CHECK-NEXT: crd[1] : ( 0, 1, 31, 0, 1, 0, 31 - // CHECK-NEXT: values : ( 1, 4, 6, 2, 5, 3, 7 + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 7 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 31, 0, 1, 0, 31 ) + // CHECK-NEXT: values : ( 1, 4, 6, 2, 5, 3, 7 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 32, 64 ) // CHECK-NEXT: lvl = ( 64, 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 63 - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 - // CHECK-NEXT: crd[1] : ( 0, 1, 31, 0, 1, 0, 31 - // CHECK-NEXT: values : ( 1, 4, 6, 2, 5, 3, 7 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 63 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 31, 0, 1, 0, 31 ) + // CHECK-NEXT: values : ( 1, 4, 6, 2, 5, 3, 7 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 32, 64 ) // CHECK-NEXT: lvl = ( 32, 64 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 31 - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 - // CHECK-NEXT: crd[1] : ( 0, 1, 63, 0, 1, 0, 63 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 31 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 63, 0, 1, 0, 63 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 32, 64 ) // CHECK-NEXT: lvl = ( 32, 64 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 31 - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 - // CHECK-NEXT: crd[1] : ( 0, 1, 63, 0, 1, 0, 63 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 31 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 63, 0, 1, 0, 63 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 ) // CHECK-NEXT: ---- // sparse_tensor.print %1 : tensor<32x64xf64, #DCSR> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_coo_test.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_coo_test.mlir index 16813e0aa707..c16ae0de1820 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_coo_test.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_coo_test.mlir @@ -209,21 +209,21 @@ module { // CHECK-NEXT: nse = 64 // CHECK-NEXT: dim = ( 8, 8 ) // CHECK-NEXT: lvl = ( 8, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 64 + // CHECK-NEXT: pos[0] : ( 0, 64 ) // CHECK-NEXT: crd[0] : ( 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, // CHECK-SAME: 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, // CHECK-SAME: 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, - // CHECK-SAME: 7, 7, 7, 7 + // CHECK-SAME: 7, 7, 7, 7 ) // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, // CHECK-SAME: 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, // CHECK-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, - // CHECK-SAME: 4, 5, 6, 7 + // CHECK-SAME: 4, 5, 6, 7 ) // CHECK-NEXT: values : ( 8.8, 4.8, 6.8, 4.8, 8.8, 6.1, 14.8, 16.8, 4.4, 4.4, 4.4, 8.4, // CHECK-SAME: 8.4, 12.4, 16.4, 16.4, 8.8, 4.8, 6.8, 8.8, 8.8, 12.8, 14.8, // CHECK-SAME: 15.8, 4.3, 5.3, 6.3, 8.3, 8.3, 12.3, 14.3, 16.3, 4.5, 4.5, // CHECK-SAME: 6.5, 8.5, 8.5, 12.5, 14.5, 16.5, 9.9, 4.9, 6.9, 8.9, 8.9, // CHECK-SAME: 12.9, 15.9, 16.9, 12.1, 6.1, 5.1, 9.1, 9.1, 13.1, 15.1, 17.1, - // CHECK-SAME: 15.4, 5.4, 7.4, 5.4, 11.4, 10.4, 11.4, 9.4 + // CHECK-SAME: 15.4, 5.4, 7.4, 5.4, 11.4, 10.4, 11.4, 9.4 ) // CHECK-NEXT: ---- // sparse_tensor.print %COO_RET : tensor<8x8xf32, #SortedCOOSoA> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_dot.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_dot.mlir index 5451f2d957ad..b41fda19459e 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_dot.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_dot.mlir @@ -67,18 +67,18 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 1024 ) // CHECK-NEXT: lvl = ( 1024 ) - // CHECK-NEXT: pos[0] : ( 0, 5 - // CHECK-NEXT: crd[0] : ( 0, 1, 22, 23, 1022 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5 + // CHECK-NEXT: pos[0] : ( 0, 5 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 22, 23, 1022 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 1024 ) // CHECK-NEXT: lvl = ( 1024 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 22, 1022, 1023 - // CHECK-NEXT: values : ( 6, 7, 8 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 22, 1022, 1023 ) + // CHECK-NEXT: values : ( 6, 7, 8 ) // CHECK-NEXT: ---- // sparse_tensor.print %s1 : tensor<1024xf32, #SparseVector> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_ds.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_ds.mlir index f4ae33a42d06..17fab93b9b21 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_ds.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_ds.mlir @@ -79,9 +79,9 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 3, 8 ) // CHECK-NEXT: lvl = ( 3, 8 ) - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12, ) - // CHECK-NEXT: crd[1] : ( 2, 3, 5, 7, 1, 2, 4, 7, 0, 2, 4, 5, ) - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, ) + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 ) + // CHECK-NEXT: crd[1] : ( 2, 3, 5, 7, 1, 2, 4, 7, 0, 2, 4, 5 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 ) // CHECK-NEXT: ---- // sparse_tensor.print %A1 : tensor @@ -93,9 +93,9 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 3, 8 ) // CHECK-NEXT: lvl = ( 3, 8 ) - // CHECK-NEXT: pos[1] : ( 0, 4, 4, 8, 8, 12, - // CHECK-NEXT: crd[1] : ( 2, 3, 5, 7, 1, 2, 4, 7, 0, 2, 4, 5, ) - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, ) + // CHECK-NEXT: pos[1] : ( 0, 4, 4, 8, 8, 12, {{.*}} ) + // CHECK-NEXT: crd[1] : ( 2, 3, 5, 7, 1, 2, 4, 7, 0, 2, 4, 5 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 ) // CHECK-NEXT: ---- // sparse_tensor.print %A2 : tensor @@ -107,8 +107,8 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 3, 8 ) // CHECK-NEXT: lvl = ( 3, 2, 4 ) - // CHECK-NEXT: crd[2] : ( 2, 3, 1, 3, 1, 2, 0, 3, 0, 2, 0, 1, ) - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, ) + // CHECK-NEXT: crd[2] : ( 2, 3, 1, 3, 1, 2, 0, 3, 0, 2, 0, 1 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 ) // CHECK-NEXT: ---- // CHECK-NEXT: ---- Sparse Tensor ---- // @@ -120,8 +120,8 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 3, 8 ) // CHECK-NEXT: lvl = ( 3, 1, 8 ) - // CHECK-NEXT: crd[2] : ( 2, 3, 5, 7, 1, 2, 4, 7, 0, 2, 4, 5, ) - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, ) + // CHECK-NEXT: crd[2] : ( 2, 3, 5, 7, 1, 2, 4, 7, 0, 2, 4, 5 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 ) // CHECK-NEXT: ---- // sparse_tensor.print %A4 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_empty.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_empty.mlir index 7fc37eade720..7255649ccd42 100755 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_empty.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_empty.mlir @@ -98,36 +98,36 @@ module { // CHECK-NEXT: nse = 0 // CHECK-NEXT: dim = ( 10 ) // CHECK-NEXT: lvl = ( 10 ) - // CHECK-NEXT: pos[0] : ( 0, 0, ) - // CHECK-NEXT: crd[0] : ( ) - // CHECK-NEXT: values : ( ) + // CHECK-NEXT: pos[0] : ( 0, 0 ) + // CHECK-NEXT: crd[0] : ( ) + // CHECK-NEXT: values : ( ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 0 // CHECK-NEXT: dim = ( 10 ) // CHECK-NEXT: lvl = ( 10 ) - // CHECK-NEXT: pos[0] : ( 0, 0, - // CHECK-NEXT: crd[0] : ( ) - // CHECK-NEXT: values : ( ) + // CHECK-NEXT: pos[0] : ( 0, 0 ) + // CHECK-NEXT: crd[0] : ( ) + // CHECK-NEXT: values : ( ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 0 // CHECK-NEXT: dim = ( 10 ) // CHECK-NEXT: lvl = ( 10 ) - // CHECK-NEXT: pos[0] : ( 0, 0, ) - // CHECK-NEXT: crd[0] : ( ) - // CHECK-NEXT: values : ( ) + // CHECK-NEXT: pos[0] : ( 0, 0 ) + // CHECK-NEXT: crd[0] : ( ) + // CHECK-NEXT: values : ( ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 10 // CHECK-NEXT: dim = ( 10 ) // CHECK-NEXT: lvl = ( 10 ) - // CHECK-NEXT: pos[0] : ( 0, 10, ) - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, ) - // CHECK-NEXT: values : ( 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, ) + // CHECK-NEXT: pos[0] : ( 0, 10 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ) + // CHECK-NEXT: values : ( 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor<10xf32, #SV> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand.mlir index 451195b2185b..6e875de7481e 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand.mlir @@ -86,13 +86,13 @@ module { // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 8, 4 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[1] : ( 0, 8, 16, 24, 32 + // CHECK-NEXT: pos[1] : ( 0, 8, 16, 24, 32 ) // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, - // CHECK-SAME: 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7 + // CHECK-SAME: 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7 ) // CHECK-NEXT: values : ( 32.53, 34.56, 36.59, 38.62, 40.65, 42.68, 44.71, 46.74, // CHECK-SAME: 35.73, 37.96, 40.19, 42.42, 44.65, 46.88, 49.11, 51.34, // CHECK-SAME: 38.93, 41.36, 43.79, 46.22, 48.65, 51.08, 53.51, 55.94, - // CHECK-SAME: 42.13, 44.76, 47.39, 50.02, 52.65, 55.28, 57.91, 60.54 + // CHECK-SAME: 42.13, 44.76, 47.39, 50.02, 52.65, 55.28, 57.91, 60.54 ) // CHECK-NEXT: ---- // sparse_tensor.print %x3 : tensor<8x4xf64, #CSC> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand_shape.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand_shape.mlir index 393242484576..5e021596efea 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand_shape.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand_shape.mlir @@ -200,74 +200,74 @@ module { // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 3, 4 ) // CHECK-NEXT: lvl = ( 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 - // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, 0, 2 - // CHECK-NEXT: values : ( 1, 3, 5, 7, 9, 11 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, 0, 2 ) + // CHECK-NEXT: values : ( 1, 3, 5, 7, 9, 11 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 3, 4 ) // CHECK-NEXT: lvl = ( 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 - // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, 0, 2 - // CHECK-NEXT: values : ( 1, 3, 5, 7, 9, 11 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, 0, 2 ) + // CHECK-NEXT: values : ( 1, 3, 5, 7, 9, 11 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 3, 2, 2 ) // CHECK-NEXT: lvl = ( 3, 2, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12 - // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: values : ( 1.1, 1.2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 3.1, 3.2, 3.3, 3.4 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: values : ( 1.1, 1.2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 3.1, 3.2, 3.3, 3.4 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 3, 2, 2 ) // CHECK-NEXT: lvl = ( 3, 2, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12 - // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: values : ( 1.1, 1.2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 3.1, 3.2, 3.3, 3.4 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: values : ( 1.1, 1.2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 3.1, 3.2, 3.3, 3.4 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 3, 2, 2 ) // CHECK-NEXT: lvl = ( 3, 2, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12 - // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: values : ( 1.1, 1.2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 3.1, 3.2, 3.3, 3.4 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: values : ( 1.1, 1.2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 3.1, 3.2, 3.3, 3.4 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 3, 2, 2 ) // CHECK-NEXT: lvl = ( 3, 2, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12 - // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 - // CHECK-NEXT: values : ( 1.1, 1.2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 3.1, 3.2, 3.3, 3.4 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: pos[2] : ( 0, 2, 4, 6, 8, 10, 12 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 ) + // CHECK-NEXT: values : ( 1.1, 1.2, 1.3, 1.4, 2.1, 2.2, 2.3, 2.4, 3.1, 3.2, 3.3, 3.4 ) // CHECK-NEXT: ---- // sparse_tensor.print %expand2 : tensor<3x4xf64, #SparseMatrix> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_filter_conv2d.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_filter_conv2d.mlir index 37ff2e3ffd3f..93b8eda2c2ae 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_filter_conv2d.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_filter_conv2d.mlir @@ -106,13 +106,13 @@ module { // CHECK-NEXT: nse = 36 // CHECK-NEXT: dim = ( 6, 6 ) // CHECK-NEXT: lvl = ( 6, 6 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 - // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5 ) + // CHECK-NEXT: pos[1] : ( 0, 6, 12, 18, 24, 30, 36 ) // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, - // CHECK-SAME: 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 + // CHECK-SAME: 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5 ) // CHECK-NEXT: values : ( 0, 0, -1, -6, -1, 6, -1, 0, 1, 0, 1, 0, 0, -1, 1, - // CHECK-SAME: 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 + // CHECK-SAME: 0, 0, 0, -1, 0, 0, 0, 0, 0, 0, 0, 3, 6, -3, -6, 2, -1, 3, 0, -3, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %1 : tensor<6x6xi32, #DCSR> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_index.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_index.mlir index 3ce45e5fd971..005398445828 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_index.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_index.mlir @@ -212,80 +212,80 @@ module { // CHECK-NEXT: nse = 2 // CHECK-NEXT: dim = ( 8 ) // CHECK-NEXT: lvl = ( 8 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 2, 4 - // CHECK-NEXT: values : ( 20, 80 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 2, 4 ) + // CHECK-NEXT: values : ( 20, 80 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 8 ) // CHECK-NEXT: lvl = ( 8 ) - // CHECK-NEXT: pos[0] : ( 0, 8 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7 - // CHECK-NEXT: values : ( 0, 1, 12, 3, 24, 5, 6, 7 + // CHECK-NEXT: pos[0] : ( 0, 8 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7 ) + // CHECK-NEXT: values : ( 0, 1, 12, 3, 24, 5, 6, 7 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 8 ) // CHECK-NEXT: lvl = ( 8 ) - // CHECK-NEXT: pos[0] : ( 0, 8 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7 - // CHECK-NEXT: values : ( 0, 2, 8, 24, 64, 160, 384, 896 + // CHECK-NEXT: pos[0] : ( 0, 8 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7 ) + // CHECK-NEXT: values : ( 0, 2, 8, 24, 64, 160, 384, 896 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 8 ) // CHECK-NEXT: lvl = ( 8 ) - // CHECK-NEXT: pos[0] : ( 0, 8 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7 - // CHECK-NEXT: values : ( 1, 3, 6, 11, 20, 37, 70, 135 + // CHECK-NEXT: pos[0] : ( 0, 8 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7 ) + // CHECK-NEXT: values : ( 1, 3, 6, 11, 20, 37, 70, 135 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 2 // CHECK-NEXT: dim = ( 3, 4 ) // CHECK-NEXT: lvl = ( 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 1, 2 - // CHECK-NEXT: crd[1] : ( 1, 3 - // CHECK-NEXT: values : ( 10, 120 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 2 ) + // CHECK-NEXT: crd[1] : ( 1, 3 ) + // CHECK-NEXT: values : ( 10, 120 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 3, 4 ) // CHECK-NEXT: lvl = ( 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 0, 1, 2, 3, 1, 12, 3, 4, 2, 3, 4, 25 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 0, 1, 2, 3, 1, 12, 3, 4, 2, 3, 4, 25 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 3, 4 ) // CHECK-NEXT: lvl = ( 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 0, 0, 0, 0, 0, 2, 2, 3, 0, 2, 12, 24 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 0, 0, 0, 0, 0, 2, 2, 3, 0, 2, 12, 24 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 3, 4 ) // CHECK-NEXT: lvl = ( 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 2, 4, 4, 5, 3, 4, 7, 9 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 2, 4, 4, 5, 3, 4, 7, 9 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor<8xi64, #SparseVector> @@ -304,11 +304,11 @@ module { // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 2, 3 ) // CHECK-NEXT: lvl = ( 2, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 1 - // CHECK-NEXT: pos[1] : ( 0, 3, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: values : ( 0, 10, 0, 1, 1, 42 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: values : ( 0, 10, 0, 1, 1, 42 ) // CHECK-NEXT: ---- // %100 = call @add_outer_2d(%sf32) : (tensor<2x3xf32, #SparseMatrix>) diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_1d.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_1d.mlir index 12e0d2267a26..a81ec172f599 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_1d.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_1d.mlir @@ -65,9 +65,9 @@ module { // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 1024 ) // CHECK-NEXT: lvl = ( 1024 ) - // CHECK-NEXT: pos[0] : ( 0, 4, - // CHECK-NEXT: crd[0] : ( 0, 1, 3, 1023, - // CHECK-NEXT: values : ( 1, 2, 3, 4, + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 3, 1023 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4 ) // CHECK-NEXT: ---- // sparse_tensor.print %5 : tensor<1024xf32, #SparseVector> @@ -86,9 +86,9 @@ module { // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 1024 ) // CHECK-NEXT: lvl = ( 1024 ) - // CHECK-NEXT: pos[0] : ( 0, 8, - // CHECK-NEXT: crd[0] : ( 0, 3, 6, 9, 12, 15, 18, 21, - // CHECK-NEXT: values : ( 1, 1, 1, 1, 1, 1, 1, 1, + // CHECK-NEXT: pos[0] : ( 0, 8 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 6, 9, 12, 15, 18, 21 ) + // CHECK-NEXT: values : ( 1, 1, 1, 1, 1, 1, 1, 1 ) // CHECK-NEXT: ---- // sparse_tensor.print %8 : tensor<1024xf32, #SparseVector> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_2d.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_2d.mlir index 883109150653..baab6e759886 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_2d.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_2d.mlir @@ -68,7 +68,7 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 4, 3 ) // CHECK-NEXT: lvl = ( 4, 3 ) - // CHECK-NEXT: values : ( 1, 0, 0, 0, 0, 0, 0, 0, 2, 3, 0, 4, + // CHECK-NEXT: values : ( 1, 0, 0, 0, 0, 0, 0, 0, 2, 3, 0, 4 ) // CHECK-NEXT: ---- // %densea = tensor.empty() : tensor<4x3xf64, #Dense> @@ -86,10 +86,10 @@ module { // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 4, 3 ) // CHECK-NEXT: lvl = ( 4, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 4, - // CHECK-NEXT: crd[0] : ( 0, 2, 3, 3, - // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, - // CHECK-NEXT: values : ( 1, 2, 3, 4, + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 3, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4 ) // CHECK-NEXT: ---- // %cooa = tensor.empty() : tensor<4x3xf64, #SortedCOO> @@ -107,9 +107,9 @@ module { // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 4, 3 ) // CHECK-NEXT: lvl = ( 4, 3 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 1, 2, 4, - // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, - // CHECK-NEXT: values : ( 1, 2, 3, 4, + // CHECK-NEXT: pos[1] : ( 0, 1, 1, 2, 4 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4 ) // CHECK-NEXT: ---- // %csra = tensor.empty() : tensor<4x3xf64, #CSR> @@ -127,11 +127,11 @@ module { // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 4, 3 ) // CHECK-NEXT: lvl = ( 4, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 0, 2, 3, - // CHECK-NEXT: pos[1] : ( 0, 1, 2, 4, - // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, - // CHECK-NEXT: values : ( 1, 2, 3, 4, + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 2, 4 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4 ) // CHECK-NEXT: ---- // %dcsra = tensor.empty() : tensor<4x3xf64, #DCSR> @@ -149,9 +149,9 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 4, 3 ) // CHECK-NEXT: lvl = ( 4, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 0, 2, 3, - // CHECK-NEXT: values : ( 1, 0, 0, 0, 0, 2, 3, 0, 4, + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 3 ) + // CHECK-NEXT: values : ( 1, 0, 0, 0, 0, 2, 3, 0, 4 ) // CHECK-NEXT: ---- // %rowa = tensor.empty() : tensor<4x3xf64, #Row> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_3d.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_3d.mlir index db6612402357..12ef94fc2baa 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_3d.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_3d.mlir @@ -64,11 +64,11 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 5, 4, 3 ) // CHECK-NEXT: lvl = ( 5, 4, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 3, 4 - // CHECK-NEXT: pos[2] : ( 0, 2, 2, 2, 3, 3, 3, 4, 5 - // CHECK-NEXT: crd[2] : ( 1, 2, 1, 2, 2 - // CHECK-NEXT: values : ( 1.1, 2.2, 3.3, 4.4, 5.5 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 3, 4 ) + // CHECK-NEXT: pos[2] : ( 0, 2, 2, 2, 3, 3, 3, 4, 5 ) + // CHECK-NEXT: crd[2] : ( 1, 2, 1, 2, 2 ) + // CHECK-NEXT: values : ( 1.1, 2.2, 3.3, 4.4, 5.5 ) // CHECK-NEXT: ---- %tensora = tensor.empty() : tensor<5x4x3xf64, #TensorCSR> %tensor1 = tensor.insert %f1 into %tensora[%c3, %c0, %c1] : tensor<5x4x3xf64, #TensorCSR> @@ -83,11 +83,11 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 5, 4, 3 ) // CHECK-NEXT: lvl = ( 5, 4, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 3, 4 - // CHECK-NEXT: pos[1] : ( 0, 2, 4 - // CHECK-NEXT: crd[1] : ( 0, 3, 2, 3 - // CHECK-NEXT: values : ( 0, 1.1, 2.2, 0, 3.3, 0, 0, 0, 4.4, 0, 0, 5.5 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 3, 4 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4 ) + // CHECK-NEXT: crd[1] : ( 0, 3, 2, 3 ) + // CHECK-NEXT: values : ( 0, 1.1, 2.2, 0, 3.3, 0, 0, 0, 4.4, 0, 0, 5.5 ) // CHECK-NEXT: ---- %rowa = tensor.empty() : tensor<5x4x3xf64, #TensorRow> %row1 = tensor.insert %f1 into %rowa[%c3, %c0, %c1] : tensor<5x4x3xf64, #TensorRow> @@ -102,11 +102,11 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 5, 4, 3 ) // CHECK-NEXT: lvl = ( 5, 4, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 3, 4 - // CHECK-NEXT: pos[1] : ( 0, 3, 5 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 2, 3, 1, 2, 2, 3, 2 - // CHECK-NEXT: values : ( 1.1, 2.2, 3.3, 4.4, 5.5 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 3, 4 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 2, 3, 1, 2, 2, 3, 2 ) + // CHECK-NEXT: values : ( 1.1, 2.2, 3.3, 4.4, 5.5 ) // CHECK-NEXT: ---- %ccoo = tensor.empty() : tensor<5x4x3xf64, #CCoo> %ccoo1 = tensor.insert %f1 into %ccoo[%c3, %c0, %c1] : tensor<5x4x3xf64, #CCoo> @@ -121,9 +121,9 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 5, 4, 3 ) // CHECK-NEXT: lvl = ( 5, 4, 3 ) - // CHECK-NEXT: pos[1] : ( 0, 0, 0, 0, 3, 5 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 2, 3, 1, 2, 2, 3, 2 - // CHECK-NEXT: values : ( 1.1, 2.2, 3.3, 4.4, 5.5 + // CHECK-NEXT: pos[1] : ( 0, 0, 0, 0, 3, 5 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 2, 3, 1, 2, 2, 3, 2 ) + // CHECK-NEXT: values : ( 1.1, 2.2, 3.3, 4.4, 5.5 ) // CHECK-NEXT: ---- %dcoo = tensor.empty() : tensor<5x4x3xf64, #DCoo> %dcoo1 = tensor.insert %f1 into %dcoo[%c3, %c0, %c1] : tensor<5x4x3xf64, #DCoo> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_loose.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_loose.mlir index c05a9f574269..416c137a1dc3 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_loose.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_loose.mlir @@ -38,14 +38,17 @@ module { [13.0, 14.0, 15.0, 16.0 ]]> : tensor<5x4xf64> %s = sparse_tensor.convert %d : tensor<5x4xf64> to tensor<5x4xf64, #CSR_hi> + // + // Note: position for loose_compressed level can vary in the end, + // therefore we loosly check it with {{.*}}. // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 17 // CHECK-NEXT: dim = ( 5, 4 ) // CHECK-NEXT: lvl = ( 5, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 4, 4, 8, 8, 9, 9, 13 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 2, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 5.5, 9, 10, 11, 12, 13, 14, 15, 16 + // CHECK-NEXT: pos[1] : ( 0, 4, 4, 8, 8, 9, 9, 13, {{.*}} ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 2, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 5.5, 9, 10, 11, 12, 13, 14, 15, 16 ) // CHECK-NEXT: ---- // sparse_tensor.print %s : tensor<5x4xf64, #CSR_hi> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul.mlir index e505559037a9..14fa22a70134 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul.mlir @@ -146,9 +146,9 @@ module { // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[1] : ( 0, 8, 16, 24, 32 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7 - // CHECK-NEXT: values : ( 1.1, 2.1, 3.1, 4.1, 5.1, 6.1, 7.1, 8.1, 1.2, 2.2, 3.2, 4.2, 5.2, 6.2, 7.2, 8.2, 1.3, 2.3, 3.3, 4.3, 5.3, 6.3, 7.3, 8.3, 1.4, 2.4, 3.4, 4.4, 5.4, 6.4, 7.4, 8.4 + // CHECK-NEXT: pos[1] : ( 0, 8, 16, 24, 32 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7 ) + // CHECK-NEXT: values : ( 1.1, 2.1, 3.1, 4.1, 5.1, 6.1, 7.1, 8.1, 1.2, 2.2, 3.2, 4.2, 5.2, 6.2, 7.2, 8.2, 1.3, 2.3, 3.3, 4.3, 5.3, 6.3, 7.3, 8.3, 1.4, 2.4, 3.4, 4.4, 5.4, 6.4, 7.4, 8.4 ) // CHECK-NEXT: ---- // sparse_tensor.print %a1 : tensor<4x8xf64, #CSR> @@ -158,11 +158,11 @@ module { // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 8, 16, 24, 32 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7 - // CHECK-NEXT: values : ( 1.1, 2.1, 3.1, 4.1, 5.1, 6.1, 7.1, 8.1, 1.2, 2.2, 3.2, 4.2, 5.2, 6.2, 7.2, 8.2, 1.3, 2.3, 3.3, 4.3, 5.3, 6.3, 7.3, 8.3, 1.4, 2.4, 3.4, 4.4, 5.4, 6.4, 7.4, 8.4 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 8, 16, 24, 32 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7 ) + // CHECK-NEXT: values : ( 1.1, 2.1, 3.1, 4.1, 5.1, 6.1, 7.1, 8.1, 1.2, 2.2, 3.2, 4.2, 5.2, 6.2, 7.2, 8.2, 1.3, 2.3, 3.3, 4.3, 5.3, 6.3, 7.3, 8.3, 1.4, 2.4, 3.4, 4.4, 5.4, 6.4, 7.4, 8.4 ) // CHECK-NEXT: ---- // sparse_tensor.print %a2 : tensor<4x8xf64, #DCSR> @@ -172,9 +172,9 @@ module { // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 2, 3, 4 - // CHECK-NEXT: crd[1] : ( 1, 5, 1, 7 - // CHECK-NEXT: values : ( 2.1, 6.1, 2.3, 1 + // CHECK-NEXT: pos[1] : ( 0, 2, 2, 3, 4 ) + // CHECK-NEXT: crd[1] : ( 1, 5, 1, 7 ) + // CHECK-NEXT: values : ( 2.1, 6.1, 2.3, 1 ) // CHECK-NEXT: ---- // sparse_tensor.print %a3 : tensor<4x8xf64, #CSR> @@ -184,11 +184,11 @@ module { // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 4 - // CHECK-NEXT: crd[1] : ( 1, 5, 1, 7 - // CHECK-NEXT: values : ( 2.1, 6.1, 2.3, 1 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 4 ) + // CHECK-NEXT: crd[1] : ( 1, 5, 1, 7 ) + // CHECK-NEXT: values : ( 2.1, 6.1, 2.3, 1 ) // CHECK-NEXT: ---- // sparse_tensor.print %a4 : tensor<4x8xf64, #DCSR> @@ -198,9 +198,9 @@ module { // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 8, 4 ) // CHECK-NEXT: lvl = ( 8, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12, 16, 20, 24, 28, 32 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 10.1, 11.1, 12.1, 13.1, 10.2, 11.2, 12.2, 13.2, 10.3, 11.3, 12.3, 13.3, 10.4, 11.4, 12.4, 13.4, 10.5, 11.5, 12.5, 13.5, 10.6, 11.6, 12.6, 13.6, 10.7, 11.7, 12.7, 13.7, 10.8, 11.8, 12.8, 13.8 + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12, 16, 20, 24, 28, 32 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 10.1, 11.1, 12.1, 13.1, 10.2, 11.2, 12.2, 13.2, 10.3, 11.3, 12.3, 13.3, 10.4, 11.4, 12.4, 13.4, 10.5, 11.5, 12.5, 13.5, 10.6, 11.6, 12.6, 13.6, 10.7, 11.7, 12.7, 13.7, 10.8, 11.8, 12.8, 13.8 ) // CHECK-NEXT: ---- // sparse_tensor.print %b1 : tensor<8x4xf64, #CSR> @@ -210,11 +210,11 @@ module { // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 8, 4 ) // CHECK-NEXT: lvl = ( 8, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 8 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7 - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12, 16, 20, 24, 28, 32 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 10.1, 11.1, 12.1, 13.1, 10.2, 11.2, 12.2, 13.2, 10.3, 11.3, 12.3, 13.3, 10.4, 11.4, 12.4, 13.4, 10.5, 11.5, 12.5, 13.5, 10.6, 11.6, 12.6, 13.6, 10.7, 11.7, 12.7, 13.7, 10.8, 11.8, 12.8, 13.8 + // CHECK-NEXT: pos[0] : ( 0, 8 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7 ) + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12, 16, 20, 24, 28, 32 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 10.1, 11.1, 12.1, 13.1, 10.2, 11.2, 12.2, 13.2, 10.3, 11.3, 12.3, 13.3, 10.4, 11.4, 12.4, 13.4, 10.5, 11.5, 12.5, 13.5, 10.6, 11.6, 12.6, 13.6, 10.7, 11.7, 12.7, 13.7, 10.8, 11.8, 12.8, 13.8 ) // CHECK-NEXT: ---- // sparse_tensor.print %b2 : tensor<8x4xf64, #DCSR> @@ -224,9 +224,9 @@ module { // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 8, 4 ) // CHECK-NEXT: lvl = ( 8, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 2, 3, 4, 4, 5, 6, 8 - // CHECK-NEXT: crd[1] : ( 3, 2, 1, 0, 1, 2, 2, 3 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8 + // CHECK-NEXT: pos[1] : ( 0, 1, 2, 3, 4, 4, 5, 6, 8 ) + // CHECK-NEXT: crd[1] : ( 3, 2, 1, 0, 1, 2, 2, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8 ) // CHECK-NEXT: ---- // sparse_tensor.print %b3 : tensor<8x4xf64, #CSR> @@ -236,11 +236,11 @@ module { // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 8, 4 ) // CHECK-NEXT: lvl = ( 8, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 7 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 5, 6, 7 - // CHECK-NEXT: pos[1] : ( 0, 1, 2, 3, 4, 5, 6, 8 - // CHECK-NEXT: crd[1] : ( 3, 2, 1, 0, 1, 2, 2, 3 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8 + // CHECK-NEXT: pos[0] : ( 0, 7 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 5, 6, 7 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 2, 3, 4, 5, 6, 8 ) + // CHECK-NEXT: crd[1] : ( 3, 2, 1, 0, 1, 2, 2, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8 ) // CHECK-NEXT: ---- // sparse_tensor.print %b4 : tensor<8x4xf64, #DCSR> @@ -289,9 +289,9 @@ module { // CHECK-NEXT: nse = 16 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12, 16 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 388.76, 425.56, 462.36, 499.16, 397.12, 434.72, 472.32, 509.92, 405.48, 443.88, 482.28, 520.68, 413.84, 453.04, 492.24, 531.44 + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12, 16 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 388.76, 425.56, 462.36, 499.16, 397.12, 434.72, 472.32, 509.92, 405.48, 443.88, 482.28, 520.68, 413.84, 453.04, 492.24, 531.44 ) // CHECK-NEXT: ---- // sparse_tensor.print %1 : tensor<4x4xf64, #CSR> @@ -301,11 +301,11 @@ module { // CHECK-NEXT: nse = 16 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12, 16 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 388.76, 425.56, 462.36, 499.16, 397.12, 434.72, 472.32, 509.92, 405.48, 443.88, 482.28, 520.68, 413.84, 453.04, 492.24, 531.44 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12, 16 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 388.76, 425.56, 462.36, 499.16, 397.12, 434.72, 472.32, 509.92, 405.48, 443.88, 482.28, 520.68, 413.84, 453.04, 492.24, 531.44 ) // CHECK-NEXT: ---- // sparse_tensor.print %2 : tensor<4x4xf64, #DCSR> @@ -324,9 +324,9 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 4, 4, 8, 12 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 86.08, 94.28, 102.48, 110.68, 23.46, 25.76, 28.06, 30.36, 10.8, 11.8, 12.8, 13.8 + // CHECK-NEXT: pos[1] : ( 0, 4, 4, 8, 12 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 86.08, 94.28, 102.48, 110.68, 23.46, 25.76, 28.06, 30.36, 10.8, 11.8, 12.8, 13.8 ) // CHECK-NEXT: ---- // sparse_tensor.print %4 : tensor<4x4xf64, #CSR> @@ -336,11 +336,11 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 86.08, 94.28, 102.48, 110.68, 23.46, 25.76, 28.06, 30.36, 10.8, 11.8, 12.8, 13.8 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 4, 8, 12 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 86.08, 94.28, 102.48, 110.68, 23.46, 25.76, 28.06, 30.36, 10.8, 11.8, 12.8, 13.8 ) // CHECK-NEXT: ---- // sparse_tensor.print %5 : tensor<4x4xf64, #DCSR> @@ -359,9 +359,9 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 2, 3, 5 - // CHECK-NEXT: crd[1] : ( 1, 2, 2, 2, 3 - // CHECK-NEXT: values : ( 30.5, 4.2, 4.6, 7, 8 + // CHECK-NEXT: pos[1] : ( 0, 2, 2, 3, 5 ) + // CHECK-NEXT: crd[1] : ( 1, 2, 2, 2, 3 ) + // CHECK-NEXT: values : ( 30.5, 4.2, 4.6, 7, 8 ) // CHECK-NEXT: ---- // sparse_tensor.print %7 : tensor<4x4xf64, #CSR> @@ -371,11 +371,11 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 5 - // CHECK-NEXT: crd[1] : ( 1, 2, 2, 2, 3 - // CHECK-NEXT: values : ( 30.5, 4.2, 4.6, 7, 8 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 5 ) + // CHECK-NEXT: crd[1] : ( 1, 2, 2, 2, 3 ) + // CHECK-NEXT: values : ( 30.5, 4.2, 4.6, 7, 8 ) // CHECK-NEXT: ---- // sparse_tensor.print %8 : tensor<4x4xf64, #DCSR> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul_slice.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul_slice.mlir index 58e96d1fa51f..c76bf2ccfe35 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul_slice.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul_slice.mlir @@ -174,11 +174,11 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 5 - // CHECK-NEXT: crd[1] : ( 1, 2, 2, 2, 3 - // CHECK-NEXT: values : ( 30.5, 4.2, 4.6, 7, 8 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 5 ) + // CHECK-NEXT: crd[1] : ( 1, 2, 2, 2, 3 ) + // CHECK-NEXT: values : ( 30.5, 4.2, 4.6, 7, 8 ) // CHECK-NEXT: ---- // sparse_tensor.print %2 : tensor<4x4xf64, #DCSR> @@ -196,9 +196,9 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 2, 3, 5 - // CHECK-NEXT: crd[1] : ( 1, 2, 2, 2, 3 - // CHECK-NEXT: values : ( 30.5, 4.2, 4.6, 7, 8 + // CHECK-NEXT: pos[1] : ( 0, 2, 2, 3, 5 ) + // CHECK-NEXT: crd[1] : ( 1, 2, 2, 2, 3 ) + // CHECK-NEXT: values : ( 30.5, 4.2, 4.6, 7, 8 ) // CHECK-NEXT: ---- // sparse_tensor.print %3 : tensor<4x4xf64, #CSR> @@ -210,9 +210,9 @@ module { // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 2, 2, 3 - // CHECK-NEXT: crd[1] : ( 0, 0, 0 - // CHECK-NEXT: values : ( 2.3, 6.9, 12.6 + // CHECK-NEXT: pos[1] : ( 0, 1, 2, 2, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 0, 0 ) + // CHECK-NEXT: values : ( 2.3, 6.9, 12.6 ) // CHECK-NEXT: ---- // %s1 = tensor.extract_slice %tmp[0, 1][4, 4][2, 1] : tensor<8x8xf64, #DCSR> to tensor<4x4xf64, #DCSR_SLICE_1> @@ -228,9 +228,9 @@ module { // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 0, 1, 0, 3, 0 - // CHECK-NEXT: values : ( 2.3, 6.9, 12.6 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 0, 1, 0, 3, 0 ) + // CHECK-NEXT: values : ( 2.3, 6.9, 12.6 ) // CHECK-NEXT: ---- // %t1_coo = sparse_tensor.convert %sa : tensor<8x8xf64> to tensor<8x8xf64, #COO> @@ -246,9 +246,9 @@ module { // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 2, 2, 3 - // CHECK-NEXT: crd[1] : ( 0, 0, 0 - // CHECK-NEXT: values : ( 2.3, 6.9, 12.6 + // CHECK-NEXT: pos[1] : ( 0, 1, 2, 2, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 0, 0 ) + // CHECK-NEXT: values : ( 2.3, 6.9, 12.6 ) // CHECK-NEXT: ---- // %s1_dyn = tensor.extract_slice %tmp[%c_0, %c_1][4, 4][%c_2, %c_1] : tensor<8x8xf64, #DCSR> to tensor<4x4xf64, #DCSR_SLICE_dyn> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matrix_ops.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matrix_ops.mlir index 8ea26fa3efdf..770c4f55a280 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matrix_ops.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matrix_ops.mlir @@ -163,11 +163,11 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 - // CHECK-NEXT: crd[1] : ( 0, 1, 7, 2, 4, 7, 0, 2, 3 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 7, 2, 4, 7, 0, 2, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9 ) // CHECK-NEXT: ---- // sparse_tensor.print %sm1 : tensor @@ -177,11 +177,11 @@ module { // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 - // CHECK-NEXT: crd[1] : ( 0, 7, 0, 6, 1, 7 - // CHECK-NEXT: values : ( 6, 5, 4, 3, 2, 1 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 7, 0, 6, 1, 7 ) + // CHECK-NEXT: values : ( 6, 5, 4, 3, 2, 1 ) // CHECK-NEXT: ---- // sparse_tensor.print %sm2 : tensor @@ -191,11 +191,11 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 - // CHECK-NEXT: crd[1] : ( 0, 1, 7, 2, 4, 7, 0, 2, 3 - // CHECK-NEXT: values : ( 2, 4, 6, 8, 10, 12, 14, 16, 18 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 7, 2, 4, 7, 0, 2, 3 ) + // CHECK-NEXT: values : ( 2, 4, 6, 8, 10, 12, 14, 16, 18 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor @@ -205,11 +205,11 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 - // CHECK-NEXT: crd[1] : ( 0, 1, 7, 2, 4, 7, 0, 2, 3 - // CHECK-NEXT: values : ( 2, 4, 6, 8, 10, 12, 14, 16, 18 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 7, 2, 4, 7, 0, 2, 3 ) + // CHECK-NEXT: values : ( 2, 4, 6, 8, 10, 12, 14, 16, 18 ) // CHECK-NEXT: ---- // sparse_tensor.print %1 : tensor @@ -219,11 +219,11 @@ module { // CHECK-NEXT: nse = 13 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 3, 6, 10, 13 - // CHECK-NEXT: crd[1] : ( 0, 1, 7, 0, 6, 7, 1, 2, 4, 7, 0, 2, 3 - // CHECK-NEXT: values : ( 8, 4, 5, 4, 3, 6, 2, 8, 10, 13, 14, 16, 18 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 6, 10, 13 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 7, 0, 6, 7, 1, 2, 4, 7, 0, 2, 3 ) + // CHECK-NEXT: values : ( 8, 4, 5, 4, 3, 6, 2, 8, 10, 13, 14, 16, 18 ) // CHECK-NEXT: ---- // sparse_tensor.print %2 : tensor @@ -233,11 +233,11 @@ module { // CHECK-NEXT: nse = 2 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 2 - // CHECK-NEXT: pos[1] : ( 0, 1, 2 - // CHECK-NEXT: crd[1] : ( 0, 7 - // CHECK-NEXT: values : ( 12, 12 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 2 ) + // CHECK-NEXT: crd[1] : ( 0, 7 ) + // CHECK-NEXT: values : ( 12, 12 ) // CHECK-NEXT: ---- // sparse_tensor.print %3 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_mult_elt.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_mult_elt.mlir index c30c6b9b5cc2..683be61be2a2 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_mult_elt.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_mult_elt.mlir @@ -88,11 +88,11 @@ module { // CHECK-NEXT: nse = 2 // CHECK-NEXT: dim = ( 32, 16 ) // CHECK-NEXT: lvl = ( 32, 16 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 2, 31 - // CHECK-NEXT: pos[1] : ( 0, 1, 2 - // CHECK-NEXT: crd[1] : ( 2, 0 - // CHECK-NEXT: values : ( 14, 20 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 2, 31 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 2 ) + // CHECK-NEXT: crd[1] : ( 2, 0 ) + // CHECK-NEXT: values : ( 14, 20 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor<32x16xf32, #DCSR> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_reduction.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_reduction.mlir index 74f0e7698bc1..8eadc348020f 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_reduction.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_reduction.mlir @@ -95,11 +95,11 @@ module { // CHECK-NEXT: nse = 2 // CHECK-NEXT: dim = ( 3, 3 ) // CHECK-NEXT: lvl = ( 3, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 1, 2 - // CHECK-NEXT: pos[1] : ( 0, 1, 2 - // CHECK-NEXT: crd[1] : ( 1, 2 - // CHECK-NEXT: values : ( 7, 69 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 1, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 2 ) + // CHECK-NEXT: crd[1] : ( 1, 2 ) + // CHECK-NEXT: values : ( 7, 69 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_simple.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_simple.mlir index 88513c80219a..334ffe492952 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_simple.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_simple.mlir @@ -87,11 +87,11 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 5, 5 ) // CHECK-NEXT: lvl = ( 5, 5 ) - // CHECK-NEXT: pos[0] : ( 0, 5 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 5, 7, 9 - // CHECK-NEXT: crd[1] : ( 0, 3, 1, 4, 2, 0, 3, 1, 4 - // CHECK-NEXT: values : ( 1, 1.96, 4, 6.25, 9, 16.81, 16, 27.04, 25 + // CHECK-NEXT: pos[0] : ( 0, 5 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 5, 7, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 3, 1, 4, 2, 0, 3, 1, 4 ) + // CHECK-NEXT: values : ( 1, 1.96, 4, 6.25, 9, 16.81, 16, 27.04, 25 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack_d.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack_d.mlir index 467a77f30777..b48ff9c9df74 100755 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack_d.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack_d.mlir @@ -111,29 +111,29 @@ module { // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 4, 3, 2 ) // CHECK-NEXT: lvl = ( 4, 3, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 0, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 5 - // CHECK-NEXT: crd[1] : ( 0, 1, 1, 2, 1 - // CHECK-NEXT: pos[2] : ( 0, 2, 4, 5, 7, 8 - // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 0, 1, 0 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 5 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 1, 2, 1 ) + // CHECK-NEXT: pos[2] : ( 0, 2, 4, 5, 7, 8 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 0, 1, 0, 0, 1, 0 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 16 // CHECK-NEXT: dim = ( 4, 3, 2 ) // CHECK-NEXT: lvl = ( 4, 3, 2 ) - // CHECK-NEXT: pos[2] : ( 0, 2, 3, 4, 6, 6, 7, 9, 11, 13, 14, 15, 16 - // CHECK-NEXT: crd[2] : ( 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0, 1, 1 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 + // CHECK-NEXT: pos[2] : ( 0, 2, 3, 4, 6, 6, 7, 9, 11, 13, 14, 15, 16 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0, 1, 1 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 22 // CHECK-NEXT: dim = ( 4, 3, 2 ) // CHECK-NEXT: lvl = ( 4, 3, 2 ) - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 8, 11 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 2, 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: values : ( 1, 2, 0, 3, 4, 0, 5, 6, 0, 7, 8, 9, 10, 11, 12, 13, 14, 0, 0, 15, 0, 16 + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 8, 11 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 2, 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: values : ( 1, 2, 0, 3, 4, 0, 5, 6, 0, 7, 8, 9, 10, 11, 12, 13, 14, 0, 0, 15, 0, 16 ) // CHECK-NEXT: ---- // sparse_tensor.print %s0 : tensor<4x3x2xf32, #CCC> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pooling_nhwc.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pooling_nhwc.mlir index 39699fbdb14e..7c78bfc36200 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pooling_nhwc.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pooling_nhwc.mlir @@ -80,15 +80,15 @@ func.func @main() { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 1, 3, 3, 1 ) // CHECK-NEXT: lvl = ( 1, 3, 3, 1 ) - // CHECK-NEXT: pos[0] : ( 0, 1 - // CHECK-NEXT: crd[0] : ( 0 - // CHECK-NEXT: pos[1] : ( 0, 3 - // CHECK-NEXT: crd[1] : ( 0, 1, 2 - // CHECK-NEXT: pos[2] : ( 0, 3, 6, 9 - // CHECK-NEXT: crd[2] : ( 0, 1, 2, 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: pos[3] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 - // CHECK-NEXT: crd[3] : ( 0, 0, 0, 0, 0, 0, 0, 0, 0 - // CHECK-NEXT: values : ( 6, 6, 6, 6, 6, 6, 6, 6, 6 + // CHECK-NEXT: pos[0] : ( 0, 1 ) + // CHECK-NEXT: crd[0] : ( 0 ) + // CHECK-NEXT: pos[1] : ( 0, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2 ) + // CHECK-NEXT: pos[2] : ( 0, 3, 6, 9 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 2, 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: pos[3] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ) + // CHECK-NEXT: crd[3] : ( 0, 0, 0, 0, 0, 0, 0, 0, 0 ) + // CHECK-NEXT: values : ( 6, 6, 6, 6, 6, 6, 6, 6, 6 ) // CHECK-NEXT: ---- // sparse_tensor.print %CCCC_ret : tensor<1x3x3x1xf32, #CCCC> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_print.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_print.mlir index b664b7f99944..f3c721535e75 100755 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_print.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_print.mlir @@ -147,7 +147,7 @@ module { // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 5, 0, 0, ) + // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 5, 0, 0 ) // CHECK-NEXT: ---- sparse_tensor.print %XO : tensor<4x8xi32, #AllDense> @@ -155,7 +155,7 @@ module { // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 8, 4 ) - // CHECK-NEXT: values : ( 1, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, ) + // CHECK-NEXT: values : ( 1, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0 ) // CHECK-NEXT: ---- sparse_tensor.print %XT : tensor<4x8xi32, #AllDenseT> @@ -176,9 +176,9 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 2, 2, 5, ) - // CHECK-NEXT: crd[1] : ( 0, 2, 2, 3, 5, ) - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, ) + // CHECK-NEXT: pos[1] : ( 0, 2, 2, 2, 5 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 2, 3, 5 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5 ) // CHECK-NEXT: ---- sparse_tensor.print %a : tensor<4x8xi32, #CSR> @@ -186,11 +186,11 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 2, ) - // CHECK-NEXT: crd[0] : ( 0, 3, ) - // CHECK-NEXT: pos[1] : ( 0, 2, 5, ) - // CHECK-NEXT: crd[1] : ( 0, 2, 2, 3, 5, ) - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, ) + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 5 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 2, 3, 5 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5 ) // CHECK-NEXT: ---- sparse_tensor.print %b : tensor<4x8xi32, #DCSR> @@ -198,9 +198,9 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 8, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 1, 3, 4, 4, 5, 5, 5, ) - // CHECK-NEXT: crd[1] : ( 0, 0, 3, 3, 3, ) - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, ) + // CHECK-NEXT: pos[1] : ( 0, 1, 1, 3, 4, 4, 5, 5, 5 ) + // CHECK-NEXT: crd[1] : ( 0, 0, 3, 3, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5 ) // CHECK-NEXT: ---- sparse_tensor.print %c : tensor<4x8xi32, #CSC> @@ -208,11 +208,11 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 8, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 4, ) - // CHECK-NEXT: crd[0] : ( 0, 2, 3, 5, ) - // CHECK-NEXT: pos[1] : ( 0, 1, 3, 4, 5, ) - // CHECK-NEXT: crd[1] : ( 0, 0, 3, 3, 3, ) - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, ) + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 3, 5 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 3, 4, 5 ) + // CHECK-NEXT: crd[1] : ( 0, 0, 3, 3, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5 ) // CHECK-NEXT: ---- sparse_tensor.print %d : tensor<4x8xi32, #DCSC> @@ -220,11 +220,11 @@ module { // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 2, 2, 2, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 2, ) - // CHECK-NEXT: crd[0] : ( 0, 1, ) - // CHECK-NEXT: pos[1] : ( 0, 1, 3, ) - // CHECK-NEXT: crd[1] : ( 0, 0, 1, ) - // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 0, 5, 0, 0, ) + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 0, 1 ) + // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 0, 5, 0, 0 ) // CHECK-NEXT: ---- sparse_tensor.print %e : tensor<4x8xi32, #BSR> @@ -232,11 +232,11 @@ module { // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 2, 2, 4, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 2, ) - // CHECK-NEXT: crd[0] : ( 0, 1, ) - // CHECK-NEXT: pos[1] : ( 0, 1, 3, ) - // CHECK-NEXT: crd[1] : ( 0, 0, 1, ) - // CHECK-NEXT: values : ( 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 4, 0, 0, 0, 5, 0, 0, 0, 0, ) + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 0, 1 ) + // CHECK-NEXT: values : ( 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 4, 0, 0, 0, 5, 0, 0, 0, 0 ) // CHECK-NEXT: ---- sparse_tensor.print %f : tensor<4x8xi32, #BSRC> @@ -244,11 +244,11 @@ module { // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 2, 2, 2, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 2, ) - // CHECK-NEXT: crd[0] : ( 0, 1, ) - // CHECK-NEXT: pos[1] : ( 0, 2, 3, ) - // CHECK-NEXT: crd[1] : ( 0, 1, 1, ) - // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 0, 5, 0, 0, ) + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 1 ) + // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 0, 5, 0, 0 ) // CHECK-NEXT: ---- sparse_tensor.print %g : tensor<4x8xi32, #BSC> @@ -256,11 +256,11 @@ module { // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 2, 2, 4, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 2, ) - // CHECK-NEXT: crd[0] : ( 0, 1, ) - // CHECK-NEXT: pos[1] : ( 0, 2, 3, ) - // CHECK-NEXT: crd[1] : ( 0, 1, 1, ) - // CHECK-NEXT: values : ( 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 4, 0, 0, 0, 5, 0, 0, 0, 0, ) + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 1 ) + // CHECK-NEXT: values : ( 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 4, 0, 0, 0, 5, 0, 0, 0, 0 ) // CHECK-NEXT: ---- sparse_tensor.print %h : tensor<4x8xi32, #BSCC> @@ -268,9 +268,9 @@ module { // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 2, 2, 2, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 3, ) - // CHECK-NEXT: crd[1] : ( 0, 0, 1, ) - // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 0, 5, 0, 0, ) + // CHECK-NEXT: pos[1] : ( 0, 1, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 0, 1 ) + // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 0, 5, 0, 0 ) // CHECK-NEXT: ---- sparse_tensor.print %i : tensor<4x8xi32, #BSR0> @@ -278,9 +278,9 @@ module { // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 2, 2, 2, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 3, ) - // CHECK-NEXT: crd[1] : ( 0, 1, 1, ) - // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 0, 5, 0, 0, ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 1 ) + // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 0, 5, 0, 0 ) // CHECK-NEXT: ---- sparse_tensor.print %j : tensor<4x8xi32, #BSC0> @@ -288,9 +288,9 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 5, ) - // CHECK-NEXT: crd[0] : ( 0, 0, 0, 2, 3, 2, 3, 3, 3, 5, ) - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, ) + // CHECK-NEXT: pos[0] : ( 0, 5 ) + // CHECK-NEXT: crd[0] : ( 0, 0, 0, 2, 3, 2, 3, 3, 3, 5 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5 ) // CHECK-NEXT: ---- sparse_tensor.print %AoS : tensor<4x8xi32, #COOAoS> @@ -298,10 +298,10 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 5, ) - // CHECK-NEXT: crd[0] : ( 0, 0, 3, 3, 3, ) - // CHECK-NEXT: crd[1] : ( 0, 2, 2, 3, 5, ) - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, ) + // CHECK-NEXT: pos[0] : ( 0, 5 ) + // CHECK-NEXT: crd[0] : ( 0, 0, 3, 3, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 2, 3, 5 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5 ) // CHECK-NEXT: ---- sparse_tensor.print %SoA : tensor<4x8xi32, #COOSoA> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_print_3d.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_print_3d.mlir index 98dee304fa51..4f1e4312d7bc 100755 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_print_3d.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_print_3d.mlir @@ -61,11 +61,11 @@ module { // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 2, 4, 8 ) // CHECK-NEXT: lvl = ( 2, 4, 8 ) - // CHECK-NEXT: pos[2] : ( ( 0, 8, 16, 24, 32, )( 0, 8, 16, 24, 32, ) ) - // CHECK-NEXT: crd[2] : ( ( 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, ) - // CHECK-SAME: ( 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, ) ) - // CHECK-NEXT: values : ( ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ) - // CHECK-SAME: ( 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, ) ) + // CHECK-NEXT: pos[2] : ( ( 0, 8, 16, 24, 32 )( 0, 8, 16, 24, 32 ) ) + // CHECK-NEXT: crd[2] : ( ( 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7 ) + // CHECK-SAME: ( 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7 ) ) + // CHECK-NEXT: values : ( ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 ) + // CHECK-SAME: ( 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 ) ) // CHECK-NEXT: ---- sparse_tensor.print %X : tensor<2x4x8xf64, #BatchedCSR> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_re_im.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_re_im.mlir index 7bacbe3b87e4..fc23fe501fcf 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_re_im.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_re_im.mlir @@ -93,18 +93,18 @@ module { // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 0, 20, 31, - // CHECK-NEXT: values : ( 5.13, 3, 5, + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 20, 31 ) + // CHECK-NEXT: values : ( 5.13, 3, 5 ) // CHECK-NEXT: ---- // // CHECK-NEXT: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 3, - // CHECK-NEXT: crd[0] : ( 0, 20, 31, - // CHECK-NEXT: values : ( 2, 4, 6, + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 0, 20, 31 ) + // CHECK-NEXT: values : ( 2, 4, 6 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reduce_custom.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reduce_custom.mlir index a927a5dfb94b..5da028c3685c 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reduce_custom.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reduce_custom.mlir @@ -144,33 +144,33 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 4, 5 ) // CHECK-NEXT: lvl = ( 4, 5 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 2, 3, 4, 0, 2, 3 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9 + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 2, 3, 4, 0, 2, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 5, 4 ) // CHECK-NEXT: lvl = ( 5, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 2, 4, 5, 6 - // CHECK-NEXT: crd[1] : ( 0, 3, 0, 3, 1, 1 - // CHECK-NEXT: values : ( 6, 5, 4, 3, 2, 11 + // CHECK-NEXT: pos[1] : ( 0, 1, 2, 4, 5, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 3, 0, 3, 1, 1 ) + // CHECK-NEXT: values : ( 6, 5, 4, 3, 2, 11 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 - // CHECK-NEXT: crd[1] : ( 0, 3, 0, 0, 1, 3, 0, 1, 3 - // CHECK-NEXT: values : ( 7, 7, 9, 8, 7, 7, 12, 11, 11 + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 3, 0, 0, 1, 3, 0, 1, 3 ) + // CHECK-NEXT: values : ( 7, 7, 9, 8, 7, 7, 12, 11, 11 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 4, 4 ) // CHECK-NEXT: lvl = ( 4, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 - // CHECK-NEXT: crd[1] : ( 0, 3, 0, 0, 1, 3, 0, 1, 3 - // CHECK-NEXT: values : ( 7, 7, 9, 8, 7, 7, 12, 11, 11 + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 3, 0, 0, 1, 3, 0, 1, 3 ) + // CHECK-NEXT: values : ( 7, 7, 9, 8, 7, 7, 12, 11, 11 ) // CHECK-NEXT: ---- // sparse_tensor.print %sm1 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reduce_custom_prod.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reduce_custom_prod.mlir index 18bf6a71c530..d32a92e337ba 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reduce_custom_prod.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reduce_custom_prod.mlir @@ -118,33 +118,33 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 4, 5 ) // CHECK-NEXT: lvl = ( 4, 5 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 2, 3, 4, 0, 2, 3 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9 + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 2, 3, 4, 0, 2, 3 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 5, 4 ) // CHECK-NEXT: lvl = ( 5, 4 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 2, 4, 5, 6 - // CHECK-NEXT: crd[1] : ( 0, 3, 0, 3, 1, 1 - // CHECK-NEXT: values : ( 6, 5, 4, 3, 2, 11 + // CHECK-NEXT: pos[1] : ( 0, 1, 2, 4, 5, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 3, 0, 3, 1, 1 ) + // CHECK-NEXT: values : ( 6, 5, 4, 3, 2, 11 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 4 ) // CHECK-NEXT: lvl = ( 4 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: values : ( 2, 3, 120, 504 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 2, 3, 120, 504 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 5 ) // CHECK-NEXT: lvl = ( 5 ) - // CHECK-NEXT: pos[0] : ( 0, 5 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4 - // CHECK-NEXT: values : ( 6, 5, 12, 2, 11 + // CHECK-NEXT: pos[0] : ( 0, 5 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4 ) + // CHECK-NEXT: values : ( 6, 5, 12, 2, 11 ) // CHECK-NEXT: ---- // sparse_tensor.print %sm1 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reshape.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reshape.mlir index 4c26ebe6e401..317fe0f225ee 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reshape.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reshape.mlir @@ -81,31 +81,31 @@ module { // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 2, 6 ) // CHECK-NEXT: lvl = ( 2, 6 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 1 - // CHECK-NEXT: pos[1] : ( 0, 3, 6 - // CHECK-NEXT: crd[1] : ( 0, 2, 4, 0, 2, 4 - // CHECK-NEXT: values : ( 1.1, 1.3, 2.1, 2.3, 3.1, 3.3 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 4, 0, 2, 4 ) + // CHECK-NEXT: values : ( 1.1, 1.3, 2.1, 2.3, 3.1, 3.3 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 12 ) // CHECK-NEXT: lvl = ( 12 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 2, 4, 6, 8, 10 - // CHECK-NEXT: values : ( 1.1, 1.3, 2.1, 2.3, 3.1, 3.3 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 4, 6, 8, 10 ) + // CHECK-NEXT: values : ( 1.1, 1.3, 2.1, 2.3, 3.1, 3.3 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 2, 3, 2 ) // CHECK-NEXT: lvl = ( 2, 3, 2 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 1 - // CHECK-NEXT: pos[1] : ( 0, 3, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: pos[2] : ( 0, 1, 2, 3, 4, 5, 6 - // CHECK-NEXT: crd[2] : ( 0, 0, 0, 0, 0, 0 - // CHECK-NEXT: values : ( 1.1, 1.3, 2.1, 2.3, 3.1, 3.3 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: pos[2] : ( 0, 1, 2, 3, 4, 5, 6 ) + // CHECK-NEXT: crd[2] : ( 0, 0, 0, 0, 0, 0 ) + // CHECK-NEXT: values : ( 1.1, 1.3, 2.1, 2.3, 3.1, 3.3 ) // CHECK-NEXT: ---- // sparse_tensor.print %reshaped0: tensor<2x6xf64, #SparseMatrix> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_mm_fusion.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_mm_fusion.mlir index 20a8c5f812de..eecd970e01ac 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_mm_fusion.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_mm_fusion.mlir @@ -211,22 +211,22 @@ module { // CHECK-NEXT: nse = 2 // CHECK-NEXT: dim = ( 8, 8 ) // CHECK-NEXT: lvl = ( 8, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 7 - // CHECK-NEXT: pos[1] : ( 0, 1, 2 - // CHECK-NEXT: crd[1] : ( 0, 7 - // CHECK-NEXT: values : ( 96, 192 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 7 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 2 ) + // CHECK-NEXT: crd[1] : ( 0, 7 ) + // CHECK-NEXT: values : ( 96, 192 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 2 // CHECK-NEXT: dim = ( 8, 8 ) // CHECK-NEXT: lvl = ( 8, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 7 - // CHECK-NEXT: pos[1] : ( 0, 1, 2 - // CHECK-NEXT: crd[1] : ( 0, 7 - // CHECK-NEXT: values : ( 96, 192 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 7 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 2 ) + // CHECK-NEXT: crd[1] : ( 0, 7 ) + // CHECK-NEXT: values : ( 96, 192 ) // CHECK-NEXT: ---- // %v0 = vector.transfer_read %0[%c0, %c0], %d0 diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scale.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scale.mlir index 4e9090ae201d..c62cdc900b83 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scale.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scale.mlir @@ -92,9 +92,9 @@ module { // CHECK-NEXT: nse = 16 // CHECK-NEXT: dim = ( 8, 8 ) // CHECK-NEXT: lvl = ( 8, 8 ) - // CHECK-NEXT: pos[1] : ( 0, 3, 4, 5, 6, 8, 11, 14, 16 - // CHECK-NEXT: crd[1] : ( 0, 2, 7, 1, 2, 3, 1, 4, 1, 2, 5, 2, 6, 7, 2, 7 - // CHECK-NEXT: values : ( 2, 2, 2, 4, 6, 8, 2, 10, 2, 2, 12, 2, 14, 2, 2, 16 + // CHECK-NEXT: pos[1] : ( 0, 3, 4, 5, 6, 8, 11, 14, 16 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 7, 1, 2, 3, 1, 4, 1, 2, 5, 2, 6, 7, 2, 7 ) + // CHECK-NEXT: values : ( 2, 2, 2, 4, 6, 8, 2, 10, 2, 2, 12, 2, 14, 2, 2, 16 ) // CHECK-NEXT: ---- // sparse_tensor.print %2 : tensor<8x8xf32, #CSR> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scf_nested.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scf_nested.mlir index dd8396dc23b0..3f0cf70675ba 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scf_nested.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scf_nested.mlir @@ -91,25 +91,25 @@ module @func_sparse.2 { // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 2, 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 1 - // CHECK-NEXT: pos[1] : ( 0, 3, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: pos[2] : ( 0, 4, 8, 12, 16, 20, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: pos[2] : ( 0, 4, 8, 12, 16, 20, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 2, 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 1 - // CHECK-NEXT: pos[1] : ( 0, 3, 6 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 - // CHECK-NEXT: pos[2] : ( 0, 4, 8, 12, 16, 20, 24 - // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 - // CHECK-NEXT: values : ( 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 1 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 0, 1, 2 ) + // CHECK-NEXT: pos[2] : ( 0, 4, 8, 12, 16, 20, 24 ) + // CHECK-NEXT: crd[2] : ( 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3 ) + // CHECK-NEXT: values : ( 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 ) // CHECK-NEXT: ---- // sparse_tensor.print %sm_t : tensor<2x3x4xf64, #SparseMatrix> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_select.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_select.mlir index 68bc17175e3b..bd61563b4b2d 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_select.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_select.mlir @@ -124,33 +124,33 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 10 ) // CHECK-NEXT: lvl = ( 10 ) - // CHECK-NEXT: pos[0] : ( 0, 5 - // CHECK-NEXT: crd[0] : ( 1, 3, 5, 7, 9 - // CHECK-NEXT: values : ( 1, 2, -4, 0, 5 + // CHECK-NEXT: pos[0] : ( 0, 5 ) + // CHECK-NEXT: crd[0] : ( 1, 3, 5, 7, 9 ) + // CHECK-NEXT: values : ( 1, 2, -4, 0, 5 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 7 // CHECK-NEXT: dim = ( 5, 5 ) // CHECK-NEXT: lvl = ( 5, 5 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 2, 4, 6, 7 - // CHECK-NEXT: crd[1] : ( 3, 4, 1, 3, 3, 4, 2 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 + // CHECK-NEXT: pos[1] : ( 0, 1, 2, 4, 6, 7 ) + // CHECK-NEXT: crd[1] : ( 3, 4, 1, 3, 3, 4, 2 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 3 // CHECK-NEXT: dim = ( 10 ) // CHECK-NEXT: lvl = ( 10 ) - // CHECK-NEXT: pos[0] : ( 0, 3 - // CHECK-NEXT: crd[0] : ( 1, 3, 9 - // CHECK-NEXT: values : ( 1, 2, 5 + // CHECK-NEXT: pos[0] : ( 0, 3 ) + // CHECK-NEXT: crd[0] : ( 1, 3, 9 ) + // CHECK-NEXT: values : ( 1, 2, 5 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 5, 5 ) // CHECK-NEXT: lvl = ( 5, 5 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 2, 3, 4, 4 - // CHECK-NEXT: crd[1] : ( 3, 4, 3, 4 - // CHECK-NEXT: values : ( 1, 2, 4, 6 + // CHECK-NEXT: pos[1] : ( 0, 1, 2, 3, 4, 4 ) + // CHECK-NEXT: crd[1] : ( 3, 4, 3, 4 ) + // CHECK-NEXT: values : ( 1, 2, 4, 6 ) // CHECK-NEXT: ---- // sparse_tensor.print %sv1 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_semiring_select.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_semiring_select.mlir index f4435c81117b..d96b07a0db33 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_semiring_select.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_semiring_select.mlir @@ -91,11 +91,11 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 5, 5 ) // CHECK-NEXT: lvl = ( 5, 5 ) - // CHECK-NEXT: pos[0] : ( 0, 5 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4 - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, 8, 9 - // CHECK-NEXT: crd[1] : ( 0, 1, 1, 2, 2, 3, 3, 4, 4 - // CHECK-NEXT: values : ( 0.1, 1.1, 1.1, 2.2, 2.1, 3.3, 3.1, 4.4, 4.1 + // CHECK-NEXT: pos[0] : ( 0, 5 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 6, 8, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 1, 2, 2, 3, 3, 4, 4 ) + // CHECK-NEXT: values : ( 0.1, 1.1, 1.1, 2.2, 2.1, 3.3, 3.1, 4.4, 4.1 ) // CHECK-NEXT: ---- // sparse_tensor.print %1 : tensor<5x5xf64, #DCSR> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sign.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sign.mlir index c09374918b7d..11d23d681c82 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sign.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sign.mlir @@ -114,9 +114,9 @@ module { // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 12 - // CHECK-NEXT: crd[0] : ( 0, 3, 5, 11, 13, 17, 18, 20, 21, 28, 29, 31 - // CHECK-NEXT: values : ( -1, 1, -1, 1, 1, -1, nan, -nan, 1, -1, -0, 0 + // CHECK-NEXT: pos[0] : ( 0, 12 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 5, 11, 13, 17, 18, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( -1, 1, -1, 1, 1, -1, nan, -nan, 1, -1, -0, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sorted_coo.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sorted_coo.mlir index 7b3f9a2ce0e0..3117d2539f17 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sorted_coo.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sorted_coo.mlir @@ -107,10 +107,10 @@ module { // CHECK-NEXT: nse = 17 // CHECK-NEXT: dim = ( 4, 256 ) // CHECK-NEXT: lvl = ( 4, 256 ) - // CHECK-NEXT: pos[0] : ( 0, 17 - // CHECK-NEXT: crd[0] : ( 0, 0, 0, 0, 1, 1, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 - // CHECK-NEXT: crd[1] : ( 0, 126, 127, 254, 1, 253, 2, 0, 1, 3, 98, 126, 127, 128, 249, 253, 255 - // CHECK-NEXT: values : ( -1, 2, -3, 4, -5, 6, -7, 8, -9, 10, -11, 12, -13, 14, -15, 16, -17 + // CHECK-NEXT: pos[0] : ( 0, 17 ) + // CHECK-NEXT: crd[0] : ( 0, 0, 0, 0, 1, 1, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 126, 127, 254, 1, 253, 2, 0, 1, 3, 98, 126, 127, 128, 249, 253, 255 ) + // CHECK-NEXT: values : ( -1, 2, -3, 4, -5, 6, -7, 8, -9, 10, -11, 12, -13, 14, -15, 16, -17 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor @@ -120,10 +120,10 @@ module { // CHECK-NEXT: nse = 17 // CHECK-NEXT: dim = ( 4, 256 ) // CHECK-NEXT: lvl = ( 256, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 17 - // CHECK-NEXT: crd[0] : ( 0, 0, 1, 1, 2, 3, 98, 126, 126, 127, 127, 128, 249, 253, 253, 254, 255 - // CHECK-NEXT: crd[1] : ( 0, 3, 1, 3, 2, 3, 3, 0, 3, 0, 3, 3, 3, 1, 3, 0, 3 - // CHECK-NEXT: values : ( -1, 8, -5, -9, -7, 10, -11, 2, 12, -3, -13, 14, -15, 6, 16, 4, -17 + // CHECK-NEXT: pos[0] : ( 0, 17 ) + // CHECK-NEXT: crd[0] : ( 0, 0, 1, 1, 2, 3, 98, 126, 126, 127, 127, 128, 249, 253, 253, 254, 255 ) + // CHECK-NEXT: crd[1] : ( 0, 3, 1, 3, 2, 3, 3, 0, 3, 0, 3, 3, 3, 1, 3, 0, 3 ) + // CHECK-NEXT: values : ( -1, 8, -5, -9, -7, 10, -11, 2, 12, -3, -13, 14, -15, 6, 16, 4, -17 ) // CHECK-NEXT: ---- // sparse_tensor.print %1 : tensor @@ -133,11 +133,11 @@ module { // CHECK-NEXT: nse = 17 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 2, 3, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 17 - // CHECK-NEXT: crd[0] : ( 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 - // CHECK-NEXT: crd[1] : ( 0, 0, 1, 1, 2, 2, 2, 2, 0, 0, 0, 1, 1, 1, 1, 2, 2 - // CHECK-NEXT: crd[2] : ( 2, 3, 1, 2, 0, 1, 2, 3, 0, 2, 3, 0, 1, 2, 3, 1, 2 - // CHECK-NEXT: values : ( 3, 63, 11, 100, 66, 61, 13, 43, 77, 10, 46, 61, 53, 3, 75, 22, 18 + // CHECK-NEXT: pos[0] : ( 0, 17 ) + // CHECK-NEXT: crd[0] : ( 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 ) + // CHECK-NEXT: crd[1] : ( 0, 0, 1, 1, 2, 2, 2, 2, 0, 0, 0, 1, 1, 1, 1, 2, 2 ) + // CHECK-NEXT: crd[2] : ( 2, 3, 1, 2, 0, 1, 2, 3, 0, 2, 3, 0, 1, 2, 3, 1, 2 ) + // CHECK-NEXT: values : ( 3, 63, 11, 100, 66, 61, 13, 43, 77, 10, 46, 61, 53, 3, 75, 22, 18 ) // CHECK-NEXT: ---- // sparse_tensor.print %2 : tensor @@ -147,11 +147,11 @@ module { // CHECK-NEXT: nse = 17 // CHECK-NEXT: dim = ( 2, 3, 4 ) // CHECK-NEXT: lvl = ( 4, 2, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 17 - // CHECK-NEXT: crd[0] : ( 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3 - // CHECK-NEXT: crd[1] : ( 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1 - // CHECK-NEXT: crd[2] : ( 2, 0, 1, 1, 2, 1, 2, 0, 1, 2, 0, 1, 2, 0, 2, 0, 1 - // CHECK-NEXT: values : ( 66, 77, 61, 11, 61, 53, 22, 3, 100, 13, 10, 3, 18, 63, 43, 46, 75 + // CHECK-NEXT: pos[0] : ( 0, 17 ) + // CHECK-NEXT: crd[0] : ( 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1 ) + // CHECK-NEXT: crd[2] : ( 2, 0, 1, 1, 2, 1, 2, 0, 1, 2, 0, 1, 2, 0, 2, 0, 1 ) + // CHECK-NEXT: values : ( 66, 77, 61, 11, 61, 53, 22, 3, 100, 13, 10, 3, 18, 63, 43, 46, 75 ) // CHECK-NEXT: ---- // sparse_tensor.print %3 : tensor @@ -161,10 +161,10 @@ module { // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 5, 4 ) // CHECK-NEXT: lvl = ( 5, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 2, 3, 4 - // CHECK-NEXT: crd[1] : ( 0, 3, 0, 3, 1, 1 - // CHECK-NEXT: values : ( 6, 5, 4, 3, 2, 11 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 2, 3, 4 ) + // CHECK-NEXT: crd[1] : ( 0, 3, 0, 3, 1, 1 ) + // CHECK-NEXT: values : ( 6, 5, 4, 3, 2, 11 ) // CHECK-NEXT: ---- // sparse_tensor.print %4 : tensor @@ -178,10 +178,10 @@ module { // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 5, 4 ) // CHECK-NEXT: lvl = ( 5, 4 ) - // CHECK-NEXT: pos[0] : ( 0, 6 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 2, 3, 4 - // CHECK-NEXT: crd[1] : ( 0, 3, 0, 3, 1, 1 - // CHECK-NEXT: values : ( 12, 10, 8, 6, 4, 22 + // CHECK-NEXT: pos[0] : ( 0, 6 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 2, 3, 4 ) + // CHECK-NEXT: crd[1] : ( 0, 3, 0, 3, 1, 1 ) + // CHECK-NEXT: values : ( 12, 10, 8, 6, 4, 22 ) // CHECK-NEXT: ---- // sparse_tensor.print %5 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_storage.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_storage.mlir index 2ee189de7906..da87b5cc3c6d 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_storage.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_storage.mlir @@ -111,7 +111,7 @@ module { // CHECK-NEXT: nse = 80 // CHECK-NEXT: dim = ( 10, 8 ) // CHECK-NEXT: lvl = ( 10, 8 ) - // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 7, 8, 0, 0, 0, 0, 9, 0, 0, 10, 0, 0, 0, 11, 12, 0, 13, 14, 0, 0, 0, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0 + // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 7, 8, 0, 0, 0, 0, 9, 0, 0, 10, 0, 0, 0, 11, 12, 0, 13, 14, 0, 0, 0, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor<10x8xf64, #Dense> @@ -124,9 +124,9 @@ module { // CHECK-NEXT: nse = 17 // CHECK-NEXT: dim = ( 10, 8 ) // CHECK-NEXT: lvl = ( 10, 8 ) - // CHECK-NEXT: pos[1] : ( 0, 3, 3, 4, 5, 6, 9, 12, 16, 16, 17 - // CHECK-NEXT: crd[1] : ( 0, 2, 7, 2, 3, 4, 1, 2, 7, 2, 6, 7, 1, 2, 6, 7, 6 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 + // CHECK-NEXT: pos[1] : ( 0, 3, 3, 4, 5, 6, 9, 12, 16, 16, 17 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 7, 2, 3, 4, 1, 2, 7, 2, 6, 7, 1, 2, 6, 7, 6 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 ) // CHECK-NEXT: ---- // sparse_tensor.print %1 : tensor<10x8xf64, #CSR> @@ -138,11 +138,11 @@ module { // CHECK-NEXT: nse = 17 // CHECK-NEXT: dim = ( 10, 8 ) // CHECK-NEXT: lvl = ( 10, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 8 - // CHECK-NEXT: crd[0] : ( 0, 2, 3, 4, 5, 6, 7, 9 - // CHECK-NEXT: pos[1] : ( 0, 3, 4, 5, 6, 9, 12, 16, 17 - // CHECK-NEXT: crd[1] : ( 0, 2, 7, 2, 3, 4, 1, 2, 7, 2, 6, 7, 1, 2, 6, 7, 6 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 + // CHECK-NEXT: pos[0] : ( 0, 8 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 3, 4, 5, 6, 7, 9 ) + // CHECK-NEXT: pos[1] : ( 0, 3, 4, 5, 6, 9, 12, 16, 17 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 7, 2, 3, 4, 1, 2, 7, 2, 6, 7, 1, 2, 6, 7, 6 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 ) // CHECK-NEXT: ---- // sparse_tensor.print %2 : tensor<10x8xf64, #DCSR> @@ -154,9 +154,9 @@ module { // CHECK-NEXT: nse = 17 // CHECK-NEXT: dim = ( 10, 8 ) // CHECK-NEXT: lvl = ( 8, 10 ) - // CHECK-NEXT: pos[1] : ( 0, 1, 3, 8, 9, 10, 10, 13, 17 - // CHECK-NEXT: crd[1] : ( 0, 5, 7, 0, 2, 5, 6, 7, 3, 4, 6, 7, 9, 0, 5, 6, 7 - // CHECK-NEXT: values : ( 1, 7, 13, 2, 4, 8, 10, 14, 5, 6, 11, 15, 17, 3, 9, 12, 16 + // CHECK-NEXT: pos[1] : ( 0, 1, 3, 8, 9, 10, 10, 13, 17 ) + // CHECK-NEXT: crd[1] : ( 0, 5, 7, 0, 2, 5, 6, 7, 3, 4, 6, 7, 9, 0, 5, 6, 7 ) + // CHECK-NEXT: values : ( 1, 7, 13, 2, 4, 8, 10, 14, 5, 6, 11, 15, 17, 3, 9, 12, 16 ) // CHECK-NEXT: ---- // sparse_tensor.print %3 : tensor<10x8xf64, #CSC> @@ -168,11 +168,11 @@ module { // CHECK-NEXT: nse = 17 // CHECK-NEXT: dim = ( 10, 8 ) // CHECK-NEXT: lvl = ( 8, 10 ) - // CHECK-NEXT: pos[0] : ( 0, 7 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 6, 7 - // CHECK-NEXT: pos[1] : ( 0, 1, 3, 8, 9, 10, 13, 17 - // CHECK-NEXT: crd[1] : ( 0, 5, 7, 0, 2, 5, 6, 7, 3, 4, 6, 7, 9, 0, 5, 6, 7 - // CHECK-NEXT: values : ( 1, 7, 13, 2, 4, 8, 10, 14, 5, 6, 11, 15, 17, 3, 9, 12, 16 + // CHECK-NEXT: pos[0] : ( 0, 7 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 6, 7 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 3, 8, 9, 10, 13, 17 ) + // CHECK-NEXT: crd[1] : ( 0, 5, 7, 0, 2, 5, 6, 7, 3, 4, 6, 7, 9, 0, 5, 6, 7 ) + // CHECK-NEXT: values : ( 1, 7, 13, 2, 4, 8, 10, 14, 5, 6, 11, 15, 17, 3, 9, 12, 16 ) // CHECK-NEXT: ---- // sparse_tensor.print %4 : tensor<10x8xf64, #DCSC> @@ -184,9 +184,9 @@ module { // CHECK-NEXT: nse = 64 // CHECK-NEXT: dim = ( 10, 8 ) // CHECK-NEXT: lvl = ( 10, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 8 - // CHECK-NEXT: crd[0] : ( 0, 2, 3, 4, 5, 6, 7, 9 - // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 3, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 7, 8, 0, 0, 0, 0, 9, 0, 0, 10, 0, 0, 0, 11, 12, 0, 13, 14, 0, 0, 0, 15, 16, 0, 0, 0, 0, 0, 0, 17, 0 + // CHECK-NEXT: pos[0] : ( 0, 8 ) + // CHECK-NEXT: crd[0] : ( 0, 2, 3, 4, 5, 6, 7, 9 ) + // CHECK-NEXT: values : ( 1, 0, 2, 0, 0, 0, 0, 3, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 7, 8, 0, 0, 0, 0, 9, 0, 0, 10, 0, 0, 0, 11, 12, 0, 13, 14, 0, 0, 0, 15, 16, 0, 0, 0, 0, 0, 0, 17, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %x : tensor<10x8xf64, #BlockRow> @@ -198,9 +198,9 @@ module { // CHECK-NEXT: nse = 70 // CHECK-NEXT: dim = ( 10, 8 ) // CHECK-NEXT: lvl = ( 8, 10 ) - // CHECK-NEXT: pos[0] : ( 0, 7 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 6, 7 - // CHECK-NEXT: values : ( 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 13, 0, 0, 2, 0, 4, 0, 0, 8, 10, 14, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 15, 0, 17, 3, 0, 0, 0, 0, 9, 12, 16, 0, 0 + // CHECK-NEXT: pos[0] : ( 0, 7 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 6, 7 ) + // CHECK-NEXT: values : ( 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 13, 0, 0, 2, 0, 4, 0, 0, 8, 10, 14, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 15, 0, 17, 3, 0, 0, 0, 0, 9, 12, 16, 0, 0 ) // CHECK-NEXT: ---- // sparse_tensor.print %y : tensor<10x8xf64, #BlockCol> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tanh.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tanh.mlir index 29bc744c9920..748fffc1e637 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tanh.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tanh.mlir @@ -77,9 +77,9 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 9 - // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 - // CHECK-NEXT: values : ({{ -0.761[0-9]*, 0.761[0-9]*, 0.96[0-9]*, 0.99[0-9]*, 0.99[0-9]*, 0.99[0-9]*, 0.99[0-9]*, 0.99[0-9]*, 1}} + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ({{ -0.761[0-9]*, 0.761[0-9]*, 0.96[0-9]*, 0.99[0-9]*, 0.99[0-9]*, 0.99[0-9]*, 0.99[0-9]*, 0.99[0-9]*, 1}} ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_mul.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_mul.mlir index 67155201c584..fe2f2690e860 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_mul.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_mul.mlir @@ -110,13 +110,13 @@ module { // CHECK-NEXT: nse = 4 // CHECK-NEXT: dim = ( 3, 3, 5 ) // CHECK-NEXT: lvl = ( 3, 3, 5 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 2 - // CHECK-NEXT: pos[1] : ( 0, 1, 3 - // CHECK-NEXT: crd[1] : ( 2, 0, 2 - // CHECK-NEXT: pos[2] : ( 0, 2, 3, 4 - // CHECK-NEXT: crd[2] : ( 0, 2, 0, 2 - // CHECK-NEXT: values : ( 2.4, 3.5, 2, 8 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 1, 3 ) + // CHECK-NEXT: crd[1] : ( 2, 0, 2 ) + // CHECK-NEXT: pos[2] : ( 0, 2, 3, 4 ) + // CHECK-NEXT: crd[2] : ( 0, 2, 0, 2 ) + // CHECK-NEXT: values : ( 2.4, 3.5, 2, 8 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_ops.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_ops.mlir index 356808ebee3f..a46c3a8d5ef6 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_ops.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_ops.mlir @@ -97,23 +97,23 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 3, 4, 8 ) // CHECK-NEXT: lvl = ( 3, 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 2 - // CHECK-NEXT: pos[1] : ( 0, 2, 3 - // CHECK-NEXT: crd[1] : ( 0, 3, 2 - // CHECK-NEXT: pos[2] : ( 0, 1, 2, 5 - // CHECK-NEXT: crd[2] : ( 0, 7, 1, 2, 7 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 3, 2 ) + // CHECK-NEXT: pos[2] : ( 0, 1, 2, 5 ) + // CHECK-NEXT: crd[2] : ( 0, 7, 1, 2, 7 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 24 // CHECK-NEXT: dim = ( 3, 4, 8 ) // CHECK-NEXT: lvl = ( 3, 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 2 - // CHECK-NEXT: crd[0] : ( 0, 2 - // CHECK-NEXT: pos[1] : ( 0, 2, 3 - // CHECK-NEXT: crd[1] : ( 0, 3, 2 - // CHECK-NEXT: values : ( 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 6, 8, 0, 0, 0, 0, 10 + // CHECK-NEXT: pos[0] : ( 0, 2 ) + // CHECK-NEXT: crd[0] : ( 0, 2 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 3, 2 ) + // CHECK-NEXT: values : ( 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 6, 8, 0, 0, 0, 0, 10 ) // CHECK-NEXT: ---- // sparse_tensor.print %st : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose.mlir index 549c2082fcb3..434cc9509464 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose.mlir @@ -119,21 +119,21 @@ module { // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 4, 3 ) // CHECK-NEXT: lvl = ( 4, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 4, 6 - // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, 0, 2 - // CHECK-NEXT: values : ( 1.1, 3.1, 1.2, 3.3, 1.4, 3.4 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 4, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, 0, 2 ) + // CHECK-NEXT: values : ( 1.1, 3.1, 1.2, 3.3, 1.4, 3.4 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 6 // CHECK-NEXT: dim = ( 4, 3 ) // CHECK-NEXT: lvl = ( 4, 3 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 4, 6 - // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, 0, 2 - // CHECK-NEXT: values : ( 1.1, 3.1, 1.2, 3.3, 1.4, 3.4 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 4, 6 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, 0, 2 ) + // CHECK-NEXT: values : ( 1.1, 3.1, 1.2, 3.3, 1.4, 3.4 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor<4x3xf64, #DCSR> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose_coo.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose_coo.mlir index cc6f6a068746..3b7760e5052c 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose_coo.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose_coo.mlir @@ -83,19 +83,19 @@ module { // CHECK-NEXT: nse = 50 // CHECK-NEXT: dim = ( 10, 5 ) // CHECK-NEXT: lvl = ( 10, 5 ) - // CHECK-NEXT: pos[0] : ( 0, 50 - // CHECK-NEXT: crd[0] : ( 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4 - // CHECK-NEXT: values : ( 10, 20, 30, 40, 50, 11, 21, 31, 41, 51, 12, 22, 32, 42, 52, 13, 23, 33, 43, 53, 14, 24, 34, 44, 54, 15, 25, 35, 45, 55, 16, 26, 36, 46, 56, 17, 27, 37, 47, 57, 18, 28, 38, 48, 58, 19, 29, 39, 49, 59 + // CHECK-NEXT: pos[0] : ( 0, 50 ) + // CHECK-NEXT: crd[0] : ( 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4 ) + // CHECK-NEXT: values : ( 10, 20, 30, 40, 50, 11, 21, 31, 41, 51, 12, 22, 32, 42, 52, 13, 23, 33, 43, 53, 14, 24, 34, 44, 54, 15, 25, 35, 45, 55, 16, 26, 36, 46, 56, 17, 27, 37, 47, 57, 18, 28, 38, 48, 58, 19, 29, 39, 49, 59 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 50 // CHECK-NEXT: dim = ( 5, 10 ) // CHECK-NEXT: lvl = ( 5, 10 ) - // CHECK-NEXT: pos[0] : ( 0, 50 - // CHECK-NEXT: crd[0] : ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 - // CHECK-NEXT: values : ( 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59 + // CHECK-NEXT: pos[0] : ( 0, 50 ) + // CHECK-NEXT: crd[0] : ( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ) + // CHECK-NEXT: values : ( 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59 ) // CHECK-NEXT: ---- // sparse_tensor.print %SA : tensor<10x5xf32, #SortedCOO> diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_unary.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_unary.mlir index 3da1e35818cf..acb7a99a3418 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_unary.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_unary.mlir @@ -247,53 +247,53 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 9 - // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9 + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 23 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 23 - // CHECK-NEXT: crd[0] : ( 1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 18, 19, 22, 23, 24, 25, 26, 27, 30 - // CHECK-NEXT: values : ( 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 + // CHECK-NEXT: pos[0] : ( 0, 23 ) + // CHECK-NEXT: crd[0] : ( 1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 18, 19, 22, 23, 24, 25, 26, 27, 30 ) + // CHECK-NEXT: values : ( 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 32 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 - // CHECK-NEXT: values : ( -1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1, -3, 1, 1, 1, 1, 1, -4, 1, 1, -5, -6, 1, 1, 1, 1, 1, 1, -7, -8, 1, -9 + // CHECK-NEXT: pos[0] : ( 0, 32 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ) + // CHECK-NEXT: values : ( -1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1, -3, 1, 1, 1, 1, 1, -4, 1, 1, -5, -6, 1, 1, 1, 1, 1, 1, -7, -8, 1, -9 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 9 - // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 - // CHECK-NEXT: values : ( 0, 6, 33, 68, 100, 126, 196, 232, 279 + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 0, 6, 33, 68, 100, 126, 196, 232, 279 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 - // CHECK-NEXT: crd[1] : ( 0, 1, 7, 2, 4, 7, 0, 2, 3 - // CHECK-NEXT: values : ( 3, 3, 3, 4, 5, 6, 7, 7, 7 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 7, 2, 4, 7, 0, 2, 3 ) + // CHECK-NEXT: values : ( 3, 3, 3, 4, 5, 6, 7, 7, 7 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 4, 8 ) // CHECK-NEXT: lvl = ( 4, 8 ) - // CHECK-NEXT: pos[0] : ( 0, 4 - // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 - // CHECK-NEXT: crd[1] : ( 0, 1, 7, 2, 4, 7, 0, 2, 3 - // CHECK-NEXT: values : ( 99, 99, 99, 99, 5, 6, 99, 99, 99 + // CHECK-NEXT: pos[0] : ( 0, 4 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 6, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 7, 2, 4, 7, 0, 2, 3 ) + // CHECK-NEXT: values : ( 99, 99, 99, 99, 5, 6, 99, 99, 99 ) // CHECK-NEXT: ---- // CHECK-NEXT: ( 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0 ) // diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_vector_ops.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_vector_ops.mlir index 553323331641..10ccf47c3408 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_vector_ops.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_vector_ops.mlir @@ -209,55 +209,55 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 9 - // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 - // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9 + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 1, 2, 3, 4, 5, 6, 7, 8, 9 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 10 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 10 - // CHECK-NEXT: crd[0] : ( 1, 3, 4, 10, 16, 18, 21, 28, 29, 31 - // CHECK-NEXT: values : ( 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 + // CHECK-NEXT: pos[0] : ( 0, 10 ) + // CHECK-NEXT: crd[0] : ( 1, 3, 4, 10, 16, 18, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 9 - // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 - // CHECK-NEXT: values : ( 2, 4, 6, 8, 10, 12, 14, 16, 18 + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 2, 4, 6, 8, 10, 12, 14, 16, 18 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 9 - // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 - // CHECK-NEXT: values : ( 2, 4, 6, 8, 10, 12, 14, 16, 18 + // CHECK-NEXT: pos[0] : ( 0, 9 ) + // CHECK-NEXT: crd[0] : ( 0, 3, 11, 17, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 2, 4, 6, 8, 10, 12, 14, 16, 18 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 14 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 14 - // CHECK-NEXT: crd[0] : ( 0, 1, 3, 4, 10, 11, 16, 17, 18, 20, 21, 28, 29, 31 - // CHECK-NEXT: values : ( 2, 11, 16, 13, 14, 6, 15, 8, 16, 10, 29, 32, 35, 38 + // CHECK-NEXT: pos[0] : ( 0, 14 ) + // CHECK-NEXT: crd[0] : ( 0, 1, 3, 4, 10, 11, 16, 17, 18, 20, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 2, 11, 16, 13, 14, 6, 15, 8, 16, 10, 29, 32, 35, 38 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: pos[0] : ( 0, 5 - // CHECK-NEXT: crd[0] : ( 3, 21, 28, 29, 31 - // CHECK-NEXT: values : ( 48, 204, 252, 304, 360 + // CHECK-NEXT: pos[0] : ( 0, 5 ) + // CHECK-NEXT: crd[0] : ( 3, 21, 28, 29, 31 ) + // CHECK-NEXT: values : ( 48, 204, 252, 304, 360 ) // CHECK-NEXT: ---- // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 32 // CHECK-NEXT: dim = ( 32 ) // CHECK-NEXT: lvl = ( 32 ) - // CHECK-NEXT: values : ( 0, 0, 0, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 204, 0, 0, 0, 0, 0, 0, 252, 304, 0, 360 + // CHECK-NEXT: values : ( 0, 0, 0, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 204, 0, 0, 0, 0, 0, 0, 252, 304, 0, 360 ) // CHECK-NEXT: ---- // CHECK-NEXT: 1169.1 // diff --git a/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-gemm-lib.mlir b/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-gemm-lib.mlir index 9413119509c6..bd71409892f4 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-gemm-lib.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-gemm-lib.mlir @@ -68,9 +68,9 @@ module { // CHECK-NEXT: nse = 20 // CHECK-NEXT: dim = ( 8, 8 ) // CHECK-NEXT: lvl = ( 8, 8 ) - // CHECK-NEXT: pos[1] : ( 0, 5, 5, 6, 7, 8, 12, 16, 20, ) - // CHECK-NEXT: crd[1] : ( 0, 1, 2, 6, 7, 2, 3, 4, 1, 2, 6, 7, 1, 2, 6, 7, 1, 2, 6, 7, ) - // CHECK-NEXT: values : ( 1, 39, 52, 45, 51, 16, 25, 36, 117, 158, 135, 144, 156, 318, 301, 324, 208, 430, 405, 436, ) + // CHECK-NEXT: pos[1] : ( 0, 5, 5, 6, 7, 8, 12, 16, 20 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 2, 6, 7, 2, 3, 4, 1, 2, 6, 7, 1, 2, 6, 7, 1, 2, 6, 7 ) + // CHECK-NEXT: values : ( 1, 39, 52, 45, 51, 16, 25, 36, 117, 158, 135, 144, 156, 318, 301, 324, 208, 430, 405, 436 ) // CHECK-NEXT: ---- sparse_tensor.print %Ccsr : tensor<8x8xf32, #CSR> diff --git a/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-sampled-matmul-lib.mlir b/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-sampled-matmul-lib.mlir index 3b3d074f7e2a..64f289626c07 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-sampled-matmul-lib.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-sampled-matmul-lib.mlir @@ -117,9 +117,9 @@ module { // CHECK-NEXT: nse = 9 // CHECK-NEXT: dim = ( 5, 5 ) // CHECK-NEXT: lvl = ( 5, 5 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 4, 5, 7, 9, ) - // CHECK-NEXT: crd[1] : ( 0, 3, 1, 4, 2, 0, 3, 1, 4, ) - // CHECK-NEXT: values : ( 11, 41.4, 42, 102.5, 93, 44.1, 164, 105.2, 255, ) + // CHECK-NEXT: pos[1] : ( 0, 2, 4, 5, 7, 9 ) + // CHECK-NEXT: crd[1] : ( 0, 3, 1, 4, 2, 0, 3, 1, 4 ) + // CHECK-NEXT: values : ( 11, 41.4, 42, 102.5, 93, 44.1, 164, 105.2, 255 ) // CHECK-NEXT: ---- sparse_tensor.print %0 : tensor @@ -145,9 +145,9 @@ module { // CHECK-NEXT: nse = 5 // CHECK-NEXT: dim = ( 8, 8 ) // CHECK-NEXT: lvl = ( 8, 8 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 3, 3, 4, 4, 4, 4, 5, ) - // CHECK-NEXT: crd[1] : ( 0, 1, 0, 4, 7, ) - // CHECK-NEXT: values : ( 17, 18, 19, 20, 21, ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3, 3, 4, 4, 4, 4, 5 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 0, 4, 7 ) + // CHECK-NEXT: values : ( 17, 18, 19, 20, 21 ) // CHECK-NEXT: ---- // sparse_tensor.print %1 : tensor diff --git a/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-sddmm-lib.mlir b/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-sddmm-lib.mlir index 18f59f59a9f0..4b503ae0d110 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-sddmm-lib.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-sddmm-lib.mlir @@ -170,18 +170,18 @@ module { // CHECK-NEXT: nse = 8 // CHECK-NEXT: dim = ( 4, 6 ) // CHECK-NEXT: lvl = ( 4, 6 ) - // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7, 8, ) - // CHECK-NEXT: crd[1] : ( 0, 1, 4, 1, 5, 2, 3, 2, ) - // CHECK-NEXT: values : ( 5, 10, 24, 19, 53, 42, 55, 56, ) + // CHECK-NEXT: pos[1] : ( 0, 3, 5, 7, 8 ) + // CHECK-NEXT: crd[1] : ( 0, 1, 4, 1, 5, 2, 3, 2 ) + // CHECK-NEXT: values : ( 5, 10, 24, 19, 53, 42, 55, 56 ) // CHECK-NEXT: ---- // // CHECK: ---- Sparse Tensor ---- // CHECK-NEXT: nse = 12 // CHECK-NEXT: dim = ( 4, 6 ) // CHECK-NEXT: lvl = ( 2, 3, 2, 2 ) - // CHECK-NEXT: pos[1] : ( 0, 2, 3, ) - // CHECK-NEXT: crd[1] : ( 0, 2, 1, ) - // CHECK-NEXT: values : ( 5, 10, 8, 19, 24, 24, 40, 53, 42, 55, 56, 64, ) + // CHECK-NEXT: pos[1] : ( 0, 2, 3 ) + // CHECK-NEXT: crd[1] : ( 0, 2, 1 ) + // CHECK-NEXT: values : ( 5, 10, 8, 19, 24, 24, 40, 53, 42, 55, 56, 64 ) // CHECK-NEXT: ---- // sparse_tensor.print %0 : tensor -- GitLab From 9e1a49cba71416d7e425eb420e86e1120199f4de Mon Sep 17 00:00:00 2001 From: David Green Date: Thu, 9 May 2024 17:15:35 +0100 Subject: [PATCH 163/328] [AArch64][ARM] Add tests for frem power2 lowering. NFC --- llvm/test/CodeGen/AArch64/frem-power2.ll | 479 +++++++++++++++++++++++ llvm/test/CodeGen/ARM/frem-power2.ll | 50 +++ 2 files changed, 529 insertions(+) create mode 100644 llvm/test/CodeGen/AArch64/frem-power2.ll create mode 100644 llvm/test/CodeGen/ARM/frem-power2.ll diff --git a/llvm/test/CodeGen/AArch64/frem-power2.ll b/llvm/test/CodeGen/AArch64/frem-power2.ll new file mode 100644 index 000000000000..5d627fcd6b65 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/frem-power2.ll @@ -0,0 +1,479 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD +; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI + +define float @frem2(float %x) { +; CHECK-LABEL: frem2: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fmov s1, #2.00000000 +; CHECK-NEXT: b fmodf +entry: + %fmod = frem float %x, 2.0 + ret float %fmod +} + +define float @frem2_nsz(float %x) { +; CHECK-LABEL: frem2_nsz: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fmov s1, #2.00000000 +; CHECK-NEXT: b fmodf +entry: + %fmod = frem nsz float %x, 2.0 + ret float %fmod +} + +define float @frem2_fast(float %x) { +; CHECK-LABEL: frem2_fast: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fmov s1, #2.00000000 +; CHECK-NEXT: b fmodf +entry: + %fmod = frem fast float %x, 2.0 + ret float %fmod +} + +define float @frem2_abs(float %x) { +; CHECK-LABEL: frem2_abs: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fabs s0, s0 +; CHECK-NEXT: fmov s1, #2.00000000 +; CHECK-NEXT: b fmodf +entry: + %a = tail call float @llvm.fabs.f32(float %x) + %fmod = frem float %a, 2.0 + ret float %fmod +} + +define half @hrem2_nsz(half %x) { +; CHECK-SD-LABEL: hrem2_nsz: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: .cfi_offset w30, -16 +; CHECK-SD-NEXT: fcvt s0, h0 +; CHECK-SD-NEXT: fmov s1, #2.00000000 +; CHECK-SD-NEXT: bl fmodf +; CHECK-SD-NEXT: fcvt h0, s0 +; CHECK-SD-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: hrem2_nsz: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: .cfi_offset w30, -16 +; CHECK-GI-NEXT: fmov h1, #2.00000000 +; CHECK-GI-NEXT: fcvt s0, h0 +; CHECK-GI-NEXT: fcvt s1, h1 +; CHECK-GI-NEXT: bl fmodf +; CHECK-GI-NEXT: fcvt h0, s0 +; CHECK-GI-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-GI-NEXT: ret +entry: + %fmod = frem nsz half %x, 2.0 + ret half %fmod +} + +define double @drem2_nsz(double %x) { +; CHECK-LABEL: drem2_nsz: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fmov d1, #2.00000000 +; CHECK-NEXT: b fmod +entry: + %fmod = frem nsz double %x, 2.0 + ret double %fmod +} + +define float @frem3_nsz(float %x) { +; CHECK-LABEL: frem3_nsz: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fmov s1, #3.00000000 +; CHECK-NEXT: b fmodf +entry: + %fmod = frem nsz float %x, 3.0 + ret float %fmod +} + +define float @frem05_nsz(float %x) { +; CHECK-LABEL: frem05_nsz: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fmov s1, #0.50000000 +; CHECK-NEXT: b fmodf +entry: + %fmod = frem nsz float %x, 0.5 + ret float %fmod +} + +define float @frem1_nsz(float %x) { +; CHECK-LABEL: frem1_nsz: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fmov s1, #1.00000000 +; CHECK-NEXT: b fmodf +entry: + %fmod = frem nsz float %x, 1.0 + ret float %fmod +} + +define float @frem0_nsz(float %x) { +; CHECK-LABEL: frem0_nsz: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: movi d1, #0000000000000000 +; CHECK-NEXT: b fmodf +entry: + %fmod = frem nsz float %x, 0.0 + ret float %fmod +} + +define float @fremm2_nsz(float %x) { +; CHECK-LABEL: fremm2_nsz: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fmov s1, #-2.00000000 +; CHECK-NEXT: b fmodf +entry: + %fmod = frem nsz float %x, -2.0 + ret float %fmod +} + +define float @frem4_abs(float %x) { +; CHECK-LABEL: frem4_abs: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fabs s0, s0 +; CHECK-NEXT: fmov s1, #4.00000000 +; CHECK-NEXT: b fmodf +entry: + %a = tail call float @llvm.fabs.f32(float %x) + %fmod = frem float %a, 4.0 + ret float %fmod +} + +define float @frem16_abs(float %x) { +; CHECK-LABEL: frem16_abs: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fabs s0, s0 +; CHECK-NEXT: fmov s1, #16.00000000 +; CHECK-NEXT: b fmodf +entry: + %a = tail call float @llvm.fabs.f32(float %x) + %fmod = frem float %a, 16.0 + ret float %fmod +} + +define float @frem4294967296_abs(float %x) { +; CHECK-LABEL: frem4294967296_abs: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fabs s0, s0 +; CHECK-NEXT: mov w8, #1333788672 // =0x4f800000 +; CHECK-NEXT: fmov s1, w8 +; CHECK-NEXT: b fmodf +entry: + %a = tail call float @llvm.fabs.f32(float %x) + %fmod = frem float %a, 4294967296.0 + ret float %fmod +} + +define float @frem1152921504606846976_abs(float %x) { +; CHECK-LABEL: frem1152921504606846976_abs: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fabs s0, s0 +; CHECK-NEXT: mov w8, #1568669696 // =0x5d800000 +; CHECK-NEXT: fmov s1, w8 +; CHECK-NEXT: b fmodf +entry: + %a = tail call float @llvm.fabs.f32(float %x) + %fmod = frem float %a, 1152921504606846976.0 + ret float %fmod +} + +define float @frem4611686018427387904_abs(float %x) { +; CHECK-LABEL: frem4611686018427387904_abs: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fabs s0, s0 +; CHECK-NEXT: mov w8, #1585446912 // =0x5e800000 +; CHECK-NEXT: fmov s1, w8 +; CHECK-NEXT: b fmodf +entry: + %a = tail call float @llvm.fabs.f32(float %x) + %fmod = frem float %a, 4611686018427387904.0 + ret float %fmod +} + +define float @frem9223372036854775808_abs(float %x) { +; CHECK-LABEL: frem9223372036854775808_abs: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fabs s0, s0 +; CHECK-NEXT: movi v1.2s, #95, lsl #24 +; CHECK-NEXT: b fmodf +entry: + %a = tail call float @llvm.fabs.f32(float %x) + %fmod = frem float %a, 9223372036854775808.0 + ret float %fmod +} + +define <4 x float> @frem2_nsz_vec(<4 x float> %x) { +; CHECK-SD-LABEL: frem2_nsz_vec: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #48 +; CHECK-SD-NEXT: str x30, [sp, #32] // 8-byte Folded Spill +; CHECK-SD-NEXT: .cfi_def_cfa_offset 48 +; CHECK-SD-NEXT: .cfi_offset w30, -16 +; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Folded Spill +; CHECK-SD-NEXT: mov s0, v0.s[1] +; CHECK-SD-NEXT: fmov s1, #2.00000000 +; CHECK-SD-NEXT: bl fmodf +; CHECK-SD-NEXT: fmov s1, #2.00000000 +; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill +; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload +; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-SD-NEXT: bl fmodf +; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload +; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-SD-NEXT: mov v0.s[1], v1.s[0] +; CHECK-SD-NEXT: fmov s1, #2.00000000 +; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill +; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload +; CHECK-SD-NEXT: mov s0, v0.s[2] +; CHECK-SD-NEXT: bl fmodf +; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload +; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-SD-NEXT: mov v1.s[2], v0.s[0] +; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload +; CHECK-SD-NEXT: mov s0, v0.s[3] +; CHECK-SD-NEXT: str q1, [sp] // 16-byte Folded Spill +; CHECK-SD-NEXT: fmov s1, #2.00000000 +; CHECK-SD-NEXT: bl fmodf +; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload +; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-SD-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload +; CHECK-SD-NEXT: mov v1.s[3], v0.s[0] +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: add sp, sp, #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem2_nsz_vec: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #80 +; CHECK-GI-NEXT: str d10, [sp, #48] // 8-byte Folded Spill +; CHECK-GI-NEXT: stp d9, d8, [sp, #56] // 16-byte Folded Spill +; CHECK-GI-NEXT: str x30, [sp, #72] // 8-byte Folded Spill +; CHECK-GI-NEXT: .cfi_def_cfa_offset 80 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset b8, -16 +; CHECK-GI-NEXT: .cfi_offset b9, -24 +; CHECK-GI-NEXT: .cfi_offset b10, -32 +; CHECK-GI-NEXT: fmov s1, #2.00000000 +; CHECK-GI-NEXT: mov s8, v0.s[1] +; CHECK-GI-NEXT: mov s9, v0.s[2] +; CHECK-GI-NEXT: mov s10, v0.s[3] +; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-GI-NEXT: bl fmodf +; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Folded Spill +; CHECK-GI-NEXT: fmov s1, #2.00000000 +; CHECK-GI-NEXT: fmov s0, s8 +; CHECK-GI-NEXT: bl fmodf +; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Folded Spill +; CHECK-GI-NEXT: fmov s1, #2.00000000 +; CHECK-GI-NEXT: fmov s0, s9 +; CHECK-GI-NEXT: bl fmodf +; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-GI-NEXT: str q0, [sp] // 16-byte Folded Spill +; CHECK-GI-NEXT: fmov s1, #2.00000000 +; CHECK-GI-NEXT: fmov s0, s10 +; CHECK-GI-NEXT: bl fmodf +; CHECK-GI-NEXT: ldp q2, q1, [sp, #16] // 32-byte Folded Reload +; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-GI-NEXT: ldr x30, [sp, #72] // 8-byte Folded Reload +; CHECK-GI-NEXT: ldp d9, d8, [sp, #56] // 16-byte Folded Reload +; CHECK-GI-NEXT: ldr d10, [sp, #48] // 8-byte Folded Reload +; CHECK-GI-NEXT: mov v1.s[1], v2.s[0] +; CHECK-GI-NEXT: ldr q2, [sp] // 16-byte Folded Reload +; CHECK-GI-NEXT: mov v1.s[2], v2.s[0] +; CHECK-GI-NEXT: mov v1.s[3], v0.s[0] +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: add sp, sp, #80 +; CHECK-GI-NEXT: ret +entry: + %fmod = frem nsz <4 x float> %x, + ret <4 x float> %fmod +} + +define <4 x float> @frem1152921504606846976_absv(<4 x float> %x) { +; CHECK-SD-LABEL: frem1152921504606846976_absv: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #48 +; CHECK-SD-NEXT: str d8, [sp, #32] // 8-byte Folded Spill +; CHECK-SD-NEXT: str x30, [sp, #40] // 8-byte Folded Spill +; CHECK-SD-NEXT: .cfi_def_cfa_offset 48 +; CHECK-SD-NEXT: .cfi_offset w30, -8 +; CHECK-SD-NEXT: .cfi_offset b8, -16 +; CHECK-SD-NEXT: fabs v0.4s, v0.4s +; CHECK-SD-NEXT: mov w8, #1568669696 // =0x5d800000 +; CHECK-SD-NEXT: fmov s8, w8 +; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Folded Spill +; CHECK-SD-NEXT: mov s0, v0.s[1] +; CHECK-SD-NEXT: fmov s1, s8 +; CHECK-SD-NEXT: bl fmodf +; CHECK-SD-NEXT: fmov s1, s8 +; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill +; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload +; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-SD-NEXT: bl fmodf +; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload +; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-SD-NEXT: mov v0.s[1], v1.s[0] +; CHECK-SD-NEXT: fmov s1, s8 +; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill +; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload +; CHECK-SD-NEXT: mov s0, v0.s[2] +; CHECK-SD-NEXT: bl fmodf +; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload +; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-SD-NEXT: mov v1.s[2], v0.s[0] +; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload +; CHECK-SD-NEXT: mov s0, v0.s[3] +; CHECK-SD-NEXT: str q1, [sp] // 16-byte Folded Spill +; CHECK-SD-NEXT: fmov s1, s8 +; CHECK-SD-NEXT: bl fmodf +; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload +; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-SD-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload +; CHECK-SD-NEXT: ldr d8, [sp, #32] // 8-byte Folded Reload +; CHECK-SD-NEXT: mov v1.s[3], v0.s[0] +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: add sp, sp, #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem1152921504606846976_absv: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #96 +; CHECK-GI-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill +; CHECK-GI-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill +; CHECK-GI-NEXT: str x30, [sp, #80] // 8-byte Folded Spill +; CHECK-GI-NEXT: .cfi_def_cfa_offset 96 +; CHECK-GI-NEXT: .cfi_offset w30, -16 +; CHECK-GI-NEXT: .cfi_offset b8, -24 +; CHECK-GI-NEXT: .cfi_offset b9, -32 +; CHECK-GI-NEXT: .cfi_offset b10, -40 +; CHECK-GI-NEXT: .cfi_offset b11, -48 +; CHECK-GI-NEXT: mov w8, #1568669696 // =0x5d800000 +; CHECK-GI-NEXT: fabs v0.4s, v0.4s +; CHECK-GI-NEXT: fmov s11, w8 +; CHECK-GI-NEXT: fmov s1, s11 +; CHECK-GI-NEXT: mov s8, v0.s[1] +; CHECK-GI-NEXT: mov s9, v0.s[2] +; CHECK-GI-NEXT: mov s10, v0.s[3] +; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-GI-NEXT: bl fmodf +; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Folded Spill +; CHECK-GI-NEXT: fmov s1, s11 +; CHECK-GI-NEXT: fmov s0, s8 +; CHECK-GI-NEXT: bl fmodf +; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Folded Spill +; CHECK-GI-NEXT: fmov s1, s11 +; CHECK-GI-NEXT: fmov s0, s9 +; CHECK-GI-NEXT: bl fmodf +; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-GI-NEXT: str q0, [sp] // 16-byte Folded Spill +; CHECK-GI-NEXT: fmov s1, s11 +; CHECK-GI-NEXT: fmov s0, s10 +; CHECK-GI-NEXT: bl fmodf +; CHECK-GI-NEXT: ldp q2, q1, [sp, #16] // 32-byte Folded Reload +; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-GI-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload +; CHECK-GI-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload +; CHECK-GI-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload +; CHECK-GI-NEXT: mov v1.s[1], v2.s[0] +; CHECK-GI-NEXT: ldr q2, [sp] // 16-byte Folded Reload +; CHECK-GI-NEXT: mov v1.s[2], v2.s[0] +; CHECK-GI-NEXT: mov v1.s[3], v0.s[0] +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: add sp, sp, #96 +; CHECK-GI-NEXT: ret +entry: + %a = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %x) + %fmod = frem <4 x float> %a, + ret <4 x float> %fmod +} + +define float @frem2_nsz_sitofp(float %x, i32 %sa) { +; CHECK-LABEL: frem2_nsz_sitofp: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: mov w8, #1 // =0x1 +; CHECK-NEXT: lsl w8, w8, w0 +; CHECK-NEXT: scvtf s1, w8 +; CHECK-NEXT: b fmodf +entry: + %s = shl i32 1, %sa + %y = sitofp i32 %s to float + %fmod = frem nsz float %x, %y + ret float %fmod +} + +define float @frem2_nsz_uitofp(float %x, i32 %sa) { +; CHECK-LABEL: frem2_nsz_uitofp: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: mov w8, #1 // =0x1 +; CHECK-NEXT: lsl w8, w8, w0 +; CHECK-NEXT: ucvtf s1, w8 +; CHECK-NEXT: b fmodf +entry: + %s = shl i32 1, %sa + %y = uitofp i32 %s to float + %fmod = frem nsz float %x, %y + ret float %fmod +} + +define float @frem2_const_sitofp(float %x, i32 %sa) { +; CHECK-SD-LABEL: frem2_const_sitofp: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: mov w8, #1 // =0x1 +; CHECK-SD-NEXT: fmov s0, #12.50000000 +; CHECK-SD-NEXT: lsl w8, w8, w0 +; CHECK-SD-NEXT: scvtf s1, w8 +; CHECK-SD-NEXT: b fmodf +; +; CHECK-GI-LABEL: frem2_const_sitofp: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov w8, #1 // =0x1 +; CHECK-GI-NEXT: and w9, w0, #0x1f +; CHECK-GI-NEXT: fmov s0, #12.50000000 +; CHECK-GI-NEXT: lsl w8, w8, w9 +; CHECK-GI-NEXT: scvtf s1, w8 +; CHECK-GI-NEXT: b fmodf +entry: + %sa2 = and i32 %sa, 31 + %s = shl i32 1, %sa2 + %y = sitofp i32 %s to float + %fmod = frem float 12.50, %y + ret float %fmod +} + +define float @frem2_constneg_sitofp(float %x, i32 %sa) { +; CHECK-SD-LABEL: frem2_constneg_sitofp: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: mov w8, #1 // =0x1 +; CHECK-SD-NEXT: fmov s0, #-12.50000000 +; CHECK-SD-NEXT: lsl w8, w8, w0 +; CHECK-SD-NEXT: scvtf s1, w8 +; CHECK-SD-NEXT: b fmodf +; +; CHECK-GI-LABEL: frem2_constneg_sitofp: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov w8, #1 // =0x1 +; CHECK-GI-NEXT: and w9, w0, #0x1f +; CHECK-GI-NEXT: fmov s0, #-12.50000000 +; CHECK-GI-NEXT: lsl w8, w8, w9 +; CHECK-GI-NEXT: scvtf s1, w8 +; CHECK-GI-NEXT: b fmodf +entry: + %sa2 = and i32 %sa, 31 + %s = shl i32 1, %sa2 + %y = sitofp i32 %s to float + %fmod = frem float -12.50, %y + ret float %fmod +} diff --git a/llvm/test/CodeGen/ARM/frem-power2.ll b/llvm/test/CodeGen/ARM/frem-power2.ll new file mode 100644 index 000000000000..8052c8c35bcf --- /dev/null +++ b/llvm/test/CodeGen/ARM/frem-power2.ll @@ -0,0 +1,50 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s --check-prefix=CHECK-SOFT +; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+fp-armv8 %s -o - | FileCheck %s --check-prefix=CHECK-FP +; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+fp-armv8,+slowfpvfmx %s -o - | FileCheck %s --check-prefix=CHECK-M33 + +define float @frem4(float %x) { +; CHECK-SOFT-LABEL: frem4: +; CHECK-SOFT: @ %bb.0: @ %entry +; CHECK-SOFT-NEXT: .save {r7, lr} +; CHECK-SOFT-NEXT: push {r7, lr} +; CHECK-SOFT-NEXT: mov.w r1, #1082130432 +; CHECK-SOFT-NEXT: bl fmodf +; CHECK-SOFT-NEXT: pop {r7, pc} +; +; CHECK-FP-LABEL: frem4: +; CHECK-FP: @ %bb.0: @ %entry +; CHECK-FP-NEXT: mov.w r1, #1082130432 +; CHECK-FP-NEXT: b fmodf +; +; CHECK-M33-LABEL: frem4: +; CHECK-M33: @ %bb.0: @ %entry +; CHECK-M33-NEXT: mov.w r1, #1082130432 +; CHECK-M33-NEXT: b fmodf +entry: + %fmod = frem float %x, 4.0 + ret float %fmod +} + +define float @frem4_nsz(float %x) { +; CHECK-SOFT-LABEL: frem4_nsz: +; CHECK-SOFT: @ %bb.0: @ %entry +; CHECK-SOFT-NEXT: .save {r7, lr} +; CHECK-SOFT-NEXT: push {r7, lr} +; CHECK-SOFT-NEXT: mov.w r1, #1082130432 +; CHECK-SOFT-NEXT: bl fmodf +; CHECK-SOFT-NEXT: pop {r7, pc} +; +; CHECK-FP-LABEL: frem4_nsz: +; CHECK-FP: @ %bb.0: @ %entry +; CHECK-FP-NEXT: mov.w r1, #1082130432 +; CHECK-FP-NEXT: b fmodf +; +; CHECK-M33-LABEL: frem4_nsz: +; CHECK-M33: @ %bb.0: @ %entry +; CHECK-M33-NEXT: mov.w r1, #1082130432 +; CHECK-M33-NEXT: b fmodf +entry: + %fmod = frem nsz float %x, 4.0 + ret float %fmod +} -- GitLab From 937643b8e1017ce6456de0c05b1673bd9ed0800d Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Thu, 9 May 2024 18:39:08 +0200 Subject: [PATCH 164/328] [libc++][test] Fixes constexpr char_traits. (#90981) The issue in nasty_char_traits was discovered by @StephanTLavavej who provided the solution they use in MSVC STL. This solution is based on that example. The same issue affects the constexpr_char_traits which was discovered in https://github.com/llvm/llvm-project/pull/88389. This uses the same fix. Fixes: https://github.com/llvm/llvm-project/issues/74221 --- libcxx/test/support/constexpr_char_traits.h | 57 +++++++++++++++------ libcxx/test/support/nasty_string.h | 12 +++-- 2 files changed, 48 insertions(+), 21 deletions(-) diff --git a/libcxx/test/support/constexpr_char_traits.h b/libcxx/test/support/constexpr_char_traits.h index 75380d5a7ffb..7c487c504af1 100644 --- a/libcxx/test/support/constexpr_char_traits.h +++ b/libcxx/test/support/constexpr_char_traits.h @@ -16,6 +16,31 @@ #include "test_macros.h" +// Tests whether the pointer p is in the range [first, last). +// +// Precondition: The range [first, last) is a valid range. +// +// Typically the pointers are compared with less than. This is not allowed when +// the pointers belong to different ranges, which is UB. Typically, this is +// benign at run-time, however since UB is not allowed during constant +// evaluation this does not compile. This function does the validation without +// UB. +// +// When p is in the range [first, last) the data can be copied from the +// beginning to the end. Otherwise it needs to be copied from the end to the +// beginning. +template +TEST_CONSTEXPR_CXX14 bool is_pointer_in_range(const CharT* first, const CharT* last, const CharT* p) { + if (first == p) // Needed when n == 0 + return true; + + for (; first != last; ++first) + if (first == p) + return true; + + return false; +} + template struct constexpr_char_traits { @@ -98,23 +123,21 @@ constexpr_char_traits::find(const char_type* s, std::size_t n, const char } template -TEST_CONSTEXPR_CXX14 CharT* -constexpr_char_traits::move(char_type* s1, const char_type* s2, std::size_t n) -{ - char_type* r = s1; - if (s1 < s2) - { - for (; n; --n, ++s1, ++s2) - assign(*s1, *s2); - } - else if (s2 < s1) - { - s1 += n; - s2 += n; - for (; n; --n) - assign(*--s1, *--s2); - } - return r; +TEST_CONSTEXPR_CXX14 CharT* constexpr_char_traits::move(char_type* s1, const char_type* s2, std::size_t n) { + if (s1 == s2) + return s1; + + char_type* r = s1; + if (is_pointer_in_range(s1, s1 + n, s2)) { + for (; n; --n) + assign(*s1++, *s2++); + } else { + s1 += n; + s2 += n; + for (; n; --n) + assign(*--s1, *--s2); + } + return r; } template diff --git a/libcxx/test/support/nasty_string.h b/libcxx/test/support/nasty_string.h index 672c3cb4ed9e..ea9d83ccf282 100644 --- a/libcxx/test/support/nasty_string.h +++ b/libcxx/test/support/nasty_string.h @@ -16,6 +16,7 @@ #include "make_string.h" #include "test_macros.h" +#include "constexpr_char_traits.h" // is_pointer_in_range // This defines a nasty_string similar to nasty_containers. This string's // value_type does operator hijacking, which allows us to ensure that the @@ -118,11 +119,14 @@ constexpr const nasty_char* nasty_char_traits::find(const nasty_char* s, std::si } constexpr nasty_char* nasty_char_traits::move(nasty_char* s1, const nasty_char* s2, std::size_t n) { + if (s1 == s2) + return s1; + nasty_char* r = s1; - if (s1 < s2) { - for (; n; --n, ++s1, ++s2) - assign(*s1, *s2); - } else if (s2 < s1) { + if (is_pointer_in_range(s1, s1 + n, s2)) { + for (; n; --n) + assign(*s1++, *s2++); + } else { s1 += n; s2 += n; for (; n; --n) -- GitLab From 6c8356579b20a6522d39649bcaaaf77e8e324daf Mon Sep 17 00:00:00 2001 From: Tacet Date: Thu, 9 May 2024 18:40:15 +0200 Subject: [PATCH 165/328] [libc++][ASan] Fix std::basic_string trait type (#91590) Addresses the comment: https://github.com/llvm/llvm-project/pull/79536#discussion_r1593652240 Changes the type to `void` instead of `false_type`. The value is used here: https://github.com/llvm/llvm-project/blob/6f1013a5b3f92d3ae6e378d6706584a2a44e6964/libcxx/include/__type_traits/is_trivially_relocatable.h#L35-L38 --- libcxx/include/string | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libcxx/include/string b/libcxx/include/string index 8f629d8bf13c..1db803e822d7 100644 --- a/libcxx/include/string +++ b/libcxx/include/string @@ -741,8 +741,8 @@ public: // is kept inside objects memory (short string optimization), instead of in allocated // external memory. In such cases, the destructor is responsible for unpoisoning // the memory to avoid triggering false positives. - // Therefore it's crucial to ensure the destructor is called - using __trivially_relocatable = false_type; + // Therefore it's crucial to ensure the destructor is called. + using __trivially_relocatable = void; #else using __trivially_relocatable = __conditional_t< __libcpp_is_trivially_relocatable::value && __libcpp_is_trivially_relocatable::value, -- GitLab From 2083e97e88ed13d39d9190d65696ad3866c23caa Mon Sep 17 00:00:00 2001 From: Benoit Jacob Date: Thu, 9 May 2024 12:42:45 -0400 Subject: [PATCH 166/328] Fix VectorEmulateNarrowType asserting on scalar type vs vector type. (#91613) --- .../Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp index a301b919dc52..6025c4ad7c14 100644 --- a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp +++ b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp @@ -1119,8 +1119,9 @@ struct RewriteAlignedSubByteIntExt : OpRewritePattern { PatternRewriter &rewriter) const override { // Verify the preconditions. Value srcValue = conversionOp.getIn(); - auto srcVecType = cast(srcValue.getType()); - auto dstVecType = cast(conversionOp.getType()); + auto srcVecType = dyn_cast(srcValue.getType()); + auto dstVecType = dyn_cast(conversionOp.getType()); + if (failed( commonConversionPrecondition(rewriter, dstVecType, conversionOp))) return failure(); -- GitLab From 28c427e5c022634ef479a98dc46291067a8c6c96 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 9 May 2024 09:44:07 -0700 Subject: [PATCH 167/328] [flang] Ensure that DATA converter can cope with proc ptr error (#90973) Multiple definitions of a procedure pointer with DATA statements should elicit an error message, not a compiler crash. Fixes https://github.com/llvm/llvm-project/issues/90944. --- flang/include/flang/Evaluate/tools.h | 6 ++++-- flang/lib/Evaluate/fold-designator.cpp | 28 ++++++++++++++++---------- flang/lib/Evaluate/tools.cpp | 6 +++--- flang/test/Semantics/data01.f90 | 2 +- flang/test/Semantics/data23.f90 | 18 +++++++++++++++++ 5 files changed, 43 insertions(+), 17 deletions(-) create mode 100644 flang/test/Semantics/data23.f90 diff --git a/flang/include/flang/Evaluate/tools.h b/flang/include/flang/Evaluate/tools.h index ca14c144af2d..cb750d5e82d8 100644 --- a/flang/include/flang/Evaluate/tools.h +++ b/flang/include/flang/Evaluate/tools.h @@ -152,9 +152,11 @@ std::optional> AsGenericExpr(const Symbol &); // Propagate std::optional from input to output. template std::optional> AsGenericExpr(std::optional &&x) { - if (!x) + if (x) { + return AsGenericExpr(std::move(*x)); + } else { return std::nullopt; - return AsGenericExpr(std::move(*x)); + } } template diff --git a/flang/lib/Evaluate/fold-designator.cpp b/flang/lib/Evaluate/fold-designator.cpp index 6952436681f7..0d8c22fb2977 100644 --- a/flang/lib/Evaluate/fold-designator.cpp +++ b/flang/lib/Evaluate/fold-designator.cpp @@ -273,9 +273,8 @@ static std::optional OffsetToDataRef(FoldingContext &context, if (IsAllocatableOrPointer(symbol)) { return entity.IsSymbol() ? DataRef{symbol} : DataRef{std::move(entity.GetComponent())}; - } - std::optional result; - if (std::optional type{DynamicType::From(symbol)}) { + } else if (std::optional type{DynamicType::From(symbol)}) { + std::optional result; if (!type->IsUnlimitedPolymorphic()) { if (std::optional shape{GetShape(context, symbol)}) { if (GetRank(*shape) > 0) { @@ -289,7 +288,7 @@ static std::optional OffsetToDataRef(FoldingContext &context, : DataRef{std::move(entity.GetComponent())}; } if (result && type->category() == TypeCategory::Derived && - size < result->GetLastSymbol().size()) { + size <= result->GetLastSymbol().size()) { if (const Symbol * component{OffsetToUniqueComponent( type->GetDerivedTypeSpec(), offset)}) { @@ -298,25 +297,32 @@ static std::optional OffsetToDataRef(FoldingContext &context, NamedEntity{Component{std::move(*result), *component}}, offset, size); } - result.reset(); } } } + return result; + } else { + return std::nullopt; } - return result; } // Reconstructs a Designator from a symbol, an offset, and a size. +// Returns a ProcedureDesignator in the case of a whole procedure pointer. std::optional> OffsetToDesignator(FoldingContext &context, const Symbol &baseSymbol, ConstantSubscript offset, std::size_t size) { if (offset < 0) { return std::nullopt; - } - if (std::optional dataRef{ - OffsetToDataRef(context, NamedEntity{baseSymbol}, offset, size)}) { + } else if (std::optional dataRef{OffsetToDataRef( + context, NamedEntity{baseSymbol}, offset, size)}) { const Symbol &symbol{dataRef->GetLastSymbol()}; - if (std::optional> result{ - AsGenericExpr(std::move(*dataRef))}) { + if (IsProcedurePointer(symbol)) { + if (std::holds_alternative(dataRef->u)) { + return Expr{ProcedureDesignator{symbol}}; + } else if (auto *component{std::get_if(&dataRef->u)}) { + return Expr{ProcedureDesignator{std::move(*component)}}; + } + } else if (std::optional> result{ + AsGenericExpr(std::move(*dataRef))}) { if (IsAllocatableOrPointer(symbol)) { } else if (auto type{DynamicType::From(symbol)}) { if (auto elementBytes{ diff --git a/flang/lib/Evaluate/tools.cpp b/flang/lib/Evaluate/tools.cpp index 9a5f9130632e..826b97b87bf3 100644 --- a/flang/lib/Evaluate/tools.cpp +++ b/flang/lib/Evaluate/tools.cpp @@ -28,11 +28,11 @@ namespace Fortran::evaluate { static constexpr bool allowOperandDuplication{false}; std::optional> AsGenericExpr(DataRef &&ref) { - const Symbol &symbol{ref.GetLastSymbol()}; - if (auto dyType{DynamicType::From(symbol)}) { + if (auto dyType{DynamicType::From(ref.GetLastSymbol())}) { return TypedWrapper(*dyType, std::move(ref)); + } else { + return std::nullopt; } - return std::nullopt; } std::optional> AsGenericExpr(const Symbol &symbol) { diff --git a/flang/test/Semantics/data01.f90 b/flang/test/Semantics/data01.f90 index 9046487fa176..fe2d16e95ee1 100644 --- a/flang/test/Semantics/data01.f90 +++ b/flang/test/Semantics/data01.f90 @@ -67,6 +67,6 @@ subroutine CheckValue !ERROR: DATA statement value 'b(1_8)' for 'z' is not a constant data z / b(1) / type(hasAlloc) ha - !ERROR: DATA statement value 'hasalloc(a=0_4)' for 'ha' is not a constant + !ERROR: DATA statement value 'hasalloc(a=0_4)' for 'ha%a' is not a constant data ha / hasAlloc(0) / end diff --git a/flang/test/Semantics/data23.f90 b/flang/test/Semantics/data23.f90 new file mode 100644 index 000000000000..8210e9e62b81 --- /dev/null +++ b/flang/test/Semantics/data23.f90 @@ -0,0 +1,18 @@ +! RUN: %python %S/test_errors.py %s %flang_fc1 +program p + interface + subroutine s + end subroutine + end interface + !ERROR: DATA statement initializations affect 'p' more than once + procedure(s), pointer :: p + type t + procedure(s), pointer, nopass :: p + end type + !ERROR: DATA statement initializations affect 'x%p' more than once + type(t) x + data p /s/ + data p /s/ + data x%p /s/ + data x%p /s/ +end -- GitLab From e9be1292873428a81524f200aaa5cc23b857b22e Mon Sep 17 00:00:00 2001 From: Tulio Magno Quites Machado Filho Date: Thu, 9 May 2024 13:46:49 -0300 Subject: [PATCH 168/328] [Offload] Fixes typo in aarch64 triple (#91622) Use llvm::Triple:aarch64 as the little-endian triple. Fixes commit 3e54768d7a0e1cfa65e892b6602993192ecad91e. --- offload/plugins-nextgen/host/src/rtl.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/offload/plugins-nextgen/host/src/rtl.cpp b/offload/plugins-nextgen/host/src/rtl.cpp index 409b44b1640a..ef84cbaf5458 100644 --- a/offload/plugins-nextgen/host/src/rtl.cpp +++ b/offload/plugins-nextgen/host/src/rtl.cpp @@ -427,7 +427,7 @@ struct GenELF64PluginTy final : public GenericPluginTy { return llvm::Triple::systemz; #elif defined(__aarch64__) #ifdef LITTLEENDIAN_CPU - return llvm::Triple::aarch64_le; + return llvm::Triple::aarch64; #else return llvm::Triple::aarch64_be; #endif -- GitLab From 41f0574c4654fb8a8cbb8c26d453f51a31cfd2a0 Mon Sep 17 00:00:00 2001 From: Xiang Li Date: Thu, 9 May 2024 09:47:07 -0700 Subject: [PATCH 169/328] [HLSL] reenable add packoffset in AST (#91474) This reapplies https://github.com/llvm/llvm-project/commit/c5509fedc5757fffece385d9d068e36b26793ade "[HLSL] Support packoffset attribute in AST (https://github.com/llvm/llvm-project/pull/89836)" with a fix for the test failure caused by missing -fnative-half-type. Since we have to parse the attribute manually in ParseHLSLAnnotations, we could create the ParsedAttribute with an integer offset parameter instead of string. This approach avoids parsing the string if the offset is saved as a string in HLSLPackOffsetAttr. For #57914 --- clang/include/clang/Basic/Attr.td | 12 ++ clang/include/clang/Basic/AttrDocs.td | 20 +++ clang/include/clang/Basic/DiagnosticGroups.td | 3 + .../clang/Basic/DiagnosticParseKinds.td | 2 + .../clang/Basic/DiagnosticSemaKinds.td | 5 + clang/lib/Parse/ParseHLSL.cpp | 88 +++++++++++++ clang/lib/Sema/SemaDeclAttr.cpp | 52 ++++++++ clang/lib/Sema/SemaHLSL.cpp | 80 ++++++++++++ clang/test/AST/HLSL/packoffset.hlsl | 100 ++++++++++++++ clang/test/SemaHLSL/packoffset-invalid.hlsl | 122 ++++++++++++++++++ 10 files changed, 484 insertions(+) create mode 100644 clang/test/AST/HLSL/packoffset.hlsl create mode 100644 clang/test/SemaHLSL/packoffset-invalid.hlsl diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 0225598cbbe8..52552ba48856 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -4415,6 +4415,18 @@ def HLSLResourceBinding: InheritableAttr { let Documentation = [HLSLResourceBindingDocs]; } +def HLSLPackOffset: HLSLAnnotationAttr { + let Spellings = [HLSLAnnotation<"packoffset">]; + let LangOpts = [HLSL]; + let Args = [IntArgument<"Subcomponent">, IntArgument<"Component">]; + let Documentation = [HLSLPackOffsetDocs]; + let AdditionalMembers = [{ + unsigned getOffset() { + return subcomponent * 4 + component; + } + }]; +} + def HLSLSV_DispatchThreadID: HLSLAnnotationAttr { let Spellings = [HLSLAnnotation<"SV_DispatchThreadID">]; let Subjects = SubjectList<[ParmVar, Field]>; diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index 8e6faabfae64..f351822ac74b 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -7408,6 +7408,26 @@ The full documentation is available here: https://docs.microsoft.com/en-us/windo }]; } +def HLSLPackOffsetDocs : Documentation { + let Category = DocCatFunction; + let Content = [{ +The packoffset attribute is used to change the layout of a cbuffer. +Attribute spelling in HLSL is: ``packoffset( c[Subcomponent][.component] )``. +A subcomponent is a register number, which is an integer. A component is in the form of [.xyzw]. + +Examples: + +.. code-block:: c++ + + cbuffer A { + float3 a : packoffset(c0.y); + float4 b : packoffset(c4); + } + +The full documentation is available here: https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-variable-packoffset + }]; +} + def HLSLSV_DispatchThreadIDDocs : Documentation { let Category = DocCatFunction; let Content = [{ diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td index 60f87da2a738..2beb1d45124b 100644 --- a/clang/include/clang/Basic/DiagnosticGroups.td +++ b/clang/include/clang/Basic/DiagnosticGroups.td @@ -1507,6 +1507,9 @@ def BranchProtection : DiagGroup<"branch-protection">; // Warnings for HLSL Clang extensions def HLSLExtension : DiagGroup<"hlsl-extensions">; +// Warning for mix packoffset and non-packoffset. +def HLSLMixPackOffset : DiagGroup<"mix-packoffset">; + // Warnings for DXIL validation def DXILValidation : DiagGroup<"dxil-validation">; diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td index fdffb35ea0d9..bc9d7cacc50b 100644 --- a/clang/include/clang/Basic/DiagnosticParseKinds.td +++ b/clang/include/clang/Basic/DiagnosticParseKinds.td @@ -1754,5 +1754,7 @@ def err_hlsl_separate_attr_arg_and_number : Error<"wrong argument format for hls def ext_hlsl_access_specifiers : ExtWarn< "access specifiers are a clang HLSL extension">, InGroup; +def err_hlsl_unsupported_component : Error<"invalid component '%0' used; expected 'x', 'y', 'z', or 'w'">; +def err_hlsl_packoffset_invalid_reg : Error<"invalid resource class specifier '%0' for packoffset, expected 'c'">; } // end of Parser diagnostics diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 9317ae675c72..d6863f90edb6 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -12184,6 +12184,11 @@ def err_hlsl_init_priority_unsupported : Error< def err_hlsl_unsupported_register_type : Error<"invalid resource class specifier '%0' used; expected 'b', 's', 't', or 'u'">; def err_hlsl_unsupported_register_number : Error<"register number should be an integer">; def err_hlsl_expected_space : Error<"invalid space specifier '%0' used; expected 'space' followed by an integer, like space1">; +def warn_hlsl_packoffset_mix : Warning<"cannot mix packoffset elements with nonpackoffset elements in a cbuffer">, + InGroup; +def err_hlsl_packoffset_overlap : Error<"packoffset overlap between %0, %1">; +def err_hlsl_packoffset_cross_reg_boundary : Error<"packoffset cannot cross register boundary">; +def err_hlsl_packoffset_alignment_mismatch : Error<"packoffset at 'y' not match alignment %0 required by %1">; def err_hlsl_pointers_unsupported : Error< "%select{pointers|references}0 are unsupported in HLSL">; diff --git a/clang/lib/Parse/ParseHLSL.cpp b/clang/lib/Parse/ParseHLSL.cpp index f4cbece31f18..e9c8d6dca7bf 100644 --- a/clang/lib/Parse/ParseHLSL.cpp +++ b/clang/lib/Parse/ParseHLSL.cpp @@ -183,6 +183,94 @@ void Parser::ParseHLSLAnnotations(ParsedAttributes &Attrs, return; } } break; + case ParsedAttr::AT_HLSLPackOffset: { + // Parse 'packoffset( c[Subcomponent][.component] )'. + // Check '('. + if (ExpectAndConsume(tok::l_paren, diag::err_expected_lparen_after)) { + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + // Check c[Subcomponent] as an identifier. + if (!Tok.is(tok::identifier)) { + Diag(Tok.getLocation(), diag::err_expected) << tok::identifier; + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + StringRef OffsetStr = Tok.getIdentifierInfo()->getName(); + SourceLocation SubComponentLoc = Tok.getLocation(); + if (OffsetStr[0] != 'c') { + Diag(Tok.getLocation(), diag::err_hlsl_packoffset_invalid_reg) + << OffsetStr; + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + OffsetStr = OffsetStr.substr(1); + unsigned SubComponent = 0; + if (!OffsetStr.empty()) { + // Make sure SubComponent is a number. + if (OffsetStr.getAsInteger(10, SubComponent)) { + Diag(SubComponentLoc.getLocWithOffset(1), + diag::err_hlsl_unsupported_register_number); + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + } + unsigned Component = 0; + ConsumeToken(); // consume identifier. + SourceLocation ComponentLoc; + if (Tok.is(tok::period)) { + ConsumeToken(); // consume period. + if (!Tok.is(tok::identifier)) { + Diag(Tok.getLocation(), diag::err_expected) << tok::identifier; + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + StringRef ComponentStr = Tok.getIdentifierInfo()->getName(); + ComponentLoc = Tok.getLocation(); + ConsumeToken(); // consume identifier. + // Make sure Component is a single character. + if (ComponentStr.size() != 1) { + Diag(ComponentLoc, diag::err_hlsl_unsupported_component) + << ComponentStr; + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + switch (ComponentStr[0]) { + case 'x': + case 'r': + Component = 0; + break; + case 'y': + case 'g': + Component = 1; + break; + case 'z': + case 'b': + Component = 2; + break; + case 'w': + case 'a': + Component = 3; + break; + default: + Diag(ComponentLoc, diag::err_hlsl_unsupported_component) + << ComponentStr; + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + } + ASTContext &Ctx = Actions.getASTContext(); + QualType SizeTy = Ctx.getSizeType(); + uint64_t SizeTySize = Ctx.getTypeSize(SizeTy); + ArgExprs.push_back(IntegerLiteral::Create( + Ctx, llvm::APInt(SizeTySize, SubComponent), SizeTy, SubComponentLoc)); + ArgExprs.push_back(IntegerLiteral::Create( + Ctx, llvm::APInt(SizeTySize, Component), SizeTy, ComponentLoc)); + if (ExpectAndConsume(tok::r_paren, diag::err_expected)) { + SkipUntil(tok::r_paren, StopAtSemi); // skip through ) + return; + } + } break; case ParsedAttr::UnknownAttribute: Diag(Loc, diag::err_unknown_hlsl_semantic) << II; return; diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 6ca42856459f..6d957ac09e1c 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -7309,6 +7309,55 @@ static void handleHLSLSV_DispatchThreadIDAttr(Sema &S, Decl *D, D->addAttr(::new (S.Context) HLSLSV_DispatchThreadIDAttr(S.Context, AL)); } +static void handleHLSLPackOffsetAttr(Sema &S, Decl *D, const ParsedAttr &AL) { + if (!isa(D) || !isa(D->getDeclContext())) { + S.Diag(AL.getLoc(), diag::err_hlsl_attr_invalid_ast_node) + << AL << "shader constant in a constant buffer"; + return; + } + + uint32_t SubComponent; + if (!checkUInt32Argument(S, AL, AL.getArgAsExpr(0), SubComponent)) + return; + uint32_t Component; + if (!checkUInt32Argument(S, AL, AL.getArgAsExpr(1), Component)) + return; + + QualType T = cast(D)->getType().getCanonicalType(); + // Check if T is an array or struct type. + // TODO: mark matrix type as aggregate type. + bool IsAggregateTy = (T->isArrayType() || T->isStructureType()); + + // Check Component is valid for T. + if (Component) { + unsigned Size = S.getASTContext().getTypeSize(T); + if (IsAggregateTy || Size > 128) { + S.Diag(AL.getLoc(), diag::err_hlsl_packoffset_cross_reg_boundary); + return; + } else { + // Make sure Component + sizeof(T) <= 4. + if ((Component * 32 + Size) > 128) { + S.Diag(AL.getLoc(), diag::err_hlsl_packoffset_cross_reg_boundary); + return; + } + QualType EltTy = T; + if (const auto *VT = T->getAs()) + EltTy = VT->getElementType(); + unsigned Align = S.getASTContext().getTypeAlign(EltTy); + if (Align > 32 && Component == 1) { + // NOTE: Component 3 will hit err_hlsl_packoffset_cross_reg_boundary. + // So we only need to check Component 1 here. + S.Diag(AL.getLoc(), diag::err_hlsl_packoffset_alignment_mismatch) + << Align << EltTy; + return; + } + } + } + + D->addAttr(::new (S.Context) + HLSLPackOffsetAttr(S.Context, AL, SubComponent, Component)); +} + static void handleHLSLShaderAttr(Sema &S, Decl *D, const ParsedAttr &AL) { StringRef Str; SourceLocation ArgLoc; @@ -9730,6 +9779,9 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, case ParsedAttr::AT_HLSLSV_DispatchThreadID: handleHLSLSV_DispatchThreadIDAttr(S, D, AL); break; + case ParsedAttr::AT_HLSLPackOffset: + handleHLSLPackOffsetAttr(S, D, AL); + break; case ParsedAttr::AT_HLSLShader: handleHLSLShaderAttr(S, D, AL); break; diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp index bb9e37f18d37..6a12c417e2f3 100644 --- a/clang/lib/Sema/SemaHLSL.cpp +++ b/clang/lib/Sema/SemaHLSL.cpp @@ -39,9 +39,89 @@ Decl *SemaHLSL::ActOnStartBuffer(Scope *BufferScope, bool CBuffer, return Result; } +// Calculate the size of a legacy cbuffer type based on +// https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-packing-rules +static unsigned calculateLegacyCbufferSize(const ASTContext &Context, + QualType T) { + unsigned Size = 0; + constexpr unsigned CBufferAlign = 128; + if (const RecordType *RT = T->getAs()) { + const RecordDecl *RD = RT->getDecl(); + for (const FieldDecl *Field : RD->fields()) { + QualType Ty = Field->getType(); + unsigned FieldSize = calculateLegacyCbufferSize(Context, Ty); + unsigned FieldAlign = 32; + if (Ty->isAggregateType()) + FieldAlign = CBufferAlign; + Size = llvm::alignTo(Size, FieldAlign); + Size += FieldSize; + } + } else if (const ConstantArrayType *AT = Context.getAsConstantArrayType(T)) { + if (unsigned ElementCount = AT->getSize().getZExtValue()) { + unsigned ElementSize = + calculateLegacyCbufferSize(Context, AT->getElementType()); + unsigned AlignedElementSize = llvm::alignTo(ElementSize, CBufferAlign); + Size = AlignedElementSize * (ElementCount - 1) + ElementSize; + } + } else if (const VectorType *VT = T->getAs()) { + unsigned ElementCount = VT->getNumElements(); + unsigned ElementSize = + calculateLegacyCbufferSize(Context, VT->getElementType()); + Size = ElementSize * ElementCount; + } else { + Size = Context.getTypeSize(T); + } + return Size; +} + void SemaHLSL::ActOnFinishBuffer(Decl *Dcl, SourceLocation RBrace) { auto *BufDecl = cast(Dcl); BufDecl->setRBraceLoc(RBrace); + + // Validate packoffset. + llvm::SmallVector> PackOffsetVec; + bool HasPackOffset = false; + bool HasNonPackOffset = false; + for (auto *Field : BufDecl->decls()) { + VarDecl *Var = dyn_cast(Field); + if (!Var) + continue; + if (Field->hasAttr()) { + PackOffsetVec.emplace_back(Var, Field->getAttr()); + HasPackOffset = true; + } else { + HasNonPackOffset = true; + } + } + + if (HasPackOffset && HasNonPackOffset) + Diag(BufDecl->getLocation(), diag::warn_hlsl_packoffset_mix); + + if (HasPackOffset) { + ASTContext &Context = getASTContext(); + // Make sure no overlap in packoffset. + // Sort PackOffsetVec by offset. + std::sort(PackOffsetVec.begin(), PackOffsetVec.end(), + [](const std::pair &LHS, + const std::pair &RHS) { + return LHS.second->getOffset() < RHS.second->getOffset(); + }); + + for (unsigned i = 0; i < PackOffsetVec.size() - 1; i++) { + VarDecl *Var = PackOffsetVec[i].first; + HLSLPackOffsetAttr *Attr = PackOffsetVec[i].second; + unsigned Size = calculateLegacyCbufferSize(Context, Var->getType()); + unsigned Begin = Attr->getOffset() * 32; + unsigned End = Begin + Size; + unsigned NextBegin = PackOffsetVec[i + 1].second->getOffset() * 32; + if (End > NextBegin) { + VarDecl *NextVar = PackOffsetVec[i + 1].first; + Diag(NextVar->getLocation(), diag::err_hlsl_packoffset_overlap) + << NextVar << Var; + } + } + } + SemaRef.PopDeclContext(); } diff --git a/clang/test/AST/HLSL/packoffset.hlsl b/clang/test/AST/HLSL/packoffset.hlsl new file mode 100644 index 000000000000..060288c2f7f7 --- /dev/null +++ b/clang/test/AST/HLSL/packoffset.hlsl @@ -0,0 +1,100 @@ +// RUN: %clang_cc1 -triple dxil-unknown-shadermodel6.3-library -S -finclude-default-header -fnative-half-type -ast-dump -x hlsl %s | FileCheck %s + + +// CHECK: HLSLBufferDecl {{.*}} cbuffer A +cbuffer A +{ + // CHECK-NEXT: VarDecl {{.*}} A1 'float4' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 0 + float4 A1 : packoffset(c); + // CHECK-NEXT: VarDecl {{.*}} col:11 A2 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 1 0 + float A2 : packoffset(c1); + // CHECK-NEXT: VarDecl {{.*}} col:11 A3 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 1 1 + float A3 : packoffset(c1.y); +} + +// CHECK: HLSLBufferDecl {{.*}} cbuffer B +cbuffer B +{ + // CHECK: VarDecl {{.*}} B0 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 1 + float B0 : packoffset(c0.g); + // CHECK-NEXT: VarDecl {{.*}} B1 'double' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 2 + double B1 : packoffset(c0.b); + // CHECK-NEXT: VarDecl {{.*}} B2 'half' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 0 + half B2 : packoffset(c0.r); +} + +// CHECK: HLSLBufferDecl {{.*}} cbuffer C +cbuffer C +{ + // CHECK: VarDecl {{.*}} C0 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 1 + float C0 : packoffset(c0.y); + // CHECK-NEXT: VarDecl {{.*}} C1 'float2' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 2 + float2 C1 : packoffset(c0.z); + // CHECK-NEXT: VarDecl {{.*}} C2 'half' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 + half C2 : packoffset(c0.x); +} + + +// CHECK: HLSLBufferDecl {{.*}} cbuffer D +cbuffer D +{ + // CHECK: VarDecl {{.*}} D0 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 1 + float D0 : packoffset(c0.y); + // CHECK-NEXT: VarDecl {{.*}} D1 'float[2]' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 1 0 + float D1[2] : packoffset(c1.x); + // CHECK-NEXT: VarDecl {{.*}} D2 'half3' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 2 1 + half3 D2 : packoffset(c2.y); + // CHECK-NEXT: VarDecl {{.*}} D3 'double' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 2 + double D3 : packoffset(c0.z); +} + +struct ST { + float a; + float2 b; + half c; +}; + +// CHECK: HLSLBufferDecl {{.*}} cbuffer S +cbuffer S { + // CHECK: VarDecl {{.*}} S0 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 1 + float S0 : packoffset(c0.y); + // CHECK: VarDecl {{.*}} S1 'ST' + // CHECK: HLSLPackOffsetAttr {{.*}} 1 0 + ST S1 : packoffset(c1); + // CHECK: VarDecl {{.*}} S2 'double2' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 2 0 + double2 S2 : packoffset(c2); +} + +struct ST2 { + float s0; + ST s1; + half s2; +}; + +// CHECK: HLSLBufferDecl {{.*}} cbuffer S2 +cbuffer S2 { + // CHECK: VarDecl {{.*}} S20 'float' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 0 3 + float S20 : packoffset(c0.a); + // CHECK: VarDecl {{.*}} S21 'ST2' + // CHECK: HLSLPackOffsetAttr {{.*}} 1 0 + ST2 S21 : packoffset(c1); + // CHECK: VarDecl {{.*}} S22 'half' + // CHECK-NEXT: HLSLPackOffsetAttr {{.*}} 3 1 + half S22 : packoffset(c3.y); +} diff --git a/clang/test/SemaHLSL/packoffset-invalid.hlsl b/clang/test/SemaHLSL/packoffset-invalid.hlsl new file mode 100644 index 000000000000..526a511edf1f --- /dev/null +++ b/clang/test/SemaHLSL/packoffset-invalid.hlsl @@ -0,0 +1,122 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.3-library -fnative-half-type -verify %s + +// expected-warning@+1{{cannot mix packoffset elements with nonpackoffset elements in a cbuffer}} +cbuffer Mix +{ + float4 M1 : packoffset(c0); + float M2; + float M3 : packoffset(c1.y); +} + +// expected-warning@+1{{cannot mix packoffset elements with nonpackoffset elements in a cbuffer}} +cbuffer Mix2 +{ + float4 M4; + float M5 : packoffset(c1.y); + float M6 ; +} + +// expected-error@+1{{attribute 'packoffset' only applies to shader constant in a constant buffer}} +float4 g : packoffset(c0); + +cbuffer IllegalOffset +{ + // expected-error@+1{{invalid resource class specifier 't2' for packoffset, expected 'c'}} + float4 i1 : packoffset(t2); + // expected-error@+1{{invalid component 'm' used; expected 'x', 'y', 'z', or 'w'}} + float i2 : packoffset(c1.m); +} + +cbuffer Overlap +{ + float4 o1 : packoffset(c0); + // expected-error@+1{{packoffset overlap between 'o2', 'o1'}} + float2 o2 : packoffset(c0.z); +} + +cbuffer CrossReg +{ + // expected-error@+1{{packoffset cannot cross register boundary}} + float4 c1 : packoffset(c0.y); + // expected-error@+1{{packoffset cannot cross register boundary}} + float2 c2 : packoffset(c1.w); +} + +struct ST { + float s; +}; + +cbuffer Aggregate +{ + // expected-error@+1{{packoffset cannot cross register boundary}} + ST A1 : packoffset(c0.y); + // expected-error@+1{{packoffset cannot cross register boundary}} + float A2[2] : packoffset(c1.w); +} + +cbuffer Double { + // expected-error@+1{{packoffset at 'y' not match alignment 64 required by 'double'}} + double d : packoffset(c.y); + // expected-error@+1{{packoffset cannot cross register boundary}} + double2 d2 : packoffset(c.z); + // expected-error@+1{{packoffset cannot cross register boundary}} + double3 d3 : packoffset(c.z); +} + +cbuffer ParsingFail { +// expected-error@+1{{expected identifier}} +float pf0 : packoffset(); +// expected-error@+1{{expected identifier}} +float pf1 : packoffset((c0)); +// expected-error@+1{{expected ')'}} +float pf2 : packoffset(c0, x); +// expected-error@+1{{invalid component 'X' used}} +float pf3 : packoffset(c.X); +// expected-error@+1{{expected '(' after ''}} +float pf4 : packoffset; +// expected-error@+1{{expected identifier}} +float pf5 : packoffset(; +// expected-error@+1{{expected '(' after '}} +float pf6 : packoffset); +// expected-error@+1{{expected '(' after '}} +float pf7 : packoffset c0.x; + +// expected-error@+1{{invalid component 'xy' used}} +float pf8 : packoffset(c0.xy); +// expected-error@+1{{invalid component 'rg' used}} +float pf9 : packoffset(c0.rg); +// expected-error@+1{{invalid component 'yes' used}} +float pf10 : packoffset(c0.yes); +// expected-error@+1{{invalid component 'woo'}} +float pf11 : packoffset(c0.woo); +// expected-error@+1{{invalid component 'xr' used}} +float pf12 : packoffset(c0.xr); +} + +struct ST2 { + float a; + float2 b; +}; + +cbuffer S { + float S0 : packoffset(c0.y); + ST2 S1[2] : packoffset(c1); + // expected-error@+1{{packoffset overlap between 'S2', 'S1'}} + half2 S2 : packoffset(c1.w); + half2 S3 : packoffset(c2.w); +} + +struct ST23 { + float s0; + ST2 s1; +}; + +cbuffer S2 { + float S20 : packoffset(c0.y); + ST2 S21 : packoffset(c1); + half2 S22 : packoffset(c2.w); + double S23[2] : packoffset(c3); + // expected-error@+1{{packoffset overlap between 'S24', 'S23'}} + float S24 : packoffset(c3.z); + float S25 : packoffset(c4.z); +} -- GitLab From d0bafb5435d5ebd90cdf965a9b35bdfa05dde23b Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Thu, 9 May 2024 09:28:06 -0700 Subject: [PATCH 170/328] [RISCV] Add coverage for zext.w/h interaction with shift transforms Two cases where folding the and (which could be a zext.w) through shifts in generic DAG result in net worse code quality. And one negative case where keeping a zext.h would result in a longer critical path. --- llvm/test/CodeGen/RISCV/rv64zba.ll | 63 ++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll index 5931e0982a4a..8fe221f2a297 100644 --- a/llvm/test/CodeGen/RISCV/rv64zba.ll +++ b/llvm/test/CodeGen/RISCV/rv64zba.ll @@ -2853,3 +2853,66 @@ entry: ret i64 %6 } +define ptr @gep_lshr_i32(ptr %0, i64 %1) { +; RV64I-LABEL: gep_lshr_i32: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: srli a1, a1, 2 +; RV64I-NEXT: li a2, 5 +; RV64I-NEXT: slli a2, a2, 36 +; RV64I-NEXT: slli a1, a1, 32 +; RV64I-NEXT: mulhu a1, a1, a2 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: gep_lshr_i32: +; RV64ZBA: # %bb.0: # %entry +; RV64ZBA-NEXT: slli a1, a1, 2 +; RV64ZBA-NEXT: srli a1, a1, 4 +; RV64ZBA-NEXT: slli.uw a1, a1, 4 +; RV64ZBA-NEXT: sh2add a1, a1, a1 +; RV64ZBA-NEXT: add a0, a0, a1 +; RV64ZBA-NEXT: ret +entry: + %2 = lshr exact i64 %1, 2 + %3 = and i64 %2, 4294967295 + %5 = getelementptr [80 x i8], ptr %0, i64 %3 + ret ptr %5 +} + +define i64 @srli_slliw(i64 %1) { +; RV64I-LABEL: srli_slliw: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: slli a0, a0, 2 +; RV64I-NEXT: li a1, 1 +; RV64I-NEXT: slli a1, a1, 36 +; RV64I-NEXT: addi a1, a1, -16 +; RV64I-NEXT: and a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: srli_slliw: +; RV64ZBA: # %bb.0: # %entry +; RV64ZBA-NEXT: slli a0, a0, 2 +; RV64ZBA-NEXT: srli a0, a0, 4 +; RV64ZBA-NEXT: slli.uw a0, a0, 4 +; RV64ZBA-NEXT: ret +entry: + %2 = lshr exact i64 %1, 2 + %3 = and i64 %2, 4294967295 + %4 = shl i64 %3, 4 + ret i64 %4 +} + +define i64 @srli_slli_i16(i64 %1) { +; CHECK-LABEL: srli_slli_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: slli a0, a0, 2 +; CHECK-NEXT: lui a1, 256 +; CHECK-NEXT: addiw a1, a1, -16 +; CHECK-NEXT: and a0, a0, a1 +; CHECK-NEXT: ret +entry: + %2 = lshr exact i64 %1, 2 + %3 = and i64 %2, 65535 + %4 = shl i64 %3, 4 + ret i64 %4 +} -- GitLab From 8ed7ea08962bb878d31052c15e811d1a6cda0f07 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 9 May 2024 09:56:01 -0700 Subject: [PATCH 171/328] [flang] Defer conversion of PDT default initializers (#91026) As the kinds of the integer types of type parameters may well depend on the values of other type parameters, defer the attempt to convert their values to the point of type instantiation instead of doing it during declaration processing. --- flang/lib/Semantics/resolve-names.cpp | 3 +-- flang/test/Semantics/modfile12.f90 | 2 +- flang/test/Semantics/modfile17.f90 | 6 +++--- flang/test/Semantics/pdt03.f90 | 9 +++++++++ 4 files changed, 14 insertions(+), 6 deletions(-) create mode 100644 flang/test/Semantics/pdt03.f90 diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index 61394b0f41de..2199e3f16e62 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -5550,8 +5550,7 @@ void DeclarationVisitor::Post(const parser::TypeParamDefStmt &x) { SetType(name, *type); if (auto &init{ std::get>(decl.t)}) { - if (auto maybeExpr{EvaluateNonPointerInitializer( - *symbol, *init, init->thing.thing.thing.value().source)}) { + if (auto maybeExpr{AnalyzeExpr(context(), *init)}) { if (auto *intExpr{std::get_if(&maybeExpr->u)}) { symbol->get().set_init(std::move(*intExpr)); } diff --git a/flang/test/Semantics/modfile12.f90 b/flang/test/Semantics/modfile12.f90 index 17b6e95c4a56..41ab300e00f6 100644 --- a/flang/test/Semantics/modfile12.f90 +++ b/flang/test/Semantics/modfile12.f90 @@ -41,7 +41,7 @@ end ! real(4)::y(1_8:8_8) ! type::t(c,d) ! integer(4),kind::c=1_4 -! integer(4),len::d=3_4 +! integer(4),len::d=3_8 ! end type ! type(t(c=4_4,d=:)),allocatable::z ! class(t(c=5_4,d=:)),allocatable::z2 diff --git a/flang/test/Semantics/modfile17.f90 b/flang/test/Semantics/modfile17.f90 index 189d8a83de8c..4ab5cc85db25 100644 --- a/flang/test/Semantics/modfile17.f90 +++ b/flang/test/Semantics/modfile17.f90 @@ -97,10 +97,10 @@ end module !integer(k8)::j8 !end type !type::defaulted(n1,n2,n4,n8) -!integer(1),kind::n1=1_1 -!integer(2),kind::n2=int(2_4*int(int(n1,kind=1),kind=4),kind=2) +!integer(1),kind::n1=1_4 +!integer(2),kind::n2=2_4*int(int(n1,kind=1),kind=4) !integer(4),kind::n4=2_4*int(int(n2,kind=2),kind=4) -!integer(8),kind::n8=int(12_4-int(n4,kind=4),kind=8) +!integer(8),kind::n8=12_4-int(n4,kind=4) !type(capture(k1=int(n1,kind=1),k2=int(n2,kind=2),k4=int(n4,kind=4),k8=n8))::cap !end type !type,extends(defaulted)::extension(k5) diff --git a/flang/test/Semantics/pdt03.f90 b/flang/test/Semantics/pdt03.f90 new file mode 100644 index 000000000000..2fb63d21540b --- /dev/null +++ b/flang/test/Semantics/pdt03.f90 @@ -0,0 +1,9 @@ +! RUN: %flang_fc1 -fdebug-unparse %s 2>&1 | FileCheck %s +type t(kp1,kp2) + integer, kind :: kp1 + integer(kp1), kind :: kp2 = kp1 +end type +type(t(kp1=8_8)) x +!CHECK: 4_4, 8_4, 8_4, 8_8 +print *, kind(x%kp1), x%kp1, kind(x%kp2), x%kp2 +end -- GitLab From 4c3db2588e8b38f75744def6e2dd17c556950e46 Mon Sep 17 00:00:00 2001 From: Adam Siemieniuk Date: Thu, 9 May 2024 19:02:44 +0200 Subject: [PATCH 172/328] [mlir][linalg] Block pack matmul pass (#89782) Pack a matmul MxNxK operation into 4D blocked layout. Any present batch dimensions remain unchanged and the result is unpacked back to the original layout. Matmul block packing splits the operands into major blocks (outer dimensions) and minor blocks (inner dimensions). The desired block layout can be controlled through packing options. --- mlir/include/mlir/Dialect/Linalg/Passes.td | 59 +++ .../Dialect/Linalg/Transforms/Transforms.h | 64 +++ .../Linalg/Transforms/BlockPackMatmul.cpp | 321 ++++++++++++ .../Dialect/Linalg/Transforms/CMakeLists.txt | 1 + .../Linalg/block-pack-matmul-layout.mlir | 101 ++++ .../Linalg/block-pack-matmul-padding.mlir | 82 +++ .../Dialect/Linalg/block-pack-matmul.mlir | 478 ++++++++++++++++++ 7 files changed, 1106 insertions(+) create mode 100644 mlir/lib/Dialect/Linalg/Transforms/BlockPackMatmul.cpp create mode 100644 mlir/test/Dialect/Linalg/block-pack-matmul-layout.mlir create mode 100644 mlir/test/Dialect/Linalg/block-pack-matmul-padding.mlir create mode 100644 mlir/test/Dialect/Linalg/block-pack-matmul.mlir diff --git a/mlir/include/mlir/Dialect/Linalg/Passes.td b/mlir/include/mlir/Dialect/Linalg/Passes.td index 85f11c66d29a..0a4ce8953136 100644 --- a/mlir/include/mlir/Dialect/Linalg/Passes.td +++ b/mlir/include/mlir/Dialect/Linalg/Passes.td @@ -141,4 +141,63 @@ def LinalgDetensorizePass : InterfacePass<"linalg-detensorize", "FunctionOpInter ]; } +def LinalgBlockPackMatmul : Pass<"linalg-block-pack-matmul"> { + let summary = "Convert linalg matmul ops to block layout and back"; + let description = [{ + Pack a matmul operation into blocked layout with two levels of subdivision: + - major 2D blocks - outer dimensions, consist of minor blocks + - minor 2D blocks - inner dimensions, consist of scalar elements + + A 2D matmul MxNxK gets reshaped into blocked 4D representation + as: [MB][NB][mb][nb] += [MB][KB][mb][kb] * [NB][KB][nb][kb] + where the (MB, NB, KB) dimensions represent the major blocks, + and the (mb, nb, kb) are the minor blocks of their respective + original 2D dimensions (M, N, K). + + Depending on the initial operands' data layout and the specified + packing options, the major blocks dimensions might get transposed + e.g., [MB][KB] -> [KB][MB]. The minor blocks can also be transposed + e.g., [mb][kb] -> [kb][mb]. + Any present batch dimensions remain unchanged. + The final result is unpacked back to the original shape. + + For example, given a matmul operation: + ```mlir + %res = linalg.matmul ins(%A, %B) outs(%C) + ``` + the default transformation result can be represented as: + ```mlir + %A_packed = pack %A : 2D -> 4D + %B_packed = pack %B : 2D -> 4D + %C_packed = pack %C : 2D -> 4D + %res_packed = linalg.mmt4d ins(%A_packed, %B_packed) outs(%C_packed) + %res = unpack %res_packed : 4D -> 2D + ``` + }]; + let dependentDialects = ["linalg::LinalgDialect", "tensor::TensorDialect"]; + let options = [ + ListOption<"blockFactors", "block-factors", "int64_t", + "Block factors (mb, nb, kb) for relayout">, + Option<"allowPadding", "allow-padding", "bool", + /*default=*/"true", + "Allow packing padding">, + ListOption<"mnkPaddedSizesNextMultipleOf", "mnk-padded-multiples", "int64_t", + "Next multiples of the packing sizes">, + ListOption<"mnkOrder", "mnk-order", "int64_t", + "Permutation of matmul (M, N, K) dimensions order">, + Option<"lhsTransposeOuterBlocks", "lhs-transpose-outer-blocks", "bool", + /*default=*/"false", + "Transpose LHS outer block layout [MB][KB] -> [KB][MB]">, + Option<"lhsTransposeInnerBlocks", "lhs-transpose-inner-blocks", "bool", + /*default=*/"false", + "Transpose LHS inner block layout [mb][kb] -> [kb][mb]">, + Option<"rhsTransposeOuterBlocks", "rhs-transpose-outer-blocks", "bool", + /*default=*/"true", + "Transpose RHS outer block layout [KB][NB] -> [NB][KB]">, + Option<"rhsTransposeInnerBlocks", "rhs-transpose-inner-blocks", "bool", + /*default=*/"true", + "Transpose RHS inner block layout [kb][nb] -> [nb][kb]"> + ]; +} + #endif // MLIR_DIALECT_LINALG_PASSES diff --git a/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h b/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h index 5ecf84fa9c70..f77c19ed0fcc 100644 --- a/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h +++ b/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h @@ -1162,6 +1162,66 @@ packMatmulGreedily(RewriterBase &rewriter, LinalgOp linalgOp, ArrayRef mnkPaddedSizesNextMultipleOf, ArrayRef mnkOrder); +struct BlockPackMatmulOptions { + /// Minor block factors (mb, nb, kb) for packing relayout where mb, mn are + /// the parallel dimensions and kb is the reduction dimension. + SmallVector blockFactors; + + /// If true, allows packing of dimensions that only partially fit into the + /// block factors. + bool allowPadding = true; + + /// Next multiples of the packing sizes. + SmallVector mnkPaddedSizesNextMultipleOf; + + /// Permutation of matmul (M, N, K) dimensions order. + SmallVector mnkOrder = {0, 1, 2}; + + /// Transpose LHS outer block layout [MB][KB] -> [KB][MB]. + bool lhsTransposeOuterBlocks = false; + + /// Transpose LHS inner block layout [mb][kb] -> [kb][mb]. + bool lhsTransposeInnerBlocks = false; + + /// Transpose RHS outer block layout [KB][NB] -> [NB][KB]. + bool rhsTransposeOuterBlocks = true; + + /// Transpose RHS inner block layout [kb][nb] -> [nb][kb]. + bool rhsTransposeInnerBlocks = true; +}; + +/// Function type which is used to control matmul packing. +/// It is expected to return valid packing configuration for each operation. +/// Lack of packing options indicates that no valid configuration could be +/// assigned and the operation will not be packed. +using ControlBlockPackMatmulFn = + std::function(linalg::LinalgOp)>; + +/// Pack a matmul operation into blocked 4D layout. +/// +/// Relayout a matmul operation into blocked layout with two levels of +/// subdivision: +/// - major 2D blocks - outer dimensions, consist of minor blocks +/// - minor 2D blocks - inner dimensions, consist of scalar elements +/// +/// A 2D matmul MxNxK gets reshaped into blocked 4D representation +/// as: [MB][NB][mb][nb] += [MB][KB][mb][kb] * [NB][KB][nb][kb] +/// where the (MB, NB, KB) dimensions represent the major blocks, +/// and the (mb, nb, kb) are the minor blocks of their respective +/// original 2D dimensions (M, N, K). +/// +/// Depending on the initial operands' data layout and the specified +/// packing options, the major blocks dimensions might get transposed +/// e.g., [MB][KB] -> [KB][MB]. The minor blocks can also be transposed +/// e.g., [mb][kb] -> [kb][mb]. +/// Any present batch dimensions remain unchanged. +/// The final result is unpacked back to the original shape. +/// +/// Return failure if no valid packing options are provided. +FailureOr +blockPackMatmul(RewriterBase &rewriter, linalg::LinalgOp linalgOp, + const ControlBlockPackMatmulFn &controlPackMatmul); + /// Rewrite tensor.from_elements to linalg.generic. FailureOr rewriteInDestinationPassingStyle(RewriterBase &rewriter, @@ -1628,6 +1688,10 @@ void populateSplitReductionPattern( void populateTransposeMatmulPatterns(RewritePatternSet &patterns, bool transposeLHS = true); +/// Patterns to block pack Linalg matmul ops. +void populateBlockPackMatmulPatterns(RewritePatternSet &patterns, + const ControlBlockPackMatmulFn &controlFn); + } // namespace linalg } // namespace mlir diff --git a/mlir/lib/Dialect/Linalg/Transforms/BlockPackMatmul.cpp b/mlir/lib/Dialect/Linalg/Transforms/BlockPackMatmul.cpp new file mode 100644 index 000000000000..c07d1387ec75 --- /dev/null +++ b/mlir/lib/Dialect/Linalg/Transforms/BlockPackMatmul.cpp @@ -0,0 +1,321 @@ +//===- BlockPackMatmul.cpp - Linalg matmul block packing ------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/Linalg/Passes.h" + +#include "mlir/Dialect/Linalg/IR/Linalg.h" +#include "mlir/Dialect/Linalg/Transforms/Transforms.h" +#include "mlir/Dialect/Linalg/Utils/Utils.h" +#include "mlir/IR/PatternMatch.h" +#include "mlir/Transforms/GreedyPatternRewriteDriver.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/TypeSwitch.h" + +#include + +namespace mlir { +#define GEN_PASS_DEF_LINALGBLOCKPACKMATMUL +#include "mlir/Dialect/Linalg/Passes.h.inc" +} // namespace mlir + +using namespace mlir; +using namespace mlir::linalg; + +/// Return constant range span or nullopt, otherwise. +static std::optional getConstantRange(const Range &range) { + std::optional stride = getConstantIntValue(range.stride); + if (!stride || *stride != 1) + return std::nullopt; + std::optional offset = getConstantIntValue(range.offset); + if (!offset) + return std::nullopt; + std::optional size = getConstantIntValue(range.size); + if (!size) + return std::nullopt; + return (*size - *offset); +} + +/// Return true if all dimensions are fully divisible by the respective tiles. +static bool validateFullTilesOnDims(linalg::LinalgOp linalgOp, + ArrayRef tiles, + ArrayRef dims) { + if (dims.size() != tiles.size() || tiles.empty()) + return false; + + FailureOr contractDims = + inferContractionDims(linalgOp); + if (failed(contractDims)) + return false; + unsigned batchDimsOffset = contractDims->batch.size(); + + // Skip the batch dimension if present. + // Offset all dimensions accordingly. + SmallVector offsetDims{dims}; + for (size_t i = 0; i < offsetDims.size(); i++) + offsetDims[i] += batchDimsOffset; + + auto tileOp = cast(linalgOp.getOperation()); + OpBuilder builder(tileOp); + OpBuilder::InsertionGuard guard(builder); + SmallVector iterationDomain = tileOp.getIterationDomain(builder); + + for (auto dim : llvm::enumerate(offsetDims)) { + if (dim.value() >= static_cast(iterationDomain.size())) + return false; + + std::optional tileSize = getConstantIntValue(tiles[dim.index()]); + std::optional rangeOnDim = + getConstantRange(iterationDomain[dim.value()]); + + // If the tile factor or the range are non-constant, the tile size is + // considered to be invalid. + if (!tileSize || !rangeOnDim) + return false; + + // The dimension must be fully divisible by the tile. + if (*rangeOnDim % *tileSize != 0) + return false; + } + + return true; +} + +/// Return failure or packed matmul with one of its operands transposed. +static FailureOr +transposePackedMatmul(RewriterBase &rewriter, linalg::LinalgOp linalgOp, + tensor::PackOp packOp, AffineMap operandMap, + ArrayRef blocksStartDimPos, + bool transposeOuterBlocks, bool transposeInnerBlocks) { + assert(operandMap.getNumDims() >= 4 && + "expected at least 4D prepacked matmul"); + assert(blocksStartDimPos.size() >= 2 && + "expected starting outer and inner block positions"); + + // Bias toward innermost dimensions. + unsigned outerBlockPos = operandMap.getNumResults() - 4; + unsigned innerBlockPos = operandMap.getNumResults() - 2; + + // Transpose control options define the desired block and element layout. + // Block transposition (outer dimensions) or element transposition (inner + // dimensions) may not be necessary depending on the original matmul data + // layout. + bool isOuterTransposed = + operandMap.getDimPosition(outerBlockPos) != blocksStartDimPos.end()[-2]; + bool isInnerTransposed = + operandMap.getDimPosition(innerBlockPos) != blocksStartDimPos.back(); + + // Transpose only the dimensions that need that to conform to the provided + // transpotion settings. + SmallVector innerPerm{0, 1}; + if (isInnerTransposed != transposeInnerBlocks) + innerPerm = {1, 0}; + SmallVector outerPerm{0, 1}; + if (isOuterTransposed != transposeOuterBlocks) + outerPerm = {1, 0}; + + // Leave the outer dimensions, like batch, unchanged by offsetting all + // outer dimensions permutations. + SmallVector offsetPerms; + for (auto i : llvm::seq(0u, outerBlockPos)) + offsetPerms.push_back(i); + for (auto perm : outerPerm) + offsetPerms.push_back(perm + outerBlockPos); + outerPerm = offsetPerms; + + FailureOr packTransposedMatmul = + packTranspose(rewriter, packOp, linalgOp, + /*maybeUnPackOp=*/nullptr, outerPerm, innerPerm); + + return packTransposedMatmul; +} + +/// Pack a matmul operation into blocked 4D layout. +FailureOr +linalg::blockPackMatmul(RewriterBase &rewriter, linalg::LinalgOp linalgOp, + const ControlBlockPackMatmulFn &controlPackMatmul) { + if (linalgOp.hasPureBufferSemantics()) + return rewriter.notifyMatchFailure(linalgOp, "require tensor semantics"); + + std::optional options = controlPackMatmul(linalgOp); + if (!options) + return rewriter.notifyMatchFailure(linalgOp, "invalid packing options"); + + if (options->blockFactors.size() != 3) + return rewriter.notifyMatchFailure(linalgOp, "require 3 tile factors"); + + SmallVector mnkTiles = + getAsOpFoldResult(rewriter.getI64ArrayAttr(options->blockFactors)); + + // If padding is disabled, make sure that dimensions can be packed cleanly. + if (!options->allowPadding && + !validateFullTilesOnDims(linalgOp, mnkTiles, options->mnkOrder)) { + return rewriter.notifyMatchFailure(linalgOp, + "expect packing full tiles only"); + } + + OpBuilder::InsertionGuard guard(rewriter); + // The op is replaced, we need to set the insertion point after it. + rewriter.setInsertionPointAfter(linalgOp); + + // Pack the matmul operation into blocked layout with two levels of + // subdivision: + // - major 2D blocks - outer dimensions, consist of minor blocks + // - minor 2D blocks - inner dimensions, consist of scalar elements + FailureOr packedMatmul = packMatmulGreedily( + rewriter, linalgOp, mnkTiles, options->mnkPaddedSizesNextMultipleOf, + options->mnkOrder); + if (failed(packedMatmul)) + return failure(); + + assert(packedMatmul->packOps.size() == 3 && + "invalid number of pack ops after matmul packing"); + assert(packedMatmul->unPackOps.size() == 1 && + "invalid number of unpack ops after matmul packing"); + + FailureOr contractDims = + inferContractionDims(packedMatmul->packedLinalgOp); + if (failed(contractDims)) + return failure(); + + auto genericOp = + dyn_cast(packedMatmul->packedLinalgOp.getOperation()); + SmallVector maps = genericOp.getIndexingMapsArray(); + + // Transpose LHS matrix according to the options. + FailureOr packedLhs = transposePackedMatmul( + rewriter, packedMatmul->packedLinalgOp, packedMatmul->packOps[0], maps[0], + contractDims->m, options->lhsTransposeOuterBlocks, + options->lhsTransposeInnerBlocks); + if (failed(packedLhs)) + return failure(); + + // Update results. + packedMatmul->packOps[0] = packedLhs->transposedPackOp; + packedMatmul->packedLinalgOp = packedLhs->transposedLinalgOp; + + // Transpose RHS matrix according to the options. + FailureOr packedRhs = transposePackedMatmul( + rewriter, packedMatmul->packedLinalgOp, packedMatmul->packOps[1], maps[1], + contractDims->k, options->rhsTransposeOuterBlocks, + options->rhsTransposeInnerBlocks); + if (failed(packedRhs)) + return failure(); + + // Update results. + packedMatmul->packOps[1] = packedRhs->transposedPackOp; + packedMatmul->packedLinalgOp = packedRhs->transposedLinalgOp; + + return packedMatmul; +} + +namespace { +template +struct BlockPackMatmul : public OpRewritePattern { + BlockPackMatmul(MLIRContext *context, ControlBlockPackMatmulFn fun, + PatternBenefit benefit = 1) + : OpRewritePattern(context, benefit), controlFn(std::move(fun)) {} + + LogicalResult matchAndRewrite(OpTy linalgOp, + PatternRewriter &rewriter) const override { + FailureOr packedMatmul = + blockPackMatmul(rewriter, linalgOp, controlFn); + if (failed(packedMatmul)) + return failure(); + return success(); + } + +private: + ControlBlockPackMatmulFn controlFn; +}; + +template <> +struct BlockPackMatmul + : public OpRewritePattern { + BlockPackMatmul(MLIRContext *context, ControlBlockPackMatmulFn fun, + PatternBenefit benefit = 1) + : OpRewritePattern(context, benefit), + controlFn(std::move(fun)) {} + + LogicalResult matchAndRewrite(linalg::GenericOp linalgOp, + PatternRewriter &rewriter) const override { + // Match suitable generics. + if (failed(linalg::detail::verifyContractionInterface( + linalgOp.getOperation()))) { + return rewriter.notifyMatchFailure(linalgOp, "not a contraction"); + } + + using MapList = ArrayRef>; + auto infer = [&](MapList m) { + return AffineMap::inferFromExprList(m, linalgOp.getContext()); + }; + + AffineExpr i, j, k; + bindDims(linalgOp->getContext(), i, j, k); + SmallVector maps = linalgOp.getIndexingMapsArray(); + + // For now, only match simple matmuls. + if (!(maps == infer({{i, k}, {k, j}, {i, j}}) || + maps == infer({{k, i}, {k, j}, {i, j}}) || + maps == infer({{i, k}, {j, k}, {i, j}}))) { + return rewriter.notifyMatchFailure(linalgOp, "not a suitable matmul"); + } + + FailureOr packedMatmul = + blockPackMatmul(rewriter, linalgOp, controlFn); + if (failed(packedMatmul)) + return failure(); + return success(); + } + +private: + ControlBlockPackMatmulFn controlFn; +}; + +/// Convert linalg matmul ops to block layout and back. +struct LinalgBlockPackMatmul + : public impl::LinalgBlockPackMatmulBase { + using LinalgBlockPackMatmulBase::LinalgBlockPackMatmulBase; + + void runOnOperation() override { + Operation *op = getOperation(); + RewritePatternSet patterns(&getContext()); + + ControlBlockPackMatmulFn controlFn = + [&](linalg::LinalgOp op) -> BlockPackMatmulOptions { + BlockPackMatmulOptions options; + options.blockFactors = SmallVector{*blockFactors}; + options.allowPadding = allowPadding; + options.mnkPaddedSizesNextMultipleOf = + SmallVector{*mnkPaddedSizesNextMultipleOf}; + if (!mnkOrder.empty()) + options.mnkOrder = SmallVector{*mnkOrder}; + options.lhsTransposeOuterBlocks = lhsTransposeOuterBlocks; + options.lhsTransposeInnerBlocks = lhsTransposeInnerBlocks; + options.rhsTransposeOuterBlocks = rhsTransposeOuterBlocks; + options.rhsTransposeInnerBlocks = rhsTransposeInnerBlocks; + return options; + }; + + linalg::populateBlockPackMatmulPatterns(patterns, controlFn); + if (failed(applyPatternsAndFoldGreedily(op, std::move(patterns)))) + return signalPassFailure(); + } +}; +} // namespace + +void linalg::populateBlockPackMatmulPatterns( + RewritePatternSet &patterns, const ControlBlockPackMatmulFn &controlFn) { + patterns.add, + BlockPackMatmul, + BlockPackMatmul, + BlockPackMatmul, + BlockPackMatmul, + BlockPackMatmul, + BlockPackMatmul>( + patterns.getContext(), controlFn); +} diff --git a/mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt b/mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt index 3b5282a09569..ed9f40089282 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt +++ b/mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt @@ -25,6 +25,7 @@ add_mlir_dialect_library(MLIRLinalgTransforms TransposeMatmul.cpp MeshShardingInterfaceImpl.cpp NamedOpConversions.cpp + BlockPackMatmul.cpp Padding.cpp Promotion.cpp RuntimeOpVerification.cpp diff --git a/mlir/test/Dialect/Linalg/block-pack-matmul-layout.mlir b/mlir/test/Dialect/Linalg/block-pack-matmul-layout.mlir new file mode 100644 index 000000000000..01ca4374da04 --- /dev/null +++ b/mlir/test/Dialect/Linalg/block-pack-matmul-layout.mlir @@ -0,0 +1,101 @@ +// RUN: mlir-opt %s -linalg-block-pack-matmul="block-factors=32,16,64 \ +// RUN: lhs-transpose-outer-blocks=false lhs-transpose-inner-blocks=false \ +// RUN: rhs-transpose-outer-blocks=true rhs-transpose-inner-blocks=true" \ +// RUN: -canonicalize | FileCheck %s --check-prefix=MMT4D + +// RUN: mlir-opt %s -linalg-block-pack-matmul="block-factors=32,16,64 \ +// RUN: lhs-transpose-outer-blocks=false lhs-transpose-inner-blocks=false \ +// RUN: rhs-transpose-outer-blocks=false rhs-transpose-inner-blocks=false" \ +// RUN: -canonicalize | FileCheck %s --check-prefix=MM4D + +// RUN: mlir-opt %s -linalg-block-pack-matmul="block-factors=32,16,64 \ +// RUN: lhs-transpose-outer-blocks=true lhs-transpose-inner-blocks=true \ +// RUN: rhs-transpose-outer-blocks=false rhs-transpose-inner-blocks=false" \ +// RUN: -canonicalize | FileCheck %s --check-prefix=MTM4D + +func.func @block_matmul( + %A: tensor<64x128xf32>, %B: tensor<128x64xf32>, %C: tensor<64x64xf32>) -> tensor<64x64xf32> { + %0 = linalg.matmul ins(%A, %B : tensor<64x128xf32>, tensor<128x64xf32>) + outs(%C : tensor<64x64xf32>) -> tensor<64x64xf32> + return %0 : tensor<64x64xf32> +} + +func.func @block_matmul_transpose_a( + %A: tensor<128x64xf32>, %B: tensor<128x64xf32>, %C: tensor<64x64xf32>) -> tensor<64x64xf32> { + %0 = linalg.matmul_transpose_a ins(%A, %B : tensor<128x64xf32>, tensor<128x64xf32>) + outs(%C : tensor<64x64xf32>) -> tensor<64x64xf32> + return %0 : tensor<64x64xf32> +} + +func.func @block_matmul_transpose_b( + %A: tensor<64x128xf32>, %B: tensor<64x128xf32>, %C: tensor<64x64xf32>) -> tensor<64x64xf32> { + %0 = linalg.matmul_transpose_b ins(%A, %B : tensor<64x128xf32>, tensor<64x128xf32>) + outs(%C : tensor<64x64xf32>) -> tensor<64x64xf32> + return %0 : tensor<64x64xf32> +} + +// MMT4D-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)> +// MMT4D-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d2, d4, d5)> +// MMT4D-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)> +// MMT4D-LABEL: func @block_matmul +// MMT4D-COUNT-3: tensor.pack +// MMT4D: linalg.generic +// MMT4D-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// MMT4D-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// MMT4D-COUNT-1: tensor.unpack +// MMT4D-LABEL: func @block_matmul_transpose_a +// MMT4D-COUNT-3: tensor.pack +// MMT4D: linalg.generic +// MMT4D-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// MMT4D-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// MMT4D-COUNT-1: tensor.unpack +// MMT4D-LABEL: func @block_matmul_transpose_b +// MMT4D-COUNT-3: tensor.pack +// MMT4D: linalg.generic +// MMT4D-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// MMT4D-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// MMT4D-COUNT-1: tensor.unpack + +// MM4D-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)> +// MM4D-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)> +// MM4D-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)> +// MM4D-LABEL: func @block_matmul +// MM4D-COUNT-3: tensor.pack +// MM4D: linalg.generic +// MM4D-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// MM4D-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// MM4D-COUNT-1: tensor.unpack +// MM4D-LABEL: func @block_matmul_transpose_a +// MM4D-COUNT-3: tensor.pack +// MM4D: linalg.generic +// MM4D-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// MM4D-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// MM4D-COUNT-1: tensor.unpack +// MM4D-LABEL: func @block_matmul_transpose_b +// MM4D-COUNT-3: tensor.pack +// MM4D: linalg.generic +// MM4D-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// MM4D-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// MM4D-COUNT-1: tensor.unpack + +// MTM4D-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d0, d5, d3)> +// MTM4D-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)> +// MTM4D-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)> +// MTM4D-LABEL: func @block_matmul +// MTM4D-COUNT-3: tensor.pack +// MTM4D: linalg.generic +// MTM4D-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// MTM4D-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// MTM4D-COUNT-1: tensor.unpack +// MTM4D-LABEL: func @block_matmul_transpose_a +// MTM4D-COUNT-3: tensor.pack +// MTM4D: linalg.generic +// MTM4D-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// MTM4D-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// MTM4D-COUNT-1: tensor.unpack +// MTM4D-LABEL: func @block_matmul_transpose_b +// MTM4D-COUNT-3: tensor.pack +// MTM4D: linalg.generic +// MTM4D-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// MTM4D-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// MTM4D-COUNT-1: tensor.unpack diff --git a/mlir/test/Dialect/Linalg/block-pack-matmul-padding.mlir b/mlir/test/Dialect/Linalg/block-pack-matmul-padding.mlir new file mode 100644 index 000000000000..9e396ba08d24 --- /dev/null +++ b/mlir/test/Dialect/Linalg/block-pack-matmul-padding.mlir @@ -0,0 +1,82 @@ +// RUN: mlir-opt %s -linalg-block-pack-matmul="block-factors=32,16,64 allow-padding=1" \ +// RUN: -canonicalize | FileCheck %s + +// RUN: mlir-opt %s -linalg-block-pack-matmul="block-factors=32,16,64 allow-padding=0" \ +// RUN: -canonicalize | FileCheck %s --check-prefix=NOPAD + +// RUN: mlir-opt %s -linalg-block-pack-matmul="block-factors=32,16,64 allow-padding=1 mnk-padded-multiples=256,512,384" \ +// RUN: -canonicalize | FileCheck %s --check-prefix=PAD-MULT + +func.func @block_matmul_padding( + %A: tensor<123x125xf32>, %B: tensor<125x124xf32>, %C: tensor<123x124xf32>) -> tensor<123x124xf32> { + %0 = linalg.matmul ins(%A, %B : tensor<123x125xf32>, tensor<125x124xf32>) + outs(%C : tensor<123x124xf32>) -> tensor<123x124xf32> + return %0 : tensor<123x124xf32> +} + +// CHECK-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)> +// CHECK-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d2, d4, d5)> +// CHECK-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)> +// CHECK-LABEL: func @block_matmul_padding( +// CHECK-SAME: %[[A:[0-9a-z]+]]: tensor<123x125xf32>, %[[B:[0-9a-z]+]]: tensor<125x124xf32>, %[[C:[0-9a-z]+]]: tensor<123x124xf32> +// CHECK-DAG: %[[ZERO:.+]] = arith.constant 0.000000e+00 : f32 +// CHECK: %[[PACK_DST_0:.+]] = tensor.empty() : tensor<4x2x32x64xf32> +// CHECK: %[[A_PACKED:.+]] = tensor.pack %[[A]] +// CHECK-SAME: padding_value(%[[ZERO]] : f32) +// CHECK-SAME: outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [32, 64] +// CHECK-SAME: into %[[PACK_DST_0]] : tensor<123x125xf32> -> tensor<4x2x32x64xf32> +// CHECK: %[[PACK_DST_1:.+]] = tensor.empty() : tensor<8x2x16x64xf32> +// CHECK: %[[B_PACKED:.+]] = tensor.pack %[[B]] +// CHECK-SAME: padding_value(%[[ZERO]] : f32) +// CHECK-SAME: outer_dims_perm = [1, 0] inner_dims_pos = [1, 0] inner_tiles = [16, 64] +// CHECK-SAME: into %[[PACK_DST_1]] : tensor<125x124xf32> -> tensor<8x2x16x64xf32> +// CHECK: %[[PACK_DST_2:.+]] = tensor.empty() : tensor<4x8x32x16xf32> +// CHECK: %[[C_PACKED:.+]] = tensor.pack %[[C]] +// CHECK-SAME: padding_value(%[[ZERO]] : f32) +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[PACK_DST_2]] : tensor<123x124xf32> -> tensor<4x8x32x16xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// CHECK-SAME: ins(%[[A_PACKED]], %[[B_PACKED]] : tensor<4x2x32x64xf32>, tensor<8x2x16x64xf32>) outs(%[[C_PACKED]] : tensor<4x8x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor<4x8x32x16xf32> -> tensor<123x124xf32> +// CHECK: return %[[RES_UNPACKED]] : tensor<123x124xf32> + +// NOPAD-LABEL: func @block_matmul_padding( +// NOPAD-SAME: %[[A:[0-9a-z]+]]: tensor<123x125xf32>, %[[B:[0-9a-z]+]]: tensor<125x124xf32>, %[[C:[0-9a-z]+]]: tensor<123x124xf32> +// NOPAD-NOT: tensor.pack +// NOPAD: linalg.matmul ins(%[[A]], %[[B]] : tensor<123x125xf32>, tensor<125x124xf32>) +// NOPAD-SAME: outs(%[[C]] : tensor<123x124xf32>) -> tensor<123x124xf32> +// NOPAD-NOT: tensor.unpack + +// PAD-MULT-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)> +// PAD-MULT-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d2, d4, d5)> +// PAD-MULT-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)> +// PAD-MULT-LABEL: func @block_matmul_padding( +// PAD-MULT-SAME: %[[A:[0-9a-z]+]]: tensor<123x125xf32>, %[[B:[0-9a-z]+]]: tensor<125x124xf32>, %[[C:[0-9a-z]+]]: tensor<123x124xf32> +// PAD-MULT-DAG: %[[ZERO:.+]] = arith.constant 0.000000e+00 : f32 +// PAD-MULT: %[[PACK_DST_0:.+]] = tensor.empty() : tensor<1x1x256x384xf32> +// PAD-MULT: %[[A_PACKED:.+]] = tensor.pack %[[A]] +// PAD-MULT-SAME: padding_value(%[[ZERO]] : f32) +// PAD-MULT-SAME: outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [256, 384] +// PAD-MULT-SAME: into %[[PACK_DST_0]] : tensor<123x125xf32> -> tensor<1x1x256x384xf32> +// PAD-MULT: %[[PACK_DST_1:.+]] = tensor.empty() : tensor<1x1x512x384xf32> +// PAD-MULT: %[[B_PACKED:.+]] = tensor.pack %[[B]] +// PAD-MULT-SAME: padding_value(%[[ZERO]] : f32) +// PAD-MULT-SAME: outer_dims_perm = [1, 0] inner_dims_pos = [1, 0] inner_tiles = [512, 384] +// PAD-MULT-SAME: into %[[PACK_DST_1]] : tensor<125x124xf32> -> tensor<1x1x512x384xf32> +// PAD-MULT: %[[PACK_DST_2:.+]] = tensor.empty() : tensor<1x1x256x512xf32> +// PAD-MULT: %[[C_PACKED:.+]] = tensor.pack %[[C]] +// PAD-MULT-SAME: padding_value(%[[ZERO]] : f32) +// PAD-MULT-SAME: inner_dims_pos = [0, 1] inner_tiles = [256, 512] +// PAD-MULT-SAME: into %[[PACK_DST_2]] : tensor<123x124xf32> -> tensor<1x1x256x512xf32> +// PAD-MULT: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// PAD-MULT-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// PAD-MULT-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// PAD-MULT-SAME: ins(%[[A_PACKED]], %[[B_PACKED]] : tensor<1x1x256x384xf32>, tensor<1x1x512x384xf32>) outs(%[[C_PACKED]] : tensor<1x1x256x512xf32>) +// PAD-MULT: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// PAD-MULT-SAME: inner_dims_pos = [0, 1] inner_tiles = [256, 512] +// PAD-MULT-SAME: into %[[C]] : tensor<1x1x256x512xf32> -> tensor<123x124xf32> +// PAD-MULT: return %[[RES_UNPACKED]] : tensor<123x124xf32> diff --git a/mlir/test/Dialect/Linalg/block-pack-matmul.mlir b/mlir/test/Dialect/Linalg/block-pack-matmul.mlir new file mode 100644 index 000000000000..cc9af913ca15 --- /dev/null +++ b/mlir/test/Dialect/Linalg/block-pack-matmul.mlir @@ -0,0 +1,478 @@ +// RUN: mlir-opt %s -linalg-block-pack-matmul=block-factors=32,16,64 -canonicalize -split-input-file | FileCheck %s + +func.func @block_matmul( + %A: tensor<128x128xf32>, %B: tensor<128x128xf32>, %C: tensor<128x128xf32>) -> tensor<128x128xf32> { + %0 = linalg.matmul ins(%A, %B : tensor<128x128xf32>, tensor<128x128xf32>) + outs(%C : tensor<128x128xf32>) -> tensor<128x128xf32> + return %0 : tensor<128x128xf32> +} + +// CHECK-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)> +// CHECK-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d2, d4, d5)> +// CHECK-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)> + +// CHECK-LABEL: func @block_matmul( +// CHECK-SAME: %[[A:[0-9a-z]+]]: tensor<128x128xf32>, %[[B:[0-9a-z]+]]: tensor<128x128xf32>, %[[C:[0-9a-z]+]]: tensor<128x128xf32> +// CHECK: %[[PACK_DST_0:.+]] = tensor.empty() : tensor<4x2x32x64xf32> +// CHECK: %[[A_PACKED:.+]] = tensor.pack %[[A]] +// CHECK-SAME: outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [32, 64] +// CHECK-SAME: into %[[PACK_DST_0]] : tensor<128x128xf32> -> tensor<4x2x32x64xf32> +// CHECK: %[[PACK_DST_1:.+]] = tensor.empty() : tensor<8x2x16x64xf32> +// CHECK: %[[B_PACKED:.+]] = tensor.pack %[[B]] +// CHECK-SAME: outer_dims_perm = [1, 0] inner_dims_pos = [1, 0] inner_tiles = [16, 64] +// CHECK-SAME: into %[[PACK_DST_1]] : tensor<128x128xf32> -> tensor<8x2x16x64xf32> +// CHECK: %[[PACK_DST_2:.+]] = tensor.empty() : tensor<4x8x32x16xf32> +// CHECK: %[[C_PACKED:.+]] = tensor.pack %[[C]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[PACK_DST_2]] : tensor<128x128xf32> -> tensor<4x8x32x16xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// CHECK-SAME: ins(%[[A_PACKED]], %[[B_PACKED]] : tensor<4x2x32x64xf32>, tensor<8x2x16x64xf32>) outs(%[[C_PACKED]] : tensor<4x8x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor<4x8x32x16xf32> -> tensor<128x128xf32> +// CHECK: return %[[RES_UNPACKED]] : tensor<128x128xf32> + +// ----- + +func.func @block_matmul_dynamic( + %A: tensor, %B: tensor, %C: tensor) -> tensor { + %0 = linalg.matmul ins(%A, %B : tensor, tensor) + outs(%C : tensor) -> tensor + return %0 : tensor +} + +// CHECK-DAG: #[[$MAP_M:.+]] = affine_map<()[s0] -> (s0 ceildiv 32)> +// CHECK-DAG: #[[$MAP_K:.+]] = affine_map<()[s0] -> (s0 ceildiv 64)> +// CHECK-DAG: #[[$MAP_N:.+]] = affine_map<()[s0] -> (s0 ceildiv 16)> +// CHECK-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)> +// CHECK-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d2, d4, d5)> +// CHECK-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)> + +// CHECK-LABEL: func @block_matmul_dynamic( +// CHECK-SAME: %[[A:[0-9a-z]+]]: tensor, %[[B:[0-9a-z]+]]: tensor, %[[C:[0-9a-z]+]]: tensor +// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index +// CHECK-DAG: %[[C1:.+]] = arith.constant 1 : index +// CHECK-DAG: %[[ZERO:.+]] = arith.constant 0.000000e+00 : f32 +// CHECK-DAG: %[[A_M:.+]] = tensor.dim %[[A]], %[[C0]] : tensor +// CHECK-DAG: %[[A_K:.+]] = tensor.dim %[[A]], %[[C1]] : tensor +// CHECK-DAG: %[[A_OUTER_TILE_M:.+]] = affine.apply #[[$MAP_M]]()[%[[A_M]]] +// CHECK-DAG: %[[A_OUTER_TILE_K:.+]] = affine.apply #[[$MAP_K]]()[%[[A_K]]] +// CHECK: %[[PACK_DST_0:.+]] = tensor.empty(%[[A_OUTER_TILE_M]], %[[A_OUTER_TILE_K]]) : tensor +// CHECK: %[[A_PACKED:.+]] = tensor.pack %[[A]] +// CHECK-SAME: padding_value(%[[ZERO]] : f32) +// CHECK-SAME: outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [32, 64] +// CHECK-SAME: into %[[PACK_DST_0]] : tensor -> tensor +// CHECK-DAG: %[[B_K:.+]] = tensor.dim %[[B]], %[[C0]] : tensor +// CHECK-DAG: %[[B_N:.+]] = tensor.dim %[[B]], %[[C1]] : tensor +// CHECK-DAG: %[[B_OUTER_TILE_K:.+]] = affine.apply #[[$MAP_K]]()[%[[B_K]]] +// CHECK-DAG: %[[B_OUTER_TILE_N:.+]] = affine.apply #[[$MAP_N]]()[%[[B_N]]] +// CHECK: %[[PACK_DST_1:.+]] = tensor.empty(%[[B_OUTER_TILE_N]], %[[B_OUTER_TILE_K]]) : tensor +// CHECK: %[[B_PACKED:.+]] = tensor.pack %[[B]] +// CHECK-SAME: padding_value(%[[ZERO]] : f32) +// CHECK-SAME: outer_dims_perm = [1, 0] inner_dims_pos = [1, 0] inner_tiles = [16, 64] +// CHECK-SAME: into %[[PACK_DST_1]] : tensor -> tensor +// CHECK-DAG: %[[C_M:.+]] = tensor.dim %[[C]], %[[C0]] : tensor +// CHECK-DAG: %[[C_N:.+]] = tensor.dim %[[C]], %[[C1]] : tensor +// CHECK-DAG: %[[C_OUTER_TILE_M:.+]] = affine.apply #[[$MAP_M]]()[%[[C_M]]] +// CHECK-DAG: %[[C_OUTER_TILE_N:.+]] = affine.apply #[[$MAP_N]]()[%[[C_N]]] +// CHECK: %[[PACK_DST_2:.+]] = tensor.empty(%[[C_OUTER_TILE_M]], %[[C_OUTER_TILE_N]]) : tensor +// CHECK: %[[C_PACKED:.+]] = tensor.pack %[[C]] +// CHECK-SAME: padding_value(%[[ZERO]] : f32) +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[PACK_DST_2]] : tensor -> tensor +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// CHECK-SAME: ins(%[[A_PACKED]], %[[B_PACKED]] : tensor, tensor) outs(%[[C_PACKED]] : tensor) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor -> tensor +// CHECK: return %[[RES_UNPACKED]] : tensor + +// ----- + +func.func @block_matmul_with_constant( + %A: tensor<128x128xf32>, %B: tensor<128x128xf32>) -> tensor<128x128xf32> { + %cst_acc = arith.constant dense<0.0> : tensor<128x128xf32> + %0 = linalg.matmul ins(%A, %B : tensor<128x128xf32>, tensor<128x128xf32>) + outs(%cst_acc : tensor<128x128xf32>) -> tensor<128x128xf32> + return %0 : tensor<128x128xf32> +} + +// CHECK-LABEL: func @block_matmul_with_constant( +// CHECK-SAME: %[[A:[0-9a-z]+]]: tensor<128x128xf32>, %[[B:[0-9a-z]+]]: tensor<128x128xf32> +// CHECK-DAG: %[[CST_ACC_PACKED:.+]] = arith.constant dense<0.000000e+00> : tensor<4x8x32x16xf32> +// CHECK-DAG: %[[RES_DST:.+]] = arith.constant dense<0.000000e+00> : tensor<128x128xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: ins({{.*}} : tensor<4x2x32x64xf32>, tensor<8x2x16x64xf32>) outs(%[[CST_ACC_PACKED]] : tensor<4x8x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[RES_DST]] : tensor<4x8x32x16xf32> -> tensor<128x128xf32> +// CHECK: return %[[RES_UNPACKED]] : tensor<128x128xf32> + +// ----- + +func.func @block_matmul_with_producer( + %A: tensor<128x128xf32>, %B: tensor<128x128xf32>, %C: tensor<128x128xf32>) -> tensor<128x128xf32> { + %cst = arith.constant 0.0 : f32 + %acc = linalg.fill ins(%cst : f32) outs(%C : tensor<128x128xf32>) -> tensor<128x128xf32> + %1 = linalg.matmul ins(%A, %B : tensor<128x128xf32>, tensor<128x128xf32>) + outs(%acc : tensor<128x128xf32>) -> tensor<128x128xf32> + return %1 : tensor<128x128xf32> +} + +// CHECK-LABEL: func @block_matmul_with_producer( +// CHECK-SAME: %[[A:[0-9a-z]+]]: tensor<128x128xf32>, %[[B:[0-9a-z]+]]: tensor<128x128xf32>, %[[C:[0-9a-z]+]]: tensor<128x128xf32> +// CHECK-DAG: %[[C0:.+]] = arith.constant 0.000000e+00 : f32 +// CHECK: %[[FILL_DST_PACKED:.+]] = tensor.empty() : tensor<4x8x32x16xf32> +// CHECK: %[[ACC_PACKED:.+]] = linalg.fill ins(%[[C0]] : f32) outs(%[[FILL_DST_PACKED]] : tensor<4x8x32x16xf32>) -> tensor<4x8x32x16xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: ins({{.*}} : tensor<4x2x32x64xf32>, tensor<8x2x16x64xf32>) outs(%[[ACC_PACKED]] : tensor<4x8x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor<4x8x32x16xf32> -> tensor<128x128xf32> +// CHECK: return %[[RES_UNPACKED]] : tensor<128x128xf32> + +// ----- + +func.func @block_matmul_with_consumer( + %A: tensor<128x128xf32>, %B: tensor<128x128xf32>, %C: tensor<128x128xf32>, %D: tensor<128x128xf32>) -> tensor<128x128xf32> { + %0 = tensor.empty() : tensor<128x128xf32> + %1 = linalg.matmul ins(%A, %B : tensor<128x128xf32>, tensor<128x128xf32>) + outs(%C : tensor<128x128xf32>) -> tensor<128x128xf32> + %2 = linalg.add ins(%1, %D : tensor<128x128xf32>, tensor<128x128xf32>) + outs(%0 : tensor<128x128xf32>) -> tensor<128x128xf32> + return %2 : tensor<128x128xf32> +} + +// CHECK-LABEL: func @block_matmul_with_consumer( +// CHECK-SAME: %[[A:[0-9a-z]+]]: tensor<128x128xf32>, %[[B:[0-9a-z]+]]: tensor<128x128xf32>, %[[C:[0-9a-z]+]]: tensor<128x128xf32>, %[[D:[0-9a-z]+]]: tensor<128x128xf32> +// CHECK-DAG: %[[RES_DST:.+]] = tensor.empty() : tensor<128x128xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: outs({{.*}} : tensor<4x8x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor<4x8x32x16xf32> -> tensor<128x128xf32> +// CHECK: %[[ADD_RES:.+]] = linalg.add +// CHECK-SAME: ins(%[[RES_UNPACKED]], %[[D]] : tensor<128x128xf32>, tensor<128x128xf32>) outs(%[[RES_DST]] : tensor<128x128xf32>) +// CHECK: return %[[ADD_RES]] : tensor<128x128xf32> + +// ----- + +func.func @block_batch_matmul( + %A: tensor<512x64x128xf32>, %B: tensor<512x128x64xf32>, %C: tensor<512x64x64xf32>) -> tensor<512x64x64xf32> { + %0 = linalg.batch_matmul ins(%A, %B : tensor<512x64x128xf32>, tensor<512x128x64xf32>) + outs(%C : tensor<512x64x64xf32>) -> tensor<512x64x64xf32> + return %0 : tensor<512x64x64xf32> +} + +// CHECK-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1, d3, d4, d6)> +// CHECK-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d2, d3, d5, d6)> +// CHECK-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1, d2, d4, d5)> + +// CHECK-LABEL: func @block_batch_matmul( +// CHECK-SAME: %[[A:.+]]: tensor<512x64x128xf32>, %[[B:.+]]: tensor<512x128x64xf32>, %[[C:.+]]: tensor<512x64x64xf32> +// CHECK: %[[PACK_DST_0:.+]] = tensor.empty() : tensor<512x2x2x32x64xf32> +// CHECK: %[[A_PACKED:.+]] = tensor.pack %[[A]] +// CHECK-SAME: outer_dims_perm = [0, 1, 2] inner_dims_pos = [1, 2] inner_tiles = [32, 64] +// CHECK-SAME: into %[[PACK_DST_0]] : tensor<512x64x128xf32> -> tensor<512x2x2x32x64xf32> +// CHECK: %[[PACK_DST_1:.+]] = tensor.empty() : tensor<512x4x2x16x64xf32> +// CHECK: %[[B_PACKED:.+]] = tensor.pack %[[B]] +// CHECK-SAME: outer_dims_perm = [0, 2, 1] inner_dims_pos = [2, 1] inner_tiles = [16, 64] +// CHECK-SAME: into %[[PACK_DST_1]] : tensor<512x128x64xf32> -> tensor<512x4x2x16x64xf32> +// CHECK: %[[PACK_DST_2:.+]] = tensor.empty() : tensor<512x2x4x32x16xf32> +// CHECK: %[[C_PACKED:.+]] = tensor.pack %[[C]] +// CHECK-SAME: inner_dims_pos = [1, 2] inner_tiles = [32, 16] +// CHECK-SAME: into %[[PACK_DST_2]] : tensor<512x64x64xf32> -> tensor<512x2x4x32x16xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// CHECK-SAME: ins(%[[A_PACKED]], %[[B_PACKED]] : tensor<512x2x2x32x64xf32>, tensor<512x4x2x16x64xf32>) outs(%[[C_PACKED]] : tensor<512x2x4x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [1, 2] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor<512x2x4x32x16xf32> -> tensor<512x64x64xf32> +// CHECK: return %[[RES_UNPACKED]] : tensor<512x64x64xf32> + +// ----- + +func.func @block_matmul_transpose_a( + %A: tensor<128x64xf32>, %B: tensor<128x64xf32>, %C: tensor<64x64xf32>) -> tensor<64x64xf32> { + %0 = linalg.matmul_transpose_a ins(%A, %B : tensor<128x64xf32>, tensor<128x64xf32>) + outs(%C : tensor<64x64xf32>) -> tensor<64x64xf32> + return %0 : tensor<64x64xf32> +} + +// CHECK-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)> +// CHECK-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d2, d4, d5)> +// CHECK-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)> + +// CHECK-LABEL: func @block_matmul_transpose_a( +// CHECK-SAME: %[[A:[0-9a-z]+]]: tensor<128x64xf32>, %[[B:[0-9a-z]+]]: tensor<128x64xf32>, %[[C:[0-9a-z]+]]: tensor<64x64xf32> +// CHECK: %[[PACK_DST_0:.+]] = tensor.empty() : tensor<2x2x32x64xf32> +// CHECK: %[[A_PACKED:.+]] = tensor.pack %[[A]] +// CHECK-SAME: outer_dims_perm = [1, 0] inner_dims_pos = [1, 0] inner_tiles = [32, 64] +// CHECK-SAME: into %[[PACK_DST_0]] : tensor<128x64xf32> -> tensor<2x2x32x64xf32> +// CHECK: %[[PACK_DST_1:.+]] = tensor.empty() : tensor<4x2x16x64xf32> +// CHECK: %[[B_PACKED:.+]] = tensor.pack %[[B]] +// CHECK-SAME: outer_dims_perm = [1, 0] inner_dims_pos = [1, 0] inner_tiles = [16, 64] +// CHECK-SAME: into %[[PACK_DST_1]] : tensor<128x64xf32> -> tensor<4x2x16x64xf32> +// CHECK: %[[PACK_DST_2:.+]] = tensor.empty() : tensor<2x4x32x16xf32> +// CHECK: %[[C_PACKED:.+]] = tensor.pack %[[C]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[PACK_DST_2]] : tensor<64x64xf32> -> tensor<2x4x32x16xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// CHECK-SAME: ins(%[[A_PACKED]], %[[B_PACKED]] : tensor<2x2x32x64xf32>, tensor<4x2x16x64xf32>) outs(%[[C_PACKED]] : tensor<2x4x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor<2x4x32x16xf32> -> tensor<64x64xf32> +// CHECK: return %[[RES_UNPACKED]] : tensor<64x64xf32> + +// ----- + +func.func @block_batch_matmul_transpose_a( + %A: tensor<512x128x64xf32>, %B: tensor<512x128x64xf32>, %C: tensor<512x64x64xf32>) -> tensor<512x64x64xf32> { + %0 = linalg.batch_matmul_transpose_a ins(%A, %B : tensor<512x128x64xf32>, tensor<512x128x64xf32>) + outs(%C : tensor<512x64x64xf32>) -> tensor<512x64x64xf32> + return %0 : tensor<512x64x64xf32> +} + +// CHECK-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1, d3, d4, d6)> +// CHECK-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d2, d3, d5, d6)> +// CHECK-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1, d2, d4, d5)> + +// CHECK-LABEL: func @block_batch_matmul_transpose_a( +// CHECK-SAME: %[[A:.+]]: tensor<512x128x64xf32>, %[[B:.+]]: tensor<512x128x64xf32>, %[[C:.+]]: tensor<512x64x64xf32> +// CHECK: %[[PACK_DST_0:.+]] = tensor.empty() : tensor<512x2x2x32x64xf32> +// CHECK: %[[A_PACKED:.+]] = tensor.pack %[[A]] +// CHECK-SAME: outer_dims_perm = [0, 2, 1] inner_dims_pos = [2, 1] inner_tiles = [32, 64] +// CHECK-SAME: into %[[PACK_DST_0]] : tensor<512x128x64xf32> -> tensor<512x2x2x32x64xf32> +// CHECK: %[[PACK_DST_1:.+]] = tensor.empty() : tensor<512x4x2x16x64xf32> +// CHECK: %[[B_PACKED:.+]] = tensor.pack %[[B]] +// CHECK-SAME: outer_dims_perm = [0, 2, 1] inner_dims_pos = [2, 1] inner_tiles = [16, 64] +// CHECK-SAME: into %[[PACK_DST_1]] : tensor<512x128x64xf32> -> tensor<512x4x2x16x64xf32> +// CHECK: %[[PACK_DST_2:.+]] = tensor.empty() : tensor<512x2x4x32x16xf32> +// CHECK: %[[C_PACKED:.+]] = tensor.pack %[[C]] +// CHECK-SAME: inner_dims_pos = [1, 2] inner_tiles = [32, 16] +// CHECK-SAME: into %[[PACK_DST_2]] : tensor<512x64x64xf32> -> tensor<512x2x4x32x16xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// CHECK-SAME: ins(%[[A_PACKED]], %[[B_PACKED]] : tensor<512x2x2x32x64xf32>, tensor<512x4x2x16x64xf32>) outs(%[[C_PACKED]] : tensor<512x2x4x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [1, 2] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor<512x2x4x32x16xf32> -> tensor<512x64x64xf32> +// CHECK: return %[[RES_UNPACKED]] : tensor<512x64x64xf32> + +// ----- + +func.func @block_matmul_transpose_b( + %A: tensor<64x128xf32>, %B: tensor<64x128xf32>, %C: tensor<64x64xf32>) -> tensor<64x64xf32> { + %0 = linalg.matmul_transpose_b ins(%A, %B : tensor<64x128xf32>, tensor<64x128xf32>) + outs(%C : tensor<64x64xf32>) -> tensor<64x64xf32> + return %0 : tensor<64x64xf32> +} + +// CHECK-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)> +// CHECK-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d2, d4, d5)> +// CHECK-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)> + +// CHECK-LABEL: func @block_matmul_transpose_b( +// CHECK-SAME: %[[A:[0-9a-z]+]]: tensor<64x128xf32>, %[[B:[0-9a-z]+]]: tensor<64x128xf32>, %[[C:[0-9a-z]+]]: tensor<64x64xf32> +// CHECK: %[[PACK_DST_0:.+]] = tensor.empty() : tensor<2x2x32x64xf32> +// CHECK: %[[A_PACKED:.+]] = tensor.pack %[[A]] +// CHECK-SAME: outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [32, 64] +// CHECK-SAME: into %[[PACK_DST_0]] : tensor<64x128xf32> -> tensor<2x2x32x64xf32> +// CHECK: %[[PACK_DST_1:.+]] = tensor.empty() : tensor<4x2x16x64xf32> +// CHECK: %[[B_PACKED:.+]] = tensor.pack %[[B]] +// CHECK-SAME: outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 64] +// CHECK-SAME: into %[[PACK_DST_1]] : tensor<64x128xf32> -> tensor<4x2x16x64xf32> +// CHECK: %[[PACK_DST_2:.+]] = tensor.empty() : tensor<2x4x32x16xf32> +// CHECK: %[[C_PACKED:.+]] = tensor.pack %[[C]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[PACK_DST_2]] : tensor<64x64xf32> -> tensor<2x4x32x16xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// CHECK-SAME: ins(%[[A_PACKED]], %[[B_PACKED]] : tensor<2x2x32x64xf32>, tensor<4x2x16x64xf32>) outs(%[[C_PACKED]] : tensor<2x4x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor<2x4x32x16xf32> -> tensor<64x64xf32> +// CHECK: return %[[RES_UNPACKED]] : tensor<64x64xf32> + +// ----- + +func.func @block_batch_matmul_transpose_b( + %A: tensor<512x64x128xf32>, %B: tensor<512x64x128xf32>, %C: tensor<512x64x64xf32>) -> tensor<512x64x64xf32> { + %0 = linalg.batch_matmul_transpose_b ins(%A, %B : tensor<512x64x128xf32>, tensor<512x64x128xf32>) + outs(%C : tensor<512x64x64xf32>) -> tensor<512x64x64xf32> + return %0 : tensor<512x64x64xf32> +} + +// CHECK-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1, d3, d4, d6)> +// CHECK-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d2, d3, d5, d6)> +// CHECK-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1, d2, d4, d5)> + +// CHECK-LABEL: func @block_batch_matmul_transpose_b( +// CHECK-SAME: %[[A:.+]]: tensor<512x64x128xf32>, %[[B:.+]]: tensor<512x64x128xf32>, %[[C:.+]]: tensor<512x64x64xf32> +// CHECK: %[[PACK_DST_0:.+]] = tensor.empty() : tensor<512x2x2x32x64xf32> +// CHECK: %[[A_PACKED:.+]] = tensor.pack %[[A]] +// CHECK-SAME: outer_dims_perm = [0, 1, 2] inner_dims_pos = [1, 2] inner_tiles = [32, 64] +// CHECK-SAME: into %[[PACK_DST_0]] : tensor<512x64x128xf32> -> tensor<512x2x2x32x64xf32> +// CHECK: %[[PACK_DST_1:.+]] = tensor.empty() : tensor<512x4x2x16x64xf32> +// CHECK: %[[B_PACKED:.+]] = tensor.pack %[[B]] +// CHECK-SAME: outer_dims_perm = [0, 1, 2] inner_dims_pos = [1, 2] inner_tiles = [16, 64] +// CHECK-SAME: into %[[PACK_DST_1]] : tensor<512x64x128xf32> -> tensor<512x4x2x16x64xf32> +// CHECK: %[[PACK_DST_2:.+]] = tensor.empty() : tensor<512x2x4x32x16xf32> +// CHECK: %[[C_PACKED:.+]] = tensor.pack %[[C]] +// CHECK-SAME: inner_dims_pos = [1, 2] inner_tiles = [32, 16] +// CHECK-SAME: into %[[PACK_DST_2]] : tensor<512x64x64xf32> -> tensor<512x2x4x32x16xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// CHECK-SAME: ins(%[[A_PACKED]], %[[B_PACKED]] : tensor<512x2x2x32x64xf32>, tensor<512x4x2x16x64xf32>) outs(%[[C_PACKED]] : tensor<512x2x4x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [1, 2] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor<512x2x4x32x16xf32> -> tensor<512x64x64xf32> +// CHECK: return %[[RES_UNPACKED]] : tensor<512x64x64xf32> + +// ----- + +#map = affine_map<(d0, d1, d2) -> (d0, d2)> +#map1 = affine_map<(d0, d1, d2) -> (d2, d1)> +#map2 = affine_map<(d0, d1, d2) -> (d0, d1)> + +func.func @block_generic_matmul( + %A: tensor<128x128xf32>, %B: tensor<128x128xf32>, %C: tensor<128x128xf32>) -> tensor<128x128xf32> { + %0 = linalg.generic {indexing_maps = [#map, #map1, #map2], iterator_types = ["parallel", "parallel", "reduction"]} + ins(%A, %B : tensor<128x128xf32>, tensor<128x128xf32>) + outs(%C : tensor<128x128xf32>) { + ^bb0(%in: f32, %in_0: f32, %out: f32): + %1 = arith.mulf %in, %in_0 : f32 + %2 = arith.addf %out, %1 : f32 + linalg.yield %2 : f32 + } -> tensor<128x128xf32> + return %0 : tensor<128x128xf32> +} + +// CHECK-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)> +// CHECK-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d2, d4, d5)> +// CHECK-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)> + +// CHECK-LABEL: func @block_generic_matmul( +// CHECK-SAME: %[[A:[0-9a-z]+]]: tensor<128x128xf32>, %[[B:[0-9a-z]+]]: tensor<128x128xf32>, %[[C:[0-9a-z]+]]: tensor<128x128xf32> +// CHECK: %[[PACK_DST_0:.+]] = tensor.empty() : tensor<4x2x32x64xf32> +// CHECK: %[[A_PACKED:.+]] = tensor.pack %[[A]] +// CHECK-SAME: outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [32, 64] +// CHECK-SAME: into %[[PACK_DST_0]] : tensor<128x128xf32> -> tensor<4x2x32x64xf32> +// CHECK: %[[PACK_DST_1:.+]] = tensor.empty() : tensor<8x2x16x64xf32> +// CHECK: %[[B_PACKED:.+]] = tensor.pack %[[B]] +// CHECK-SAME: outer_dims_perm = [1, 0] inner_dims_pos = [1, 0] inner_tiles = [16, 64] +// CHECK-SAME: into %[[PACK_DST_1]] : tensor<128x128xf32> -> tensor<8x2x16x64xf32> +// CHECK: %[[PACK_DST_2:.+]] = tensor.empty() : tensor<4x8x32x16xf32> +// CHECK: %[[C_PACKED:.+]] = tensor.pack %[[C]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[PACK_DST_2]] : tensor<128x128xf32> -> tensor<4x8x32x16xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// CHECK-SAME: ins(%[[A_PACKED]], %[[B_PACKED]] : tensor<4x2x32x64xf32>, tensor<8x2x16x64xf32>) outs(%[[C_PACKED]] : tensor<4x8x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor<4x8x32x16xf32> -> tensor<128x128xf32> +// CHECK: return %[[RES_UNPACKED]] : tensor<128x128xf32> + +// ----- + +#map = affine_map<(d0, d1, d2) -> (d2, d0)> +#map1 = affine_map<(d0, d1, d2) -> (d2, d1)> +#map2 = affine_map<(d0, d1, d2) -> (d0, d1)> + +func.func @block_generic_matmul_transpose_a( + %A: tensor<128x64xf32>, %B: tensor<128x64xf32>, %C: tensor<64x64xf32>) -> tensor<64x64xf32> { + %0 = linalg.generic {indexing_maps = [#map, #map1, #map2], iterator_types = ["parallel", "parallel", "reduction"]} + ins(%A, %B : tensor<128x64xf32>, tensor<128x64xf32>) + outs(%C : tensor<64x64xf32>) { + ^bb0(%in: f32, %in_0: f32, %out: f32): + %1 = arith.mulf %in, %in_0 : f32 + %2 = arith.addf %out, %1 : f32 + linalg.yield %2 : f32 + } -> tensor<64x64xf32> + return %0 : tensor<64x64xf32> +} + +// CHECK-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)> +// CHECK-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d2, d4, d5)> +// CHECK-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)> + +// CHECK-LABEL: func @block_generic_matmul_transpose_a( +// CHECK-SAME: %[[A:[0-9a-z]+]]: tensor<128x64xf32>, %[[B:[0-9a-z]+]]: tensor<128x64xf32>, %[[C:[0-9a-z]+]]: tensor<64x64xf32> +// CHECK: %[[PACK_DST_0:.+]] = tensor.empty() : tensor<2x2x32x64xf32> +// CHECK: %[[A_PACKED:.+]] = tensor.pack %[[A]] +// CHECK-SAME: outer_dims_perm = [1, 0] inner_dims_pos = [1, 0] inner_tiles = [32, 64] +// CHECK-SAME: into %[[PACK_DST_0]] : tensor<128x64xf32> -> tensor<2x2x32x64xf32> +// CHECK: %[[PACK_DST_1:.+]] = tensor.empty() : tensor<4x2x16x64xf32> +// CHECK: %[[B_PACKED:.+]] = tensor.pack %[[B]] +// CHECK-SAME: outer_dims_perm = [1, 0] inner_dims_pos = [1, 0] inner_tiles = [16, 64] +// CHECK-SAME: into %[[PACK_DST_1]] : tensor<128x64xf32> -> tensor<4x2x16x64xf32> +// CHECK: %[[PACK_DST_2:.+]] = tensor.empty() : tensor<2x4x32x16xf32> +// CHECK: %[[C_PACKED:.+]] = tensor.pack %[[C]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[PACK_DST_2]] : tensor<64x64xf32> -> tensor<2x4x32x16xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// CHECK-SAME: ins(%[[A_PACKED]], %[[B_PACKED]] : tensor<2x2x32x64xf32>, tensor<4x2x16x64xf32>) outs(%[[C_PACKED]] : tensor<2x4x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor<2x4x32x16xf32> -> tensor<64x64xf32> +// CHECK: return %[[RES_UNPACKED]] : tensor<64x64xf32> + +// ----- + +#map = affine_map<(d0, d1, d2) -> (d0, d2)> +#map1 = affine_map<(d0, d1, d2) -> (d1, d2)> +#map2 = affine_map<(d0, d1, d2) -> (d0, d1)> + +func.func @block_generic_matmul_transpose_b( + %A: tensor<64x128xf32>, %B: tensor<64x128xf32>, %C: tensor<64x64xf32>) -> tensor<64x64xf32> { + %0 = linalg.generic {indexing_maps = [#map, #map1, #map2], iterator_types = ["parallel", "parallel", "reduction"]} + ins(%A, %B : tensor<64x128xf32>, tensor<64x128xf32>) + outs(%C : tensor<64x64xf32>) { + ^bb0(%in: f32, %in_0: f32, %out: f32): + %1 = arith.mulf %in, %in_0 : f32 + %2 = arith.addf %out, %1 : f32 + linalg.yield %2 : f32 + } -> tensor<64x64xf32> + return %0 : tensor<64x64xf32> +} + +// CHECK-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)> +// CHECK-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d2, d4, d5)> +// CHECK-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)> + +// CHECK-LABEL: func @block_generic_matmul_transpose_b( +// CHECK-SAME: %[[A:[0-9a-z]+]]: tensor<64x128xf32>, %[[B:[0-9a-z]+]]: tensor<64x128xf32>, %[[C:[0-9a-z]+]]: tensor<64x64xf32> +// CHECK: %[[PACK_DST_0:.+]] = tensor.empty() : tensor<2x2x32x64xf32> +// CHECK: %[[A_PACKED:.+]] = tensor.pack %[[A]] +// CHECK-SAME: outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [32, 64] +// CHECK-SAME: into %[[PACK_DST_0]] : tensor<64x128xf32> -> tensor<2x2x32x64xf32> +// CHECK: %[[PACK_DST_1:.+]] = tensor.empty() : tensor<4x2x16x64xf32> +// CHECK: %[[B_PACKED:.+]] = tensor.pack %[[B]] +// CHECK-SAME: outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 64] +// CHECK-SAME: into %[[PACK_DST_1]] : tensor<64x128xf32> -> tensor<4x2x16x64xf32> +// CHECK: %[[PACK_DST_2:.+]] = tensor.empty() : tensor<2x4x32x16xf32> +// CHECK: %[[C_PACKED:.+]] = tensor.pack %[[C]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[PACK_DST_2]] : tensor<64x64xf32> -> tensor<2x4x32x16xf32> +// CHECK: %[[GEMM_RES_PACKED:.+]] = linalg.generic +// CHECK-SAME: indexing_maps = [#[[$MAP]], #[[$MAP1]], #[[$MAP2]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"] +// CHECK-SAME: ins(%[[A_PACKED]], %[[B_PACKED]] : tensor<2x2x32x64xf32>, tensor<4x2x16x64xf32>) outs(%[[C_PACKED]] : tensor<2x4x32x16xf32>) +// CHECK: %[[RES_UNPACKED:.+]] = tensor.unpack %[[GEMM_RES_PACKED]] +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [32, 16] +// CHECK-SAME: into %[[C]] : tensor<2x4x32x16xf32> -> tensor<64x64xf32> +// CHECK: return %[[RES_UNPACKED]] : tensor<64x64xf32> -- GitLab From 317e6ff6290c4c3065cb79c3eaf52f171e40cdfd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Danny=20M=C3=B6sch?= Date: Thu, 9 May 2024 19:07:43 +0200 Subject: [PATCH 173/328] [NFC] Move parameter into field (#91065) Fixes #89194. --- llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h index 06f1396c06fe..d8e41fe92258 100644 --- a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h +++ b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h @@ -97,13 +97,15 @@ struct LTOCodeGenerator { void setFileType(CodeGenFileType FT) { Config.CGFileType = FT; } void setCpu(StringRef MCpu) { Config.CPU = std::string(MCpu); } - void setAttrs(std::vector MAttrs) { Config.MAttrs = MAttrs; } + void setAttrs(std::vector MAttrs) { + Config.MAttrs = std::move(MAttrs); + } void setOptLevel(unsigned OptLevel); void setShouldInternalize(bool Value) { ShouldInternalize = Value; } void setShouldEmbedUselists(bool Value) { ShouldEmbedUselists = Value; } void setSaveIRBeforeOptPath(std::string Value) { - SaveIRBeforeOptPath = Value; + SaveIRBeforeOptPath = std::move(Value); } /// Restore linkage of globals -- GitLab From e1f279e92ddda4e4fdd6fff165b950d0879fa41e Mon Sep 17 00:00:00 2001 From: lntue <35648136+lntue@users.noreply.github.com> Date: Thu, 9 May 2024 13:10:43 -0400 Subject: [PATCH 174/328] [libc] Use __builtin_fma(f) by default if LIBC_TARGET_CPU_HAS_FMA is defined. (#91535) --- libc/src/__support/FPUtil/FMA.h | 26 +++++---- libc/src/__support/FPUtil/aarch64/FMA.h | 50 ----------------- libc/src/__support/FPUtil/gpu/FMA.h | 36 ------------ libc/src/__support/FPUtil/riscv/FMA.h | 54 ------------------ libc/src/__support/FPUtil/x86_64/FMA.h | 55 ------------------- .../llvm-project-overlay/libc/BUILD.bazel | 8 --- 6 files changed, 16 insertions(+), 213 deletions(-) delete mode 100644 libc/src/__support/FPUtil/aarch64/FMA.h delete mode 100644 libc/src/__support/FPUtil/gpu/FMA.h delete mode 100644 libc/src/__support/FPUtil/riscv/FMA.h delete mode 100644 libc/src/__support/FPUtil/x86_64/FMA.h diff --git a/libc/src/__support/FPUtil/FMA.h b/libc/src/__support/FPUtil/FMA.h index 0e1ede02d5cc..c277da49538b 100644 --- a/libc/src/__support/FPUtil/FMA.h +++ b/libc/src/__support/FPUtil/FMA.h @@ -9,25 +9,31 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_FMA_H #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_FMA_H +#include "src/__support/CPP/type_traits.h" #include "src/__support/macros/properties/architectures.h" #include "src/__support/macros/properties/cpu_features.h" // LIBC_TARGET_CPU_HAS_FMA #if defined(LIBC_TARGET_CPU_HAS_FMA) -#if defined(LIBC_TARGET_ARCH_IS_X86_64) -#include "x86_64/FMA.h" -#elif defined(LIBC_TARGET_ARCH_IS_AARCH64) -#include "aarch64/FMA.h" -#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV) -#include "riscv/FMA.h" -#elif defined(LIBC_TARGET_ARCH_IS_GPU) -#include "gpu/FMA.h" -#endif +namespace LIBC_NAMESPACE { +namespace fputil { + +template +LIBC_INLINE cpp::enable_if_t, T> fma(T x, T y, T z) { + return __builtin_fmaf(x, y, z); +} + +template +LIBC_INLINE cpp::enable_if_t, T> fma(T x, T y, T z) { + return __builtin_fma(x, y, z); +} + +} // namespace fputil +} // namespace LIBC_NAMESPACE #else // FMA instructions are not available #include "generic/FMA.h" -#include "src/__support/CPP/type_traits.h" namespace LIBC_NAMESPACE { namespace fputil { diff --git a/libc/src/__support/FPUtil/aarch64/FMA.h b/libc/src/__support/FPUtil/aarch64/FMA.h deleted file mode 100644 index 6254a0673ff4..000000000000 --- a/libc/src/__support/FPUtil/aarch64/FMA.h +++ /dev/null @@ -1,50 +0,0 @@ -//===-- Aarch64 implementations of the fma function -------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_AARCH64_FMA_H -#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_AARCH64_FMA_H - -#include "src/__support/macros/attributes.h" // LIBC_INLINE -#include "src/__support/macros/properties/architectures.h" -#include "src/__support/macros/properties/cpu_features.h" // LIBC_TARGET_CPU_HAS_FMA - -#if !defined(LIBC_TARGET_ARCH_IS_AARCH64) -#error "Invalid include" -#endif - -#if !defined(LIBC_TARGET_CPU_HAS_FMA) -#error "FMA instructions are not supported" -#endif - -#include "src/__support/CPP/type_traits.h" - -namespace LIBC_NAMESPACE { -namespace fputil { - -template -LIBC_INLINE cpp::enable_if_t, T> fma(T x, T y, T z) { - float result; - LIBC_INLINE_ASM("fmadd %s0, %s1, %s2, %s3\n\t" - : "=w"(result) - : "w"(x), "w"(y), "w"(z)); - return result; -} - -template -LIBC_INLINE cpp::enable_if_t, T> fma(T x, T y, T z) { - double result; - LIBC_INLINE_ASM("fmadd %d0, %d1, %d2, %d3\n\t" - : "=w"(result) - : "w"(x), "w"(y), "w"(z)); - return result; -} - -} // namespace fputil -} // namespace LIBC_NAMESPACE - -#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_AARCH64_FMA_H diff --git a/libc/src/__support/FPUtil/gpu/FMA.h b/libc/src/__support/FPUtil/gpu/FMA.h deleted file mode 100644 index ef1cd26a72dd..000000000000 --- a/libc/src/__support/FPUtil/gpu/FMA.h +++ /dev/null @@ -1,36 +0,0 @@ -//===-- GPU implementations of the fma function -----------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_GPU_FMA_H -#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_GPU_FMA_H - -#include "src/__support/CPP/type_traits.h" - -// These intrinsics map to the FMA instructions in the target ISA for the GPU. -// The default rounding mode generated from these will be to the nearest even. -#if !__has_builtin(__builtin_fma) || !__has_builtin(__builtin_fmaf) -#error "FMA builtins must be defined"); -#endif - -namespace LIBC_NAMESPACE { -namespace fputil { - -template -LIBC_INLINE cpp::enable_if_t, T> fma(T x, T y, T z) { - return __builtin_fmaf(x, y, z); -} - -template -LIBC_INLINE cpp::enable_if_t, T> fma(T x, T y, T z) { - return __builtin_fma(x, y, z); -} - -} // namespace fputil -} // namespace LIBC_NAMESPACE - -#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_GPU_FMA_H diff --git a/libc/src/__support/FPUtil/riscv/FMA.h b/libc/src/__support/FPUtil/riscv/FMA.h deleted file mode 100644 index f01962174f16..000000000000 --- a/libc/src/__support/FPUtil/riscv/FMA.h +++ /dev/null @@ -1,54 +0,0 @@ -//===-- RISCV implementations of the fma function ---------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FMA_H -#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FMA_H - -#include "src/__support/macros/attributes.h" // LIBC_INLINE -#include "src/__support/macros/properties/architectures.h" -#include "src/__support/macros/properties/cpu_features.h" // LIBC_TARGET_CPU_HAS_FMA - -#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV) -#error "Invalid include" -#endif - -#if !defined(LIBC_TARGET_CPU_HAS_FMA) -#error "FMA instructions are not supported" -#endif - -#include "src/__support/CPP/type_traits.h" - -namespace LIBC_NAMESPACE { -namespace fputil { - -#ifdef __riscv_flen -template -LIBC_INLINE cpp::enable_if_t, T> fma(T x, T y, T z) { - float result; - LIBC_INLINE_ASM("fmadd.s %0, %1, %2, %3\n\t" - : "=f"(result) - : "f"(x), "f"(y), "f"(z)); - return result; -} - -#if __riscv_flen >= 64 -template -LIBC_INLINE cpp::enable_if_t, T> fma(T x, T y, T z) { - double result; - LIBC_INLINE_ASM("fmadd.d %0, %1, %2, %3\n\t" - : "=f"(result) - : "f"(x), "f"(y), "f"(z)); - return result; -} -#endif // __riscv_flen >= 64 -#endif // __riscv_flen - -} // namespace fputil -} // namespace LIBC_NAMESPACE - -#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FMA_H diff --git a/libc/src/__support/FPUtil/x86_64/FMA.h b/libc/src/__support/FPUtil/x86_64/FMA.h deleted file mode 100644 index 91ef7f96ff4d..000000000000 --- a/libc/src/__support/FPUtil/x86_64/FMA.h +++ /dev/null @@ -1,55 +0,0 @@ -//===-- x86_64 implementations of the fma function --------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_X86_64_FMA_H -#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_X86_64_FMA_H - -#include "src/__support/macros/attributes.h" // LIBC_INLINE -#include "src/__support/macros/properties/architectures.h" -#include "src/__support/macros/properties/cpu_features.h" // LIBC_TARGET_CPU_HAS_FMA - -#if !defined(LIBC_TARGET_ARCH_IS_X86_64) -#error "Invalid include" -#endif - -#if !defined(LIBC_TARGET_CPU_HAS_FMA) -#error "FMA instructions are not supported" -#endif - -#include "src/__support/CPP/type_traits.h" -#include - -namespace LIBC_NAMESPACE { -namespace fputil { - -template -LIBC_INLINE cpp::enable_if_t, T> fma(T x, T y, T z) { - float result; - __m128 xmm = _mm_load_ss(&x); // NOLINT - __m128 ymm = _mm_load_ss(&y); // NOLINT - __m128 zmm = _mm_load_ss(&z); // NOLINT - __m128 r = _mm_fmadd_ss(xmm, ymm, zmm); // NOLINT - _mm_store_ss(&result, r); // NOLINT - return result; -} - -template -LIBC_INLINE cpp::enable_if_t, T> fma(T x, T y, T z) { - double result; - __m128d xmm = _mm_load_sd(&x); // NOLINT - __m128d ymm = _mm_load_sd(&y); // NOLINT - __m128d zmm = _mm_load_sd(&z); // NOLINT - __m128d r = _mm_fmadd_sd(xmm, ymm, zmm); // NOLINT - _mm_store_sd(&result, r); // NOLINT - return result; -} - -} // namespace fputil -} // namespace LIBC_NAMESPACE - -#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_X86_64_FMA_H diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index 055630cb6a00..6255ac998db1 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -913,17 +913,9 @@ fma_common_hdrs = [ "src/__support/FPUtil/generic/FMA.h", ] -fma_platform_hdrs = [ - "src/__support/FPUtil/x86_64/FMA.h", - "src/__support/FPUtil/aarch64/FMA.h", -] - libc_support_library( name = "__support_fputil_fma", hdrs = fma_common_hdrs, - # These are conditionally included and will #error out if the platform - # doesn't support FMA, so they can't be compiled on their own. - textual_hdrs = fma_platform_hdrs, deps = [ ":__support_cpp_bit", ":__support_cpp_type_traits", -- GitLab From ecae3ed958481cba7d60868cf3504292f7f4fdf5 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Thu, 9 May 2024 18:12:54 +0100 Subject: [PATCH 175/328] [LAA] Apply loop guards to dependence distance. After supporting non-constant dependence distances in 933f49248bf, applying information from loop guards can help further disambiguate dependencies. --- llvm/lib/Analysis/LoopAccessAnalysis.cpp | 3 + .../offset-range-known-via-assume.ll | 62 +++++++------------ 2 files changed, 27 insertions(+), 38 deletions(-) diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp index ae7f0373c4e8..6fc7da168b42 100644 --- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp +++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp @@ -2005,6 +2005,9 @@ getDependenceDistanceStrideAndSize( return MemoryDepChecker::Dependence::Unknown; } + if (!isa(Dist)) + Dist = SE.applyLoopGuards(Dist, InnermostLoop); + uint64_t TypeByteSize = DL.getTypeAllocSize(ATy); bool HasSameSize = DL.getTypeStoreSizeInBits(ATy) == DL.getTypeStoreSizeInBits(BTy); diff --git a/llvm/test/Analysis/LoopAccessAnalysis/offset-range-known-via-assume.ll b/llvm/test/Analysis/LoopAccessAnalysis/offset-range-known-via-assume.ll index 7e36da78d6aa..c358b00dad22 100644 --- a/llvm/test/Analysis/LoopAccessAnalysis/offset-range-known-via-assume.ll +++ b/llvm/test/Analysis/LoopAccessAnalysis/offset-range-known-via-assume.ll @@ -7,26 +7,19 @@ declare void @llvm.assume(i1) declare void @use(ptr noundef) -; TODO: %offset is known positive via assume, so we should be able to detect the +; %offset is known positive via assume, so we should be able to detect the ; forward dependence. define void @offset_i8_known_positive_via_assume_forward_dep_1(ptr %A, i64 %offset, i64 %N) { ; CHECK-LABEL: 'offset_i8_known_positive_via_assume_forward_dep_1' ; CHECK-NEXT: loop: -; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Memory dependences are safe ; CHECK-NEXT: Dependences: +; CHECK-NEXT: Forward: +; CHECK-NEXT: %l = load i8, ptr %gep.off, align 4 -> +; CHECK-NEXT: store i8 %add, ptr %gep, align 4 +; CHECK-EMPTY: ; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP1:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv -; CHECK-NEXT: Against group ([[GRP2:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep.off = getelementptr inbounds i8, ptr %off, i64 %iv ; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP1]]: -; CHECK-NEXT: (Low: %A High: (%N + %A)) -; CHECK-NEXT: Member: {%A,+,1}<%loop> -; CHECK-NEXT: Group [[GRP2]]: -; CHECK-NEXT: (Low: (%offset + %A) High: (%offset + %N + %A)) -; CHECK-NEXT: Member: {(%offset + %A),+,1}<%loop> ; CHECK-EMPTY: ; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. ; CHECK-NEXT: SCEV assumptions: @@ -62,15 +55,15 @@ define void @offset_i32_known_positive_via_assume_forward_dep_1(ptr %A, i64 %off ; CHECK-NEXT: Dependences: ; CHECK-NEXT: Run-time memory checks: ; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP3:0x[0-9a-f]+]]): +; CHECK-NEXT: Comparing group ([[GRP1:0x[0-9a-f]+]]): ; CHECK-NEXT: %gep = getelementptr inbounds i32, ptr %A, i64 %iv -; CHECK-NEXT: Against group ([[GRP4:0x[0-9a-f]+]]): +; CHECK-NEXT: Against group ([[GRP2:0x[0-9a-f]+]]): ; CHECK-NEXT: %gep.off = getelementptr inbounds i32, ptr %off, i64 %iv ; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP3]]: +; CHECK-NEXT: Group [[GRP1]]: ; CHECK-NEXT: (Low: %A High: (-3 + (4 * %N) + %A)) ; CHECK-NEXT: Member: {%A,+,4}<%loop> -; CHECK-NEXT: Group [[GRP4]]: +; CHECK-NEXT: Group [[GRP2]]: ; CHECK-NEXT: (Low: ((4 * %offset) + %A) High: (-3 + (4 * %offset) + (4 * %N) + %A)) ; CHECK-NEXT: Member: {((4 * %offset) + %A),+,4}<%loop> ; CHECK-EMPTY: @@ -103,26 +96,19 @@ exit: ret void } -; TODO: %offset is known positive via assume, so we should be able to detect the +; %offset is known positive via assume, so we should be able to detect the ; forward dependence. define void @offset_known_positive_via_assume_forward_dep_2(ptr %A, i64 %offset, i64 %N) { ; CHECK-LABEL: 'offset_known_positive_via_assume_forward_dep_2' ; CHECK-NEXT: loop: -; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Memory dependences are safe ; CHECK-NEXT: Dependences: +; CHECK-NEXT: Forward: +; CHECK-NEXT: %l = load i32, ptr %gep.off, align 4 -> +; CHECK-NEXT: store i32 %add, ptr %gep, align 4 +; CHECK-EMPTY: ; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP5:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep = getelementptr inbounds i32, ptr %A, i64 %iv -; CHECK-NEXT: Against group ([[GRP6:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep.off = getelementptr inbounds i32, ptr %off, i64 %iv ; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP5]]: -; CHECK-NEXT: (Low: %A High: ((4 * %N) + %A)) -; CHECK-NEXT: Member: {%A,+,4}<%loop> -; CHECK-NEXT: Group [[GRP6]]: -; CHECK-NEXT: (Low: ((4 * %offset) + %A) High: ((4 * %offset) + (4 * %N) + %A)) -; CHECK-NEXT: Member: {((4 * %offset) + %A),+,4}<%loop> ; CHECK-EMPTY: ; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. ; CHECK-NEXT: SCEV assumptions: @@ -160,15 +146,15 @@ define void @offset_may_be_negative_via_assume_unknown_dep(ptr %A, i64 %offset, ; CHECK-NEXT: Dependences: ; CHECK-NEXT: Run-time memory checks: ; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP7:0x[0-9a-f]+]]): +; CHECK-NEXT: Comparing group ([[GRP3:0x[0-9a-f]+]]): ; CHECK-NEXT: %gep.mul.2 = getelementptr inbounds i32, ptr %A, i64 %iv -; CHECK-NEXT: Against group ([[GRP8:0x[0-9a-f]+]]): +; CHECK-NEXT: Against group ([[GRP4:0x[0-9a-f]+]]): ; CHECK-NEXT: %gep = getelementptr inbounds i32, ptr %off, i64 %iv ; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP7]]: +; CHECK-NEXT: Group [[GRP3]]: ; CHECK-NEXT: (Low: %A High: ((4 * %N) + %A)) ; CHECK-NEXT: Member: {%A,+,4}<%loop> -; CHECK-NEXT: Group [[GRP8]]: +; CHECK-NEXT: Group [[GRP4]]: ; CHECK-NEXT: (Low: ((4 * %offset) + %A) High: ((4 * %offset) + (4 * %N) + %A)) ; CHECK-NEXT: Member: {((4 * %offset) + %A),+,4}<%loop> ; CHECK-EMPTY: @@ -207,15 +193,15 @@ define void @offset_no_assumes(ptr %A, i64 %offset, i64 %N) { ; CHECK-NEXT: Dependences: ; CHECK-NEXT: Run-time memory checks: ; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP9:0x[0-9a-f]+]]): +; CHECK-NEXT: Comparing group ([[GRP5:0x[0-9a-f]+]]): ; CHECK-NEXT: %gep = getelementptr inbounds i32, ptr %A, i64 %iv -; CHECK-NEXT: Against group ([[GRP10:0x[0-9a-f]+]]): +; CHECK-NEXT: Against group ([[GRP6:0x[0-9a-f]+]]): ; CHECK-NEXT: %gep.off = getelementptr inbounds i32, ptr %off, i64 %iv ; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP9]]: +; CHECK-NEXT: Group [[GRP5]]: ; CHECK-NEXT: (Low: %A High: ((4 * %N) + %A)) ; CHECK-NEXT: Member: {%A,+,4}<%loop> -; CHECK-NEXT: Group [[GRP10]]: +; CHECK-NEXT: Group [[GRP6]]: ; CHECK-NEXT: (Low: ((4 * %offset) + %A) High: ((4 * %offset) + (4 * %N) + %A)) ; CHECK-NEXT: Member: {((4 * %offset) + %A),+,4}<%loop> ; CHECK-EMPTY: -- GitLab From 785b143a402a282822c3d5e30bb4e2b1980c0b1e Mon Sep 17 00:00:00 2001 From: Med Ismail Bennani Date: Thu, 9 May 2024 10:13:20 -0700 Subject: [PATCH 176/328] [lldb/crashlog] Enforce image loading policy (#91109) In `27f27d1`, we changed the image loading logic to conform to the various options (`-a|--load-all` & `-c|--crashed-only`) and loaded them concurrently. However, instead of the subset of images that matched the user option, the thread pool would always run on all the crashlog images, causing them to be all loaded in the target everytime. This matches the `-a|--load-all` option behaviour but depending on the report, it can cause lldb to load thousands of images, which can take a very long time if the images are downloaded over the network. This patch fixes that issue by keeping a list of `images_to_load` based of the user-provided option. This list will be used with our executor thread pool to load the images according to the user selection, and reinstates the expected default behaviour, by only loading the crashed thread images and skipping all the others. This patch also unifies the way we load images into a single method that's shared by both the batch mode & the interactive scripted process. rdar://123694062 Signed-off-by: Med Ismail Bennani --- lldb/examples/python/crashlog.py | 82 +++++++++++-------- .../python/crashlog_scripted_process.py | 38 +++------ 2 files changed, 63 insertions(+), 57 deletions(-) diff --git a/lldb/examples/python/crashlog.py b/lldb/examples/python/crashlog.py index c992348b24be..d147d0e322a3 100755 --- a/lldb/examples/python/crashlog.py +++ b/lldb/examples/python/crashlog.py @@ -252,7 +252,7 @@ class CrashLog(symbolication.Symbolicator): self.idents.append(ident) def did_crash(self): - return self.reason is not None + return self.crashed def __str__(self): if self.app_specific_backtrace: @@ -526,6 +526,49 @@ class CrashLog(symbolication.Symbolicator): def get_target(self): return self.target + def load_images(self, options, loaded_images=None): + if not loaded_images: + loaded_images = [] + images_to_load = self.images + if options.load_all_images: + for image in self.images: + image.resolve = True + elif options.crashed_only: + for thread in self.threads: + if thread.did_crash(): + images_to_load = [] + for ident in thread.idents: + for image in self.find_images_with_identifier(ident): + image.resolve = True + images_to_load.append(image) + + futures = [] + with tempfile.TemporaryDirectory() as obj_dir: + with concurrent.futures.ThreadPoolExecutor() as executor: + + def add_module(image, target, obj_dir): + return image, image.add_module(target, obj_dir) + + for image in images_to_load: + if image not in loaded_images: + if image.uuid == uuid.UUID(int=0): + continue + futures.append( + executor.submit( + add_module, + image=image, + target=self.target, + obj_dir=obj_dir, + ) + ) + + for future in concurrent.futures.as_completed(futures): + image, err = future.result() + if err: + print(err) + else: + loaded_images.append(image) + class CrashLogFormatException(Exception): pass @@ -1408,36 +1451,7 @@ def SymbolicateCrashLog(crash_log, options): if not target: return - if options.load_all_images: - for image in crash_log.images: - image.resolve = True - elif options.crashed_only: - for thread in crash_log.threads: - if thread.did_crash(): - for ident in thread.idents: - for image in crash_log.find_images_with_identifier(ident): - image.resolve = True - - futures = [] - loaded_images = [] - with tempfile.TemporaryDirectory() as obj_dir: - with concurrent.futures.ThreadPoolExecutor() as executor: - - def add_module(image, target, obj_dir): - return image, image.add_module(target, obj_dir) - - for image in crash_log.images: - futures.append( - executor.submit( - add_module, image=image, target=target, obj_dir=obj_dir - ) - ) - for future in concurrent.futures.as_completed(futures): - image, err = future.result() - if err: - print(err) - else: - loaded_images.append(image) + crash_log.load_images(options) if crash_log.backtraces: for thread in crash_log.backtraces: @@ -1498,7 +1512,11 @@ def load_crashlog_in_scripted_process(debugger, crashlog_path, options, result): structured_data = lldb.SBStructuredData() structured_data.SetFromJSON( json.dumps( - {"file_path": crashlog_path, "load_all_images": options.load_all_images} + { + "file_path": crashlog_path, + "load_all_images": options.load_all_images, + "crashed_only": options.crashed_only, + } ) ) launch_info = lldb.SBLaunchInfo(None) diff --git a/lldb/examples/python/crashlog_scripted_process.py b/lldb/examples/python/crashlog_scripted_process.py index c69985b1a072..26c5c37b7371 100644 --- a/lldb/examples/python/crashlog_scripted_process.py +++ b/lldb/examples/python/crashlog_scripted_process.py @@ -29,27 +29,7 @@ class CrashLogScriptedProcess(ScriptedProcess): if hasattr(self.crashlog, "asb"): self.extended_thread_info = self.crashlog.asb - if self.load_all_images: - for image in self.crashlog.images: - image.resolve = True - else: - for thread in self.crashlog.threads: - if thread.did_crash(): - for ident in thread.idents: - for image in self.crashlog.find_images_with_identifier(ident): - image.resolve = True - - with tempfile.TemporaryDirectory() as obj_dir: - for image in self.crashlog.images: - if image not in self.loaded_images: - if image.uuid == uuid.UUID(int=0): - continue - err = image.add_module(self.target, obj_dir) - if err: - # Append to SBCommandReturnObject - print(err) - else: - self.loaded_images.append(image) + crashlog.load_images(self.options, self.loaded_images) for thread in self.crashlog.threads: if ( @@ -70,6 +50,10 @@ class CrashLogScriptedProcess(ScriptedProcess): self.app_specific_thread, self.addr_mask, self.target ) + class CrashLogOptions: + load_all_images = False + crashed_only = True + def __init__(self, exe_ctx: lldb.SBExecutionContext, args: lldb.SBStructuredData): super().__init__(exe_ctx, args) @@ -88,13 +72,17 @@ class CrashLogScriptedProcess(ScriptedProcess): # Return error return + self.options = self.CrashLogOptions() + load_all_images = args.GetValueForKey("load_all_images") if load_all_images and load_all_images.IsValid(): if load_all_images.GetType() == lldb.eStructuredDataTypeBoolean: - self.load_all_images = load_all_images.GetBooleanValue() + self.options.load_all_images = load_all_images.GetBooleanValue() - if not self.load_all_images: - self.load_all_images = False + crashed_only = args.GetValueForKey("crashed_only") + if crashed_only and crashed_only.IsValid(): + if crashed_only.GetType() == lldb.eStructuredDataTypeBoolean: + self.options.crashed_only = crashed_only.GetBooleanValue() self.pid = super().get_process_id() self.crashed_thread_idx = 0 @@ -159,7 +147,7 @@ class CrashLogScriptedThread(ScriptedThread): return frames def create_stackframes(self): - if not (self.originating_process.load_all_images or self.has_crashed): + if not (self.originating_process.options.load_all_images or self.has_crashed): return None if not self.backing_thread or not len(self.backing_thread.frames): -- GitLab From 22c59e01cd2f87164301415c93b60fc3c204dfb8 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 9 May 2024 10:17:15 -0700 Subject: [PATCH 177/328] [flang] Don't crash on bad inherited implied DO type (#91073) Fortran has an ambiguously defined rule about the typing of index variables of implied DO loops in DATA statements and array constructors that omit an explicit type specification. Such indices have the type that they would have "if they were variables" in the innermost enclosing scope. Although this could, and perhaps should, be read to mean that implicit typing rules active in that innermost enclosing scope should be applied, every other Fortran compiler interprets that language to mean that if there is a type declaration for that name that is visible from the enclosing scope, it is applied, and it is an error if that type is not integer. Fixes https://github.com/llvm/llvm-project/issues/91053. --- flang/docs/Extensions.md | 23 ++++++++++++++----- flang/lib/Evaluate/formatting.cpp | 4 ++-- flang/lib/Semantics/expression.cpp | 9 +++++--- flang/lib/Semantics/resolve-names.cpp | 5 ++-- flang/test/Semantics/array-constr-index01.f90 | 8 +++++++ 5 files changed, 35 insertions(+), 14 deletions(-) create mode 100644 flang/test/Semantics/array-constr-index01.f90 diff --git a/flang/docs/Extensions.md b/flang/docs/Extensions.md index 9030207d9bda..0a5bcdc6ff3f 100644 --- a/flang/docs/Extensions.md +++ b/flang/docs/Extensions.md @@ -107,12 +107,6 @@ end These definitions yield fairly poor results due to floating-point cancellation, and every Fortran compiler (including this one) uses better algorithms. -* When an index variable of a `FORALL` or `DO CONCURRENT` is present - in the enclosing scope, and the construct does not have an explicit - type specification for its index variables, some weird restrictions - in F'2023 subclause 19.4 paragraphs 6 & 8 should apply. Since this - compiler properly scopes these names, violations of these restrictions - elicit only portability warnings by default. * The rules for pairwise distinguishing the specific procedures of a generic interface are inadequate, as admitted in note C.11.6 of F'2023. Generic interfaces whose specific procedures can be easily proven by @@ -728,6 +722,23 @@ end array and structure constructors not to be finalized, so it also makes sense not to finalize their allocatable components when releasing their storage). +* F'2023 19.4 paragraph 5: "If integer-type-spec appears in data-implied-do or + ac-implied-do-control it has the specified type and type parameters; otherwise + it has the type and type parameters that it would have if it were the name of + a variable in the innermost executable construct or scoping unit that includes + the DATA statement or array constructor, and this type shall be integer type." + Reading "would have if it were" as being the subjunctive, this would mean that + an untyped implied DO index variable should be implicitly typed according to + the rules active in the enclosing scope. But all other Fortran compilers interpret + the "would have if it were" as meaning "has if it is" -- i.e., if the name + is visible in the enclosing scope, the type of that name is used as the + type of the implied DO index. So this is an error, not a simple application + of the default implicit typing rule: +``` +character j +print *, [(j,j=1,10)] +``` + ## De Facto Standard Features * `EXTENDS_TYPE_OF()` returns `.TRUE.` if both of its arguments have the diff --git a/flang/lib/Evaluate/formatting.cpp b/flang/lib/Evaluate/formatting.cpp index 5f822bbcbb04..20193b006bf2 100644 --- a/flang/lib/Evaluate/formatting.cpp +++ b/flang/lib/Evaluate/formatting.cpp @@ -539,10 +539,10 @@ std::string DynamicType::AsFortran() const { result += length->AsFortran(); } return result + ')'; - } else if (IsUnlimitedPolymorphic()) { - return "CLASS(*)"; } else if (IsAssumedType()) { return "TYPE(*)"; + } else if (IsUnlimitedPolymorphic()) { + return "CLASS(*)"; } else if (IsTypelessIntrinsicArgument()) { return "(typeless intrinsic function argument)"; } else { diff --git a/flang/lib/Semantics/expression.cpp b/flang/lib/Semantics/expression.cpp index 8445be581fdd..ff30b3ab831c 100644 --- a/flang/lib/Semantics/expression.cpp +++ b/flang/lib/Semantics/expression.cpp @@ -1805,10 +1805,13 @@ void ArrayConstructorContext::Add(const parser::AcImpliedDo &impliedDo) { const auto &bounds{std::get(control.t)}; exprAnalyzer_.Analyze(bounds.name); parser::CharBlock name{bounds.name.thing.thing.source}; - const Symbol *symbol{bounds.name.thing.thing.symbol}; int kind{ImpliedDoIntType::kind}; - if (const auto dynamicType{DynamicType::From(symbol)}) { - kind = dynamicType->kind(); + if (const Symbol * symbol{bounds.name.thing.thing.symbol}) { + if (auto dynamicType{DynamicType::From(symbol)}) { + if (dynamicType->category() == TypeCategory::Integer) { + kind = dynamicType->kind(); + } + } } std::optional> lower{ GetSpecificIntExpr(bounds.lower)}; diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index 2199e3f16e62..4df347a878de 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -6555,6 +6555,7 @@ Symbol *DeclarationVisitor::DeclareStatementEntity( return nullptr; } name.symbol = nullptr; + // F'2023 19.4 p5 ambiguous rule about outer declarations declTypeSpec = prev->GetType(); } Symbol &symbol{DeclareEntity(name, {})}; @@ -6573,9 +6574,7 @@ Symbol *DeclarationVisitor::DeclareStatementEntity( } else { ApplyImplicitRules(symbol); } - Symbol *result{Resolve(name, &symbol)}; - AnalyzeExpr(context(), doVar); // enforce INTEGER type - return result; + return Resolve(name, &symbol); } // Set the type of an entity or report an error. diff --git a/flang/test/Semantics/array-constr-index01.f90 b/flang/test/Semantics/array-constr-index01.f90 new file mode 100644 index 000000000000..560b6be83139 --- /dev/null +++ b/flang/test/Semantics/array-constr-index01.f90 @@ -0,0 +1,8 @@ +!RUN: %python %S/test_errors.py %s %flang_fc1 +subroutine s(i) + type(*) :: i + !ERROR: TYPE(*) dummy argument may only be used as an actual argument + !ERROR: Assumed-type entity 'i' must be a dummy argument + !ERROR: Must have INTEGER type, but is TYPE(*) + print *, [(i, i = 1,1)] +end -- GitLab From 8585bf7542f1098bd03a667a408d42d2a815d305 Mon Sep 17 00:00:00 2001 From: Med Ismail Bennani Date: Thu, 9 May 2024 10:19:34 -0700 Subject: [PATCH 178/328] [lldb/crashlog] Update incorrect help message for `--no-crashed-only` option (#91162) This patch rephrases the crashlog `--no-crashed-only` option help message. This option is mainly used in batch mode to symbolicate and dump all the threads backtraces, instead of only doing it for the crashed thread which is the default behavior. rdar://127391524 Signed-off-by: Med Ismail Bennani --- lldb/examples/python/crashlog.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lldb/examples/python/crashlog.py b/lldb/examples/python/crashlog.py index d147d0e322a3..eb9af6ed3d95 100755 --- a/lldb/examples/python/crashlog.py +++ b/lldb/examples/python/crashlog.py @@ -1649,7 +1649,8 @@ def CreateSymbolicateCrashLogOptions( "--no-crashed-only", action="store_false", dest="crashed_only", - help="do not symbolicate the crashed thread", + help="in batch mode, symbolicate all threads, not only the crashed one", + default=False, ) arg_parser.add_argument( "--disasm-depth", -- GitLab From b9e3fa84d3fdfe718a4a3085f7adeda3d81f2568 Mon Sep 17 00:00:00 2001 From: Chelsea Cassanova Date: Thu, 9 May 2024 10:28:23 -0700 Subject: [PATCH 179/328] [lldb][enums] Remove broadcast bits from debugger (#91618) Removes the debugger broadcast bits from `Debugger.h` and instead uses the enum from `lldb-enumerations.h` and adds the `eBroadcastSymbolChange` bit to the enum in `lldb-enumerations.h`. This fixes a bug wherein the incorrect broadcast bit could be referenced due both of these enums previously existing and being out-of-sync with each other. --- lldb/include/lldb/Core/Debugger.h | 11 +---------- lldb/include/lldb/lldb-enumerations.h | 3 ++- lldb/source/Core/Debugger.cpp | 17 +++++++++-------- lldb/source/Core/Progress.cpp | 2 +- lldb/unittests/Core/DiagnosticEventTest.cpp | 17 +++++++---------- lldb/unittests/Core/ProgressReportTest.cpp | 8 ++++---- 6 files changed, 24 insertions(+), 34 deletions(-) diff --git a/lldb/include/lldb/Core/Debugger.h b/lldb/include/lldb/Core/Debugger.h index c0f7c732ad2d..ea994bf8c28d 100644 --- a/lldb/include/lldb/Core/Debugger.h +++ b/lldb/include/lldb/Core/Debugger.h @@ -78,15 +78,6 @@ class Debugger : public std::enable_shared_from_this, public UserID, public Properties { public: - /// Broadcaster event bits definitions. - enum { - eBroadcastBitProgress = (1 << 0), - eBroadcastBitWarning = (1 << 1), - eBroadcastBitError = (1 << 2), - eBroadcastSymbolChange = (1 << 3), - eBroadcastBitProgressCategory = (1 << 4), - }; - using DebuggerList = std::vector; static llvm::StringRef GetStaticBroadcasterClass(); @@ -628,7 +619,7 @@ protected: ReportProgress(uint64_t progress_id, std::string title, std::string details, uint64_t completed, uint64_t total, std::optional debugger_id, - uint32_t progress_category_bit = eBroadcastBitProgress); + uint32_t progress_category_bit = lldb::eBroadcastBitProgress); static void ReportDiagnosticImpl(lldb::Severity severity, std::string message, std::optional debugger_id, diff --git a/lldb/include/lldb/lldb-enumerations.h b/lldb/include/lldb/lldb-enumerations.h index 437971b3364c..8e05f6ba9c87 100644 --- a/lldb/include/lldb/lldb-enumerations.h +++ b/lldb/include/lldb/lldb-enumerations.h @@ -1344,7 +1344,8 @@ enum DebuggerBroadcastBit { eBroadcastBitProgress = (1 << 0), eBroadcastBitWarning = (1 << 1), eBroadcastBitError = (1 << 2), - eBroadcastBitProgressCategory = (1 << 3), + eBroadcastSymbolChange = (1 << 3), + eBroadcastBitProgressCategory = (1 << 4), }; /// Used for expressing severity in logs and diagnostics. diff --git a/lldb/source/Core/Debugger.cpp b/lldb/source/Core/Debugger.cpp index 976420a43443..9951fbcd3e7c 100644 --- a/lldb/source/Core/Debugger.cpp +++ b/lldb/source/Core/Debugger.cpp @@ -1485,10 +1485,10 @@ static void PrivateReportDiagnostic(Debugger &debugger, Severity severity, assert(false && "eSeverityInfo should not be broadcast"); return; case eSeverityWarning: - event_type = Debugger::eBroadcastBitWarning; + event_type = lldb::eBroadcastBitWarning; break; case eSeverityError: - event_type = Debugger::eBroadcastBitError; + event_type = lldb::eBroadcastBitError; break; } @@ -1572,7 +1572,7 @@ void Debugger::ReportSymbolChange(const ModuleSpec &module_spec) { std::lock_guard guard(*g_debugger_list_mutex_ptr); for (DebuggerSP debugger_sp : *g_debugger_list_ptr) { EventSP event_sp = std::make_shared( - Debugger::eBroadcastSymbolChange, + lldb::eBroadcastSymbolChange, new SymbolChangeEventData(debugger_sp, module_spec)); debugger_sp->GetBroadcaster().BroadcastEvent(event_sp); } @@ -1879,8 +1879,9 @@ lldb::thread_result_t Debugger::DefaultEventHandler() { CommandInterpreter::eBroadcastBitAsynchronousErrorData); listener_sp->StartListeningForEvents( - &m_broadcaster, eBroadcastBitProgress | eBroadcastBitWarning | - eBroadcastBitError | eBroadcastSymbolChange); + &m_broadcaster, lldb::eBroadcastBitProgress | lldb::eBroadcastBitWarning | + lldb::eBroadcastBitError | + lldb::eBroadcastSymbolChange); // Let the thread that spawned us know that we have started up and that we // are now listening to all required events so no events get missed @@ -1932,11 +1933,11 @@ lldb::thread_result_t Debugger::DefaultEventHandler() { } } } else if (broadcaster == &m_broadcaster) { - if (event_type & Debugger::eBroadcastBitProgress) + if (event_type & lldb::eBroadcastBitProgress) HandleProgressEvent(event_sp); - else if (event_type & Debugger::eBroadcastBitWarning) + else if (event_type & lldb::eBroadcastBitWarning) HandleDiagnosticEvent(event_sp); - else if (event_type & Debugger::eBroadcastBitError) + else if (event_type & lldb::eBroadcastBitError) HandleDiagnosticEvent(event_sp); } } diff --git a/lldb/source/Core/Progress.cpp b/lldb/source/Core/Progress.cpp index 161038284e21..1a779e2ddf92 100644 --- a/lldb/source/Core/Progress.cpp +++ b/lldb/source/Core/Progress.cpp @@ -172,7 +172,7 @@ void ProgressManager::ReportProgress( Debugger::ReportProgress(progress_data.progress_id, progress_data.title, "", completed, Progress::kNonDeterministicTotal, progress_data.debugger_id, - Debugger::eBroadcastBitProgressCategory); + lldb::eBroadcastBitProgressCategory); } void ProgressManager::Expire(llvm::StringRef key) { diff --git a/lldb/unittests/Core/DiagnosticEventTest.cpp b/lldb/unittests/Core/DiagnosticEventTest.cpp index d06f164e87e7..1423f76b8b52 100644 --- a/lldb/unittests/Core/DiagnosticEventTest.cpp +++ b/lldb/unittests/Core/DiagnosticEventTest.cpp @@ -55,9 +55,8 @@ TEST_F(DiagnosticEventTest, Warning) { ListenerSP listener_sp = Listener::MakeListener("test-listener"); listener_sp->StartListeningForEvents(&broadcaster, - Debugger::eBroadcastBitWarning); - EXPECT_TRUE( - broadcaster.EventTypeHasListeners(Debugger::eBroadcastBitWarning)); + lldb::eBroadcastBitWarning); + EXPECT_TRUE(broadcaster.EventTypeHasListeners(lldb::eBroadcastBitWarning)); Debugger::ReportWarning("foo", debugger_sp->GetID()); @@ -80,9 +79,8 @@ TEST_F(DiagnosticEventTest, Error) { Broadcaster &broadcaster = debugger_sp->GetBroadcaster(); ListenerSP listener_sp = Listener::MakeListener("test-listener"); - listener_sp->StartListeningForEvents(&broadcaster, - Debugger::eBroadcastBitError); - EXPECT_TRUE(broadcaster.EventTypeHasListeners(Debugger::eBroadcastBitError)); + listener_sp->StartListeningForEvents(&broadcaster, lldb::eBroadcastBitError); + EXPECT_TRUE(broadcaster.EventTypeHasListeners(lldb::eBroadcastBitError)); Debugger::ReportError("bar", debugger_sp->GetID()); @@ -111,7 +109,7 @@ TEST_F(DiagnosticEventTest, MultipleDebuggers) { listeners.push_back(listener); listener->StartListeningForEvents(&debugger->GetBroadcaster(), - Debugger::eBroadcastBitError); + lldb::eBroadcastBitError); } Debugger::ReportError("baz"); @@ -140,9 +138,8 @@ TEST_F(DiagnosticEventTest, WarningOnce) { ListenerSP listener_sp = Listener::MakeListener("test-listener"); listener_sp->StartListeningForEvents(&broadcaster, - Debugger::eBroadcastBitWarning); - EXPECT_TRUE( - broadcaster.EventTypeHasListeners(Debugger::eBroadcastBitWarning)); + lldb::eBroadcastBitWarning); + EXPECT_TRUE(broadcaster.EventTypeHasListeners(lldb::eBroadcastBitWarning)); std::once_flag once; Debugger::ReportWarning("foo", debugger_sp->GetID(), &once); diff --git a/lldb/unittests/Core/ProgressReportTest.cpp b/lldb/unittests/Core/ProgressReportTest.cpp index f0d253be9bf6..141244feb1f0 100644 --- a/lldb/unittests/Core/ProgressReportTest.cpp +++ b/lldb/unittests/Core/ProgressReportTest.cpp @@ -61,7 +61,7 @@ protected: }; TEST_F(ProgressReportTest, TestReportCreation) { - ListenerSP listener_sp = CreateListenerFor(Debugger::eBroadcastBitProgress); + ListenerSP listener_sp = CreateListenerFor(lldb::eBroadcastBitProgress); EventSP event_sp; const ProgressEventData *data; @@ -135,7 +135,7 @@ TEST_F(ProgressReportTest, TestReportCreation) { TEST_F(ProgressReportTest, TestProgressManager) { ListenerSP listener_sp = - CreateListenerFor(Debugger::eBroadcastBitProgressCategory); + CreateListenerFor(lldb::eBroadcastBitProgressCategory); EventSP event_sp; const ProgressEventData *data; @@ -173,7 +173,7 @@ TEST_F(ProgressReportTest, TestProgressManager) { TEST_F(ProgressReportTest, TestOverlappingEvents) { ListenerSP listener_sp = - CreateListenerFor(Debugger::eBroadcastBitProgressCategory); + CreateListenerFor(lldb::eBroadcastBitProgressCategory); EventSP event_sp; const ProgressEventData *data; @@ -214,7 +214,7 @@ TEST_F(ProgressReportTest, TestOverlappingEvents) { TEST_F(ProgressReportTest, TestProgressManagerDisjointReports) { ListenerSP listener_sp = - CreateListenerFor(Debugger::eBroadcastBitProgressCategory); + CreateListenerFor(lldb::eBroadcastBitProgressCategory); EventSP event_sp; const ProgressEventData *data; uint64_t expected_progress_id; -- GitLab From 7c1b2898302c9f84fa43952f746d79817e1ead40 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 9 May 2024 10:29:43 -0700 Subject: [PATCH 180/328] [flang] Accept compiler directives between module subprograms (#91230) Parse and represent compiler directives in a modules module-subprogram-part between the module subprograms. --- flang/include/flang/Parser/parse-tree.h | 3 ++- flang/lib/Parser/program-parsers.cpp | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/flang/include/flang/Parser/parse-tree.h b/flang/include/flang/Parser/parse-tree.h index 4641f9d20d5b..c06354458379 100644 --- a/flang/include/flang/Parser/parse-tree.h +++ b/flang/include/flang/Parser/parse-tree.h @@ -2905,7 +2905,8 @@ struct ModuleSubprogram { UNION_CLASS_BOILERPLATE(ModuleSubprogram); std::variant, common::Indirection, - common::Indirection> + common::Indirection, + common::Indirection> u; }; diff --git a/flang/lib/Parser/program-parsers.cpp b/flang/lib/Parser/program-parsers.cpp index e24559bf14f7..ff5e58ebc721 100644 --- a/flang/lib/Parser/program-parsers.cpp +++ b/flang/lib/Parser/program-parsers.cpp @@ -247,7 +247,8 @@ TYPE_CONTEXT_PARSER("module subprogram part"_en_US, // separate-module-subprogram TYPE_PARSER(construct(indirect(functionSubprogram)) || construct(indirect(subroutineSubprogram)) || - construct(indirect(Parser{}))) + construct(indirect(Parser{})) || + construct(indirect(compilerDirective))) // R1410 module-nature -> INTRINSIC | NON_INTRINSIC constexpr auto moduleNature{ -- GitLab From b3a835e129ed8a67cf393f9ee26989b36a3eff1c Mon Sep 17 00:00:00 2001 From: Med Ismail Bennani Date: Thu, 9 May 2024 10:39:05 -0700 Subject: [PATCH 181/328] [lldb] Verify target stop-hooks support with scripted process (#91107) This patch makes sure that scripted process are compatible with target stop-hooks. This wasn't tested in the past, but it turned out to be working out of the box. rdar://124396534 Signed-off-by: Med Ismail Bennani --- .../scripted_process/TestScriptedProcess.py | 7 +++++++ .../dummy_scripted_process.py | 21 +++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/lldb/test/API/functionalities/scripted_process/TestScriptedProcess.py b/lldb/test/API/functionalities/scripted_process/TestScriptedProcess.py index 5aaf68575623..9519c576689d 100644 --- a/lldb/test/API/functionalities/scripted_process/TestScriptedProcess.py +++ b/lldb/test/API/functionalities/scripted_process/TestScriptedProcess.py @@ -187,6 +187,10 @@ class ScriptedProcesTestCase(TestBase): + os.path.join(self.getSourceDir(), scripted_process_example_relpath) ) + self.runCmd( + "target stop-hook add -k first -v 1 -k second -v 2 -P dummy_scripted_process.DummyStopHook" + ) + launch_info = lldb.SBLaunchInfo(None) launch_info.SetProcessPluginName("ScriptedProcess") launch_info.SetScriptedProcessClassName( @@ -207,6 +211,9 @@ class ScriptedProcesTestCase(TestBase): self.assertTrue(hasattr(py_impl, "my_super_secret_member")) self.assertEqual(py_impl.my_super_secret_method(), 42) + self.assertTrue(hasattr(py_impl, "handled_stop")) + self.assertTrue(py_impl.handled_stop) + # Try reading from target #0 process ... addr = 0x500000000 message = "Hello, target 0" diff --git a/lldb/test/API/functionalities/scripted_process/dummy_scripted_process.py b/lldb/test/API/functionalities/scripted_process/dummy_scripted_process.py index 5aff3aa4bb55..cb07bf32c508 100644 --- a/lldb/test/API/functionalities/scripted_process/dummy_scripted_process.py +++ b/lldb/test/API/functionalities/scripted_process/dummy_scripted_process.py @@ -7,6 +7,16 @@ from lldb.plugins.scripted_process import ScriptedProcess from lldb.plugins.scripted_process import ScriptedThread +class DummyStopHook: + def __init__(self, target, args, internal_dict): + self.target = target + self.args = args + + def handle_stop(self, exe_ctx, stream): + print("My DummyStopHook triggered. Printing args: \n%s" % self.args) + sp = exe_ctx.process.GetScriptedImplementation() + sp.handled_stop = True + class DummyScriptedProcess(ScriptedProcess): memory = None @@ -18,6 +28,7 @@ class DummyScriptedProcess(ScriptedProcess): debugger = self.target.GetDebugger() index = debugger.GetIndexOfTarget(self.target) self.memory[addr] = "Hello, target " + str(index) + self.handled_stop = False def read_memory_at_address( self, addr: int, size: int, error: lldb.SBError @@ -99,7 +110,13 @@ class DummyScriptedThread(ScriptedThread): def __lldb_init_module(debugger, dict): + # This is used when loading the script in an interactive debug session to + # automatically, register the stop-hook and launch the scripted process. if not "SKIP_SCRIPTED_PROCESS_LAUNCH" in os.environ: + debugger.HandleCommand( + "target stop-hook add -k first -v 1 -k second -v 2 -P %s.%s" + % (__name__, DummyStopHook.__name__) + ) debugger.HandleCommand( "process launch -C %s.%s" % (__name__, DummyScriptedProcess.__name__) ) @@ -108,3 +125,7 @@ def __lldb_init_module(debugger, dict): "Name of the class that will manage the scripted process: '%s.%s'" % (__name__, DummyScriptedProcess.__name__) ) + print( + "Name of the class that will manage the stop-hook: '%s.%s'" + % (__name__, DummyStopHook.__name__) + ) -- GitLab From 98c1ba460a697110c64f6d1dd362dcf7088a13ca Mon Sep 17 00:00:00 2001 From: Mingming Liu Date: Thu, 9 May 2024 10:41:23 -0700 Subject: [PATCH 182/328] [InstrProf] Add vtables with type metadata into symtab (#81051) The indirect-call-promotion pass will look up the vtable to find out the virtual function [1], and add vtable-derived information in icall candidate [2] for cost-benefit analysis. [1] https://github.com/llvm/llvm-project/pull/81442/files#diff-a95d1ac8a0da69713fcb3346135d4b219f0a73920318d2549495620ea215191bR395-R416 [2] https://github.com/llvm/llvm-project/pull/81442/files#diff-a95d1ac8a0da69713fcb3346135d4b219f0a73920318d2549495620ea215191bR195-R199 --- llvm/include/llvm/ProfileData/InstrProf.h | 28 +++++++++++- llvm/lib/ProfileData/InstrProf.cpp | 32 +++++++++++++ llvm/unittests/ProfileData/InstrProfTest.cpp | 47 ++++++++++++++++++++ 3 files changed, 105 insertions(+), 2 deletions(-) diff --git a/llvm/include/llvm/ProfileData/InstrProf.h b/llvm/include/llvm/ProfileData/InstrProf.h index d5c1ba62911f..88c7fe425b5a 100644 --- a/llvm/include/llvm/ProfileData/InstrProf.h +++ b/llvm/include/llvm/ProfileData/InstrProf.h @@ -17,6 +17,7 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/BitmaskEnum.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/IntervalMap.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringRef.h" @@ -470,6 +471,12 @@ private: // A map from MD5 keys to function define. We only populate this map // when build the Symtab from a Module. std::vector> MD5FuncMap; + // A map from MD5 to the global variable. This map is only populated when + // building the symtab from a module. Use separate container instances for + // `MD5FuncMap` and `MD5VTableMap`. + // TODO: Unify the container type and the lambda function 'mapName' inside + // add{Func,VTable}WithName. + DenseMap MD5VTableMap; // A map from function runtime address to function name MD5 hash. // This map is only populated and used by raw instr profile reader. AddrHashMap AddrToMD5Map; @@ -488,12 +495,18 @@ private: // Add the function into the symbol table, by creating the following // map entries: - // name-set = {PGOFuncName} + {getCanonicalName(PGOFuncName)} if the canonical - // name is different from pgo name + // name-set = {PGOFuncName} union {getCanonicalName(PGOFuncName)} // - In MD5NameMap: for name in name-set // - In MD5FuncMap: for name in name-set Error addFuncWithName(Function &F, StringRef PGOFuncName); + // Add the vtable into the symbol table, by creating the following + // map entries: + // name-set = {PGOName} union {getCanonicalName(PGOName)} + // - In MD5NameMap: for name in name-set + // - In MD5VTableMap: for name in name-set + Error addVTableWithName(GlobalVariable &V, StringRef PGOVTableName); + // If the symtab is created by a series of calls to \c addFuncName, \c // finalizeSymtab needs to be called before looking up function names. // This is required because the underlying map is a vector (for space @@ -555,6 +568,7 @@ public: Error create(const FuncNameIterRange &FuncIterRange, const VTableNameIterRange &VTableIterRange); + // Map the MD5 of the symbol name to the name. Error addSymbolName(StringRef SymbolName) { if (SymbolName.empty()) return make_error(instrprof_error::malformed, @@ -630,6 +644,10 @@ public: /// Return function from the name's md5 hash. Return nullptr if not found. inline Function *getFunction(uint64_t FuncMD5Hash); + /// Return the global variable corresponding to md5 hash. Return nullptr if + /// not found. + inline GlobalVariable *getGlobalVariable(uint64_t MD5Hash); + /// Return the name section data. inline StringRef getNameData() const { return Data; } @@ -709,6 +727,12 @@ Function* InstrProfSymtab::getFunction(uint64_t FuncMD5Hash) { return nullptr; } +GlobalVariable *InstrProfSymtab::getGlobalVariable(uint64_t MD5Hash) { + if (auto Iter = MD5VTableMap.find(MD5Hash); Iter != MD5VTableMap.end()) + return Iter->second; + return nullptr; +} + // To store the sums of profile count values, or the percentage of // the sums of the total count values. struct CountSumOrPercent { diff --git a/llvm/lib/ProfileData/InstrProf.cpp b/llvm/lib/ProfileData/InstrProf.cpp index 1e3ca47b3d5a..806d01de1ada 100644 --- a/llvm/lib/ProfileData/InstrProf.cpp +++ b/llvm/lib/ProfileData/InstrProf.cpp @@ -476,11 +476,43 @@ Error InstrProfSymtab::create(Module &M, bool InLTO) { return E; } + SmallVector Types; + for (GlobalVariable &G : M.globals()) { + if (!G.hasName() || !G.hasMetadata(LLVMContext::MD_type)) + continue; + if (Error E = addVTableWithName( + G, getIRPGOObjectName(G, InLTO, /* PGONameMetadata */ nullptr))) + return E; + } + Sorted = false; finalizeSymtab(); return Error::success(); } +Error InstrProfSymtab::addVTableWithName(GlobalVariable &VTable, + StringRef VTablePGOName) { + auto mapName = [&](StringRef Name) -> Error { + if (Error E = addSymbolName(Name)) + return E; + + bool Inserted = true; + std::tie(std::ignore, Inserted) = + MD5VTableMap.try_emplace(GlobalValue::getGUID(Name), &VTable); + if (!Inserted) + LLVM_DEBUG(dbgs() << "GUID conflict within one module"); + return Error::success(); + }; + if (Error E = mapName(VTablePGOName)) + return E; + + StringRef CanonicalName = getCanonicalName(VTablePGOName); + if (CanonicalName != VTablePGOName) + return mapName(CanonicalName); + + return Error::success(); +} + /// \c NameStrings is a string composed of one of more possibly encoded /// sub-strings. The substrings are separated by 0 or more zero bytes. This /// method decodes the string and calls `NameCallback` for each substring. diff --git a/llvm/unittests/ProfileData/InstrProfTest.cpp b/llvm/unittests/ProfileData/InstrProfTest.cpp index 402de64fe99b..8f2c5aee1819 100644 --- a/llvm/unittests/ProfileData/InstrProfTest.cpp +++ b/llvm/unittests/ProfileData/InstrProfTest.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +#include "llvm/ADT/STLExtras.h" +#include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Function.h" #include "llvm/IR/IRBuilder.h" #include "llvm/IR/LLVMContext.h" @@ -1730,6 +1732,34 @@ TEST(SymtabTest, instr_prof_symtab_module_test) { Function::Create(FTy, Function::WeakODRLinkage, "Wblah", M.get()); Function::Create(FTy, Function::WeakODRLinkage, "Wbar", M.get()); + // [ptr, ptr, ptr] + ArrayType *VTableArrayType = ArrayType::get( + PointerType::get(Ctx, M->getDataLayout().getDefaultGlobalsAddressSpace()), + 3); + Constant *Int32TyNull = + llvm::ConstantExpr::getNullValue(PointerType::getUnqual(Ctx)); + SmallVector tys = {VTableArrayType}; + StructType *VTableType = llvm::StructType::get(Ctx, tys); + + // Create two vtables in the module, one with external linkage and the other + // with local linkage. + for (auto [Name, Linkage] : + {std::pair{"ExternalGV", GlobalValue::ExternalLinkage}, + {"LocalGV", GlobalValue::InternalLinkage}}) { + llvm::Twine FuncName(Name, StringRef("VFunc")); + Function *VFunc = Function::Create(FTy, Linkage, FuncName, M.get()); + GlobalVariable *GV = new llvm::GlobalVariable( + *M, VTableType, /* isConstant= */ true, Linkage, + llvm::ConstantStruct::get( + VTableType, + {llvm::ConstantArray::get(VTableArrayType, + {Int32TyNull, Int32TyNull, VFunc})}), + Name); + // Add type metadata for the test data, since vtables with type metadata + // are added to symtab. + GV->addTypeMetadata(16, MDString::get(Ctx, Name)); + } + InstrProfSymtab ProfSymtab; EXPECT_THAT_ERROR(ProfSymtab.create(*M), Succeeded()); @@ -1751,6 +1781,23 @@ TEST(SymtabTest, instr_prof_symtab_module_test) { EXPECT_EQ(PGOName, PGOFuncName); EXPECT_THAT(PGOFuncName.str(), EndsWith(Funcs[I].str())); } + + StringRef VTables[] = {"ExternalGV", "LocalGV"}; + for (auto [VTableName, PGOName] : {std::pair{"ExternalGV", "ExternalGV"}, + {"LocalGV", "MyModule.cpp;LocalGV"}}) { + GlobalVariable *GV = + M->getGlobalVariable(VTableName, /* AllowInternal=*/true); + + // Test that ProfSymtab returns the expected name given a hash. + std::string IRPGOName = getPGOName(*GV); + EXPECT_STREQ(IRPGOName.c_str(), PGOName); + uint64_t GUID = IndexedInstrProf::ComputeHash(IRPGOName); + EXPECT_EQ(IRPGOName, ProfSymtab.getFuncOrVarName(GUID)); + EXPECT_EQ(VTableName, getParsedIRPGOName(IRPGOName).second); + + // Test that ProfSymtab returns the expected global variable + EXPECT_EQ(GV, ProfSymtab.getGlobalVariable(GUID)); + } } // Testing symtab serialization and creator/deserialization interface -- GitLab From 7b25ddc559fad078b605c7b3c0d9f4a35a973a52 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 9 May 2024 10:43:25 -0700 Subject: [PATCH 183/328] [flang] Don't crash in expression analysis after detecting error (#91234) Avoid calling GetArguments() if a fatal error has been detected. Fixes https://github.com/llvm/llvm-project/issues/91114. --- flang/lib/Semantics/expression.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/flang/lib/Semantics/expression.cpp b/flang/lib/Semantics/expression.cpp index ff30b3ab831c..c503ea3f0246 100644 --- a/flang/lib/Semantics/expression.cpp +++ b/flang/lib/Semantics/expression.cpp @@ -4310,7 +4310,9 @@ MaybeExpr ArgumentAnalyzer::TryDefinedOp( if (Symbol *symbol{scope.FindSymbol(oprName)}) { anyPossibilities = true; parser::Name name{symbol->name(), symbol}; - result = context_.AnalyzeDefinedOp(name, GetActuals()); + if (!fatalErrors_) { + result = context_.AnalyzeDefinedOp(name, GetActuals()); + } if (result) { inaccessible = CheckAccessibleSymbol(scope, *symbol); if (inaccessible) { -- GitLab From bce3132cd26c9546a7429da534aed332f4d05d27 Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Thu, 9 May 2024 19:44:18 +0200 Subject: [PATCH 184/328] [libc++][doc] Updates Spaceship status page. The completed chrono parts no longer need an implementation. --- libcxx/docs/Status/SpaceshipProjects.csv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libcxx/docs/Status/SpaceshipProjects.csv b/libcxx/docs/Status/SpaceshipProjects.csv index 3d14f487d9a9..128b23b0c2c7 100644 --- a/libcxx/docs/Status/SpaceshipProjects.csv +++ b/libcxx/docs/Status/SpaceshipProjects.csv @@ -171,10 +171,10 @@ Section,Description,Dependencies,Assignee,Complete | `month_weekday_last `_ | `year_month_weekday `_ | `year_month_weekday_last `_",None,Hristo Hristov,|Complete| -`[time.zone.nonmembers] `_,"`chrono::time_zone`",A ```` implementation,Mark de Wever,|Complete| +`[time.zone.nonmembers] `_,"`chrono::time_zone`",,Mark de Wever,|Complete| `[time.zone.zonedtime.nonmembers] `_,"`chrono::zoned_time`",A ```` implementation,Mark de Wever,|In Progress| -`[time.zone.leap.nonmembers] `_,"`chrono::time_leap_seconds`",A ```` implementation,Mark de Wever,|Complete| -`[time.zone.link.nonmembers] `_,"`chrono::time_zone_link`",A ```` implementation,Mark de Wever,|Complete| +`[time.zone.leap.nonmembers] `_,"`chrono::time_leap_seconds`",,Mark de Wever,|Complete| +`[time.zone.link.nonmembers] `_,"`chrono::time_zone_link`",,Mark de Wever,|Complete| - `5.13 Clause 28: Localization library `_,,,, "| `[locale] `_ | `[locale.operators] `_",| remove ops `locale `_,None,Hristo Hristov,|Complete| -- GitLab From d742c2aa25226c2b48f3917ed86a5a224cf25734 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 9 May 2024 10:53:29 -0700 Subject: [PATCH 185/328] [flang] Move EQUIVALENCE object checking to check-declarations.cpp (#91259) Move EQUIVALENCE object checking from resolve-names-utils.cpp to check-declarations.cpp, where it can work on fully resolved symbols and reduce clutter in name resolution. Add a check for EQUIVALENCE objects that are not ObjectEntityDetails symbols so that attempts to equivalence a procedure are caught. --- flang/lib/Semantics/check-declarations.cpp | 68 ++++++++++++++++++++- flang/lib/Semantics/compute-offsets.cpp | 28 +++++---- flang/lib/Semantics/resolve-names-utils.cpp | 68 +-------------------- flang/test/Semantics/equivalence01.f90 | 9 +++ 4 files changed, 91 insertions(+), 82 deletions(-) diff --git a/flang/lib/Semantics/check-declarations.cpp b/flang/lib/Semantics/check-declarations.cpp index c1d9538e557f..f57020bbe707 100644 --- a/flang/lib/Semantics/check-declarations.cpp +++ b/flang/lib/Semantics/check-declarations.cpp @@ -87,6 +87,7 @@ private: bool CheckDefinedAssignmentArg(const Symbol &, const DummyArgument &, int); void CheckSpecifics(const Symbol &, const GenericDetails &); void CheckEquivalenceSet(const EquivalenceSet &); + void CheckEquivalenceObject(const EquivalenceObject &); void CheckBlockData(const Scope &); void CheckGenericOps(const Scope &); bool CheckConflicting(const Symbol &, Attr, Attr); @@ -2558,14 +2559,77 @@ void CheckHelper::CheckEquivalenceSet(const EquivalenceSet &set) { } } } - // TODO: Move C8106 (&al.) checks here from resolve-names-utils.cpp for (const EquivalenceObject &object : set) { - if (object.symbol.test(Symbol::Flag::CrayPointee)) { + CheckEquivalenceObject(object); + } +} + +static bool InCommonWithBind(const Symbol &symbol) { + if (const auto *details{symbol.detailsIf()}) { + const Symbol *commonBlock{details->commonBlock()}; + return commonBlock && commonBlock->attrs().test(Attr::BIND_C); + } else { + return false; + } +} + +void CheckHelper::CheckEquivalenceObject(const EquivalenceObject &object) { + parser::MessageFixedText msg; + const Symbol &symbol{object.symbol}; + if (symbol.owner().IsDerivedType()) { + msg = + "Derived type component '%s' is not allowed in an equivalence set"_err_en_US; + } else if (IsDummy(symbol)) { + msg = "Dummy argument '%s' is not allowed in an equivalence set"_err_en_US; + } else if (symbol.IsFuncResult()) { + msg = "Function result '%s' is not allow in an equivalence set"_err_en_US; + } else if (IsPointer(symbol)) { + msg = "Pointer '%s' is not allowed in an equivalence set"_err_en_US; + } else if (IsAllocatable(symbol)) { + msg = + "Allocatable variable '%s' is not allowed in an equivalence set"_err_en_US; + } else if (symbol.Corank() > 0) { + msg = "Coarray '%s' is not allowed in an equivalence set"_err_en_US; + } else if (symbol.has()) { + msg = + "Use-associated variable '%s' is not allowed in an equivalence set"_err_en_US; + } else if (symbol.attrs().test(Attr::BIND_C)) { + msg = + "Variable '%s' with BIND attribute is not allowed in an equivalence set"_err_en_US; + } else if (symbol.attrs().test(Attr::TARGET)) { + msg = + "Variable '%s' with TARGET attribute is not allowed in an equivalence set"_err_en_US; + } else if (IsNamedConstant(symbol)) { + msg = "Named constant '%s' is not allowed in an equivalence set"_err_en_US; + } else if (InCommonWithBind(symbol)) { + msg = + "Variable '%s' in common block with BIND attribute is not allowed in an equivalence set"_err_en_US; + } else if (!symbol.has()) { + msg = "'%s' in equivalence set is not a data object"_err_en_US; + } else if (const auto *type{symbol.GetType()}) { + const auto *derived{type->AsDerived()}; + if (derived && !derived->IsVectorType()) { + if (const auto *comp{ + FindUltimateComponent(*derived, IsAllocatableOrPointer)}) { + msg = IsPointer(*comp) + ? "Derived type object '%s' with pointer ultimate component is not allowed in an equivalence set"_err_en_US + : "Derived type object '%s' with allocatable ultimate component is not allowed in an equivalence set"_err_en_US; + } else if (!derived->typeSymbol().get().sequence()) { + msg = + "Nonsequence derived type object '%s' is not allowed in an equivalence set"_err_en_US; + } + } else if (IsAutomatic(symbol)) { + msg = + "Automatic object '%s' is not allowed in an equivalence set"_err_en_US; + } else if (symbol.test(Symbol::Flag::CrayPointee)) { messages_.Say(object.symbol.name(), "Cray pointee '%s' may not be a member of an EQUIVALENCE group"_err_en_US, object.symbol.name()); } } + if (!msg.text().empty()) { + context_.Say(object.source, std::move(msg), symbol.name()); + } } void CheckHelper::CheckBlockData(const Scope &scope) { diff --git a/flang/lib/Semantics/compute-offsets.cpp b/flang/lib/Semantics/compute-offsets.cpp index 2eb3a34ad806..d9a9576e9d67 100644 --- a/flang/lib/Semantics/compute-offsets.cpp +++ b/flang/lib/Semantics/compute-offsets.cpp @@ -277,20 +277,22 @@ std::size_t ComputeOffsetsHelper::ComputeOffset( const EquivalenceObject &object) { std::size_t offset{0}; if (!object.subscripts.empty()) { - const ArraySpec &shape{object.symbol.get().shape()}; - auto lbound{[&](std::size_t i) { - return *ToInt64(shape[i].lbound().GetExplicit()); - }}; - auto ubound{[&](std::size_t i) { - return *ToInt64(shape[i].ubound().GetExplicit()); - }}; - for (std::size_t i{object.subscripts.size() - 1};;) { - offset += object.subscripts[i] - lbound(i); - if (i == 0) { - break; + if (const auto *details{object.symbol.detailsIf()}) { + const ArraySpec &shape{details->shape()}; + auto lbound{[&](std::size_t i) { + return *ToInt64(shape[i].lbound().GetExplicit()); + }}; + auto ubound{[&](std::size_t i) { + return *ToInt64(shape[i].ubound().GetExplicit()); + }}; + for (std::size_t i{object.subscripts.size() - 1};;) { + offset += object.subscripts[i] - lbound(i); + if (i == 0) { + break; + } + --i; + offset *= ubound(i) - lbound(i) + 1; } - --i; - offset *= ubound(i) - lbound(i) + 1; } } auto result{offset * GetSizeAndAlignment(object.symbol, false).size}; diff --git a/flang/lib/Semantics/resolve-names-utils.cpp b/flang/lib/Semantics/resolve-names-utils.cpp index 801473876e7e..3ca460b8e46a 100644 --- a/flang/lib/Semantics/resolve-names-utils.cpp +++ b/flang/lib/Semantics/resolve-names-utils.cpp @@ -568,75 +568,9 @@ bool EquivalenceSets::CheckDataRef( x.u); } -static bool InCommonWithBind(const Symbol &symbol) { - if (const auto *details{symbol.detailsIf()}) { - const Symbol *commonBlock{details->commonBlock()}; - return commonBlock && commonBlock->attrs().test(Attr::BIND_C); - } else { - return false; - } -} - -// If symbol can't be in equivalence set report error and return false; bool EquivalenceSets::CheckObject(const parser::Name &name) { - if (!name.symbol) { - return false; // an error has already occurred - } currObject_.symbol = name.symbol; - parser::MessageFixedText msg; - const Symbol &symbol{*name.symbol}; - if (symbol.owner().IsDerivedType()) { // C8107 - msg = "Derived type component '%s'" - " is not allowed in an equivalence set"_err_en_US; - } else if (IsDummy(symbol)) { // C8106 - msg = "Dummy argument '%s' is not allowed in an equivalence set"_err_en_US; - } else if (symbol.IsFuncResult()) { // C8106 - msg = "Function result '%s' is not allow in an equivalence set"_err_en_US; - } else if (IsPointer(symbol)) { // C8106 - msg = "Pointer '%s' is not allowed in an equivalence set"_err_en_US; - } else if (IsAllocatable(symbol)) { // C8106 - msg = "Allocatable variable '%s'" - " is not allowed in an equivalence set"_err_en_US; - } else if (symbol.Corank() > 0) { // C8106 - msg = "Coarray '%s' is not allowed in an equivalence set"_err_en_US; - } else if (symbol.has()) { // C8115 - msg = "Use-associated variable '%s'" - " is not allowed in an equivalence set"_err_en_US; - } else if (symbol.attrs().test(Attr::BIND_C)) { // C8106 - msg = "Variable '%s' with BIND attribute" - " is not allowed in an equivalence set"_err_en_US; - } else if (symbol.attrs().test(Attr::TARGET)) { // C8108 - msg = "Variable '%s' with TARGET attribute" - " is not allowed in an equivalence set"_err_en_US; - } else if (IsNamedConstant(symbol)) { // C8106 - msg = "Named constant '%s' is not allowed in an equivalence set"_err_en_US; - } else if (InCommonWithBind(symbol)) { // C8106 - msg = "Variable '%s' in common block with BIND attribute" - " is not allowed in an equivalence set"_err_en_US; - } else if (const auto *type{symbol.GetType()}) { - const auto *derived{type->AsDerived()}; - if (derived && !derived->IsVectorType()) { - if (const auto *comp{FindUltimateComponent( - *derived, IsAllocatableOrPointer)}) { // C8106 - msg = IsPointer(*comp) - ? "Derived type object '%s' with pointer ultimate component" - " is not allowed in an equivalence set"_err_en_US - : "Derived type object '%s' with allocatable ultimate component" - " is not allowed in an equivalence set"_err_en_US; - } else if (!derived->typeSymbol().get().sequence()) { - msg = "Nonsequence derived type object '%s'" - " is not allowed in an equivalence set"_err_en_US; - } - } else if (IsAutomatic(symbol)) { - msg = "Automatic object '%s'" - " is not allowed in an equivalence set"_err_en_US; - } - } - if (!msg.text().empty()) { - context_.Say(name.source, std::move(msg), name.source); - return false; - } - return true; + return currObject_.symbol != nullptr; } bool EquivalenceSets::CheckArrayBound(const parser::Expr &bound) { diff --git a/flang/test/Semantics/equivalence01.f90 b/flang/test/Semantics/equivalence01.f90 index 7ef47fb554b5..ec68e9066a29 100644 --- a/flang/test/Semantics/equivalence01.f90 +++ b/flang/test/Semantics/equivalence01.f90 @@ -244,3 +244,12 @@ module m18 type(t1) x common x end + +subroutine s19 + entry e19 + !ERROR: 'e19' in equivalence set is not a data object + equivalence (e19, j) + !ERROR: 'e20' in equivalence set is not a data object + equivalence (e20, j) + entry e20 +end -- GitLab From 5ad418b55c167fbdce31b92467e90eb3a03d85ce Mon Sep 17 00:00:00 2001 From: erichkeane Date: Thu, 9 May 2024 10:57:52 -0700 Subject: [PATCH 186/328] Remove stale TODO comment --- clang/lib/Parse/ParseOpenACC.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/clang/lib/Parse/ParseOpenACC.cpp b/clang/lib/Parse/ParseOpenACC.cpp index 90dfea6f5f5c..0e10632c8317 100644 --- a/clang/lib/Parse/ParseOpenACC.cpp +++ b/clang/lib/Parse/ParseOpenACC.cpp @@ -956,7 +956,6 @@ Parser::OpenACCClauseParseResult Parser::ParseOpenACCClauseParams( break; case OpenACCClauseKind::Attach: case OpenACCClauseKind::DevicePtr: - // TODO: ERICH: Figure out how to limit to just ptrs? ParsedClause.setVarListDetails(ParseOpenACCVarList(), /*IsReadOnly=*/false, /*IsZero=*/false); break; -- GitLab From 90501be35b2c4ad314a45634062e0dfe878d8621 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 9 May 2024 11:04:50 -0700 Subject: [PATCH 187/328] [flang] Accept interoperable types without BIND(C) (#91363) A derived type that meets (most of) the requirements of an interoperable type but doesn't actually have the BIND(C) attribute can be accepted as an interoperable type, with optional warnings. --- flang/docs/Extensions.md | 7 + flang/include/flang/Common/Fortran-features.h | 3 +- flang/lib/Semantics/check-declarations.cpp | 265 ++++++++++++------ flang/test/Semantics/bind-c03.f90 | 7 +- flang/test/Semantics/bind-c06.f90 | 28 +- flang/test/Semantics/bindings01.f90 | 4 +- flang/test/Semantics/resolve81.f90 | 8 +- flang/test/Semantics/resolve85.f90 | 2 +- 8 files changed, 214 insertions(+), 110 deletions(-) diff --git a/flang/docs/Extensions.md b/flang/docs/Extensions.md index 0a5bcdc6ff3f..43ed35e36a6e 100644 --- a/flang/docs/Extensions.md +++ b/flang/docs/Extensions.md @@ -114,6 +114,10 @@ end appear in real applications, but are still non-conforming under the incomplete tests in F'2023 15.4.3.4.5. These cases are compiled with optional portability warnings. +* `PROCEDURE(), BIND(C) :: PROC` is not conforming, as there is no + procedure interface. This compiler accepts it, since there is otherwise + no way to declare an interoperable dummy procedure with an arbitrary + interface like `void (*)()`. ## Extensions, deletions, and legacy features supported by default @@ -345,6 +349,9 @@ end when necessary to the type of the result. An `OPTIONAL`, `POINTER`, or `ALLOCATABLE` argument after the first two cannot be converted, as it may not be present. +* A derived type that meets (most of) the requirements of an interoperable + derived type can be used as such where an interoperable type is + required, with warnings, even if it lacks the BIND(C) attribute. ### Extensions supported when enabled by options diff --git a/flang/include/flang/Common/Fortran-features.h b/flang/include/flang/Common/Fortran-features.h index 6b3e37cd9c25..07ed7f43c1e7 100644 --- a/flang/include/flang/Common/Fortran-features.h +++ b/flang/include/flang/Common/Fortran-features.h @@ -48,7 +48,8 @@ ENUM_CLASS(LanguageFeature, BackslashEscapes, OldDebugLines, ImpliedDoIndexScope, DistinctCommonSizes, OddIndexVariableRestrictions, IndistinguishableSpecifics, SubroutineAndFunctionSpecifics, EmptySequenceType, NonSequenceCrayPointee, BranchIntoConstruct, - BadBranchTarget, ConvertedArgument, HollerithPolymorphic, ListDirectedSize) + BadBranchTarget, ConvertedArgument, HollerithPolymorphic, ListDirectedSize, + NonBindCInteroperability) // Portability and suspicious usage warnings ENUM_CLASS(UsageWarning, Portability, PointerToUndefinable, diff --git a/flang/lib/Semantics/check-declarations.cpp b/flang/lib/Semantics/check-declarations.cpp index f57020bbe707..9ef34f0f81c0 100644 --- a/flang/lib/Semantics/check-declarations.cpp +++ b/flang/lib/Semantics/check-declarations.cpp @@ -116,11 +116,16 @@ private: } return msg; } + bool InModuleFile() const { + return FindModuleFileContaining(context_.FindScope(messages_.at())) != + nullptr; + } template parser::Message *WarnIfNotInModuleFile(A &&...x) { - if (FindModuleFileContaining(context_.FindScope(messages_.at()))) { + if (InModuleFile()) { return nullptr; + } else { + return messages_.Say(std::forward(x)...); } - return messages_.Say(std::forward(x)...); } template parser::Message *WarnIfNotInModuleFile(parser::CharBlock source, A &&...x) { @@ -133,6 +138,7 @@ private: void CheckGlobalName(const Symbol &); void CheckProcedureAssemblyName(const Symbol &symbol); void CheckExplicitSave(const Symbol &); + parser::Messages WhyNotInteroperableDerivedType(const Symbol &, bool isError); void CheckBindC(const Symbol &); void CheckBindCFunctionResult(const Symbol &); // Check functions for defined I/O procedures @@ -183,6 +189,8 @@ private: // Collection of target dependent assembly names of external and BIND(C) // procedures. std::map procedureAssemblyNames_; + // Derived types that have been examined by WhyNotInteroperableDerivedType + UnorderedSymbolSet examinedByWhyNotInteroperableDerivedType_; }; class DistinguishabilityHelper { @@ -2822,11 +2830,129 @@ void CheckHelper::CheckProcedureAssemblyName(const Symbol &symbol) { } } +parser::Messages CheckHelper::WhyNotInteroperableDerivedType( + const Symbol &symbol, bool isError) { + parser::Messages msgs; + if (examinedByWhyNotInteroperableDerivedType_.find(symbol) != + examinedByWhyNotInteroperableDerivedType_.end()) { + return msgs; + } + isError |= symbol.attrs().test(Attr::BIND_C); + examinedByWhyNotInteroperableDerivedType_.insert(symbol); + if (const auto *derived{symbol.detailsIf()}) { + if (derived->sequence()) { // C1801 + msgs.Say(symbol.name(), + "An interoperable derived type cannot have the SEQUENCE attribute"_err_en_US); + } else if (!derived->paramDecls().empty()) { // C1802 + msgs.Say(symbol.name(), + "An interoperable derived type cannot have a type parameter"_err_en_US); + } else if (const auto *parent{ + symbol.scope()->GetDerivedTypeParent()}) { // C1803 + if (isError) { + msgs.Say(symbol.name(), + "A derived type with the BIND attribute cannot be an extended derived type"_err_en_US); + } else { + bool interoperableParent{true}; + if (parent->symbol()) { + auto bad{WhyNotInteroperableDerivedType(*parent->symbol(), false)}; + if (bad.AnyFatalError()) { + auto &msg{msgs.Say(symbol.name(), + "The parent of an interoperable type is not interoperable"_err_en_US)}; + bad.AttachTo(msg, parser::Severity::None); + interoperableParent = false; + } + } + if (interoperableParent) { + msgs.Say(symbol.name(), + "An interoperable type should not be an extended derived type"_warn_en_US); + } + } + } + const Symbol *parentComponent{symbol.scope() + ? derived->GetParentComponent(*symbol.scope()) + : nullptr}; + for (const auto &pair : *symbol.scope()) { + const Symbol &component{*pair.second}; + if (&component == parentComponent) { + continue; // was checked above + } + if (IsProcedure(component)) { // C1804 + msgs.Say(component.name(), + "An interoperable derived type cannot have a type bound procedure"_err_en_US); + } else if (IsAllocatableOrPointer(component)) { // C1806 + msgs.Say(component.name(), + "An interoperable derived type cannot have a pointer or allocatable component"_err_en_US); + } else if (const auto *type{component.GetType()}) { + if (const auto *derived{type->AsDerived()}) { + auto bad{ + WhyNotInteroperableDerivedType(derived->typeSymbol(), isError)}; + if (bad.AnyFatalError()) { + auto &msg{msgs.Say(component.name(), + "Component '%s' of an interoperable derived type must have an interoperable type but does not"_err_en_US, + component.name())}; + bad.AttachTo(msg, parser::Severity::None); + } else if (!derived->typeSymbol().GetUltimate().attrs().test( + Attr::BIND_C)) { + auto &msg{ + msgs.Say(component.name(), + "Derived type of component '%s' of an interoperable derived type should have the BIND attribute"_warn_en_US, + component.name()) + .Attach(derived->typeSymbol().name(), + "Non-BIND(C) component type"_en_US)}; + bad.AttachTo(msg, parser::Severity::None); + } else { + msgs.Annex(std::move(bad)); + } + } else if (!IsInteroperableIntrinsicType( + *type, context_.languageFeatures())) { + auto maybeDyType{evaluate::DynamicType::From(*type)}; + if (type->category() == DeclTypeSpec::Logical) { + if (context_.ShouldWarn(common::UsageWarning::LogicalVsCBool)) { + msgs.Say(component.name(), + "A LOGICAL component of an interoperable type should have the interoperable KIND=C_BOOL"_port_en_US); + } + } else if (type->category() == DeclTypeSpec::Character && + maybeDyType && maybeDyType->kind() == 1) { + if (context_.ShouldWarn(common::UsageWarning::BindCCharLength)) { + msgs.Say(component.name(), + "A CHARACTER component of an interoperable type should have length 1"_port_en_US); + } + } else { + msgs.Say(component.name(), + "Each component of an interoperable derived type must have an interoperable type"_err_en_US); + } + } + } + if (auto extents{ + evaluate::GetConstantExtents(foldingContext_, &component)}; + extents && evaluate::GetSize(*extents) == 0) { + msgs.Say(component.name(), + "An array component of an interoperable type must have at least one element"_err_en_US); + } + } + if (derived->componentNames().empty()) { // F'2023 C1805 + if (context_.ShouldWarn(common::LanguageFeature::EmptyBindCDerivedType)) { + msgs.Say(symbol.name(), + "A derived type with the BIND attribute should not be empty"_port_en_US); + } + } + } + if (isError) { + for (auto &m : msgs.messages()) { + if (!m.IsFatal()) { + m.set_severity(parser::Severity::Error); + } + } + } + return msgs; +} + void CheckHelper::CheckBindC(const Symbol &symbol) { bool isExplicitBindC{symbol.attrs().test(Attr::BIND_C)}; if (isExplicitBindC) { - CheckConflicting(symbol, Attr::BIND_C, Attr::PARAMETER); CheckConflicting(symbol, Attr::BIND_C, Attr::ELEMENTAL); + CheckConflicting(symbol, Attr::BIND_C, Attr::INTRINSIC); + CheckConflicting(symbol, Attr::BIND_C, Attr::PARAMETER); } else { // symbol must be interoperable (e.g., dummy argument of interoperable // procedure interface) but is not itself BIND(C). @@ -2896,13 +3022,30 @@ void CheckHelper::CheckBindC(const Symbol &symbol) { } if (const auto *type{symbol.GetType()}) { const auto *derived{type->AsDerived()}; - if (derived && !derived->typeSymbol().attrs().test(Attr::BIND_C)) { - if (auto *msg{messages_.Say(symbol.name(), - "The derived type of a BIND(C) object must also be BIND(C)"_err_en_US)}) { - msg->Attach( - derived->typeSymbol().name(), "Non-interoperable type"_en_US); + if (derived) { + if (derived->typeSymbol().attrs().test(Attr::BIND_C)) { + } else if (isExplicitBindC) { + if (auto *msg{messages_.Say(symbol.name(), + "The derived type of a BIND(C) object must also be BIND(C)"_err_en_US)}) { + msg->Attach(derived->typeSymbol().name(), "Non-BIND(C) type"_en_US); + } + context_.SetError(symbol); + } else if (auto bad{WhyNotInteroperableDerivedType( + derived->typeSymbol(), false)}; + !bad.empty()) { + if (auto *msg{messages_.Say(symbol.name(), + "The derived type of an interoperable object must be interoperable, but is not"_err_en_US)}) { + msg->Attach( + derived->typeSymbol().name(), "Non-interoperable type"_en_US); + bad.AttachTo(*msg, parser::Severity::None); + } + context_.SetError(symbol); + } else { + if (auto *msg{messages_.Say(symbol.name(), + "The derived type of an interoperable object should be BIND(C)"_warn_en_US)}) { + msg->Attach(derived->typeSymbol().name(), "Non-BIND(C) type"_en_US); + } } - context_.SetError(symbol); } if (type->IsAssumedType() || IsAssumedLengthCharacter(symbol)) { // ok @@ -2945,17 +3088,20 @@ void CheckHelper::CheckBindC(const Symbol &symbol) { "An interoperable pointer must not be CONTIGUOUS"_err_en_US); } } else if (const auto *proc{symbol.detailsIf()}) { - if (!proc->procInterface() || - !proc->procInterface()->attrs().test(Attr::BIND_C)) { - if (proc->isDummy()) { - messages_.Say(symbol.name(), - "A dummy procedure to an interoperable procedure must also be interoperable"_err_en_US); - context_.SetError(symbol); - } else { - messages_.Say(symbol.name(), - "An interface name with BIND attribute must be specified if the BIND attribute is specified in a procedure declaration statement"_err_en_US); - context_.SetError(symbol); + if (!IsBindCProcedure(symbol) && proc->isDummy()) { + messages_.Say(symbol.name(), + "A dummy procedure to an interoperable procedure must also be interoperable"_err_en_US); + context_.SetError(symbol); + } else if (!proc->procInterface()) { + if (context_.ShouldWarn( + common::LanguageFeature::NonBindCInteroperability)) { + WarnIfNotInModuleFile(symbol.name(), + "An interface name with BIND attribute should be specified if the BIND attribute is specified in a procedure declaration statement"_warn_en_US); } + } else if (!proc->procInterface()->attrs().test(Attr::BIND_C)) { + messages_.Say(symbol.name(), + "An interface name with BIND attribute must be specified if the BIND attribute is specified in a procedure declaration statement"_err_en_US); + context_.SetError(symbol); } } else if (const auto *subp{symbol.detailsIf()}) { for (const Symbol *dummy : subp->dummyArgs()) { @@ -2967,77 +3113,18 @@ void CheckHelper::CheckBindC(const Symbol &symbol) { context_.SetError(symbol); } } - } else if (const auto *derived{symbol.detailsIf()}) { - if (derived->sequence()) { // C1801 - messages_.Say(symbol.name(), - "A derived type with the BIND attribute cannot have the SEQUENCE attribute"_err_en_US); - context_.SetError(symbol); - } else if (!derived->paramDecls().empty()) { // C1802 - messages_.Say(symbol.name(), - "A derived type with the BIND attribute has type parameter(s)"_err_en_US); - context_.SetError(symbol); - } else if (symbol.scope()->GetDerivedTypeParent()) { // C1803 - messages_.Say(symbol.name(), - "A derived type with the BIND attribute cannot extend from another derived type"_err_en_US); - context_.SetError(symbol); - } else { - for (const auto &pair : *symbol.scope()) { - const Symbol *component{&*pair.second}; - if (IsProcedure(*component)) { // C1804 - messages_.Say(component->name(), - "A derived type with the BIND attribute cannot have a type bound procedure"_err_en_US); - context_.SetError(symbol); - } - if (IsAllocatableOrPointer(*component)) { // C1806 - messages_.Say(component->name(), - "A derived type with the BIND attribute cannot have a pointer or allocatable component"_err_en_US); - context_.SetError(symbol); - } - if (const auto *type{component->GetType()}) { - if (const auto *derived{type->AsDerived()}) { - if (!derived->typeSymbol().attrs().test(Attr::BIND_C)) { - if (auto *msg{messages_.Say(component->name(), - "Component '%s' of an interoperable derived type must have the BIND attribute"_err_en_US, - component->name())}) { - msg->Attach(derived->typeSymbol().name(), - "Non-interoperable component type"_en_US); - } - context_.SetError(symbol); - } - } else if (!IsInteroperableIntrinsicType( - *type, context_.languageFeatures())) { - auto maybeDyType{evaluate::DynamicType::From(*type)}; - if (type->category() == DeclTypeSpec::Logical) { - if (context_.ShouldWarn(common::UsageWarning::LogicalVsCBool)) { - WarnIfNotInModuleFile(component->name(), - "A LOGICAL component of a BIND(C) type should have the interoperable KIND=C_BOOL"_port_en_US); - } - } else if (type->category() == DeclTypeSpec::Character && - maybeDyType && maybeDyType->kind() == 1) { - if (context_.ShouldWarn(common::UsageWarning::BindCCharLength)) { - WarnIfNotInModuleFile(component->name(), - "A CHARACTER component of a BIND(C) type should have length 1"_port_en_US); - } - } else { - messages_.Say(component->name(), - "Each component of an interoperable derived type must have an interoperable type"_err_en_US); - context_.SetError(symbol); - } - } - } - if (auto extents{ - evaluate::GetConstantExtents(foldingContext_, component)}; - extents && evaluate::GetSize(*extents) == 0) { - messages_.Say(component->name(), - "An array component of an interoperable type must have at least one element"_err_en_US); - context_.SetError(symbol); - } + } else if (symbol.has()) { + if (auto msgs{WhyNotInteroperableDerivedType(symbol, false)}; + !msgs.empty()) { + bool anyFatal{msgs.AnyFatalError()}; + if (msgs.AnyFatalError() || + (!InModuleFile() && + context_.ShouldWarn( + common::LanguageFeature::NonBindCInteroperability))) { + context_.messages().Annex(std::move(msgs)); } - } - if (derived->componentNames().empty()) { // F'2023 C1805 - if (context_.ShouldWarn(common::LanguageFeature::EmptyBindCDerivedType)) { - WarnIfNotInModuleFile(symbol.name(), - "A derived type with the BIND attribute is empty"_port_en_US); + if (anyFatal) { + context_.SetError(symbol); } } } diff --git a/flang/test/Semantics/bind-c03.f90 b/flang/test/Semantics/bind-c03.f90 index 65d52e964ca4..c37cb2bccb1f 100644 --- a/flang/test/Semantics/bind-c03.f90 +++ b/flang/test/Semantics/bind-c03.f90 @@ -1,4 +1,4 @@ -! RUN: %python %S/test_errors.py %s %flang_fc1 +! RUN: %python %S/test_errors.py %s %flang_fc1 -pedantic ! Check for C1521 ! If proc-language-binding-spec (bind(c)) is specified, the proc-interface ! shall appear, it shall be an interface-name, and interface-name shall be @@ -24,7 +24,10 @@ module m !ERROR: An interface name with BIND attribute must be specified if the BIND attribute is specified in a procedure declaration statement procedure(proc2), bind(c) :: pc2 - !ERROR: An interface name with BIND attribute must be specified if the BIND attribute is specified in a procedure declaration statement + !WARNING: An interface name with BIND attribute should be specified if the BIND attribute is specified in a procedure declaration statement procedure(integer), bind(c) :: pc3 + !WARNING: An interface name with BIND attribute should be specified if the BIND attribute is specified in a procedure declaration statement + procedure(), bind(c) :: pc5 + end diff --git a/flang/test/Semantics/bind-c06.f90 b/flang/test/Semantics/bind-c06.f90 index 4c25722cb775..3ad3078c4b4a 100644 --- a/flang/test/Semantics/bind-c06.f90 +++ b/flang/test/Semantics/bind-c06.f90 @@ -16,19 +16,19 @@ program main integer :: i end type - ! ERROR: A derived type with the BIND attribute cannot have the SEQUENCE attribute + ! ERROR: An interoperable derived type cannot have the SEQUENCE attribute type, bind(c) :: t1 sequence integer :: x end type - ! ERROR: A derived type with the BIND attribute has type parameter(s) + ! ERROR: An interoperable derived type cannot have a type parameter type, bind(c) :: t2(k) integer, KIND :: k integer :: x end type - ! ERROR: A derived type with the BIND attribute cannot extend from another derived type + ! ERROR: A derived type with the BIND attribute cannot be an extended derived type type, bind(c), extends(v) :: t3 integer :: x end type @@ -36,21 +36,21 @@ program main type, bind(c) :: t4 integer :: x contains - ! ERROR: A derived type with the BIND attribute cannot have a type bound procedure + ! ERROR: An interoperable derived type cannot have a type bound procedure procedure, nopass :: b => s end type - ! WARNING: A derived type with the BIND attribute is empty + ! WARNING: A derived type with the BIND attribute should not be empty type, bind(c) :: t5 end type type, bind(c) :: t6 - ! ERROR: A derived type with the BIND attribute cannot have a pointer or allocatable component + ! ERROR: An interoperable derived type cannot have a pointer or allocatable component integer, pointer :: x end type type, bind(c) :: t7 - ! ERROR: A derived type with the BIND attribute cannot have a pointer or allocatable component + ! ERROR: An interoperable derived type cannot have a pointer or allocatable component integer, allocatable :: y end type @@ -58,14 +58,20 @@ program main integer :: x end type + type :: t8a + integer, pointer :: x + end type + type, bind(c) :: t9 - !ERROR: Component 'y' of an interoperable derived type must have the BIND attribute - type(t8) :: y + !WARNING: Derived type of component 'x' of an interoperable derived type should have the BIND attribute + type(t8) :: x + !ERROR: Component 'y' of an interoperable derived type must have an interoperable type but does not + type(t8a) :: y integer :: z end type type, bind(c) :: t10 - !WARNING: A CHARACTER component of a BIND(C) type should have length 1 + !WARNING: A CHARACTER component of an interoperable type should have length 1 character(len=2) x end type type, bind(c) :: t11 @@ -73,7 +79,7 @@ program main character(kind=2) x end type type, bind(c) :: t12 - !PORTABILITY: A LOGICAL component of a BIND(C) type should have the interoperable KIND=C_BOOL + !PORTABILITY: A LOGICAL component of an interoperable type should have the interoperable KIND=C_BOOL logical(kind=8) x end type type, bind(c) :: t13 diff --git a/flang/test/Semantics/bindings01.f90 b/flang/test/Semantics/bindings01.f90 index 7f119d4e55bf..7c2dc6448bb3 100644 --- a/flang/test/Semantics/bindings01.f90 +++ b/flang/test/Semantics/bindings01.f90 @@ -4,7 +4,7 @@ module m !ERROR: An ABSTRACT derived type must be extensible - !PORTABILITY: A derived type with the BIND attribute is empty + !PORTABILITY: A derived type with the BIND attribute should not be empty type, abstract, bind(c) :: badAbstract1 end type !ERROR: An ABSTRACT derived type must be extensible @@ -45,7 +45,7 @@ module m end type type, extends(intermediate) :: concrete2 ! ensure no false missing binding error end type - !WARNING: A derived type with the BIND attribute is empty + !WARNING: A derived type with the BIND attribute should not be empty type, bind(c) :: inextensible1 end type !ERROR: The parent type is not extensible diff --git a/flang/test/Semantics/resolve81.f90 b/flang/test/Semantics/resolve81.f90 index 87901fd7d2ef..5f0b66669423 100644 --- a/flang/test/Semantics/resolve81.f90 +++ b/flang/test/Semantics/resolve81.f90 @@ -5,9 +5,9 @@ ! R801 type-declaration-stmt -> ! declaration-type-spec [[, attr-spec]... ::] entity-decl-list ! attr-spec values are: -! PUBLIC, PRIVATE, ALLOCATABLE, ASYNCHRONOUS, CODIMENSION, CONTIGUOUS, -! DIMENSION (array-spec), EXTERNAL, INTENT (intent-spec), INTRINSIC, -! BIND(C), OPTIONAL, PARAMETER, POINTER, PROTECTED, SAVE, TARGET, VALUE, +! PUBLIC, PRIVATE, ALLOCATABLE, ASYNCHRONOUS, CODIMENSION, CONTIGUOUS, +! DIMENSION (array-spec), EXTERNAL, INTENT (intent-spec), INTRINSIC, +! BIND(C), OPTIONAL, PARAMETER, POINTER, PROTECTED, SAVE, TARGET, VALUE, ! VOLATILE module m @@ -28,7 +28,7 @@ module m !WARNING: Attribute 'EXTERNAL' cannot be used more than once real, external, external :: externFunc !WARNING: Attribute 'INTRINSIC' cannot be used more than once - !ERROR: An interface name with BIND attribute must be specified if the BIND attribute is specified in a procedure declaration statement + !ERROR: 'cos' may not have both the BIND(C) and INTRINSIC attributes real, intrinsic, bind(c), intrinsic :: cos !WARNING: Attribute 'BIND(C)' cannot be used more than once integer, bind(c), volatile, bind(c) :: bindVar diff --git a/flang/test/Semantics/resolve85.f90 b/flang/test/Semantics/resolve85.f90 index f598456f9830..9b9358ecf477 100644 --- a/flang/test/Semantics/resolve85.f90 +++ b/flang/test/Semantics/resolve85.f90 @@ -24,7 +24,7 @@ module m end type derived4 !WARNING: Attribute 'BIND(C)' cannot be used more than once - !WARNING: A derived type with the BIND attribute is empty + !WARNING: A derived type with the BIND attribute should not be empty type, bind(c), public, bind(c) :: derived5 end type derived5 -- GitLab From 8fd838a8c499b4ce2822d51d1c661058ccc08c7d Mon Sep 17 00:00:00 2001 From: Harald van Dijk Date: Thu, 9 May 2024 19:15:42 +0100 Subject: [PATCH 188/328] [RISC-V] Limit vscale interleaving to addrspace 0. (#91573) The vlseg and vsseg intrinsic functions are not overloaded on pointer type, so cannot handle non-default address spaces. This fixes an error we see after #90583. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 5 + .../RISCV/interleaved-accesses.ll | 97 +++++++++++++++++++ 2 files changed, 102 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 846768f6d631..00a97d15db3e 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -21048,6 +21048,11 @@ bool RISCVTargetLowering::isLegalInterleavedAccessType( return false; ContainerVT = getContainerForFixedLengthVector(VT.getSimpleVT()); + } else { + // The intrinsics for scalable vectors are not overloaded on pointer type + // and can only handle the default address space. + if (AddrSpace) + return false; } // Need to make sure that EMUL * NFIELDS ≤ 8 diff --git a/llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll b/llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll index 9ae9245eb15d..66ece62bd74f 100644 --- a/llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll +++ b/llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll @@ -23,6 +23,55 @@ define void @load_factor2(ptr %ptr) { ret void } +define void @load_factor2_as(ptr addrspace(1) %ptr) { +; RV32-LABEL: @load_factor2_as( +; RV32-NEXT: [[TMP1:%.*]] = call { <8 x i32>, <8 x i32> } @llvm.riscv.seg2.load.v8i32.p1.i32(ptr addrspace(1) [[PTR:%.*]], i32 8) +; RV32-NEXT: [[TMP2:%.*]] = extractvalue { <8 x i32>, <8 x i32> } [[TMP1]], 1 +; RV32-NEXT: [[TMP3:%.*]] = extractvalue { <8 x i32>, <8 x i32> } [[TMP1]], 0 +; RV32-NEXT: ret void +; +; RV64-LABEL: @load_factor2_as( +; RV64-NEXT: [[TMP1:%.*]] = call { <8 x i32>, <8 x i32> } @llvm.riscv.seg2.load.v8i32.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 8) +; RV64-NEXT: [[TMP2:%.*]] = extractvalue { <8 x i32>, <8 x i32> } [[TMP1]], 1 +; RV64-NEXT: [[TMP3:%.*]] = extractvalue { <8 x i32>, <8 x i32> } [[TMP1]], 0 +; RV64-NEXT: ret void +; + %interleaved.vec = load <16 x i32>, ptr addrspace(1) %ptr + %v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <8 x i32> + %v1 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <8 x i32> + ret void +} + +define void @load_factor2_vscale(ptr %ptr) { +; RV32-LABEL: @load_factor2_vscale( +; RV32-NEXT: [[TMP1:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i32.i32( poison, poison, ptr [[PTR:%.*]], i32 -1) +; RV32-NEXT: ret void +; +; RV64-LABEL: @load_factor2_vscale( +; RV64-NEXT: [[TMP1:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8i32.i64( poison, poison, ptr [[PTR:%.*]], i64 -1) +; RV64-NEXT: ret void +; + %interleaved.vec = load , ptr %ptr + %v = call { , } @llvm.vector.deinterleave2.nxv16i32( %interleaved.vec) + ret void +} + +define void @load_factor2_vscale_as(ptr addrspace(1) %ptr) { +; RV32-LABEL: @load_factor2_vscale_as( +; RV32-NEXT: [[INTERLEAVED_VEC:%.*]] = load , ptr addrspace(1) [[PTR:%.*]], align 64 +; RV32-NEXT: [[V:%.*]] = call { , } @llvm.vector.deinterleave2.nxv16i32( [[INTERLEAVED_VEC]]) +; RV32-NEXT: ret void +; +; RV64-LABEL: @load_factor2_vscale_as( +; RV64-NEXT: [[INTERLEAVED_VEC:%.*]] = load , ptr addrspace(1) [[PTR:%.*]], align 64 +; RV64-NEXT: [[V:%.*]] = call { , } @llvm.vector.deinterleave2.nxv16i32( [[INTERLEAVED_VEC]]) +; RV64-NEXT: ret void +; + %interleaved.vec = load , ptr addrspace(1) %ptr + %v = call { , } @llvm.vector.deinterleave2.nxv16i32( %interleaved.vec) + ret void +} + define void @load_factor3(ptr %ptr) { ; RV32-LABEL: @load_factor3( ; RV32-NEXT: [[TMP1:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.riscv.seg3.load.v4i32.p0.i32(ptr [[PTR:%.*]], i32 4) @@ -219,6 +268,54 @@ define void @store_factor2(ptr %ptr, <8 x i8> %v0, <8 x i8> %v1) { ret void } +define void @store_factor2_as(ptr addrspace(1) %ptr, <8 x i8> %v0, <8 x i8> %v1) { +; RV32-LABEL: @store_factor2_as( +; RV32-NEXT: [[TMP1:%.*]] = shufflevector <8 x i8> [[V0:%.*]], <8 x i8> [[V1:%.*]], <8 x i32> +; RV32-NEXT: [[TMP2:%.*]] = shufflevector <8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i32> +; RV32-NEXT: call void @llvm.riscv.seg2.store.v8i8.p1.i32(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]], ptr addrspace(1) [[PTR:%.*]], i32 8) +; RV32-NEXT: ret void +; +; RV64-LABEL: @store_factor2_as( +; RV64-NEXT: [[TMP1:%.*]] = shufflevector <8 x i8> [[V0:%.*]], <8 x i8> [[V1:%.*]], <8 x i32> +; RV64-NEXT: [[TMP2:%.*]] = shufflevector <8 x i8> [[V0]], <8 x i8> [[V1]], <8 x i32> +; RV64-NEXT: call void @llvm.riscv.seg2.store.v8i8.p1.i64(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]], ptr addrspace(1) [[PTR:%.*]], i64 8) +; RV64-NEXT: ret void +; + %interleaved.vec = shufflevector <8 x i8> %v0, <8 x i8> %v1, <16 x i32> + store <16 x i8> %interleaved.vec, ptr addrspace(1) %ptr, align 4 + ret void +} + +define void @store_factor2_vscale(ptr %ptr, %v0, %v1) { +; RV32-LABEL: @store_factor2_vscale( +; RV32-NEXT: call void @llvm.riscv.vsseg2.nxv8i8.i32( [[V0:%.*]], [[V1:%.*]], ptr [[PTR:%.*]], i32 -1) +; RV32-NEXT: ret void +; +; RV64-LABEL: @store_factor2_vscale( +; RV64-NEXT: call void @llvm.riscv.vsseg2.nxv8i8.i64( [[V0:%.*]], [[V1:%.*]], ptr [[PTR:%.*]], i64 -1) +; RV64-NEXT: ret void +; + %interleaved.vec = call @llvm.vector.interleave2.nxv8i8( %v0, %v1) + store %interleaved.vec, ptr %ptr, align 4 + ret void +} + +define void @store_factor2_vscale_as(ptr addrspace(1) %ptr, %v0, %v1) { +; RV32-LABEL: @store_factor2_vscale_as( +; RV32-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.vector.interleave2.nxv16i8( [[V0:%.*]], [[V1:%.*]]) +; RV32-NEXT: store [[INTERLEAVED_VEC]], ptr addrspace(1) [[PTR:%.*]], align 4 +; RV32-NEXT: ret void +; +; RV64-LABEL: @store_factor2_vscale_as( +; RV64-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.vector.interleave2.nxv16i8( [[V0:%.*]], [[V1:%.*]]) +; RV64-NEXT: store [[INTERLEAVED_VEC]], ptr addrspace(1) [[PTR:%.*]], align 4 +; RV64-NEXT: ret void +; + %interleaved.vec = call @llvm.vector.interleave2.nxv8i8( %v0, %v1) + store %interleaved.vec, ptr addrspace(1) %ptr, align 4 + ret void +} + define void @store_factor3(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) { ; RV32-LABEL: @store_factor3( ; RV32-NEXT: [[S0:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <8 x i32> -- GitLab From c3d2af0f4e180e67c4c5dd0f83bed1ea226f4565 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Thu, 9 May 2024 19:18:36 +0100 Subject: [PATCH 189/328] [VPlan] VPEVLBasedIVPHI is a VPSingleDefRecipe. VPEVLBasedIVPHIRecipe inherits from VPSingleDefRecipe. Add VPEVLBasedIVPHISC to VPSingleDefRecipe::classof to make isa/dyn_cast & co work as expected. Split off https://github.com/llvm/llvm-project/pull/67934. --- llvm/lib/Transforms/Vectorize/VPlan.h | 1 + llvm/unittests/Transforms/Vectorize/VPlanTest.cpp | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index 461d7ec59862..0784665efd14 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -841,6 +841,7 @@ public: static inline bool classof(const VPRecipeBase *R) { switch (R->getVPDefID()) { case VPRecipeBase::VPDerivedIVSC: + case VPRecipeBase::VPEVLBasedIVPHISC: case VPRecipeBase::VPExpandSCEVSC: case VPRecipeBase::VPInstructionSC: case VPRecipeBase::VPReductionSC: diff --git a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp index eda4723f67b2..5c45d86130bd 100644 --- a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp +++ b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp @@ -1530,5 +1530,13 @@ TEST(VPDoubleValueDefTest, traverseUseLists) { EXPECT_EQ(&DoubleValueDef, I3.getOperand(0)->getDefiningRecipe()); } +TEST(VPRecipeTest, CastToVPSingleDefRecipe) { + VPValue Start; + VPEVLBasedIVPHIRecipe R(&Start, {}); + VPRecipeBase *B = &R; + EXPECT_TRUE(isa(B)); + // TODO: check other VPSingleDefRecipes. +} + } // namespace } // namespace llvm -- GitLab From b942c24845a39e6161c8623b1efc4e2083d879e9 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 9 May 2024 11:19:03 -0700 Subject: [PATCH 190/328] [flang] Don't crash on not-yet-implemented feature (#91368) A procedure pointer can be initialized in a DATA statement, but semantics crashes if the initializer is the name of an intrinsic function. This patch fixes that crash so that compilation survives to the point where lowering admits that it doesn't yet support the feature. Addresses https://github.com/llvm/llvm-project/issues/91295. --- flang/lib/Semantics/data-to-inits.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/flang/lib/Semantics/data-to-inits.cpp b/flang/lib/Semantics/data-to-inits.cpp index 64050874bcde..605a9f10712e 100644 --- a/flang/lib/Semantics/data-to-inits.cpp +++ b/flang/lib/Semantics/data-to-inits.cpp @@ -903,7 +903,13 @@ void ConstructInitializer(const Symbol &symbol, if (const auto *procDesignator{ std::get_if(&expr->u)}) { CHECK(!procDesignator->GetComponent()); - mutableProc.set_init(DEREF(procDesignator->GetSymbol())); + if (const auto *intrin{procDesignator->GetSpecificIntrinsic()}) { + const Symbol *intrinSymbol{ + symbol.owner().FindSymbol(SourceName{intrin->name})}; + mutableProc.set_init(DEREF(intrinSymbol)); + } else { + mutableProc.set_init(DEREF(procDesignator->GetSymbol())); + } } else { CHECK(evaluate::IsNullProcedurePointer(*expr)); mutableProc.set_init(nullptr); -- GitLab From 19b41f40a4b93a6243c816b80b6e664a4418f79f Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 9 May 2024 11:31:13 -0700 Subject: [PATCH 191/328] [flang] Complete RESULT() name constraint checking (#91476) There are two constraints in the language that prohibit the use of an ENTRY name being used as the RESULT() variable of the function or another ENTRY name in the same function's scope; neither can the name of the function be used as the RESULT() of an ENTRY. Move most of the existing partial enforcement of these constraints from name resolution into declaration checking, complete it, and add more cases to the tests. --- flang/lib/Semantics/check-declarations.cpp | 23 +++++++++- flang/lib/Semantics/resolve-names.cpp | 49 +++++++++------------- flang/test/Semantics/entry01.f90 | 15 ++++++- 3 files changed, 54 insertions(+), 33 deletions(-) diff --git a/flang/lib/Semantics/check-declarations.cpp b/flang/lib/Semantics/check-declarations.cpp index 9ef34f0f81c0..26efa288b5ae 100644 --- a/flang/lib/Semantics/check-declarations.cpp +++ b/flang/lib/Semantics/check-declarations.cpp @@ -1361,7 +1361,7 @@ void CheckHelper::CheckSubprogram( SubprogramMatchHelper{*this}.Check(symbol, *iface); } if (const Scope *entryScope{details.entryScope()}) { - // ENTRY 15.6.2.6, esp. C1571 + // ENTRY F'2023 15.6.2.6 std::optional error; const Symbol *subprogram{entryScope->symbol()}; const SubprogramDetails *subprogramDetails{nullptr}; @@ -1393,6 +1393,27 @@ void CheckHelper::CheckSubprogram( } } } + if (details.isFunction() && + details.result().name() != symbol.name()) { // F'2023 C1569 & C1583 + if (auto iter{symbol.owner().find(details.result().name())}; + iter != symbol.owner().end()) { + const Symbol &resNameSym{*iter->second}; + if (const auto *resNameSubp{resNameSym.detailsIf()}) { + if (const Scope * resNameEntryScope{resNameSubp->entryScope()}) { + const Scope *myScope{ + details.entryScope() ? details.entryScope() : symbol.scope()}; + if (resNameEntryScope == myScope) { + if (auto *msg{messages_.Say(symbol.name(), + "Explicit RESULT('%s') of function '%s' cannot have the same name as a distinct ENTRY into the same scope"_err_en_US, + details.result().name(), symbol.name())}) { + msg->Attach( + resNameSym.name(), "ENTRY with conflicting name"_en_US); + } + } + } + } + } + } if (const MaybeExpr & stmtFunction{details.stmtFunction()}) { if (auto msg{evaluate::CheckStatementFunction( symbol, *stmtFunction, context_.foldingContext())}) { diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index 4df347a878de..e2875081b732 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -4048,27 +4048,10 @@ void SubprogramVisitor::CreateEntry( attrs = extant->attrs(); } } - bool badResultName{false}; std::optional distinctResultName; if (suffix && suffix->resultName && suffix->resultName->source != entryName.source) { distinctResultName = suffix->resultName->source; - const parser::Name &resultName{*suffix->resultName}; - if (resultName.source == subprogram.name()) { // C1574 - Say2(resultName.source, - "RESULT(%s) may not have the same name as the function"_err_en_US, - subprogram, "Containing function"_en_US); - badResultName = true; - } else if (const Symbol * extant{FindSymbol(outer, resultName)}) { // C1574 - if (const auto *details{extant->detailsIf()}) { - if (details->entryScope() == &currScope()) { - Say2(resultName.source, - "RESULT(%s) may not have the same name as an ENTRY in the function"_err_en_US, - extant->name(), "Conflicting ENTRY"_en_US); - badResultName = true; - } - } - } } if (outer.IsModule() && !attrs.test(Attr::PRIVATE)) { attrs.set(Attr::PUBLIC); @@ -4104,17 +4087,24 @@ void SubprogramVisitor::CreateEntry( EntityDetails resultDetails; resultDetails.set_funcResult(true); if (distinctResultName) { - if (!badResultName) { - // RESULT(x) can be the same explicitly-named RESULT(x) as - // the enclosing function or another ENTRY. - if (auto iter{currScope().find(suffix->resultName->source)}; - iter != currScope().end()) { - result = &*iter->second; - } - if (!result) { - result = &MakeSymbol( - *distinctResultName, Attrs{}, std::move(resultDetails)); - } + // An explicit RESULT() can also be an explicit RESULT() + // of the function or another ENTRY. + if (auto iter{currScope().find(suffix->resultName->source)}; + iter != currScope().end()) { + result = &*iter->second; + } + if (!result) { + result = + &MakeSymbol(*distinctResultName, Attrs{}, std::move(resultDetails)); + } else if (!result->has()) { + Say(*distinctResultName, + "ENTRY cannot have RESULT(%s) that is not a variable"_err_en_US, + *distinctResultName) + .Attach(result->name(), "Existing declaration of '%s'"_en_US, + result->name()); + result = nullptr; + } + if (result) { Resolve(*suffix->resultName, *result); } } else { @@ -4124,8 +4114,7 @@ void SubprogramVisitor::CreateEntry( entryDetails.set_result(*result); } } - if (subpFlag == Symbol::Flag::Subroutine || - (distinctResultName && !badResultName)) { + if (subpFlag == Symbol::Flag::Subroutine || distinctResultName) { Symbol &assoc{MakeSymbol(entryName.source)}; assoc.set_details(HostAssocDetails{*entrySymbol}); assoc.set(Symbol::Flag::Subroutine); diff --git a/flang/test/Semantics/entry01.f90 b/flang/test/Semantics/entry01.f90 index 64bd954f8ae0..970cd109921a 100644 --- a/flang/test/Semantics/entry01.f90 +++ b/flang/test/Semantics/entry01.f90 @@ -86,11 +86,12 @@ function ifunc() entry ibad2() !ERROR: ENTRY in a function may not have an alternate return dummy argument entry ibadalt(*) ! C1573 - !ERROR: RESULT(ifunc) may not have the same name as the function + !ERROR: ENTRY cannot have RESULT(ifunc) that is not a variable entry isameres() result(ifunc) ! C1574 entry iok() - !ERROR: RESULT(iok) may not have the same name as an ENTRY in the function + !ERROR: Explicit RESULT('iok') of function 'isameres2' cannot have the same name as a distinct ENTRY into the same scope entry isameres2() result(iok) ! C1574 + !ERROR: Explicit RESULT('iok2') of function 'isameres3' cannot have the same name as a distinct ENTRY into the same scope entry isameres3() result(iok2) ! C1574 !ERROR: 'iok2' is already declared in this scoping unit entry iok2() @@ -255,3 +256,13 @@ subroutine s7(q,q) !ERROR: 'z' appears more than once as a dummy argument name in this ENTRY statement entry baz(z,z) end + +!ERROR: Explicit RESULT('f8e1') of function 'f8' cannot have the same name as a distinct ENTRY into the same scope +function f8() result(f8e1) + entry f8e1() + entry f8e2() result(f8e2) ! ok + !ERROR: Explicit RESULT('f8e1') of function 'f8e3' cannot have the same name as a distinct ENTRY into the same scope + entry f8e3() result(f8e1) + !ERROR: ENTRY cannot have RESULT(f8) that is not a variable + entry f8e4() result(f8) +end -- GitLab From a51d92a44740fd1b17930de183c9ad6d993029b1 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Thu, 9 May 2024 11:42:25 -0700 Subject: [PATCH 192/328] [flang] Fix crash in semantics on error case (#91482) An erroneous statement function declaration exposed an unhandled situation in a utility routine in semantics. Patch that hole and add a test. Fixes https://github.com/llvm/llvm-project/issues/91429. --- flang/lib/Semantics/tools.cpp | 14 ++++++++------ flang/test/Semantics/stmt-func01.f90 | 8 ++++++++ 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/flang/lib/Semantics/tools.cpp b/flang/lib/Semantics/tools.cpp index 2d0caff82eb2..99381918fc63 100644 --- a/flang/lib/Semantics/tools.cpp +++ b/flang/lib/Semantics/tools.cpp @@ -256,15 +256,17 @@ static const Symbol &FollowHostAssoc(const Symbol &symbol) { } bool IsHostAssociated(const Symbol &symbol, const Scope &scope) { - return DoesScopeContain( - &GetProgramUnitOrBlockConstructContaining(FollowHostAssoc(symbol)), - GetProgramUnitOrBlockConstructContaining(scope)); + const Symbol &base{FollowHostAssoc(symbol)}; + return base.owner().IsTopLevel() || + DoesScopeContain(&GetProgramUnitOrBlockConstructContaining(base), + GetProgramUnitOrBlockConstructContaining(scope)); } bool IsHostAssociatedIntoSubprogram(const Symbol &symbol, const Scope &scope) { - return DoesScopeContain( - &GetProgramUnitOrBlockConstructContaining(FollowHostAssoc(symbol)), - GetProgramUnitContaining(scope)); + const Symbol &base{FollowHostAssoc(symbol)}; + return base.owner().IsTopLevel() || + DoesScopeContain(&GetProgramUnitOrBlockConstructContaining(base), + GetProgramUnitContaining(scope)); } bool IsInStmtFunction(const Symbol &symbol) { diff --git a/flang/test/Semantics/stmt-func01.f90 b/flang/test/Semantics/stmt-func01.f90 index 733a7a56dfdb..3c9ffa565900 100644 --- a/flang/test/Semantics/stmt-func01.f90 +++ b/flang/test/Semantics/stmt-func01.f90 @@ -83,3 +83,11 @@ subroutine s4 !ERROR: VOLATILE attribute may apply only to a variable sf(x) = 1. end + +subroutine s5 + !ERROR: Invalid specification expression: reference to impure function 'k' + real x(k()) + !WARNING: Name 'k' from host scope should have a type declaration before its local statement function definition + !ERROR: 'k' is already declared in this scoping unit + k() = 0.0 +end -- GitLab From dcf92a249233cab103f848dd12e96e0d642a8899 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Thu, 9 May 2024 23:03:42 +0400 Subject: [PATCH 193/328] [clang][NFC] Add examples from [dcl.init.aggr] to C++ conformance tests (#91435) This patch adds examples from 2024-04-22 draft of [[dcl.init.aggr]](http://eel.is/c++draft/dcl.init.aggr) to C++ conformance tests. Testing is done via constant evaluation and static asserts. As far as I can see, the rest of the conformance suite is typically testing the latest language mode at the time of writing (with a notable exception of defect report tests), so I'm also testing in the latest language mode. --- clang/test/CXX/dcl/dcl.init/aggr.cpp | 294 +++++++++++++++++++++++++++ 1 file changed, 294 insertions(+) create mode 100644 clang/test/CXX/dcl/dcl.init/aggr.cpp diff --git a/clang/test/CXX/dcl/dcl.init/aggr.cpp b/clang/test/CXX/dcl/dcl.init/aggr.cpp new file mode 100644 index 000000000000..3206d2e7f616 --- /dev/null +++ b/clang/test/CXX/dcl/dcl.init/aggr.cpp @@ -0,0 +1,294 @@ +// RUN: %clang_cc1 -std=c++2c -verify %s + +namespace ex1 { +struct C { + union { + int a; + const char* p; + }; + int x; +}; + +constexpr C c = { .a = 1, .x = 3 }; +static_assert(c.a == 1); +static_assert(c.x == 3); + +static constexpr C c2 = { .a = 1.0, .x = 3 }; +// expected-error@-1 {{type 'double' cannot be narrowed to 'int' in initializer list}} +// expected-note@-2 {{insert an explicit cast to silence this issue}} +} // namespace ex1 + +namespace ex2 { +struct A { + int x; + struct B { + int i; + int j; + } b; +}; + +constexpr A a = { 1, { 2, 3 } }; +static_assert(a.x == 1); +static_assert(a.b.i == 2); +static_assert(a.b.j == 3); + +struct base1 { int b1, b2 = 42; }; +struct base2 { + constexpr base2() { + b3 = 43; + } + int b3; +}; +struct derived : base1, base2 { + int d; +}; + +constexpr derived d1{{1, 2}, {}, 4}; +static_assert(d1.b1 == 1); +static_assert(d1.b2 == 2); +static_assert(d1.b3 == 43); +static_assert(d1.d == 4); + +constexpr derived d2{{}, {}, 4}; +static_assert(d2.b1 == 0); +static_assert(d2.b2 == 42); +static_assert(d2.b3 == 43); +static_assert(d2.d == 4); +} // namespace ex2 + +namespace ex3 { +struct S { + int a; + const char* b; + int c; + int d = b[a]; +}; + +constexpr S ss = { 1, "asdf" }; +static_assert(ss.a == 1); +static_assert(__builtin_strcmp(ss.b, "asdf") == 0); +static_assert(ss.c == int{}); +static_assert(ss.d == ss.b[ss.a]); + +struct string { + int d = 43; +}; + +struct A { + string a; + int b = 42; + int c = -1; +}; + +constexpr A a{.c = 21}; +static_assert(a.a.d == string{}.d); +static_assert(a.b == 42); +static_assert(a.c == 21); +} // namespace ex3 + +namespace ex4 { +int x[] = { 1, 3, 5 }; +static_assert(sizeof(x) / sizeof(int) == 3); +} // namespace ex4 + +namespace ex5 { +struct X { int i, j, k; }; + +constexpr X a[] = { 1, 2, 3, 4, 5, 6 }; +constexpr X b[2] = { { 1, 2, 3 }, { 4, 5, 6 } }; +static_assert(sizeof(a) == sizeof(b)); +static_assert(a[0].i == b[0].i); +static_assert(a[0].j == b[0].j); +static_assert(a[0].k == b[0].k); +static_assert(a[1].i == b[1].i); +static_assert(a[1].j == b[1].j); +static_assert(a[1].k == b[1].k); +} // namespace ex5 + +namespace ex6 { +struct S { + int y[] = { 0 }; + // expected-error@-1 {{array bound cannot be deduced from a default member initializer}} +}; +} // namespace ex6 + +namespace ex7 { +struct A { + int i; + static int s; + int j; + int :17; + int k; +}; + +constexpr A a = { 1, 2, 3 }; +static_assert(a.i == 1); +static_assert(a.j == 2); +static_assert(a.k == 3); +} // namespace ex7 + +namespace ex8 { +struct A; +extern A a; +struct A { + const A& a1 { A{a,a} }; + const A& a2 { A{} }; + // expected-error@-1 {{default member initializer for 'a2' needed within definition of enclosing class 'A' outside of member functions}} + // expected-note@-2 {{default member initializer declared here}} +}; +A a{a,a}; + +struct B { + int n = B{}.n; + // expected-error@-1 {{default member initializer for 'n' needed within definition of enclosing class 'B' outside of member functions}} + // expected-note@-2 {{default member initializer declared here}} +}; +} // namespace ex8 + +namespace ex9 { +constexpr int x[2][2] = { 3, 1, 4, 2 }; +static_assert(x[0][0] == 3); +static_assert(x[0][1] == 1); +static_assert(x[1][0] == 4); +static_assert(x[1][1] == 2); + +constexpr float y[4][3] = { + { 1 }, { 2 }, { 3 }, { 4 } +}; +static_assert(y[0][0] == 1); +static_assert(y[0][1] == 0); +static_assert(y[0][2] == 0); +static_assert(y[1][0] == 2); +static_assert(y[1][1] == 0); +static_assert(y[1][2] == 0); +static_assert(y[2][0] == 3); +static_assert(y[2][1] == 0); +static_assert(y[2][2] == 0); +static_assert(y[3][0] == 4); +static_assert(y[3][1] == 0); +static_assert(y[3][2] == 0); +} // namespace ex9 + +namespace ex10 { +struct S1 { int a, b; }; +struct S2 { S1 s, t; }; + +constexpr S2 x[2] = { 1, 2, 3, 4, 5, 6, 7, 8 }; +constexpr S2 y[2] = { + { + { 1, 2 }, + { 3, 4 } + }, + { + { 5, 6 }, + { 7, 8 } + } +}; +static_assert(x[0].s.a == 1); +static_assert(x[0].s.b == 2); +static_assert(x[0].t.a == 3); +static_assert(x[0].t.b == 4); +static_assert(x[1].s.a == 5); +static_assert(x[1].s.b == 6); +static_assert(x[1].t.a == 7); +static_assert(x[1].t.b == 8); +} // namespace ex10 + +namespace ex11 { +char cv[4] = { 'a', 's', 'd', 'f', 0 }; +// expected-error@-1 {{excess elements in array initializer}} +} // namespace ex11 + +namespace ex12 { +constexpr float y[4][3] = { + { 1, 3, 5 }, + { 2, 4, 6 }, + { 3, 5, 7 }, +}; +static_assert(y[0][0] == 1); +static_assert(y[0][1] == 3); +static_assert(y[0][2] == 5); +static_assert(y[1][0] == 2); +static_assert(y[1][1] == 4); +static_assert(y[1][2] == 6); +static_assert(y[2][0] == 3); +static_assert(y[2][1] == 5); +static_assert(y[2][2] == 7); +static_assert(y[3][0] == 0.0); +static_assert(y[3][1] == 0.0); +static_assert(y[3][2] == 0.0); + +constexpr float z[4][3] = { + 1, 3, 5, 2, 4, 6, 3, 5, 7 +}; +static_assert(z[0][0] == 1); +static_assert(z[0][1] == 3); +static_assert(z[0][2] == 5); +static_assert(z[1][0] == 2); +static_assert(z[1][1] == 4); +static_assert(z[1][2] == 6); +static_assert(z[2][0] == 3); +static_assert(z[2][1] == 5); +static_assert(z[2][2] == 7); +static_assert(z[3][0] == 0.0); +static_assert(z[3][1] == 0.0); +static_assert(z[3][2] == 0.0); +} // namespace ex12 + +namespace ex13 { +struct S { } s; +struct A { + S s1; + int i1; + S s2; + int i2; + S s3; + int i3; +} a = { + { }, // Required initialization + 0, + s, // Required initialization + 0 +}; // Initialization not required for A​::​s3 because A​::​i3 is also not initialized +} // namespace ex13 + +namespace ex14 { +struct A { + int i; + constexpr operator int() const { return 42; }; +}; +struct B { + A a1, a2; + int z; +}; +constexpr A a{}; +constexpr B b = { 4, a, a }; +static_assert(b.a1.i == 4); +static_assert(b.a2.i == a.i); +static_assert(b.z == a.operator int()); +} // namespace ex14 + +namespace ex15 { +union u { // #ex15-u + int a; + const char* b; +}; + +u a = { 1 }; +u b = a; +u c = 1; +// expected-error@-1 {{no viable conversion from 'int' to 'u'}} +// expected-note@#ex15-u {{candidate constructor (the implicit copy constructor) not viable: no known conversion from 'int' to 'const u &' for 1st argument}} +// expected-note@#ex15-u {{candidate constructor (the implicit move constructor) not viable: no known conversion from 'int' to 'u &&' for 1st argument}} +u d = { 0, "asdf" }; +// expected-error@-1 {{excess elements in union initializer}} +u e = { "asdf" }; +// expected-error@-1 {{cannot initialize a member subobject of type 'int' with an lvalue of type 'const char[5]'}} +u f = { .b = "asdf" }; +u g = { + .a = 1, // #ex15-g-a + .b = "asdf" + // expected-error@-1 {{initializer partially overrides prior initialization of this subobject}} + // expected-note@#ex15-g-a {{previous initialization is here}} +}; +} // namespace ex15 -- GitLab From d36b4abb51a9f84d436f184581b15021fdf22114 Mon Sep 17 00:00:00 2001 From: Keith Smiley Date: Thu, 9 May 2024 13:14:03 -0700 Subject: [PATCH 194/328] [bazel] Rework liblldb (#91549) Previously we were linking liblldb as a shared library, but also linking the contents into the lldb binary. This is invalid and results in subtle runtime issues because of duplicate constants, like the global plugin registry. This now links the dylib to lldb directly. This requires we switch to cc_binary instead because cc_shared_library expects your library to export all symbols in your transitive dependency tree, where we only want to export lldb symbols. --- .../llvm-project-overlay/lldb/BUILD.bazel | 69 +++++++++++++------ 1 file changed, 48 insertions(+), 21 deletions(-) diff --git a/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel b/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel index 8fb90e850f00..b3a413c401cd 100644 --- a/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel @@ -728,37 +728,64 @@ cc_library( ], ) -cc_library( - name = "liblldb.static", - deps = [ - ":API", - ":Interpreter", - ], +genrule( + name = "gen_exports_file_linux", + srcs = ["//lldb:source/API/liblldb-private.exports"], + outs = ["exports_linux.txt"], + cmd = """ +cat > $(OUTS) < Date: Thu, 9 May 2024 16:34:40 -0400 Subject: [PATCH 195/328] [Clang][Sema] Revert changes to operator= lookup in templated classes from #91498, #90999, and #90152 (#91620) This reverts changes in #91498, #90999, and #90152 which make `operator=` dependent whenever the current class is templated. --- clang/lib/Sema/SemaExprMember.cpp | 5 +- clang/lib/Sema/SemaLookup.cpp | 51 +++++++------------ clang/lib/Sema/SemaTemplate.cpp | 8 ++- .../temp.res/temp.dep/temp.dep.type/p4.cpp | 2 +- 4 files changed, 28 insertions(+), 38 deletions(-) diff --git a/clang/lib/Sema/SemaExprMember.cpp b/clang/lib/Sema/SemaExprMember.cpp index 5facb14a18b7..9fa69da4f968 100644 --- a/clang/lib/Sema/SemaExprMember.cpp +++ b/clang/lib/Sema/SemaExprMember.cpp @@ -996,7 +996,10 @@ Sema::BuildMemberReferenceExpr(Expr *BaseExpr, QualType BaseExprType, // build a CXXDependentScopeMemberExpr. if (R.wasNotFoundInCurrentInstantiation() || (IsArrow && !BaseExprType->isPointerType() && - BaseExprType->isDependentType())) + BaseExprType->isDependentType()) || + (R.getLookupName().getCXXOverloadedOperator() == OO_Equal && + (SS.isSet() ? SS.getScopeRep()->isDependent() + : BaseExprType->isDependentType()))) return ActOnDependentMemberExpr(BaseExpr, BaseExprType, IsArrow, OpLoc, SS, TemplateKWLoc, FirstQualifierInScope, R.getLookupNameInfo(), TemplateArgs); diff --git a/clang/lib/Sema/SemaLookup.cpp b/clang/lib/Sema/SemaLookup.cpp index e20de338ebb1..7251aabc6af2 100644 --- a/clang/lib/Sema/SemaLookup.cpp +++ b/clang/lib/Sema/SemaLookup.cpp @@ -1267,20 +1267,6 @@ struct FindLocalExternScope { LookupResult &R; bool OldFindLocalExtern; }; - -/// Returns true if 'operator=' should be treated as a dependent name. -bool isDependentAssignmentOperator(DeclarationName Name, - DeclContext *LookupContext) { - const auto *LookupRecord = dyn_cast_if_present(LookupContext); - // If the lookup context is the current instantiation but we are outside a - // complete-class context, we will never find the implicitly declared - // copy/move assignment operators because they are declared at the closing '}' - // of the class specifier. In such cases, we treat 'operator=' like any other - // unqualified name because the results of name lookup in the template - // definition/instantiation context will always be the same. - return Name.getCXXOverloadedOperator() == OO_Equal && LookupRecord && - !LookupRecord->isBeingDefined() && LookupRecord->isDependentContext(); -} } // end anonymous namespace bool Sema::CppLookupName(LookupResult &R, Scope *S) { @@ -1289,6 +1275,14 @@ bool Sema::CppLookupName(LookupResult &R, Scope *S) { DeclarationName Name = R.getLookupName(); Sema::LookupNameKind NameKind = R.getLookupKind(); + // If this is the name of an implicitly-declared special member function, + // go through the scope stack to implicitly declare + if (isImplicitlyDeclaredMemberFunctionName(Name)) { + for (Scope *PreS = S; PreS; PreS = PreS->getParent()) + if (DeclContext *DC = PreS->getEntity()) + DeclareImplicitMemberFunctionsWithName(*this, Name, R.getNameLoc(), DC); + } + // C++23 [temp.dep.general]p2: // The component name of an unqualified-id is dependent if // - it is a conversion-function-id whose conversion-type-id @@ -1301,20 +1295,6 @@ bool Sema::CppLookupName(LookupResult &R, Scope *S) { return false; } - // If this is the name of an implicitly-declared special member function, - // go through the scope stack to implicitly declare - if (isImplicitlyDeclaredMemberFunctionName(Name)) { - for (Scope *PreS = S; PreS; PreS = PreS->getParent()) - if (DeclContext *DC = PreS->getEntity()) { - if (!R.isTemplateNameLookup() && - isDependentAssignmentOperator(Name, DC)) { - R.setNotFoundInCurrentInstantiation(); - return false; - } - DeclareImplicitMemberFunctionsWithName(*this, Name, R.getNameLoc(), DC); - } - } - // Implicitly declare member functions with the name we're looking for, if in // fact we are in a scope where it matters. @@ -2478,6 +2458,10 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, } } QL(LookupCtx); + CXXRecordDecl *LookupRec = dyn_cast(LookupCtx); + // FIXME: Per [temp.dep.general]p2, an unqualified name is also dependent + // if it's a dependent conversion-function-id or operator= where the current + // class is a templated entity. This should be handled in LookupName. if (!InUnqualifiedLookup && !R.isForRedeclaration()) { // C++23 [temp.dep.type]p5: // A qualified name is dependent if @@ -2488,16 +2472,13 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, // is operator=, or // - [...] if (DeclarationName Name = R.getLookupName(); - (Name.getNameKind() == DeclarationName::CXXConversionFunctionName && - Name.getCXXNameType()->isDependentType()) || - (!R.isTemplateNameLookup() && - isDependentAssignmentOperator(Name, LookupCtx))) { + Name.getNameKind() == DeclarationName::CXXConversionFunctionName && + Name.getCXXNameType()->isDependentType()) { R.setNotFoundInCurrentInstantiation(); return false; } } - CXXRecordDecl *LookupRec = dyn_cast(LookupCtx); if (LookupDirect(*this, R, LookupCtx)) { R.resolveKind(); if (LookupRec) @@ -2588,6 +2569,8 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, return true; }; + bool TemplateNameLookup = R.isTemplateNameLookup(); + // Determine whether two sets of members contain the same members, as // required by C++ [class.member.lookup]p6. auto HasSameDeclarations = [&](DeclContext::lookup_iterator A, @@ -2609,7 +2592,7 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, // template, and if the name is used as a template-name, the // reference refers to the class template itself and not a // specialization thereof, and is not ambiguous. - if (R.isTemplateNameLookup()) + if (TemplateNameLookup) if (auto *TD = getAsTemplateNameDecl(ND)) ND = TD; diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index 480bc74c2001..2fce2238f9c1 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -726,7 +726,7 @@ Sema::ActOnDependentIdExpression(const CXXScopeSpec &SS, const DeclarationNameInfo &NameInfo, bool isAddressOfOperand, const TemplateArgumentListInfo *TemplateArgs) { - QualType ThisType = getCurrentThisType(); + DeclContext *DC = getFunctionLevelDeclContext(); // C++11 [expr.prim.general]p12: // An id-expression that denotes a non-static data member or non-static @@ -748,7 +748,11 @@ Sema::ActOnDependentIdExpression(const CXXScopeSpec &SS, IsEnum = isa_and_nonnull(NNS->getAsType()); if (!MightBeCxx11UnevalField && !isAddressOfOperand && !IsEnum && - !ThisType.isNull()) { + isa(DC) && + cast(DC)->isImplicitObjectMemberFunction()) { + QualType ThisType = + cast(DC)->getThisType().getNonReferenceType(); + // Since the 'this' expression is synthesized, we don't need to // perform the double-lookup check. NamedDecl *FirstQualifierInScope = nullptr; diff --git a/clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/p4.cpp b/clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/p4.cpp index 43053c18c507..1adbc33a701c 100644 --- a/clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/p4.cpp +++ b/clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/p4.cpp @@ -483,7 +483,6 @@ namespace N3 { }; template struct E; // expected-note {{in instantiation of template class 'N3::E' requested here}} - } // namespace N3 namespace N4 { @@ -551,4 +550,5 @@ namespace N4 { }; template void D::instantiated(D); // expected-note {{in instantiation of}} + } // namespace N4 -- GitLab From 8ac928fea8d561261133e0337a2777fcda99f7ba Mon Sep 17 00:00:00 2001 From: Schrodinger ZHU Yifan Date: Thu, 9 May 2024 16:34:45 -0400 Subject: [PATCH 196/328] [libc][NFC] adjust time related implementations (#91485) --- libc/hdr/CMakeLists.txt | 9 ++++ libc/hdr/time_macros.h | 22 +++++++++ libc/hdr/types/CMakeLists.txt | 45 +++++++++++++++++++ libc/hdr/types/clock_t.h | 22 +++++++++ libc/hdr/types/clockid_t.h | 22 +++++++++ libc/hdr/types/struct_timeval.h | 21 +++++++++ libc/hdr/types/suseconds_t.h | 22 +++++++++ libc/hdr/types/time_t.h | 22 +++++++++ libc/src/__support/CMakeLists.txt | 2 + libc/src/__support/time/CMakeLists.txt | 19 ++++++++ libc/src/__support/time/clock_gettime.h | 23 ++++++++++ libc/src/__support/time/linux/CMakeLists.txt | 14 ++++++ .../time/linux/clock_gettime.cpp} | 25 ++++------- libc/src/__support/time/units.h | 38 ++++++++++++++++ libc/src/time/clock.h | 2 +- libc/src/time/clock_gettime.h | 5 ++- libc/src/time/gettimeofday.h | 2 +- libc/src/time/linux/CMakeLists.txt | 30 +++++++------ libc/src/time/linux/clock.cpp | 20 ++++----- libc/src/time/linux/clock_gettime.cpp | 9 +--- libc/src/time/linux/gettimeofday.cpp | 14 +++--- libc/src/time/linux/time.cpp | 12 ++--- libc/src/time/nanosleep.h | 4 +- libc/src/time/time_func.h | 2 +- 24 files changed, 335 insertions(+), 71 deletions(-) create mode 100644 libc/hdr/time_macros.h create mode 100644 libc/hdr/types/clock_t.h create mode 100644 libc/hdr/types/clockid_t.h create mode 100644 libc/hdr/types/struct_timeval.h create mode 100644 libc/hdr/types/suseconds_t.h create mode 100644 libc/hdr/types/time_t.h create mode 100644 libc/src/__support/time/CMakeLists.txt create mode 100644 libc/src/__support/time/clock_gettime.h create mode 100644 libc/src/__support/time/linux/CMakeLists.txt rename libc/src/{time/linux/clockGetTimeImpl.h => __support/time/linux/clock_gettime.cpp} (64%) create mode 100644 libc/src/__support/time/units.h diff --git a/libc/hdr/CMakeLists.txt b/libc/hdr/CMakeLists.txt index 179b05e6ee96..754934251430 100644 --- a/libc/hdr/CMakeLists.txt +++ b/libc/hdr/CMakeLists.txt @@ -68,4 +68,13 @@ add_proxy_header_library( libc.include.llvm-libc-macros.sys_epoll_macros ) +add_proxy_header_library( + time_macros + HDRS + time_macros.h + FULL_BUILD_DEPENDS + libc.include.time + libc.include.llvm-libc-macros.time_macros +) + add_subdirectory(types) diff --git a/libc/hdr/time_macros.h b/libc/hdr/time_macros.h new file mode 100644 index 000000000000..dc36fe66f7a8 --- /dev/null +++ b/libc/hdr/time_macros.h @@ -0,0 +1,22 @@ +//===-- Definition of macros from time.h ----------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_HDR_TIME_MACROS_H +#define LLVM_LIBC_HDR_TIME_MACROS_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-macros/time-macros.h" + +#else // Overlay mode + +#include + +#endif // LLVM_LIBC_FULL_BUILD + +#endif // LLVM_LIBC_HDR_TIME_MACROS_H diff --git a/libc/hdr/types/CMakeLists.txt b/libc/hdr/types/CMakeLists.txt index 46a66ec59020..3a1bb2f3c340 100644 --- a/libc/hdr/types/CMakeLists.txt +++ b/libc/hdr/types/CMakeLists.txt @@ -63,3 +63,48 @@ add_proxy_header_library( libc.include.llvm-libc-types.fexcept_t libc.include.fenv ) + +add_proxy_header_library( + time_t + HDRS + time_t.h + FULL_BUILD_DEPENDS + libc.include.llvm-libc-types.time_t + libc.include.time +) + +add_proxy_header_library( + clockid_t + HDRS + clockid_t.h + FULL_BUILD_DEPENDS + libc.include.llvm-libc-types.clockid_t + libc.include.sys_types +) + +add_proxy_header_library( + clock_t + HDRS + clock_t.h + FULL_BUILD_DEPENDS + libc.include.llvm-libc-types.clock_t + libc.include.time +) + +add_proxy_header_library( + suseconds_t + HDRS + suseconds_t.h + FULL_BUILD_DEPENDS + libc.include.llvm-libc-types.suseconds_t + libc.include.sys_time +) + +add_proxy_header_library( + struct_timeval + HDRS + struct_timeval.h + FULL_BUILD_DEPENDS + libc.include.llvm-libc-types.struct_timeval + libc.include.sys_time +) diff --git a/libc/hdr/types/clock_t.h b/libc/hdr/types/clock_t.h new file mode 100644 index 000000000000..b0b658e96c3d --- /dev/null +++ b/libc/hdr/types/clock_t.h @@ -0,0 +1,22 @@ +//===-- Proxy for clock_t -------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_HDR_TYPES_CLOCK_T_H +#define LLVM_LIBC_HDR_TYPES_CLOCK_T_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-types/clock_t.h" + +#else // Overlay mode + +#include + +#endif // LLVM_LIBC_FULL_BUILD + +#endif // LLVM_LIBC_HDR_TYPES_CLOCK_T_H diff --git a/libc/hdr/types/clockid_t.h b/libc/hdr/types/clockid_t.h new file mode 100644 index 000000000000..333342072a2f --- /dev/null +++ b/libc/hdr/types/clockid_t.h @@ -0,0 +1,22 @@ +//===-- Proxy for clockid_t -----------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_HDR_TYPES_CLOCKID_T_H +#define LLVM_LIBC_HDR_TYPES_CLOCKID_T_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-types/clockid_t.h" + +#else // Overlay mode + +#include + +#endif // LLVM_LIBC_FULL_BUILD + +#endif // LLVM_LIBC_HDR_TYPES_CLOCKID_T_H diff --git a/libc/hdr/types/struct_timeval.h b/libc/hdr/types/struct_timeval.h new file mode 100644 index 000000000000..8fc321a52d71 --- /dev/null +++ b/libc/hdr/types/struct_timeval.h @@ -0,0 +1,21 @@ +//===-- Proxy for struct timeval ----------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#ifndef LLVM_LIBC_HDR_TYPES_STRUCT_TIMEVAL_H +#define LLVM_LIBC_HDR_TYPES_STRUCT_TIMEVAL_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-types/struct_timeval.h" + +#else + +#include + +#endif // LIBC_FULL_BUILD + +#endif // LLVM_LIBC_HDR_TYPES_STRUCT_TIMEVAL_H diff --git a/libc/hdr/types/suseconds_t.h b/libc/hdr/types/suseconds_t.h new file mode 100644 index 000000000000..72e54a965f75 --- /dev/null +++ b/libc/hdr/types/suseconds_t.h @@ -0,0 +1,22 @@ +//===-- Proxy for suseconds_t ---------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_HDR_TIMES_SUSECONDS_T_H +#define LLVM_LIBC_HDR_TIMES_SUSECONDS_T_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-types/suseconds_t.h" + +#else // Overlay mode + +#include + +#endif // LLVM_LIBC_FULL_BUILD + +#endif // #ifndef LLVM_LIBC_HDR_TIMES_SUSECONDS_T_H diff --git a/libc/hdr/types/time_t.h b/libc/hdr/types/time_t.h new file mode 100644 index 000000000000..fc9a1506a2cd --- /dev/null +++ b/libc/hdr/types/time_t.h @@ -0,0 +1,22 @@ +//===-- Proxy for time_t --------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_HDR_TYPES_TIME_T_H +#define LLVM_LIBC_HDR_TYPES_TIME_T_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-types/time_t.h" + +#else // Overlay mode + +#include + +#endif // LLVM_LIBC_FULL_BUILD + +#endif // LLVM_LIBC_HDR_TYPES_TIME_T_H diff --git a/libc/src/__support/CMakeLists.txt b/libc/src/__support/CMakeLists.txt index dcae55e050bf..32d693ec6a26 100644 --- a/libc/src/__support/CMakeLists.txt +++ b/libc/src/__support/CMakeLists.txt @@ -281,3 +281,5 @@ add_subdirectory(File) add_subdirectory(HashTable) add_subdirectory(fixed_point) + +add_subdirectory(time) diff --git a/libc/src/__support/time/CMakeLists.txt b/libc/src/__support/time/CMakeLists.txt new file mode 100644 index 000000000000..36ce4f9dadb2 --- /dev/null +++ b/libc/src/__support/time/CMakeLists.txt @@ -0,0 +1,19 @@ +if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) + add_subdirectory(${LIBC_TARGET_OS}) +endif() + +add_object_library( + clock_gettime + ALIAS + DEPENDS + .${LIBC_TARGET_OS}.clock_gettime +) + +add_header_library( + units + HDRS + units.h + DEPENDS + libc.src.__support.common + libc.hdr.types.time_t +) diff --git a/libc/src/__support/time/clock_gettime.h b/libc/src/__support/time/clock_gettime.h new file mode 100644 index 000000000000..0655ccdc0028 --- /dev/null +++ b/libc/src/__support/time/clock_gettime.h @@ -0,0 +1,23 @@ +//===--- clock_gettime internal implementation ------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC___SUPPORT_TIME_CLOCK_GETTIME_H +#define LLVM_LIBC_SRC___SUPPORT_TIME_CLOCK_GETTIME_H +#include "hdr/types/clockid_t.h" +#include "hdr/types/struct_timespec.h" +#include "src/__support/common.h" + +#include "src/__support/error_or.h" + +namespace LIBC_NAMESPACE { +namespace internal { +ErrorOr clock_gettime(clockid_t clockid, timespec *ts); +} +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC___SUPPORT_TIME_CLOCK_GETTIME_H diff --git a/libc/src/__support/time/linux/CMakeLists.txt b/libc/src/__support/time/linux/CMakeLists.txt new file mode 100644 index 000000000000..034fa317ff6d --- /dev/null +++ b/libc/src/__support/time/linux/CMakeLists.txt @@ -0,0 +1,14 @@ +add_object_library( + clock_gettime + HDRS + ../clock_gettime.h + SRCS + clock_gettime.cpp + DEPENDS + libc.include.sys_syscall + libc.hdr.types.struct_timespec + libc.hdr.types.clockid_t + libc.src.__support.common + libc.src.__support.error_or + libc.src.__support.OSUtil.osutil +) diff --git a/libc/src/time/linux/clockGetTimeImpl.h b/libc/src/__support/time/linux/clock_gettime.cpp similarity index 64% rename from libc/src/time/linux/clockGetTimeImpl.h rename to libc/src/__support/time/linux/clock_gettime.cpp index 8c8c9fcf845c..6a131df9ba59 100644 --- a/libc/src/time/linux/clockGetTimeImpl.h +++ b/libc/src/__support/time/linux/clock_gettime.cpp @@ -1,4 +1,4 @@ -//===- Linux implementation of the POSIX clock_gettime function -*- C++ -*-===// +//===--- clock_gettime linux implementation ---------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,23 +6,14 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIBC_SRC_TIME_LINUX_CLOCKGETTIMEIMPL_H -#define LLVM_LIBC_SRC_TIME_LINUX_CLOCKGETTIMEIMPL_H - -#include "src/__support/OSUtil/syscall.h" // For internal syscall function. -#include "src/__support/common.h" -#include "src/__support/error_or.h" -#include "src/errno/libc_errno.h" - -#include // For int64_t. -#include // For syscall numbers. -#include - +#ifndef LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H +#define LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H +#include "src/__support/time/clock_gettime.h" +#include "src/__support/OSUtil/syscall.h" +#include namespace LIBC_NAMESPACE { namespace internal { - -LIBC_INLINE ErrorOr clock_gettimeimpl(clockid_t clockid, - struct timespec *ts) { +ErrorOr clock_gettime(clockid_t clockid, timespec *ts) { #if SYS_clock_gettime int ret = LIBC_NAMESPACE::syscall_impl(SYS_clock_gettime, static_cast(clockid), @@ -45,4 +36,4 @@ LIBC_INLINE ErrorOr clock_gettimeimpl(clockid_t clockid, } // namespace internal } // namespace LIBC_NAMESPACE -#endif // LLVM_LIBC_SRC_TIME_LINUX_CLOCKGETTIMEIMPL_H +#endif // LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H diff --git a/libc/src/__support/time/units.h b/libc/src/__support/time/units.h new file mode 100644 index 000000000000..f6bd19f9b139 --- /dev/null +++ b/libc/src/__support/time/units.h @@ -0,0 +1,38 @@ +//===--- Time units conversion ----------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC___SUPPORT_TIME_UNITS_H +#define LLVM_LIBC_SRC___SUPPORT_TIME_UNITS_H + +#include "hdr/types/time_t.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { +namespace time_units { +LIBC_INLINE constexpr time_t operator""_s_ns(unsigned long long s) { + return s * 1'000'000'000; +} +LIBC_INLINE constexpr time_t operator""_s_us(unsigned long long s) { + return s * 1'000'000; +} +LIBC_INLINE constexpr time_t operator""_s_ms(unsigned long long s) { + return s * 1'000; +} +LIBC_INLINE constexpr time_t operator""_ms_ns(unsigned long long ms) { + return ms * 1'000'000; +} +LIBC_INLINE constexpr time_t operator""_ms_us(unsigned long long ms) { + return ms * 1'000; +} +LIBC_INLINE constexpr time_t operator""_us_ns(unsigned long long us) { + return us * 1'000; +} +} // namespace time_units +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC___SUPPORT_TIME_UNITS_H diff --git a/libc/src/time/clock.h b/libc/src/time/clock.h index d4af7656644a..f5d14d036e13 100644 --- a/libc/src/time/clock.h +++ b/libc/src/time/clock.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_TIME_CLOCK_H #define LLVM_LIBC_SRC_TIME_CLOCK_H -#include +#include "hdr/types/clock_t.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/time/clock_gettime.h b/libc/src/time/clock_gettime.h index 72e2e1949feb..48e81a355429 100644 --- a/libc/src/time/clock_gettime.h +++ b/libc/src/time/clock_gettime.h @@ -9,11 +9,12 @@ #ifndef LLVM_LIBC_SRC_TIME_CLOCK_GETTIME_H #define LLVM_LIBC_SRC_TIME_CLOCK_GETTIME_H -#include +#include "hdr/types/clockid_t.h" +#include "hdr/types/struct_timespec.h" namespace LIBC_NAMESPACE { -int clock_gettime(clockid_t clockid, struct timespec *tp); +int clock_gettime(clockid_t clockid, timespec *tp); } // namespace LIBC_NAMESPACE diff --git a/libc/src/time/gettimeofday.h b/libc/src/time/gettimeofday.h index 880b94cee731..62ee31edcad6 100644 --- a/libc/src/time/gettimeofday.h +++ b/libc/src/time/gettimeofday.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_TIME_GETTIMEOFDAY_H #define LLVM_LIBC_SRC_TIME_GETTIMEOFDAY_H -#include +#include "hdr/types/struct_timeval.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/time/linux/CMakeLists.txt b/libc/src/time/linux/CMakeLists.txt index df79bf598626..8a0e6b04b66e 100644 --- a/libc/src/time/linux/CMakeLists.txt +++ b/libc/src/time/linux/CMakeLists.txt @@ -5,9 +5,9 @@ add_entrypoint_object( HDRS ../time_func.h DEPENDS - libc.include.time - libc.include.sys_syscall - libc.src.__support.OSUtil.osutil + libc.hdr.time_macros + libc.hdr.types.time_t + libc.src.__support.time.clock_gettime libc.src.errno.errno ) @@ -18,10 +18,11 @@ add_entrypoint_object( HDRS ../clock.h DEPENDS - libc.include.time - libc.include.sys_syscall + libc.hdr.time_macros + libc.hdr.types.clock_t + libc.src.__support.time.units + libc.src.__support.time.clock_gettime libc.src.__support.CPP.limits - libc.src.__support.OSUtil.osutil libc.src.errno.errno ) @@ -32,10 +33,10 @@ add_entrypoint_object( HDRS ../nanosleep.h DEPENDS - libc.include.time + libc.hdr.types.struct_timespec libc.include.sys_syscall - libc.src.__support.CPP.limits libc.src.__support.OSUtil.osutil + libc.src.__support.CPP.limits libc.src.errno.errno ) @@ -46,9 +47,9 @@ add_entrypoint_object( HDRS ../clock_gettime.h DEPENDS - libc.include.time - libc.include.sys_syscall - libc.src.__support.OSUtil.osutil + libc.hdr.types.clockid_t + libc.hdr.types.struct_timespec + libc.src.__support.time.clock_gettime libc.src.errno.errno ) @@ -59,8 +60,9 @@ add_entrypoint_object( HDRS ../gettimeofday.h DEPENDS - libc.include.time - libc.include.sys_syscall - libc.src.__support.OSUtil.osutil + libc.hdr.time_macros + libc.hdr.types.suseconds_t + libc.src.__support.time.clock_gettime + libc.src.__support.time.units libc.src.errno.errno ) diff --git a/libc/src/time/linux/clock.cpp b/libc/src/time/linux/clock.cpp index 1e95f0526bc9..fc48e2792747 100644 --- a/libc/src/time/linux/clock.cpp +++ b/libc/src/time/linux/clock.cpp @@ -7,21 +7,19 @@ //===----------------------------------------------------------------------===// #include "src/time/clock.h" - +#include "hdr/time_macros.h" #include "src/__support/CPP/limits.h" -#include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" +#include "src/__support/time/clock_gettime.h" +#include "src/__support/time/units.h" #include "src/errno/libc_errno.h" -#include "src/time/linux/clockGetTimeImpl.h" - -#include // For syscall numbers. -#include namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(clock_t, clock, ()) { + using namespace time_units; struct timespec ts; - auto result = internal::clock_gettimeimpl(CLOCK_PROCESS_CPUTIME_ID, &ts); + auto result = internal::clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &ts); if (!result.has_value()) { libc_errno = result.error(); return -1; @@ -34,15 +32,15 @@ LLVM_LIBC_FUNCTION(clock_t, clock, ()) { cpp::numeric_limits::max() / CLOCKS_PER_SEC; if (ts.tv_sec > CLOCK_SECS_MAX) return clock_t(-1); - if (ts.tv_nsec / 1000000000 > CLOCK_SECS_MAX - ts.tv_sec) + if (ts.tv_nsec / 1_s_ns > CLOCK_SECS_MAX - ts.tv_sec) return clock_t(-1); // For the integer computation converting tv_nsec to clocks to work // correctly, we want CLOCKS_PER_SEC to be less than 1000000000. - static_assert(1000000000 > CLOCKS_PER_SEC, - "Expected CLOCKS_PER_SEC to be less than 1000000000."); + static_assert(1_s_ns > CLOCKS_PER_SEC, + "Expected CLOCKS_PER_SEC to be less than 1'000'000'000."); return clock_t(ts.tv_sec * CLOCKS_PER_SEC + - ts.tv_nsec / (1000000000 / CLOCKS_PER_SEC)); + ts.tv_nsec / (1_s_ns / CLOCKS_PER_SEC)); } } // namespace LIBC_NAMESPACE diff --git a/libc/src/time/linux/clock_gettime.cpp b/libc/src/time/linux/clock_gettime.cpp index 47e974a866c8..920363e85e06 100644 --- a/libc/src/time/linux/clock_gettime.cpp +++ b/libc/src/time/linux/clock_gettime.cpp @@ -7,21 +7,16 @@ //===----------------------------------------------------------------------===// #include "src/time/clock_gettime.h" - -#include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" +#include "src/__support/time/clock_gettime.h" #include "src/errno/libc_errno.h" -#include "src/time/linux/clockGetTimeImpl.h" - -#include // For syscall numbers. -#include namespace LIBC_NAMESPACE { // TODO(michaelrj): Move this into time/linux with the other syscalls. LLVM_LIBC_FUNCTION(int, clock_gettime, (clockid_t clockid, struct timespec *ts)) { - auto result = internal::clock_gettimeimpl(clockid, ts); + auto result = internal::clock_gettime(clockid, ts); // A negative return value indicates an error with the magnitude of the // value being the error code. diff --git a/libc/src/time/linux/gettimeofday.cpp b/libc/src/time/linux/gettimeofday.cpp index 07ab4d579176..c7bcd45e01fa 100644 --- a/libc/src/time/linux/gettimeofday.cpp +++ b/libc/src/time/linux/gettimeofday.cpp @@ -7,24 +7,24 @@ //===----------------------------------------------------------------------===// #include "src/time/gettimeofday.h" - -#include "src/__support/OSUtil/syscall.h" // For internal syscall function. +#include "hdr/time_macros.h" +#include "hdr/types/suseconds_t.h" #include "src/__support/common.h" +#include "src/__support/time/clock_gettime.h" +#include "src/__support/time/units.h" #include "src/errno/libc_errno.h" -#include "src/time/linux/clockGetTimeImpl.h" - -#include // For syscall numbers. namespace LIBC_NAMESPACE { // TODO(michaelrj): Move this into time/linux with the other syscalls. LLVM_LIBC_FUNCTION(int, gettimeofday, (struct timeval * tv, [[maybe_unused]] void *unused)) { + using namespace time_units; if (tv == nullptr) return 0; struct timespec ts; - auto result = internal::clock_gettimeimpl(CLOCK_REALTIME, &ts); + auto result = internal::clock_gettime(CLOCK_REALTIME, &ts); // A negative return value indicates an error with the magnitude of the // value being the error code. @@ -34,7 +34,7 @@ LLVM_LIBC_FUNCTION(int, gettimeofday, } tv->tv_sec = ts.tv_sec; - tv->tv_usec = static_cast(ts.tv_nsec / 1000); + tv->tv_usec = static_cast(ts.tv_nsec / 1_us_ns); return 0; } diff --git a/libc/src/time/linux/time.cpp b/libc/src/time/linux/time.cpp index e286fae095b2..93d5d7362764 100644 --- a/libc/src/time/linux/time.cpp +++ b/libc/src/time/linux/time.cpp @@ -6,22 +6,18 @@ // //===----------------------------------------------------------------------===// -#include "src/time/time_func.h" - -#include "src/__support/OSUtil/syscall.h" // For internal syscall function. +#include "hdr/time_macros.h" #include "src/__support/common.h" +#include "src/__support/time/clock_gettime.h" #include "src/errno/libc_errno.h" -#include "src/time/linux/clockGetTimeImpl.h" - -#include // For syscall numbers. -#include +#include "src/time/time_func.h" namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(time_t, time, (time_t * tp)) { // TODO: Use the Linux VDSO to fetch the time and avoid the syscall. struct timespec ts; - auto result = internal::clock_gettimeimpl(CLOCK_REALTIME, &ts); + auto result = internal::clock_gettime(CLOCK_REALTIME, &ts); if (!result.has_value()) { libc_errno = result.error(); return -1; diff --git a/libc/src/time/nanosleep.h b/libc/src/time/nanosleep.h index 757394232c07..2309666b2304 100644 --- a/libc/src/time/nanosleep.h +++ b/libc/src/time/nanosleep.h @@ -9,11 +9,11 @@ #ifndef LLVM_LIBC_SRC_TIME_NANOSLEEP_H #define LLVM_LIBC_SRC_TIME_NANOSLEEP_H -#include +#include "hdr/types/struct_timespec.h" namespace LIBC_NAMESPACE { -int nanosleep(const struct timespec *req, struct timespec *rem); +int nanosleep(const timespec *req, timespec *rem); } // namespace LIBC_NAMESPACE diff --git a/libc/src/time/time_func.h b/libc/src/time/time_func.h index beb02020b575..2a5239220942 100644 --- a/libc/src/time/time_func.h +++ b/libc/src/time/time_func.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_TIME_TIME_FUNC_H #define LLVM_LIBC_SRC_TIME_TIME_FUNC_H -#include +#include "hdr/types/time_t.h" // Note this header file is named time_func.h to avoid conflicts with the // public header file time.h. -- GitLab From ddad7c3c84a8706ad539f1a69660a31a00b411a2 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Thu, 9 May 2024 21:51:39 +0100 Subject: [PATCH 197/328] [AArch64] add some more tests for FMV (#91490) Add a couple of tests to make it clear: - when FMV should be enabled and disabled by the driver. - which extensions are enabled/disabled based on the dependencies specified in TargetParser. --- clang/test/CodeGen/aarch64-fmv-dependencies.c | 240 ++++++++++++++++++ clang/test/Driver/aarch64-fmv.c | 27 ++ 2 files changed, 267 insertions(+) create mode 100644 clang/test/CodeGen/aarch64-fmv-dependencies.c create mode 100644 clang/test/Driver/aarch64-fmv.c diff --git a/clang/test/CodeGen/aarch64-fmv-dependencies.c b/clang/test/CodeGen/aarch64-fmv-dependencies.c new file mode 100644 index 000000000000..ec599e1b3fa7 --- /dev/null +++ b/clang/test/CodeGen/aarch64-fmv-dependencies.c @@ -0,0 +1,240 @@ +// Test/document all of the dependencies between possible AArch64 FMV extensions. +// Also test the name mangling. + +// RUN: %clang --target=aarch64-linux-gnu --rtlib=compiler-rt -emit-llvm -S -o - %s | FileCheck %s + +// CHECK: define dso_local i32 @fmv._Maes() #[[ATTR0:[0-9]+]] { +__attribute__((target_version("aes"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mbf16() #[[bf16_ebf16:[0-9]+]] { +__attribute__((target_version("bf16"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mbti() #[[bti:[0-9]+]] { +__attribute__((target_version("bti"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mcrc() #[[crc:[0-9]+]] { +__attribute__((target_version("crc"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mdgh() #[[ATTR0:[0-9]+]] { +__attribute__((target_version("dgh"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mdit() #[[dit:[0-9]+]] { +__attribute__((target_version("dit"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mdotprod() #[[dotprod:[0-9]+]] { +__attribute__((target_version("dotprod"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mdpb() #[[dpb:[0-9]+]] { +__attribute__((target_version("dpb"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mdpb2() #[[dpb2:[0-9]+]] { +__attribute__((target_version("dpb2"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mebf16() #[[bf16_ebf16:[0-9]+]] { +__attribute__((target_version("ebf16"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mf32mm() #[[f32mm:[0-9]+]] { +__attribute__((target_version("f32mm"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mf64mm() #[[f64mm:[0-9]+]] { +__attribute__((target_version("f64mm"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mfcma() #[[fcma:[0-9]+]] { +__attribute__((target_version("fcma"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mflagm() #[[flagm:[0-9]+]] { +__attribute__((target_version("flagm"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mflagm2() #[[flagm2:[0-9]+]] { +__attribute__((target_version("flagm2"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mfp() #[[ATTR0:[0-9]+]] { +__attribute__((target_version("fp"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mfp16() #[[fp16:[0-9]+]] { +__attribute__((target_version("fp16"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mfp16fml() #[[fp16fml:[0-9]+]] { +__attribute__((target_version("fp16fml"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mfrintts() #[[frintts:[0-9]+]] { +__attribute__((target_version("frintts"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mi8mm() #[[i8mm:[0-9]+]] { +__attribute__((target_version("i8mm"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mjscvt() #[[jscvt:[0-9]+]] { +__attribute__((target_version("jscvt"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mls64() #[[ATTR0:[0-9]+]] { +__attribute__((target_version("ls64"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mls64_accdata() #[[ls64_accdata:[0-9]+]] { +__attribute__((target_version("ls64_accdata"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mls64_v() #[[ATTR0:[0-9]+]] { +__attribute__((target_version("ls64_v"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mlse() #[[lse:[0-9]+]] { +__attribute__((target_version("lse"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mmemtag() #[[ATTR0:[0-9]+]] { +__attribute__((target_version("memtag"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mmemtag2() #[[memtag2:[0-9]+]] { +__attribute__((target_version("memtag2"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mmemtag3() #[[memtag2:[0-9]+]] { +__attribute__((target_version("memtag3"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mmops() #[[mops:[0-9]+]] { +__attribute__((target_version("mops"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mpmull() #[[pmull:[0-9]+]] { +__attribute__((target_version("pmull"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mpredres() #[[predres:[0-9]+]] { +__attribute__((target_version("predres"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mrcpc() #[[rcpc:[0-9]+]] { +__attribute__((target_version("rcpc"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mrcpc2() #[[rcpc:[0-9]+]] { +__attribute__((target_version("rcpc2"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mrcpc3() #[[rcpc3:[0-9]+]] { +__attribute__((target_version("rcpc3"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mrdm() #[[rdm:[0-9]+]] { +__attribute__((target_version("rdm"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mrng() #[[rng:[0-9]+]] { +__attribute__((target_version("rng"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mrpres() #[[ATTR0:[0-9]+]] { +__attribute__((target_version("rpres"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msb() #[[sb:[0-9]+]] { +__attribute__((target_version("sb"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msha1() #[[ATTR0:[0-9]+]] { +__attribute__((target_version("sha1"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msha2() #[[sha2:[0-9]+]] { +__attribute__((target_version("sha2"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msha3() #[[sha3:[0-9]+]] { +__attribute__((target_version("sha3"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msimd() #[[ATTR0:[0-9]+]] { +__attribute__((target_version("simd"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msm4() #[[sm4:[0-9]+]] { +__attribute__((target_version("sm4"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msme() #[[sme:[0-9]+]] { +__attribute__((target_version("sme"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msme-f64f64() #[[sme_f64f64:[0-9]+]] { +__attribute__((target_version("sme-f64f64"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msme-i16i64() #[[sme_i16i64:[0-9]+]] { +__attribute__((target_version("sme-i16i64"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msme2() #[[sme2:[0-9]+]] { +__attribute__((target_version("sme2"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mssbs() #[[ATTR0:[0-9]+]] { +__attribute__((target_version("ssbs"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mssbs2() #[[ssbs2:[0-9]+]] { +__attribute__((target_version("ssbs2"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msve() #[[sve:[0-9]+]] { +__attribute__((target_version("sve"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msve-bf16() #[[sve_bf16_ebf16:[0-9]+]] { +__attribute__((target_version("sve-bf16"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msve-ebf16() #[[sve_bf16_ebf16:[0-9]+]] { +__attribute__((target_version("sve-ebf16"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msve-i8mm() #[[sve_i8mm:[0-9]+]] { +__attribute__((target_version("sve-i8mm"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msve2() #[[sve2:[0-9]+]] { +__attribute__((target_version("sve2"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msve2-aes() #[[sve2_aes_sve2_pmull128:[0-9]+]] { +__attribute__((target_version("sve2-aes"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msve2-bitperm() #[[sve2_bitperm:[0-9]+]] { +__attribute__((target_version("sve2-bitperm"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msve2-pmull128() #[[sve2_aes_sve2_pmull128:[0-9]+]] { +__attribute__((target_version("sve2-pmull128"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msve2-sha3() #[[sve2_sha3:[0-9]+]] { +__attribute__((target_version("sve2-sha3"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Msve2-sm4() #[[sve2_sm4:[0-9]+]] { +__attribute__((target_version("sve2-sm4"))) int fmv(void) { return 0; } + +// CHECK: define dso_local i32 @fmv._Mwfxt() #[[wfxt:[0-9]+]] { +__attribute__((target_version("wfxt"))) int fmv(void) { return 0; } + +// CHECK-NOT: define dso_local i32 @fmv._M{{.*}} +__attribute__((target_version("non_existent_extension"))) int fmv(void); + +__attribute__((target_version("default"))) int fmv(void); + +int caller() { + return fmv(); +} + +// CHECK: attributes #[[ATTR0:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[bf16_ebf16:[0-9]+]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[bti:[0-9]+]] = { {{.*}} "target-features"="+bti,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[crc:[0-9]+]] = { {{.*}} "target-features"="+crc,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[dit:[0-9]+]] = { {{.*}} "target-features"="+dit,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[dotprod:[0-9]+]] = { {{.*}} "target-features"="+dotprod,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[dpb:[0-9]+]] = { {{.*}} "target-features"="+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[dpb2:[0-9]+]] = { {{.*}} "target-features"="+ccdp,+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[f32mm:[0-9]+]] = { {{.*}} "target-features"="+f32mm,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a" +// CHECK: attributes #[[f64mm:[0-9]+]] = { {{.*}} "target-features"="+f64mm,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a" +// CHECK: attributes #[[fcma:[0-9]+]] = { {{.*}} "target-features"="+complxnum,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[flagm:[0-9]+]] = { {{.*}} "target-features"="+flagm,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[flagm2:[0-9]+]] = { {{.*}} "target-features"="+altnzcv,+flagm,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[fp16:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[fp16fml:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fp16fml,+fullfp16,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[frintts:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fptoint,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[i8mm:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+i8mm,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[jscvt:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+jsconv,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[ls64_accdata:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+ls64,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[lse:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+lse,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[memtag2:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[mops:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+mops,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[pmull:[0-9]+]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[predres:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+predres,+v8a" +// CHECK: attributes #[[rcpc:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+v8a" +// CHECK: attributes #[[rcpc3:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+rcpc3,+v8a" +// CHECK: attributes #[[rdm:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rdm,+v8a" +// CHECK: attributes #[[rng:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rand,+v8a" +// CHECK: attributes #[[sb:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sb,+v8a" +// CHECK: attributes #[[sha2:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sha2,+v8a" +// CHECK: attributes #[[sha3:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sha2,+sha3,+v8a" +// CHECK: attributes #[[sm4:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sm4,+v8a" +// CHECK: attributes #[[sme:[0-9]+]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+v8a" +// CHECK: attributes #[[sme_f64f64:[0-9]+]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme-f64f64,+v8a" +// CHECK: attributes #[[sme_i16i64:[0-9]+]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme-i16i64,+v8a" +// CHECK: attributes #[[sme2:[0-9]+]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme2,+v8a" +// CHECK: attributes #[[ssbs2:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+ssbs,+v8a" +// CHECK: attributes #[[sve:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a" +// CHECK: attributes #[[sve_bf16_ebf16:[0-9]+]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a" +// CHECK: attributes #[[sve_i8mm:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+i8mm,+neon,+outline-atomics,+sve,+v8a" +// CHECK: attributes #[[sve2:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a" +// CHECK: attributes #[[sve2_aes_sve2_pmull128:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a" +// CHECK: attributes #[[sve2_bitperm:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-bitperm,+v8a" +// CHECK: attributes #[[sve2_sha3:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-sha3,+v8a" +// CHECK: attributes #[[sve2_sm4:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-sm4,+v8a" +// CHECK: attributes #[[wfxt:[0-9]+]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,+wfxt" diff --git a/clang/test/Driver/aarch64-fmv.c b/clang/test/Driver/aarch64-fmv.c new file mode 100644 index 000000000000..873a88964e9b --- /dev/null +++ b/clang/test/Driver/aarch64-fmv.c @@ -0,0 +1,27 @@ +// Test which driver flags enable/disable Function Multiversioning on aarch64. + +// FMV is enabled for non-android aarch64 targets: +// RUN: %clang --target=aarch64 --rtlib=compiler-rt -### -c %s 2>&1 | FileCheck -check-prefix=FMV-ENABLED %s +// RUN: %clang --target=aarch64-linux-gnu --rtlib=compiler-rt -### -c %s 2>&1 | FileCheck -check-prefix=FMV-ENABLED %s +// RUN: %clang --target=arm64-apple-ios --rtlib=compiler-rt -### -c %s 2>&1 | FileCheck -check-prefix=FMV-ENABLED %s +// RUN: %clang --target=arm64-apple-macosx --rtlib=compiler-rt -### -c %s 2>&1 | FileCheck -check-prefix=FMV-ENABLED %s + +// android23 defaults to --rtlib=compiler-rt: +// RUN: %clang --target=aarch64-linux-android23 -### -c %s 2>&1 | FileCheck -check-prefix=FMV-ENABLED %s +// RUN: %clang --target=aarch64-linux-android23 --rtlib=compiler-rt -### -c %s 2>&1 | FileCheck -check-prefix=FMV-ENABLED %s + +// FMV is disabled without compiler-rt: +// RUN: %clang --target=aarch64 -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s +// RUN: %clang --target=aarch64-linux-gnu -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s + +// Disabled for older android versions: +// RUN: %clang --rtlib=compiler-rt --target=aarch64-linux-android -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s +// RUN: %clang --rtlib=compiler-rt --target=aarch64-linux-android22 -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s +// RUN: %clang --rtlib=compiler-rt --target=aarch64-linux-android22 -mno-fmv -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s + +// Disabled explicitly: +// RUN: %clang --rtlib=compiler-rt --target=aarch64 -mno-fmv -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s +// RUN: %clang --rtlib=compiler-rt --target=aarch64-linux-android23 -mno-fmv -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s + +// FMV-ENABLED-NOT: "-target-feature" "-fmv" +// FMV-DISABLED: "-target-feature" "-fmv" -- GitLab From f4a7e1f9bac1f11e1db1c0a895f3f681838f89f2 Mon Sep 17 00:00:00 2001 From: Med Ismail Bennani Date: Thu, 9 May 2024 13:51:52 -0700 Subject: [PATCH 198/328] [lldb/crashlog] Fix module binary resolution (#91631) This patch fixes a bug in when resolving and loading modules from the binary image list. When loading a module, we would first use the UUID from the binary image list with `dsymForUUID` to fetch the dSYM bundle from our remote build records and copy the executable locally. If we failed to find a matching dSYM bundle for that UUID on the build record, let's say if that module was built locally, we use Spotlight (`mdfind`) to find the dSYM bundle once again using the UUID. Prior to this patch, we would set the image path to be the same as the symbol file. This resulted in trying to load the dSYM as a module in lldb, which isn't allowed. This patch address that by looking for a binary matching the image identifier, next to the dSYM bundle and try to load that instead. rdar://127433616 Signed-off-by: Med Ismail Bennani --- lldb/examples/python/crashlog.py | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/lldb/examples/python/crashlog.py b/lldb/examples/python/crashlog.py index eb9af6ed3d95..2919b9c76e68 100755 --- a/lldb/examples/python/crashlog.py +++ b/lldb/examples/python/crashlog.py @@ -418,9 +418,20 @@ class CrashLog(symbolication.Symbolicator): with print_lock: print('falling back to binary inside "%s"' % dsym) self.symfile = dsym - for filename in os.listdir(dwarf_dir): - self.path = os.path.join(dwarf_dir, filename) - if self.find_matching_slice(): + # Look for the executable next to the dSYM bundle. + parent_dir = os.path.dirname(dsym) + executables = [] + for root, _, files in os.walk(parent_dir): + for file in files: + abs_path = os.path.join(root, file) + if os.path.isfile(abs_path) and os.access( + abs_path, os.X_OK + ): + executables.append(abs_path) + for binary in executables: + basename = os.path.basename(binary) + if basename == self.identifier: + self.path = binary found_matching_slice = True break if found_matching_slice: -- GitLab From 639a740035b732e9bc0f43f3f95d1ce3acf82e1b Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Thu, 9 May 2024 21:54:48 +0100 Subject: [PATCH 199/328] [AArch64] move extension information into tablgen (#90987) Generate TargetParser extension information from tablegen. This includes FMV extension information. FMV only extensions are represented by a separate tablegen class. Use MArchName/ArchKindEnumSpelling to avoid renamings. Cases where there is simply a case difference are handled by consistently uppercasing the AEK_ name in the emitted code. Remove some Extensions which were not needed. These had AEK entries but were never actually used for anything. They are not present in Extensions[] data. --- .../Driver/aarch64-implied-sme-features.c | 12 +- .../Driver/aarch64-implied-sve-features.c | 22 +- .../command-disassemble-aarch64-extensions.s | 2 +- .../llvm/TargetParser/AArch64TargetParser.h | 139 +---------- llvm/lib/Target/AArch64/AArch64Features.td | 228 ++++++++++++++---- .../TargetParser/TargetParserTest.cpp | 8 +- llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 59 ++++- 7 files changed, 264 insertions(+), 206 deletions(-) diff --git a/clang/test/Driver/aarch64-implied-sme-features.c b/clang/test/Driver/aarch64-implied-sme-features.c index 67836f42f2c0..eca62e2563b7 100644 --- a/clang/test/Driver/aarch64-implied-sme-features.c +++ b/clang/test/Driver/aarch64-implied-sme-features.c @@ -14,7 +14,7 @@ // SME-CONFLICT: "-target-feature" "-bf16"{{.*}} "-target-feature" "-sme" // RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=SME-I16I64 -// SME-I16I64: "-target-feature" "+bf16"{{.*}} "-target-feature" "+sme-i16i64" "-target-feature" "+sme" +// SME-I16I64: "-target-feature" "+bf16"{{.*}} "-target-feature" "+sme" "-target-feature" "+sme-i16i64" // RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=NOSME-I16I64 // NOSME-I16I64-NOT: "-target-feature" "+sme-i16i64" @@ -23,7 +23,7 @@ // NOSME-I16I64-NOT: sme-i16i64" // RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64+nosme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=SME-I16I64-REVERT -// SME-I16I64-REVERT: "-target-feature" "+bf16"{{.*}} "-target-feature" "-sme-i16i64" "-target-feature" "+sme" +// SME-I16I64-REVERT: "-target-feature" "+bf16"{{.*}} "-target-feature" "+sme" "-target-feature" "-sme-i16i64" // RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme-f64f64 %s -### 2>&1 | FileCheck %s --check-prefix=NOSME-F64F64 // NOSME-F64F64-NOT: "-target-feature" "+sme-f64f64" @@ -32,15 +32,15 @@ // NOSME-F64F64-NOT: sme-f64f64" // RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-f64f64+nosme-f64f64 %s -### 2>&1 | FileCheck %s --check-prefix=SME-F64F64-REVERT -// SME-F64F64-REVERT: "-target-feature" "+bf16"{{.*}} "-target-feature" "-sme-f64f64" "-target-feature" "+sme" +// SME-F64F64-REVERT: "-target-feature" "+bf16"{{.*}} "-target-feature" "+sme" "-target-feature" "-sme-f64f64" // RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-f64f64+nosme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-MIX // SME-SUBFEATURE-MIX-NOT: "+sme-i16i64" -// SME-SUBFEATURE-MIX: "-target-feature" "+bf16"{{.*}} "-target-feature" "+sme-f64f64" "-target-feature" "+sme" +// SME-SUBFEATURE-MIX: "-target-feature" "+bf16"{{.*}} "-target-feature" "+sme" "-target-feature" "+sme-f64f64" // SME-SUBFEATURE-MIX-NOT: "+sme-i16i64" // RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64+nosme %s -### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT1 -// SME-SUBFEATURE-CONFLICT1: "-target-feature" "+bf16"{{.*}} "-target-feature" "-sme-i16i64" "-target-feature" "-sme" +// SME-SUBFEATURE-CONFLICT1: "-target-feature" "+bf16"{{.*}} "-target-feature" "-sme" "-target-feature" "-sme-i16i64" // RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-f64f64+nobf16 %s -### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT2 // SME-SUBFEATURE-CONFLICT2-NOT: "-target-feature" "+bf16" @@ -48,4 +48,4 @@ // SME-SUBFEATURE-CONFLICT2-NOT: "-target-feature" "+sme-f64f64" // RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme+sme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT-REV -// SME-SUBFEATURE-CONFLICT-REV: "-target-feature" "+bf16"{{.*}} "-target-feature" "+sme-i16i64" "-target-feature" "+sme" +// SME-SUBFEATURE-CONFLICT-REV: "-target-feature" "+bf16"{{.*}} "-target-feature" "+sme" "-target-feature" "+sme-i16i64" diff --git a/clang/test/Driver/aarch64-implied-sve-features.c b/clang/test/Driver/aarch64-implied-sve-features.c index 9227cd4981c2..f04e1a785673 100644 --- a/clang/test/Driver/aarch64-implied-sve-features.c +++ b/clang/test/Driver/aarch64-implied-sve-features.c @@ -24,7 +24,7 @@ // SVE-SVE2: "-target-feature" "+sve" "-target-feature" "+sve2" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-bitperm %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-BITPERM -// SVE2-BITPERM: "-target-feature" "+sve" "-target-feature" "+sve2-bitperm" "-target-feature" "+sve2" +// SVE2-BITPERM: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-bitperm" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+nosve2-bitperm %s -### 2>&1 | FileCheck %s --check-prefix=NOSVE2-BITPERM // NOSVE2-BITPERM-NOT: "-target-feature" "+sve2-bitperm" @@ -33,32 +33,32 @@ // NOSVE2-BITPERM-NOT: sve2-bitperm" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-bitperm+nosve2-bitperm %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-BITPERM-REVERT -// SVE2-BITPERM-REVERT: "-target-feature" "+sve" "-target-feature" "-sve2-bitperm" "-target-feature" "+sve2" +// SVE2-BITPERM-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-bitperm" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-aes+nosve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-AES-REVERT -// SVE2-AES-REVERT: "-target-feature" "+sve" "-target-feature" "-sve2-aes" "-target-feature" "+sve2" +// SVE2-AES-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-aes" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3+nosve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3-REVERT -// SVE2-SHA3-REVERT: "-target-feature" "+sve" "-target-feature" "-sve2-sha3" "-target-feature" "+sve2" +// SVE2-SHA3-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-sha3" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4+nosve2-sm4 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SM4-REVERT -// SVE2-SM4-REVERT: "-target-feature" "+sve" "-target-feature" "-sve2-sm4" "-target-feature" "+sve2" +// SVE2-SM4-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-sm4" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3 -// SVE2-SHA3: "-target-feature" "+sve" "-target-feature" "+sve2-sha3" "-target-feature" "+sve2" +// SVE2-SHA3: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-sha3" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-AES -// SVE2-AES: "-target-feature" "+sve" "-target-feature" "+sve2-aes" "-target-feature" "+sve2" +// SVE2-AES: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-aes" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SM4 -// SVE2-SM4: "-target-feature" "+sve" "-target-feature" "+sve2-sm4" "-target-feature" "+sve2" +// SVE2-SM4: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-sm4" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-bitperm+nosve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SUBFEATURE-MIX -// SVE2-SUBFEATURE-MIX: "-target-feature" "+sve" "-target-feature" "+sve2-bitperm" "-target-feature" "+sve2" +// SVE2-SUBFEATURE-MIX: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-bitperm" // SVE2-SUBFEATURE-NOT: sve2-aes // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4+nosve2 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SUBFEATURE-CONFLICT -// SVE2-SUBFEATURE-CONFLICT: "-target-feature" "+sve" "-target-feature" "-sve2-sm4" "-target-feature" "-sve2" +// SVE2-SUBFEATURE-CONFLICT: "-target-feature" "+sve" "-target-feature" "-sve2" "-target-feature" "-sve2-sm4" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-aes+nosve %s -### 2>&1 | FileCheck %s --check-prefix=SVE-SUBFEATURE-CONFLICT // SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sve2-aes" @@ -66,7 +66,7 @@ // SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sve" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+nosve+sve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE-SUBFEATURE-CONFLICT-REV -// SVE-SUBFEATURE-CONFLICT-REV: "-target-feature" "+sve" "-target-feature" "+sve2-aes" "-target-feature" "+sve2" +// SVE-SUBFEATURE-CONFLICT-REV: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-aes" // RUN: %clang --target=aarch64-linux-gnu -mcpu=neoverse-n2+nosve2 %s -### 2>&1 | FileCheck %s --check-prefix=SVE-MCPU-FEATURES // SVE-MCPU-FEATURES-NOT: "-target-feature" "+sve2-bitperm" diff --git a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s index e154f544e7cc..685d0a84ec28 100644 --- a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s +++ b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s @@ -59,7 +59,7 @@ fn: bdep z0.b, z1.b, z31.b // AEK_SVE2BITPERM rax1 z0.d, z0.d, z0.d // AEK_SVE2SHA3 sm4e z0.s, z0.s, z0.s // AEK_SVE2SM4 - addqv v0.8h, p0, z0.h // AEK_SVE2p1 / AEK_SME2p1 + addqv v0.8h, p0, z0.h // AEK_SVE2P1 / AEK_SME2P1 rcwswp x0, x1, [x2] // AEK_THE tcommit // AEK_TME lbl: diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 04fbaf07adfb..1124420daf8d 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -104,29 +104,9 @@ static_assert(FEAT_MAX < 62, "Number of features in CPUFeatures are limited to 62 entries"); // Each ArchExtKind correponds directly to a possible -target-feature. -enum ArchExtKind : unsigned { - AEK_NONE = 1, -#define ARM_EXTENSION(NAME, ENUM) ENUM, +#define EMIT_ARCHEXTKIND_ENUM #include "llvm/TargetParser/AArch64TargetParserDef.inc" - AEK_NUM_EXTENSIONS, - - // FIXME temporary fixes for inconsistent naming. - AEK_F32MM = AEK_MATMULFP32, - AEK_F64MM = AEK_MATMULFP64, - AEK_FCMA = AEK_COMPLXNUM, - AEK_FP = AEK_FPARMV8, - AEK_FP16 = AEK_FULLFP16, - AEK_I8MM = AEK_MATMULINT8, - AEK_JSCVT = AEK_JS, - AEK_PROFILE = AEK_SPE, - AEK_RASv2 = AEK_RASV2, - AEK_RAND = AEK_RANDGEN, - AEK_SIMD = AEK_NEON, - AEK_SME2p1 = AEK_SME2P1, - AEK_SVE2p1 = AEK_SVE2P1, - AEK_SME_LUTv2 = AEK_SME_LUTV2, -}; using ExtensionBitset = Bitset; // Represents an extension that can be enabled with -march=+. @@ -148,111 +128,8 @@ struct ExtensionInfo { 1000; // Maximum priority for FMV feature }; -// NOTE: If adding a new extension here, consider adding it to ExtensionMap -// in AArch64AsmParser too, if supported as an extension name by binutils. -// clang-format off -inline constexpr ExtensionInfo Extensions[] = { - {"aes", AArch64::AEK_AES, "+aes", "-aes", FEAT_AES, "+fp-armv8,+neon", 150}, - {"b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16", FEAT_INIT, "", 0}, - {"bf16", AArch64::AEK_BF16, "+bf16", "-bf16", FEAT_BF16, "+bf16", 280}, - {"brbe", AArch64::AEK_BRBE, "+brbe", "-brbe", FEAT_INIT, "", 0}, - {"bti", AArch64::AEK_NONE, {}, {}, FEAT_BTI, "+bti", 510}, - {"crc", AArch64::AEK_CRC, "+crc", "-crc", FEAT_CRC, "+crc", 110}, - {"crypto", AArch64::AEK_CRYPTO, "+crypto", "-crypto", FEAT_INIT, "+aes,+sha2", 0}, - {"cssc", AArch64::AEK_CSSC, "+cssc", "-cssc", FEAT_INIT, "", 0}, - {"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0}, - {"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260}, - {"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180}, - {"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD, "+dotprod,+fp-armv8,+neon", 104}, - {"dpb", AArch64::AEK_NONE, {}, {}, FEAT_DPB, "+ccpp", 190}, - {"dpb2", AArch64::AEK_NONE, {}, {}, FEAT_DPB2, "+ccpp,+ccdp", 200}, - {"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290}, - {"f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32mm", FEAT_SVE_F32MM, "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350}, - {"f64mm", AArch64::AEK_F64MM, "+f64mm", "-f64mm", FEAT_SVE_F64MM, "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360}, - {"fcma", AArch64::AEK_FCMA, "+complxnum", "-complxnum", FEAT_FCMA, "+fp-armv8,+neon,+complxnum", 220}, - {"flagm", AArch64::AEK_FLAGM, "+flagm", "-flagm", FEAT_FLAGM, "+flagm", 20}, - {"flagm2", AArch64::AEK_NONE, {}, {}, FEAT_FLAGM2, "+flagm,+altnzcv", 30}, - {"fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8", FEAT_FP, "+fp-armv8,+neon", 90}, - {"fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16", FEAT_FP16, "+fullfp16,+fp-armv8,+neon", 170}, - {"fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml", FEAT_FP16FML, "+fp16fml,+fullfp16,+fp-armv8,+neon", 175}, - {"frintts", AArch64::AEK_NONE, {}, {}, FEAT_FRINTTS, "+fptoint", 250}, - {"hbc", AArch64::AEK_HBC, "+hbc", "-hbc", FEAT_INIT, "", 0}, - {"i8mm", AArch64::AEK_I8MM, "+i8mm", "-i8mm", FEAT_I8MM, "+i8mm", 270}, - {"ite", AArch64::AEK_ITE, "+ite", "-ite", FEAT_INIT, "", 0}, - {"jscvt", AArch64::AEK_JSCVT, "+jsconv", "-jsconv", FEAT_JSCVT, "+fp-armv8,+neon,+jsconv", 210}, - {"ls64_accdata", AArch64::AEK_NONE, {}, {}, FEAT_LS64_ACCDATA, "+ls64", 540}, - {"ls64_v", AArch64::AEK_NONE, {}, {}, FEAT_LS64_V, "", 530}, - {"ls64", AArch64::AEK_LS64, "+ls64", "-ls64", FEAT_LS64, "", 520}, - {"lse", AArch64::AEK_LSE, "+lse", "-lse", FEAT_LSE, "+lse", 80}, - {"lse128", AArch64::AEK_LSE128, "+lse128", "-lse128", FEAT_INIT, "", 0}, - {"memtag", AArch64::AEK_MTE, "+mte", "-mte", FEAT_MEMTAG, "", 440}, - {"memtag2", AArch64::AEK_NONE, {}, {}, FEAT_MEMTAG2, "+mte", 450}, - {"memtag3", AArch64::AEK_NONE, {}, {}, FEAT_MEMTAG3, "+mte", 460}, - {"mops", AArch64::AEK_MOPS, "+mops", "-mops", FEAT_MOPS, "+mops", 650}, - {"pauth", AArch64::AEK_PAUTH, "+pauth", "-pauth", FEAT_INIT, "", 0}, - {"pmull", AArch64::AEK_NONE, {}, {}, FEAT_PMULL, "+aes,+fp-armv8,+neon", 160}, - {"pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon", FEAT_INIT, "", 0}, - {"predres", AArch64::AEK_PREDRES, "+predres", "-predres", FEAT_PREDRES, "+predres", 480}, - {"predres2", AArch64::AEK_SPECRES2, "+specres2", "-specres2", FEAT_INIT, "", 0}, - {"profile", AArch64::AEK_PROFILE, "+spe", "-spe", FEAT_INIT, "", 0}, - {"ras", AArch64::AEK_RAS, "+ras", "-ras", FEAT_INIT, "", 0}, - {"rasv2", AArch64::AEK_RASv2, "+rasv2", "-rasv2", FEAT_INIT, "", 0}, - {"rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc", FEAT_RCPC, "+rcpc", 230}, - {"rcpc2", AArch64::AEK_NONE, {}, {}, FEAT_RCPC2, "+rcpc", 240}, - {"rcpc3", AArch64::AEK_RCPC3, "+rcpc3", "-rcpc3", FEAT_RCPC3, "+rcpc,+rcpc3", 241}, - {"rdm", AArch64::AEK_RDM, "+rdm", "-rdm", FEAT_RDM, "+rdm,+fp-armv8,+neon", 108}, - {"rng", AArch64::AEK_RAND, "+rand", "-rand", FEAT_RNG, "+rand", 10}, - {"rpres", AArch64::AEK_NONE, {}, {}, FEAT_RPRES, "", 300}, - {"sb", AArch64::AEK_SB, "+sb", "-sb", FEAT_SB, "+sb", 470}, - {"sha1", AArch64::AEK_NONE, {}, {}, FEAT_SHA1, "+fp-armv8,+neon", 120}, - {"sha2", AArch64::AEK_SHA2, "+sha2", "-sha2", FEAT_SHA2, "+sha2,+fp-armv8,+neon", 130}, - {"sha3", AArch64::AEK_SHA3, "+sha3", "-sha3", FEAT_SHA3, "+sha3,+sha2,+fp-armv8,+neon", 140}, - {"simd", AArch64::AEK_SIMD, "+neon", "-neon", FEAT_SIMD, "+fp-armv8,+neon", 100}, - {"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4, "+sm4,+fp-armv8,+neon", 106}, - {"sme-f16f16", AArch64::AEK_SMEF16F16, "+sme-f16f16", "-sme-f16f16", FEAT_INIT, "+sme2,+sme-f16f16", 0}, - {"sme-f64f64", AArch64::AEK_SMEF64F64, "+sme-f64f64", "-sme-f64f64", FEAT_SME_F64, "+sme,+sme-f64f64,+bf16", 560}, - {"sme-i16i64", AArch64::AEK_SMEI16I64, "+sme-i16i64", "-sme-i16i64", FEAT_SME_I64, "+sme,+sme-i16i64,+bf16", 570}, - {"sme", AArch64::AEK_SME, "+sme", "-sme", FEAT_SME, "+sme,+bf16", 430}, - {"sme2", AArch64::AEK_SME2, "+sme2", "-sme2", FEAT_SME2, "+sme2,+sme,+bf16", 580}, - {"sme2p1", AArch64::AEK_SME2p1, "+sme2p1", "-sme2p1", FEAT_INIT, "+sme2p1,+sme2,+sme,+bf16", 0}, - {"ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs", FEAT_SSBS, "", 490}, - {"ssbs2", AArch64::AEK_NONE, {}, {}, FEAT_SSBS2, "+ssbs", 500}, - {"sve-bf16", AArch64::AEK_NONE, {}, {}, FEAT_SVE_BF16, "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320}, - {"sve-ebf16", AArch64::AEK_NONE, {}, {}, FEAT_SVE_EBF16, "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330}, - {"sve-i8mm", AArch64::AEK_NONE, {}, {}, FEAT_SVE_I8MM, "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340}, - {"sve", AArch64::AEK_SVE, "+sve", "-sve", FEAT_SVE, "+sve,+fullfp16,+fp-armv8,+neon", 310}, - {"sve2-aes", AArch64::AEK_SVE2AES, "+sve2-aes", "-sve2-aes", FEAT_SVE_AES, "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380}, - {"sve2-bitperm", AArch64::AEK_SVE2BITPERM, "+sve2-bitperm", "-sve2-bitperm", FEAT_SVE_BITPERM, "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400}, - {"sve2-pmull128", AArch64::AEK_NONE, {}, {}, FEAT_SVE_PMULL128, "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390}, - {"sve2-sha3", AArch64::AEK_SVE2SHA3, "+sve2-sha3", "-sve2-sha3", FEAT_SVE_SHA3, "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410}, - {"sve2-sm4", AArch64::AEK_SVE2SM4, "+sve2-sm4", "-sve2-sm4", FEAT_SVE_SM4, "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420}, - {"sve2", AArch64::AEK_SVE2, "+sve2", "-sve2", FEAT_SVE2, "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370}, - {"sve2p1", AArch64::AEK_SVE2p1, "+sve2p1", "-sve2p1", FEAT_INIT, "+sve2p1,+sve2,+sve,+fullfp16,+fp-armv8,+neon", 0}, - {"the", AArch64::AEK_THE, "+the", "-the", FEAT_INIT, "", 0}, - {"tme", AArch64::AEK_TME, "+tme", "-tme", FEAT_INIT, "", 0}, - {"wfxt", AArch64::AEK_NONE, {}, {}, FEAT_WFXT, "+wfxt", 550}, - {"gcs", AArch64::AEK_GCS, "+gcs", "-gcs", FEAT_INIT, "", 0}, - {"fpmr", AArch64::AEK_FPMR, "+fpmr", "-fpmr", FEAT_INIT, "", 0}, - {"fp8", AArch64::AEK_FP8, "+fp8", "-fp8", FEAT_INIT, "+fpmr", 0}, - {"faminmax", AArch64::AEK_FAMINMAX, "+faminmax", "-faminmax", FEAT_INIT, "", 0}, - {"fp8fma", AArch64::AEK_FP8FMA, "+fp8fma", "-fp8fma", FEAT_INIT, "+fpmr", 0}, - {"ssve-fp8fma", AArch64::AEK_SSVE_FP8FMA, "+ssve-fp8fma", "-ssve-fp8fma", FEAT_INIT, "+sme2", 0}, - {"fp8dot2", AArch64::AEK_FP8DOT2, "+fp8dot2", "-fp8dot2", FEAT_INIT, "", 0}, - {"ssve-fp8dot2", AArch64::AEK_SSVE_FP8DOT2, "+ssve-fp8dot2", "-ssve-fp8dot2", FEAT_INIT, "+sme2", 0}, - {"fp8dot4", AArch64::AEK_FP8DOT4, "+fp8dot4", "-fp8dot4", FEAT_INIT, "", 0}, - {"ssve-fp8dot4", AArch64::AEK_SSVE_FP8DOT4, "+ssve-fp8dot4", "-ssve-fp8dot4", FEAT_INIT, "+sme2", 0}, - {"lut", AArch64::AEK_LUT, "+lut", "-lut", FEAT_INIT, "", 0}, - {"sme-lutv2", AArch64::AEK_SME_LUTv2, "+sme-lutv2", "-sme-lutv2", FEAT_INIT, "", 0}, - {"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16", FEAT_INIT, "+fp8,+sme2", 0}, - {"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32", FEAT_INIT, "+sme2,+fp8", 0}, - {"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64", FEAT_INIT, "", 0}, - {"cpa", AArch64::AEK_CPA, "+cpa", "-cpa", FEAT_INIT, "", 0}, - {"pauth-lr", AArch64::AEK_PAUTHLR, "+pauth-lr", "-pauth-lr", FEAT_INIT, "", 0}, - {"tlbiw", AArch64::AEK_TLBIW, "+tlbiw", "-tlbiw", FEAT_INIT, "", 0}, - // Special cases - {"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "", ExtensionInfo::MaxFMVPriority}, -}; -// clang-format on +#define EMIT_EXTENSIONS +#include "llvm/TargetParser/AArch64TargetParserDef.inc" struct ExtensionSet { // Set of extensions which are currently enabled. @@ -328,7 +205,7 @@ inline constexpr ExtensionDependency ExtensionDependencies[] = { {AEK_SVE, AEK_SVE2}, {AEK_SVE, AEK_F32MM}, {AEK_SVE, AEK_F64MM}, - {AEK_SVE2, AEK_SVE2p1}, + {AEK_SVE2, AEK_SVE2P1}, {AEK_SVE2, AEK_SVE2BITPERM}, {AEK_SVE2, AEK_SVE2AES}, {AEK_SVE2, AEK_SVE2SHA3}, @@ -340,7 +217,7 @@ inline constexpr ExtensionDependency ExtensionDependencies[] = { {AEK_SME, AEK_SMEF64F64}, {AEK_SME, AEK_SMEI16I64}, {AEK_SME, AEK_SMEFA64}, - {AEK_SME2, AEK_SME2p1}, + {AEK_SME2, AEK_SME2P1}, {AEK_SME2, AEK_SSVE_FP8FMA}, {AEK_SME2, AEK_SSVE_FP8DOT2}, {AEK_SME2, AEK_SSVE_FP8DOT4}, @@ -350,7 +227,7 @@ inline constexpr ExtensionDependency ExtensionDependencies[] = { {AEK_FP8, AEK_SMEF8F32}, {AEK_LSE, AEK_LSE128}, {AEK_PREDRES, AEK_SPECRES2}, - {AEK_RAS, AEK_RASv2}, + {AEK_RAS, AEK_RASV2}, {AEK_RCPC, AEK_RCPC3}, }; // clang-format on @@ -429,7 +306,7 @@ inline constexpr ArchInfo ARMV8_7A = { VersionTuple{8, 7}, AProfile, "armv8.7-a inline constexpr ArchInfo ARMV8_8A = { VersionTuple{8, 8}, AProfile, "armv8.8-a", "+v8.8a", (ARMV8_7A.DefaultExts | AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))}; inline constexpr ArchInfo ARMV8_9A = { VersionTuple{8, 9}, AProfile, "armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASv2}))}; + AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASV2}))}; inline constexpr ArchInfo ARMV9A = { VersionTuple{9, 0}, AProfile, "armv9-a", "+v9a", (ARMV8_5A.DefaultExts | AArch64::ExtensionBitset({AArch64::AEK_FP16, AArch64::AEK_SVE, AArch64::AEK_SVE2}))}; inline constexpr ArchInfo ARMV9_1A = { VersionTuple{9, 1}, AProfile, "armv9.1-a", "+v9.1a", (ARMV9A.DefaultExts | @@ -438,7 +315,7 @@ inline constexpr ArchInfo ARMV9_2A = { VersionTuple{9, 2}, AProfile, "armv9.2-a inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3}, AProfile, "armv9.3-a", "+v9.3a", (ARMV9_2A.DefaultExts | AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))}; inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile, "armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASv2}))}; + AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASV2}))}; inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts | AArch64::ExtensionBitset({AArch64::AEK_CPA}))}; // For v8-R, we do not enable crypto and align with GCC that enables a more minimal set of optional architecture extensions. diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index b6c8e5f16089..ddc324ea14ed 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -11,42 +11,123 @@ // A SubtargetFeature that can be toggled from the command line, and therefore // has an AEK_* entry in ArmExtKind. +// +// If Function MultiVersioning (FMV) properties are left at their defaults +// (FEAT_INIT, no dependencies, priority 0) it indiates that this extension is +// not an FMV feature, but can be enabled via the command line (-march, -mcpu, +// etc). +// +// Conversely if the ArchExtKindSpelling is set to AEK_NONE, this indicates +// that a feature is FMV-only, and can not be selected on the command line. +// Such extensions should be added via FMVOnlyExtension. class Extension< - string TargetFeatureName, // String used for -target-feature. + string TargetFeatureName, // String used for -target-feature and -march, unless overridden. string Spelling, // The XYZ in HasXYZ and AEK_XYZ. string Desc, // Description. - list Implies = [] // List of dependent features. + list Implies = [], // List of dependent features. + // FMV properties + string _FMVBit = "FEAT_INIT", // FEAT_INIT is repurposed to indicate "not an FMV feature" + string _FMVDependencies = "", + int _FMVPriority = 0 > : SubtargetFeature { string ArchExtKindSpelling = "AEK_" # Spelling; // ArchExtKind enum name. + + // In general, the name written on the command line should match the name + // used for -target-feature. However, there are exceptions. Therefore we + // add a separate field for this, to allow overriding it. Strongly prefer + // not doing so. + string MArchName = TargetFeatureName; + + // Function MultiVersioning (FMV) properties + + // A C++ expression giving the number of the bit in the FMV ABI. + // Currently this is given as a value from the enum "CPUFeatures". + // If this is not set, it indicates that this is not an FMV extension. + string FMVBit = _FMVBit; + + // List of features that this feature depends on. + // FIXME generate this from Implies. + string FMVDependencies = _FMVDependencies; + + // The FMV priority + int FMVPriority = _FMVPriority; +} + +// Some extensions are available for FMV but can not be controlled via the +// command line. These entries: +// - are SubtargetFeatures, so they have (unused) FieldNames on the subtarget +// e.g. HasFMVOnlyFEAT_XYZ +// - have incorrect (empty) Implies fields, because the code that handles FMV +// ignores these dependencies and looks only at FMVDependencies. +// - have no description. +// +// In the generated data structures for extensions (ExtensionInfo), AEK_NONE is +// used to indicate that a feature is FMV only. Therefore ArchExtKindSpelling is +// manually overridden here. +class FMVOnlyExtension + : Extension { + let ArchExtKindSpelling = "AEK_NONE"; // AEK_NONE indicates FMV-only feature } +def : FMVOnlyExtension<"FEAT_DGH", "dgh", "", 260>; +def : FMVOnlyExtension<"FEAT_DIT", "dit", "+dit", 180>; +def : FMVOnlyExtension<"FEAT_DPB", "dpb", "+ccpp", 190>; +def : FMVOnlyExtension<"FEAT_DPB2", "dpb2", "+ccpp,+ccdp", 200>; +def : FMVOnlyExtension<"FEAT_EBF16", "ebf16", "+bf16", 290>; +def : FMVOnlyExtension<"FEAT_FLAGM2", "flagm2", "+flagm,+altnzcv", 30>; +def : FMVOnlyExtension<"FEAT_FRINTTS", "frintts", "+fptoint", 250>; +def : FMVOnlyExtension<"FEAT_LS64_ACCDATA", "ls64_accdata", "+ls64", 540>; +def : FMVOnlyExtension<"FEAT_LS64_V", "ls64_v", "", 530>; +def : FMVOnlyExtension<"FEAT_MEMTAG2", "memtag2", "+mte", 450>; +def : FMVOnlyExtension<"FEAT_MEMTAG3", "memtag3", "+mte", 460>; +def : FMVOnlyExtension<"FEAT_PMULL", "pmull", "+aes,+fp-armv8,+neon", 160>; +def : FMVOnlyExtension<"FEAT_RCPC2", "rcpc2", "+rcpc", 240>; +def : FMVOnlyExtension<"FEAT_RPRES", "rpres", "", 300>; +def : FMVOnlyExtension<"FEAT_SHA1", "sha1", "+fp-armv8,+neon", 120>; +def : FMVOnlyExtension<"FEAT_SSBS2", "ssbs2", "+ssbs", 500>; +def : FMVOnlyExtension<"FEAT_SVE_BF16", "sve-bf16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320>; +def : FMVOnlyExtension<"FEAT_SVE_EBF16", "sve-ebf16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>; +def : FMVOnlyExtension<"FEAT_SVE_I8MM", "sve-i8mm", "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340>; +def : FMVOnlyExtension<"FEAT_SVE_PMULL128", "sve2-pmull128", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390>; +def : FMVOnlyExtension<"FEAT_WFXT", "wfxt", "+wfxt", 550>; + + // Each SubtargetFeature which corresponds to an Arm Architecture feature should // be annotated with the respective FEAT_ feature name from the Architecture // Reference Manual. If a SubtargetFeature enables instructions from multiple // Arm Architecture Features, it should list all the relevant features. Not all // FEAT_ features have a corresponding SubtargetFeature. -def FeatureFPARMv8 : Extension<"fp-armv8", "FPARMv8", "Enable ARMv8 (FEAT_FP)">; +let ArchExtKindSpelling = "AEK_FP", MArchName = "fp" in +def FeatureFPARMv8 : Extension<"fp-armv8", "FPARMv8", + "Enable ARMv8 (FEAT_FP)", [], + "FEAT_FP", "+fp-armv8,+neon", 90>; +let ArchExtKindSpelling = "AEK_SIMD", MArchName = "simd" in def FeatureNEON : Extension<"neon", "NEON", - "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8]>; + "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8], + "FEAT_SIMD", "+fp-armv8,+neon", 100>; def FeatureSM4 : Extension< "sm4", "SM4", - "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON]>; + "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON], + "FEAT_SM4", "+sm4,+fp-armv8,+neon", 106>; def FeatureSHA2 : Extension< "sha2", "SHA2", - "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON]>; + "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON], + "FEAT_SHA2", "+sha2,+fp-armv8,+neon", 130>; def FeatureSHA3 : Extension< "sha3", "SHA3", - "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2]>; + "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2], + "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>; def FeatureAES : Extension< "aes", "AES", - "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON]>; + "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON], + "FEAT_AES", "+fp-armv8,+neon", 150>; // Crypto has been split up and any combination is now valid (see the // crypto definitions above). Also, crypto is now context sensitive: @@ -56,11 +137,13 @@ def FeatureAES : Extension< // meaning anymore. We kept the Crypto definition here for backward // compatibility, and now imply features SHA2 and AES, which was the // "traditional" meaning of Crypto. +let FMVDependencies = "+aes,+sha2" in def FeatureCrypto : Extension<"crypto", "Crypto", "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; def FeatureCRC : Extension<"crc", "CRC", - "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">; + "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)", [], + "FEAT_CRC", "+crc", 110>; def FeatureRAS : Extension<"ras", "RAS", "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">; @@ -70,7 +153,8 @@ def FeatureRASv2 : Extension<"rasv2", "RASv2", [FeatureRAS]>; def FeatureLSE : Extension<"lse", "LSE", - "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)">; + "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)", [], + "FEAT_LSE", "+lse", 80>; def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true", "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">; @@ -83,7 +167,8 @@ def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true", def FeatureRDM : Extension<"rdm", "RDM", "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)", - [FeatureNEON]>; + [FeatureNEON], + "FEAT_RDM", "+rdm,+fp-armv8,+neon", 108>; def FeaturePAN : SubtargetFeature< "pan", "HasPAN", "true", @@ -102,15 +187,20 @@ def FeatureVH : SubtargetFeature<"vh", "HasVH", "true", // This SubtargetFeature is special. It controls only whether codegen will turn // `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The // `FEAT_PMUv3*` system registers are always available for assembly/disassembly. +let MArchName = "pmuv3" in def FeaturePerfMon : Extension<"perfmon", "PerfMon", "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">; +let ArchExtKindSpelling = "AEK_FP16", MArchName = "fp16" in def FeatureFullFP16 : Extension<"fullfp16", "FullFP16", - "Full FP16 (FEAT_FP16)", [FeatureFPARMv8]>; + "Full FP16 (FEAT_FP16)", [FeatureFPARMv8], + "FEAT_FP16", "+fullfp16,+fp-armv8,+neon", 170>; def FeatureFP16FML : Extension<"fp16fml", "FP16FML", - "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>; + "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16], + "FEAT_FP16FML", "+fp16fml,+fullfp16,+fp-armv8,+neon", 175>; +let ArchExtKindSpelling = "AEK_PROFILE", MArchName = "profile" in def FeatureSPE : Extension<"spe", "SPE", "Enable Statistical Profiling extension (FEAT_SPE)">; @@ -127,11 +217,13 @@ def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", "true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >; def FeatureSVE : Extension<"sve", "SVE", - "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16]>; + "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16], + "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>; def FeatureFPMR : Extension<"fpmr", "FPMR", "Enable FPMR Register (FEAT_FPMR)">; +let FMVDependencies = "+fpmr" in def FeatureFP8 : Extension<"fp8", "FP8", "Enable FP8 instructions (FEAT_FP8)">; @@ -157,28 +249,35 @@ def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl", "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">; def FeatureBF16 : Extension<"bf16", "BF16", - "Enable BFloat16 Extension (FEAT_BF16)" >; + "Enable BFloat16 Extension (FEAT_BF16)", [], + "FEAT_BF16", "+bf16", 280>; def FeatureNoSVEFPLD1R : SubtargetFeature<"no-sve-fp-ld1r", "NoSVEFPLD1R", "true", "Avoid using LD1RX instructions for FP">; def FeatureSVE2 : Extension<"sve2", "SVE2", "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)", - [FeatureSVE, FeatureUseScalarIncVL]>; + [FeatureSVE, FeatureUseScalarIncVL], + "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>; def FeatureSVE2AES : Extension<"sve2-aes", "SVE2AES", "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)", - [FeatureSVE2, FeatureAES]>; + [FeatureSVE2, FeatureAES], + "FEAT_SVE_AES", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>; def FeatureSVE2SM4 : Extension<"sve2-sm4", "SVE2SM4", - "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4]>; + "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4], + "FEAT_SVE_SM4", "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420>; def FeatureSVE2SHA3 : Extension<"sve2-sha3", "SVE2SHA3", - "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3]>; + "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3], + "FEAT_SVE_SHA3", "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410>; def FeatureSVE2BitPerm : Extension<"sve2-bitperm", "SVE2BitPerm", - "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2]>; + "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2], + "FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>; +let FMVDependencies = "+sve2p1,+sve2,+sve,+fullfp16,+fp-armv8,+neon" in def FeatureSVE2p1: Extension<"sve2p1", "SVE2p1", "Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>; @@ -315,7 +414,8 @@ def FeatureForce32BitJumpTables "Force jump table entries to be 32-bits wide except at MinSize">; def FeatureRCPC : Extension<"rcpc", "RCPC", - "Enable support for RCPC extension (FEAT_LRCPC)">; + "Enable support for RCPC extension (FEAT_LRCPC)", [], + "FEAT_RCPC", "+rcpc", 230>; def FeatureUseRSqrt : SubtargetFeature< "use-reciprocal-square-root", "UseRSqrt", "true", @@ -323,25 +423,30 @@ def FeatureUseRSqrt : SubtargetFeature< def FeatureDotProd : Extension< "dotprod", "DotProd", - "Enable dot product support (FEAT_DotProd)", [FeatureNEON]>; + "Enable dot product support (FEAT_DotProd)", [FeatureNEON], + "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>; def FeaturePAuth : Extension< "pauth", "PAuth", "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">; +let ArchExtKindSpelling = "AEK_JSCVT", MArchName = "jscvt" in def FeatureJS : Extension< "jsconv", "JS", "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)", - [FeatureFPARMv8]>; + [FeatureFPARMv8], + "FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>; def FeatureCCIDX : SubtargetFeature< "ccidx", "HasCCIDX", "true", "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">; +let ArchExtKindSpelling = "AEK_FCMA", MArchName = "fcma" in def FeatureComplxNum : Extension< "complxnum", "ComplxNum", "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)", - [FeatureNEON]>; + [FeatureNEON], + "FEAT_FCMA", "+fp-armv8,+neon,+complxnum", 220>; def FeatureNV : SubtargetFeature< "nv", "HasNV", "true", @@ -378,7 +483,8 @@ def FeatureTLB_RMI : SubtargetFeature< def FeatureFlagM : Extension< "flagm", "FlagM", - "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)">; + "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)", [], + "FEAT_FLAGM", "+flagm", 20>; // 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", @@ -426,30 +532,41 @@ def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">; def FeatureSB : Extension<"sb", "SB", - "Enable v8.5 Speculation Barrier (FEAT_SB)" >; + "Enable v8.5 Speculation Barrier (FEAT_SB)", [], + "FEAT_SB", "+sb", 470>; def FeatureSSBS : Extension<"ssbs", "SSBS", - "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)" >; + "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)", [], + "FEAT_SSBS", "", 490>; def FeaturePredRes : Extension<"predres", "PredRes", - "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)" >; + "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)", [], + "FEAT_PREDRES", "+predres", 480>; -def FeatureCacheDeepPersist : Extension<"ccdp", "CCDP", +def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "CCDP", "true", "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >; +let ArchExtKindSpelling = "AEK_NONE" in def FeatureBranchTargetId : Extension<"bti", "BTI", - "Enable Branch Target Identification (FEAT_BTI)" >; + "Enable Branch Target Identification (FEAT_BTI)", [], + "FEAT_BTI", "+bti", 510>; +let ArchExtKindSpelling = "AEK_RAND", MArchName = "rng" in def FeatureRandGen : Extension<"rand", "RandGen", - "Enable Random Number generation instructions (FEAT_RNG)" >; + "Enable Random Number generation instructions (FEAT_RNG)", [], + "FEAT_RNG", "+rand", 10>; +// NOTE: "memtag" means FEAT_MTE + FEAT_MTE2 for -march or +// __attribute((target(...))), but only FEAT_MTE for FMV. +let MArchName = "memtag" in def FeatureMTE : Extension<"mte", "MTE", - "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)" >; + "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)", [], + "FEAT_MEMTAG", "", 440>; -def FeatureTRBE : Extension<"trbe", "TRBE", +def FeatureTRBE : SubtargetFeature<"trbe", "TRBE", "true", "Enable Trace Buffer Extension (FEAT_TRBE)">; -def FeatureETE : Extension<"ete", "ETE", +def FeatureETE : SubtargetFeature<"ete", "ETE", "true", "Enable Embedded Trace Extension (FEAT_ETE)", [FeatureTRBE]>; @@ -461,18 +578,25 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", "true", "Use an instruction sequence for taking the address of a global " "that allows a memory tag in the upper address bits">; +let ArchExtKindSpelling = "AEK_I8MM" in def FeatureMatMulInt8 : Extension<"i8mm", "MatMulInt8", - "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)">; + "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)", [], + "FEAT_I8MM", "+i8mm", 270>; +let ArchExtKindSpelling = "AEK_F32MM" in def FeatureMatMulFP32 : Extension<"f32mm", "MatMulFP32", - "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE]>; + "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE], + "FEAT_SVE_F32MM", "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350>; +let ArchExtKindSpelling = "AEK_F64MM" in def FeatureMatMulFP64 : Extension<"f64mm", "MatMulFP64", - "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE]>; + "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE], + "FEAT_SVE_F64MM", "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360>; def FeatureXS : SubtargetFeature<"xs", "HasXS", "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">; +// FIXME link with FMVExtension? def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", "true", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">; @@ -480,13 +604,15 @@ def FeatureHCX : SubtargetFeature< "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">; def FeatureLS64 : Extension<"ls64", "LS64", - "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)">; + "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)", [], + "FEAT_LS64", "", 520>; def FeatureHBC : Extension<"hbc", "HBC", "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">; def FeatureMOPS : Extension<"mops", "MOPS", - "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)">; + "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)", [], + "FEAT_MOPS", "+mops", 650>; def FeatureNMI : SubtargetFeature<"nmi", "HasNMI", "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">; @@ -508,44 +634,54 @@ def FeatureRME : SubtargetFeature<"rme", "HasRME", "true", "Enable Realm Management Extension (FEAT_RME)">; def FeatureSME : Extension<"sme", "SME", - "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>; + "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL], + "FEAT_SME", "+sme,+bf16", 430>; def FeatureSMEF64F64 : Extension<"sme-f64f64", "SMEF64F64", - "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>; + "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME], + "FEAT_SME_F64", "+sme,+sme-f64f64,+bf16", 560>; def FeatureSMEI16I64 : Extension<"sme-i16i64", "SMEI16I64", - "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>; + "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME], + "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>; def FeatureSMEFA64 : Extension<"sme-fa64", "SMEFA64", "Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)", [FeatureSME, FeatureSVE2]>; def FeatureSME2 : Extension<"sme2", "SME2", - "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>; + "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME], + "FEAT_SME2", "+sme2,+sme,+bf16", 580>; +let FMVDependencies = "+sme2,+sme-f16f16" in def FeatureSMEF16F16 : Extension<"sme-f16f16", "SMEF16F16", "Enable SME non-widening Float16 instructions (FEAT_SME_F16F16)", [FeatureSME2]>; +let FMVDependencies = "+sme2p1,+sme2,+sme,+bf16" in def FeatureSME2p1 : Extension<"sme2p1", "SME2p1", "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>; def FeatureFAMINMAX: Extension<"faminmax", "FAMINMAX", "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">; +let FMVDependencies = "+fpmr" in def FeatureFP8FMA : Extension<"fp8fma", "FP8FMA", "Enable fp8 multiply-add instructions (FEAT_FP8FMA)">; +let FMVDependencies = "+sme2" in def FeatureSSVE_FP8FMA : Extension<"ssve-fp8fma", "SSVE_FP8FMA", "Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2]>; def FeatureFP8DOT2: Extension<"fp8dot2", "FP8DOT2", "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)">; +let FMVDependencies = "+sme2" in def FeatureSSVE_FP8DOT2 : Extension<"ssve-fp8dot2", "SSVE_FP8DOT2", "Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSME2]>; def FeatureFP8DOT4: Extension<"fp8dot4", "FP8DOT4", "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)">; +let FMVDependencies = "+sme2" in def FeatureSSVE_FP8DOT4 : Extension<"ssve-fp8dot4", "SSVE_FP8DOT4", "Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSME2]>; def FeatureLUT: Extension<"lut", "LUT", @@ -554,9 +690,11 @@ def FeatureLUT: Extension<"lut", "LUT", def FeatureSME_LUTv2 : Extension<"sme-lutv2", "SME_LUTv2", "Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)">; +let FMVDependencies = "+fp8,+sme2" in def FeatureSMEF8F16 : Extension<"sme-f8f16", "SMEF8F16", "Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSME2, FeatureFP8]>; +let FMVDependencies = "+sme2,+fp8" in def FeatureSMEF8F32 : Extension<"sme-f8f32", "SMEF8F32", "Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>; @@ -592,6 +730,7 @@ def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB", def FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC", "true", "Enable SLC target for PRFM instruction">; +let MArchName = "predres2" in def FeatureSPECRES2 : Extension<"specres2", "SPECRES2", "Enable Speculation Restriction Instruction (FEAT_SPECRES2)", [FeaturePredRes]>; @@ -605,7 +744,8 @@ def FeatureITE : Extension<"ite", "ITE", def FeatureRCPC3 : Extension<"rcpc3", "RCPC3", "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)", - [FeatureRCPC_IMMO]>; + [FeatureRCPC_IMMO], + "FEAT_RCPC3", "+rcpc,+rcpc3", 241>; def FeatureTHE : Extension<"the", "THE", "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">; diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index b61928bd8f98..0455e061f0bf 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1989,19 +1989,19 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64, AArch64::AEK_SME2, AArch64::AEK_HBC, AArch64::AEK_MOPS, - AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1, - AArch64::AEK_SME2p1, AArch64::AEK_B16B16, + AArch64::AEK_PERFMON, AArch64::AEK_SVE2P1, + AArch64::AEK_SME2P1, AArch64::AEK_B16B16, AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC, AArch64::AEK_RCPC3, AArch64::AEK_THE, AArch64::AEK_D128, AArch64::AEK_LSE128, - AArch64::AEK_SPECRES2, AArch64::AEK_RASv2, + AArch64::AEK_SPECRES2, AArch64::AEK_RASV2, AArch64::AEK_ITE, AArch64::AEK_GCS, AArch64::AEK_FPMR, AArch64::AEK_FP8, AArch64::AEK_FAMINMAX, AArch64::AEK_FP8FMA, AArch64::AEK_SSVE_FP8FMA, AArch64::AEK_FP8DOT2, AArch64::AEK_SSVE_FP8DOT2, AArch64::AEK_FP8DOT4, AArch64::AEK_SSVE_FP8DOT4, AArch64::AEK_LUT, - AArch64::AEK_SME_LUTv2, AArch64::AEK_SMEF8F16, + AArch64::AEK_SME_LUTV2, AArch64::AEK_SMEF8F16, AArch64::AEK_SMEF8F32, AArch64::AEK_SMEFA64, AArch64::AEK_CPA, AArch64::AEK_PAUTHLR, AArch64::AEK_TLBIW, AArch64::AEK_JSCVT, diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp index 05aa146b5715..4a46f2ea9586 100644 --- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -15,6 +15,7 @@ #include "llvm/ADT/StringSet.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" +#include using namespace llvm; @@ -33,6 +34,16 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { return Set; }; + // Sort the extensions alphabetically, so they don't appear in tablegen order. + std::vector SortedExtensions = + RK.getAllDerivedDefinitions("Extension"); + auto Alphabetical = [](Record *A, Record *B) -> bool { + const auto MarchA = A->getValueAsString("MArchName"); + const auto MarchB = B->getValueAsString("MArchName"); + return MarchA.compare(MarchB) < 0; // A lexographically less than B + }; + std::sort(SortedExtensions.begin(), SortedExtensions.end(), Alphabetical); + // The ARMProcFamilyEnum values are initialised by SubtargetFeature defs // which set the ARMProcFamily field. We can generate the enum from these defs // which look like this: @@ -57,16 +68,46 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { OS << "ARM_ARCHITECTURE(" << Arch << ")\n"; OS << "\n#undef ARM_ARCHITECTURE\n\n"; - // Emit information for each defined Extension; used to build ArmExtKind. - OS << "#ifndef ARM_EXTENSION\n" - << "#define ARM_EXTENSION(NAME, ENUM)\n" - << "#endif\n\n"; - for (const Record *Rec : RK.getAllDerivedDefinitions("Extension")) { - StringRef Name = Rec->getValueAsString("Name"); - std::string Enum = Rec->getValueAsString("ArchExtKindSpelling").upper(); - OS << "ARM_EXTENSION(" << Name << ", " << Enum << ")\n"; + // Emit the ArchExtKind enum + OS << "#ifdef EMIT_ARCHEXTKIND_ENUM\n" + << "enum ArchExtKind : unsigned {\n" + << " AEK_NONE = 1,\n"; + for (const Record *Rec : SortedExtensions) { + auto AEK = Rec->getValueAsString("ArchExtKindSpelling").upper(); + if (AEK != "AEK_NONE") + OS << " " << AEK << ",\n"; } - OS << "\n#undef ARM_EXTENSION\n\n"; + OS << " AEK_NUM_EXTENSIONS\n" + << "};\n" + << "#undef EMIT_ARCHEXTKIND_ENUM\n" + << "#endif // EMIT_ARCHEXTKIND_ENUM\n"; + + // Emit information for each defined Extension; used to build ArmExtKind. + OS << "#ifdef EMIT_EXTENSIONS\n" + << "inline constexpr ExtensionInfo Extensions[] = {\n"; + for (const Record *Rec : SortedExtensions) { + auto AEK = Rec->getValueAsString("ArchExtKindSpelling").upper(); + OS << " "; + OS << "{\"" << Rec->getValueAsString("MArchName") << "\""; + OS << ", AArch64::" << AEK; + if (AEK == "AEK_NONE") { + // HACK: don't emit posfeat/negfeat strings for FMVOnlyExtensions. + OS << ", {}, {}"; + } else { + OS << ", \"+" << Rec->getValueAsString("Name") << "\""; // posfeature + OS << ", \"-" << Rec->getValueAsString("Name") << "\""; // negfeature + } + OS << ", " << Rec->getValueAsString("FMVBit"); + OS << ", \"" << Rec->getValueAsString("FMVDependencies") << "\""; + OS << ", " << (uint64_t)Rec->getValueAsInt("FMVPriority"); + OS << "},\n"; + }; + OS << " {\"none\", AArch64::AEK_NONE, {}, {}, FEAT_INIT, \"\", " + "ExtensionInfo::MaxFMVPriority},\n"; + OS << "};\n" + << "#undef EMIT_EXTENSIONS\n" + << "#endif // EMIT_EXTENSIONS\n" + << "\n"; } static TableGen::Emitter::Opt -- GitLab From 99f45b4c5b67cccb7845580a67b42776f49ef0e2 Mon Sep 17 00:00:00 2001 From: Keith Smiley Date: Thu, 9 May 2024 14:03:08 -0700 Subject: [PATCH 200/328] [bazel] Fix new CodeGen dep (#91654) ``` .../AMDGPUUtilsAndDesc/AMDGPUCallLowering.h:17:10: fatal error: 'llvm/CodeGen/GlobalISel/CallLowering.h' file not found ``` https://buildkite.com/llvm-project/upstream-bazel/builds/97166 --- utils/bazel/llvm-project-overlay/llvm/BUILD.bazel | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel index c159204cede7..df5cd276b12f 100644 --- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel @@ -636,8 +636,8 @@ cc_binary( cc_binary( name = "llvm-min-tblgen", srcs = [ - "utils/TableGen/Attributes.cpp", "utils/TableGen/ARMTargetDefEmitter.cpp", + "utils/TableGen/Attributes.cpp", "utils/TableGen/Basic/CodeGenIntrinsics.cpp", "utils/TableGen/Basic/CodeGenIntrinsics.h", "utils/TableGen/Basic/SDNodeProperties.cpp", @@ -2421,6 +2421,7 @@ gentbl( strip_include_prefix = "lib/Target/" + target["name"], deps = [ ":BinaryFormat", + ":CodeGen", ":CodeGenTypes", ":Core", ":DebugInfoCodeView", @@ -4049,7 +4050,7 @@ cc_binary( cc_binary( name = "llvm-mca", - srcs =[ + srcs = [ "tools/llvm-mca/llvm-mca.cpp", ], copts = llvm_copts, -- GitLab From db9421381980cdf3d6914f8898a77d3237325019 Mon Sep 17 00:00:00 2001 From: Med Ismail Bennani Date: Thu, 9 May 2024 14:13:44 -0700 Subject: [PATCH 201/328] [lldb/crashlog] Fix test failure when creating a target using command options (#91653) This should fix the various crashlog test failures on the bots: ``` lldb-shell :: ScriptInterpreter/Python/Crashlog/app_specific_backtrace_crashlog.test lldb-shell :: ScriptInterpreter/Python/Crashlog/interactive_crashlog_json.test lldb-shell :: ScriptInterpreter/Python/Crashlog/interactive_crashlog_legacy.test lldb-shell :: ScriptInterpreter/Python/Crashlog/last_exception_backtrace_crashlog.test lldb-shell :: ScriptInterpreter/Python/Crashlog/skipped_status_interactive_crashlog.test ``` When we create a target by using the command option, we don't set it in the crashlog object which later on cause us to fail loading the images. rdar://127832961 Signed-off-by: Med Ismail Bennani --- lldb/examples/python/crashlog.py | 1 + 1 file changed, 1 insertion(+) diff --git a/lldb/examples/python/crashlog.py b/lldb/examples/python/crashlog.py index 2919b9c76e68..641b2e64d53b 100755 --- a/lldb/examples/python/crashlog.py +++ b/lldb/examples/python/crashlog.py @@ -1494,6 +1494,7 @@ def load_crashlog_in_scripted_process(debugger, crashlog_path, options, result): raise InteractiveCrashLogException( "couldn't create target provided by the user (%s)" % options.target_path ) + crashlog.target = target # 2. If the user didn't provide a target, try to create a target using the symbolicator if not target or not target.IsValid(): -- GitLab From ca3917538de1deeb0e51f11fbdbe295b6d3768d1 Mon Sep 17 00:00:00 2001 From: "Yaxun (Sam) Liu" Date: Thu, 9 May 2024 17:14:43 -0400 Subject: [PATCH 202/328] [ClangOffloadBundler] make hipv4 and hip compatible (#91637) The distinction between the hip and hipv4 offload kinds is historically based. Originally, these designations might have indicated different versions of the code object ABI (Application Binary Interface). However, as the system has evolved, the ABI version is now embedded directly within the code object itself, making these historical distinctions irrelevant during the unbundling process. Consequently, hip and hipv4 are treated as compatible in current implementations, facilitating interchangeable handling of code objects without differentiation based on offload kind. This change streamlines code management within the ecosystem. --- clang/docs/ClangOffloadBundler.rst | 12 ++++++++++-- clang/lib/Driver/OffloadBundler.cpp | 5 ++++- clang/test/Driver/clang-offload-bundler.c | 11 +++++++++++ clang/test/Driver/linker-wrapper.c | 4 ++-- .../clang-linker-wrapper/ClangLinkerWrapper.cpp | 2 +- 5 files changed, 28 insertions(+), 6 deletions(-) diff --git a/clang/docs/ClangOffloadBundler.rst b/clang/docs/ClangOffloadBundler.rst index 515e6c00a3b8..3c241027d405 100644 --- a/clang/docs/ClangOffloadBundler.rst +++ b/clang/docs/ClangOffloadBundler.rst @@ -245,7 +245,7 @@ Where: object as a data section with the name ``.hip_fatbin``. hipv4 Offload code object for the HIP language. Used for AMD GPU - code objects with at least ABI version V4 when the + code objects with at least ABI version V4 and above when the ``clang-offload-bundler`` is used to create a *fat binary* to be loaded by the HIP runtime. The fat binary can be loaded directly from a file, or be embedded in the host code @@ -254,6 +254,14 @@ Where: openmp Offload code object for the OpenMP language extension. ============= ============================================================== +Note: The distinction between the `hip` and `hipv4` offload kinds is historically based. +Originally, these designations might have indicated different versions of the +code object ABI. However, as the system has evolved, the ABI version is now embedded +directly within the code object itself, making these historical distinctions irrelevant +during the unbundling process. Consequently, `hip` and `hipv4` are treated as compatible +in current implementations, facilitating interchangeable handling of code objects +without differentiation based on offload kind. + **target-triple** The target triple of the code object. See `Target Triple `_. @@ -295,7 +303,7 @@ Compatibility Rules for Bundle Entry ID A code object, specified using its Bundle Entry ID, can be loaded and executed on a target processor, if: - * Their offload kinds are the same. + * Their offload kinds are the same or comptible. * Their target triples are compatible. * Their Target IDs are compatible as defined in :ref:`compatibility-target-id`. diff --git a/clang/lib/Driver/OffloadBundler.cpp b/clang/lib/Driver/OffloadBundler.cpp index 8cc82a0ee716..191d108e9b73 100644 --- a/clang/lib/Driver/OffloadBundler.cpp +++ b/clang/lib/Driver/OffloadBundler.cpp @@ -113,8 +113,11 @@ bool OffloadTargetInfo::isOffloadKindValid() const { bool OffloadTargetInfo::isOffloadKindCompatible( const StringRef TargetOffloadKind) const { - if (OffloadKind == TargetOffloadKind) + if ((OffloadKind == TargetOffloadKind) || + (OffloadKind == "hip" && TargetOffloadKind == "hipv4") || + (OffloadKind == "hipv4" && TargetOffloadKind == "hip")) return true; + if (BundlerConfig.HipOpenmpCompatible) { bool HIPCompatibleWithOpenMP = OffloadKind.starts_with_insensitive("hip") && TargetOffloadKind == "openmp"; diff --git a/clang/test/Driver/clang-offload-bundler.c b/clang/test/Driver/clang-offload-bundler.c index e492da31abb7..1909ff2d71d0 100644 --- a/clang/test/Driver/clang-offload-bundler.c +++ b/clang/test/Driver/clang-offload-bundler.c @@ -505,6 +505,17 @@ // RUN: -output=%t.res.tgt1 -input=%t.hip.bundle.bc -unbundle 2>&1 | FileCheck %s -check-prefix=NOGFX906 // NOGFX906: error: Can't find bundles for hip-amdgcn-amd-amdhsa--gfx906 +// +// Check hip and hipv4 are compatible as offload kind. +// +// RUN: clang-offload-bundler -type=o -targets=hip-amdgcn-amd-amdhsa--gfx90a -input=%t.tgt1 -output=%t.bundle3.o +// RUN: clang-offload-bundler -type=o -targets=hipv4-amdgcn-amd-amdhsa--gfx90a:sramecc-:xnack+ -output=%t.res.tgt1 -input=%t.bundle3.o -unbundle +// RUN: diff %t.tgt1 %t.res.tgt1 + +// RUN: clang-offload-bundler -type=o -targets=hipv4-amdgcn-amd-amdhsa--gfx90a -input=%t.tgt1 -output=%t.bundle3.o +// RUN: clang-offload-bundler -type=o -targets=hip-amdgcn-amd-amdhsa--gfx90a:sramecc-:xnack+ -output=%t.res.tgt1 -input=%t.bundle3.o -unbundle +// RUN: diff %t.tgt1 %t.res.tgt1 + // // Check archive unbundling // diff --git a/clang/test/Driver/linker-wrapper.c b/clang/test/Driver/linker-wrapper.c index cbf24d4ce3a8..51bf98b2ed39 100644 --- a/clang/test/Driver/linker-wrapper.c +++ b/clang/test/Driver/linker-wrapper.c @@ -120,7 +120,7 @@ __attribute__((visibility("protected"), used)) int x; // HIP: clang{{.*}} -o [[IMG_GFX908:.+]] --target=amdgcn-amd-amdhsa -mcpu=gfx908 // HIP: clang{{.*}} -o [[IMG_GFX90A:.+]] --target=amdgcn-amd-amdhsa -mcpu=gfx90a -// HIP: clang-offload-bundler{{.*}}-type=o -bundle-align=4096 -compress -compression-level=6 -targets=host-x86_64-unknown-linux,hipv4-amdgcn-amd-amdhsa--gfx90a,hipv4-amdgcn-amd-amdhsa--gfx908 -input=/dev/null -input=[[IMG_GFX90A]] -input=[[IMG_GFX908]] -output={{.*}}.hipfb +// HIP: clang-offload-bundler{{.*}}-type=o -bundle-align=4096 -compress -compression-level=6 -targets=host-x86_64-unknown-linux,hip-amdgcn-amd-amdhsa--gfx90a,hip-amdgcn-amd-amdhsa--gfx908 -input=/dev/null -input=[[IMG_GFX90A]] -input=[[IMG_GFX908]] -output={{.*}}.hipfb // RUN: clang-offload-packager -o %t.out \ // RUN: --image=file=%t.elf.o,kind=openmp,triple=amdgcn-amd-amdhsa,arch=gfx908 \ @@ -210,7 +210,7 @@ __attribute__((visibility("protected"), used)) int x; // RUN: %t.o -o a.out 2>&1 | FileCheck %s --check-prefix=RELOCATABLE-LINK-HIP // RELOCATABLE-LINK-HIP: clang{{.*}} -o {{.*}}.img --target=amdgcn-amd-amdhsa -// RELOCATABLE-LINK-HIP: clang-offload-bundler{{.*}} -type=o -bundle-align=4096 -targets=host-x86_64-unknown-linux,hipv4-amdgcn-amd-amdhsa--gfx90a -input=/dev/null -input={{.*}} -output={{.*}} +// RELOCATABLE-LINK-HIP: clang-offload-bundler{{.*}} -type=o -bundle-align=4096 -targets=host-x86_64-unknown-linux,hip-amdgcn-amd-amdhsa--gfx90a -input=/dev/null -input={{.*}} -output={{.*}} // RELOCATABLE-LINK-HIP: /usr/bin/ld.lld{{.*}}-r // RELOCATABLE-LINK-HIP: llvm-objcopy{{.*}}a.out --remove-section .llvm.offloading diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index a1879fc7712d..69d8cb446fad 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -413,7 +413,7 @@ fatbinary(ArrayRef> InputFiles, SmallVector Targets = {"-targets=host-x86_64-unknown-linux"}; for (const auto &[File, Arch] : InputFiles) - Targets.push_back(Saver.save("hipv4-amdgcn-amd-amdhsa--" + Arch)); + Targets.push_back(Saver.save("hip-amdgcn-amd-amdhsa--" + Arch)); CmdArgs.push_back(Saver.save(llvm::join(Targets, ","))); #ifdef _WIN32 -- GitLab From 5a0e0b659fb5c652c66a083224bf300b4ae32452 Mon Sep 17 00:00:00 2001 From: Schrodinger ZHU Yifan Date: Thu, 9 May 2024 17:27:59 -0400 Subject: [PATCH 203/328] Revert "[libc][NFC] adjust time related implementations" (#91657) Reverts llvm/llvm-project#91485. It breaks GPU and fuchisa. --- libc/hdr/CMakeLists.txt | 9 ---- libc/hdr/time_macros.h | 22 --------- libc/hdr/types/CMakeLists.txt | 45 ------------------- libc/hdr/types/clock_t.h | 22 --------- libc/hdr/types/clockid_t.h | 22 --------- libc/hdr/types/struct_timeval.h | 21 --------- libc/hdr/types/suseconds_t.h | 22 --------- libc/hdr/types/time_t.h | 22 --------- libc/src/__support/CMakeLists.txt | 2 - libc/src/__support/time/CMakeLists.txt | 19 -------- libc/src/__support/time/clock_gettime.h | 23 ---------- libc/src/__support/time/linux/CMakeLists.txt | 14 ------ libc/src/__support/time/units.h | 38 ---------------- libc/src/time/clock.h | 2 +- libc/src/time/clock_gettime.h | 5 +-- libc/src/time/gettimeofday.h | 2 +- libc/src/time/linux/CMakeLists.txt | 30 ++++++------- libc/src/time/linux/clock.cpp | 20 +++++---- .../linux/clockGetTimeImpl.h} | 25 +++++++---- libc/src/time/linux/clock_gettime.cpp | 9 +++- libc/src/time/linux/gettimeofday.cpp | 14 +++--- libc/src/time/linux/time.cpp | 12 +++-- libc/src/time/nanosleep.h | 4 +- libc/src/time/time_func.h | 2 +- 24 files changed, 71 insertions(+), 335 deletions(-) delete mode 100644 libc/hdr/time_macros.h delete mode 100644 libc/hdr/types/clock_t.h delete mode 100644 libc/hdr/types/clockid_t.h delete mode 100644 libc/hdr/types/struct_timeval.h delete mode 100644 libc/hdr/types/suseconds_t.h delete mode 100644 libc/hdr/types/time_t.h delete mode 100644 libc/src/__support/time/CMakeLists.txt delete mode 100644 libc/src/__support/time/clock_gettime.h delete mode 100644 libc/src/__support/time/linux/CMakeLists.txt delete mode 100644 libc/src/__support/time/units.h rename libc/src/{__support/time/linux/clock_gettime.cpp => time/linux/clockGetTimeImpl.h} (64%) diff --git a/libc/hdr/CMakeLists.txt b/libc/hdr/CMakeLists.txt index 754934251430..179b05e6ee96 100644 --- a/libc/hdr/CMakeLists.txt +++ b/libc/hdr/CMakeLists.txt @@ -68,13 +68,4 @@ add_proxy_header_library( libc.include.llvm-libc-macros.sys_epoll_macros ) -add_proxy_header_library( - time_macros - HDRS - time_macros.h - FULL_BUILD_DEPENDS - libc.include.time - libc.include.llvm-libc-macros.time_macros -) - add_subdirectory(types) diff --git a/libc/hdr/time_macros.h b/libc/hdr/time_macros.h deleted file mode 100644 index dc36fe66f7a8..000000000000 --- a/libc/hdr/time_macros.h +++ /dev/null @@ -1,22 +0,0 @@ -//===-- Definition of macros from time.h ----------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_HDR_TIME_MACROS_H -#define LLVM_LIBC_HDR_TIME_MACROS_H - -#ifdef LIBC_FULL_BUILD - -#include "include/llvm-libc-macros/time-macros.h" - -#else // Overlay mode - -#include - -#endif // LLVM_LIBC_FULL_BUILD - -#endif // LLVM_LIBC_HDR_TIME_MACROS_H diff --git a/libc/hdr/types/CMakeLists.txt b/libc/hdr/types/CMakeLists.txt index 3a1bb2f3c340..46a66ec59020 100644 --- a/libc/hdr/types/CMakeLists.txt +++ b/libc/hdr/types/CMakeLists.txt @@ -63,48 +63,3 @@ add_proxy_header_library( libc.include.llvm-libc-types.fexcept_t libc.include.fenv ) - -add_proxy_header_library( - time_t - HDRS - time_t.h - FULL_BUILD_DEPENDS - libc.include.llvm-libc-types.time_t - libc.include.time -) - -add_proxy_header_library( - clockid_t - HDRS - clockid_t.h - FULL_BUILD_DEPENDS - libc.include.llvm-libc-types.clockid_t - libc.include.sys_types -) - -add_proxy_header_library( - clock_t - HDRS - clock_t.h - FULL_BUILD_DEPENDS - libc.include.llvm-libc-types.clock_t - libc.include.time -) - -add_proxy_header_library( - suseconds_t - HDRS - suseconds_t.h - FULL_BUILD_DEPENDS - libc.include.llvm-libc-types.suseconds_t - libc.include.sys_time -) - -add_proxy_header_library( - struct_timeval - HDRS - struct_timeval.h - FULL_BUILD_DEPENDS - libc.include.llvm-libc-types.struct_timeval - libc.include.sys_time -) diff --git a/libc/hdr/types/clock_t.h b/libc/hdr/types/clock_t.h deleted file mode 100644 index b0b658e96c3d..000000000000 --- a/libc/hdr/types/clock_t.h +++ /dev/null @@ -1,22 +0,0 @@ -//===-- Proxy for clock_t -------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_HDR_TYPES_CLOCK_T_H -#define LLVM_LIBC_HDR_TYPES_CLOCK_T_H - -#ifdef LIBC_FULL_BUILD - -#include "include/llvm-libc-types/clock_t.h" - -#else // Overlay mode - -#include - -#endif // LLVM_LIBC_FULL_BUILD - -#endif // LLVM_LIBC_HDR_TYPES_CLOCK_T_H diff --git a/libc/hdr/types/clockid_t.h b/libc/hdr/types/clockid_t.h deleted file mode 100644 index 333342072a2f..000000000000 --- a/libc/hdr/types/clockid_t.h +++ /dev/null @@ -1,22 +0,0 @@ -//===-- Proxy for clockid_t -----------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_HDR_TYPES_CLOCKID_T_H -#define LLVM_LIBC_HDR_TYPES_CLOCKID_T_H - -#ifdef LIBC_FULL_BUILD - -#include "include/llvm-libc-types/clockid_t.h" - -#else // Overlay mode - -#include - -#endif // LLVM_LIBC_FULL_BUILD - -#endif // LLVM_LIBC_HDR_TYPES_CLOCKID_T_H diff --git a/libc/hdr/types/struct_timeval.h b/libc/hdr/types/struct_timeval.h deleted file mode 100644 index 8fc321a52d71..000000000000 --- a/libc/hdr/types/struct_timeval.h +++ /dev/null @@ -1,21 +0,0 @@ -//===-- Proxy for struct timeval ----------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -#ifndef LLVM_LIBC_HDR_TYPES_STRUCT_TIMEVAL_H -#define LLVM_LIBC_HDR_TYPES_STRUCT_TIMEVAL_H - -#ifdef LIBC_FULL_BUILD - -#include "include/llvm-libc-types/struct_timeval.h" - -#else - -#include - -#endif // LIBC_FULL_BUILD - -#endif // LLVM_LIBC_HDR_TYPES_STRUCT_TIMEVAL_H diff --git a/libc/hdr/types/suseconds_t.h b/libc/hdr/types/suseconds_t.h deleted file mode 100644 index 72e54a965f75..000000000000 --- a/libc/hdr/types/suseconds_t.h +++ /dev/null @@ -1,22 +0,0 @@ -//===-- Proxy for suseconds_t ---------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_HDR_TIMES_SUSECONDS_T_H -#define LLVM_LIBC_HDR_TIMES_SUSECONDS_T_H - -#ifdef LIBC_FULL_BUILD - -#include "include/llvm-libc-types/suseconds_t.h" - -#else // Overlay mode - -#include - -#endif // LLVM_LIBC_FULL_BUILD - -#endif // #ifndef LLVM_LIBC_HDR_TIMES_SUSECONDS_T_H diff --git a/libc/hdr/types/time_t.h b/libc/hdr/types/time_t.h deleted file mode 100644 index fc9a1506a2cd..000000000000 --- a/libc/hdr/types/time_t.h +++ /dev/null @@ -1,22 +0,0 @@ -//===-- Proxy for time_t --------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_HDR_TYPES_TIME_T_H -#define LLVM_LIBC_HDR_TYPES_TIME_T_H - -#ifdef LIBC_FULL_BUILD - -#include "include/llvm-libc-types/time_t.h" - -#else // Overlay mode - -#include - -#endif // LLVM_LIBC_FULL_BUILD - -#endif // LLVM_LIBC_HDR_TYPES_TIME_T_H diff --git a/libc/src/__support/CMakeLists.txt b/libc/src/__support/CMakeLists.txt index 32d693ec6a26..dcae55e050bf 100644 --- a/libc/src/__support/CMakeLists.txt +++ b/libc/src/__support/CMakeLists.txt @@ -281,5 +281,3 @@ add_subdirectory(File) add_subdirectory(HashTable) add_subdirectory(fixed_point) - -add_subdirectory(time) diff --git a/libc/src/__support/time/CMakeLists.txt b/libc/src/__support/time/CMakeLists.txt deleted file mode 100644 index 36ce4f9dadb2..000000000000 --- a/libc/src/__support/time/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) - add_subdirectory(${LIBC_TARGET_OS}) -endif() - -add_object_library( - clock_gettime - ALIAS - DEPENDS - .${LIBC_TARGET_OS}.clock_gettime -) - -add_header_library( - units - HDRS - units.h - DEPENDS - libc.src.__support.common - libc.hdr.types.time_t -) diff --git a/libc/src/__support/time/clock_gettime.h b/libc/src/__support/time/clock_gettime.h deleted file mode 100644 index 0655ccdc0028..000000000000 --- a/libc/src/__support/time/clock_gettime.h +++ /dev/null @@ -1,23 +0,0 @@ -//===--- clock_gettime internal implementation ------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_SRC___SUPPORT_TIME_CLOCK_GETTIME_H -#define LLVM_LIBC_SRC___SUPPORT_TIME_CLOCK_GETTIME_H -#include "hdr/types/clockid_t.h" -#include "hdr/types/struct_timespec.h" -#include "src/__support/common.h" - -#include "src/__support/error_or.h" - -namespace LIBC_NAMESPACE { -namespace internal { -ErrorOr clock_gettime(clockid_t clockid, timespec *ts); -} -} // namespace LIBC_NAMESPACE - -#endif // LLVM_LIBC_SRC___SUPPORT_TIME_CLOCK_GETTIME_H diff --git a/libc/src/__support/time/linux/CMakeLists.txt b/libc/src/__support/time/linux/CMakeLists.txt deleted file mode 100644 index 034fa317ff6d..000000000000 --- a/libc/src/__support/time/linux/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -add_object_library( - clock_gettime - HDRS - ../clock_gettime.h - SRCS - clock_gettime.cpp - DEPENDS - libc.include.sys_syscall - libc.hdr.types.struct_timespec - libc.hdr.types.clockid_t - libc.src.__support.common - libc.src.__support.error_or - libc.src.__support.OSUtil.osutil -) diff --git a/libc/src/__support/time/units.h b/libc/src/__support/time/units.h deleted file mode 100644 index f6bd19f9b139..000000000000 --- a/libc/src/__support/time/units.h +++ /dev/null @@ -1,38 +0,0 @@ -//===--- Time units conversion ----------------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_SRC___SUPPORT_TIME_UNITS_H -#define LLVM_LIBC_SRC___SUPPORT_TIME_UNITS_H - -#include "hdr/types/time_t.h" -#include "src/__support/common.h" - -namespace LIBC_NAMESPACE { -namespace time_units { -LIBC_INLINE constexpr time_t operator""_s_ns(unsigned long long s) { - return s * 1'000'000'000; -} -LIBC_INLINE constexpr time_t operator""_s_us(unsigned long long s) { - return s * 1'000'000; -} -LIBC_INLINE constexpr time_t operator""_s_ms(unsigned long long s) { - return s * 1'000; -} -LIBC_INLINE constexpr time_t operator""_ms_ns(unsigned long long ms) { - return ms * 1'000'000; -} -LIBC_INLINE constexpr time_t operator""_ms_us(unsigned long long ms) { - return ms * 1'000; -} -LIBC_INLINE constexpr time_t operator""_us_ns(unsigned long long us) { - return us * 1'000; -} -} // namespace time_units -} // namespace LIBC_NAMESPACE - -#endif // LLVM_LIBC_SRC___SUPPORT_TIME_UNITS_H diff --git a/libc/src/time/clock.h b/libc/src/time/clock.h index f5d14d036e13..d4af7656644a 100644 --- a/libc/src/time/clock.h +++ b/libc/src/time/clock.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_TIME_CLOCK_H #define LLVM_LIBC_SRC_TIME_CLOCK_H -#include "hdr/types/clock_t.h" +#include namespace LIBC_NAMESPACE { diff --git a/libc/src/time/clock_gettime.h b/libc/src/time/clock_gettime.h index 48e81a355429..72e2e1949feb 100644 --- a/libc/src/time/clock_gettime.h +++ b/libc/src/time/clock_gettime.h @@ -9,12 +9,11 @@ #ifndef LLVM_LIBC_SRC_TIME_CLOCK_GETTIME_H #define LLVM_LIBC_SRC_TIME_CLOCK_GETTIME_H -#include "hdr/types/clockid_t.h" -#include "hdr/types/struct_timespec.h" +#include namespace LIBC_NAMESPACE { -int clock_gettime(clockid_t clockid, timespec *tp); +int clock_gettime(clockid_t clockid, struct timespec *tp); } // namespace LIBC_NAMESPACE diff --git a/libc/src/time/gettimeofday.h b/libc/src/time/gettimeofday.h index 62ee31edcad6..880b94cee731 100644 --- a/libc/src/time/gettimeofday.h +++ b/libc/src/time/gettimeofday.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_TIME_GETTIMEOFDAY_H #define LLVM_LIBC_SRC_TIME_GETTIMEOFDAY_H -#include "hdr/types/struct_timeval.h" +#include namespace LIBC_NAMESPACE { diff --git a/libc/src/time/linux/CMakeLists.txt b/libc/src/time/linux/CMakeLists.txt index 8a0e6b04b66e..df79bf598626 100644 --- a/libc/src/time/linux/CMakeLists.txt +++ b/libc/src/time/linux/CMakeLists.txt @@ -5,9 +5,9 @@ add_entrypoint_object( HDRS ../time_func.h DEPENDS - libc.hdr.time_macros - libc.hdr.types.time_t - libc.src.__support.time.clock_gettime + libc.include.time + libc.include.sys_syscall + libc.src.__support.OSUtil.osutil libc.src.errno.errno ) @@ -18,11 +18,10 @@ add_entrypoint_object( HDRS ../clock.h DEPENDS - libc.hdr.time_macros - libc.hdr.types.clock_t - libc.src.__support.time.units - libc.src.__support.time.clock_gettime + libc.include.time + libc.include.sys_syscall libc.src.__support.CPP.limits + libc.src.__support.OSUtil.osutil libc.src.errno.errno ) @@ -33,10 +32,10 @@ add_entrypoint_object( HDRS ../nanosleep.h DEPENDS - libc.hdr.types.struct_timespec + libc.include.time libc.include.sys_syscall - libc.src.__support.OSUtil.osutil libc.src.__support.CPP.limits + libc.src.__support.OSUtil.osutil libc.src.errno.errno ) @@ -47,9 +46,9 @@ add_entrypoint_object( HDRS ../clock_gettime.h DEPENDS - libc.hdr.types.clockid_t - libc.hdr.types.struct_timespec - libc.src.__support.time.clock_gettime + libc.include.time + libc.include.sys_syscall + libc.src.__support.OSUtil.osutil libc.src.errno.errno ) @@ -60,9 +59,8 @@ add_entrypoint_object( HDRS ../gettimeofday.h DEPENDS - libc.hdr.time_macros - libc.hdr.types.suseconds_t - libc.src.__support.time.clock_gettime - libc.src.__support.time.units + libc.include.time + libc.include.sys_syscall + libc.src.__support.OSUtil.osutil libc.src.errno.errno ) diff --git a/libc/src/time/linux/clock.cpp b/libc/src/time/linux/clock.cpp index fc48e2792747..1e95f0526bc9 100644 --- a/libc/src/time/linux/clock.cpp +++ b/libc/src/time/linux/clock.cpp @@ -7,19 +7,21 @@ //===----------------------------------------------------------------------===// #include "src/time/clock.h" -#include "hdr/time_macros.h" + #include "src/__support/CPP/limits.h" +#include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" -#include "src/__support/time/clock_gettime.h" -#include "src/__support/time/units.h" #include "src/errno/libc_errno.h" +#include "src/time/linux/clockGetTimeImpl.h" + +#include // For syscall numbers. +#include namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(clock_t, clock, ()) { - using namespace time_units; struct timespec ts; - auto result = internal::clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &ts); + auto result = internal::clock_gettimeimpl(CLOCK_PROCESS_CPUTIME_ID, &ts); if (!result.has_value()) { libc_errno = result.error(); return -1; @@ -32,15 +34,15 @@ LLVM_LIBC_FUNCTION(clock_t, clock, ()) { cpp::numeric_limits::max() / CLOCKS_PER_SEC; if (ts.tv_sec > CLOCK_SECS_MAX) return clock_t(-1); - if (ts.tv_nsec / 1_s_ns > CLOCK_SECS_MAX - ts.tv_sec) + if (ts.tv_nsec / 1000000000 > CLOCK_SECS_MAX - ts.tv_sec) return clock_t(-1); // For the integer computation converting tv_nsec to clocks to work // correctly, we want CLOCKS_PER_SEC to be less than 1000000000. - static_assert(1_s_ns > CLOCKS_PER_SEC, - "Expected CLOCKS_PER_SEC to be less than 1'000'000'000."); + static_assert(1000000000 > CLOCKS_PER_SEC, + "Expected CLOCKS_PER_SEC to be less than 1000000000."); return clock_t(ts.tv_sec * CLOCKS_PER_SEC + - ts.tv_nsec / (1_s_ns / CLOCKS_PER_SEC)); + ts.tv_nsec / (1000000000 / CLOCKS_PER_SEC)); } } // namespace LIBC_NAMESPACE diff --git a/libc/src/__support/time/linux/clock_gettime.cpp b/libc/src/time/linux/clockGetTimeImpl.h similarity index 64% rename from libc/src/__support/time/linux/clock_gettime.cpp rename to libc/src/time/linux/clockGetTimeImpl.h index 6a131df9ba59..8c8c9fcf845c 100644 --- a/libc/src/__support/time/linux/clock_gettime.cpp +++ b/libc/src/time/linux/clockGetTimeImpl.h @@ -1,4 +1,4 @@ -//===--- clock_gettime linux implementation ---------------------*- C++ -*-===// +//===- Linux implementation of the POSIX clock_gettime function -*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,14 +6,23 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H -#define LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H -#include "src/__support/time/clock_gettime.h" -#include "src/__support/OSUtil/syscall.h" -#include +#ifndef LLVM_LIBC_SRC_TIME_LINUX_CLOCKGETTIMEIMPL_H +#define LLVM_LIBC_SRC_TIME_LINUX_CLOCKGETTIMEIMPL_H + +#include "src/__support/OSUtil/syscall.h" // For internal syscall function. +#include "src/__support/common.h" +#include "src/__support/error_or.h" +#include "src/errno/libc_errno.h" + +#include // For int64_t. +#include // For syscall numbers. +#include + namespace LIBC_NAMESPACE { namespace internal { -ErrorOr clock_gettime(clockid_t clockid, timespec *ts) { + +LIBC_INLINE ErrorOr clock_gettimeimpl(clockid_t clockid, + struct timespec *ts) { #if SYS_clock_gettime int ret = LIBC_NAMESPACE::syscall_impl(SYS_clock_gettime, static_cast(clockid), @@ -36,4 +45,4 @@ ErrorOr clock_gettime(clockid_t clockid, timespec *ts) { } // namespace internal } // namespace LIBC_NAMESPACE -#endif // LLVM_LIBC_SRC___SUPPORT_TIME_LINUX_CLOCK_GETTIME_H +#endif // LLVM_LIBC_SRC_TIME_LINUX_CLOCKGETTIMEIMPL_H diff --git a/libc/src/time/linux/clock_gettime.cpp b/libc/src/time/linux/clock_gettime.cpp index 920363e85e06..47e974a866c8 100644 --- a/libc/src/time/linux/clock_gettime.cpp +++ b/libc/src/time/linux/clock_gettime.cpp @@ -7,16 +7,21 @@ //===----------------------------------------------------------------------===// #include "src/time/clock_gettime.h" + +#include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" -#include "src/__support/time/clock_gettime.h" #include "src/errno/libc_errno.h" +#include "src/time/linux/clockGetTimeImpl.h" + +#include // For syscall numbers. +#include namespace LIBC_NAMESPACE { // TODO(michaelrj): Move this into time/linux with the other syscalls. LLVM_LIBC_FUNCTION(int, clock_gettime, (clockid_t clockid, struct timespec *ts)) { - auto result = internal::clock_gettime(clockid, ts); + auto result = internal::clock_gettimeimpl(clockid, ts); // A negative return value indicates an error with the magnitude of the // value being the error code. diff --git a/libc/src/time/linux/gettimeofday.cpp b/libc/src/time/linux/gettimeofday.cpp index c7bcd45e01fa..07ab4d579176 100644 --- a/libc/src/time/linux/gettimeofday.cpp +++ b/libc/src/time/linux/gettimeofday.cpp @@ -7,24 +7,24 @@ //===----------------------------------------------------------------------===// #include "src/time/gettimeofday.h" -#include "hdr/time_macros.h" -#include "hdr/types/suseconds_t.h" + +#include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" -#include "src/__support/time/clock_gettime.h" -#include "src/__support/time/units.h" #include "src/errno/libc_errno.h" +#include "src/time/linux/clockGetTimeImpl.h" + +#include // For syscall numbers. namespace LIBC_NAMESPACE { // TODO(michaelrj): Move this into time/linux with the other syscalls. LLVM_LIBC_FUNCTION(int, gettimeofday, (struct timeval * tv, [[maybe_unused]] void *unused)) { - using namespace time_units; if (tv == nullptr) return 0; struct timespec ts; - auto result = internal::clock_gettime(CLOCK_REALTIME, &ts); + auto result = internal::clock_gettimeimpl(CLOCK_REALTIME, &ts); // A negative return value indicates an error with the magnitude of the // value being the error code. @@ -34,7 +34,7 @@ LLVM_LIBC_FUNCTION(int, gettimeofday, } tv->tv_sec = ts.tv_sec; - tv->tv_usec = static_cast(ts.tv_nsec / 1_us_ns); + tv->tv_usec = static_cast(ts.tv_nsec / 1000); return 0; } diff --git a/libc/src/time/linux/time.cpp b/libc/src/time/linux/time.cpp index 93d5d7362764..e286fae095b2 100644 --- a/libc/src/time/linux/time.cpp +++ b/libc/src/time/linux/time.cpp @@ -6,18 +6,22 @@ // //===----------------------------------------------------------------------===// -#include "hdr/time_macros.h" +#include "src/time/time_func.h" + +#include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" -#include "src/__support/time/clock_gettime.h" #include "src/errno/libc_errno.h" -#include "src/time/time_func.h" +#include "src/time/linux/clockGetTimeImpl.h" + +#include // For syscall numbers. +#include namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(time_t, time, (time_t * tp)) { // TODO: Use the Linux VDSO to fetch the time and avoid the syscall. struct timespec ts; - auto result = internal::clock_gettime(CLOCK_REALTIME, &ts); + auto result = internal::clock_gettimeimpl(CLOCK_REALTIME, &ts); if (!result.has_value()) { libc_errno = result.error(); return -1; diff --git a/libc/src/time/nanosleep.h b/libc/src/time/nanosleep.h index 2309666b2304..757394232c07 100644 --- a/libc/src/time/nanosleep.h +++ b/libc/src/time/nanosleep.h @@ -9,11 +9,11 @@ #ifndef LLVM_LIBC_SRC_TIME_NANOSLEEP_H #define LLVM_LIBC_SRC_TIME_NANOSLEEP_H -#include "hdr/types/struct_timespec.h" +#include namespace LIBC_NAMESPACE { -int nanosleep(const timespec *req, timespec *rem); +int nanosleep(const struct timespec *req, struct timespec *rem); } // namespace LIBC_NAMESPACE diff --git a/libc/src/time/time_func.h b/libc/src/time/time_func.h index 2a5239220942..beb02020b575 100644 --- a/libc/src/time/time_func.h +++ b/libc/src/time/time_func.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_TIME_TIME_FUNC_H #define LLVM_LIBC_SRC_TIME_TIME_FUNC_H -#include "hdr/types/time_t.h" +#include // Note this header file is named time_func.h to avoid conflicts with the // public header file time.h. -- GitLab From dfff57e751f6bae12172a1a246e1f8b33db042f8 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 9 May 2024 14:39:06 -0700 Subject: [PATCH 204/328] [RISCV] Add isel special case for (and (shl X, c2), c1) -> (slli_uw (srli x, c3-c2), c3). (#91638) Where c1 is a shifted mask with 32 set bits and c3 trailing zeros. --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 13 +++++++ llvm/test/CodeGen/RISCV/rv64zba.ll | 40 ++++++++++++++++++--- 2 files changed, 49 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index e73a3af92af6..3c4646b95715 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -1416,6 +1416,19 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { ReplaceNode(Node, SLLI); return; } + + // If we have 32 bits in the mask, we can use SLLI_UW instead of SLLI. + if (C2 < Trailing && Leading + Trailing == 32 && OneUseOrZExtW && + Subtarget->hasStdExtZba()) { + SDNode *SRLI = CurDAG->getMachineNode( + RISCV::SRLI, DL, VT, X, + CurDAG->getTargetConstant(Trailing - C2, DL, VT)); + SDNode *SLLI_UW = CurDAG->getMachineNode( + RISCV::SLLI_UW, DL, VT, SDValue(SRLI, 0), + CurDAG->getTargetConstant(Trailing, DL, VT)); + ReplaceNode(Node, SLLI_UW); + return; + } } } diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll index 8fe221f2a297..dc93c0215a25 100644 --- a/llvm/test/CodeGen/RISCV/rv64zba.ll +++ b/llvm/test/CodeGen/RISCV/rv64zba.ll @@ -2866,8 +2866,7 @@ define ptr @gep_lshr_i32(ptr %0, i64 %1) { ; ; RV64ZBA-LABEL: gep_lshr_i32: ; RV64ZBA: # %bb.0: # %entry -; RV64ZBA-NEXT: slli a1, a1, 2 -; RV64ZBA-NEXT: srli a1, a1, 4 +; RV64ZBA-NEXT: srli a1, a1, 2 ; RV64ZBA-NEXT: slli.uw a1, a1, 4 ; RV64ZBA-NEXT: sh2add a1, a1, a1 ; RV64ZBA-NEXT: add a0, a0, a1 @@ -2891,8 +2890,7 @@ define i64 @srli_slliw(i64 %1) { ; ; RV64ZBA-LABEL: srli_slliw: ; RV64ZBA: # %bb.0: # %entry -; RV64ZBA-NEXT: slli a0, a0, 2 -; RV64ZBA-NEXT: srli a0, a0, 4 +; RV64ZBA-NEXT: srli a0, a0, 2 ; RV64ZBA-NEXT: slli.uw a0, a0, 4 ; RV64ZBA-NEXT: ret entry: @@ -2902,6 +2900,40 @@ entry: ret i64 %4 } +define i64 @srli_slliw_canonical(i64 %0) { +; RV64I-LABEL: srli_slliw_canonical: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: slli a0, a0, 2 +; RV64I-NEXT: li a1, 1 +; RV64I-NEXT: slli a1, a1, 36 +; RV64I-NEXT: addi a1, a1, -16 +; RV64I-NEXT: and a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: srli_slliw_canonical: +; RV64ZBA: # %bb.0: # %entry +; RV64ZBA-NEXT: srli a0, a0, 2 +; RV64ZBA-NEXT: slli.uw a0, a0, 4 +; RV64ZBA-NEXT: ret +entry: + %1 = shl i64 %0, 2 + %2 = and i64 %1, 68719476720 + ret i64 %2 +} + +; Make sure we don't accidentally use slli.uw with a shift of 32. +define i64 @srli_slliuw_negative_test(i64 %0) { +; CHECK-LABEL: srli_slliuw_negative_test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: srli a0, a0, 6 +; CHECK-NEXT: slli a0, a0, 32 +; CHECK-NEXT: ret +entry: + %1 = lshr i64 %0, 6 + %2 = shl i64 %1, 32 + ret i64 %2 +} + define i64 @srli_slli_i16(i64 %1) { ; CHECK-LABEL: srli_slli_i16: ; CHECK: # %bb.0: # %entry -- GitLab From a3457369cd12b093185a5bda3443e08a4390f3ed Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Thu, 9 May 2024 14:38:28 -0700 Subject: [PATCH 205/328] [Orc] Fix `-Wsign-compare` warnings in unittest Multiple compares against `LookupsCompleted`, which is effectively an unsigned long, with constant signed integer were throwing -Wsign-compare warnings. This is effectively NFC. --- llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp b/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp index a6fa69f97fcb..53a74c833eb3 100644 --- a/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp +++ b/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp @@ -1170,7 +1170,7 @@ TEST_F(CoreAPIsStandardTest, ErrorFromAutoSuspendedAsynchronousGeneratorTest) { }, NoDependenciesToRegister); - EXPECT_EQ(LookupsCompleted, 0); + EXPECT_EQ(LookupsCompleted, 0U); // Suspend the first lookup. auto LS1 = std::move(G.takeLookup().LS); @@ -1185,7 +1185,7 @@ TEST_F(CoreAPIsStandardTest, ErrorFromAutoSuspendedAsynchronousGeneratorTest) { }, NoDependenciesToRegister); - EXPECT_EQ(LookupsCompleted, 0); + EXPECT_EQ(LookupsCompleted, 0U); // Unsuspend the first lookup. LS1.continueLookup(make_error("boom", inconvertibleErrorCode())); @@ -1194,7 +1194,7 @@ TEST_F(CoreAPIsStandardTest, ErrorFromAutoSuspendedAsynchronousGeneratorTest) { G.takeLookup().LS.continueLookup( make_error("boom", inconvertibleErrorCode())); - EXPECT_EQ(LookupsCompleted, 2); + EXPECT_EQ(LookupsCompleted, 2U); } TEST_F(CoreAPIsStandardTest, BlockedGeneratorAutoSuspensionTest) { -- GitLab From 8466480bdad9d1ef858329ec51cd910c419036a0 Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Thu, 9 May 2024 14:42:52 -0700 Subject: [PATCH 206/328] [ProfData] Remove unused variable in unittest Removed unused `VTables` in unittests/ProfileData/InstrProfTest.cpp. NFC. --- llvm/unittests/ProfileData/InstrProfTest.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/unittests/ProfileData/InstrProfTest.cpp b/llvm/unittests/ProfileData/InstrProfTest.cpp index 8f2c5aee1819..924d848176e7 100644 --- a/llvm/unittests/ProfileData/InstrProfTest.cpp +++ b/llvm/unittests/ProfileData/InstrProfTest.cpp @@ -1782,7 +1782,6 @@ TEST(SymtabTest, instr_prof_symtab_module_test) { EXPECT_THAT(PGOFuncName.str(), EndsWith(Funcs[I].str())); } - StringRef VTables[] = {"ExternalGV", "LocalGV"}; for (auto [VTableName, PGOName] : {std::pair{"ExternalGV", "ExternalGV"}, {"LocalGV", "MyModule.cpp;LocalGV"}}) { GlobalVariable *GV = -- GitLab From 04ce10357b485e5e03480b1ca2e91e75c50b1fef Mon Sep 17 00:00:00 2001 From: MaheshRavishankar <1663364+MaheshRavishankar@users.noreply.github.com> Date: Thu, 9 May 2024 14:54:38 -0700 Subject: [PATCH 207/328] [mlir][SCF] Avoid generating unnecessary div/rem operations during coalescing (#91562) When coalescing is some of the loops are unit-trip we can avoid generating div/rem instructions during delinearization. Ideally we could use some thing like `affine.delinearize` to handle this but tthat causes dependence issues. --- mlir/lib/Dialect/SCF/Utils/Utils.cpp | 57 +++++++++++--- .../Dialect/SCF/transform-op-coalesce.mlir | 77 +++++++++++++++++++ 2 files changed, 124 insertions(+), 10 deletions(-) diff --git a/mlir/lib/Dialect/SCF/Utils/Utils.cpp b/mlir/lib/Dialect/SCF/Utils/Utils.cpp index 9279081cfd45..6658cca03eba 100644 --- a/mlir/lib/Dialect/SCF/Utils/Utils.cpp +++ b/mlir/lib/Dialect/SCF/Utils/Utils.cpp @@ -544,11 +544,24 @@ static void denormalizeInductionVariable(RewriterBase &rewriter, Location loc, static Value getProductOfIntsOrIndexes(RewriterBase &rewriter, Location loc, ArrayRef values) { assert(!values.empty() && "unexpected empty list"); - Value productOf = values.front(); - for (auto v : values.drop_front()) { - productOf = rewriter.create(loc, productOf, v); + std::optional productOf; + for (auto v : values) { + auto vOne = getConstantIntValue(v); + if (vOne && vOne.value() == 1) + continue; + if (productOf) + productOf = + rewriter.create(loc, productOf.value(), v).getResult(); + else + productOf = v; } - return productOf; + if (!productOf) { + productOf = rewriter + .create( + loc, rewriter.getOneAttr(values.front().getType())) + .getResult(); + } + return productOf.value(); } /// For each original loop, the value of the @@ -562,19 +575,43 @@ static Value getProductOfIntsOrIndexes(RewriterBase &rewriter, Location loc, static std::pair, SmallPtrSet> delinearizeInductionVariable(RewriterBase &rewriter, Location loc, Value linearizedIv, ArrayRef ubs) { - Value previous = linearizedIv; SmallVector delinearizedIvs(ubs.size()); SmallPtrSet preservedUsers; - for (unsigned i = 0, e = ubs.size(); i < e; ++i) { - unsigned idx = ubs.size() - i - 1; - if (i != 0) { + + llvm::BitVector isUbOne(ubs.size()); + for (auto [index, ub] : llvm::enumerate(ubs)) { + auto ubCst = getConstantIntValue(ub); + if (ubCst && ubCst.value() == 1) + isUbOne.set(index); + } + + // Prune the lead ubs that are all ones. + unsigned numLeadingOneUbs = 0; + for (auto [index, ub] : llvm::enumerate(ubs)) { + if (!isUbOne.test(index)) { + break; + } + delinearizedIvs[index] = rewriter.create( + loc, rewriter.getZeroAttr(ub.getType())); + numLeadingOneUbs++; + } + + Value previous = linearizedIv; + for (unsigned i = numLeadingOneUbs, e = ubs.size(); i < e; ++i) { + unsigned idx = ubs.size() - (i - numLeadingOneUbs) - 1; + if (i != numLeadingOneUbs && !isUbOne.test(idx + 1)) { previous = rewriter.create(loc, previous, ubs[idx + 1]); preservedUsers.insert(previous.getDefiningOp()); } Value iv = previous; if (i != e - 1) { - iv = rewriter.create(loc, previous, ubs[idx]); - preservedUsers.insert(iv.getDefiningOp()); + if (!isUbOne.test(idx)) { + iv = rewriter.create(loc, previous, ubs[idx]); + preservedUsers.insert(iv.getDefiningOp()); + } else { + iv = rewriter.create( + loc, rewriter.getZeroAttr(ubs[idx].getType())); + } } delinearizedIvs[idx] = iv; } diff --git a/mlir/test/Dialect/SCF/transform-op-coalesce.mlir b/mlir/test/Dialect/SCF/transform-op-coalesce.mlir index 4dc3e4ea0ef4..6fcd727621ba 100644 --- a/mlir/test/Dialect/SCF/transform-op-coalesce.mlir +++ b/mlir/test/Dialect/SCF/transform-op-coalesce.mlir @@ -299,3 +299,80 @@ module attributes {transform.with_named_sequence} { // CHECK-NOT: scf.for // CHECK: transform.named_sequence +// ----- + +// Check avoiding generating unnecessary operations while collapsing trip-1 loops. +func.func @trip_one_loops(%arg0 : tensor, %arg1 : index, %arg2 : index) -> tensor { + %c0 = arith.constant 0 : index + %c1 = arith.constant 1 : index + %0 = scf.for %iv0 = %c0 to %c1 step %c1 iter_args(%iter0 = %arg0) -> tensor { + %1 = scf.for %iv1 = %c0 to %c1 step %c1 iter_args(%iter1 = %iter0) -> tensor { + %2 = scf.for %iv2 = %c0 to %arg1 step %c1 iter_args(%iter2 = %iter1) -> tensor { + %3 = scf.for %iv3 = %c0 to %c1 step %c1 iter_args(%iter3 = %iter2) -> tensor { + %4 = scf.for %iv4 = %c0 to %arg2 step %c1 iter_args(%iter4 = %iter3) -> tensor { + %5 = "some_use"(%iter4, %iv0, %iv1, %iv2, %iv3, %iv4) + : (tensor, index, index, index, index, index) -> (tensor) + scf.yield %5 : tensor + } + scf.yield %4 : tensor + } + scf.yield %3 : tensor + } + scf.yield %2 : tensor + } + scf.yield %1 : tensor + } {coalesce} + return %0 : tensor +} +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["scf.for"]} attributes {coalesce} in %arg1 : (!transform.any_op) -> !transform.any_op + %1 = transform.cast %0 : !transform.any_op to !transform.op<"scf.for"> + %2 = transform.loop.coalesce %1 : (!transform.op<"scf.for">) -> (!transform.op<"scf.for">) + transform.yield + } +} +// CHECK-LABEL: func @trip_one_loops +// CHECK-SAME: , %[[ARG1:.+]]: index, +// CHECK-SAME: %[[ARG2:.+]]: index) +// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index +// CHECK-DAG: %[[C1:.+]] = arith.constant 1 : index +// CHECK: %[[UB:.+]] = arith.muli %[[ARG1]], %[[ARG2]] +// CHECK: scf.for %[[IV:.+]] = %[[C0]] to %[[UB]] step %[[C1]] +// CHECK: %[[IV1:.+]] = arith.remsi %[[IV]], %[[ARG2]] +// CHECK: %[[IV2:.+]] = arith.divsi %[[IV]], %[[ARG2]] +// CHECK: "some_use"(%{{[a-zA-Z0-9]+}}, %[[C0]], %[[C0]], %[[IV2]], %[[C0]], %[[IV1]]) + +// ----- + +// Check generating no instructions when all except one loops is non unit-trip. +func.func @all_outer_trip_one(%arg0 : tensor, %arg1 : index) -> tensor { + %c0 = arith.constant 0 : index + %c1 = arith.constant 1 : index + %0 = scf.for %iv0 = %c0 to %c1 step %c1 iter_args(%iter0 = %arg0) -> tensor { + %1 = scf.for %iv1 = %c0 to %c1 step %c1 iter_args(%iter1 = %iter0) -> tensor { + %2 = scf.for %iv2 = %c0 to %arg1 step %c1 iter_args(%iter2 = %iter1) -> tensor { + %3 = "some_use"(%iter2, %iv0, %iv1, %iv2) + : (tensor, index, index, index) -> (tensor) + scf.yield %3 : tensor + } + scf.yield %2 : tensor + } + scf.yield %1 : tensor + } {coalesce} + return %0 : tensor +} +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["scf.for"]} attributes {coalesce} in %arg1 : (!transform.any_op) -> !transform.any_op + %1 = transform.cast %0 : !transform.any_op to !transform.op<"scf.for"> + %2 = transform.loop.coalesce %1 : (!transform.op<"scf.for">) -> (!transform.op<"scf.for">) + transform.yield + } +} +// CHECK-LABEL: func @all_outer_trip_one +// CHECK-SAME: , %[[ARG1:.+]]: index) +// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index +// CHECK-DAG: %[[C1:.+]] = arith.constant 1 : index +// CHECK: scf.for %[[IV:.+]] = %[[C0]] to %[[ARG1]] step %[[C1]] +// CHECK: "some_use"(%{{[a-zA-Z0-9]+}}, %[[C0]], %[[C0]], %[[IV]]) -- GitLab From ba66dfb11bcaef5e0dc21358b3712b491d61d020 Mon Sep 17 00:00:00 2001 From: Dmitry Vasilyev Date: Fri, 10 May 2024 01:56:14 +0400 Subject: [PATCH 208/328] [lldb] Fixed SyntaxWarning: invalid escape sequence \[ \d \s (#91146) Reproduced with Python 3.12.3 --- .../lldbsuite/test/tools/lldb-server/gdbremote_testcase.py | 4 ++-- .../lldbsuite/test/tools/lldb-server/lldbgdbserverutils.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py index 75522158b322..8c8e4abed0b4 100644 --- a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py +++ b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py @@ -130,9 +130,9 @@ class GdbRemoteTestCaseBase(Base, metaclass=GdbRemoteTestCaseFactory): self.stub_sends_two_stop_notifications_on_kill = False if configuration.lldb_platform_url: if configuration.lldb_platform_url.startswith("unix-"): - url_pattern = "(.+)://\[?(.+?)\]?/.*" + url_pattern = r"(.+)://\[?(.+?)\]?/.*" else: - url_pattern = "(.+)://(.+):\d+" + url_pattern = r"(.+)://(.+):\d+" scheme, host = re.match( url_pattern, configuration.lldb_platform_url ).groups() diff --git a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/lldbgdbserverutils.py b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/lldbgdbserverutils.py index 61c5c3a7c865..d1a4119bac78 100644 --- a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/lldbgdbserverutils.py +++ b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/lldbgdbserverutils.py @@ -50,7 +50,7 @@ def get_debugserver_exe(): _LOG_LINE_REGEX = re.compile( - r"^(lldb-server|debugserver)\s+<\s*(\d+)>" + "\s+(read|send)\s+packet:\s+(.+)$" + r"^(lldb-server|debugserver)\s+<\s*(\d+)>\s+(read|send)\s+packet:\s+(.+)$" ) -- GitLab From 5d51db75e46155d0f3d70cf3253d3b075cfcf93a Mon Sep 17 00:00:00 2001 From: asraa Date: Thu, 9 May 2024 16:57:59 -0500 Subject: [PATCH 209/328] [mlir][affine] Use alias analysis to redetermine intervening memory effects in affine-scalrep (#90859) This fixes a TODO to use alias analysis to determine whether a read op intervenes between two write operations to the same memref. Signed-off-by: Asra --- mlir/include/mlir/Dialect/Affine/Utils.h | 7 ++- .../Transforms/AffineScalarReplacement.cpp | 4 +- mlir/lib/Dialect/Affine/Utils/Utils.cpp | 52 ++++++++++--------- mlir/test/Dialect/Affine/scalrep.mlir | 18 +++++++ 4 files changed, 54 insertions(+), 27 deletions(-) diff --git a/mlir/include/mlir/Dialect/Affine/Utils.h b/mlir/include/mlir/Dialect/Affine/Utils.h index 67c7a964feef..7f25db029781 100644 --- a/mlir/include/mlir/Dialect/Affine/Utils.h +++ b/mlir/include/mlir/Dialect/Affine/Utils.h @@ -13,6 +13,7 @@ #ifndef MLIR_DIALECT_AFFINE_UTILS_H #define MLIR_DIALECT_AFFINE_UTILS_H +#include "mlir/Analysis/AliasAnalysis.h" #include "mlir/Dialect/Affine/Analysis/AffineAnalysis.h" #include "mlir/Dialect/Affine/IR/AffineOps.h" #include "mlir/IR/OpDefinition.h" @@ -106,7 +107,8 @@ struct VectorizationStrategy { /// loads and eliminate invariant affine loads; consequently, eliminate dead /// allocs. void affineScalarReplace(func::FuncOp f, DominanceInfo &domInfo, - PostDominanceInfo &postDomInfo); + PostDominanceInfo &postDomInfo, + AliasAnalysis &analysis); /// Vectorizes affine loops in 'loops' using the n-D vectorization factors in /// 'vectorSizes'. By default, each vectorization factor is applied @@ -325,7 +327,8 @@ OpFoldResult linearizeIndex(ArrayRef multiIndex, /// will check if there is no write to the memory between `start` and `memOp` /// that would change the read within `memOp`. template -bool hasNoInterveningEffect(Operation *start, T memOp); +bool hasNoInterveningEffect(Operation *start, T memOp, + llvm::function_ref mayAlias); struct AffineValueExpr { explicit AffineValueExpr(AffineExpr e) : e(e) {} diff --git a/mlir/lib/Dialect/Affine/Transforms/AffineScalarReplacement.cpp b/mlir/lib/Dialect/Affine/Transforms/AffineScalarReplacement.cpp index ed94fb690af2..707bba2f1e6f 100644 --- a/mlir/lib/Dialect/Affine/Transforms/AffineScalarReplacement.cpp +++ b/mlir/lib/Dialect/Affine/Transforms/AffineScalarReplacement.cpp @@ -13,6 +13,7 @@ #include "mlir/Dialect/Affine/Passes.h" +#include "mlir/Analysis/AliasAnalysis.h" #include "mlir/Dialect/Affine/Utils.h" #include "mlir/Dialect/Func/IR/FuncOps.h" #include "mlir/IR/Dominance.h" @@ -47,5 +48,6 @@ mlir::affine::createAffineScalarReplacementPass() { void AffineScalarReplacement::runOnOperation() { affineScalarReplace(getOperation(), getAnalysis(), - getAnalysis()); + getAnalysis(), + getAnalysis()); } diff --git a/mlir/lib/Dialect/Affine/Utils/Utils.cpp b/mlir/lib/Dialect/Affine/Utils/Utils.cpp index 8b8ed2578ca5..f46381403bc5 100644 --- a/mlir/lib/Dialect/Affine/Utils/Utils.cpp +++ b/mlir/lib/Dialect/Affine/Utils/Utils.cpp @@ -678,12 +678,9 @@ static bool mayHaveEffect(Operation *srcMemOp, Operation *destMemOp, } template -bool mlir::affine::hasNoInterveningEffect(Operation *start, T memOp) { - auto isLocallyAllocated = [](Value memref) { - auto *defOp = memref.getDefiningOp(); - return defOp && hasSingleEffect(defOp, memref); - }; - +bool mlir::affine::hasNoInterveningEffect( + Operation *start, T memOp, + llvm::function_ref mayAlias) { // A boolean representing whether an intervening operation could have impacted // memOp. bool hasSideEffect = false; @@ -704,11 +701,8 @@ bool mlir::affine::hasNoInterveningEffect(Operation *start, T memOp) { // If op causes EffectType on a potentially aliasing location for // memOp, mark as having the effect. if (isa(effect.getEffect())) { - // TODO: This should be replaced with a check for no aliasing. - // Aliasing information should be passed to this method. if (effect.getValue() && effect.getValue() != memref && - isLocallyAllocated(memref) && - isLocallyAllocated(effect.getValue())) + !mayAlias(effect.getValue(), memref)) continue; opMayHaveEffect = true; break; @@ -832,10 +826,10 @@ bool mlir::affine::hasNoInterveningEffect(Operation *start, T memOp) { /// other operations will overwrite the memory loaded between the given load /// and store. If such a value exists, the replaced `loadOp` will be added to /// `loadOpsToErase` and its memref will be added to `memrefsToErase`. -static void forwardStoreToLoad(AffineReadOpInterface loadOp, - SmallVectorImpl &loadOpsToErase, - SmallPtrSetImpl &memrefsToErase, - DominanceInfo &domInfo) { +static void forwardStoreToLoad( + AffineReadOpInterface loadOp, SmallVectorImpl &loadOpsToErase, + SmallPtrSetImpl &memrefsToErase, DominanceInfo &domInfo, + llvm::function_ref mayAlias) { // The store op candidate for forwarding that satisfies all conditions // to replace the load, if any. @@ -872,7 +866,8 @@ static void forwardStoreToLoad(AffineReadOpInterface loadOp, // 4. Ensure there is no intermediate operation which could replace the // value in memory. - if (!affine::hasNoInterveningEffect(storeOp, loadOp)) + if (!affine::hasNoInterveningEffect(storeOp, loadOp, + mayAlias)) continue; // We now have a candidate for forwarding. @@ -901,7 +896,8 @@ static void forwardStoreToLoad(AffineReadOpInterface loadOp, template bool mlir::affine::hasNoInterveningEffect( - mlir::Operation *, affine::AffineReadOpInterface); + mlir::Operation *, affine::AffineReadOpInterface, + llvm::function_ref); // This attempts to find stores which have no impact on the final result. // A writing op writeA will be eliminated if there exists an op writeB if @@ -910,7 +906,8 @@ mlir::affine::hasNoInterveningEffect &opsToErase, - PostDominanceInfo &postDominanceInfo) { + PostDominanceInfo &postDominanceInfo, + llvm::function_ref mayAlias) { for (Operation *user : writeA.getMemRef().getUsers()) { // Only consider writing operations. @@ -939,7 +936,8 @@ static void findUnusedStore(AffineWriteOpInterface writeA, // There cannot be an operation which reads from memory between // the two writes. - if (!affine::hasNoInterveningEffect(writeA, writeB)) + if (!affine::hasNoInterveningEffect(writeA, writeB, + mayAlias)) continue; opsToErase.push_back(writeA); @@ -955,7 +953,8 @@ static void findUnusedStore(AffineWriteOpInterface writeA, // 3) There is no write between loadA and loadB. static void loadCSE(AffineReadOpInterface loadA, SmallVectorImpl &loadOpsToErase, - DominanceInfo &domInfo) { + DominanceInfo &domInfo, + llvm::function_ref mayAlias) { SmallVector loadCandidates; for (auto *user : loadA.getMemRef().getUsers()) { auto loadB = dyn_cast(user); @@ -976,7 +975,7 @@ static void loadCSE(AffineReadOpInterface loadA, // 3. There should not be a write between loadA and loadB. if (!affine::hasNoInterveningEffect( - loadB.getOperation(), loadA)) + loadB.getOperation(), loadA, mayAlias)) continue; // Check if two values have the same shape. This is needed for affine vector @@ -1034,16 +1033,21 @@ static void loadCSE(AffineReadOpInterface loadA, // than dealloc) remain. // void mlir::affine::affineScalarReplace(func::FuncOp f, DominanceInfo &domInfo, - PostDominanceInfo &postDomInfo) { + PostDominanceInfo &postDomInfo, + AliasAnalysis &aliasAnalysis) { // Load op's whose results were replaced by those forwarded from stores. SmallVector opsToErase; // A list of memref's that are potentially dead / could be eliminated. SmallPtrSet memrefsToErase; + auto mayAlias = [&](Value val1, Value val2) -> bool { + return !aliasAnalysis.alias(val1, val2).isNo(); + }; + // Walk all load's and perform store to load forwarding. f.walk([&](AffineReadOpInterface loadOp) { - forwardStoreToLoad(loadOp, opsToErase, memrefsToErase, domInfo); + forwardStoreToLoad(loadOp, opsToErase, memrefsToErase, domInfo, mayAlias); }); for (auto *op : opsToErase) op->erase(); @@ -1051,7 +1055,7 @@ void mlir::affine::affineScalarReplace(func::FuncOp f, DominanceInfo &domInfo, // Walk all store's and perform unused store elimination f.walk([&](AffineWriteOpInterface storeOp) { - findUnusedStore(storeOp, opsToErase, postDomInfo); + findUnusedStore(storeOp, opsToErase, postDomInfo, mayAlias); }); for (auto *op : opsToErase) op->erase(); @@ -1084,7 +1088,7 @@ void mlir::affine::affineScalarReplace(func::FuncOp f, DominanceInfo &domInfo, // stores. Otherwise, some stores are wrongly seen as having an intervening // effect. f.walk([&](AffineReadOpInterface loadOp) { - loadCSE(loadOp, opsToErase, domInfo); + loadCSE(loadOp, opsToErase, domInfo, mayAlias); }); for (auto *op : opsToErase) op->erase(); diff --git a/mlir/test/Dialect/Affine/scalrep.mlir b/mlir/test/Dialect/Affine/scalrep.mlir index 22d394bfcf09..4a99dee50a28 100644 --- a/mlir/test/Dialect/Affine/scalrep.mlir +++ b/mlir/test/Dialect/Affine/scalrep.mlir @@ -682,6 +682,24 @@ func.func @redundant_store_elim(%out : memref<512xf32>) { // CHECK-NEXT: affine.store // CHECK-NEXT: } +// CHECK-LABEL: func @redundant_store_elim_nonintervening + +func.func @redundant_store_elim_nonintervening(%in : memref<512xf32>) { + %cf1 = arith.constant 1.0 : f32 + %out = memref.alloc() : memref<512xf32> + affine.for %i = 0 to 16 { + affine.store %cf1, %out[32*%i] : memref<512xf32> + %0 = affine.load %in[32*%i] : memref<512xf32> + affine.store %0, %out[32*%i] : memref<512xf32> + } + return +} + +// CHECK: affine.for +// CHECK-NEXT: affine.load +// CHECK-NEXT: affine.store +// CHECK-NEXT: } + // CHECK-LABEL: func @redundant_store_elim_fail func.func @redundant_store_elim_fail(%out : memref<512xf32>) { -- GitLab From a99cb96dfa97c04c3313cb3770b876fee20eb131 Mon Sep 17 00:00:00 2001 From: Ryosuke Niwa Date: Thu, 9 May 2024 15:34:27 -0700 Subject: [PATCH 210/328] [alpha.webkit.UncountedCallArgsChecker] Allow trivial operator++ (#91102) This PR adds the support for trivial operator++ implementations. T& operator++() and T operator++(int) are trivial if the callee is trivial. Also allow incrementing and decrementing of a POD member variable. Also treat any __builtin_ functions as trivial. --- .../Checkers/WebKit/PtrTypesSemantics.cpp | 29 ++++++------- .../Checkers/WebKit/uncounted-obj-arg.cpp | 43 +++++++++++++++++++ 2 files changed, 56 insertions(+), 16 deletions(-) diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp index 6901dbb415bf..3abfa4cbb295 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp @@ -309,21 +309,8 @@ public: bool VisitDefaultStmt(const DefaultStmt *DS) { return VisitChildren(DS); } bool VisitUnaryOperator(const UnaryOperator *UO) { - // Operator '*' and '!' are allowed as long as the operand is trivial. - auto op = UO->getOpcode(); - if (op == UO_Deref || op == UO_AddrOf || op == UO_LNot || op == UO_Not) - return Visit(UO->getSubExpr()); - - if (UO->isIncrementOp() || UO->isDecrementOp()) { - // Allow increment or decrement of a POD type. - if (auto *RefExpr = dyn_cast(UO->getSubExpr())) { - if (auto *Decl = dyn_cast(RefExpr->getDecl())) - return Decl->isLocalVarDeclOrParm() && - Decl->getType().isPODType(Decl->getASTContext()); - } - } - // Other operators are non-trivial. - return false; + // Unary operators are trivial if its operand is trivial except co_await. + return UO->getOpcode() != UO_Coawait && Visit(UO->getSubExpr()); } bool VisitBinaryOperator(const BinaryOperator *BO) { @@ -364,7 +351,7 @@ public: if (Name == "WTFCrashWithInfo" || Name == "WTFBreakpointTrap" || Name == "WTFReportAssertionFailure" || - Name == "compilerFenceForCrash" || Name == "__builtin_unreachable") + Name == "compilerFenceForCrash" || Name.find("__builtin") == 0) return true; return TrivialFunctionAnalysis::isTrivialImpl(Callee, Cache); @@ -405,6 +392,16 @@ public: return TrivialFunctionAnalysis::isTrivialImpl(Callee, Cache); } + bool VisitCXXOperatorCallExpr(const CXXOperatorCallExpr *OCE) { + if (!checkArguments(OCE)) + return false; + auto *Callee = OCE->getCalleeDecl(); + if (!Callee) + return false; + // Recursively descend into the callee to confirm that it's trivial as well. + return TrivialFunctionAnalysis::isTrivialImpl(Callee, Cache); + } + bool VisitCXXDefaultArgExpr(const CXXDefaultArgExpr *E) { if (auto *Expr = E->getExpr()) { if (!Visit(Expr)) diff --git a/clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.cpp b/clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.cpp index e75d42b9f149..6ca7677511d7 100644 --- a/clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.cpp +++ b/clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.cpp @@ -138,11 +138,29 @@ public: Number(int v) : v(v) { } Number(double); Number operator+(const Number&); + Number& operator++() { ++v; return *this; } + Number operator++(int) { Number returnValue(v); ++v; return returnValue; } const int& value() const { return v; } + void someMethod(); + private: int v; }; +class ComplexNumber { +public: + ComplexNumber() : real(0), complex(0) { } + ComplexNumber(const ComplexNumber&); + ComplexNumber& operator++() { real.someMethod(); return *this; } + ComplexNumber operator++(int); + ComplexNumber& operator<<(int); + ComplexNumber& operator+(); + +private: + Number real; + Number complex; +}; + class RefCounted { public: void ref() const; @@ -210,6 +228,12 @@ public: unsigned trivial32() { return sizeof(int); } unsigned trivial33() { return ~0xff; } template unsigned trivial34() { return v; } + void trivial35() { v++; } + void trivial36() { ++(*number); } + void trivial37() { (*number)++; } + void trivial38() { v++; if (__builtin_expect(!!(number), 1)) (*number)++; } + int trivial39() { return -v; } + int trivial40() { return v << 2; } static RefCounted& singleton() { static RefCounted s_RefCounted; @@ -284,9 +308,14 @@ public: int nonTrivial13() { return ~otherFunction(); } int nonTrivial14() { int r = 0xff; r |= otherFunction(); return r; } + void nonTrivial15() { ++complex; } + void nonTrivial16() { complex++; } + ComplexNumber nonTrivial17() { return complex << 2; } + ComplexNumber nonTrivial18() { return +complex; } unsigned v { 0 }; Number* number { nullptr }; + ComplexNumber complex; Enum enumValue { Enum::Value1 }; }; @@ -342,6 +371,12 @@ public: getFieldTrivial().trivial32(); // no-warning getFieldTrivial().trivial33(); // no-warning getFieldTrivial().trivial34<7>(); // no-warning + getFieldTrivial().trivial35(); // no-warning + getFieldTrivial().trivial36(); // no-warning + getFieldTrivial().trivial37(); // no-warning + getFieldTrivial().trivial38(); // no-warning + getFieldTrivial().trivial39(); // no-warning + getFieldTrivial().trivial40(); // no-warning RefCounted::singleton().trivial18(); // no-warning RefCounted::singleton().someFunction(); // no-warning @@ -376,6 +411,14 @@ public: // expected-warning@-1{{Call argument for 'this' parameter is uncounted and unsafe}} getFieldTrivial().nonTrivial14(); // expected-warning@-1{{Call argument for 'this' parameter is uncounted and unsafe}} + getFieldTrivial().nonTrivial15(); + // expected-warning@-1{{Call argument for 'this' parameter is uncounted and unsafe}} + getFieldTrivial().nonTrivial16(); + // expected-warning@-1{{Call argument for 'this' parameter is uncounted and unsafe}} + getFieldTrivial().nonTrivial17(); + // expected-warning@-1{{Call argument for 'this' parameter is uncounted and unsafe}} + getFieldTrivial().nonTrivial18(); + // expected-warning@-1{{Call argument for 'this' parameter is uncounted and unsafe}} } }; -- GitLab From 8a3277acbc7b7af917f570f7d6430dda41c4d9ee Mon Sep 17 00:00:00 2001 From: Brendan Dahl Date: Thu, 9 May 2024 15:38:13 -0700 Subject: [PATCH 211/328] [WebAssembly] Implement prototype f32.store_f16 instruction. (#91545) Adds a builtin and intrinsic for the f32.store_f16 instruction. The instruction stores an f32 value as an f16 memory. Specified at: https://github.com/WebAssembly/half-precision/blob/29a9b9462c9285d4ccc1a5dc39214ddfd1892658/proposals/half-precision/Overview.md Note: the current spec has f32.store_f16 as opcode 0xFD0121, but this is incorrect and will be changed to 0xFC31 soon. --- .../clang/Basic/BuiltinsWebAssembly.def | 1 + clang/lib/CodeGen/CGBuiltin.cpp | 6 +++++ clang/test/CodeGen/builtins-wasm.c | 6 +++++ llvm/include/llvm/IR/IntrinsicsWebAssembly.td | 5 ++++ .../MCTargetDesc/WebAssemblyMCTargetDesc.h | 1 + .../WebAssembly/WebAssemblyISelLowering.cpp | 8 ++++++ .../WebAssembly/WebAssemblyInstrMemory.td | 11 ++++++-- .../CodeGen/WebAssembly/half-precision.ll | 9 +++++++ llvm/test/CodeGen/WebAssembly/offset.ll | 27 +++++++++++++++++++ llvm/test/MC/WebAssembly/simd-encodings.s | 3 +++ 10 files changed, 75 insertions(+), 2 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsWebAssembly.def b/clang/include/clang/Basic/BuiltinsWebAssembly.def index cf54f8f4422f..8645cff1e867 100644 --- a/clang/include/clang/Basic/BuiltinsWebAssembly.def +++ b/clang/include/clang/Basic/BuiltinsWebAssembly.def @@ -192,6 +192,7 @@ TARGET_BUILTIN(__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4, "V4fV8UsV8UsV4f" // Half-Precision (fp16) TARGET_BUILTIN(__builtin_wasm_loadf16_f32, "fh*", "nU", "half-precision") +TARGET_BUILTIN(__builtin_wasm_storef16_f32, "vfh*", "n", "half-precision") // Reference Types builtins // Some builtins are custom type-checked - see 't' as part of the third argument, diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 4b03b8b0e093..f9ee93049b12 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -21310,6 +21310,12 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID, Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_loadf16_f32); return Builder.CreateCall(Callee, {Addr}); } + case WebAssembly::BI__builtin_wasm_storef16_f32: { + Value *Val = EmitScalarExpr(E->getArg(0)); + Value *Addr = EmitScalarExpr(E->getArg(1)); + Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_storef16_f32); + return Builder.CreateCall(Callee, {Val, Addr}); + } case WebAssembly::BI__builtin_wasm_table_get: { assert(E->getArg(0)->getType()->isArrayType()); Value *Table = EmitArrayToPointerDecay(E->getArg(0)).emitRawPointer(*this); diff --git a/clang/test/CodeGen/builtins-wasm.c b/clang/test/CodeGen/builtins-wasm.c index ab1c6cd494ae..bcb15969de1c 100644 --- a/clang/test/CodeGen/builtins-wasm.c +++ b/clang/test/CodeGen/builtins-wasm.c @@ -807,6 +807,12 @@ float load_f16_f32(__fp16 *addr) { // WEBASSEMBLY: call float @llvm.wasm.loadf16.f32(ptr %{{.*}}) } +void store_f16_f32(float val, __fp16 *addr) { + return __builtin_wasm_storef16_f32(val, addr); + // WEBASSEMBLY: tail call void @llvm.wasm.storef16.f32(float %val, ptr %{{.*}}) + // WEBASSEMBLY-NEXT: ret +} + __externref_t externref_null() { return __builtin_wasm_ref_null_extern(); // WEBASSEMBLY: tail call ptr addrspace(10) @llvm.wasm.ref.null.extern() diff --git a/llvm/include/llvm/IR/IntrinsicsWebAssembly.td b/llvm/include/llvm/IR/IntrinsicsWebAssembly.td index f8142a8ca9e9..572d334ac955 100644 --- a/llvm/include/llvm/IR/IntrinsicsWebAssembly.td +++ b/llvm/include/llvm/IR/IntrinsicsWebAssembly.td @@ -332,6 +332,11 @@ def int_wasm_loadf16_f32: [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly], "", [SDNPMemOperand]>; +def int_wasm_storef16_f32: + Intrinsic<[], + [llvm_float_ty, llvm_ptr_ty], + [IntrWriteMem, IntrArgMemOnly], + "", [SDNPMemOperand]>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h index d3b496ae5917..d4e9fb057c44 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h @@ -207,6 +207,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) { WASM_LOAD_STORE(LOAD_LANE_I16x8) WASM_LOAD_STORE(STORE_LANE_I16x8) WASM_LOAD_STORE(LOAD_F16_F32) + WASM_LOAD_STORE(STORE_F16_F32) return 1; WASM_LOAD_STORE(LOAD_I32) WASM_LOAD_STORE(LOAD_F32) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index ed52fe53bc60..527bb4c9fbea 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -914,6 +914,14 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(2); Info.flags = MachineMemOperand::MOLoad; return true; + case Intrinsic::wasm_storef16_f32: + Info.opc = ISD::INTRINSIC_VOID; + Info.memVT = MVT::f16; + Info.ptrVal = I.getArgOperand(1); + Info.offset = 0; + Info.align = Align(2); + Info.flags = MachineMemOperand::MOStore; + return true; default: return false; } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td index e4baf842462a..9d452879bbf8 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td @@ -72,8 +72,9 @@ defm LOAD16_U_I64 : WebAssemblyLoad; defm LOAD32_S_I64 : WebAssemblyLoad; defm LOAD32_U_I64 : WebAssemblyLoad; -// Half Precision -defm LOAD_F16_F32 : WebAssemblyLoad; +// Half-precision load. +defm LOAD_F16_F32 : + WebAssemblyLoad; // Pattern matching @@ -171,12 +172,18 @@ defm STORE8_I64 : WebAssemblyStore; defm STORE16_I64 : WebAssemblyStore; defm STORE32_I64 : WebAssemblyStore; +// Half-precision store. +defm STORE_F16_F32 : + WebAssemblyStore; + defm : StorePat; defm : StorePat; defm : StorePat; defm : StorePat; defm : StorePat; +defm : StorePat; + multiclass MemoryOps { // Current memory size. defm MEMORY_SIZE_A#B : I<(outs rc:$dst), (ins i32imm:$flags), diff --git a/llvm/test/CodeGen/WebAssembly/half-precision.ll b/llvm/test/CodeGen/WebAssembly/half-precision.ll index 582771d3f95f..89e9c42637c1 100644 --- a/llvm/test/CodeGen/WebAssembly/half-precision.ll +++ b/llvm/test/CodeGen/WebAssembly/half-precision.ll @@ -2,6 +2,7 @@ ; RUN: llc < %s --mtriple=wasm64-unknown-unknown -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+half-precision | FileCheck %s declare float @llvm.wasm.loadf32.f16(ptr) +declare void @llvm.wasm.storef16.f32(float, ptr) ; CHECK-LABEL: ldf16_32: ; CHECK: f32.load_f16 $push[[NUM0:[0-9]+]]=, 0($0){{$}} @@ -10,3 +11,11 @@ define float @ldf16_32(ptr %p) { %v = call float @llvm.wasm.loadf16.f32(ptr %p) ret float %v } + +; CHECK-LABEL: stf16_32: +; CHECK: f32.store_f16 0($1), $0 +; CHECK-NEXT: return +define void @stf16_32(float %v, ptr %p) { + tail call void @llvm.wasm.storef16.f32(float %v, ptr %p) + ret void +} diff --git a/llvm/test/CodeGen/WebAssembly/offset.ll b/llvm/test/CodeGen/WebAssembly/offset.ll index b497ddd7273a..65de341780e3 100644 --- a/llvm/test/CodeGen/WebAssembly/offset.ll +++ b/llvm/test/CodeGen/WebAssembly/offset.ll @@ -692,3 +692,30 @@ define float @load_f16_f32_with_folded_gep_offset(ptr %p) { %t = call float @llvm.wasm.loadf16.f32(ptr %s) ret float %t } + +;===---------------------------------------------------------------------------- +; Stores: Half Precision +;===---------------------------------------------------------------------------- + +; Basic store. + +; CHECK-LABEL: store_f16_f32_no_offset: +; CHECK-NEXT: .functype store_f16_f32_no_offset (i32, f32) -> (){{$}} +; CHECK-NEXT: f32.store_f16 0($0), $1{{$}} +; CHECK-NEXT: return{{$}} +define void @store_f16_f32_no_offset(ptr %p, float %v) { + call void @llvm.wasm.storef16.f32(float %v, ptr %p) + ret void +} + +; Storing to a fixed address. + +; CHECK-LABEL: store_f16_f32_to_numeric_address: +; CHECK: i32.const $push1=, 0{{$}} +; CHECK-NEXT: f32.const $push0=, 0x0p0{{$}} +; CHECK-NEXT: f32.store_f16 42($pop1), $pop0{{$}} +define void @store_f16_f32_to_numeric_address() { + %s = inttoptr i32 42 to ptr + call void @llvm.wasm.storef16.f32(float 0.0, ptr %s) + ret void +} diff --git a/llvm/test/MC/WebAssembly/simd-encodings.s b/llvm/test/MC/WebAssembly/simd-encodings.s index e7c3761f381d..57fa71e74b8d 100644 --- a/llvm/test/MC/WebAssembly/simd-encodings.s +++ b/llvm/test/MC/WebAssembly/simd-encodings.s @@ -842,4 +842,7 @@ main: # CHECK: f32.load_f16 48 # encoding: [0xfc,0x30,0x01,0x30] f32.load_f16 48 + # CHECK: f32.store_f16 32 # encoding: [0xfc,0x31,0x01,0x20] + f32.store_f16 32 + end_function -- GitLab From 1e97d114b5b2b522de7e0aa9c950199de0798d53 Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Thu, 9 May 2024 15:55:36 -0700 Subject: [PATCH 212/328] [dsymutil] Add -q/--quiet flag to suppress warnings (#91658) Add a -q/--quiet flag to suppress dsymutil output. For now the flag is limited to dsymutil, though there might be other places in the DWARF linker that could be conditionalized by this flag. The motivation is having a way to silence the "no debug symbols in executable" warning. This is useful when we want to generate a dSYM for a binary not containing debug symbols, but still want a dSYM that can be indexed by spotlight. rdar://127843467 --- llvm/docs/CommandGuide/dsymutil.rst | 4 ++ llvm/test/tools/dsymutil/ARM/empty-map.test | 2 + llvm/test/tools/dsymutil/cmdline.test | 4 ++ llvm/tools/dsymutil/LinkUtils.h | 3 ++ llvm/tools/dsymutil/Options.td | 8 ++++ llvm/tools/dsymutil/dsymutil.cpp | 45 ++++++++++++++------- 6 files changed, 51 insertions(+), 15 deletions(-) diff --git a/llvm/docs/CommandGuide/dsymutil.rst b/llvm/docs/CommandGuide/dsymutil.rst index e3f2f33224b0..6026e2f534ed 100644 --- a/llvm/docs/CommandGuide/dsymutil.rst +++ b/llvm/docs/CommandGuide/dsymutil.rst @@ -115,6 +115,10 @@ OPTIONS Specifies an alternate ``path`` to place the dSYM bundle. The default dSYM bundle path is created by appending ``.dSYM`` to the executable name. +.. option:: -q, --quiet + + Enable quiet mode and limit output. + .. option:: --remarks-drop-without-debug Drop remarks without valid debug locations. Without this flags, all remarks are kept. diff --git a/llvm/test/tools/dsymutil/ARM/empty-map.test b/llvm/test/tools/dsymutil/ARM/empty-map.test index 40ffa8b1cc51..eeca28273a3f 100644 --- a/llvm/test/tools/dsymutil/ARM/empty-map.test +++ b/llvm/test/tools/dsymutil/ARM/empty-map.test @@ -1,4 +1,5 @@ # RUN: dsymutil -f -oso-prepend-path=%p/../Inputs -y %s -o - 2>&1 | FileCheck %s +# RUN: dsymutil -q -f -oso-prepend-path=%p/../Inputs -y %s -o - 2>&1 | FileCheck %s --check-prefix QUIET # RUN: dsymutil --linker parallel -f -oso-prepend-path=%p/../Inputs -y %s -o - 2>&1 | FileCheck %s @@ -7,3 +8,4 @@ triple: 'thumbv7-apple-darwin' ... # CHECK: warning: no debug symbols in executable (-arch armv7) +# QUIET-NOT: no debug symbols in executable diff --git a/llvm/test/tools/dsymutil/cmdline.test b/llvm/test/tools/dsymutil/cmdline.test index 814252b6e230..6c67ac7cd723 100644 --- a/llvm/test/tools/dsymutil/cmdline.test +++ b/llvm/test/tools/dsymutil/cmdline.test @@ -23,6 +23,7 @@ CHECK: -object-prefix-map CHECK: -oso-prepend-path CHECK: -out CHECK: {{-o }} +CHECK: -quiet CHECK: -remarks-drop-without-debug CHECK: -remarks-output-format CHECK: -remarks-prepend-path @@ -46,3 +47,6 @@ NOINPUT: error: no input files specified RUN: dsymutil -bogus -help 2>&1 | FileCheck --check-prefix=BOGUS %s BOGUS: warning: ignoring unknown option: -bogus + +RUN: not dsymutil --quiet --verbose 2>&1 | FileCheck --check-prefix=CONFLICT %s +CONFLICT: error: --quiet and --verbose cannot be specified together diff --git a/llvm/tools/dsymutil/LinkUtils.h b/llvm/tools/dsymutil/LinkUtils.h index 6aa0b847eebd..ad5515a04333 100644 --- a/llvm/tools/dsymutil/LinkUtils.h +++ b/llvm/tools/dsymutil/LinkUtils.h @@ -38,6 +38,9 @@ struct LinkOptions { /// Verbosity bool Verbose = false; + /// Quiet + bool Quiet = false; + /// Statistics bool Statistics = false; diff --git a/llvm/tools/dsymutil/Options.td b/llvm/tools/dsymutil/Options.td index d8cec0cb2c41..b72ae1909a72 100644 --- a/llvm/tools/dsymutil/Options.td +++ b/llvm/tools/dsymutil/Options.td @@ -24,6 +24,14 @@ def verbose: F<"verbose">, HelpText<"Enable verbose mode.">, Group; +def quiet: F<"quiet">, + HelpText<"Enable quiet mode.">, + Group; +def: Flag<["-"], "q">, + Alias, + HelpText<"Alias for --quiet">, + Group; + def keep_func_for_static: F<"keep-function-for-static">, HelpText<"Make a static variable keep the enclosing function even if it would have been omitted otherwise.">, Group; diff --git a/llvm/tools/dsymutil/dsymutil.cpp b/llvm/tools/dsymutil/dsymutil.cpp index bc968b6387b6..728f2ed3e62a 100644 --- a/llvm/tools/dsymutil/dsymutil.cpp +++ b/llvm/tools/dsymutil/dsymutil.cpp @@ -169,6 +169,12 @@ static Expected> getInputs(opt::InputArgList &Args, // Verify that the given combination of options makes sense. static Error verifyOptions(const DsymutilOptions &Options) { + if (Options.LinkOpts.Verbose && Options.LinkOpts.Quiet) { + return make_error( + "--quiet and --verbose cannot be specified together", + errc::invalid_argument); + } + if (Options.InputFiles.empty()) { return make_error("no input files specified", errc::invalid_argument); @@ -311,6 +317,7 @@ static Expected getOptions(opt::InputArgList &Args) { Options.LinkOpts.NoTimestamp = Args.hasArg(OPT_no_swiftmodule_timestamp); Options.LinkOpts.Update = Args.hasArg(OPT_update); Options.LinkOpts.Verbose = Args.hasArg(OPT_verbose); + Options.LinkOpts.Quiet = Args.hasArg(OPT_quiet); Options.LinkOpts.Statistics = Args.hasArg(OPT_statistics); Options.LinkOpts.Fat64 = Args.hasArg(OPT_fat64); Options.LinkOpts.KeepFunctionForStatic = @@ -483,16 +490,20 @@ static bool verifyOutput(StringRef OutputFile, StringRef Arch, DsymutilOptions Options, std::mutex &Mutex) { if (OutputFile == "-") { - std::lock_guard Guard(Mutex); - WithColor::warning() << "verification skipped for " << Arch - << " because writing to stdout.\n"; + if (!Options.LinkOpts.Quiet) { + std::lock_guard Guard(Mutex); + WithColor::warning() << "verification skipped for " << Arch + << " because writing to stdout.\n"; + } return true; } if (Options.LinkOpts.NoOutput) { - std::lock_guard Guard(Mutex); - WithColor::warning() << "verification skipped for " << Arch - << " because --no-output was passed.\n"; + if (!Options.LinkOpts.Quiet) { + std::lock_guard Guard(Mutex); + WithColor::warning() << "verification skipped for " << Arch + << " because --no-output was passed.\n"; + } return true; } @@ -507,10 +518,12 @@ static bool verifyOutput(StringRef OutputFile, StringRef Arch, if (auto *Obj = dyn_cast(&Binary)) { std::unique_ptr DICtx = DWARFContext::create(*Obj); if (DICtx->getMaxVersion() > 5) { - std::lock_guard Guard(Mutex); - WithColor::warning() - << "verification skipped for " << Arch - << " because DWARF standard greater than v5 is not supported yet.\n"; + if (!Options.LinkOpts.Quiet) { + std::lock_guard Guard(Mutex); + WithColor::warning() << "verification skipped for " << Arch + << " because DWARF standard greater than v5 is " + "not supported yet.\n"; + } return true; } @@ -751,11 +764,13 @@ int dsymutil_main(int argc, char **argv, const llvm::ToolContext &) { continue; if (Map->begin() == Map->end()) { - std::lock_guard Guard(ErrorHandlerMutex); - WithColor::warning() - << "no debug symbols in executable (-arch " - << MachOUtils::getArchName(Map->getTriple().getArchName()) - << ")\n"; + if (!Options.LinkOpts.Quiet) { + std::lock_guard Guard(ErrorHandlerMutex); + WithColor::warning() + << "no debug symbols in executable (-arch " + << MachOUtils::getArchName(Map->getTriple().getArchName()) + << ")\n"; + } } // Using a std::shared_ptr rather than std::unique_ptr because move-only -- GitLab From 95f208f97e709139c3ecbce552bcf1e34b9fcf12 Mon Sep 17 00:00:00 2001 From: Anthony Ha Date: Thu, 9 May 2024 15:57:46 -0700 Subject: [PATCH 213/328] [lldb] Unify CalculateMD5 return types (#91029) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a retake of https://github.com/llvm/llvm-project/pull/90921 which got reverted because I forgot to modify the CalculateMD5 unit test I had added in https://github.com/llvm/llvm-project/pull/88812 The prior failing build is here: https://lab.llvm.org/buildbot/#/builders/68/builds/73622 To make sure this error doesn't happen, I ran `ninja ProcessGdbRemoteTests` and then executed the resulting test binary and observed the `CalculateMD5` test passed. # Overview In my previous PR: https://github.com/llvm/llvm-project/pull/88812, @JDevlieghere suggested to match return types of the various calculate md5 functions. This PR achieves that by changing the various calculate md5 functions to return `llvm::ErrorOr`.   The suggestion was to go for `std::optional<>` but I opted for `llvm::ErrorOr<>` because local calculate md5 was already possibly returning `ErrorOr`. To make sure I didn't break the md5 calculation functionality, I ran some tests for the gdb remote client, and things seem to work. # Testing 1. Remote file doesn't exist ![image](https://github.com/llvm/llvm-project/assets/1326275/b26859e2-18c3-4685-be8f-c6b6a5a4bc77) 1. Remote file differs ![image](https://github.com/llvm/llvm-project/assets/1326275/cbdb3c58-555a-401b-9444-c5ff4c04c491) 1. Remote file matches ![image](https://github.com/llvm/llvm-project/assets/1326275/07561572-22d1-4e0a-988f-bc91b5c2ffce) ## Test gaps Unfortunately, I had to modify `lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp` and I can't test the changes there. Hopefully, the existing test suite / code review from whomever is reading this will catch any issues. --- lldb/include/lldb/Target/Platform.h | 4 +-- .../include/lldb/Target/RemoteAwarePlatform.h | 4 +-- .../Platform/MacOSX/PlatformDarwinDevice.cpp | 16 +++++---- .../gdb-server/PlatformRemoteGDBServer.cpp | 8 ++--- .../gdb-server/PlatformRemoteGDBServer.h | 4 +-- .../GDBRemoteCommunicationClient.cpp | 30 ++++++++++------ .../gdb-remote/GDBRemoteCommunicationClient.h | 2 +- lldb/source/Target/Platform.cpp | 36 +++++++++---------- lldb/source/Target/RemoteAwarePlatform.cpp | 8 ++--- .../GDBRemoteCommunicationClientTest.cpp | 13 ++++--- 10 files changed, 66 insertions(+), 59 deletions(-) diff --git a/lldb/include/lldb/Target/Platform.h b/lldb/include/lldb/Target/Platform.h index ad9c9dcbe684..e05c79cb501b 100644 --- a/lldb/include/lldb/Target/Platform.h +++ b/lldb/include/lldb/Target/Platform.h @@ -649,8 +649,8 @@ public: virtual std::string GetPlatformSpecificConnectionInformation() { return ""; } - virtual bool CalculateMD5(const FileSpec &file_spec, uint64_t &low, - uint64_t &high); + virtual llvm::ErrorOr + CalculateMD5(const FileSpec &file_spec); virtual uint32_t GetResumeCountForLaunchInfo(ProcessLaunchInfo &launch_info) { return 1; diff --git a/lldb/include/lldb/Target/RemoteAwarePlatform.h b/lldb/include/lldb/Target/RemoteAwarePlatform.h index d183815e1c8b..0b9d79f9ff03 100644 --- a/lldb/include/lldb/Target/RemoteAwarePlatform.h +++ b/lldb/include/lldb/Target/RemoteAwarePlatform.h @@ -58,8 +58,8 @@ public: Status SetFilePermissions(const FileSpec &file_spec, uint32_t file_permissions) override; - bool CalculateMD5(const FileSpec &file_spec, uint64_t &low, - uint64_t &high) override; + llvm::ErrorOr + CalculateMD5(const FileSpec &file_spec) override; Status GetFileWithUUID(const FileSpec &platform_file, const UUID *uuid, FileSpec &local_file) override; diff --git a/lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp b/lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp index 52777909a1f8..82156aca8cf1 100644 --- a/lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp +++ b/lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp @@ -405,17 +405,21 @@ lldb_private::Status PlatformDarwinDevice::GetSharedModuleWithLocalCache( // when going over the *slow* GDB remote transfer mechanism we first // check the hashes of the files - and only do the actual transfer if // they differ - uint64_t high_local, high_remote, low_local, low_remote; auto MD5 = llvm::sys::fs::md5_contents(module_cache_spec.GetPath()); if (!MD5) return Status(MD5.getError()); - std::tie(high_local, low_local) = MD5->words(); - m_remote_platform_sp->CalculateMD5(module_spec.GetFileSpec(), - low_remote, high_remote); - if (low_local != low_remote || high_local != high_remote) { + Log *log = GetLog(LLDBLog::Platform); + bool requires_transfer = true; + llvm::ErrorOr remote_md5 = + m_remote_platform_sp->CalculateMD5(module_spec.GetFileSpec()); + if (std::error_code ec = remote_md5.getError()) + LLDB_LOG(log, "couldn't get md5 sum from remote: {0}", + ec.message()); + else + requires_transfer = *MD5 != *remote_md5; + if (requires_transfer) { // bring in the remote file - Log *log = GetLog(LLDBLog::Platform); LLDB_LOGF(log, "[%s] module %s/%s needs to be replaced from remote copy", (IsHost() ? "host" : "remote"), diff --git a/lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp b/lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp index 0dce5add2e37..4684947ede20 100644 --- a/lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp +++ b/lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp @@ -684,12 +684,12 @@ Status PlatformRemoteGDBServer::RunShellCommand( signo_ptr, command_output, timeout); } -bool PlatformRemoteGDBServer::CalculateMD5(const FileSpec &file_spec, - uint64_t &low, uint64_t &high) { +llvm::ErrorOr +PlatformRemoteGDBServer::CalculateMD5(const FileSpec &file_spec) { if (!IsConnected()) - return false; + return std::make_error_code(std::errc::not_connected); - return m_gdb_client_up->CalculateMD5(file_spec, low, high); + return m_gdb_client_up->CalculateMD5(file_spec); } void PlatformRemoteGDBServer::CalculateTrapHandlerSymbolNames() { diff --git a/lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.h b/lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.h index d83fc386f594..0ae1f3cb4199 100644 --- a/lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.h +++ b/lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.h @@ -146,8 +146,8 @@ public: void CalculateTrapHandlerSymbolNames() override; - bool CalculateMD5(const FileSpec &file_spec, uint64_t &low, - uint64_t &high) override; + llvm::ErrorOr + CalculateMD5(const FileSpec &file_spec) override; const lldb::UnixSignalsSP &GetRemoteUnixSignals() override; diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp index 7498a070c260..db9fb37a9a3c 100644 --- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp @@ -3418,8 +3418,8 @@ bool GDBRemoteCommunicationClient::GetFileExists( return true; } -bool GDBRemoteCommunicationClient::CalculateMD5( - const lldb_private::FileSpec &file_spec, uint64_t &low, uint64_t &high) { +llvm::ErrorOr GDBRemoteCommunicationClient::CalculateMD5( + const lldb_private::FileSpec &file_spec) { std::string path(file_spec.GetPath(false)); lldb_private::StreamString stream; stream.PutCString("vFile:MD5:"); @@ -3428,11 +3428,11 @@ bool GDBRemoteCommunicationClient::CalculateMD5( if (SendPacketAndWaitForResponse(stream.GetString(), response) == PacketResult::Success) { if (response.GetChar() != 'F') - return false; + return std::make_error_code(std::errc::illegal_byte_sequence); if (response.GetChar() != ',') - return false; + return std::make_error_code(std::errc::illegal_byte_sequence); if (response.Peek() && *response.Peek() == 'x') - return false; + return std::make_error_code(std::errc::no_such_file_or_directory); // GDBRemoteCommunicationServerCommon::Handle_vFile_MD5 concatenates low and // high hex strings. We can't use response.GetHexMaxU64 because that can't @@ -3455,25 +3455,33 @@ bool GDBRemoteCommunicationClient::CalculateMD5( auto part = response.GetStringRef().substr(response.GetFilePos(), MD5_HALF_LENGTH); if (part.size() != MD5_HALF_LENGTH) - return false; + return std::make_error_code(std::errc::illegal_byte_sequence); response.SetFilePos(response.GetFilePos() + part.size()); + uint64_t low; if (part.getAsInteger(/*radix=*/16, low)) - return false; + return std::make_error_code(std::errc::illegal_byte_sequence); // Get high part part = response.GetStringRef().substr(response.GetFilePos(), MD5_HALF_LENGTH); if (part.size() != MD5_HALF_LENGTH) - return false; + return std::make_error_code(std::errc::illegal_byte_sequence); response.SetFilePos(response.GetFilePos() + part.size()); + uint64_t high; if (part.getAsInteger(/*radix=*/16, high)) - return false; + return std::make_error_code(std::errc::illegal_byte_sequence); - return true; + llvm::MD5::MD5Result result; + llvm::support::endian::write( + result.data(), low); + llvm::support::endian::write( + result.data() + 8, high); + + return result; } - return false; + return std::make_error_code(std::errc::operation_canceled); } bool GDBRemoteCommunicationClient::AvoidGPackets(ProcessGDBRemote *process) { diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h index 4be7eb00f42b..898d176abc34 100644 --- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h +++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h @@ -392,7 +392,7 @@ public: *command_output, // Pass nullptr if you don't want the command output const Timeout &timeout); - bool CalculateMD5(const FileSpec &file_spec, uint64_t &low, uint64_t &high); + llvm::ErrorOr CalculateMD5(const FileSpec &file_spec); lldb::DataBufferSP ReadRegister( lldb::tid_t tid, diff --git a/lldb/source/Target/Platform.cpp b/lldb/source/Target/Platform.cpp index 91483ba008f4..4af4aa68ccd0 100644 --- a/lldb/source/Target/Platform.cpp +++ b/lldb/source/Target/Platform.cpp @@ -1199,22 +1199,22 @@ Status Platform::PutFile(const FileSpec &source, const FileSpec &destination, Status error; bool requires_upload = true; - uint64_t dest_md5_low, dest_md5_high; - bool success = CalculateMD5(destination, dest_md5_low, dest_md5_high); - if (!success) { - LLDB_LOGF(log, "[PutFile] couldn't get md5 sum of destination"); + llvm::ErrorOr remote_md5 = CalculateMD5(destination); + if (std::error_code ec = remote_md5.getError()) { + LLDB_LOG(log, "[PutFile] couldn't get md5 sum of destination: {0}", + ec.message()); } else { - auto local_md5 = llvm::sys::fs::md5_contents(source.GetPath()); - if (!local_md5) { - LLDB_LOGF(log, "[PutFile] couldn't get md5 sum of source"); + llvm::ErrorOr local_md5 = + llvm::sys::fs::md5_contents(source.GetPath()); + if (std::error_code ec = local_md5.getError()) { + LLDB_LOG(log, "[PutFile] couldn't get md5 sum of source: {0}", + ec.message()); } else { - const auto [local_md5_high, local_md5_low] = local_md5->words(); LLDB_LOGF(log, "[PutFile] destination md5: %016" PRIx64 "%016" PRIx64, - dest_md5_high, dest_md5_low); + remote_md5->high(), remote_md5->low()); LLDB_LOGF(log, "[PutFile] local md5: %016" PRIx64 "%016" PRIx64, - local_md5_high, local_md5_low); - requires_upload = - local_md5_high != dest_md5_high || local_md5_low != dest_md5_low; + local_md5->high(), local_md5->low()); + requires_upload = *remote_md5 != *local_md5; } } @@ -1339,15 +1339,11 @@ lldb_private::Status Platform::RunShellCommand( return Status("unable to run a remote command without a platform"); } -bool Platform::CalculateMD5(const FileSpec &file_spec, uint64_t &low, - uint64_t &high) { +llvm::ErrorOr +Platform::CalculateMD5(const FileSpec &file_spec) { if (!IsHost()) - return false; - auto Result = llvm::sys::fs::md5_contents(file_spec.GetPath()); - if (!Result) - return false; - std::tie(high, low) = Result->words(); - return true; + return std::make_error_code(std::errc::not_supported); + return llvm::sys::fs::md5_contents(file_spec.GetPath()); } void Platform::SetLocalCacheDirectory(const char *local) { diff --git a/lldb/source/Target/RemoteAwarePlatform.cpp b/lldb/source/Target/RemoteAwarePlatform.cpp index 0bd6c9251c85..9a41a423cadd 100644 --- a/lldb/source/Target/RemoteAwarePlatform.cpp +++ b/lldb/source/Target/RemoteAwarePlatform.cpp @@ -266,11 +266,11 @@ Status RemoteAwarePlatform::Unlink(const FileSpec &file_spec) { return Platform::Unlink(file_spec); } -bool RemoteAwarePlatform::CalculateMD5(const FileSpec &file_spec, uint64_t &low, - uint64_t &high) { +llvm::ErrorOr +RemoteAwarePlatform::CalculateMD5(const FileSpec &file_spec) { if (m_remote_platform_sp) - return m_remote_platform_sp->CalculateMD5(file_spec, low, high); - return Platform::CalculateMD5(file_spec, low, high); + return m_remote_platform_sp->CalculateMD5(file_spec); + return Platform::CalculateMD5(file_spec); } FileSpec RemoteAwarePlatform::GetRemoteWorkingDirectory() { diff --git a/lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp b/lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp index 6b11ec43a65d..24111396b0ac 100644 --- a/lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp +++ b/lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp @@ -595,10 +595,8 @@ TEST_F(GDBRemoteCommunicationClientTest, WriteMemoryTags) { TEST_F(GDBRemoteCommunicationClientTest, CalculateMD5) { FileSpec file_spec("/foo/bar", FileSpec::Style::posix); - uint64_t low, high; - std::future async_result = std::async(std::launch::async, [&] { - return client.CalculateMD5(file_spec, low, high); - }); + std::future> async_result = std::async( + std::launch::async, [&] { return client.CalculateMD5(file_spec); }); lldb_private::StreamString stream; stream.PutCString("vFile:MD5:"); @@ -607,11 +605,12 @@ TEST_F(GDBRemoteCommunicationClientTest, CalculateMD5) { "F," "deadbeef01020304" "05060708deadbeef"); - ASSERT_TRUE(async_result.get()); + auto result = async_result.get(); // Server and client puts/parses low, and then high const uint64_t expected_low = 0xdeadbeef01020304; const uint64_t expected_high = 0x05060708deadbeef; - EXPECT_EQ(expected_low, low); - EXPECT_EQ(expected_high, high); + ASSERT_TRUE(result); + EXPECT_EQ(expected_low, result->low()); + EXPECT_EQ(expected_high, result->high()); } -- GitLab From f893dccbba372792e7e7095d741f98a234654875 Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Thu, 9 May 2024 16:50:01 -0700 Subject: [PATCH 214/328] Replace uses of ConstantExpr::getCompare. (#91558) Use ICmpInst::compare() where possible, ConstantFoldCompareInstOperands in other places. This only changes places where the either the fold is guaranteed to succeed, or the code doesn't use the resulting compare if we fail to fold. --- .../llvm/Transforms/Scalar/JumpThreading.h | 2 +- llvm/lib/Analysis/BranchProbabilityInfo.cpp | 4 ++-- llvm/lib/Analysis/ConstantFolding.cpp | 8 ++++---- llvm/lib/Analysis/InlineCost.cpp | 12 +++++------- llvm/lib/Analysis/ScalarEvolution.cpp | 4 +--- llvm/lib/IR/Constants.cpp | 4 ++-- .../AMDGPU/AMDGPUInstCombineIntrinsic.cpp | 5 +++-- .../lib/Target/X86/X86InstCombineIntrinsic.cpp | 18 ++++++++++-------- .../InstCombine/InstCombineAndOrXor.cpp | 4 ++-- .../InstCombine/InstCombineCalls.cpp | 3 ++- .../InstCombine/InstCombineCompares.cpp | 15 ++++++--------- .../InstCombine/InstCombineSelect.cpp | 17 +++++++++-------- .../InstCombine/InstructionCombining.cpp | 9 ++++++--- llvm/lib/Transforms/Scalar/JumpThreading.cpp | 16 ++++++++++------ llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 9 +++++---- .../Transforms/JumpThreading/thread-two-bbs.ll | 15 ++++++++------- 16 files changed, 76 insertions(+), 69 deletions(-) diff --git a/llvm/include/llvm/Transforms/Scalar/JumpThreading.h b/llvm/include/llvm/Transforms/Scalar/JumpThreading.h index f7358ac9b1ee..65d43775bdc1 100644 --- a/llvm/include/llvm/Transforms/Scalar/JumpThreading.h +++ b/llvm/include/llvm/Transforms/Scalar/JumpThreading.h @@ -142,7 +142,7 @@ public: } Constant *evaluateOnPredecessorEdge(BasicBlock *BB, BasicBlock *PredPredBB, - Value *cond); + Value *cond, const DataLayout &DL); bool maybethreadThroughTwoBasicBlocks(BasicBlock *BB, Value *Cond); void threadThroughTwoBasicBlocks(BasicBlock *PredPredBB, BasicBlock *PredBB, BasicBlock *BB, BasicBlock *SuccBB); diff --git a/llvm/lib/Analysis/BranchProbabilityInfo.cpp b/llvm/lib/Analysis/BranchProbabilityInfo.cpp index 36a2df645913..cd3e3a499132 100644 --- a/llvm/lib/Analysis/BranchProbabilityInfo.cpp +++ b/llvm/lib/Analysis/BranchProbabilityInfo.cpp @@ -630,8 +630,8 @@ computeUnlikelySuccessors(const BasicBlock *BB, Loop *L, if (!CmpLHSConst) continue; // Now constant-evaluate the compare - Constant *Result = ConstantExpr::getCompare(CI->getPredicate(), - CmpLHSConst, CmpConst, true); + Constant *Result = ConstantFoldCompareInstOperands( + CI->getPredicate(), CmpLHSConst, CmpConst, DL); // If the result means we don't branch to the block then that block is // unlikely. if (Result && diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp index 749374a3aa48..046a76945380 100644 --- a/llvm/lib/Analysis/ConstantFolding.cpp +++ b/llvm/lib/Analysis/ConstantFolding.cpp @@ -1268,10 +1268,10 @@ Constant *llvm::ConstantFoldCompareInstOperands( Value *Stripped1 = Ops1->stripAndAccumulateInBoundsConstantOffsets(DL, Offset1); if (Stripped0 == Stripped1) - return ConstantExpr::getCompare( - ICmpInst::getSignedPredicate(Predicate), - ConstantInt::get(CE0->getContext(), Offset0), - ConstantInt::get(CE0->getContext(), Offset1)); + return ConstantInt::getBool( + Ops0->getContext(), + ICmpInst::compare(Offset0, Offset1, + ICmpInst::getSignedPredicate(Predicate))); } } else if (isa(Ops1)) { // If RHS is a constant expression, but the left side isn't, swap the diff --git a/llvm/lib/Analysis/InlineCost.cpp b/llvm/lib/Analysis/InlineCost.cpp index c75460f44c1d..a531064e304d 100644 --- a/llvm/lib/Analysis/InlineCost.cpp +++ b/llvm/lib/Analysis/InlineCost.cpp @@ -2046,13 +2046,11 @@ bool CallAnalyzer::visitCmpInst(CmpInst &I) { if (RHSBase && LHSBase == RHSBase) { // We have common bases, fold the icmp to a constant based on the // offsets. - Constant *CLHS = ConstantInt::get(LHS->getContext(), LHSOffset); - Constant *CRHS = ConstantInt::get(RHS->getContext(), RHSOffset); - if (Constant *C = ConstantExpr::getICmp(I.getPredicate(), CLHS, CRHS)) { - SimplifiedValues[&I] = C; - ++NumConstantPtrCmps; - return true; - } + SimplifiedValues[&I] = ConstantInt::getBool( + I.getType(), + ICmpInst::compare(LHSOffset, RHSOffset, I.getPredicate())); + ++NumConstantPtrCmps; + return true; } } diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp index 93f885c5d5ad..7dc5aa084f3c 100644 --- a/llvm/lib/Analysis/ScalarEvolution.cpp +++ b/llvm/lib/Analysis/ScalarEvolution.cpp @@ -10615,9 +10615,7 @@ bool ScalarEvolution::SimplifyICmpOperands(ICmpInst::Predicate &Pred, if (const SCEVConstant *LHSC = dyn_cast(LHS)) { // Check for both operands constant. if (const SCEVConstant *RHSC = dyn_cast(RHS)) { - if (ConstantExpr::getICmp(Pred, - LHSC->getValue(), - RHSC->getValue())->isNullValue()) + if (!ICmpInst::compare(LHSC->getAPInt(), RHSC->getAPInt(), Pred)) return TrivialCase(false); return TrivialCase(true); } diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp index 5268eccf7014..db442c54125a 100644 --- a/llvm/lib/IR/Constants.cpp +++ b/llvm/lib/IR/Constants.cpp @@ -315,8 +315,8 @@ bool Constant::isElementWiseEqual(Value *Y) const { Type *IntTy = VectorType::getInteger(VTy); Constant *C0 = ConstantExpr::getBitCast(const_cast(this), IntTy); Constant *C1 = ConstantExpr::getBitCast(cast(Y), IntTy); - Constant *CmpEq = ConstantExpr::getICmp(ICmpInst::ICMP_EQ, C0, C1); - return isa(CmpEq) || match(CmpEq, m_One()); + Constant *CmpEq = ConstantFoldCompareInstruction(ICmpInst::ICMP_EQ, C0, C1); + return CmpEq && (isa(CmpEq) || match(CmpEq, m_One())); } static bool diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp index 5b7fa13f2e83..160a17584ca3 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp @@ -854,8 +854,9 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { if (auto *CSrc0 = dyn_cast(Src0)) { if (auto *CSrc1 = dyn_cast(Src1)) { - Constant *CCmp = ConstantExpr::getCompare(CCVal, CSrc0, CSrc1); - if (CCmp->isNullValue()) { + Constant *CCmp = ConstantFoldCompareInstOperands( + (ICmpInst::Predicate)CCVal, CSrc0, CSrc1, DL); + if (CCmp && CCmp->isNullValue()) { return IC.replaceInstUsesWith( II, IC.Builder.CreateSExt(CCmp, II.getType())); } diff --git a/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp b/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp index e46fc034cc26..8e75e185f0f6 100644 --- a/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp +++ b/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp @@ -26,20 +26,21 @@ using namespace llvm; /// Return a constant boolean vector that has true elements in all positions /// where the input constant data vector has an element with the sign bit set. -static Constant *getNegativeIsTrueBoolVec(Constant *V) { +static Constant *getNegativeIsTrueBoolVec(Constant *V, const DataLayout &DL) { VectorType *IntTy = VectorType::getInteger(cast(V->getType())); V = ConstantExpr::getBitCast(V, IntTy); - V = ConstantExpr::getICmp(CmpInst::ICMP_SGT, Constant::getNullValue(IntTy), - V); + V = ConstantFoldCompareInstOperands(CmpInst::ICMP_SGT, + Constant::getNullValue(IntTy), V, DL); + assert(V && "Vector must be foldable"); return V; } /// Convert the x86 XMM integer vector mask to a vector of bools based on /// each element's most significant bit (the sign bit). -static Value *getBoolVecFromMask(Value *Mask) { +static Value *getBoolVecFromMask(Value *Mask, const DataLayout &DL) { // Fold Constant Mask. if (auto *ConstantMask = dyn_cast(Mask)) - return getNegativeIsTrueBoolVec(ConstantMask); + return getNegativeIsTrueBoolVec(ConstantMask, DL); // Mask was extended from a boolean vector. Value *ExtMask; @@ -65,7 +66,7 @@ static Instruction *simplifyX86MaskedLoad(IntrinsicInst &II, InstCombiner &IC) { // The mask is constant or extended from a bool vector. Convert this x86 // intrinsic to the LLVM intrinsic to allow target-independent optimizations. - if (Value *BoolMask = getBoolVecFromMask(Mask)) { + if (Value *BoolMask = getBoolVecFromMask(Mask, IC.getDataLayout())) { // First, cast the x86 intrinsic scalar pointer to a vector pointer to match // the LLVM intrinsic definition for the pointer argument. unsigned AddrSpace = cast(Ptr->getType())->getAddressSpace(); @@ -102,7 +103,7 @@ static bool simplifyX86MaskedStore(IntrinsicInst &II, InstCombiner &IC) { // The mask is constant or extended from a bool vector. Convert this x86 // intrinsic to the LLVM intrinsic to allow target-independent optimizations. - if (Value *BoolMask = getBoolVecFromMask(Mask)) { + if (Value *BoolMask = getBoolVecFromMask(Mask, IC.getDataLayout())) { unsigned AddrSpace = cast(Ptr->getType())->getAddressSpace(); PointerType *VecPtrTy = PointerType::get(Vec->getType(), AddrSpace); Value *PtrCast = IC.Builder.CreateBitCast(Ptr, VecPtrTy, "castvec"); @@ -2688,7 +2689,8 @@ X86TTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { // Constant Mask - select 1st/2nd argument lane based on top bit of mask. if (auto *ConstantMask = dyn_cast(Mask)) { - Constant *NewSelector = getNegativeIsTrueBoolVec(ConstantMask); + Constant *NewSelector = + getNegativeIsTrueBoolVec(ConstantMask, IC.getDataLayout()); return SelectInst::Create(NewSelector, Op1, Op0, "blendv"); } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index a52c70dbdf3f..8695e9e69df2 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -2504,8 +2504,8 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) { match(C1, m_Power2())) { Constant *Log2C1 = ConstantExpr::getExactLogBase2(C1); Constant *Cmp = - ConstantExpr::getCompare(ICmpInst::ICMP_ULT, Log2C3, C2); - if (Cmp->isZeroValue()) { + ConstantFoldCompareInstOperands(ICmpInst::ICMP_ULT, Log2C3, C2, DL); + if (Cmp && Cmp->isZeroValue()) { // iff C1,C3 is pow2 and Log2(C3) >= C2: // ((C1 >> X) << C2) & C3 -> X == (cttz(C1)+C2-cttz(C3)) ? C3 : 0 Constant *ShlC = ConstantExpr::getAdd(C2, Log2C1); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp index d7433ad3599f..77534e0d3613 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -1982,7 +1982,8 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) { if (ModuloC != ShAmtC) return replaceOperand(*II, 2, ModuloC); - assert(match(ConstantExpr::getICmp(ICmpInst::ICMP_UGT, WidthC, ShAmtC), + assert(match(ConstantFoldCompareInstOperands(ICmpInst::ICMP_UGT, WidthC, + ShAmtC, DL), m_One()) && "Shift amount expected to be modulo bitwidth"); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index 7092fb5e509b..e1a3194a1beb 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -3176,15 +3176,12 @@ Instruction *InstCombinerImpl::foldICmpSelectConstant(ICmpInst &Cmp, C3GreaterThan)) { assert(C1LessThan && C2Equal && C3GreaterThan); - bool TrueWhenLessThan = - ConstantExpr::getCompare(Cmp.getPredicate(), C1LessThan, C) - ->isAllOnesValue(); - bool TrueWhenEqual = - ConstantExpr::getCompare(Cmp.getPredicate(), C2Equal, C) - ->isAllOnesValue(); - bool TrueWhenGreaterThan = - ConstantExpr::getCompare(Cmp.getPredicate(), C3GreaterThan, C) - ->isAllOnesValue(); + bool TrueWhenLessThan = ICmpInst::compare( + C1LessThan->getValue(), C->getValue(), Cmp.getPredicate()); + bool TrueWhenEqual = ICmpInst::compare(C2Equal->getValue(), C->getValue(), + Cmp.getPredicate()); + bool TrueWhenGreaterThan = ICmpInst::compare( + C3GreaterThan->getValue(), C->getValue(), Cmp.getPredicate()); // This generates the new instruction that will replace the original Cmp // Instruction. Instead of enumerating the various combinations when diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index 8818369e7945..ee090e012508 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -1365,7 +1365,8 @@ Instruction *InstCombinerImpl::foldSelectValueEquivalence(SelectInst &Sel, // Also ULT predicate can also be UGT iff C0 != -1 (+invert result) // SLT predicate can also be SGT iff C2 != INT_MAX (+invert res.) static Value *canonicalizeClampLike(SelectInst &Sel0, ICmpInst &Cmp0, - InstCombiner::BuilderTy &Builder) { + InstCombiner::BuilderTy &Builder, + InstCombiner &IC) { Value *X = Sel0.getTrueValue(); Value *Sel1 = Sel0.getFalseValue(); @@ -1493,14 +1494,14 @@ static Value *canonicalizeClampLike(SelectInst &Sel0, ICmpInst &Cmp0, std::swap(ThresholdLowIncl, ThresholdHighExcl); // The fold has a precondition 1: C2 s>= ThresholdLow - auto *Precond1 = ConstantExpr::getICmp(ICmpInst::Predicate::ICMP_SGE, C2, - ThresholdLowIncl); - if (!match(Precond1, m_One())) + auto *Precond1 = ConstantFoldCompareInstOperands( + ICmpInst::Predicate::ICMP_SGE, C2, ThresholdLowIncl, IC.getDataLayout()); + if (!Precond1 || !match(Precond1, m_One())) return nullptr; // The fold has a precondition 2: C2 s<= ThresholdHigh - auto *Precond2 = ConstantExpr::getICmp(ICmpInst::Predicate::ICMP_SLE, C2, - ThresholdHighExcl); - if (!match(Precond2, m_One())) + auto *Precond2 = ConstantFoldCompareInstOperands( + ICmpInst::Predicate::ICMP_SLE, C2, ThresholdHighExcl, IC.getDataLayout()); + if (!Precond2 || !match(Precond2, m_One())) return nullptr; // If we are matching from a truncated input, we need to sext the @@ -1803,7 +1804,7 @@ Instruction *InstCombinerImpl::foldSelectInstWithICmp(SelectInst &SI, if (Value *V = foldSelectInstWithICmpConst(SI, ICI, Builder)) return replaceInstUsesWith(SI, V); - if (Value *V = canonicalizeClampLike(SI, *ICI, Builder)) + if (Value *V = canonicalizeClampLike(SI, *ICI, Builder, *this)) return replaceInstUsesWith(SI, V); if (Instruction *NewSel = diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index b6f8b24f43b8..6c25ff215c37 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -808,9 +808,12 @@ Instruction *InstCombinerImpl::tryFoldInstWithCtpopWithNot(Instruction *I) { Constant *BitWidthC = ConstantInt::get(Ty, Ty->getScalarSizeInBits()); // Need extra check for icmp. Note if this check is true, it generally means // the icmp will simplify to true/false. - if (Opc == Instruction::ICmp && !cast(I)->isEquality() && - !ConstantExpr::getICmp(ICmpInst::ICMP_UGT, C, BitWidthC)->isZeroValue()) - return nullptr; + if (Opc == Instruction::ICmp && !cast(I)->isEquality()) { + Constant *Cmp = + ConstantFoldCompareInstOperands(ICmpInst::ICMP_UGT, C, BitWidthC, DL); + if (!Cmp || !Cmp->isZeroValue()) + return nullptr; + } // Check we can invert `(not x)` for free. bool Consumes = false; diff --git a/llvm/lib/Transforms/Scalar/JumpThreading.cpp b/llvm/lib/Transforms/Scalar/JumpThreading.cpp index 08d82fa66da3..802467b5b183 100644 --- a/llvm/lib/Transforms/Scalar/JumpThreading.cpp +++ b/llvm/lib/Transforms/Scalar/JumpThreading.cpp @@ -868,7 +868,8 @@ bool JumpThreadingPass::computeValueKnownInPredecessorsImpl( for (const auto &LHSVal : LHSVals) { Constant *V = LHSVal.first; - Constant *Folded = ConstantExpr::getCompare(Pred, V, CmpConst); + Constant *Folded = + ConstantFoldCompareInstOperands(Pred, V, CmpConst, DL); if (Constant *KC = getKnownConstant(Folded, WantInteger)) Result.emplace_back(KC, LHSVal.second); } @@ -1509,7 +1510,8 @@ findMostPopularDest(BasicBlock *BB, // BB->getSinglePredecessor() and then on to BB. Constant *JumpThreadingPass::evaluateOnPredecessorEdge(BasicBlock *BB, BasicBlock *PredPredBB, - Value *V) { + Value *V, + const DataLayout &DL) { BasicBlock *PredBB = BB->getSinglePredecessor(); assert(PredBB && "Expected a single predecessor"); @@ -1534,11 +1536,12 @@ Constant *JumpThreadingPass::evaluateOnPredecessorEdge(BasicBlock *BB, if (CmpInst *CondCmp = dyn_cast(V)) { if (CondCmp->getParent() == BB) { Constant *Op0 = - evaluateOnPredecessorEdge(BB, PredPredBB, CondCmp->getOperand(0)); + evaluateOnPredecessorEdge(BB, PredPredBB, CondCmp->getOperand(0), DL); Constant *Op1 = - evaluateOnPredecessorEdge(BB, PredPredBB, CondCmp->getOperand(1)); + evaluateOnPredecessorEdge(BB, PredPredBB, CondCmp->getOperand(1), DL); if (Op0 && Op1) { - return ConstantExpr::getCompare(CondCmp->getPredicate(), Op0, Op1); + return ConstantFoldCompareInstOperands(CondCmp->getPredicate(), Op0, + Op1, DL); } } return nullptr; @@ -2191,12 +2194,13 @@ bool JumpThreadingPass::maybethreadThroughTwoBasicBlocks(BasicBlock *BB, unsigned OneCount = 0; BasicBlock *ZeroPred = nullptr; BasicBlock *OnePred = nullptr; + const DataLayout &DL = BB->getModule()->getDataLayout(); for (BasicBlock *P : predecessors(PredBB)) { // If PredPred ends with IndirectBrInst, we can't handle it. if (isa(P->getTerminator())) continue; if (ConstantInt *CI = dyn_cast_or_null( - evaluateOnPredecessorEdge(BB, P, Cond))) { + evaluateOnPredecessorEdge(BB, P, Cond, DL))) { if (CI->isZero()) { ZeroCount++; ZeroPred = P; diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index 23a896c59bf6..93701b2a7791 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -6580,16 +6580,17 @@ static void reuseTableCompare( Constant *FalseConst = ConstantInt::getFalse(RangeCmp->getType()); // Check if the compare with the default value is constant true or false. - Constant *DefaultConst = ConstantExpr::getICmp(CmpInst->getPredicate(), - DefaultValue, CmpOp1, true); + const DataLayout &DL = PhiBlock->getModule()->getDataLayout(); + Constant *DefaultConst = ConstantFoldCompareInstOperands( + CmpInst->getPredicate(), DefaultValue, CmpOp1, DL); if (DefaultConst != TrueConst && DefaultConst != FalseConst) return; // Check if the compare with the case values is distinct from the default // compare result. for (auto ValuePair : Values) { - Constant *CaseConst = ConstantExpr::getICmp(CmpInst->getPredicate(), - ValuePair.second, CmpOp1, true); + Constant *CaseConst = ConstantFoldCompareInstOperands( + CmpInst->getPredicate(), ValuePair.second, CmpOp1, DL); if (!CaseConst || CaseConst == DefaultConst || (CaseConst != TrueConst && CaseConst != FalseConst)) return; diff --git a/llvm/test/Transforms/JumpThreading/thread-two-bbs.ll b/llvm/test/Transforms/JumpThreading/thread-two-bbs.ll index f7e6b2189dc8..09394a946241 100644 --- a/llvm/test/Transforms/JumpThreading/thread-two-bbs.ll +++ b/llvm/test/Transforms/JumpThreading/thread-two-bbs.ll @@ -130,8 +130,8 @@ exit: } -; Verify that we do *not* thread any edge. We used to evaluate -; constant expressions like: +; Verify that we thread the edge correctly. We used to evaluate constant +; expressions like: ; ; icmp ugt ptr null, inttoptr (i64 4 to ptr) ; @@ -141,16 +141,17 @@ define void @icmp_ult_null_constexpr(ptr %arg1, ptr %arg2) { ; CHECK-LABEL: @icmp_ult_null_constexpr( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq ptr [[ARG1:%.*]], null -; CHECK-NEXT: br i1 [[CMP1]], label [[BB_BAR1:%.*]], label [[BB_END:%.*]] -; CHECK: bb_bar1: -; CHECK-NEXT: call void @bar(i32 1) -; CHECK-NEXT: br label [[BB_END]] +; CHECK-NEXT: br i1 [[CMP1]], label [[BB_END_THREAD:%.*]], label [[BB_END:%.*]] ; CHECK: bb_end: ; CHECK-NEXT: [[CMP2:%.*]] = icmp ne ptr [[ARG2:%.*]], null ; CHECK-NEXT: br i1 [[CMP2]], label [[BB_CONT:%.*]], label [[BB_BAR2:%.*]] +; CHECK: bb_end.thread: +; CHECK-NEXT: call void @bar(i32 1) +; CHECK-NEXT: [[CMP21:%.*]] = icmp ne ptr [[ARG2]], null +; CHECK-NEXT: br i1 [[CMP21]], label [[BB_EXIT:%.*]], label [[BB_BAR2]] ; CHECK: bb_bar2: ; CHECK-NEXT: call void @bar(i32 2) -; CHECK-NEXT: br label [[BB_EXIT:%.*]] +; CHECK-NEXT: br label [[BB_EXIT]] ; CHECK: bb_cont: ; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[ARG1]], inttoptr (i64 4 to ptr) ; CHECK-NEXT: br i1 [[CMP3]], label [[BB_EXIT]], label [[BB_BAR3:%.*]] -- GitLab From f865dbff17ca516d605b053d5556c1498c300a42 Mon Sep 17 00:00:00 2001 From: Jeffrey Byrnes Date: Thu, 9 May 2024 16:57:36 -0700 Subject: [PATCH 215/328] [SeparateConstOffsetFromGEP] Support GEP reordering for different types (#90802) This doesn't show up in existing lit tests, but has an impact on real code -- especially after the canonicalization of GEPs to i8. Alive2 tests for the inbounds handling: Case 1: https://alive2.llvm.org/ce/z/6bfFY3 Case 2: https://alive2.llvm.org/ce/z/DkLMLF --- .../Scalar/SeparateConstOffsetFromGEP.cpp | 28 +- .../AMDGPU/reorder-gep-inbounds.ll | 297 +++++++++++- .../AMDGPU/reorder-gep.ll | 437 +++++++++++------- .../NVPTX/lower-gep-reorder.ll | 12 +- .../SeparateConstOffsetFromGEP/reorder-gep.ll | 63 +++ 5 files changed, 629 insertions(+), 208 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp index c54a956fc7e2..9f85396cde25 100644 --- a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp +++ b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp @@ -972,22 +972,13 @@ SeparateConstOffsetFromGEP::lowerToArithmetics(GetElementPtrInst *Variadic, bool SeparateConstOffsetFromGEP::reorderGEP(GetElementPtrInst *GEP, TargetTransformInfo &TTI) { - Type *GEPType = GEP->getResultElementType(); - // TODO: support reordering for non-trivial GEP chains - if (GEPType->isAggregateType() || GEP->getNumIndices() != 1) + if (GEP->getNumIndices() != 1) return false; auto PtrGEP = dyn_cast(GEP->getPointerOperand()); if (!PtrGEP) return false; - Type *PtrGEPType = PtrGEP->getResultElementType(); - // TODO: support reordering for non-trivial GEP chains - if (PtrGEPType->isAggregateType() || PtrGEP->getNumIndices() != 1) - return false; - - // TODO: support reordering for non-trivial GEP chains - if (PtrGEPType != GEPType || - PtrGEP->getSourceElementType() != GEP->getSourceElementType()) + if (PtrGEP->getNumIndices() != 1) return false; bool NestedNeedsExtraction; @@ -1002,8 +993,6 @@ bool SeparateConstOffsetFromGEP::reorderGEP(GetElementPtrInst *GEP, /*HasBaseReg=*/true, /*Scale=*/0, AddrSpace)) return false; - IRBuilder<> Builder(GEP); - Builder.SetCurrentDebugLocation(GEP->getDebugLoc()); bool GEPInBounds = GEP->isInBounds(); bool PtrGEPInBounds = PtrGEP->isInBounds(); bool IsChainInBounds = GEPInBounds && PtrGEPInBounds; @@ -1018,13 +1007,14 @@ bool SeparateConstOffsetFromGEP::reorderGEP(GetElementPtrInst *GEP, } } + IRBuilder<> Builder(GEP); // For trivial GEP chains, we can swap the indicies. - auto NewSrc = Builder.CreateGEP(PtrGEPType, PtrGEP->getPointerOperand(), - SmallVector(GEP->indices())); - cast(NewSrc)->setIsInBounds(IsChainInBounds); - auto NewGEP = Builder.CreateGEP(GEPType, NewSrc, - SmallVector(PtrGEP->indices())); - cast(NewGEP)->setIsInBounds(IsChainInBounds); + Value *NewSrc = Builder.CreateGEP( + GEP->getSourceElementType(), PtrGEP->getPointerOperand(), + SmallVector(GEP->indices()), "", IsChainInBounds); + Value *NewGEP = Builder.CreateGEP(PtrGEP->getSourceElementType(), NewSrc, + SmallVector(PtrGEP->indices()), + "", IsChainInBounds); GEP->replaceAllUsesWith(NewGEP); RecursivelyDeleteTriviallyDeadInstructions(GEP); return true; diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep-inbounds.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep-inbounds.ll index c24bbd5f658f..16e47f057bab 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep-inbounds.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep-inbounds.ll @@ -1,28 +1,27 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 ; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -S -passes=separate-const-offset-from-gep < %s | FileCheck %s -define void @inboundsPossiblyNegative(ptr %in.ptr, i32 %in.idx1) { +define void @inboundsPossiblyNegative(ptr %in.ptr, i64 %in.idx1) { ; CHECK-LABEL: define void @inboundsPossiblyNegative( -; CHECK-SAME: ptr [[IN_PTR:%.*]], i32 [[IN_IDX1:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[IN_IDX1]] to i64 -; CHECK-NEXT: [[TMP0:%.*]] = getelementptr <2 x i8>, ptr [[IN_PTR]], i64 [[IDXPROM]] -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr <2 x i8>, ptr [[TMP0]], i32 1 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr <2 x i8>, ptr [[IN_PTR]], i64 [[IN_IDX1]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr <2 x i8>, ptr [[TMP0]], i64 1 ; CHECK-NEXT: ret void ; entry: - %const1 = getelementptr inbounds <2 x i8>, ptr %in.ptr, i32 1 - %idx1 = getelementptr inbounds <2 x i8>, ptr %const1, i32 %in.idx1 + %const1 = getelementptr inbounds <2 x i8>, ptr %in.ptr, i64 1 + %idx1 = getelementptr inbounds <2 x i8>, ptr %const1, i64 %in.idx1 ret void } -define void @inboundsNonNegative(ptr %in.ptr, i32 %in.idx1) { -; CHECK-LABEL: define void @inboundsNonNegative( +define void @inboundsNonNegative_nonCanonical(ptr %in.ptr, i32 %in.idx1) { +; CHECK-LABEL: define void @inboundsNonNegative_nonCanonical( ; CHECK-SAME: ptr [[IN_PTR:%.*]], i32 [[IN_IDX1:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i32 [[IN_IDX1]], 2147483647 -; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[IN_IDX1_NNEG]] to i64 -; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <2 x i8>, ptr [[IN_PTR]], i64 [[IDXPROM]] +; CHECK-NEXT: [[IN_IDX1_NNEG1:%.*]] = and i32 [[IN_IDX1]], 2147483647 +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = sext i32 [[IN_IDX1_NNEG1]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <2 x i8>, ptr [[IN_PTR]], i64 [[IN_IDX1_NNEG]] ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <2 x i8>, ptr [[TMP0]], i32 1 ; CHECK-NEXT: ret void ; @@ -33,19 +32,277 @@ entry: ret void } -define void @inboundsNonchained(ptr %in.ptr, i32 %in.idx1) { +define void @inboundsNonNegative(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @inboundsNonNegative( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IDXPROM:%.*]] = and i64 [[IN_IDX1]], 9223372036854775807 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <2 x i8>, ptr [[IN_PTR]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <2 x i8>, ptr [[TMP0]], i64 1 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 9223372036854775807 + %const1 = getelementptr inbounds <2 x i8>, ptr %in.ptr, i64 1 + %idx1 = getelementptr inbounds <2 x i8>, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @inboundsNonchained(ptr %in.ptr, i64 %in.idx1) { ; CHECK-LABEL: define void @inboundsNonchained( -; CHECK-SAME: ptr [[IN_PTR:%.*]], i32 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i32 [[IN_IDX1]], 2147483647 -; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[IN_IDX1_NNEG]] to i64 +; CHECK-NEXT: [[IDXPROM:%.*]] = and i64 [[IN_IDX1]], 9223372036854775807 ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr <2 x i8>, ptr [[IN_PTR]], i64 [[IDXPROM]] -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr <2 x i8>, ptr [[TMP0]], i32 1 +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr <2 x i8>, ptr [[TMP0]], i64 1 ; CHECK-NEXT: ret void ; entry: - %in.idx1.nneg = and i32 %in.idx1, 2147483647 - %const1 = getelementptr inbounds <2 x i8>, ptr %in.ptr, i32 1 - %idx1 = getelementptr <2 x i8>, ptr %const1, i32 %in.idx1.nneg + %in.idx1.nneg = and i64 %in.idx1, 9223372036854775807 + %const1 = getelementptr inbounds <2 x i8>, ptr %in.ptr, i64 1 + %idx1 = getelementptr <2 x i8>, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @inboundsNonNegativeType_i16i8(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @inboundsNonNegativeType_i16i8( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IDXPROM:%.*]] = and i64 [[IN_IDX1]], 9223372036854775807 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[IN_PTR]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i16, ptr [[TMP0]], i64 1024 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 9223372036854775807 + %const1 = getelementptr inbounds i16, ptr %in.ptr, i64 1024 + %idx1 = getelementptr inbounds i8, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @inboundsNonNegative_i8i16(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @inboundsNonNegative_i8i16( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IDXPROM:%.*]] = and i64 [[IN_IDX1]], 9223372036854775807 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i16, ptr [[IN_PTR]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 1024 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 9223372036854775807 + %const1 = getelementptr inbounds i8, ptr %in.ptr, i64 1024 + %idx1 = getelementptr inbounds i16, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @inboundsNonchained_first(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @inboundsNonchained_first( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 9223372036854775807 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i32, ptr [[IN_PTR]], i64 [[IN_IDX1_NNEG]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i64 1024 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 9223372036854775807 + %const1 = getelementptr inbounds i8, ptr %in.ptr, i64 1024 + %idx1 = getelementptr i32, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @inboundsNonchained_second(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @inboundsNonchained_second( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 9223372036854775807 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[IN_PTR]], i64 [[IN_IDX1_NNEG]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i64 1024 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 9223372036854775807 + %const1 = getelementptr i8, ptr %in.ptr, i64 1024 + %idx1 = getelementptr inbounds i64, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @notInbounds(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @notInbounds( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 9223372036854775807 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i128, ptr [[IN_PTR]], i64 [[IN_IDX1_NNEG]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i64 1024 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 9223372036854775807 + %const1 = getelementptr i8, ptr %in.ptr, i64 1024 + %idx1 = getelementptr i128, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @vectorType1(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @vectorType1( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 2147483647 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <2 x i8>, ptr [[IN_PTR]], i64 [[IN_IDX1_NNEG]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <4 x i8>, ptr [[TMP0]], i32 3 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 2147483647 + %const1 = getelementptr inbounds <4 x i8>, ptr %in.ptr, i32 3 + %idx1 = getelementptr inbounds <2 x i8>, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @vectorType2(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @vectorType2( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 2147483647 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <4 x half>, ptr [[IN_PTR]], i64 [[IN_IDX1_NNEG]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <4 x i8>, ptr [[TMP0]], i32 1 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 2147483647 + %const1 = getelementptr inbounds <4 x i8>, ptr %in.ptr, i32 1 + %idx1 = getelementptr inbounds <4 x half>, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @vectorType3(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @vectorType3( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 2147483647 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds ptr, ptr [[IN_PTR]], i64 [[IN_IDX1_NNEG]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <4 x ptr>, ptr [[TMP0]], i32 1 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 2147483647 + %const1 = getelementptr inbounds <4 x ptr>, ptr %in.ptr, i32 1 + %idx1 = getelementptr inbounds ptr, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @vectorType4(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @vectorType4( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 2147483647 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <8 x ptr addrspace(1)>, ptr [[IN_PTR]], i64 [[IN_IDX1_NNEG]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <4 x ptr>, ptr [[TMP0]], i32 3 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 2147483647 + %const1 = getelementptr inbounds <4 x ptr>, ptr %in.ptr, i32 3 + %idx1 = getelementptr inbounds <8 x ptr addrspace(1)>, ptr %const1, i64 %in.idx1.nneg + ret void +} + + +define void @ptrType(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @ptrType( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 2147483647 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds ptr, ptr [[IN_PTR]], i64 [[IN_IDX1_NNEG]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr addrspace(2), ptr [[TMP0]], i32 1 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 2147483647 + %const1 = getelementptr inbounds ptr addrspace(2), ptr %in.ptr, i32 1 + %idx1 = getelementptr inbounds ptr, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @ptrType2(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @ptrType2( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 2147483647 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i64, ptr [[IN_PTR]], i64 [[IN_IDX1_NNEG]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr addrspace(3), ptr [[TMP0]], i32 3 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 2147483647 + %const1 = getelementptr inbounds ptr addrspace(3), ptr %in.ptr, i32 3 + %idx1 = getelementptr inbounds i64, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @ptrType3(ptr %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @ptrType3( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 2147483647 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i16, ptr [[IN_PTR]], i64 [[IN_IDX1_NNEG]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr addrspace(7), ptr [[TMP0]], i32 3 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 2147483647 + %const1 = getelementptr inbounds ptr addrspace(7), ptr %in.ptr, i32 3 + %idx1 = getelementptr inbounds i16, ptr %const1, i64 %in.idx1.nneg + ret void +} + +define void @addrspace1(ptr addrspace(1) %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @addrspace1( +; CHECK-SAME: ptr addrspace(1) [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 9223372036854775807 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i128, ptr addrspace(1) [[IN_PTR]], i64 [[IN_IDX1_NNEG]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP0]], i64 1024 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 9223372036854775807 + %const1 = getelementptr inbounds i8, ptr addrspace(1) %in.ptr, i64 1024 + %idx1 = getelementptr inbounds i128, ptr addrspace(1) %const1, i64 %in.idx1.nneg + ret void +} + +define void @addrspace3(ptr addrspace(3) %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @addrspace3( +; CHECK-SAME: ptr addrspace(3) [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 9223372036854775807 +; CHECK-NEXT: [[IDXPROM:%.*]] = trunc i64 [[IN_IDX1_NNEG]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i128, ptr addrspace(3) [[IN_PTR]], i32 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP0]], i64 1024 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 9223372036854775807 + %const1 = getelementptr inbounds i8, ptr addrspace(3) %in.ptr, i64 1024 + %idx1 = getelementptr inbounds i128, ptr addrspace(3) %const1, i64 %in.idx1.nneg + ret void +} + +define void @addrspace7(ptr addrspace(7) %in.ptr, i64 %in.idx1) { +; CHECK-LABEL: define void @addrspace7( +; CHECK-SAME: ptr addrspace(7) [[IN_PTR:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IN_IDX1_NNEG:%.*]] = and i64 [[IN_IDX1]], 9223372036854775807 +; CHECK-NEXT: [[IDXPROM:%.*]] = trunc i64 [[IN_IDX1_NNEG]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i128, ptr addrspace(7) [[IN_PTR]], i32 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(7) [[TMP0]], i64 1024 +; CHECK-NEXT: ret void +; +entry: + %in.idx1.nneg = and i64 %in.idx1, 9223372036854775807 + %const1 = getelementptr inbounds i8, ptr addrspace(7) %in.ptr, i64 1024 + %idx1 = getelementptr inbounds i128, ptr addrspace(7) %const1, i64 %in.idx1.nneg ret void } diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep.ll index 7137f0fb66fd..b4119f0b50b4 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep.ll @@ -1,175 +1,286 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a --start-before=separate-const-offset-from-gep < %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a --passes=separate-const-offset-from-gep < %s | FileCheck %s -define protected amdgpu_kernel void @sink_addr(ptr addrspace(3) %in.ptr, i32 %in.idx0, i32 %in.idx1) { -; CHECK-LABEL: sink_addr: -; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0 -; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: s_lshl_b32 s3, s1, 1 -; CHECK-NEXT: s_add_i32 s0, s0, s3 -; CHECK-NEXT: s_lshl_b32 s2, s2, 1 -; CHECK-NEXT: s_add_i32 s0, s0, s2 -; CHECK-NEXT: s_cmp_lg_u32 s1, 0 -; CHECK-NEXT: s_cbranch_scc1 .LBB0_2 -; CHECK-NEXT: ; %bb.1: ; %bb.1 -; CHECK-NEXT: v_mov_b32_e32 v12, s0 -; CHECK-NEXT: ds_read_b128 v[0:3], v12 -; CHECK-NEXT: ds_read_b128 v[4:7], v12 offset:512 -; CHECK-NEXT: ds_read_b128 v[8:11], v12 offset:1024 -; CHECK-NEXT: ds_read_b128 v[12:15], v12 offset:1536 -; CHECK-NEXT: s_waitcnt lgkmcnt(3) -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v[0:3] -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: s_waitcnt lgkmcnt(2) -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v[4:7] -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: s_waitcnt lgkmcnt(1) -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v[8:11] -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v[12:15] -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: .LBB0_2: ; %end -; CHECK-NEXT: s_add_i32 s1, s0, 0x200 -; CHECK-NEXT: v_mov_b32_e32 v0, s0 -; CHECK-NEXT: s_add_i32 s2, s0, 0x400 -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v0 -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: v_mov_b32_e32 v0, s1 -; CHECK-NEXT: s_add_i32 s3, s0, 0x600 -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v0 -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: v_mov_b32_e32 v0, s2 -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v0 -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: v_mov_b32_e32 v0, s3 -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v0 -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: s_endpgm +define void @sink_addr(ptr addrspace(3) %in.ptr, i64 %in.idx0, i64 %in.idx1) { +; CHECK-LABEL: define void @sink_addr( +; CHECK-SAME: ptr addrspace(3) [[IN_PTR:%.*]], i64 [[IN_IDX0:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IDXPROM:%.*]] = trunc i64 [[IN_IDX0]] to i32 +; CHECK-NEXT: [[BASE:%.*]] = getelementptr half, ptr addrspace(3) [[IN_PTR]], i32 [[IDXPROM]] +; CHECK-NEXT: [[IDXPROM1:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX0:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM1]] +; CHECK-NEXT: [[IDXPROM2:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM2]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr half, ptr addrspace(3) [[TMP0]], i64 256 +; CHECK-NEXT: [[IDXPROM3:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM3]] +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr half, ptr addrspace(3) [[TMP2]], i64 512 +; CHECK-NEXT: [[IDXPROM4:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM4]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP4]], i64 768 +; CHECK-NEXT: ret void +; entry: - %base = getelementptr half, ptr addrspace(3) %in.ptr, i32 %in.idx0 - %idx0 = getelementptr half, ptr addrspace(3) %base, i32 %in.idx1 - %const1 = getelementptr half, ptr addrspace(3) %base, i32 256 - %idx1 = getelementptr half, ptr addrspace(3) %const1, i32 %in.idx1 - %const2 = getelementptr half, ptr addrspace(3) %base, i32 512 - %idx2 = getelementptr half, ptr addrspace(3) %const2, i32 %in.idx1 - %const3 = getelementptr half, ptr addrspace(3) %base, i32 768 - %idx3 = getelementptr half, ptr addrspace(3) %const3, i32 %in.idx1 - %cmp0 = icmp eq i32 %in.idx0, 0 - br i1 %cmp0, label %bb.1, label %end + %base = getelementptr half, ptr addrspace(3) %in.ptr, i64 %in.idx0 + %idx0 = getelementptr half, ptr addrspace(3) %base, i64 %in.idx1 + %const1 = getelementptr half, ptr addrspace(3) %base, i64 256 + %idx1 = getelementptr half, ptr addrspace(3) %const1, i64 %in.idx1 + %const2 = getelementptr half, ptr addrspace(3) %base, i64 512 + %idx2 = getelementptr half, ptr addrspace(3) %const2, i64 %in.idx1 + %const3 = getelementptr half, ptr addrspace(3) %base, i64 768 + %idx3 = getelementptr half, ptr addrspace(3) %const3, i64 %in.idx1 + ret void +} + +define void @illegal_addr_mode(ptr addrspace(3) %in.ptr, i64 %in.idx0, i64 %in.idx1) { +; CHECK-LABEL: define void @illegal_addr_mode( +; CHECK-SAME: ptr addrspace(3) [[IN_PTR:%.*]], i64 [[IN_IDX0:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IDXPROM:%.*]] = trunc i64 [[IN_IDX0]] to i32 +; CHECK-NEXT: [[BASE:%.*]] = getelementptr half, ptr addrspace(3) [[IN_PTR]], i32 [[IDXPROM]] +; CHECK-NEXT: [[IDXPROM1:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX0:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM1]] +; CHECK-NEXT: [[CONST1:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i64 38192 +; CHECK-NEXT: [[IDXPROM2:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX1:%.*]] = getelementptr half, ptr addrspace(3) [[CONST1]], i32 [[IDXPROM2]] +; CHECK-NEXT: [[CONST2:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i64 38448 +; CHECK-NEXT: [[IDXPROM3:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX2:%.*]] = getelementptr half, ptr addrspace(3) [[CONST2]], i32 [[IDXPROM3]] +; CHECK-NEXT: [[CONST3:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i64 38764 +; CHECK-NEXT: [[IDXPROM4:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX3:%.*]] = getelementptr half, ptr addrspace(3) [[CONST3]], i32 [[IDXPROM4]] +; CHECK-NEXT: ret void +; +entry: + %base = getelementptr half, ptr addrspace(3) %in.ptr, i64 %in.idx0 + %idx0 = getelementptr half, ptr addrspace(3) %base, i64 %in.idx1 + %const1 = getelementptr half, ptr addrspace(3) %base, i64 38192 + %idx1 = getelementptr half, ptr addrspace(3) %const1, i64 %in.idx1 + %const2 = getelementptr half, ptr addrspace(3) %base, i64 38448 + %idx2 = getelementptr half, ptr addrspace(3) %const2, i64 %in.idx1 + %const3 = getelementptr half, ptr addrspace(3) %base, i64 38764 + %idx3 = getelementptr half, ptr addrspace(3) %const3, i64 %in.idx1 + ret void +} + + +define void @reorder_i8half(ptr addrspace(3) %in.ptr, i64 %in.idx0, i64 %in.idx1) { +; CHECK-LABEL: define void @reorder_i8half( +; CHECK-SAME: ptr addrspace(3) [[IN_PTR:%.*]], i64 [[IN_IDX0:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IDXPROM:%.*]] = trunc i64 [[IN_IDX0]] to i32 +; CHECK-NEXT: [[BASE:%.*]] = getelementptr i8, ptr addrspace(3) [[IN_PTR]], i32 [[IDXPROM]] +; CHECK-NEXT: [[IDXPROM1:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX0:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM1]] +; CHECK-NEXT: [[IDXPROM2:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM2]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP0]], i64 256 +; CHECK-NEXT: [[IDXPROM3:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM3]] +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i64 512 +; CHECK-NEXT: [[IDXPROM4:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM4]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i64 768 +; CHECK-NEXT: ret void +; +entry: + %base = getelementptr i8, ptr addrspace(3) %in.ptr, i64 %in.idx0 + %idx0 = getelementptr half, ptr addrspace(3) %base, i64 %in.idx1 + %const1 = getelementptr i8, ptr addrspace(3) %base, i64 256 + %idx1 = getelementptr half, ptr addrspace(3) %const1, i64 %in.idx1 + %const2 = getelementptr i8, ptr addrspace(3) %base, i64 512 + %idx2 = getelementptr half, ptr addrspace(3) %const2, i64 %in.idx1 + %const3 = getelementptr i8, ptr addrspace(3) %base, i64 768 + %idx3 = getelementptr half, ptr addrspace(3) %const3, i64 %in.idx1 + ret void +} + +define void @reorder_i64half(ptr addrspace(3) %in.ptr, i64 %in.idx0, i64 %in.idx1) { +; CHECK-LABEL: define void @reorder_i64half( +; CHECK-SAME: ptr addrspace(3) [[IN_PTR:%.*]], i64 [[IN_IDX0:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IDXPROM:%.*]] = trunc i64 [[IN_IDX0]] to i32 +; CHECK-NEXT: [[BASE:%.*]] = getelementptr i64, ptr addrspace(3) [[IN_PTR]], i32 [[IDXPROM]] +; CHECK-NEXT: [[IDXPROM1:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX0:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM1]] +; CHECK-NEXT: [[IDXPROM2:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM2]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr addrspace(3) [[TMP0]], i64 256 +; CHECK-NEXT: [[IDXPROM3:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM3]] +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr addrspace(3) [[TMP2]], i64 512 +; CHECK-NEXT: [[IDXPROM4:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM4]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr addrspace(3) [[TMP4]], i64 768 +; CHECK-NEXT: ret void +; +entry: + %base = getelementptr i64, ptr addrspace(3) %in.ptr, i64 %in.idx0 + %idx0 = getelementptr half, ptr addrspace(3) %base, i64 %in.idx1 + %const1 = getelementptr i64, ptr addrspace(3) %base, i64 256 + %idx1 = getelementptr half, ptr addrspace(3) %const1, i64 %in.idx1 + %const2 = getelementptr i64, ptr addrspace(3) %base, i64 512 + %idx2 = getelementptr half, ptr addrspace(3) %const2, i64 %in.idx1 + %const3 = getelementptr i64, ptr addrspace(3) %base, i64 768 + %idx3 = getelementptr half, ptr addrspace(3) %const3, i64 %in.idx1 + ret void +} -bb.1: - %val0 = load <8 x half>, ptr addrspace(3) %idx0, align 16 - %val1 = load <8 x half>, ptr addrspace(3) %idx1, align 16 - %val2 = load <8 x half>, ptr addrspace(3) %idx2, align 16 - %val3 = load <8 x half>, ptr addrspace(3) %idx3, align 16 - call void asm sideeffect "; use $0", "v"(<8 x half> %val0) - call void asm sideeffect "; use $0", "v"(<8 x half> %val1) - call void asm sideeffect "; use $0", "v"(<8 x half> %val2) - call void asm sideeffect "; use $0", "v"(<8 x half> %val3) - br label %end +define void @reorder_halfi8(ptr addrspace(3) %in.ptr, i64 %in.idx0, i64 %in.idx1) { +; CHECK-LABEL: define void @reorder_halfi8( +; CHECK-SAME: ptr addrspace(3) [[IN_PTR:%.*]], i64 [[IN_IDX0:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IDXPROM:%.*]] = trunc i64 [[IN_IDX0]] to i32 +; CHECK-NEXT: [[BASE:%.*]] = getelementptr half, ptr addrspace(3) [[IN_PTR]], i32 [[IDXPROM]] +; CHECK-NEXT: [[IDXPROM1:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX0:%.*]] = getelementptr i8, ptr addrspace(3) [[BASE]], i32 [[IDXPROM1]] +; CHECK-NEXT: [[IDXPROM2:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr addrspace(3) [[BASE]], i32 [[IDXPROM2]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr half, ptr addrspace(3) [[TMP0]], i64 256 +; CHECK-NEXT: [[IDXPROM3:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr addrspace(3) [[BASE]], i32 [[IDXPROM3]] +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr half, ptr addrspace(3) [[TMP2]], i64 512 +; CHECK-NEXT: [[IDXPROM4:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(3) [[BASE]], i32 [[IDXPROM4]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP4]], i64 768 +; CHECK-NEXT: ret void +; +entry: + %base = getelementptr half, ptr addrspace(3) %in.ptr, i64 %in.idx0 + %idx0 = getelementptr i8, ptr addrspace(3) %base, i64 %in.idx1 + %const1 = getelementptr half, ptr addrspace(3) %base, i64 256 + %idx1 = getelementptr i8, ptr addrspace(3) %const1, i64 %in.idx1 + %const2 = getelementptr half, ptr addrspace(3) %base, i64 512 + %idx2 = getelementptr i8, ptr addrspace(3) %const2, i64 %in.idx1 + %const3 = getelementptr half, ptr addrspace(3) %base, i64 768 + %idx3 = getelementptr i8, ptr addrspace(3) %const3, i64 %in.idx1 + ret void +} -end: - call void asm sideeffect "; use $0", "v"(ptr addrspace(3) %idx0) - call void asm sideeffect "; use $0", "v"(ptr addrspace(3) %idx1) - call void asm sideeffect "; use $0", "v"(ptr addrspace(3) %idx2) - call void asm sideeffect "; use $0", "v"(ptr addrspace(3) %idx3) + + +define void @bad_index(ptr addrspace(3) %in.ptr, i64 %in.idx0, i64 %in.idx1) { +; CHECK-LABEL: define void @bad_index( +; CHECK-SAME: ptr addrspace(3) [[IN_PTR:%.*]], i64 [[IN_IDX0:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IDXPROM:%.*]] = trunc i64 [[IN_IDX0]] to i32 +; CHECK-NEXT: [[BASE:%.*]] = getelementptr half, ptr addrspace(3) [[IN_PTR]], i32 [[IDXPROM]] +; CHECK-NEXT: [[IDXPROM1:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX0:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM1]] +; CHECK-NEXT: [[IDXPROM2:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM2]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i64 1 +; CHECK-NEXT: [[IDXPROM3:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM3]] +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i64 2 +; CHECK-NEXT: [[IDXPROM4:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr half, ptr addrspace(3) [[BASE]], i32 [[IDXPROM4]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP0]], i64 3 +; CHECK-NEXT: ret void +; +entry: + %base = getelementptr half, ptr addrspace(3) %in.ptr, i64 %in.idx0 + %idx0 = getelementptr half, ptr addrspace(3) %base, i64 %in.idx1 + %const1 = getelementptr i8, ptr addrspace(3) %base, i64 1 + %idx1 = getelementptr half, ptr addrspace(3) %const1, i64 %in.idx1 + %const2 = getelementptr i8, ptr addrspace(3) %base, i64 2 + %idx2 = getelementptr half, ptr addrspace(3) %const2, i64 %in.idx1 + %const3 = getelementptr i8, ptr addrspace(3) %base, i64 3 + %idx3 = getelementptr half, ptr addrspace(3) %const3, i64 %in.idx1 ret void } -define protected amdgpu_kernel void @illegal_addr_mode(ptr addrspace(3) %in.ptr, i32 %in.idx0, i32 %in.idx1) { -; CHECK-LABEL: illegal_addr_mode: -; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x0 -; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: s_lshl_b32 s0, s5, 1 -; CHECK-NEXT: s_lshl_b32 s1, s6, 1 -; CHECK-NEXT: s_add_i32 s3, s4, s0 -; CHECK-NEXT: s_add_i32 s3, s3, s1 -; CHECK-NEXT: s_add_i32 s2, s3, 0x12a60 -; CHECK-NEXT: s_add_i32 s1, s3, 0x12c60 -; CHECK-NEXT: s_add_i32 s0, s3, 0x12ed8 -; CHECK-NEXT: s_cmp_lg_u32 s5, 0 -; CHECK-NEXT: s_cbranch_scc1 .LBB1_2 -; CHECK-NEXT: ; %bb.1: ; %bb.1 -; CHECK-NEXT: v_mov_b32_e32 v0, s3 -; CHECK-NEXT: v_mov_b32_e32 v4, s2 -; CHECK-NEXT: v_mov_b32_e32 v8, s1 -; CHECK-NEXT: v_mov_b32_e32 v12, s0 -; CHECK-NEXT: ds_read_b128 v[0:3], v0 -; CHECK-NEXT: ds_read_b128 v[4:7], v4 -; CHECK-NEXT: ds_read_b128 v[8:11], v8 -; CHECK-NEXT: ds_read_b128 v[12:15], v12 -; CHECK-NEXT: s_waitcnt lgkmcnt(3) -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v[0:3] -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: s_waitcnt lgkmcnt(2) -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v[4:7] -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: s_waitcnt lgkmcnt(1) -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v[8:11] -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v[12:15] -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: .LBB1_2: ; %end -; CHECK-NEXT: v_mov_b32_e32 v0, s3 -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v0 -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: v_mov_b32_e32 v0, s2 -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v0 -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: v_mov_b32_e32 v0, s1 -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v0 -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: v_mov_b32_e32 v0, s0 -; CHECK-NEXT: ;;#ASMSTART -; CHECK-NEXT: ; use v0 -; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: s_endpgm + +%struct.vec = type { [8 x i8], [4 x half] } +define void @vector_struct_type(ptr addrspace(3) %in.ptr, i64 %in.idx0, i64 %in.idx1) { +; CHECK-LABEL: define void @vector_struct_type( +; CHECK-SAME: ptr addrspace(3) [[IN_PTR:%.*]], i64 [[IN_IDX0:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IDXPROM:%.*]] = trunc i64 [[IN_IDX0]] to i32 +; CHECK-NEXT: [[BASE:%.*]] = getelementptr [1024 x %struct.vec], ptr addrspace(3) [[IN_PTR]], i32 [[IDXPROM]] +; CHECK-NEXT: [[IDXPROM1:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX0:%.*]] = getelementptr i8, ptr addrspace(3) [[BASE]], i32 [[IDXPROM1]] +; CHECK-NEXT: [[CONST1:%.*]] = getelementptr [1024 x %struct.vec], ptr addrspace(3) [[BASE]], i64 256 +; CHECK-NEXT: [[IDXPROM2:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX1:%.*]] = getelementptr i8, ptr addrspace(3) [[CONST1]], i32 [[IDXPROM2]] +; CHECK-NEXT: [[CONST2:%.*]] = getelementptr [1024 x %struct.vec], ptr addrspace(3) [[BASE]], i64 512 +; CHECK-NEXT: [[IDXPROM3:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX2:%.*]] = getelementptr i8, ptr addrspace(3) [[CONST2]], i32 [[IDXPROM3]] +; CHECK-NEXT: [[CONST3:%.*]] = getelementptr [1024 x %struct.vec], ptr addrspace(3) [[BASE]], i64 768 +; CHECK-NEXT: [[IDXPROM4:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX3:%.*]] = getelementptr i8, ptr addrspace(3) [[CONST3]], i32 [[IDXPROM4]] +; CHECK-NEXT: ret void +; entry: - %base = getelementptr half, ptr addrspace(3) %in.ptr, i32 %in.idx0 - %idx0 = getelementptr half, ptr addrspace(3) %base, i32 %in.idx1 - %const1 = getelementptr half, ptr addrspace(3) %base, i32 38192 - %idx1 = getelementptr half, ptr addrspace(3) %const1, i32 %in.idx1 - %const2 = getelementptr half, ptr addrspace(3) %base, i32 38448 - %idx2 = getelementptr half, ptr addrspace(3) %const2, i32 %in.idx1 - %const3 = getelementptr half, ptr addrspace(3) %base, i32 38764 - %idx3 = getelementptr half, ptr addrspace(3) %const3, i32 %in.idx1 - %cmp0 = icmp eq i32 %in.idx0, 0 - br i1 %cmp0, label %bb.1, label %end + %base = getelementptr [1024 x %struct.vec], ptr addrspace(3) %in.ptr, i64 %in.idx0 + %idx0 = getelementptr i8, ptr addrspace(3) %base, i64 %in.idx1 + %const1 = getelementptr [1024 x %struct.vec], ptr addrspace(3) %base, i64 256 + %idx1 = getelementptr i8, ptr addrspace(3) %const1, i64 %in.idx1 + %const2 = getelementptr [1024 x %struct.vec], ptr addrspace(3) %base, i64 512 + %idx2 = getelementptr i8, ptr addrspace(3) %const2, i64 %in.idx1 + %const3 = getelementptr [1024 x %struct.vec], ptr addrspace(3) %base, i64 768 + %idx3 = getelementptr i8, ptr addrspace(3) %const3, i64 %in.idx1 + ret void +} -bb.1: - %val0 = load <8 x half>, ptr addrspace(3) %idx0, align 16 - %val1 = load <8 x half>, ptr addrspace(3) %idx1, align 16 - %val2 = load <8 x half>, ptr addrspace(3) %idx2, align 16 - %val3 = load <8 x half>, ptr addrspace(3) %idx3, align 16 - call void asm sideeffect "; use $0", "v"(<8 x half> %val0) - call void asm sideeffect "; use $0", "v"(<8 x half> %val1) - call void asm sideeffect "; use $0", "v"(<8 x half> %val2) - call void asm sideeffect "; use $0", "v"(<8 x half> %val3) - br label %end +define void @struct_type(ptr addrspace(3) %in.ptr, i64 %in.idx0, i64 %in.idx1) { +; CHECK-LABEL: define void @struct_type( +; CHECK-SAME: ptr addrspace(3) [[IN_PTR:%.*]], i64 [[IN_IDX0:%.*]], i64 [[IN_IDX1:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IDXPROM:%.*]] = trunc i64 [[IN_IDX0]] to i32 +; CHECK-NEXT: [[BASE:%.*]] = getelementptr [[STRUCT_VEC:%.*]], ptr addrspace(3) [[IN_PTR]], i32 [[IDXPROM]] +; CHECK-NEXT: [[IDXPROM1:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[IDX0:%.*]] = getelementptr i8, ptr addrspace(3) [[BASE]], i32 [[IDXPROM1]] +; CHECK-NEXT: [[IDXPROM2:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr addrspace(3) [[BASE]], i32 [[IDXPROM2]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [[STRUCT_VEC]], ptr addrspace(3) [[TMP0]], i64 256 +; CHECK-NEXT: [[IDXPROM3:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr addrspace(3) [[BASE]], i32 [[IDXPROM3]] +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_VEC]], ptr addrspace(3) [[TMP2]], i64 512 +; CHECK-NEXT: [[IDXPROM4:%.*]] = trunc i64 [[IN_IDX1]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(3) [[BASE]], i32 [[IDXPROM4]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr [[STRUCT_VEC]], ptr addrspace(3) [[TMP4]], i64 768 +; CHECK-NEXT: ret void +; +entry: + %base = getelementptr %struct.vec, ptr addrspace(3) %in.ptr, i64 %in.idx0 + %idx0 = getelementptr i8, ptr addrspace(3) %base, i64 %in.idx1 + %const1 = getelementptr %struct.vec, ptr addrspace(3) %base, i64 256 + %idx1 = getelementptr i8, ptr addrspace(3) %const1, i64 %in.idx1 + %const2 = getelementptr %struct.vec, ptr addrspace(3) %base, i64 512 + %idx2 = getelementptr i8, ptr addrspace(3) %const2, i64 %in.idx1 + %const3 = getelementptr %struct.vec, ptr addrspace(3) %base, i64 768 + %idx3 = getelementptr i8, ptr addrspace(3) %const3, i64 %in.idx1 + ret void +} -end: - call void asm sideeffect "; use $0", "v"(ptr addrspace(3) %idx0) - call void asm sideeffect "; use $0", "v"(ptr addrspace(3) %idx1) - call void asm sideeffect "; use $0", "v"(ptr addrspace(3) %idx2) - call void asm sideeffect "; use $0", "v"(ptr addrspace(3) %idx3) +define void @struct_type_multiindex(ptr addrspace(3) %in.ptr, i64 %in.idx0, i32 %in.idx1, i64 %in.idx2) { +; CHECK-LABEL: define void @struct_type_multiindex( +; CHECK-SAME: ptr addrspace(3) [[IN_PTR:%.*]], i64 [[IN_IDX0:%.*]], i32 [[IN_IDX1:%.*]], i64 [[IN_IDX2:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[IDXPROM:%.*]] = trunc i64 [[IN_IDX0]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr [[STRUCT_VEC:%.*]], ptr addrspace(3) [[IN_PTR]], i32 [[IDXPROM]], i32 0, i32 0 +; CHECK-NEXT: [[IDXPROM2:%.*]] = trunc i64 [[IN_IDX2]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP0]], i32 [[IDXPROM2]] +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP1]], i32 2 +; CHECK-NEXT: [[IDXPROM3:%.*]] = trunc i64 [[IN_IDX0]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_VEC]], ptr addrspace(3) [[IN_PTR]], i32 [[IDXPROM3]], i32 0, i32 0 +; CHECK-NEXT: [[IDXPROM5:%.*]] = trunc i64 [[IN_IDX2]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP3]], i32 [[IDXPROM5]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 4 +; CHECK-NEXT: [[IDXPROM6:%.*]] = trunc i64 [[IN_IDX0]] to i32 +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_VEC]], ptr addrspace(3) [[IN_PTR]], i32 [[IDXPROM6]], i32 0, i32 0 +; CHECK-NEXT: [[IDXPROM8:%.*]] = trunc i64 [[IN_IDX2]] to i32 +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 [[IDXPROM8]] +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 6 +; CHECK-NEXT: ret void +; +entry: + %const1 = getelementptr %struct.vec, ptr addrspace(3) %in.ptr, i64 %in.idx0, i32 0, i32 2 + %idx1 = getelementptr i8, ptr addrspace(3) %const1, i64 %in.idx2 + %const2 = getelementptr %struct.vec, ptr addrspace(3) %in.ptr, i64 %in.idx0, i32 0, i32 4 + %idx2 = getelementptr i8, ptr addrspace(3) %const2, i64 %in.idx2 + %const3 = getelementptr %struct.vec, ptr addrspace(3) %in.ptr, i64 %in.idx0, i32 0, i32 6 + %idx3 = getelementptr i8, ptr addrspace(3) %const3, i64 %in.idx2 ret void } diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/lower-gep-reorder.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/lower-gep-reorder.ll index a91c8172177f..43dda1ae1517 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/lower-gep-reorder.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/lower-gep-reorder.ll @@ -7,14 +7,14 @@ define protected amdgpu_kernel void @sink_addr(ptr %in.ptr, i64 %in.idx0, i64 %i ; CHECK-NEXT: entry: ; CHECK-NEXT: [[IDX0:%.*]] = getelementptr [8192 x i64], ptr [[IN_PTR]], i64 [[IN_IDX0]], i64 [[IN_IDX1]] ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr [8192 x i64], ptr [[IN_PTR]], i64 [[IN_IDX0]], i64 0 -; CHECK-NEXT: [[CONST11:%.*]] = getelementptr i8, ptr [[TMP0]], i64 2048 -; CHECK-NEXT: [[IDX1:%.*]] = getelementptr i64, ptr [[CONST11]], i64 [[IN_IDX1]] +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[TMP0]], i64 [[IN_IDX1]] +; CHECK-NEXT: [[IDX1:%.*]] = getelementptr i8, ptr [[TMP3]], i64 2048 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [8192 x i64], ptr [[IN_PTR]], i64 [[IN_IDX0]], i64 0 -; CHECK-NEXT: [[CONST22:%.*]] = getelementptr i8, ptr [[TMP1]], i64 4096 -; CHECK-NEXT: [[IDX2:%.*]] = getelementptr i64, ptr [[CONST22]], i64 [[IN_IDX1]] +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[TMP1]], i64 [[IN_IDX1]] +; CHECK-NEXT: [[IDX2:%.*]] = getelementptr i8, ptr [[TMP4]], i64 4096 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr [8192 x i64], ptr [[IN_PTR]], i64 [[IN_IDX0]], i64 0 -; CHECK-NEXT: [[CONST33:%.*]] = getelementptr i8, ptr [[TMP2]], i64 6144 -; CHECK-NEXT: [[IDX3:%.*]] = getelementptr i64, ptr [[CONST33]], i64 [[IN_IDX1]] +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[TMP2]], i64 [[IN_IDX1]] +; CHECK-NEXT: [[IDX3:%.*]] = getelementptr i8, ptr [[TMP7]], i64 6144 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i64 [[IN_IDX0]], 0 ; CHECK-NEXT: br i1 [[CMP0]], label [[BB_1:%.*]], label [[END:%.*]] ; CHECK: bb.1: diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/reorder-gep.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/reorder-gep.ll index a15f11a634db..2e3b6ca3653f 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/reorder-gep.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/reorder-gep.ll @@ -186,3 +186,66 @@ end: call void asm sideeffect "; use $0", "v"(ptr %idx3) ret void } + + +define void @different_type_reorder2(ptr %in.ptr, i64 %in.idx0, i64 %in.idx1) { +; CHECK-LABEL: define void @different_type_reorder2( +; CHECK-SAME: ptr [[IN_PTR:%.*]], i64 [[IN_IDX0:%.*]], i64 [[IN_IDX1:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[BASE:%.*]] = getelementptr i8, ptr [[IN_PTR]], i64 [[IN_IDX0]] +; CHECK-NEXT: [[IDX0:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[IN_IDX1]] +; CHECK-NEXT: [[CONST1:%.*]] = getelementptr i64, ptr [[BASE]], i64 256 +; CHECK-NEXT: [[IDX1:%.*]] = getelementptr i8, ptr [[CONST1]], i64 [[IN_IDX1]] +; CHECK-NEXT: [[CONST2:%.*]] = getelementptr i64, ptr [[BASE]], i64 512 +; CHECK-NEXT: [[IDX2:%.*]] = getelementptr i8, ptr [[CONST2]], i64 [[IN_IDX1]] +; CHECK-NEXT: [[CONST3:%.*]] = getelementptr i64, ptr [[BASE]], i64 768 +; CHECK-NEXT: [[IDX3:%.*]] = getelementptr i8, ptr [[CONST3]], i64 [[IN_IDX1]] +; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i64 [[IN_IDX0]], 0 +; CHECK-NEXT: br i1 [[CMP0]], label [[BB_1:%.*]], label [[END:%.*]] +; CHECK: bb.1: +; CHECK-NEXT: [[VAL0:%.*]] = load <8 x i64>, ptr [[IDX0]], align 16 +; CHECK-NEXT: [[VAL1:%.*]] = load <8 x i64>, ptr [[IDX1]], align 16 +; CHECK-NEXT: [[VAL2:%.*]] = load <8 x i64>, ptr [[IDX2]], align 16 +; CHECK-NEXT: [[VAL3:%.*]] = load <8 x i64>, ptr [[IDX3]], align 16 +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: br label [[END]] +; CHECK: end: +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: call void asm sideeffect " +; CHECK-NEXT: ret void +; +entry: + %base = getelementptr i8, ptr %in.ptr, i64 %in.idx0 + %idx0 = getelementptr i8, ptr %base, i64 %in.idx1 + %const1 = getelementptr i64, ptr %base, i64 256 + %idx1 = getelementptr i8, ptr %const1, i64 %in.idx1 + %const2 = getelementptr i64, ptr %base, i64 512 + %idx2 = getelementptr i8, ptr %const2, i64 %in.idx1 + %const3 = getelementptr i64, ptr %base, i64 768 + %idx3 = getelementptr i8, ptr %const3, i64 %in.idx1 + %cmp0 = icmp eq i64 %in.idx0, 0 + br i1 %cmp0, label %bb.1, label %end + +bb.1: + %val0 = load <8 x i64>, ptr %idx0, align 16 + %val1 = load <8 x i64>, ptr %idx1, align 16 + %val2 = load <8 x i64>, ptr %idx2, align 16 + %val3 = load <8 x i64>, ptr %idx3, align 16 + call void asm sideeffect "; use $0", "v"(<8 x i64> %val0) + call void asm sideeffect "; use $0", "v"(<8 x i64> %val1) + call void asm sideeffect "; use $0", "v"(<8 x i64> %val2) + call void asm sideeffect "; use $0", "v"(<8 x i64> %val3) + br label %end + +end: + call void asm sideeffect "; use $0", "v"(ptr %idx0) + call void asm sideeffect "; use $0", "v"(ptr %idx1) + call void asm sideeffect "; use $0", "v"(ptr %idx2) + call void asm sideeffect "; use $0", "v"(ptr %idx3) + ret void +} -- GitLab From e4763ca83b90eed96be6fd83a9867e435f4b8ffe Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Thu, 9 May 2024 16:58:40 -0700 Subject: [PATCH 216/328] [ctx_profile] Pull `ContextNode` in a `.inc` file (#91669) This pulls out `ContextNode` as we need to use it pretty much as-is to implement a writer. The writer will be implemented on the LLVM side because it takes a dependency on BitStreamWriter. Since we can't reuse a header between compiler-rt and llvm, we use a header file which is copied on both sides, and test that the 2 copies are identical. The changes adds the necessary other stuff for compiler-rt/ctx_profile testing. --- compiler-rt/lib/ctx_profile/CMakeLists.txt | 1 + .../lib/ctx_profile/CtxInstrContextNode.h | 116 +++++++++++++++++ .../lib/ctx_profile/CtxInstrProfiling.cpp | 58 ++++----- .../lib/ctx_profile/CtxInstrProfiling.h | 118 ++---------------- compiler-rt/test/ctx_profile/CMakeLists.txt | 22 ++++ .../TestCases/check-same-ctx-node.test | 5 + compiler-rt/test/ctx_profile/lit.cfg.py | 31 +++++ .../test/ctx_profile/lit.site.cfg.py.in | 14 +++ compiler-rt/test/lit.common.cfg.py | 6 + llvm/lib/ProfileData/CtxInstrContextNode.h | 116 +++++++++++++++++ 10 files changed, 354 insertions(+), 133 deletions(-) create mode 100644 compiler-rt/lib/ctx_profile/CtxInstrContextNode.h create mode 100644 compiler-rt/test/ctx_profile/TestCases/check-same-ctx-node.test create mode 100644 compiler-rt/test/ctx_profile/lit.cfg.py create mode 100644 compiler-rt/test/ctx_profile/lit.site.cfg.py.in create mode 100644 llvm/lib/ProfileData/CtxInstrContextNode.h diff --git a/compiler-rt/lib/ctx_profile/CMakeLists.txt b/compiler-rt/lib/ctx_profile/CMakeLists.txt index 80e71acc38f8..1fa70594b28a 100644 --- a/compiler-rt/lib/ctx_profile/CMakeLists.txt +++ b/compiler-rt/lib/ctx_profile/CMakeLists.txt @@ -5,6 +5,7 @@ set(CTX_PROFILE_SOURCES ) set(CTX_PROFILE_HEADERS + CtxInstrContextNode.h CtxInstrProfiling.h ) diff --git a/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h b/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h new file mode 100644 index 000000000000..1627bdfffd08 --- /dev/null +++ b/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h @@ -0,0 +1,116 @@ +//===--- CtxInstrContextNode.h - Contextual Profile Node --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +//============================================================================== +// +// NOTE! +// llvm/lib/ProfileData/CtxInstrContextNode.h and +// compiler-rt/lib/ctx_profile/CtxInstrContextNode.h +// must be exact copies of eachother +// +// compiler-rt creates these objects as part of the instrumentation runtime for +// contextual profiling. LLVM only consumes them to convert a contextual tree +// to a bitstream. +// +//============================================================================== + +/// The contextual profile is a directed tree where each node has one parent. A +/// node (ContextNode) corresponds to a function activation. The root of the +/// tree is at a function that was marked as entrypoint to the compiler. A node +/// stores counter values for edges and a vector of subcontexts. These are the +/// contexts of callees. The index in the subcontext vector corresponds to the +/// index of the callsite (as was instrumented via llvm.instrprof.callsite). At +/// that index we find a linked list, potentially empty, of ContextNodes. Direct +/// calls will have 0 or 1 values in the linked list, but indirect callsites may +/// have more. +/// +/// The ContextNode has a fixed sized header describing it - the GUID of the +/// function, the size of the counter and callsite vectors. It is also an +/// (intrusive) linked list for the purposes of the indirect call case above. +/// +/// Allocation is expected to happen on an Arena. The allocation lays out inline +/// the counter and subcontexts vectors. The class offers APIs to correctly +/// reference the latter. +/// +/// The layout is as follows: +/// +/// [[declared fields][counters vector][vector of ptrs to subcontexts]] +/// +/// See also documentation on the counters and subContexts members below. +/// +/// The structure of the ContextNode is known to LLVM, because LLVM needs to: +/// (1) increment counts, and +/// (2) form a GEP for the position in the subcontext list of a callsite +/// This means changes to LLVM contextual profile lowering and changes here +/// must be coupled. +/// Note: the header content isn't interesting to LLVM (other than its size) +/// +/// Part of contextual collection is the notion of "scratch contexts". These are +/// buffers that are "large enough" to allow for memory-safe acceses during +/// counter increments - meaning the counter increment code in LLVM doesn't need +/// to be concerned with memory safety. Their subcontexts never get populated, +/// though. The runtime code here produces and recognizes them. + +#ifndef LLVM_LIB_PROFILEDATA_CTXINSTRCONTEXTNODE_H +#define LLVM_LIB_PROFILEDATA_CTXINSTRCONTEXTNODE_H + +#include +#include + +namespace llvm { +namespace ctx_profile { +using GUID = uint64_t; + +class ContextNode final { + const GUID Guid; + ContextNode *const Next; + const uint32_t NrCounters; + const uint32_t NrCallsites; + +public: + ContextNode(GUID Guid, uint32_t NrCounters, uint32_t NrCallsites, + ContextNode *Next = nullptr) + : Guid(Guid), Next(Next), NrCounters(NrCounters), + NrCallsites(NrCallsites) {} + + static inline size_t getAllocSize(uint32_t NrCounters, uint32_t NrCallsites) { + return sizeof(ContextNode) + sizeof(uint64_t) * NrCounters + + sizeof(ContextNode *) * NrCallsites; + } + + // The counters vector starts right after the static header. + uint64_t *counters() { + ContextNode *addr_after = &(this[1]); + return reinterpret_cast(addr_after); + } + + uint32_t counters_size() const { return NrCounters; } + uint32_t callsites_size() const { return NrCallsites; } + + const uint64_t *counters() const { + return const_cast(this)->counters(); + } + + // The subcontexts vector starts right after the end of the counters vector. + ContextNode **subContexts() { + return reinterpret_cast(&(counters()[NrCounters])); + } + + ContextNode *const *subContexts() const { + return const_cast(this)->subContexts(); + } + + GUID guid() const { return Guid; } + ContextNode *next() const { return Next; } + + size_t size() const { return getAllocSize(NrCounters, NrCallsites); } + + uint64_t entrycount() const { return counters()[0]; } +}; +} // namespace ctx_profile +} // namespace llvm +#endif \ No newline at end of file diff --git a/compiler-rt/lib/ctx_profile/CtxInstrProfiling.cpp b/compiler-rt/lib/ctx_profile/CtxInstrProfiling.cpp index 68bfe5c1ae61..c5d167bf996a 100644 --- a/compiler-rt/lib/ctx_profile/CtxInstrProfiling.cpp +++ b/compiler-rt/lib/ctx_profile/CtxInstrProfiling.cpp @@ -90,6 +90,26 @@ bool validate(const ContextRoot *Root) { } return true; } + +inline ContextNode *allocContextNode(char *Place, GUID Guid, + uint32_t NrCounters, uint32_t NrCallsites, + ContextNode *Next = nullptr) { + assert(reinterpret_cast(Place) % ExpectedAlignment == 0); + return new (Place) ContextNode(Guid, NrCounters, NrCallsites, Next); +} + +void resetContextNode(ContextNode &Node) { + // FIXME(mtrofin): this is std::memset, which we can probably use if we + // drop/reduce the dependency on sanitizer_common. + for (uint32_t I = 0; I < Node.counters_size(); ++I) + Node.counters()[I] = 0; + for (uint32_t I = 0; I < Node.callsites_size(); ++I) + for (auto *Next = Node.subContexts()[I]; Next; Next = Next->next()) + resetContextNode(*Next); +} + +void onContextEnter(ContextNode &Node) { ++Node.counters()[0]; } + } // namespace // the scratch buffer - what we give when we can't produce a real context (the @@ -134,27 +154,9 @@ void Arena::freeArenaList(Arena *&A) { A = nullptr; } -inline ContextNode *ContextNode::alloc(char *Place, GUID Guid, - uint32_t NrCounters, - uint32_t NrCallsites, - ContextNode *Next) { - assert(reinterpret_cast(Place) % ExpectedAlignment == 0); - return new (Place) ContextNode(Guid, NrCounters, NrCallsites, Next); -} - -void ContextNode::reset() { - // FIXME(mtrofin): this is std::memset, which we can probably use if we - // drop/reduce the dependency on sanitizer_common. - for (uint32_t I = 0; I < NrCounters; ++I) - counters()[I] = 0; - for (uint32_t I = 0; I < NrCallsites; ++I) - for (auto *Next = subContexts()[I]; Next; Next = Next->Next) - Next->reset(); -} - // If this is the first time we hit a callsite with this (Guid) particular // callee, we need to allocate. -ContextNode *getCallsiteSlow(uint64_t Guid, ContextNode **InsertionPoint, +ContextNode *getCallsiteSlow(GUID Guid, ContextNode **InsertionPoint, uint32_t NrCounters, uint32_t NrCallsites) { auto AllocSize = ContextNode::getAllocSize(NrCounters, NrCallsites); auto *Mem = __llvm_ctx_profile_current_context_root->CurrentMem; @@ -169,8 +171,8 @@ ContextNode *getCallsiteSlow(uint64_t Guid, ContextNode **InsertionPoint, Mem->allocateNewArena(getArenaAllocSize(AllocSize), Mem); AllocPlace = Mem->tryBumpAllocate(AllocSize); } - auto *Ret = ContextNode::alloc(AllocPlace, Guid, NrCounters, NrCallsites, - *InsertionPoint); + auto *Ret = allocContextNode(AllocPlace, Guid, NrCounters, NrCallsites, + *InsertionPoint); *InsertionPoint = Ret; return Ret; } @@ -224,7 +226,7 @@ ContextNode *__llvm_ctx_profile_get_context(void *Callee, GUID Guid, "Context: %p, Asked: %lu %u %u, Got: %lu %u %u \n", Ret, Guid, NrCallsites, NrCounters, Ret->guid(), Ret->callsites_size(), Ret->counters_size()); - Ret->onEntry(); + onContextEnter(*Ret); return Ret; } @@ -241,8 +243,8 @@ void setupContext(ContextRoot *Root, GUID Guid, uint32_t NrCounters, auto *M = Arena::allocateNewArena(getArenaAllocSize(Needed)); Root->FirstMemBlock = M; Root->CurrentMem = M; - Root->FirstNode = ContextNode::alloc(M->tryBumpAllocate(Needed), Guid, - NrCounters, NrCallsites); + Root->FirstNode = allocContextNode(M->tryBumpAllocate(Needed), Guid, + NrCounters, NrCallsites); AllContextRoots.PushBack(Root); } @@ -254,7 +256,7 @@ ContextNode *__llvm_ctx_profile_start_context( } if (Root->Taken.TryLock()) { __llvm_ctx_profile_current_context_root = Root; - Root->FirstNode->onEntry(); + onContextEnter(*Root->FirstNode); return Root->FirstNode; } // If this thread couldn't take the lock, return scratch context. @@ -281,13 +283,13 @@ void __llvm_ctx_profile_start_collection() { for (auto *Mem = Root->FirstMemBlock; Mem; Mem = Mem->next()) ++NrMemUnits; - Root->FirstNode->reset(); + resetContextNode(*Root->FirstNode); } __sanitizer::Printf("[ctxprof] Initial NrMemUnits: %zu \n", NrMemUnits); } -bool __llvm_ctx_profile_fetch( - void *Data, bool (*Writer)(void *W, const __ctx_profile::ContextNode &)) { +bool __llvm_ctx_profile_fetch(void *Data, + bool (*Writer)(void *W, const ContextNode &)) { assert(Writer); __sanitizer::GenericScopedLock<__sanitizer::SpinMutex> Lock( &AllContextsMutex); diff --git a/compiler-rt/lib/ctx_profile/CtxInstrProfiling.h b/compiler-rt/lib/ctx_profile/CtxInstrProfiling.h index 8c4be5d8a23a..69ce796b71e3 100644 --- a/compiler-rt/lib/ctx_profile/CtxInstrProfiling.h +++ b/compiler-rt/lib/ctx_profile/CtxInstrProfiling.h @@ -9,11 +9,14 @@ #ifndef CTX_PROFILE_CTXINSTRPROFILING_H_ #define CTX_PROFILE_CTXINSTRPROFILING_H_ +#include "CtxInstrContextNode.h" #include "sanitizer_common/sanitizer_mutex.h" #include +using namespace llvm::ctx_profile; + namespace __ctx_profile { -using GUID = uint64_t; + static constexpr size_t ExpectedAlignment = 8; // We really depend on this, see further below. We currently support x86_64. // When we want to support other archs, we need to trace the places Alignment is @@ -62,99 +65,6 @@ private: // it to be thus aligned. static_assert(alignof(Arena) == ExpectedAlignment); -/// The contextual profile is a directed tree where each node has one parent. A -/// node (ContextNode) corresponds to a function activation. The root of the -/// tree is at a function that was marked as entrypoint to the compiler. A node -/// stores counter values for edges and a vector of subcontexts. These are the -/// contexts of callees. The index in the subcontext vector corresponds to the -/// index of the callsite (as was instrumented via llvm.instrprof.callsite). At -/// that index we find a linked list, potentially empty, of ContextNodes. Direct -/// calls will have 0 or 1 values in the linked list, but indirect callsites may -/// have more. -/// -/// The ContextNode has a fixed sized header describing it - the GUID of the -/// function, the size of the counter and callsite vectors. It is also an -/// (intrusive) linked list for the purposes of the indirect call case above. -/// -/// Allocation is expected to happen on an Arena. The allocation lays out inline -/// the counter and subcontexts vectors. The class offers APIs to correctly -/// reference the latter. -/// -/// The layout is as follows: -/// -/// [[declared fields][counters vector][vector of ptrs to subcontexts]] -/// -/// See also documentation on the counters and subContexts members below. -/// -/// The structure of the ContextNode is known to LLVM, because LLVM needs to: -/// (1) increment counts, and -/// (2) form a GEP for the position in the subcontext list of a callsite -/// This means changes to LLVM contextual profile lowering and changes here -/// must be coupled. -/// Note: the header content isn't interesting to LLVM (other than its size) -/// -/// Part of contextual collection is the notion of "scratch contexts". These are -/// buffers that are "large enough" to allow for memory-safe acceses during -/// counter increments - meaning the counter increment code in LLVM doesn't need -/// to be concerned with memory safety. Their subcontexts never get populated, -/// though. The runtime code here produces and recognizes them. -class ContextNode final { - const GUID Guid; - ContextNode *const Next; - const uint32_t NrCounters; - const uint32_t NrCallsites; - -public: - ContextNode(GUID Guid, uint32_t NrCounters, uint32_t NrCallsites, - ContextNode *Next = nullptr) - : Guid(Guid), Next(Next), NrCounters(NrCounters), - NrCallsites(NrCallsites) {} - static inline ContextNode *alloc(char *Place, GUID Guid, uint32_t NrCounters, - uint32_t NrCallsites, - ContextNode *Next = nullptr); - - static inline size_t getAllocSize(uint32_t NrCounters, uint32_t NrCallsites) { - return sizeof(ContextNode) + sizeof(uint64_t) * NrCounters + - sizeof(ContextNode *) * NrCallsites; - } - - // The counters vector starts right after the static header. - uint64_t *counters() { - ContextNode *addr_after = &(this[1]); - return reinterpret_cast(addr_after); - } - - uint32_t counters_size() const { return NrCounters; } - uint32_t callsites_size() const { return NrCallsites; } - - const uint64_t *counters() const { - return const_cast(this)->counters(); - } - - // The subcontexts vector starts right after the end of the counters vector. - ContextNode **subContexts() { - return reinterpret_cast(&(counters()[NrCounters])); - } - - ContextNode *const *subContexts() const { - return const_cast(this)->subContexts(); - } - - GUID guid() const { return Guid; } - ContextNode *next() { return Next; } - - size_t size() const { return getAllocSize(NrCounters, NrCallsites); } - - void reset(); - - // since we go through the runtime to get a context back to LLVM, in the entry - // basic block, might as well handle incrementing the entry basic block - // counter. - void onEntry() { ++counters()[0]; } - - uint64_t entrycount() const { return counters()[0]; } -}; - // Verify maintenance to ContextNode doesn't change this invariant, which makes // sure the inlined vectors are appropriately aligned. static_assert(alignof(ContextNode) == ExpectedAlignment); @@ -219,8 +129,7 @@ extern "C" { extern __thread void *volatile __llvm_ctx_profile_expected_callee[2]; /// TLS where LLVM stores the pointer inside a caller's subcontexts vector that /// corresponds to the callsite being lowered. -extern __thread __ctx_profile::ContextNode * - *volatile __llvm_ctx_profile_callsite[2]; +extern __thread ContextNode **volatile __llvm_ctx_profile_callsite[2]; // __llvm_ctx_profile_current_context_root is exposed for unit testing, // othwerise it's only used internally by compiler-rt/ctx_profile. @@ -229,10 +138,9 @@ extern __thread __ctx_profile::ContextRoot /// called by LLVM in the entry BB of a "entry point" function. The returned /// pointer may be "tainted" - its LSB set to 1 - to indicate it's scratch. -__ctx_profile::ContextNode * -__llvm_ctx_profile_start_context(__ctx_profile::ContextRoot *Root, - __ctx_profile::GUID Guid, uint32_t Counters, - uint32_t Callsites); +ContextNode *__llvm_ctx_profile_start_context(__ctx_profile::ContextRoot *Root, + GUID Guid, uint32_t Counters, + uint32_t Callsites); /// paired with __llvm_ctx_profile_start_context, and called at the exit of the /// entry point function. @@ -240,9 +148,9 @@ void __llvm_ctx_profile_release_context(__ctx_profile::ContextRoot *Root); /// called for any other function than entry points, in the entry BB of such /// function. Same consideration about LSB of returned value as .._start_context -__ctx_profile::ContextNode * -__llvm_ctx_profile_get_context(void *Callee, __ctx_profile::GUID Guid, - uint32_t NrCounters, uint32_t NrCallsites); +ContextNode *__llvm_ctx_profile_get_context(void *Callee, GUID Guid, + uint32_t NrCounters, + uint32_t NrCallsites); /// Prepares for collection. Currently this resets counter values but preserves /// internal context tree structure. @@ -257,7 +165,7 @@ void __llvm_ctx_profile_free(); /// The Writer's first parameter plays the role of closure for Writer, and is /// what the caller of __llvm_ctx_profile_fetch passes as the Data parameter. /// The second parameter is the root of a context tree. -bool __llvm_ctx_profile_fetch( - void *Data, bool (*Writer)(void *, const __ctx_profile::ContextNode &)); +bool __llvm_ctx_profile_fetch(void *Data, + bool (*Writer)(void *, const ContextNode &)); } #endif // CTX_PROFILE_CTXINSTRPROFILING_H_ diff --git a/compiler-rt/test/ctx_profile/CMakeLists.txt b/compiler-rt/test/ctx_profile/CMakeLists.txt index 23c6fb16ed1f..371f1a2dcbb0 100644 --- a/compiler-rt/test/ctx_profile/CMakeLists.txt +++ b/compiler-rt/test/ctx_profile/CMakeLists.txt @@ -2,6 +2,28 @@ set(CTX_PROFILE_LIT_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}) set(CTX_PROFILE_TESTSUITES) +macro(get_bits_for_arch arch bits) + if (${arch} MATCHES "x86_64") + set(${bits} 64) + else() + message(FATAL_ERROR "Unexpected target architecture: ${arch}") + endif() +endmacro() + +set(CTX_PROFILE_TEST_DEPS ${SANITIZER_COMMON_LIT_TEST_DEPS} ctx_profile) + +foreach(arch ${CTX_PROFILE_SUPPORTED_ARCH}) + set(CTX_PROFILE_TEST_TARGET_ARCH ${arch}) + string(TOLOWER "-${arch}-${OS_NAME}" CTX_PROFILE_TEST_CONFIG_SUFFIX) + string(TOUPPER ${arch} ARCH_UPPER_CASE) + set(CONFIG_NAME ${ARCH_UPPER_CASE}${OS_NAME}Config) + configure_lit_site_cfg( + ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.py.in + ${CMAKE_CURRENT_BINARY_DIR}/${CONFIG_NAME}/lit.site.cfg.py + ) + list(APPEND CTX_PROFILE_TESTSUITES ${CMAKE_CURRENT_BINARY_DIR}/${CONFIG_NAME}) +endforeach() + # Add unit tests. if(COMPILER_RT_INCLUDE_TESTS) foreach(arch ${CTX_PROFILE_SUPPORTED_ARCH}) diff --git a/compiler-rt/test/ctx_profile/TestCases/check-same-ctx-node.test b/compiler-rt/test/ctx_profile/TestCases/check-same-ctx-node.test new file mode 100644 index 000000000000..37d36dbb9379 --- /dev/null +++ b/compiler-rt/test/ctx_profile/TestCases/check-same-ctx-node.test @@ -0,0 +1,5 @@ +; +; NOTE: if this test fails, please make sure the two files are identical copies +; of eachother. +; +; RUN: diff %crt_src/lib/ctx_profile/CtxInstrContextNode.h %llvm_src/lib/ProfileData/CtxInstrContextNode.h diff --git a/compiler-rt/test/ctx_profile/lit.cfg.py b/compiler-rt/test/ctx_profile/lit.cfg.py new file mode 100644 index 000000000000..a56dabb8ebeb --- /dev/null +++ b/compiler-rt/test/ctx_profile/lit.cfg.py @@ -0,0 +1,31 @@ +# -*- Python -*- + +import os +import platform +import re + +import lit.formats + +# Only run the tests on supported OSs. +if config.host_os not in ["Linux"]: + config.unsupported = True + + +def get_required_attr(config, attr_name): + attr_value = getattr(config, attr_name, None) + if attr_value == None: + lit_config.fatal( + "No attribute %r in test configuration! You may need to run " + "tests from your build directory or add this attribute " + "to lit.site.cfg.py " % attr_name + ) + return attr_value + + +# Setup config name. +config.name = "CtxProfile" + config.name_suffix + +# Setup source root. +config.test_source_root = os.path.dirname(__file__) +# Default test suffixes. +config.suffixes = [".c", ".cpp", ".test"] diff --git a/compiler-rt/test/ctx_profile/lit.site.cfg.py.in b/compiler-rt/test/ctx_profile/lit.site.cfg.py.in new file mode 100644 index 000000000000..e8df42d097d8 --- /dev/null +++ b/compiler-rt/test/ctx_profile/lit.site.cfg.py.in @@ -0,0 +1,14 @@ +@LIT_SITE_CFG_IN_HEADER@ + +# Tool-specific config options. +config.name_suffix = "@CTX_PROFILE_TEST_CONFIG_SUFFIX@" +config.target_cflags = "@CTX_PROFILE_TEST_TARGET_CFLAGS@" +config.clang = "@CTX_PROFILE_TEST_TARGET_CC@" +config.bits = "@CTX_PROFILE_TEST_BITS@" +config.target_arch = "@CTX_PROFILE_TEST_TARGET_ARCH@" + +# Load common config for all compiler-rt lit tests. +lit_config.load_config(config, "@COMPILER_RT_BINARY_DIR@/test/lit.common.configured") + +# Load tool-specific config that would do the real work. +lit_config.load_config(config, "@CTX_PROFILE_LIT_SOURCE_DIR@/lit.cfg.py") diff --git a/compiler-rt/test/lit.common.cfg.py b/compiler-rt/test/lit.common.cfg.py index 28f126a11b16..fae1d1686e56 100644 --- a/compiler-rt/test/lit.common.cfg.py +++ b/compiler-rt/test/lit.common.cfg.py @@ -987,3 +987,9 @@ if config.compiler_id == "GNU": gcc_dir = os.path.dirname(config.clang) libasan_dir = os.path.join(gcc_dir, "..", "lib" + config.bits) push_dynamic_library_lookup_path(config, libasan_dir) + + +# Help tests that make sure certain files are in-sync between compiler-rt and +# llvm. +config.substitutions.append(("%crt_src", config.compiler_rt_src_root)) +config.substitutions.append(("%llvm_src", config.llvm_src_root)) diff --git a/llvm/lib/ProfileData/CtxInstrContextNode.h b/llvm/lib/ProfileData/CtxInstrContextNode.h new file mode 100644 index 000000000000..1627bdfffd08 --- /dev/null +++ b/llvm/lib/ProfileData/CtxInstrContextNode.h @@ -0,0 +1,116 @@ +//===--- CtxInstrContextNode.h - Contextual Profile Node --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +//============================================================================== +// +// NOTE! +// llvm/lib/ProfileData/CtxInstrContextNode.h and +// compiler-rt/lib/ctx_profile/CtxInstrContextNode.h +// must be exact copies of eachother +// +// compiler-rt creates these objects as part of the instrumentation runtime for +// contextual profiling. LLVM only consumes them to convert a contextual tree +// to a bitstream. +// +//============================================================================== + +/// The contextual profile is a directed tree where each node has one parent. A +/// node (ContextNode) corresponds to a function activation. The root of the +/// tree is at a function that was marked as entrypoint to the compiler. A node +/// stores counter values for edges and a vector of subcontexts. These are the +/// contexts of callees. The index in the subcontext vector corresponds to the +/// index of the callsite (as was instrumented via llvm.instrprof.callsite). At +/// that index we find a linked list, potentially empty, of ContextNodes. Direct +/// calls will have 0 or 1 values in the linked list, but indirect callsites may +/// have more. +/// +/// The ContextNode has a fixed sized header describing it - the GUID of the +/// function, the size of the counter and callsite vectors. It is also an +/// (intrusive) linked list for the purposes of the indirect call case above. +/// +/// Allocation is expected to happen on an Arena. The allocation lays out inline +/// the counter and subcontexts vectors. The class offers APIs to correctly +/// reference the latter. +/// +/// The layout is as follows: +/// +/// [[declared fields][counters vector][vector of ptrs to subcontexts]] +/// +/// See also documentation on the counters and subContexts members below. +/// +/// The structure of the ContextNode is known to LLVM, because LLVM needs to: +/// (1) increment counts, and +/// (2) form a GEP for the position in the subcontext list of a callsite +/// This means changes to LLVM contextual profile lowering and changes here +/// must be coupled. +/// Note: the header content isn't interesting to LLVM (other than its size) +/// +/// Part of contextual collection is the notion of "scratch contexts". These are +/// buffers that are "large enough" to allow for memory-safe acceses during +/// counter increments - meaning the counter increment code in LLVM doesn't need +/// to be concerned with memory safety. Their subcontexts never get populated, +/// though. The runtime code here produces and recognizes them. + +#ifndef LLVM_LIB_PROFILEDATA_CTXINSTRCONTEXTNODE_H +#define LLVM_LIB_PROFILEDATA_CTXINSTRCONTEXTNODE_H + +#include +#include + +namespace llvm { +namespace ctx_profile { +using GUID = uint64_t; + +class ContextNode final { + const GUID Guid; + ContextNode *const Next; + const uint32_t NrCounters; + const uint32_t NrCallsites; + +public: + ContextNode(GUID Guid, uint32_t NrCounters, uint32_t NrCallsites, + ContextNode *Next = nullptr) + : Guid(Guid), Next(Next), NrCounters(NrCounters), + NrCallsites(NrCallsites) {} + + static inline size_t getAllocSize(uint32_t NrCounters, uint32_t NrCallsites) { + return sizeof(ContextNode) + sizeof(uint64_t) * NrCounters + + sizeof(ContextNode *) * NrCallsites; + } + + // The counters vector starts right after the static header. + uint64_t *counters() { + ContextNode *addr_after = &(this[1]); + return reinterpret_cast(addr_after); + } + + uint32_t counters_size() const { return NrCounters; } + uint32_t callsites_size() const { return NrCallsites; } + + const uint64_t *counters() const { + return const_cast(this)->counters(); + } + + // The subcontexts vector starts right after the end of the counters vector. + ContextNode **subContexts() { + return reinterpret_cast(&(counters()[NrCounters])); + } + + ContextNode *const *subContexts() const { + return const_cast(this)->subContexts(); + } + + GUID guid() const { return Guid; } + ContextNode *next() const { return Next; } + + size_t size() const { return getAllocSize(NrCounters, NrCallsites); } + + uint64_t entrycount() const { return counters()[0]; } +}; +} // namespace ctx_profile +} // namespace llvm +#endif \ No newline at end of file -- GitLab From 0fd017ce43875283ecce55f18f721f47ba37a920 Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Thu, 9 May 2024 17:30:46 -0700 Subject: [PATCH 217/328] [nfc][ctx_profile] Move `CtxInstrContextNode.h` in `include` Follow-up from PR #91669. --- compiler-rt/lib/ctx_profile/CtxInstrContextNode.h | 4 ++-- .../test/ctx_profile/TestCases/check-same-ctx-node.test | 2 +- llvm/{lib => include/llvm}/ProfileData/CtxInstrContextNode.h | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) rename llvm/{lib => include/llvm}/ProfileData/CtxInstrContextNode.h (97%) diff --git a/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h b/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h index 1627bdfffd08..a916f197aa14 100644 --- a/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h +++ b/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h @@ -55,8 +55,8 @@ /// to be concerned with memory safety. Their subcontexts never get populated, /// though. The runtime code here produces and recognizes them. -#ifndef LLVM_LIB_PROFILEDATA_CTXINSTRCONTEXTNODE_H -#define LLVM_LIB_PROFILEDATA_CTXINSTRCONTEXTNODE_H +#ifndef LLVM_PROFILEDATA_CTXINSTRCONTEXTNODE_H +#define LLVM_PROFILEDATA_CTXINSTRCONTEXTNODE_H #include #include diff --git a/compiler-rt/test/ctx_profile/TestCases/check-same-ctx-node.test b/compiler-rt/test/ctx_profile/TestCases/check-same-ctx-node.test index 37d36dbb9379..4ad7b23d458f 100644 --- a/compiler-rt/test/ctx_profile/TestCases/check-same-ctx-node.test +++ b/compiler-rt/test/ctx_profile/TestCases/check-same-ctx-node.test @@ -2,4 +2,4 @@ ; NOTE: if this test fails, please make sure the two files are identical copies ; of eachother. ; -; RUN: diff %crt_src/lib/ctx_profile/CtxInstrContextNode.h %llvm_src/lib/ProfileData/CtxInstrContextNode.h +; RUN: diff %crt_src/lib/ctx_profile/CtxInstrContextNode.h %llvm_src/include/llvm/ProfileData/CtxInstrContextNode.h diff --git a/llvm/lib/ProfileData/CtxInstrContextNode.h b/llvm/include/llvm/ProfileData/CtxInstrContextNode.h similarity index 97% rename from llvm/lib/ProfileData/CtxInstrContextNode.h rename to llvm/include/llvm/ProfileData/CtxInstrContextNode.h index 1627bdfffd08..a916f197aa14 100644 --- a/llvm/lib/ProfileData/CtxInstrContextNode.h +++ b/llvm/include/llvm/ProfileData/CtxInstrContextNode.h @@ -55,8 +55,8 @@ /// to be concerned with memory safety. Their subcontexts never get populated, /// though. The runtime code here produces and recognizes them. -#ifndef LLVM_LIB_PROFILEDATA_CTXINSTRCONTEXTNODE_H -#define LLVM_LIB_PROFILEDATA_CTXINSTRCONTEXTNODE_H +#ifndef LLVM_PROFILEDATA_CTXINSTRCONTEXTNODE_H +#define LLVM_PROFILEDATA_CTXINSTRCONTEXTNODE_H #include #include -- GitLab From db78ee0cb82669302a5e0f18a15fd53346a73823 Mon Sep 17 00:00:00 2001 From: alx32 <103613512+alx32@users.noreply.github.com> Date: Thu, 9 May 2024 17:56:46 -0700 Subject: [PATCH 218/328] [lld-macho] Fix address sanitizer for category merging (#91680) FIxing the address sanitizer issue reported in https://github.com/llvm/llvm-project/pull/91548 . The problem comes from the assignment `auto bodyData = newSectionData` which defaults to `SmallVector data = newSectionData` - which actually creates a copy of the data, placed on the stack. By explicitly using `ArrayRef` instead, we make sure that the original copy is used. We also change the assignment in `ObjcCategoryMerger::newStringData` from `auto` to `SmallVector &` to make it explicit. --- lld/MachO/ObjC.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lld/MachO/ObjC.cpp b/lld/MachO/ObjC.cpp index 96ec646095be..9d1612beae87 100644 --- a/lld/MachO/ObjC.cpp +++ b/lld/MachO/ObjC.cpp @@ -1148,7 +1148,7 @@ void ObjcCategoryMerger::generateCatListForNonErasedCategories( assert(nonErasedCatBody && "Failed to relocate non-deleted category"); // Allocate data for the new __objc_catlist slot - auto bodyData = newSectionData(target->wordSize); + llvm::ArrayRef bodyData = newSectionData(target->wordSize); // We mark the __objc_catlist slot as belonging to the same file as the // category @@ -1279,7 +1279,7 @@ void ObjcCategoryMerger::doCleanup() { generatedSectionData.clear(); } StringRef ObjcCategoryMerger::newStringData(const char *str) { uint32_t len = strlen(str); uint32_t bufSize = len + 1; - auto &data = newSectionData(bufSize); + SmallVector &data = newSectionData(bufSize); char *strData = reinterpret_cast(data.data()); // Copy the string chars and null-terminator memcpy(strData, str, bufSize); -- GitLab From d24eaef92525d03b4b64c7b4acd07197bdfb57cc Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Fri, 10 May 2024 10:01:23 +0800 Subject: [PATCH 219/328] [RISCV] Sink vector select splat operands (#91554) vmerge.vxm allows us to splat the true operand of a select, so sink it where possible to reduce vector register pressure. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 1 + .../CodeGen/RISCV/rvv/sink-splat-operands.ll | 17 ++++++++--------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 00a97d15db3e..e0937989a6a4 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -2019,6 +2019,7 @@ bool RISCVTargetLowering::canSplatOperand(unsigned Opcode, int Operand) const { case Instruction::SDiv: case Instruction::URem: case Instruction::SRem: + case Instruction::Select: return Operand == 1; default: return false; diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll index 6e902e79896b..618672344fe7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll @@ -5427,19 +5427,18 @@ for.cond.cleanup: ; preds = %vector.body define void @sink_splat_select(ptr nocapture %a, i32 signext %x) { ; CHECK-LABEL: sink_splat_select: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lui a2, 1 +; CHECK-NEXT: add a2, a0, a2 +; CHECK-NEXT: li a3, 42 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; CHECK-NEXT: vmv.v.x v8, a1 -; CHECK-NEXT: lui a1, 1 -; CHECK-NEXT: add a1, a0, a1 -; CHECK-NEXT: li a2, 42 ; CHECK-NEXT: .LBB117_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vle32.v v9, (a0) -; CHECK-NEXT: vmseq.vx v0, v9, a2 -; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0 -; CHECK-NEXT: vse32.v v9, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmseq.vx v0, v8, a3 +; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a0, a0, 16 -; CHECK-NEXT: bne a0, a1, .LBB117_1 +; CHECK-NEXT: bne a0, a2, .LBB117_1 ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: ret entry: -- GitLab From 427beff2ad274f38f9de682f48f550cdcf5fc505 Mon Sep 17 00:00:00 2001 From: Kareem Ergawy Date: Fri, 10 May 2024 04:20:43 +0200 Subject: [PATCH 220/328] [OpenMP][MLIR] Add `private` clause to `omp.target` (#91202) --- mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 6 +- mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp | 58 +++++++++++++++++-- mlir/test/Dialect/OpenMP/invalid.mlir | 2 +- mlir/test/Dialect/OpenMP/ops.mlir | 40 ++++++++++++- 4 files changed, 98 insertions(+), 8 deletions(-) diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td index a40676d071e6..a641588eaa8d 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td @@ -1787,7 +1787,10 @@ def TargetOp : OpenMP_Op<"target", [IsolatedFromAbove, MapClauseOwningOpInterfac UnitAttr:$nowait, Variadic:$is_device_ptr, Variadic:$has_device_addr, - Variadic:$map_operands); + Variadic:$map_operands, + Variadic:$private_vars, + OptionalAttr:$privatizers); + let regions = (region AnyRegion:$region); let builders = [ @@ -1802,6 +1805,7 @@ def TargetOp : OpenMP_Op<"target", [IsolatedFromAbove, MapClauseOwningOpInterfac | `is_device_ptr` `(` $is_device_ptr `:` type($is_device_ptr) `)` | `has_device_addr` `(` $has_device_addr `:` type($has_device_addr) `)` | `map_entries` `(` custom($map_operands, type($map_operands)) `)` + | `private` `(` custom($private_vars, type($private_vars), $privatizers) `)` | `depend` `(` custom($depend_vars, type($depend_vars), $depends) `)` ) $region attr-dict }]; diff --git a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp index 0799090cdea9..e016a326ecc7 100644 --- a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp +++ b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp @@ -470,13 +470,17 @@ static void printClauseWithRegionArgs(OpAsmPrinter &p, Operation *op, ValueRange argsSubrange, StringRef clauseName, ValueRange operands, TypeRange types, ArrayAttr symbols) { - p << clauseName << "("; + if (!clauseName.empty()) + p << clauseName << "("; + llvm::interleaveComma( llvm::zip_equal(symbols, operands, argsSubrange, types), p, [&p](auto t) { auto [sym, op, arg, type] = t; p << sym << " " << op << " -> " << arg << " : " << type; }); - p << ") "; + + if (!clauseName.empty()) + p << ") "; } static ParseResult parseParallelRegion( @@ -1048,6 +1052,49 @@ static void printMapEntries(OpAsmPrinter &p, Operation *op, } } +static ParseResult parsePrivateList( + OpAsmParser &parser, + SmallVectorImpl &privateOperands, + SmallVectorImpl &privateOperandTypes, ArrayAttr &privatizerSymbols) { + SmallVector privateSymRefs; + SmallVector regionPrivateArgs; + + if (failed(parser.parseCommaSeparatedList([&]() { + if (parser.parseAttribute(privateSymRefs.emplace_back()) || + parser.parseOperand(privateOperands.emplace_back()) || + parser.parseArrow() || + parser.parseArgument(regionPrivateArgs.emplace_back()) || + parser.parseColonType(privateOperandTypes.emplace_back())) + return failure(); + return success(); + }))) + return failure(); + + SmallVector privateSymAttrs(privateSymRefs.begin(), + privateSymRefs.end()); + privatizerSymbols = ArrayAttr::get(parser.getContext(), privateSymAttrs); + + return success(); +} + +static void printPrivateList(OpAsmPrinter &p, Operation *op, + ValueRange privateVarOperands, + TypeRange privateVarTypes, + ArrayAttr privatizerSymbols) { + // TODO: Remove target-specific logic from this function. + auto targetOp = mlir::dyn_cast(op); + assert(targetOp); + + auto ®ion = op->getRegion(0); + auto *argsBegin = region.front().getArguments().begin(); + MutableArrayRef argsSubrange(argsBegin + targetOp.getMapOperands().size(), + argsBegin + targetOp.getMapOperands().size() + + privateVarTypes.size()); + printClauseWithRegionArgs( + p, op, argsSubrange, /*clauseName=*/llvm::StringRef{}, privateVarOperands, + privateVarTypes, privatizerSymbols); +} + static void printCaptureType(OpAsmPrinter &p, Operation *op, VariableCaptureKindAttr mapCaptureType) { std::string typeCapStr; @@ -1256,13 +1303,14 @@ void TargetOp::build(OpBuilder &builder, OperationState &state, const TargetClauseOps &clauses) { MLIRContext *ctx = builder.getContext(); // TODO Store clauses in op: allocateVars, allocatorVars, inReductionVars, - // inReductionDeclSymbols, privateVars, privatizers, reductionVars, - // reductionByRefAttr, reductionDeclSymbols. + // inReductionDeclSymbols, reductionVars, reductionByRefAttr, + // reductionDeclSymbols. TargetOp::build( builder, state, clauses.ifVar, clauses.deviceVar, clauses.threadLimitVar, makeArrayAttr(ctx, clauses.dependTypeAttrs), clauses.dependVars, clauses.nowaitAttr, clauses.isDevicePtrVars, clauses.hasDeviceAddrVars, - clauses.mapVars); + clauses.mapVars, clauses.privateVars, + makeArrayAttr(ctx, clauses.privatizers)); } LogicalResult TargetOp::verify() { diff --git a/mlir/test/Dialect/OpenMP/invalid.mlir b/mlir/test/Dialect/OpenMP/invalid.mlir index 511e7d396c68..138c2c9d418d 100644 --- a/mlir/test/Dialect/OpenMP/invalid.mlir +++ b/mlir/test/Dialect/OpenMP/invalid.mlir @@ -2087,7 +2087,7 @@ func.func @omp_target_depend(%data_var: memref) { // expected-error @below {{op expected as many depend values as depend variables}} "omp.target"(%data_var) ({ "omp.terminator"() : () -> () - }) {depends = [], operandSegmentSizes = array} : (memref) -> () + }) {depends = [], operandSegmentSizes = array} : (memref) -> () "func.return"() : () -> () } diff --git a/mlir/test/Dialect/OpenMP/ops.mlir b/mlir/test/Dialect/OpenMP/ops.mlir index 60fc10f9d64b..828c9d2c3b84 100644 --- a/mlir/test/Dialect/OpenMP/ops.mlir +++ b/mlir/test/Dialect/OpenMP/ops.mlir @@ -737,7 +737,7 @@ func.func @omp_target(%if_cond : i1, %device : si32, %num_threads : i32, %devic "omp.target"(%if_cond, %device, %num_threads) ({ // CHECK: omp.terminator omp.terminator - }) {nowait, operandSegmentSizes = array} : ( i1, si32, i32 ) -> () + }) {nowait, operandSegmentSizes = array} : ( i1, si32, i32 ) -> () // Test with optional map clause. // CHECK: %[[MAP_A:.*]] = omp.map.info var_ptr(%[[VAL_1:.*]] : memref, tensor) map_clauses(tofrom) capture(ByRef) -> memref {name = ""} @@ -2550,3 +2550,41 @@ func.func @parallel_op_reduction_and_private(%priv_var: !llvm.ptr, %priv_var2: ! } return } + +// CHECK-LABEL: omp_target_private +func.func @omp_target_private(%map1: memref, %map2: memref, %priv_var: !llvm.ptr) -> () { + %mapv1 = omp.map.info var_ptr(%map1 : memref, tensor) map_clauses(tofrom) capture(ByRef) -> memref {name = ""} + %mapv2 = omp.map.info var_ptr(%map2 : memref, tensor) map_clauses(exit_release_or_enter_alloc) capture(ByRef) -> memref {name = ""} + + // CHECK: omp.target + // CHECK-SAME: private( + // CHECK-SAME: @x.privatizer %{{[^[:space:]]+}} -> %[[PRIV_ARG:[^[:space:]]+]] + // CHECK-SAME: : !llvm.ptr + // CHECK-SAME: ) + omp.target private(@x.privatizer %priv_var -> %priv_arg : !llvm.ptr) { + // CHECK: ^bb0(%[[PRIV_ARG]]: !llvm.ptr): + ^bb0(%priv_arg: !llvm.ptr): + omp.terminator + } + + // CHECK: omp.target + + // CHECK-SAME: map_entries( + // CHECK-SAME: %{{[^[:space:]]+}} -> %[[MAP1_ARG:[^[:space:]]+]], + // CHECK-SAME: %{{[^[:space:]]+}} -> %[[MAP2_ARG:[^[:space:]]+]] + // CHECK-SAME: : memref, memref + // CHECK-SAME: ) + + // CHECK-SAME: private( + // CHECK-SAME: @x.privatizer %{{[^[:space:]]+}} -> %[[PRIV_ARG:[^[:space:]]+]] + // CHECK-SAME: : !llvm.ptr + // CHECK-SAME: ) + omp.target map_entries(%mapv1 -> %arg0, %mapv2 -> %arg1 : memref, memref) private(@x.privatizer %priv_var -> %priv_arg : !llvm.ptr) { + // CHECK: ^bb0(%[[MAP1_ARG]]: memref, %[[MAP2_ARG]]: memref + // CHECK-SAME: , %[[PRIV_ARG]]: !llvm.ptr): + ^bb0(%arg0: memref, %arg1: memref, %priv_arg: !llvm.ptr): + omp.terminator + } + + return +} -- GitLab From e069bb7fd85b69abded27b44f33bf40a522ab9b6 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 9 May 2024 20:12:29 -0700 Subject: [PATCH 221/328] [RISCV] Use map::count instead of hasExtension in RISCVISAInfo::updateCombination. NFC hasExtension check isSupportedExtension before the map lookup. All of the extensions we check for in updateCombination should be valid extension names so we can bypass that to save some time. --- llvm/lib/TargetParser/RISCVISAInfo.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index c553e330a878..975cb5897b76 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -890,7 +890,7 @@ void RISCVISAInfo::updateCombination() { do { MadeChange = false; for (StringRef CombineExt : CombineIntoExts) { - if (hasExtension(CombineExt)) + if (Exts.count(CombineExt.str())) continue; // Look up the extension in the ImpliesExt table to find everything it @@ -899,7 +899,7 @@ void RISCVISAInfo::updateCombination() { std::end(ImpliedExts), CombineExt); bool HasAllRequiredFeatures = std::all_of( Range.first, Range.second, [&](const ImpliedExtsEntry &Implied) { - return hasExtension(Implied.ImpliedExt); + return Exts.count(Implied.ImpliedExt); }); if (HasAllRequiredFeatures) { auto Version = findDefaultVersion(CombineExt); -- GitLab From 0d31ac8893c382117abfb238f52c9736b2a38a8d Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 9 May 2024 20:29:25 -0700 Subject: [PATCH 222/328] workflows: Remove top-level permissions from release-tasks.yml (#91088) This is the recommend best practice and we also don't need write access for all jobs. --- .github/workflows/release-tasks.yml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/.github/workflows/release-tasks.yml b/.github/workflows/release-tasks.yml index 53da8662b020..29049ff01428 100644 --- a/.github/workflows/release-tasks.yml +++ b/.github/workflows/release-tasks.yml @@ -1,7 +1,7 @@ name: Release Task permissions: - contents: write + contents: read on: push: @@ -27,6 +27,8 @@ jobs: release-create: name: Create a New Release runs-on: ubuntu-latest + permissions: + contents: write # For creating the release. needs: validate-tag steps: @@ -55,6 +57,8 @@ jobs: release-doxygen: name: Build and Upload Release Doxygen + permissions: + contents: write needs: - validate-tag - release-create @@ -72,6 +76,8 @@ jobs: release-binaries: name: Build Release Binaries + permissions: + contents: write needs: - validate-tag - release-create -- GitLab From 720dfd94dfe83d8ce57ad3fe317563d7e1a9c602 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 9 May 2024 20:30:29 -0700 Subject: [PATCH 223/328] workflows: Fix missing GITHUB_TOKEN in release-doxygen.yml upload step (#91091) We were accidentally setting the GITHUB_TOKEN environment variable in the previous step. --- .github/workflows/release-doxygen.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/release-doxygen.yml b/.github/workflows/release-doxygen.yml index 5e322849a1d0..12c14bea52f6 100644 --- a/.github/workflows/release-doxygen.yml +++ b/.github/workflows/release-doxygen.yml @@ -56,12 +56,12 @@ jobs: pip3 install --user -r ./llvm/docs/requirements.txt - name: Build Doxygen - env: - GITHUB_TOKEN: ${{ github.token }} run: | ./llvm/utils/release/build-docs.sh -release "${{ inputs.release-version }}" -no-sphinx - name: Upload Doxygen if: env.upload + env: + GITHUB_TOKEN: ${{ github.token }} run: | ./llvm/utils/release/github-upload-release.py --token "$GITHUB_TOKEN" --release "${{ inputs.release-version }}" --user "${{ github.actor }}" upload --files ./*doxygen*.tar.xz -- GitLab From 181e2e8fb9efe6e8f3f7fc094516f125659b687c Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Thu, 9 May 2024 20:47:10 -0700 Subject: [PATCH 224/328] [nfc][memprof] Add missing license to `MemProfTest` (#91695) --- llvm/unittests/ProfileData/MemProfTest.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/llvm/unittests/ProfileData/MemProfTest.cpp b/llvm/unittests/ProfileData/MemProfTest.cpp index 40335d191ba7..8b97866e403f 100644 --- a/llvm/unittests/ProfileData/MemProfTest.cpp +++ b/llvm/unittests/ProfileData/MemProfTest.cpp @@ -1,3 +1,11 @@ +//===- unittests/Support/MemProfTest.cpp ----------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + #include "llvm/ProfileData/MemProf.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/MapVector.h" -- GitLab From 21be8182239a9c87a50071d122d5532037fd8305 Mon Sep 17 00:00:00 2001 From: Ryosuke Niwa Date: Thu, 9 May 2024 21:32:28 -0700 Subject: [PATCH 225/328] [analyzer] Support determining origins in a conditional operator in WebKit checkers. (#91143) This PR adds the support for determining the origin of a pointer in a conditional operator. Because such an expression can have two distinct origins each of which needs to be visited, this PR refactors tryToFindPtrOrigin to take a callback instead of returning a pair. The callback is called for the second operand and the third operand of the conditioanl operator (i.e. E2 and E3 in E1 ? E2 : E3). Also treat nullptr and integer literal as safe pointer origins in the local variable checker. --- .../Checkers/WebKit/ASTUtils.cpp | 23 ++++-- .../StaticAnalyzer/Checkers/WebKit/ASTUtils.h | 11 ++- .../WebKit/UncountedCallArgsChecker.cpp | 36 +++++---- .../WebKit/UncountedLocalVarsChecker.cpp | 73 +++++++++++-------- .../Analysis/Checkers/WebKit/call-args.cpp | 14 ++++ .../Checkers/WebKit/uncounted-local-vars.cpp | 18 +++++ 6 files changed, 113 insertions(+), 62 deletions(-) diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp index 5c49eecacc0f..f81db0e67d83 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp @@ -16,8 +16,9 @@ namespace clang { -std::pair -tryToFindPtrOrigin(const Expr *E, bool StopAtFirstRefCountedObj) { +bool tryToFindPtrOrigin( + const Expr *E, bool StopAtFirstRefCountedObj, + std::function callback) { while (E) { if (auto *tempExpr = dyn_cast(E)) { E = tempExpr->getSubExpr(); @@ -31,12 +32,18 @@ tryToFindPtrOrigin(const Expr *E, bool StopAtFirstRefCountedObj) { E = tempExpr->getSubExpr(); continue; } + if (auto *Expr = dyn_cast(E)) { + return tryToFindPtrOrigin(Expr->getTrueExpr(), StopAtFirstRefCountedObj, + callback) && + tryToFindPtrOrigin(Expr->getFalseExpr(), StopAtFirstRefCountedObj, + callback); + } if (auto *cast = dyn_cast(E)) { if (StopAtFirstRefCountedObj) { if (auto *ConversionFunc = dyn_cast_or_null(cast->getConversionFunction())) { if (isCtorOfRefCounted(ConversionFunc)) - return {E, true}; + return callback(E, true); } } // FIXME: This can give false "origin" that would lead to false negatives @@ -51,7 +58,7 @@ tryToFindPtrOrigin(const Expr *E, bool StopAtFirstRefCountedObj) { if (IsGetterOfRefCt && *IsGetterOfRefCt) { E = memberCall->getImplicitObjectArgument(); if (StopAtFirstRefCountedObj) { - return {E, true}; + return callback(E, true); } continue; } @@ -68,17 +75,17 @@ tryToFindPtrOrigin(const Expr *E, bool StopAtFirstRefCountedObj) { if (auto *callee = call->getDirectCallee()) { if (isCtorOfRefCounted(callee)) { if (StopAtFirstRefCountedObj) - return {E, true}; + return callback(E, true); E = call->getArg(0); continue; } if (isReturnValueRefCounted(callee)) - return {E, true}; + return callback(E, true); if (isSingleton(callee)) - return {E, true}; + return callback(E, true); if (isPtrConversion(callee)) { E = call->getArg(0); @@ -95,7 +102,7 @@ tryToFindPtrOrigin(const Expr *E, bool StopAtFirstRefCountedObj) { break; } // Some other expression. - return {E, false}; + return callback(E, false); } bool isASafeCallArg(const Expr *E) { diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h b/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h index e35ea4ef05dd..e972924e0c52 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h @@ -13,6 +13,7 @@ #include "llvm/ADT/APInt.h" #include "llvm/Support/Casting.h" +#include #include #include @@ -48,10 +49,12 @@ class Expr; /// represents ref-counted object during the traversal we return relevant /// sub-expression and true. /// -/// \returns subexpression that we traversed to and if \p -/// StopAtFirstRefCountedObj is true we also return whether we stopped early. -std::pair -tryToFindPtrOrigin(const clang::Expr *E, bool StopAtFirstRefCountedObj); +/// Calls \p callback with the subexpression that we traversed to and if \p +/// StopAtFirstRefCountedObj is true we also specify whether we stopped early. +/// Returns false if any of calls to callbacks returned false. Otherwise true. +bool tryToFindPtrOrigin( + const clang::Expr *E, bool StopAtFirstRefCountedObj, + std::function callback); /// For \p E referring to a ref-countable/-counted pointer/reference we return /// whether it's a safe call argument. Examples: function parameter or diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp index 9a178a690ff2..704c082a4d1d 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp @@ -126,25 +126,23 @@ public: } bool isPtrOriginSafe(const Expr *Arg) const { - std::pair ArgOrigin = - tryToFindPtrOrigin(Arg, true); - - // Temporary ref-counted object created as part of the call argument - // would outlive the call. - if (ArgOrigin.second) - return true; - - if (isa(ArgOrigin.first)) { - // foo(nullptr) - return true; - } - if (isa(ArgOrigin.first)) { - // FIXME: Check the value. - // foo(NULL) - return true; - } - - return isASafeCallArg(ArgOrigin.first); + return tryToFindPtrOrigin(Arg, /*StopAtFirstRefCountedObj=*/true, + [](const clang::Expr *ArgOrigin, bool IsSafe) { + if (IsSafe) + return true; + if (isa(ArgOrigin)) { + // foo(nullptr) + return true; + } + if (isa(ArgOrigin)) { + // FIXME: Check the value. + // foo(NULL) + return true; + } + if (isASafeCallArg(ArgOrigin)) + return true; + return false; + }); } bool shouldSkipCall(const CallExpr *CE) const { diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp index 98a73810b7af..0d9710a5e2d8 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp @@ -188,39 +188,50 @@ public: if (!InitExpr) return; // FIXME: later on we might warn on uninitialized vars too - const clang::Expr *const InitArgOrigin = - tryToFindPtrOrigin(InitExpr, /*StopAtFirstRefCountedObj=*/false) - .first; - if (!InitArgOrigin) + if (tryToFindPtrOrigin( + InitExpr, /*StopAtFirstRefCountedObj=*/false, + [&](const clang::Expr *InitArgOrigin, bool IsSafe) { + if (!InitArgOrigin) + return true; + + if (isa(InitArgOrigin)) + return true; + + if (isa(InitArgOrigin)) + return true; + + if (isa(InitArgOrigin)) + return true; + + if (auto *Ref = llvm::dyn_cast(InitArgOrigin)) { + if (auto *MaybeGuardian = + dyn_cast_or_null(Ref->getFoundDecl())) { + const auto *MaybeGuardianArgType = + MaybeGuardian->getType().getTypePtr(); + if (MaybeGuardianArgType) { + const CXXRecordDecl *const MaybeGuardianArgCXXRecord = + MaybeGuardianArgType->getAsCXXRecordDecl(); + if (MaybeGuardianArgCXXRecord) { + if (MaybeGuardian->isLocalVarDecl() && + (isRefCounted(MaybeGuardianArgCXXRecord) || + isRefcountedStringsHack(MaybeGuardian)) && + isGuardedScopeEmbeddedInGuardianScope( + V, MaybeGuardian)) + return true; + } + } + + // Parameters are guaranteed to be safe for the duration of + // the call by another checker. + if (isa(MaybeGuardian)) + return true; + } + } + + return false; + })) return; - if (isa(InitArgOrigin)) - return; - - if (auto *Ref = llvm::dyn_cast(InitArgOrigin)) { - if (auto *MaybeGuardian = - dyn_cast_or_null(Ref->getFoundDecl())) { - const auto *MaybeGuardianArgType = - MaybeGuardian->getType().getTypePtr(); - if (MaybeGuardianArgType) { - const CXXRecordDecl *const MaybeGuardianArgCXXRecord = - MaybeGuardianArgType->getAsCXXRecordDecl(); - if (MaybeGuardianArgCXXRecord) { - if (MaybeGuardian->isLocalVarDecl() && - (isRefCounted(MaybeGuardianArgCXXRecord) || - isRefcountedStringsHack(MaybeGuardian)) && - isGuardedScopeEmbeddedInGuardianScope(V, MaybeGuardian)) - return; - } - } - - // Parameters are guaranteed to be safe for the duration of the call - // by another checker. - if (isa(MaybeGuardian)) - return; - } - } - reportBug(V); } } diff --git a/clang/test/Analysis/Checkers/WebKit/call-args.cpp b/clang/test/Analysis/Checkers/WebKit/call-args.cpp index 45d900d4ba88..e1bee8a23a25 100644 --- a/clang/test/Analysis/Checkers/WebKit/call-args.cpp +++ b/clang/test/Analysis/Checkers/WebKit/call-args.cpp @@ -344,3 +344,17 @@ namespace cxx_member_operator_call { // expected-warning@-1{{Call argument for parameter 'bad' is uncounted and unsafe}} } } + +namespace call_with_ptr_on_ref { + Ref provideProtected(); + void bar(RefCountable* bad); + bool baz(); + void foo(bool v) { + bar(v ? nullptr : provideProtected().ptr()); + bar(baz() ? provideProtected().ptr() : nullptr); + bar(v ? provide() : provideProtected().ptr()); + // expected-warning@-1{{Call argument for parameter 'bad' is uncounted and unsafe}} + bar(v ? provideProtected().ptr() : provide()); + // expected-warning@-1{{Call argument for parameter 'bad' is uncounted and unsafe}} + } +} diff --git a/clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp b/clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp index 8da1dc557a5a..632a82eb0d8d 100644 --- a/clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp +++ b/clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp @@ -198,3 +198,21 @@ void system_header() { } } // ignore_system_headers + +namespace conditional_op { +RefCountable *provide_ref_ctnbl(); +bool bar(); + +void foo() { + RefCountable *a = bar() ? nullptr : provide_ref_ctnbl(); + // expected-warning@-1{{Local variable 'a' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + RefPtr b = provide_ref_ctnbl(); + { + RefCountable* c = bar() ? nullptr : b.get(); + c->method(); + RefCountable* d = bar() ? b.get() : nullptr; + d->method(); + } +} + +} // namespace conditional_op -- GitLab From 2c5f470da6ab313f7c6a1aa53fb40dbcbde338f1 Mon Sep 17 00:00:00 2001 From: Chaitanya Date: Fri, 10 May 2024 10:49:48 +0530 Subject: [PATCH 226/328] [AMDGPU] Move LDS utilities from amdgpu-lower-module-lds pass to AMDGPUMemoryUtils (#88002) This moves some of the utility methods from amdgpu-lower-module-lds pass to AMDGPUMemoryUtils. --- .../AMDGPU/AMDGPULowerModuleLDSPass.cpp | 186 +-------------- .../Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp | 215 +++++++++++++++++- .../Target/AMDGPU/Utils/AMDGPUMemoryUtils.h | 31 ++- 3 files changed, 245 insertions(+), 187 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp index c8bf9dd39e38..2c7163a77537 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp @@ -212,6 +212,7 @@ #define DEBUG_TYPE "amdgpu-lower-module-lds" using namespace llvm; +using namespace AMDGPU; namespace { @@ -234,17 +235,6 @@ cl::opt LoweringKindLoc( clEnumValN(LoweringKind::hybrid, "hybrid", "Lower via mixture of above strategies"))); -bool isKernelLDS(const Function *F) { - // Some weirdness here. AMDGPU::isKernelCC does not call into - // AMDGPU::isKernel with the calling conv, it instead calls into - // isModuleEntryFunction which returns true for more calling conventions - // than AMDGPU::isKernel does. There's a FIXME on AMDGPU::isKernel. - // There's also a test that checks that the LDS lowering does not hit on - // a graphics shader, denoted amdgpu_ps, so stay with the limited case. - // Putting LDS in the name of the function to draw attention to this. - return AMDGPU::isKernel(F->getCallingConv()); -} - template std::vector sortByName(std::vector &&V) { llvm::sort(V.begin(), V.end(), [](const auto *L, const auto *R) { return L->getName() < R->getName(); @@ -305,183 +295,9 @@ class AMDGPULowerModuleLDS { Decl, {}, {OperandBundleDefT("ExplicitUse", UseInstance)}); } - static bool eliminateConstantExprUsesOfLDSFromAllInstructions(Module &M) { - // Constants are uniqued within LLVM. A ConstantExpr referring to a LDS - // global may have uses from multiple different functions as a result. - // This pass specialises LDS variables with respect to the kernel that - // allocates them. - - // This is semantically equivalent to (the unimplemented as slow): - // for (auto &F : M.functions()) - // for (auto &BB : F) - // for (auto &I : BB) - // for (Use &Op : I.operands()) - // if (constantExprUsesLDS(Op)) - // replaceConstantExprInFunction(I, Op); - - SmallVector LDSGlobals; - for (auto &GV : M.globals()) - if (AMDGPU::isLDSVariableToLower(GV)) - LDSGlobals.push_back(&GV); - - return convertUsersOfConstantsToInstructions(LDSGlobals); - } - public: AMDGPULowerModuleLDS(const AMDGPUTargetMachine &TM_) : TM(TM_) {} - using FunctionVariableMap = DenseMap>; - - using VariableFunctionMap = DenseMap>; - - static void getUsesOfLDSByFunction(CallGraph const &CG, Module &M, - FunctionVariableMap &kernels, - FunctionVariableMap &functions) { - - // Get uses from the current function, excluding uses by called functions - // Two output variables to avoid walking the globals list twice - for (auto &GV : M.globals()) { - if (!AMDGPU::isLDSVariableToLower(GV)) { - continue; - } - - for (User *V : GV.users()) { - if (auto *I = dyn_cast(V)) { - Function *F = I->getFunction(); - if (isKernelLDS(F)) { - kernels[F].insert(&GV); - } else { - functions[F].insert(&GV); - } - } - } - } - } - - struct LDSUsesInfoTy { - FunctionVariableMap direct_access; - FunctionVariableMap indirect_access; - }; - - static LDSUsesInfoTy getTransitiveUsesOfLDS(CallGraph const &CG, Module &M) { - - FunctionVariableMap direct_map_kernel; - FunctionVariableMap direct_map_function; - getUsesOfLDSByFunction(CG, M, direct_map_kernel, direct_map_function); - - // Collect variables that are used by functions whose address has escaped - DenseSet VariablesReachableThroughFunctionPointer; - for (Function &F : M.functions()) { - if (!isKernelLDS(&F)) - if (F.hasAddressTaken(nullptr, - /* IgnoreCallbackUses */ false, - /* IgnoreAssumeLikeCalls */ false, - /* IgnoreLLVMUsed */ true, - /* IgnoreArcAttachedCall */ false)) { - set_union(VariablesReachableThroughFunctionPointer, - direct_map_function[&F]); - } - } - - auto functionMakesUnknownCall = [&](const Function *F) -> bool { - assert(!F->isDeclaration()); - for (const CallGraphNode::CallRecord &R : *CG[F]) { - if (!R.second->getFunction()) { - return true; - } - } - return false; - }; - - // Work out which variables are reachable through function calls - FunctionVariableMap transitive_map_function = direct_map_function; - - // If the function makes any unknown call, assume the worst case that it can - // access all variables accessed by functions whose address escaped - for (Function &F : M.functions()) { - if (!F.isDeclaration() && functionMakesUnknownCall(&F)) { - if (!isKernelLDS(&F)) { - set_union(transitive_map_function[&F], - VariablesReachableThroughFunctionPointer); - } - } - } - - // Direct implementation of collecting all variables reachable from each - // function - for (Function &Func : M.functions()) { - if (Func.isDeclaration() || isKernelLDS(&Func)) - continue; - - DenseSet seen; // catches cycles - SmallVector wip{&Func}; - - while (!wip.empty()) { - Function *F = wip.pop_back_val(); - - // Can accelerate this by referring to transitive map for functions that - // have already been computed, with more care than this - set_union(transitive_map_function[&Func], direct_map_function[F]); - - for (const CallGraphNode::CallRecord &R : *CG[F]) { - Function *ith = R.second->getFunction(); - if (ith) { - if (!seen.contains(ith)) { - seen.insert(ith); - wip.push_back(ith); - } - } - } - } - } - - // direct_map_kernel lists which variables are used by the kernel - // find the variables which are used through a function call - FunctionVariableMap indirect_map_kernel; - - for (Function &Func : M.functions()) { - if (Func.isDeclaration() || !isKernelLDS(&Func)) - continue; - - for (const CallGraphNode::CallRecord &R : *CG[&Func]) { - Function *ith = R.second->getFunction(); - if (ith) { - set_union(indirect_map_kernel[&Func], transitive_map_function[ith]); - } else { - set_union(indirect_map_kernel[&Func], - VariablesReachableThroughFunctionPointer); - } - } - } - - // Verify that we fall into one of 2 cases: - // - All variables are absolute: this is a re-run of the pass - // so we don't have anything to do. - // - No variables are absolute. - std::optional HasAbsoluteGVs; - for (auto &Map : {direct_map_kernel, indirect_map_kernel}) { - for (auto &[Fn, GVs] : Map) { - for (auto *GV : GVs) { - bool IsAbsolute = GV->isAbsoluteSymbolRef(); - if (HasAbsoluteGVs.has_value()) { - if (*HasAbsoluteGVs != IsAbsolute) { - report_fatal_error( - "Module cannot mix absolute and non-absolute LDS GVs"); - } - } else - HasAbsoluteGVs = IsAbsolute; - } - } - } - - // If we only had absolute GVs, we have nothing to do, return an empty - // result. - if (HasAbsoluteGVs && *HasAbsoluteGVs) - return {FunctionVariableMap(), FunctionVariableMap()}; - - return {std::move(direct_map_kernel), std::move(indirect_map_kernel)}; - } - struct LDSVariableReplacement { GlobalVariable *SGV = nullptr; DenseMap LDSVarsToConstantGEP; diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp index 79c359a57554..239e0ee70572 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp @@ -9,13 +9,16 @@ #include "AMDGPUMemoryUtils.h" #include "AMDGPU.h" #include "AMDGPUBaseInfo.h" +#include "llvm/ADT/SetOperations.h" #include "llvm/ADT/SmallSet.h" #include "llvm/Analysis/AliasAnalysis.h" +#include "llvm/Analysis/CallGraph.h" #include "llvm/Analysis/MemorySSA.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/IntrinsicsAMDGPU.h" +#include "llvm/IR/Operator.h" #include "llvm/IR/ReplaceConstant.h" #define DEBUG_TYPE "amdgpu-memory-utils" @@ -26,7 +29,7 @@ namespace llvm { namespace AMDGPU { -Align getAlign(DataLayout const &DL, const GlobalVariable *GV) { +Align getAlign(const DataLayout &DL, const GlobalVariable *GV) { return DL.getValueOrABITypeAlignment(GV->getPointerAlignment(DL), GV->getValueType()); } @@ -61,6 +64,216 @@ bool isLDSVariableToLower(const GlobalVariable &GV) { return true; } +bool eliminateConstantExprUsesOfLDSFromAllInstructions(Module &M) { + // Constants are uniqued within LLVM. A ConstantExpr referring to a LDS + // global may have uses from multiple different functions as a result. + // This pass specialises LDS variables with respect to the kernel that + // allocates them. + + // This is semantically equivalent to (the unimplemented as slow): + // for (auto &F : M.functions()) + // for (auto &BB : F) + // for (auto &I : BB) + // for (Use &Op : I.operands()) + // if (constantExprUsesLDS(Op)) + // replaceConstantExprInFunction(I, Op); + + SmallVector LDSGlobals; + for (auto &GV : M.globals()) + if (AMDGPU::isLDSVariableToLower(GV)) + LDSGlobals.push_back(&GV); + return convertUsersOfConstantsToInstructions(LDSGlobals); +} + +void getUsesOfLDSByFunction(const CallGraph &CG, Module &M, + FunctionVariableMap &kernels, + FunctionVariableMap &Functions) { + // Get uses from the current function, excluding uses by called Functions + // Two output variables to avoid walking the globals list twice + for (auto &GV : M.globals()) { + if (!AMDGPU::isLDSVariableToLower(GV)) + continue; + for (User *V : GV.users()) { + if (auto *I = dyn_cast(V)) { + Function *F = I->getFunction(); + if (isKernelLDS(F)) + kernels[F].insert(&GV); + else + Functions[F].insert(&GV); + } + } + } +} + +bool isKernelLDS(const Function *F) { + // Some weirdness here. AMDGPU::isKernelCC does not call into + // AMDGPU::isKernel with the calling conv, it instead calls into + // isModuleEntryFunction which returns true for more calling conventions + // than AMDGPU::isKernel does. There's a FIXME on AMDGPU::isKernel. + // There's also a test that checks that the LDS lowering does not hit on + // a graphics shader, denoted amdgpu_ps, so stay with the limited case. + // Putting LDS in the name of the function to draw attention to this. + return AMDGPU::isKernel(F->getCallingConv()); +} + +LDSUsesInfoTy getTransitiveUsesOfLDS(const CallGraph &CG, Module &M) { + + FunctionVariableMap DirectMapKernel; + FunctionVariableMap DirectMapFunction; + getUsesOfLDSByFunction(CG, M, DirectMapKernel, DirectMapFunction); + + // Collect variables that are used by functions whose address has escaped + DenseSet VariablesReachableThroughFunctionPointer; + for (Function &F : M.functions()) { + if (!isKernelLDS(&F)) + if (F.hasAddressTaken(nullptr, + /* IgnoreCallbackUses */ false, + /* IgnoreAssumeLikeCalls */ false, + /* IgnoreLLVMUsed */ true, + /* IgnoreArcAttachedCall */ false)) { + set_union(VariablesReachableThroughFunctionPointer, + DirectMapFunction[&F]); + } + } + + auto FunctionMakesUnknownCall = [&](const Function *F) -> bool { + assert(!F->isDeclaration()); + for (const CallGraphNode::CallRecord &R : *CG[F]) { + if (!R.second->getFunction()) + return true; + } + return false; + }; + + // Work out which variables are reachable through function calls + FunctionVariableMap TransitiveMapFunction = DirectMapFunction; + + // If the function makes any unknown call, assume the worst case that it can + // access all variables accessed by functions whose address escaped + for (Function &F : M.functions()) { + if (!F.isDeclaration() && FunctionMakesUnknownCall(&F)) { + if (!isKernelLDS(&F)) { + set_union(TransitiveMapFunction[&F], + VariablesReachableThroughFunctionPointer); + } + } + } + + // Direct implementation of collecting all variables reachable from each + // function + for (Function &Func : M.functions()) { + if (Func.isDeclaration() || isKernelLDS(&Func)) + continue; + + DenseSet seen; // catches cycles + SmallVector wip = {&Func}; + + while (!wip.empty()) { + Function *F = wip.pop_back_val(); + + // Can accelerate this by referring to transitive map for functions that + // have already been computed, with more care than this + set_union(TransitiveMapFunction[&Func], DirectMapFunction[F]); + + for (const CallGraphNode::CallRecord &R : *CG[F]) { + Function *Ith = R.second->getFunction(); + if (Ith) { + if (!seen.contains(Ith)) { + seen.insert(Ith); + wip.push_back(Ith); + } + } + } + } + } + + // DirectMapKernel lists which variables are used by the kernel + // find the variables which are used through a function call + FunctionVariableMap IndirectMapKernel; + + for (Function &Func : M.functions()) { + if (Func.isDeclaration() || !isKernelLDS(&Func)) + continue; + + for (const CallGraphNode::CallRecord &R : *CG[&Func]) { + Function *Ith = R.second->getFunction(); + if (Ith) { + set_union(IndirectMapKernel[&Func], TransitiveMapFunction[Ith]); + } else { + set_union(IndirectMapKernel[&Func], + VariablesReachableThroughFunctionPointer); + } + } + } + + // Verify that we fall into one of 2 cases: + // - All variables are absolute: this is a re-run of the pass + // so we don't have anything to do. + // - No variables are absolute. + std::optional HasAbsoluteGVs; + for (auto &Map : {DirectMapKernel, IndirectMapKernel}) { + for (auto &[Fn, GVs] : Map) { + for (auto *GV : GVs) { + bool IsAbsolute = GV->isAbsoluteSymbolRef(); + if (HasAbsoluteGVs.has_value()) { + if (*HasAbsoluteGVs != IsAbsolute) { + report_fatal_error( + "Module cannot mix absolute and non-absolute LDS GVs"); + } + } else + HasAbsoluteGVs = IsAbsolute; + } + } + } + + // If we only had absolute GVs, we have nothing to do, return an empty + // result. + if (HasAbsoluteGVs && *HasAbsoluteGVs) + return {FunctionVariableMap(), FunctionVariableMap()}; + + return {std::move(DirectMapKernel), std::move(IndirectMapKernel)}; +} + +void removeFnAttrFromReachable(CallGraph &CG, Function *KernelRoot, + StringRef FnAttr) { + KernelRoot->removeFnAttr(FnAttr); + + SmallVector WorkList = {CG[KernelRoot]->getFunction()}; + SmallPtrSet Visited; + bool SeenUnknownCall = false; + + while (!WorkList.empty()) { + Function *F = WorkList.pop_back_val(); + + for (auto &CallRecord : *CG[F]) { + if (!CallRecord.second) + continue; + + Function *Callee = CallRecord.second->getFunction(); + if (!Callee) { + if (!SeenUnknownCall) { + SeenUnknownCall = true; + + // If we see any indirect calls, assume nothing about potential + // targets. + // TODO: This could be refined to possible LDS global users. + for (auto &ExternalCallRecord : *CG.getExternalCallingNode()) { + Function *PotentialCallee = + ExternalCallRecord.second->getFunction(); + assert(PotentialCallee); + if (!isKernelLDS(PotentialCallee)) + PotentialCallee->removeFnAttr(FnAttr); + } + } + } else { + Callee->removeFnAttr(FnAttr); + if (Visited.insert(Callee).second) + WorkList.push_back(Callee); + } + } + } +} + bool isReallyAClobber(const Value *Ptr, MemoryDef *Def, AAResults *AA) { Instruction *DefInst = Def->getMemoryInst(); diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.h index e42b27f8e09e..4d3ad328e131 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.h @@ -9,6 +9,9 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUMEMORYUTILS_H #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUMEMORYUTILS_H +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseSet.h" + namespace llvm { struct Align; @@ -19,14 +22,40 @@ class LoadInst; class MemoryDef; class MemorySSA; class Value; +class Function; +class CallGraph; +class Module; namespace AMDGPU { -Align getAlign(DataLayout const &DL, const GlobalVariable *GV); +using FunctionVariableMap = DenseMap>; +using VariableFunctionMap = DenseMap>; + +Align getAlign(const DataLayout &DL, const GlobalVariable *GV); bool isDynamicLDS(const GlobalVariable &GV); bool isLDSVariableToLower(const GlobalVariable &GV); +struct LDSUsesInfoTy { + FunctionVariableMap direct_access; + FunctionVariableMap indirect_access; +}; + +bool eliminateConstantExprUsesOfLDSFromAllInstructions(Module &M); + +void getUsesOfLDSByFunction(const CallGraph &CG, Module &M, + FunctionVariableMap &kernels, + FunctionVariableMap &functions); + +bool isKernelLDS(const Function *F); + +LDSUsesInfoTy getTransitiveUsesOfLDS(const CallGraph &CG, Module &M); + +/// Strip FnAttr attribute from any functions where we may have +/// introduced its use. +void removeFnAttrFromReachable(CallGraph &CG, Function *KernelRoot, + StringRef FnAttr); + /// Given a \p Def clobbering a load from \p Ptr according to the MSSA check /// if this is actually a memory update or an artificial clobber to facilitate /// ordering constraints. -- GitLab From 87f3407856e61a73798af4e41b28bc33b5bf4ce6 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Fri, 10 May 2024 13:25:37 +0800 Subject: [PATCH 227/328] [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694) --- llvm/lib/TargetParser/Host.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index 834f4536f93a..c5156c6cb802 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -1802,7 +1802,8 @@ bool sys::getHostCPUFeatures(StringMap &Features) { Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); // AVX512 is only supported if the OS supports the context save for it. Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; - Features["evex512"] = Features["avx512f"]; + if (Features["avx512f"]) + Features["evex512"] = true; Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); -- GitLab From 06ad86361ab29d344a5e2e22903c2739743c77be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Danny=20M=C3=B6sch?= Date: Fri, 10 May 2024 07:56:35 +0200 Subject: [PATCH 228/328] [NFC] Prefer `str.resize(len)` over `str.substr(0, len)` (#91067) --- llvm/include/llvm/Analysis/DOTGraphTraitsPass.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/Analysis/DOTGraphTraitsPass.h b/llvm/include/llvm/Analysis/DOTGraphTraitsPass.h index da72fb511f82..7aea7a3b0f6d 100644 --- a/llvm/include/llvm/Analysis/DOTGraphTraitsPass.h +++ b/llvm/include/llvm/Analysis/DOTGraphTraitsPass.h @@ -87,13 +87,12 @@ private: }; static inline void shortenFileName(std::string &FN, unsigned char len = 250) { - - FN = FN.substr(0, len); - + if (FN.length() > len) + FN.resize(len); auto strLen = FN.length(); while (strLen > 0) { - if (auto it = nameObj.find(FN); it != nameObj.end()) { - FN = FN.substr(0, --len); + if (nameObj.find(FN) != nameObj.end()) { + FN.resize(--len); } else { nameObj.insert(FN); break; -- GitLab From 135d92f903161e66ff82ab846acfbc5015ef3096 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Thu, 9 May 2024 23:12:08 -0700 Subject: [PATCH 229/328] [Driver] Use StringRef::operator== instead of StringRef::equals (NFC) (#91698) I'm planning to remove StringRef::equals in favor of StringRef::operator==. - StringRef::operator==/!= outnumber StringRef::equals by a factor of 13 under clang/ in terms of their usage. - The elimination of StringRef::equals brings StringRef closer to std::string_view, which has operator== but not equals. - S == "foo" is more readable than S.equals("foo"), especially for !Long.Expression.equals("str") vs Long.Expression != "str". --- clang/lib/Driver/Driver.cpp | 6 +- clang/lib/Driver/ToolChains/AIX.cpp | 4 +- clang/lib/Driver/ToolChains/AMDGPU.cpp | 2 +- clang/lib/Driver/ToolChains/Clang.cpp | 66 +++++++++++----------- clang/lib/Driver/ToolChains/CommonArgs.cpp | 2 +- clang/lib/Driver/ToolChains/Flang.cpp | 13 ++--- 6 files changed, 45 insertions(+), 48 deletions(-) diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 114320f5d314..7b36d8e5084c 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -564,9 +564,9 @@ static llvm::Triple computeTargetTriple(const Driver &D, StringRef ObjectMode = *ObjectModeValue; llvm::Triple::ArchType AT = llvm::Triple::UnknownArch; - if (ObjectMode.equals("64")) { + if (ObjectMode == "64") { AT = Target.get64BitArchVariant().getArch(); - } else if (ObjectMode.equals("32")) { + } else if (ObjectMode == "32") { AT = Target.get32BitArchVariant().getArch(); } else { D.Diag(diag::err_drv_invalid_object_mode) << ObjectMode; @@ -6694,7 +6694,7 @@ llvm::StringRef clang::driver::getDriverMode(StringRef ProgName, return Opt.consume_front(OptName) ? Opt : ""; } -bool driver::IsClangCL(StringRef DriverMode) { return DriverMode.equals("cl"); } +bool driver::IsClangCL(StringRef DriverMode) { return DriverMode == "cl"; } llvm::Error driver::expandResponseFiles(SmallVectorImpl &Args, bool ClangCLMode, diff --git a/clang/lib/Driver/ToolChains/AIX.cpp b/clang/lib/Driver/ToolChains/AIX.cpp index aab98506adb9..85825e1ea65b 100644 --- a/clang/lib/Driver/ToolChains/AIX.cpp +++ b/clang/lib/Driver/ToolChains/AIX.cpp @@ -481,8 +481,8 @@ static void addTocDataOptions(const llvm::opt::ArgList &Args, // Currently only supported for small code model. if (TOCDataGloballyinEffect && - (Args.getLastArgValue(options::OPT_mcmodel_EQ).equals("large") || - Args.getLastArgValue(options::OPT_mcmodel_EQ).equals("medium"))) { + (Args.getLastArgValue(options::OPT_mcmodel_EQ) == "large" || + Args.getLastArgValue(options::OPT_mcmodel_EQ) == "medium")) { D.Diag(clang::diag::warn_drv_unsupported_tocdata); return; } diff --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp b/clang/lib/Driver/ToolChains/AMDGPU.cpp index 07965b487ea7..9ffea57b005d 100644 --- a/clang/lib/Driver/ToolChains/AMDGPU.cpp +++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp @@ -732,7 +732,7 @@ AMDGPUToolChain::TranslateArgs(const DerivedArgList &Args, StringRef BoundArch, checkTargetID(*DAL); - if (!Args.getLastArgValue(options::OPT_x).equals("cl")) + if (Args.getLastArgValue(options::OPT_x) != "cl") return DAL; // Phase 1 (.cl -> .bc) diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 775dc249999e..449eb9b2a965 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -1526,7 +1526,7 @@ static void CollectARMPACBTIOptions(const ToolChain &TC, const ArgList &Args, CmdArgs.push_back( Args.MakeArgString(Twine("-msign-return-address=") + Scope)); - if (!Scope.equals("none")) + if (Scope != "none") CmdArgs.push_back( Args.MakeArgString(Twine("-msign-return-address-key=") + Key)); if (BranchProtectionPAuthLR) @@ -1719,10 +1719,9 @@ void Clang::AddAArch64TargetArgs(const ArgList &Args, if (Arg *A = Args.getLastArg(options::OPT_msve_vector_bits_EQ)) { StringRef Val = A->getValue(); const Driver &D = getToolChain().getDriver(); - if (Val.equals("128") || Val.equals("256") || Val.equals("512") || - Val.equals("1024") || Val.equals("2048") || Val.equals("128+") || - Val.equals("256+") || Val.equals("512+") || Val.equals("1024+") || - Val.equals("2048+")) { + if (Val == "128" || Val == "256" || Val == "512" || Val == "1024" || + Val == "2048" || Val == "128+" || Val == "256+" || Val == "512+" || + Val == "1024+" || Val == "2048+") { unsigned Bits = 0; if (!Val.consume_back("+")) { bool Invalid = Val.getAsInteger(10, Bits); (void)Invalid; @@ -1736,7 +1735,7 @@ void Clang::AddAArch64TargetArgs(const ArgList &Args, CmdArgs.push_back( Args.MakeArgString("-mvscale-min=" + llvm::Twine(Bits / 128))); // Silently drop requests for vector-length agnostic code as it's implied. - } else if (!Val.equals("scalable")) + } else if (Val != "scalable") // Handle the unsupported values passed to msve-vector-bits. D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << Val; @@ -2098,7 +2097,7 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args, // If the value is "zvl", use MinVLen from march. Otherwise, try to parse // as integer as long as we have a MinVLen. unsigned Bits = 0; - if (Val.equals("zvl") && MinVLen >= llvm::RISCV::RVVBitsPerBlock) { + if (Val == "zvl" && MinVLen >= llvm::RISCV::RVVBitsPerBlock) { Bits = MinVLen; } else if (!Val.getAsInteger(10, Bits)) { // Only accept power of 2 values beteen RVVBitsPerBlock and 65536 that @@ -2115,7 +2114,7 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args, Args.MakeArgString("-mvscale-max=" + llvm::Twine(VScaleMin))); CmdArgs.push_back( Args.MakeArgString("-mvscale-min=" + llvm::Twine(VScaleMin))); - } else if (!Val.equals("scalable")) { + } else if (Val != "scalable") { // Handle the unsupported values passed to mrvv-vector-bits. D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << Val; @@ -2865,13 +2864,13 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, case options::OPT_fcomplex_arithmetic_EQ: { LangOptions::ComplexRangeKind RangeVal; StringRef Val = A->getValue(); - if (Val.equals("full")) + if (Val == "full") RangeVal = LangOptions::ComplexRangeKind::CX_Full; - else if (Val.equals("improved")) + else if (Val == "improved") RangeVal = LangOptions::ComplexRangeKind::CX_Improved; - else if (Val.equals("promoted")) + else if (Val == "promoted") RangeVal = LangOptions::ComplexRangeKind::CX_Promoted; - else if (Val.equals("basic")) + else if (Val == "basic") RangeVal = LangOptions::ComplexRangeKind::CX_Basic; else { D.Diag(diag::err_drv_unsupported_option_argument) @@ -2910,24 +2909,24 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, FPContract = "on"; StringRef Val = A->getValue(); - if (OFastEnabled && !Val.equals("fast")) { - // Only -ffp-model=fast is compatible with OFast, ignore. + if (OFastEnabled && Val != "fast") { + // Only -ffp-model=fast is compatible with OFast, ignore. D.Diag(clang::diag::warn_drv_overriding_option) << Args.MakeArgString("-ffp-model=" + Val) << "-Ofast"; break; } StrictFPModel = false; - if (!FPModel.empty() && !FPModel.equals(Val)) + if (!FPModel.empty() && FPModel != Val) D.Diag(clang::diag::warn_drv_overriding_option) << Args.MakeArgString("-ffp-model=" + FPModel) << Args.MakeArgString("-ffp-model=" + Val); - if (Val.equals("fast")) { + if (Val == "fast") { FPModel = Val; applyFastMath(); - } else if (Val.equals("precise")) { + } else if (Val == "precise") { FPModel = Val; FPContract = "on"; - } else if (Val.equals("strict")) { + } else if (Val == "strict") { StrictFPModel = true; FPExceptionBehavior = "strict"; FPModel = Val; @@ -2957,7 +2956,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, case options::OPT_fno_signed_zeros: SignedZeros = false; break; case options::OPT_ftrapping_math: if (!TrappingMathPresent && !FPExceptionBehavior.empty() && - !FPExceptionBehavior.equals("strict")) + FPExceptionBehavior != "strict") // Warn that previous value of option is overridden. D.Diag(clang::diag::warn_drv_overriding_option) << Args.MakeArgString("-ffp-exception-behavior=" + @@ -2969,7 +2968,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, break; case options::OPT_fno_trapping_math: if (!TrappingMathPresent && !FPExceptionBehavior.empty() && - !FPExceptionBehavior.equals("ignore")) + FPExceptionBehavior != "ignore") // Warn that previous value of option is overridden. D.Diag(clang::diag::warn_drv_overriding_option) << Args.MakeArgString("-ffp-exception-behavior=" + @@ -3008,8 +3007,8 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // Validate and pass through -ffp-contract option. case options::OPT_ffp_contract: { StringRef Val = A->getValue(); - if (Val.equals("fast") || Val.equals("on") || Val.equals("off") || - Val.equals("fast-honor-pragmas")) { + if (Val == "fast" || Val == "on" || Val == "off" || + Val == "fast-honor-pragmas") { FPContract = Val; LastSeenFfpContractOption = Val; } else @@ -3022,16 +3021,16 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, case options::OPT_ffp_exception_behavior_EQ: { StringRef Val = A->getValue(); if (!TrappingMathPresent && !FPExceptionBehavior.empty() && - !FPExceptionBehavior.equals(Val)) + FPExceptionBehavior != Val) // Warn that previous value of option is overridden. D.Diag(clang::diag::warn_drv_overriding_option) << Args.MakeArgString("-ffp-exception-behavior=" + FPExceptionBehavior) << Args.MakeArgString("-ffp-exception-behavior=" + Val); TrappingMath = TrappingMathPresent = false; - if (Val.equals("ignore") || Val.equals("maytrap")) + if (Val == "ignore" || Val == "maytrap") FPExceptionBehavior = Val; - else if (Val.equals("strict")) { + else if (Val == "strict") { FPExceptionBehavior = Val; TrappingMath = TrappingMathPresent = true; } else @@ -3043,8 +3042,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // Validate and pass through -ffp-eval-method option. case options::OPT_ffp_eval_method_EQ: { StringRef Val = A->getValue(); - if (Val.equals("double") || Val.equals("extended") || - Val.equals("source")) + if (Val == "double" || Val == "extended" || Val == "source") FPEvalMethod = Val; else D.Diag(diag::err_drv_unsupported_option_argument) @@ -3056,18 +3054,18 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, StringRef Val = A->getValue(); const llvm::Triple::ArchType Arch = TC.getArch(); if (Arch == llvm::Triple::x86 || Arch == llvm::Triple::x86_64) { - if (Val.equals("standard") || Val.equals("fast")) + if (Val == "standard" || Val == "fast") Float16ExcessPrecision = Val; // To make it GCC compatible, allow the value of "16" which // means disable excess precision, the same meaning than clang's // equivalent value "none". - else if (Val.equals("16")) + else if (Val == "16") Float16ExcessPrecision = "none"; else D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << Val; } else { - if (!(Val.equals("standard") || Val.equals("fast"))) + if (!(Val == "standard" || Val == "fast")) D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << Val; } @@ -3149,7 +3147,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // subsequent options conflict then emit warning diagnostic. if (HonorINFs && HonorNaNs && !AssociativeMath && !ReciprocalMath && SignedZeros && TrappingMath && RoundingFPMath && !ApproxFunc && - FPContract.equals("off")) + FPContract == "off") // OK: Current Arg doesn't conflict with -ffp-model=strict ; else { @@ -3195,7 +3193,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, if (TrappingMath) { // FP Exception Behavior is also set to strict - assert(FPExceptionBehavior.equals("strict")); + assert(FPExceptionBehavior == "strict"); } // The default is IEEE. @@ -3244,8 +3242,8 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, if (!HonorINFs && !HonorNaNs && !MathErrno && AssociativeMath && ApproxFunc && ReciprocalMath && !SignedZeros && !TrappingMath && !RoundingFPMath) { CmdArgs.push_back("-ffast-math"); - if (FPModel.equals("fast")) { - if (FPContract.equals("fast")) + if (FPModel == "fast") { + if (FPContract == "fast") // All set, do nothing. ; else if (FPContract.empty()) diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 6796b43a1550..71e993119436 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -346,7 +346,7 @@ void tools::addDirectoryList(const ArgList &Args, ArgStringList &CmdArgs, return; // Nothing to do. StringRef Name(ArgName); - if (Name.equals("-I") || Name.equals("-L") || Name.empty()) + if (Name == "-I" || Name == "-L" || Name.empty()) CombinedArg = true; StringRef Dirs(DirList); diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index 436a9c418a5f..d275528b6905 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -170,10 +170,9 @@ void Flang::AddAArch64TargetArgs(const ArgList &Args, if (Arg *A = Args.getLastArg(options::OPT_msve_vector_bits_EQ)) { StringRef Val = A->getValue(); const Driver &D = getToolChain().getDriver(); - if (Val.equals("128") || Val.equals("256") || Val.equals("512") || - Val.equals("1024") || Val.equals("2048") || Val.equals("128+") || - Val.equals("256+") || Val.equals("512+") || Val.equals("1024+") || - Val.equals("2048+")) { + if (Val == "128" || Val == "256" || Val == "512" || Val == "1024" || + Val == "2048" || Val == "128+" || Val == "256+" || Val == "512+" || + Val == "1024+" || Val == "2048+") { unsigned Bits = 0; if (!Val.consume_back("+")) { [[maybe_unused]] bool Invalid = Val.getAsInteger(10, Bits); @@ -187,7 +186,7 @@ void Flang::AddAArch64TargetArgs(const ArgList &Args, CmdArgs.push_back( Args.MakeArgString("-mvscale-min=" + llvm::Twine(Bits / 128))); // Silently drop requests for vector-length agnostic code as it's implied. - } else if (!Val.equals("scalable")) + } else if (Val != "scalable") // Handle the unsupported values passed to msve-vector-bits. D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << Val; @@ -214,7 +213,7 @@ void Flang::AddRISCVTargetArgs(const ArgList &Args, // If the value is "zvl", use MinVLen from march. Otherwise, try to parse // as integer as long as we have a MinVLen. unsigned Bits = 0; - if (Val.equals("zvl") && MinVLen >= llvm::RISCV::RVVBitsPerBlock) { + if (Val == "zvl" && MinVLen >= llvm::RISCV::RVVBitsPerBlock) { Bits = MinVLen; } else if (!Val.getAsInteger(10, Bits)) { // Only accept power of 2 values beteen RVVBitsPerBlock and 65536 that @@ -231,7 +230,7 @@ void Flang::AddRISCVTargetArgs(const ArgList &Args, Args.MakeArgString("-mvscale-max=" + llvm::Twine(VScaleMin))); CmdArgs.push_back( Args.MakeArgString("-mvscale-min=" + llvm::Twine(VScaleMin))); - } else if (!Val.equals("scalable")) { + } else if (Val != "scalable") { // Handle the unsupported values passed to mrvv-vector-bits. D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << Val; -- GitLab From e7e13c6ffec58fe67a23d173387e96d5ebb8f84b Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Fri, 10 May 2024 16:09:34 +1000 Subject: [PATCH 230/328] [ORC] Fix another error fall-through in EPCGenericDylibManager::lookupAsync. The early return added in this commit should have been added in cbf1535cc81. No test-case: This would require a deliberately injected failure in a remote-JIT test and we don't have the infrastructure for that at the moment. rdar://126772381 --- llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp b/llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp index 7c0d89012922..298bde46ab75 100644 --- a/llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp +++ b/llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp @@ -92,6 +92,7 @@ void EPCGenericDylibManager::lookupAsync(tpctypes::DylibHandle H, if (SerializationErr) { cantFail(Result.takeError()); Complete(std::move(SerializationErr)); + return; } Complete(std::move(Result)); }, -- GitLab From 0ebe48f068c0ca69f76ed68b621c9294acd75f76 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Fri, 10 May 2024 14:31:43 +0800 Subject: [PATCH 231/328] [RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701) This further splits off #91440 to inch RISCVInsertVSETVLI closer to post vector regalloc. As noted in #91440, most of the diffs are from moving vsetvli insertion after the vxrm/csr insertion passes, but these are getting conflated with the changes from moving to LiveIntervals. One idea was that we could try and remove some of these diffs by manually moving back the vsetvlis past the vxrm/csr instructions. But this meant having to touch up the LiveIntervals again which seemed to lead to even more diffs. This instead just moves RISCVInsertVSETVLI after RISCVInsertReadWriteCSR and RISCVInsertWriteVXRM so we can isolate those changes. --- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +- llvm/test/CodeGen/RISCV/O0-pipeline.ll | 2 +- llvm/test/CodeGen/RISCV/O3-pipeline.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/commutable.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll | 56 +-- llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll | 352 +++++++++--------- llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll | 32 +- .../CodeGen/RISCV/rvv/double-round-conv.ll | 32 +- .../RISCV/rvv/fixed-vectors-ceil-vp.ll | 38 +- .../CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 16 +- .../RISCV/rvv/fixed-vectors-floor-vp.ll | 38 +- .../RISCV/rvv/fixed-vectors-round-vp.ll | 38 +- .../RISCV/rvv/fixed-vectors-roundeven-vp.ll | 38 +- .../RISCV/rvv/fixed-vectors-roundtozero-vp.ll | 38 +- .../CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll | 38 +- .../CodeGen/RISCV/rvv/float-round-conv.ll | 48 +-- llvm/test/CodeGen/RISCV/rvv/floor-vp.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/frm-insert.ll | 84 ++--- .../test/CodeGen/RISCV/rvv/half-round-conv.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/masked-tama.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/round-vp.ll | 52 +-- llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll | 52 +-- llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll | 52 +-- .../rvv/rvv-peephole-vmerge-masked-vops.ll | 4 +- .../RISCV/rvv/rvv-peephole-vmerge-vops.ll | 14 +- .../CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll | 40 +- .../CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll | 40 +- llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll | 22 +- llvm/test/CodeGen/RISCV/rvv/vaadd.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vaaddu.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vasub.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vasubu.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vfadd.ll | 234 ++++++------ llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfdiv.ll | 234 ++++++------ llvm/test/CodeGen/RISCV/rvv/vfmacc.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfmadd.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfmsac.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfmsub.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfmul.ll | 234 ++++++------ llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll | 72 ++-- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll | 72 ++-- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll | 72 ++-- llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfrec7.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfredosum.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfredusum.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfwadd.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll | 244 ++++++------ llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll | 72 ++-- llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll | 72 ++-- llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwmul.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll | 88 ++--- llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll | 88 ++--- llvm/test/CodeGen/RISCV/rvv/vfwsub.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll | 244 ++++++------ llvm/test/CodeGen/RISCV/rvv/vnclip.ll | 180 ++++----- llvm/test/CodeGen/RISCV/rvv/vnclipu.ll | 180 ++++----- llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll | 160 ++++---- llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vxrm.mir | 6 +- 86 files changed, 4519 insertions(+), 4519 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index b79568539046..7b2dcadc4191 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -541,9 +541,9 @@ void RISCVPassConfig::addPreRegAlloc() { addPass(createRISCVPreRAExpandPseudoPass()); if (TM->getOptLevel() != CodeGenOptLevel::None) addPass(createRISCVMergeBaseOffsetOptPass()); - addPass(createRISCVInsertVSETVLIPass()); addPass(createRISCVInsertReadWriteCSRPass()); addPass(createRISCVInsertWriteVXRMPass()); + addPass(createRISCVInsertVSETVLIPass()); } void RISCVPassConfig::addFastRegAlloc() { diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll index 56bd4bd0c08f..c4a7f9562534 100644 --- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll @@ -40,9 +40,9 @@ ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions ; CHECK-NEXT: Local Stack Slot Allocation ; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass -; CHECK-NEXT: RISC-V Insert VSETVLI pass ; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass ; CHECK-NEXT: RISC-V Insert Write VXRM Pass +; CHECK-NEXT: RISC-V Insert VSETVLI pass ; CHECK-NEXT: Init Undef Pass ; CHECK-NEXT: Eliminate PHI nodes for register allocation ; CHECK-NEXT: Two-Address instruction pass diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll index 04b055f9b216..4a71d3276d26 100644 --- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll @@ -115,9 +115,9 @@ ; RV64-NEXT: RISC-V Optimize W Instructions ; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass ; CHECK-NEXT: RISC-V Merge Base Offset -; CHECK-NEXT: RISC-V Insert VSETVLI pass ; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass ; CHECK-NEXT: RISC-V Insert Write VXRM Pass +; CHECK-NEXT: RISC-V Insert VSETVLI pass ; CHECK-NEXT: Detect Dead Lanes ; CHECK-NEXT: Init Undef Pass ; CHECK-NEXT: Process Implicit Definitions diff --git a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll index 5b271606f08a..aa11e012af20 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll @@ -15,8 +15,8 @@ define @vp_ceil_vv_nxv1f16( %va, @vp_ceil_vv_nxv2f16( %va, @vp_ceil_vv_nxv4f16( %va, @vp_ceil_vv_nxv8f16( %va, @vp_ceil_vv_nxv16f16( %va, @vp_ceil_vv_nxv32f16( %va, @vp_ceil_vv_nxv1f32( %va, @vp_ceil_vv_nxv2f32( %va, @vp_ceil_vv_nxv4f32( %va, @vp_ceil_vv_nxv8f32( %va, @vp_ceil_vv_nxv16f32( %va, @vp_ceil_vv_nxv1f64( %va, @vp_ceil_vv_nxv2f64( %va, @vp_ceil_vv_nxv4f64( %va, @vp_ceil_vv_nxv7f64( %va, @vp_ceil_vv_nxv8f64( %va, @vp_ceil_vv_nxv16f64( %va, < ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a2, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a2 @@ -750,8 +750,8 @@ define @vp_ceil_vv_nxv16f64( %va, < ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/commutable.ll b/llvm/test/CodeGen/RISCV/rvv/commutable.ll index d94b529bac01..5bca2eeb3fdd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/commutable.ll +++ b/llvm/test/CodeGen/RISCV/rvv/commutable.ll @@ -720,8 +720,8 @@ declare @llvm.riscv.vaadd.nxv1i64.nxv1i64(, define @commutable_vaadd_vv( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: commutable_vaadd_vv: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 @@ -737,8 +737,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64( @commutable_vaadd_vv_masked( %0, %1, %mask, iXLen %2) { ; CHECK-LABEL: commutable_vaadd_vv_masked: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vaadd.vv v10, v8, v9, v0.t ; CHECK-NEXT: vaadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma @@ -755,8 +755,8 @@ declare @llvm.riscv.vaaddu.nxv1i64.nxv1i64( define @commutable_vaaddu_vv( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: commutable_vaaddu_vv: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 @@ -772,8 +772,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64( @commutable_vaaddu_vv_masked( %0, %1, %mask, iXLen %2) { ; CHECK-LABEL: commutable_vaaddu_vv_masked: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v10, v8, v9, v0.t ; CHECK-NEXT: vaaddu.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma @@ -790,8 +790,8 @@ declare @llvm.riscv.vsmul.nxv1i64.nxv1i64(, define @commutable_vsmul_vv( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: commutable_vsmul_vv: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 @@ -807,8 +807,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64( @commutable_vsmul_vv_masked( %0, %1, %mask, iXLen %2) { ; CHECK-LABEL: commutable_vsmul_vv_masked: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsmul.vv v10, v8, v9, v0.t ; CHECK-NEXT: vsmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll index d756cfcf7077..41ec102c34ef 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll @@ -806,8 +806,8 @@ define @ctlz_nxv1i32( %va) { ; ; CHECK-F-LABEL: ctlz_nxv1i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -878,8 +878,8 @@ define @ctlz_nxv2i32( %va) { ; ; CHECK-F-LABEL: ctlz_nxv2i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -950,8 +950,8 @@ define @ctlz_nxv4i32( %va) { ; ; CHECK-F-LABEL: ctlz_nxv4i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -1022,8 +1022,8 @@ define @ctlz_nxv8i32( %va) { ; ; CHECK-F-LABEL: ctlz_nxv8i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -1094,8 +1094,8 @@ define @ctlz_nxv16i32( %va) { ; ; CHECK-F-LABEL: ctlz_nxv16i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -1107,8 +1107,8 @@ define @ctlz_nxv16i32( %va) { ; ; CHECK-D-LABEL: ctlz_nxv16i32: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: vsrl.vi v8, v8, 23 ; CHECK-D-NEXT: li a1, 158 @@ -1234,8 +1234,8 @@ define @ctlz_nxv1i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32F-NEXT: vmv.v.x v9, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: vsrl.vi v8, v10, 23 ; RV32F-NEXT: vwsubu.wv v9, v9, v8 @@ -1262,8 +1262,8 @@ define @ctlz_nxv1i64( %va) { ; ; CHECK-D-LABEL: ctlz_nxv1i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -1390,8 +1390,8 @@ define @ctlz_nxv2i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32F-NEXT: vmv.v.x v10, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v8 ; RV32F-NEXT: vsrl.vi v8, v12, 23 ; RV32F-NEXT: vwsubu.wv v10, v10, v8 @@ -1418,8 +1418,8 @@ define @ctlz_nxv2i64( %va) { ; ; CHECK-D-LABEL: ctlz_nxv2i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -1546,8 +1546,8 @@ define @ctlz_nxv4i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32F-NEXT: vmv.v.x v12, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v16, v8 ; RV32F-NEXT: vsrl.vi v8, v16, 23 ; RV32F-NEXT: vwsubu.wv v12, v12, v8 @@ -1574,8 +1574,8 @@ define @ctlz_nxv4i64( %va) { ; ; CHECK-D-LABEL: ctlz_nxv4i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -1702,8 +1702,8 @@ define @ctlz_nxv8i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32F-NEXT: vmv.v.x v16, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v24, v8 ; RV32F-NEXT: vsrl.vi v8, v24, 23 ; RV32F-NEXT: vwsubu.wv v16, v16, v8 @@ -1730,8 +1730,8 @@ define @ctlz_nxv8i64( %va) { ; ; CHECK-D-LABEL: ctlz_nxv8i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -2497,8 +2497,8 @@ define @ctlz_zero_undef_nxv1i32( %va) { ; ; CHECK-F-LABEL: ctlz_zero_undef_nxv1i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -2564,8 +2564,8 @@ define @ctlz_zero_undef_nxv2i32( %va) { ; ; CHECK-F-LABEL: ctlz_zero_undef_nxv2i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -2631,8 +2631,8 @@ define @ctlz_zero_undef_nxv4i32( %va) { ; ; CHECK-F-LABEL: ctlz_zero_undef_nxv4i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -2698,8 +2698,8 @@ define @ctlz_zero_undef_nxv8i32( %va) { ; ; CHECK-F-LABEL: ctlz_zero_undef_nxv8i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -2765,8 +2765,8 @@ define @ctlz_zero_undef_nxv16i32( %va) { ; ; CHECK-F-LABEL: ctlz_zero_undef_nxv16i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -2776,8 +2776,8 @@ define @ctlz_zero_undef_nxv16i32( %va) { ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv16i32: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: vsrl.vi v8, v8, 23 ; CHECK-D-NEXT: li a1, 158 @@ -2900,8 +2900,8 @@ define @ctlz_zero_undef_nxv1i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32F-NEXT: vmv.v.x v9, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: vsrl.vi v8, v10, 23 ; RV32F-NEXT: vwsubu.wv v9, v9, v8 @@ -2923,8 +2923,8 @@ define @ctlz_zero_undef_nxv1i64( %va) { ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv1i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -3048,8 +3048,8 @@ define @ctlz_zero_undef_nxv2i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32F-NEXT: vmv.v.x v10, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v8 ; RV32F-NEXT: vsrl.vi v8, v12, 23 ; RV32F-NEXT: vwsubu.wv v10, v10, v8 @@ -3071,8 +3071,8 @@ define @ctlz_zero_undef_nxv2i64( %va) { ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv2i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -3196,8 +3196,8 @@ define @ctlz_zero_undef_nxv4i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32F-NEXT: vmv.v.x v12, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v16, v8 ; RV32F-NEXT: vsrl.vi v8, v16, 23 ; RV32F-NEXT: vwsubu.wv v12, v12, v8 @@ -3219,8 +3219,8 @@ define @ctlz_zero_undef_nxv4i64( %va) { ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv4i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -3345,8 +3345,8 @@ define @ctlz_zero_undef_nxv8i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32F-NEXT: vmv.v.x v8, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v24, v16 ; RV32F-NEXT: vsrl.vi v16, v24, 23 ; RV32F-NEXT: vwsubu.wv v8, v8, v16 @@ -3367,8 +3367,8 @@ define @ctlz_zero_undef_nxv8i64( %va) { ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv8i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll index 2a75e5ce7175..86086f5dc88f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll @@ -937,15 +937,15 @@ declare @llvm.vp.ctlz.nxv16i32(, i1 immar define @vp_ctlz_nxv16i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv16i32: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t -; CHECK-NEXT: li a1, 158 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 32 -; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 158 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 32 +; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i32: @@ -960,15 +960,15 @@ define @vp_ctlz_nxv16i32( %va, @vp_ctlz_nxv16i32_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv16i32_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vsrl.vi v8, v8, 23 -; CHECK-NEXT: li a1, 158 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: li a1, 32 -; CHECK-NEXT: vminu.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 158 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: li a0, 32 +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i32_unmasked: @@ -985,16 +985,16 @@ declare @llvm.vp.ctlz.nxv1i64(, i1 immarg, define @vp_ctlz_nxv1i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv1i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i64: @@ -1009,16 +1009,16 @@ define @vp_ctlz_nxv1i64( %va, @vp_ctlz_nxv1i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv1i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i64_unmasked: @@ -1035,16 +1035,16 @@ declare @llvm.vp.ctlz.nxv2i64(, i1 immarg, define @vp_ctlz_nxv2i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv2i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv2i64: @@ -1059,16 +1059,16 @@ define @vp_ctlz_nxv2i64( %va, @vp_ctlz_nxv2i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv2i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv2i64_unmasked: @@ -1085,16 +1085,16 @@ declare @llvm.vp.ctlz.nxv4i64(, i1 immarg, define @vp_ctlz_nxv4i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv4i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv4i64: @@ -1109,16 +1109,16 @@ define @vp_ctlz_nxv4i64( %va, @vp_ctlz_nxv4i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv4i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv4i64_unmasked: @@ -1135,16 +1135,16 @@ declare @llvm.vp.ctlz.nxv7i64(, i1 immarg, define @vp_ctlz_nxv7i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv7i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv7i64: @@ -1159,16 +1159,16 @@ define @vp_ctlz_nxv7i64( %va, @vp_ctlz_nxv7i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv7i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv7i64_unmasked: @@ -1185,16 +1185,16 @@ declare @llvm.vp.ctlz.nxv8i64(, i1 immarg, define @vp_ctlz_nxv8i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv8i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv8i64: @@ -1209,16 +1209,16 @@ define @vp_ctlz_nxv8i64( %va, @vp_ctlz_nxv8i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv8i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv8i64_unmasked: @@ -1244,10 +1244,10 @@ define @vp_ctlz_nxv16i64( %va, @vp_ctlz_nxv16i64( %va, @vp_ctlz_nxv16i64_unmasked( %va, i ; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: and a2, a3, a2 +; CHECK-NEXT: fsrmi a3, 1 ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a2, 1 ; CHECK-NEXT: vfcvt.f.xu.v v16, v16 -; CHECK-NEXT: fsrm a2 +; CHECK-NEXT: fsrm a3 ; CHECK-NEXT: li a2, 52 ; CHECK-NEXT: vsrl.vx v16, v16, a2 ; CHECK-NEXT: li a3, 1086 @@ -1315,13 +1315,13 @@ define @vp_ctlz_nxv16i64_unmasked( %va, i ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: .LBB47_2: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vsrl.vx v8, v8, a2 ; CHECK-NEXT: vrsub.vx v8, v8, a3 ; CHECK-NEXT: vminu.vx v8, v8, a4 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i64_unmasked: @@ -2198,13 +2198,13 @@ define @vp_ctlz_zero_undef_nxv8i32_unmasked( @vp_ctlz_zero_undef_nxv16i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i32: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t -; CHECK-NEXT: li a1, 158 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 158 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i32: @@ -2219,13 +2219,13 @@ define @vp_ctlz_zero_undef_nxv16i32( %va, define @vp_ctlz_zero_undef_nxv16i32_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i32_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vsrl.vi v8, v8, 23 -; CHECK-NEXT: li a1, 158 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 158 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i32_unmasked: @@ -2241,14 +2241,14 @@ define @vp_ctlz_zero_undef_nxv16i32_unmasked( @vp_ctlz_zero_undef_nxv1i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i64: @@ -2263,14 +2263,14 @@ define @vp_ctlz_zero_undef_nxv1i64( %va, @vp_ctlz_zero_undef_nxv1i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i64_unmasked: @@ -2286,14 +2286,14 @@ define @vp_ctlz_zero_undef_nxv1i64_unmasked( @vp_ctlz_zero_undef_nxv2i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i64: @@ -2308,14 +2308,14 @@ define @vp_ctlz_zero_undef_nxv2i64( %va, @vp_ctlz_zero_undef_nxv2i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i64_unmasked: @@ -2331,14 +2331,14 @@ define @vp_ctlz_zero_undef_nxv2i64_unmasked( @vp_ctlz_zero_undef_nxv4i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i64: @@ -2353,14 +2353,14 @@ define @vp_ctlz_zero_undef_nxv4i64( %va, @vp_ctlz_zero_undef_nxv4i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i64_unmasked: @@ -2376,14 +2376,14 @@ define @vp_ctlz_zero_undef_nxv4i64_unmasked( @vp_ctlz_zero_undef_nxv7i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv7i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv7i64: @@ -2398,14 +2398,14 @@ define @vp_ctlz_zero_undef_nxv7i64( %va, @vp_ctlz_zero_undef_nxv7i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv7i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv7i64_unmasked: @@ -2421,14 +2421,14 @@ define @vp_ctlz_zero_undef_nxv7i64_unmasked( @vp_ctlz_zero_undef_nxv8i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i64: @@ -2443,14 +2443,14 @@ define @vp_ctlz_zero_undef_nxv8i64( %va, @vp_ctlz_zero_undef_nxv8i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i64_unmasked: @@ -2474,10 +2474,10 @@ define @vp_ctlz_zero_undef_nxv16i64( %va, ; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: and a2, a3, a2 +; CHECK-NEXT: fsrmi a3, 1 ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a2, 1 ; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t -; CHECK-NEXT: fsrm a2 +; CHECK-NEXT: fsrm a3 ; CHECK-NEXT: li a2, 52 ; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t ; CHECK-NEXT: li a3, 1086 @@ -2486,13 +2486,13 @@ define @vp_ctlz_zero_undef_nxv16i64( %va, ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: .LBB94_2: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t ; CHECK-NEXT: vsrl.vx v8, v8, a2, v0.t ; CHECK-NEXT: vrsub.vx v8, v8, a3, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i64: @@ -2528,10 +2528,10 @@ define @vp_ctlz_zero_undef_nxv16i64_unmasked( @vp_ctlz_zero_undef_nxv16i64_unmasked( @cttz_nxv1i64( %va) { ; RV32F-NEXT: vmseq.vx v0, v8, zero ; RV32F-NEXT: vrsub.vi v9, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v9 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v9, v8 ; RV32F-NEXT: vsrl.vi v8, v9, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma @@ -1237,8 +1237,8 @@ define @cttz_nxv1i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64F-NEXT: vrsub.vi v9, v8, 0 ; RV64F-NEXT: vand.vv v9, v8, v9 -; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v10, v9 ; RV64F-NEXT: vsrl.vi v9, v10, 23 ; RV64F-NEXT: li a1, 127 @@ -1381,8 +1381,8 @@ define @cttz_nxv2i64( %va) { ; RV32F-NEXT: vmseq.vx v0, v8, zero ; RV32F-NEXT: vrsub.vi v10, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v10 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: vsrl.vi v8, v10, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma @@ -1399,8 +1399,8 @@ define @cttz_nxv2i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV64F-NEXT: vrsub.vi v10, v8, 0 ; RV64F-NEXT: vand.vv v10, v8, v10 -; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v12, v10 ; RV64F-NEXT: vsrl.vi v10, v12, 23 ; RV64F-NEXT: li a1, 127 @@ -1543,8 +1543,8 @@ define @cttz_nxv4i64( %va) { ; RV32F-NEXT: vmseq.vx v0, v8, zero ; RV32F-NEXT: vrsub.vi v12, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v12 -; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v8 ; RV32F-NEXT: vsrl.vi v8, v12, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma @@ -1561,8 +1561,8 @@ define @cttz_nxv4i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV64F-NEXT: vrsub.vi v12, v8, 0 ; RV64F-NEXT: vand.vv v12, v8, v12 -; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v16, v12 ; RV64F-NEXT: vsrl.vi v12, v16, 23 ; RV64F-NEXT: li a1, 127 @@ -1705,8 +1705,8 @@ define @cttz_nxv8i64( %va) { ; RV32F-NEXT: vmseq.vx v0, v8, zero ; RV32F-NEXT: vrsub.vi v16, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v16 -; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v16, v8 ; RV32F-NEXT: vsrl.vi v8, v16, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma @@ -1723,8 +1723,8 @@ define @cttz_nxv8i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV64F-NEXT: vrsub.vi v16, v8, 0 ; RV64F-NEXT: vand.vv v16, v8, v16 -; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v24, v16 ; RV64F-NEXT: vsrl.vi v16, v24, 23 ; RV64F-NEXT: li a1, 127 @@ -2892,8 +2892,8 @@ define @cttz_zero_undef_nxv1i64( %va) { ; RV32F-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32F-NEXT: vrsub.vi v9, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v9 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v9, v8 ; RV32F-NEXT: vsrl.vi v8, v9, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma @@ -2908,8 +2908,8 @@ define @cttz_zero_undef_nxv1i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64F-NEXT: vrsub.vi v9, v8, 0 ; RV64F-NEXT: vand.vv v8, v8, v9 -; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v9, v8 ; RV64F-NEXT: vsrl.vi v9, v9, 23 ; RV64F-NEXT: li a1, 127 @@ -3026,8 +3026,8 @@ define @cttz_zero_undef_nxv2i64( %va) { ; RV32F-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV32F-NEXT: vrsub.vi v10, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v10 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: vsrl.vi v8, v10, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma @@ -3042,8 +3042,8 @@ define @cttz_zero_undef_nxv2i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV64F-NEXT: vrsub.vi v10, v8, 0 ; RV64F-NEXT: vand.vv v8, v8, v10 -; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v10, v8 ; RV64F-NEXT: vsrl.vi v10, v10, 23 ; RV64F-NEXT: li a1, 127 @@ -3160,8 +3160,8 @@ define @cttz_zero_undef_nxv4i64( %va) { ; RV32F-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32F-NEXT: vrsub.vi v12, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v12 -; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v8 ; RV32F-NEXT: vsrl.vi v8, v12, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma @@ -3176,8 +3176,8 @@ define @cttz_zero_undef_nxv4i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV64F-NEXT: vrsub.vi v12, v8, 0 ; RV64F-NEXT: vand.vv v8, v8, v12 -; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v12, v8 ; RV64F-NEXT: vsrl.vi v12, v12, 23 ; RV64F-NEXT: li a1, 127 @@ -3294,8 +3294,8 @@ define @cttz_zero_undef_nxv8i64( %va) { ; RV32F-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV32F-NEXT: vrsub.vi v16, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v16 -; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v16, v8 ; RV32F-NEXT: vsrl.vi v8, v16, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma @@ -3310,8 +3310,8 @@ define @cttz_zero_undef_nxv8i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV64F-NEXT: vrsub.vi v16, v8, 0 ; RV64F-NEXT: vand.vv v8, v8, v16 -; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v16, v8 ; RV64F-NEXT: vsrl.vi v16, v16, 23 ; RV64F-NEXT: li a1, 127 diff --git a/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll index ee9ad097b442..8c63c2d4be8c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll @@ -677,8 +677,8 @@ define @ceil_nxv1f64_to_ui16( %x) { define @ceil_nxv1f64_to_si32( %x) { ; RV32-LABEL: ceil_nxv1f64_to_si32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV32-NEXT: vfncvt.x.f.w v9, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 @@ -686,8 +686,8 @@ define @ceil_nxv1f64_to_si32( %x) { ; ; RV64-LABEL: ceil_nxv1f64_to_si32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vfncvt.x.f.w v9, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 @@ -700,8 +700,8 @@ define @ceil_nxv1f64_to_si32( %x) { define @ceil_nxv1f64_to_ui32( %x) { ; RV32-LABEL: ceil_nxv1f64_to_ui32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV32-NEXT: vfncvt.xu.f.w v9, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 @@ -709,8 +709,8 @@ define @ceil_nxv1f64_to_ui32( %x) { ; ; RV64-LABEL: ceil_nxv1f64_to_ui32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vfncvt.xu.f.w v9, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 @@ -723,16 +723,16 @@ define @ceil_nxv1f64_to_ui32( %x) { define @ceil_nxv1f64_to_si64( %x) { ; RV32-LABEL: ceil_nxv1f64_to_si64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vfcvt.x.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv1f64_to_si64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-NEXT: vfcvt.x.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -744,16 +744,16 @@ define @ceil_nxv1f64_to_si64( %x) { define @ceil_nxv1f64_to_ui64( %x) { ; RV32-LABEL: ceil_nxv1f64_to_ui64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vfcvt.xu.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv1f64_to_ui64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-NEXT: vfcvt.xu.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -951,8 +951,8 @@ define @ceil_nxv4f64_to_ui16( %x) { define @ceil_nxv4f64_to_si32( %x) { ; RV32-LABEL: ceil_nxv4f64_to_si32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vfncvt.x.f.w v12, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv.v.v v8, v12 @@ -960,8 +960,8 @@ define @ceil_nxv4f64_to_si32( %x) { ; ; RV64-LABEL: ceil_nxv4f64_to_si32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vfncvt.x.f.w v12, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv.v.v v8, v12 @@ -974,8 +974,8 @@ define @ceil_nxv4f64_to_si32( %x) { define @ceil_nxv4f64_to_ui32( %x) { ; RV32-LABEL: ceil_nxv4f64_to_ui32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vfncvt.xu.f.w v12, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv.v.v v8, v12 @@ -983,8 +983,8 @@ define @ceil_nxv4f64_to_ui32( %x) { ; ; RV64-LABEL: ceil_nxv4f64_to_ui32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vfncvt.xu.f.w v12, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv.v.v v8, v12 @@ -997,16 +997,16 @@ define @ceil_nxv4f64_to_ui32( %x) { define @ceil_nxv4f64_to_si64( %x) { ; RV32-LABEL: ceil_nxv4f64_to_si64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vfcvt.x.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv4f64_to_si64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-NEXT: vfcvt.x.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -1018,16 +1018,16 @@ define @ceil_nxv4f64_to_si64( %x) { define @ceil_nxv4f64_to_ui64( %x) { ; RV32-LABEL: ceil_nxv4f64_to_ui64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vfcvt.xu.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv4f64_to_ui64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-NEXT: vfcvt.xu.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll index 5d024f140fd5..3e2af7e8267b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll @@ -19,8 +19,8 @@ define <2 x half> @vp_ceil_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: fsrmi a0, 3 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -38,8 +38,8 @@ define <2 x half> @vp_ceil_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 3 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -101,8 +101,8 @@ define <4 x half> @vp_ceil_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: fsrmi a0, 3 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -120,8 +120,8 @@ define <4 x half> @vp_ceil_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 3 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -183,8 +183,8 @@ define <8 x half> @vp_ceil_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: fsrmi a0, 3 +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -203,8 +203,8 @@ define <8 x half> @vp_ceil_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v9, v12, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 3 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -268,8 +268,8 @@ define <16 x half> @vp_ceil_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %e ; ZVFH-NEXT: vfabs.v v12, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: fsrmi a0, 3 +; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v10 ; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -289,8 +289,8 @@ define <16 x half> @vp_ceil_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %e ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v10, v16, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 3 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -353,8 +353,8 @@ define <2 x float> @vp_ceil_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -395,8 +395,8 @@ define <4 x float> @vp_ceil_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -438,8 +438,8 @@ define <8 x float> @vp_ceil_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -482,8 +482,8 @@ define <16 x float> @vp_ceil_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -525,8 +525,8 @@ define <2 x double> @vp_ceil_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vfabs.v v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -568,8 +568,8 @@ define <4 x double> @vp_ceil_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vfabs.v v12, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -612,8 +612,8 @@ define <8 x double> @vp_ceil_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -656,8 +656,8 @@ define <15 x double> @vp_ceil_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroex ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -700,8 +700,8 @@ define <16 x double> @vp_ceil_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroex ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -764,8 +764,8 @@ define <32 x double> @vp_ceil_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a1, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a1 @@ -788,8 +788,8 @@ define <32 x double> @vp_ceil_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll index 277146cc1403..49e5a1c79c43 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll @@ -353,8 +353,8 @@ define void @ctlz_v2i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: li a1, 190 ; RV32F-NEXT: vmv.v.x v9, a1 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v8, v10, 23 @@ -762,8 +762,8 @@ define void @ctlz_v4i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: li a1, 190 ; RV32F-NEXT: vmv.v.x v10, a1 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v8 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v8, v12, 23 @@ -1152,8 +1152,8 @@ define void @ctlz_zero_undef_v2i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: li a1, 190 ; RV32F-NEXT: vmv.v.x v9, a1 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v8, v10, 23 @@ -1537,8 +1537,8 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: li a1, 190 ; RV32F-NEXT: vmv.v.x v10, a1 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v8 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v8, v12, 23 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll index 8c8da6d1e003..ea3a78ae0bec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll @@ -336,8 +336,8 @@ define void @cttz_v2i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: vrsub.vi v9, v8, 0 ; RV32F-NEXT: vand.vv v9, v8, v9 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v9 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v9, v10, 23 @@ -357,8 +357,8 @@ define void @cttz_v2i64(ptr %x, ptr %y) nounwind { ; RV64F-NEXT: vle64.v v8, (a0) ; RV64F-NEXT: vrsub.vi v9, v8, 0 ; RV64F-NEXT: vand.vv v9, v8, v9 -; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: fsrmi a1, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v10, v9 ; RV64F-NEXT: fsrm a1 ; RV64F-NEXT: vsrl.vi v9, v10, 23 @@ -737,8 +737,8 @@ define void @cttz_v4i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: vrsub.vi v10, v8, 0 ; RV32F-NEXT: vand.vv v10, v8, v10 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v10 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v10, v12, 23 @@ -758,8 +758,8 @@ define void @cttz_v4i64(ptr %x, ptr %y) nounwind { ; RV64F-NEXT: vle64.v v8, (a0) ; RV64F-NEXT: vrsub.vi v10, v8, 0 ; RV64F-NEXT: vand.vv v10, v8, v10 -; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: fsrmi a1, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v12, v10 ; RV64F-NEXT: fsrm a1 ; RV64F-NEXT: vsrl.vi v10, v12, 23 @@ -1115,8 +1115,8 @@ define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: vrsub.vi v9, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v9 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v9, v8 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v8, v9, 23 @@ -1133,8 +1133,8 @@ define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind { ; RV64F-NEXT: vle64.v v8, (a0) ; RV64F-NEXT: vrsub.vi v9, v8, 0 ; RV64F-NEXT: vand.vv v8, v8, v9 -; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: fsrmi a1, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v9, v8 ; RV64F-NEXT: fsrm a1 ; RV64F-NEXT: vsrl.vi v8, v9, 23 @@ -1486,8 +1486,8 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: vrsub.vi v10, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v10 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v8, v10, 23 @@ -1504,8 +1504,8 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind { ; RV64F-NEXT: vle64.v v8, (a0) ; RV64F-NEXT: vrsub.vi v10, v8, 0 ; RV64F-NEXT: vand.vv v8, v8, v10 -; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: fsrmi a1, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v10, v8 ; RV64F-NEXT: fsrm a1 ; RV64F-NEXT: vsrl.vi v8, v10, 23 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll index 6c2be509f7c2..287dd510674d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll @@ -19,8 +19,8 @@ define <2 x half> @vp_floor_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: fsrmi a0, 2 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -38,8 +38,8 @@ define <2 x half> @vp_floor_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 2 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -101,8 +101,8 @@ define <4 x half> @vp_floor_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: fsrmi a0, 2 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -120,8 +120,8 @@ define <4 x half> @vp_floor_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 2 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -183,8 +183,8 @@ define <8 x half> @vp_floor_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: fsrmi a0, 2 +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -203,8 +203,8 @@ define <8 x half> @vp_floor_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v9, v12, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 2 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -268,8 +268,8 @@ define <16 x half> @vp_floor_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext % ; ZVFH-NEXT: vfabs.v v12, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: fsrmi a0, 2 +; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v10 ; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -289,8 +289,8 @@ define <16 x half> @vp_floor_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext % ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v10, v16, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 2 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -353,8 +353,8 @@ define <2 x float> @vp_floor_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -395,8 +395,8 @@ define <4 x float> @vp_floor_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -438,8 +438,8 @@ define <8 x float> @vp_floor_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -482,8 +482,8 @@ define <16 x float> @vp_floor_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -525,8 +525,8 @@ define <2 x double> @vp_floor_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext % ; CHECK-NEXT: vfabs.v v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -568,8 +568,8 @@ define <4 x double> @vp_floor_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext % ; CHECK-NEXT: vfabs.v v12, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -612,8 +612,8 @@ define <8 x double> @vp_floor_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext % ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -656,8 +656,8 @@ define <15 x double> @vp_floor_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -700,8 +700,8 @@ define <16 x double> @vp_floor_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -764,8 +764,8 @@ define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a1, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a1 @@ -788,8 +788,8 @@ define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll index 6f045349423c..716cf7b0f46f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll @@ -19,8 +19,8 @@ define <2 x half> @vp_round_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: fsrmi a0, 4 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -38,8 +38,8 @@ define <2 x half> @vp_round_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 4 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -101,8 +101,8 @@ define <4 x half> @vp_round_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: fsrmi a0, 4 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -120,8 +120,8 @@ define <4 x half> @vp_round_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 4 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -183,8 +183,8 @@ define <8 x half> @vp_round_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: fsrmi a0, 4 +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -203,8 +203,8 @@ define <8 x half> @vp_round_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v9, v12, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 4 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -268,8 +268,8 @@ define <16 x half> @vp_round_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext % ; ZVFH-NEXT: vfabs.v v12, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: fsrmi a0, 4 +; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v10 ; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -289,8 +289,8 @@ define <16 x half> @vp_round_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext % ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v10, v16, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 4 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -353,8 +353,8 @@ define <2 x float> @vp_round_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -395,8 +395,8 @@ define <4 x float> @vp_round_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -438,8 +438,8 @@ define <8 x float> @vp_round_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -482,8 +482,8 @@ define <16 x float> @vp_round_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -525,8 +525,8 @@ define <2 x double> @vp_round_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext % ; CHECK-NEXT: vfabs.v v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -568,8 +568,8 @@ define <4 x double> @vp_round_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext % ; CHECK-NEXT: vfabs.v v12, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -612,8 +612,8 @@ define <8 x double> @vp_round_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext % ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -656,8 +656,8 @@ define <15 x double> @vp_round_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -700,8 +700,8 @@ define <16 x double> @vp_round_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -764,8 +764,8 @@ define <32 x double> @vp_round_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a1, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a1 @@ -788,8 +788,8 @@ define <32 x double> @vp_round_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll index 738d7e37c50b..603f9397dc90 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll @@ -19,8 +19,8 @@ define <2 x half> @vp_roundeven_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext % ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: fsrmi a0, 0 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -38,8 +38,8 @@ define <2 x half> @vp_roundeven_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext % ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 0 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -101,8 +101,8 @@ define <4 x half> @vp_roundeven_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext % ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: fsrmi a0, 0 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -120,8 +120,8 @@ define <4 x half> @vp_roundeven_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext % ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 0 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -183,8 +183,8 @@ define <8 x half> @vp_roundeven_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext % ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: fsrmi a0, 0 +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -203,8 +203,8 @@ define <8 x half> @vp_roundeven_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext % ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v9, v12, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 0 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -268,8 +268,8 @@ define <16 x half> @vp_roundeven_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroe ; ZVFH-NEXT: vfabs.v v12, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: fsrmi a0, 0 +; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v10 ; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -289,8 +289,8 @@ define <16 x half> @vp_roundeven_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroe ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v10, v16, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 0 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -353,8 +353,8 @@ define <2 x float> @vp_roundeven_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -395,8 +395,8 @@ define <4 x float> @vp_roundeven_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -438,8 +438,8 @@ define <8 x float> @vp_roundeven_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -482,8 +482,8 @@ define <16 x float> @vp_roundeven_v16f32(<16 x float> %va, <16 x i1> %m, i32 zer ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -525,8 +525,8 @@ define <2 x double> @vp_roundeven_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -568,8 +568,8 @@ define <4 x double> @vp_roundeven_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v12, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -612,8 +612,8 @@ define <8 x double> @vp_roundeven_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -656,8 +656,8 @@ define <15 x double> @vp_roundeven_v15f64(<15 x double> %va, <15 x i1> %m, i32 z ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -700,8 +700,8 @@ define <16 x double> @vp_roundeven_v16f64(<16 x double> %va, <16 x i1> %m, i32 z ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -764,8 +764,8 @@ define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 z ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a1, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a1 @@ -788,8 +788,8 @@ define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 z ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll index 6f5b7875266b..a5adfc36887a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll @@ -19,8 +19,8 @@ define <2 x half> @vp_roundtozero_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: fsrmi a0, 1 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -38,8 +38,8 @@ define <2 x half> @vp_roundtozero_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -101,8 +101,8 @@ define <4 x half> @vp_roundtozero_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: fsrmi a0, 1 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -120,8 +120,8 @@ define <4 x half> @vp_roundtozero_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -183,8 +183,8 @@ define <8 x half> @vp_roundtozero_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: fsrmi a0, 1 +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -203,8 +203,8 @@ define <8 x half> @vp_roundtozero_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v9, v12, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -268,8 +268,8 @@ define <16 x half> @vp_roundtozero_v16f16(<16 x half> %va, <16 x i1> %m, i32 zer ; ZVFH-NEXT: vfabs.v v12, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: fsrmi a0, 1 +; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v10 ; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -289,8 +289,8 @@ define <16 x half> @vp_roundtozero_v16f16(<16 x half> %va, <16 x i1> %m, i32 zer ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v10, v16, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -353,8 +353,8 @@ define <2 x float> @vp_roundtozero_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroe ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -395,8 +395,8 @@ define <4 x float> @vp_roundtozero_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroe ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -438,8 +438,8 @@ define <8 x float> @vp_roundtozero_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroe ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -482,8 +482,8 @@ define <16 x float> @vp_roundtozero_v16f32(<16 x float> %va, <16 x i1> %m, i32 z ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -525,8 +525,8 @@ define <2 x double> @vp_roundtozero_v2f64(<2 x double> %va, <2 x i1> %m, i32 zer ; CHECK-NEXT: vfabs.v v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -568,8 +568,8 @@ define <4 x double> @vp_roundtozero_v4f64(<4 x double> %va, <4 x i1> %m, i32 zer ; CHECK-NEXT: vfabs.v v12, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -612,8 +612,8 @@ define <8 x double> @vp_roundtozero_v8f64(<8 x double> %va, <8 x i1> %m, i32 zer ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -656,8 +656,8 @@ define <15 x double> @vp_roundtozero_v15f64(<15 x double> %va, <15 x i1> %m, i32 ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -700,8 +700,8 @@ define <16 x double> @vp_roundtozero_v16f64(<16 x double> %va, <16 x i1> %m, i32 ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -764,8 +764,8 @@ define <32 x double> @vp_roundtozero_v32f64(<32 x double> %va, <32 x i1> %m, i32 ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a1, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a1 @@ -788,8 +788,8 @@ define <32 x double> @vp_roundtozero_v32f64(<32 x double> %va, <32 x i1> %m, i32 ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll index 70b547759938..600290a62515 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll @@ -5,8 +5,8 @@ define <8 x i8> @vaaddu_vv_v8i8_floor(<8 x i8> %x, <8 x i8> %y) { ; CHECK-LABEL: vaaddu_vv_v8i8_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext <8 x i8> %x to <8 x i16> @@ -20,8 +20,8 @@ define <8 x i8> @vaaddu_vv_v8i8_floor(<8 x i8> %x, <8 x i8> %y) { define <8 x i8> @vaaddu_vx_v8i8_floor(<8 x i8> %x, i8 %y) { ; CHECK-LABEL: vaaddu_vx_v8i8_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext <8 x i8> %x to <8 x i16> @@ -53,8 +53,8 @@ define <8 x i8> @vaaddu_vv_v8i8_floor_sexti16(<8 x i8> %x, <8 x i8> %y) { define <8 x i8> @vaaddu_vv_v8i8_floor_zexti32(<8 x i8> %x, <8 x i8> %y) { ; CHECK-LABEL: vaaddu_vv_v8i8_floor_zexti32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext <8 x i8> %x to <8 x i32> @@ -83,8 +83,8 @@ define <8 x i8> @vaaddu_vv_v8i8_floor_lshr2(<8 x i8> %x, <8 x i8> %y) { define <8 x i16> @vaaddu_vv_v8i16_floor(<8 x i16> %x, <8 x i16> %y) { ; CHECK-LABEL: vaaddu_vv_v8i16_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext <8 x i16> %x to <8 x i32> @@ -98,8 +98,8 @@ define <8 x i16> @vaaddu_vv_v8i16_floor(<8 x i16> %x, <8 x i16> %y) { define <8 x i16> @vaaddu_vx_v8i16_floor(<8 x i16> %x, i16 %y) { ; CHECK-LABEL: vaaddu_vx_v8i16_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext <8 x i16> %x to <8 x i32> @@ -115,8 +115,8 @@ define <8 x i16> @vaaddu_vx_v8i16_floor(<8 x i16> %x, i16 %y) { define <8 x i32> @vaaddu_vv_v8i32_floor(<8 x i32> %x, <8 x i32> %y) { ; CHECK-LABEL: vaaddu_vv_v8i32_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret %xzv = zext <8 x i32> %x to <8 x i64> @@ -130,8 +130,8 @@ define <8 x i32> @vaaddu_vv_v8i32_floor(<8 x i32> %x, <8 x i32> %y) { define <8 x i32> @vaaddu_vx_v8i32_floor(<8 x i32> %x, i32 %y) { ; CHECK-LABEL: vaaddu_vx_v8i32_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext <8 x i32> %x to <8 x i64> @@ -147,8 +147,8 @@ define <8 x i32> @vaaddu_vx_v8i32_floor(<8 x i32> %x, i32 %y) { define <8 x i64> @vaaddu_vv_v8i64_floor(<8 x i64> %x, <8 x i64> %y) { ; CHECK-LABEL: vaaddu_vv_v8i64_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret %xzv = zext <8 x i64> %x to <8 x i128> @@ -197,8 +197,8 @@ define <8 x i64> @vaaddu_vx_v8i64_floor(<8 x i64> %x, i64 %y) { ; ; RV64-LABEL: vaaddu_vx_v8i64_floor: ; RV64: # %bb.0: -; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: csrwi vxrm, 2 +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vaaddu.vx v8, v8, a0 ; RV64-NEXT: ret %xzv = zext <8 x i64> %x to <8 x i128> @@ -214,8 +214,8 @@ define <8 x i64> @vaaddu_vx_v8i64_floor(<8 x i64> %x, i64 %y) { define <8 x i8> @vaaddu_vv_v8i8_ceil(<8 x i8> %x, <8 x i8> %y) { ; CHECK-LABEL: vaaddu_vv_v8i8_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext <8 x i8> %x to <8 x i16> @@ -230,8 +230,8 @@ define <8 x i8> @vaaddu_vv_v8i8_ceil(<8 x i8> %x, <8 x i8> %y) { define <8 x i8> @vaaddu_vx_v8i8_ceil(<8 x i8> %x, i8 %y) { ; CHECK-LABEL: vaaddu_vx_v8i8_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext <8 x i8> %x to <8 x i16> @@ -267,8 +267,8 @@ define <8 x i8> @vaaddu_vv_v8i8_ceil_sexti16(<8 x i8> %x, <8 x i8> %y) { define <8 x i8> @vaaddu_vv_v8i8_ceil_zexti32(<8 x i8> %x, <8 x i8> %y) { ; CHECK-LABEL: vaaddu_vv_v8i8_ceil_zexti32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext <8 x i8> %x to <8 x i32> @@ -305,8 +305,8 @@ define <8 x i8> @vaaddu_vv_v8i8_ceil_add2(<8 x i8> %x, <8 x i8> %y) { ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vwaddu.vv v10, v8, v9 ; CHECK-NEXT: li a0, 2 -; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v10, a0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v8, 0 @@ -323,8 +323,8 @@ define <8 x i8> @vaaddu_vv_v8i8_ceil_add2(<8 x i8> %x, <8 x i8> %y) { define <8 x i16> @vaaddu_vv_v8i16_ceil(<8 x i16> %x, <8 x i16> %y) { ; CHECK-LABEL: vaaddu_vv_v8i16_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext <8 x i16> %x to <8 x i32> @@ -339,8 +339,8 @@ define <8 x i16> @vaaddu_vv_v8i16_ceil(<8 x i16> %x, <8 x i16> %y) { define <8 x i16> @vaaddu_vx_v8i16_ceil(<8 x i16> %x, i16 %y) { ; CHECK-LABEL: vaaddu_vx_v8i16_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext <8 x i16> %x to <8 x i32> @@ -357,8 +357,8 @@ define <8 x i16> @vaaddu_vx_v8i16_ceil(<8 x i16> %x, i16 %y) { define <8 x i32> @vaaddu_vv_v8i32_ceil(<8 x i32> %x, <8 x i32> %y) { ; CHECK-LABEL: vaaddu_vv_v8i32_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret %xzv = zext <8 x i32> %x to <8 x i64> @@ -373,8 +373,8 @@ define <8 x i32> @vaaddu_vv_v8i32_ceil(<8 x i32> %x, <8 x i32> %y) { define <8 x i32> @vaaddu_vx_v8i32_ceil(<8 x i32> %x, i32 %y) { ; CHECK-LABEL: vaaddu_vx_v8i32_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext <8 x i32> %x to <8 x i64> @@ -391,8 +391,8 @@ define <8 x i32> @vaaddu_vx_v8i32_ceil(<8 x i32> %x, i32 %y) { define <8 x i64> @vaaddu_vv_v8i64_ceil(<8 x i64> %x, <8 x i64> %y) { ; CHECK-LABEL: vaaddu_vv_v8i64_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret %xzv = zext <8 x i64> %x to <8 x i128> @@ -443,8 +443,8 @@ define <8 x i64> @vaaddu_vx_v8i64_ceil(<8 x i64> %x, i64 %y) { ; ; RV64-LABEL: vaaddu_vx_v8i64_ceil: ; RV64: # %bb.0: -; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: csrwi vxrm, 0 +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vaaddu.vx v8, v8, a0 ; RV64-NEXT: ret %xzv = zext <8 x i64> %x to <8 x i128> diff --git a/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll index 9dcb6d211cb9..b7661bd826fe 100644 --- a/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll @@ -487,8 +487,8 @@ define @ceil_nxv1f32_to_ui8( %x) { define @ceil_nxv1f32_to_si16( %x) { ; RV32-LABEL: ceil_nxv1f32_to_si16: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; RV32-NEXT: vfncvt.x.f.w v9, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 @@ -496,8 +496,8 @@ define @ceil_nxv1f32_to_si16( %x) { ; ; RV64-LABEL: ceil_nxv1f32_to_si16: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; RV64-NEXT: vfncvt.x.f.w v9, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 @@ -510,8 +510,8 @@ define @ceil_nxv1f32_to_si16( %x) { define @ceil_nxv1f32_to_ui16( %x) { ; RV32-LABEL: ceil_nxv1f32_to_ui16: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; RV32-NEXT: vfncvt.xu.f.w v9, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 @@ -519,8 +519,8 @@ define @ceil_nxv1f32_to_ui16( %x) { ; ; RV64-LABEL: ceil_nxv1f32_to_ui16: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; RV64-NEXT: vfncvt.xu.f.w v9, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 @@ -533,16 +533,16 @@ define @ceil_nxv1f32_to_ui16( %x) { define @ceil_nxv1f32_to_si32( %x) { ; RV32-LABEL: ceil_nxv1f32_to_si32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV32-NEXT: vfcvt.x.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv1f32_to_si32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vfcvt.x.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -554,16 +554,16 @@ define @ceil_nxv1f32_to_si32( %x) { define @ceil_nxv1f32_to_ui32( %x) { ; RV32-LABEL: ceil_nxv1f32_to_ui32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV32-NEXT: vfcvt.xu.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv1f32_to_ui32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vfcvt.xu.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -575,8 +575,8 @@ define @ceil_nxv1f32_to_ui32( %x) { define @ceil_nxv1f32_to_si64( %x) { ; RV32-LABEL: ceil_nxv1f32_to_si64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV32-NEXT: vfwcvt.x.f.v v9, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 @@ -584,8 +584,8 @@ define @ceil_nxv1f32_to_si64( %x) { ; ; RV64-LABEL: ceil_nxv1f32_to_si64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vfwcvt.x.f.v v9, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 @@ -598,8 +598,8 @@ define @ceil_nxv1f32_to_si64( %x) { define @ceil_nxv1f32_to_ui64( %x) { ; RV32-LABEL: ceil_nxv1f32_to_ui64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV32-NEXT: vfwcvt.xu.f.v v9, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 @@ -607,8 +607,8 @@ define @ceil_nxv1f32_to_ui64( %x) { ; ; RV64-LABEL: ceil_nxv1f32_to_ui64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vfwcvt.xu.f.v v9, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 @@ -713,8 +713,8 @@ define @ceil_nxv4f32_to_ui8( %x) { define @ceil_nxv4f32_to_si16( %x) { ; RV32-LABEL: ceil_nxv4f32_to_si16: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; RV32-NEXT: vfncvt.x.f.w v10, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv.v.v v8, v10 @@ -722,8 +722,8 @@ define @ceil_nxv4f32_to_si16( %x) { ; ; RV64-LABEL: ceil_nxv4f32_to_si16: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; RV64-NEXT: vfncvt.x.f.w v10, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv.v.v v8, v10 @@ -736,8 +736,8 @@ define @ceil_nxv4f32_to_si16( %x) { define @ceil_nxv4f32_to_ui16( %x) { ; RV32-LABEL: ceil_nxv4f32_to_ui16: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; RV32-NEXT: vfncvt.xu.f.w v10, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv.v.v v8, v10 @@ -745,8 +745,8 @@ define @ceil_nxv4f32_to_ui16( %x) { ; ; RV64-LABEL: ceil_nxv4f32_to_ui16: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; RV64-NEXT: vfncvt.xu.f.w v10, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv.v.v v8, v10 @@ -759,16 +759,16 @@ define @ceil_nxv4f32_to_ui16( %x) { define @ceil_nxv4f32_to_si32( %x) { ; RV32-LABEL: ceil_nxv4f32_to_si32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vfcvt.x.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv4f32_to_si32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vfcvt.x.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -780,16 +780,16 @@ define @ceil_nxv4f32_to_si32( %x) { define @ceil_nxv4f32_to_ui32( %x) { ; RV32-LABEL: ceil_nxv4f32_to_ui32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vfcvt.xu.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv4f32_to_ui32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vfcvt.xu.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -801,8 +801,8 @@ define @ceil_nxv4f32_to_ui32( %x) { define @ceil_nxv4f32_to_si64( %x) { ; RV32-LABEL: ceil_nxv4f32_to_si64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vfwcvt.x.f.v v12, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv4r.v v8, v12 @@ -810,8 +810,8 @@ define @ceil_nxv4f32_to_si64( %x) { ; ; RV64-LABEL: ceil_nxv4f32_to_si64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vfwcvt.x.f.v v12, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv4r.v v8, v12 @@ -824,8 +824,8 @@ define @ceil_nxv4f32_to_si64( %x) { define @ceil_nxv4f32_to_ui64( %x) { ; RV32-LABEL: ceil_nxv4f32_to_ui64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vfwcvt.xu.f.v v12, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv4r.v v8, v12 @@ -833,8 +833,8 @@ define @ceil_nxv4f32_to_ui64( %x) { ; ; RV64-LABEL: ceil_nxv4f32_to_ui64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vfwcvt.xu.f.v v12, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv4r.v v8, v12 diff --git a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll index 9c4706b2bda7..d464b491bbbe 100644 --- a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll @@ -15,8 +15,8 @@ define @vp_floor_nxv1f16( %va, @vp_floor_nxv2f16( %va, @vp_floor_nxv4f16( %va, @vp_floor_nxv8f16( %va, @vp_floor_nxv16f16( %va, @vp_floor_nxv32f16( %va, @vp_floor_nxv1f32( %va, @vp_floor_nxv2f32( %va, @vp_floor_nxv4f32( %va, @vp_floor_nxv8f32( %va, @vp_floor_nxv16f32( %va, @vp_floor_nxv1f64( %va, @vp_floor_nxv2f64( %va, @vp_floor_nxv4f64( %va, @vp_floor_nxv7f64( %va, @vp_floor_nxv8f64( %va, @vp_floor_nxv16f64( %va, @vp_floor_nxv16f64( %va, @llvm.riscv.vfadd.nxv1f32.nxv1f32( define @test( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: test: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; UNOPT-LABEL: test: ; UNOPT: # %bb.0: # %entry +; UNOPT-NEXT: fsrmi a1, 0 ; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; UNOPT-NEXT: fsrmi a0, 0 ; UNOPT-NEXT: vfadd.vv v8, v8, v9 -; UNOPT-NEXT: fsrm a0 +; UNOPT-NEXT: fsrm a1 ; UNOPT-NEXT: fsrmi a0, 0 ; UNOPT-NEXT: vfadd.vv v8, v8, v8 ; UNOPT-NEXT: fsrm a0 @@ -48,20 +48,20 @@ entry: define @test2( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: test2: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: fsrmi 1 ; CHECK-NEXT: vfadd.vv v8, v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; UNOPT-LABEL: test2: ; UNOPT: # %bb.0: # %entry +; UNOPT-NEXT: fsrmi a1, 0 ; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; UNOPT-NEXT: fsrmi a0, 0 ; UNOPT-NEXT: vfadd.vv v8, v8, v9 -; UNOPT-NEXT: fsrm a0 +; UNOPT-NEXT: fsrm a1 ; UNOPT-NEXT: fsrmi a0, 1 ; UNOPT-NEXT: vfadd.vv v8, v8, v8 ; UNOPT-NEXT: fsrm a0 @@ -132,12 +132,12 @@ define @before_call1( %0, @before_call1( %0, @after_call1( %0, @after_call1( %0, @before_asm1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: before_asm1: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret ; ; UNOPT-LABEL: before_asm1: ; UNOPT: # %bb.0: # %entry +; UNOPT-NEXT: fsrmi a1, 0 ; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; UNOPT-NEXT: fsrmi a0, 0 ; UNOPT-NEXT: vfadd.vv v8, v8, v9 -; UNOPT-NEXT: fsrm a0 +; UNOPT-NEXT: fsrm a1 ; UNOPT-NEXT: #APP ; UNOPT-NEXT: #NO_APP ; UNOPT-NEXT: ret @@ -416,20 +416,20 @@ entry: define @after_asm1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: after_asm1: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret ; ; UNOPT-LABEL: after_asm1: ; UNOPT: # %bb.0: # %entry +; UNOPT-NEXT: fsrmi a1, 0 ; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; UNOPT-NEXT: fsrmi a0, 0 ; UNOPT-NEXT: vfadd.vv v8, v8, v9 -; UNOPT-NEXT: fsrm a0 +; UNOPT-NEXT: fsrm a1 ; UNOPT-NEXT: #APP ; UNOPT-NEXT: #NO_APP ; UNOPT-NEXT: ret @@ -476,10 +476,10 @@ declare i32 @llvm.get.rounding() define @test5( %0, %1, i64 %2, ptr %p) nounwind { ; CHECK-LABEL: test5: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a2, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a2 ; CHECK-NEXT: frrm a0 ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: lui a2, 66 @@ -492,10 +492,10 @@ define @test5( %0, ; ; UNOPT-LABEL: test5: ; UNOPT: # %bb.0: # %entry +; UNOPT-NEXT: fsrmi a2, 0 ; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; UNOPT-NEXT: fsrmi a0, 0 ; UNOPT-NEXT: vfadd.vv v8, v8, v9 -; UNOPT-NEXT: fsrm a0 +; UNOPT-NEXT: fsrm a2 ; UNOPT-NEXT: frrm a0 ; UNOPT-NEXT: slli a0, a0, 2 ; UNOPT-NEXT: lui a2, 66 @@ -559,10 +559,10 @@ define @after_fsrm2( %0, @after_fsrm3( %0, @llvm.ceil.nxv1f16() define @ceil_nxv1f16_to_si8( %x) { ; CHECK-LABEL: ceil_nxv1f16_to_si8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vfncvt.x.f.w v9, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv1r.v v8, v9 @@ -263,8 +263,8 @@ define @ceil_nxv1f16_to_si8( %x) { define @ceil_nxv1f16_to_ui8( %x) { ; CHECK-LABEL: ceil_nxv1f16_to_ui8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv1r.v v8, v9 @@ -277,8 +277,8 @@ define @ceil_nxv1f16_to_ui8( %x) { define @ceil_nxv1f16_to_si16( %x) { ; CHECK-LABEL: ceil_nxv1f16_to_si16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -290,8 +290,8 @@ define @ceil_nxv1f16_to_si16( %x) { define @ceil_nxv1f16_to_ui16( %x) { ; CHECK-LABEL: ceil_nxv1f16_to_ui16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -303,8 +303,8 @@ define @ceil_nxv1f16_to_ui16( %x) { define @ceil_nxv1f16_to_si32( %x) { ; CHECK-LABEL: ceil_nxv1f16_to_si32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfwcvt.x.f.v v9, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv1r.v v8, v9 @@ -317,8 +317,8 @@ define @ceil_nxv1f16_to_si32( %x) { define @ceil_nxv1f16_to_ui32( %x) { ; CHECK-LABEL: ceil_nxv1f16_to_ui32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfwcvt.xu.f.v v9, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv1r.v v8, v9 @@ -451,8 +451,8 @@ declare @llvm.ceil.nxv4f16() define @ceil_nxv4f16_to_si8( %x) { ; CHECK-LABEL: ceil_nxv4f16_to_si8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vfncvt.x.f.w v9, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv1r.v v8, v9 @@ -465,8 +465,8 @@ define @ceil_nxv4f16_to_si8( %x) { define @ceil_nxv4f16_to_ui8( %x) { ; CHECK-LABEL: ceil_nxv4f16_to_ui8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv1r.v v8, v9 @@ -479,8 +479,8 @@ define @ceil_nxv4f16_to_ui8( %x) { define @ceil_nxv4f16_to_si16( %x) { ; CHECK-LABEL: ceil_nxv4f16_to_si16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -492,8 +492,8 @@ define @ceil_nxv4f16_to_si16( %x) { define @ceil_nxv4f16_to_ui16( %x) { ; CHECK-LABEL: ceil_nxv4f16_to_ui16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -505,8 +505,8 @@ define @ceil_nxv4f16_to_ui16( %x) { define @ceil_nxv4f16_to_si32( %x) { ; CHECK-LABEL: ceil_nxv4f16_to_si32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vfwcvt.x.f.v v10, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv2r.v v8, v10 @@ -519,8 +519,8 @@ define @ceil_nxv4f16_to_si32( %x) { define @ceil_nxv4f16_to_ui32( %x) { ; CHECK-LABEL: ceil_nxv4f16_to_ui32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vfwcvt.xu.f.v v10, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv2r.v v8, v10 diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-tama.ll b/llvm/test/CodeGen/RISCV/rvv/masked-tama.ll index d81079da64bd..f87fa3ec6f16 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-tama.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-tama.ll @@ -516,8 +516,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8( define @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -543,8 +543,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -570,8 +570,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8( define @intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -597,8 +597,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll b/llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll index c8bff58b00e4..4098270d365a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll @@ -489,8 +489,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8( define @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -515,8 +515,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -541,8 +541,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8( define @intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -567,8 +567,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll b/llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll index 409a008ec7cf..4cd7e143be66 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll @@ -489,8 +489,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8( define @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -515,8 +515,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -541,8 +541,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8( define @intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -567,8 +567,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll b/llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll index 90054bcc5f36..c8719e6a2e7c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll @@ -489,8 +489,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8( define @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -515,8 +515,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -541,8 +541,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8( define @intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -567,8 +567,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll index eb4994914fad..edeac1acf3b0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll @@ -19,8 +19,8 @@ define @vp_round_nxv1f16( %va, @vp_round_nxv1f16( %va, @vp_round_nxv2f16( %va, @vp_round_nxv2f16( %va, @vp_round_nxv4f16( %va, @vp_round_nxv4f16( %va, @vp_round_nxv8f16( %va, @vp_round_nxv8f16( %va, @vp_round_nxv16f16( %va, @vp_round_nxv16f16( %va, @vp_round_nxv32f16( %va, @vp_round_nxv32f16( %va, @vp_round_nxv32f16( %va, @vp_round_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: fmv.w.x fa5, a2 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: fsrmi a2, 4 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v16 ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t ; ZVFHMIN-NEXT: fsrm a2 @@ -615,8 +615,8 @@ define @vp_round_nxv1f32( %va, @vp_round_nxv2f32( %va, @vp_round_nxv4f32( %va, @vp_round_nxv8f32( %va, @vp_round_nxv16f32( %va, @vp_round_nxv1f64( %va, @vp_round_nxv2f64( %va, @vp_round_nxv4f64( %va, @vp_round_nxv7f64( %va, @vp_round_nxv8f64( %va, @vp_round_nxv16f64( %va, @vp_round_nxv16f64( %va, @vp_roundeven_nxv1f16( %va, @vp_roundeven_nxv1f16( %va, @vp_roundeven_nxv2f16( %va, @vp_roundeven_nxv2f16( %va, @vp_roundeven_nxv4f16( %va, @vp_roundeven_nxv4f16( %va, @vp_roundeven_nxv8f16( %va, @vp_roundeven_nxv8f16( %va, @vp_roundeven_nxv16f16( %va, @vp_roundeven_nxv16f16( %va, @vp_roundeven_nxv32f16( %va, @vp_roundeven_nxv32f16( %va, @vp_roundeven_nxv32f16( %va, @vp_roundeven_nxv32f16_unmasked( ; ZVFHMIN-NEXT: fmv.w.x fa5, a2 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: fsrmi a2, 0 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v16 ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t ; ZVFHMIN-NEXT: fsrm a2 @@ -615,8 +615,8 @@ define @vp_roundeven_nxv1f32( %va, @vp_roundeven_nxv2f32( %va, @vp_roundeven_nxv4f32( %va, @vp_roundeven_nxv8f32( %va, @vp_roundeven_nxv16f32( %va, < ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -831,8 +831,8 @@ define @vp_roundeven_nxv1f64( %va, @vp_roundeven_nxv2f64( %va, @vp_roundeven_nxv4f64( %va, @vp_roundeven_nxv7f64( %va, @vp_roundeven_nxv8f64( %va, @vp_roundeven_nxv16f64( %va, ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a2, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a2 @@ -1092,8 +1092,8 @@ define @vp_roundeven_nxv16f64( %va, ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll index 79c940bdf089..71a53c525551 100644 --- a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll @@ -19,8 +19,8 @@ define @vp_roundtozero_nxv1f16( %va, @vp_roundtozero_nxv1f16( %va, @vp_roundtozero_nxv2f16( %va, @vp_roundtozero_nxv2f16( %va, @vp_roundtozero_nxv4f16( %va, @vp_roundtozero_nxv4f16( %va, @vp_roundtozero_nxv8f16( %va, @vp_roundtozero_nxv8f16( %va, @vp_roundtozero_nxv16f16( %va, < ; ZVFH-NEXT: vfabs.v v16, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFH-NEXT: fsrmi a0, 1 +; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v12 ; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -375,8 +375,8 @@ define @vp_roundtozero_nxv16f16( %va, < ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v12, v24, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v12 ; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -440,8 +440,8 @@ define @vp_roundtozero_nxv32f16( %va, < ; ZVFH-NEXT: vfabs.v v24, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu ; ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, ma ; ZVFH-NEXT: fsrmi a0, 1 +; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v16 ; ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -479,8 +479,8 @@ define @vp_roundtozero_nxv32f16( %va, < ; ZVFHMIN-NEXT: fmv.w.x fa5, a2 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: fsrmi a2, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v17 ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t ; ZVFHMIN-NEXT: fsrm a2 @@ -501,8 +501,8 @@ define @vp_roundtozero_nxv32f16( %va, < ; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v16 ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -567,8 +567,8 @@ define @vp_roundtozero_nxv32f16_unmasked( @vp_roundtozero_nxv1f32( %va, @vp_roundtozero_nxv2f32( %va, @vp_roundtozero_nxv4f32( %va, @vp_roundtozero_nxv8f32( %va, @vp_roundtozero_nxv16f32( %va, ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -831,8 +831,8 @@ define @vp_roundtozero_nxv1f64( %va, ; CHECK-NEXT: vfabs.v v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -874,8 +874,8 @@ define @vp_roundtozero_nxv2f64( %va, ; CHECK-NEXT: vfabs.v v12, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -918,8 +918,8 @@ define @vp_roundtozero_nxv4f64( %va, ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -962,8 +962,8 @@ define @vp_roundtozero_nxv7f64( %va, ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -1006,8 +1006,8 @@ define @vp_roundtozero_nxv8f64( %va, ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -1068,8 +1068,8 @@ define @vp_roundtozero_nxv16f64( %v ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a2, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a2 @@ -1092,8 +1092,8 @@ define @vp_roundtozero_nxv16f64( %v ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll index 8cefbac59ce6..033a1d7e297f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll @@ -215,10 +215,10 @@ declare @llvm.vp.merge.nxv2i32(, @vmerge_vfcvt_rm( %passthru, %a, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmerge_vfcvt_rm: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 2 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 2 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %floor = call @llvm.floor.nxv2f32( %a) diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll index 64b3a6f2b4b3..1a3a1a6c1ee6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll @@ -919,8 +919,8 @@ entry: define @test_vaaddu( %var_11, i16 zeroext %var_9, %var_5, %var_0) { ; CHECK-LABEL: test_vaaddu: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetivli zero, 3, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 3, e16, mf4, ta, mu ; CHECK-NEXT: vaaddu.vx v9, v8, a0, v0.t ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret @@ -966,13 +966,13 @@ declare @llvm.riscv.vfredusum.nxv2f32.nxv2f32( define @vfredusum( %passthru, %x, %y, %m, i64 %vl) { ; CHECK-LABEL: vfredusum: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vfredusum.vs v11, v9, v10 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma ; CHECK-NEXT: vmerge.vvm v8, v8, v11, v0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret %a = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32( %passthru, @@ -1002,10 +1002,10 @@ define @vredsum_allones_mask( %passthru, @vfredusum_allones_mask( %passthru, %x, %y, i64 %vl) { ; CHECK-LABEL: vfredusum_allones_mask: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret %a = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32( %passthru, @@ -1136,10 +1136,10 @@ define @vpmerge_vwsub.w_tied( %passthru, @vpmerge_vfwsub.w_tied( %passthru, %x, %y, %mask, i32 zeroext %vl) { ; CHECK-LABEL: vpmerge_vfwsub.w_tied: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfwsub.wv v8, v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret %vl.zext = zext i32 %vl to i64 %a = call @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32( %passthru, %passthru, %y, i64 1, i64 %vl.zext) diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll index b44b57394321..3c19616576f5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.iXLen( define @intrinsic_sf_vfnrclip_x_f_qf_nxv1i8_nxv1f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv1i8_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -39,10 +39,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.iXL define @intrinsic_sf_vfnrclip_x_f_qf_mask_nxv1i8_nxv1f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_mask_nxv1i8_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.iXLen( @@ -64,10 +64,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.iXLen( define @intrinsic_sf_vfnrclip_x_f_qf_nxv2i8_nxv2f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv2i8_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -90,10 +90,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.iXL define @intrinsic_sf_vfnrclip_x_f_qf_mask_nxv2i8_nxv2f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_mask_nxv2i8_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.iXLen( @@ -115,10 +115,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.iXLen( define @intrinsic_sf_vfnrclip_x_f_qf_nxv4i8_nxv4f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv4i8_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -141,10 +141,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.iXL define @intrinsic_sf_vfnrclip_x_f_qf_mask_nxv4i8_nxv4f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_mask_nxv4i8_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.iXLen( @@ -166,10 +166,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.iXLen( define @intrinsic_sf_vfnrclip_x_f_qf_nxv8i8_nxv8f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv8i8_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -192,10 +192,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.iXL define @intrinsic_sf_vfnrclip_x_f_qf_mask_nxv8i8_nxv8f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_mask_nxv8i8_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.iXLen( @@ -217,10 +217,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.iXLen define @intrinsic_sf_vfnrclip_x_f_qf_nxv16i8_nxv16f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv16i8_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -243,10 +243,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv16i8.nxv16f32. define @intrinsic_sf_vfnrclip_x_f_qf_mask_nxv16i8_nxv16f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_mask_nxv16i8_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv16i8.nxv16f32.iXLen( diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll index bc2f7ca7dc86..dbcee311c6e3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.iXLen( define @intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -39,10 +39,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.iX define @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv1i8_nxv1f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv1i8_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.iXLen( @@ -64,10 +64,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.iXLen( define @intrinsic_sf_vfnrclip_xu_f_qf_nxv2i8_nxv2f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv2i8_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -90,10 +90,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.iX define @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv2i8_nxv2f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv2i8_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.iXLen( @@ -115,10 +115,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.iXLen( define @intrinsic_sf_vfnrclip_xu_f_qf_nxv4i8_nxv4f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv4i8_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -141,10 +141,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.iX define @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv4i8_nxv4f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv4i8_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.iXLen( @@ -166,10 +166,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.iXLen( define @intrinsic_sf_vfnrclip_xu_f_qf_nxv8i8_nxv8f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv8i8_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -192,10 +192,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.iX define @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv8i8_nxv8f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv8i8_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.iXLen( @@ -217,10 +217,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.iXLe define @intrinsic_sf_vfnrclip_xu_f_qf_nxv16i8_nxv16f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv16i8_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -243,10 +243,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv16i8.nxv16f32 define @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv16i8_nxv16f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv16i8_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv16i8.nxv16f32.iXLen( diff --git a/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll b/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll index 2926a23c8b27..25e3468dcb62 100644 --- a/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll @@ -110,8 +110,8 @@ declare @llvm.riscv.vaadd.rm.nxv1i8.nxv1i8( define @intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vaadd.vv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vaaddu.rm.nxv1i8.nxv1i8( define @intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vaaddu.vv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -199,8 +199,8 @@ declare @llvm.riscv.vasub.rm.nxv1i8.nxv1i8( define @intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vasub.vv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -222,8 +222,8 @@ declare @llvm.riscv.vasubu.rm.nxv1i8.nxv1i8( define @intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vasubu.vv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -950,8 +950,8 @@ declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vnclip.wv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -974,8 +974,8 @@ declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vnclipu.wv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -1271,8 +1271,8 @@ declare @llvm.riscv.vsmul.nxv1i8.nxv1i8( define @intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vsmul.vv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -1301,16 +1301,16 @@ define @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64( @llvm.riscv.vssra.nxv1i8.nxv1i8( define @intrinsic_vssra_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vssra_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vssra.vv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -1400,8 +1400,8 @@ declare @llvm.riscv.vssrl.nxv1i8.nxv1i8( define @intrinsic_vssrl_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vssrl.vv v8, v9, v10 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vaadd.ll b/llvm/test/CodeGen/RISCV/rvv/vaadd.ll index 82cd4bf162b9..096e60b6285f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaadd.ll @@ -13,8 +13,8 @@ declare @llvm.riscv.vaadd.nxv1i8.nxv1i8( define @intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -37,8 +37,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8( define @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vaadd.nxv2i8.nxv2i8( define @intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -85,8 +85,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i8.nxv2i8( define @intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -109,8 +109,8 @@ declare @llvm.riscv.vaadd.nxv4i8.nxv4i8( define @intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i8.nxv4i8( define @intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -157,8 +157,8 @@ declare @llvm.riscv.vaadd.nxv8i8.nxv8i8( define @intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -181,8 +181,8 @@ declare @llvm.riscv.vaadd.mask.nxv8i8.nxv8i8( define @intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -205,8 +205,8 @@ declare @llvm.riscv.vaadd.nxv16i8.nxv16i8( define @intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vaadd.mask.nxv16i8.nxv16i8( define @intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -253,8 +253,8 @@ declare @llvm.riscv.vaadd.nxv32i8.nxv32i8( define @intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -277,8 +277,8 @@ declare @llvm.riscv.vaadd.mask.nxv32i8.nxv32i8( define @intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -301,8 +301,8 @@ declare @llvm.riscv.vaadd.nxv64i8.nxv64i8( define @intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -326,8 +326,8 @@ define @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( @llvm.riscv.vaadd.nxv1i16.nxv1i16( define @intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -374,8 +374,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i16.nxv1i16( define @intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -398,8 +398,8 @@ declare @llvm.riscv.vaadd.nxv2i16.nxv2i16( define @intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -422,8 +422,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i16.nxv2i16( define @intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -446,8 +446,8 @@ declare @llvm.riscv.vaadd.nxv4i16.nxv4i16( define @intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -470,8 +470,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i16.nxv4i16( define @intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -494,8 +494,8 @@ declare @llvm.riscv.vaadd.nxv8i16.nxv8i16( define @intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -518,8 +518,8 @@ declare @llvm.riscv.vaadd.mask.nxv8i16.nxv8i16( define @intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -542,8 +542,8 @@ declare @llvm.riscv.vaadd.nxv16i16.nxv16i16( define @intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -566,8 +566,8 @@ declare @llvm.riscv.vaadd.mask.nxv16i16.nxv16i16( define @intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -590,8 +590,8 @@ declare @llvm.riscv.vaadd.nxv32i16.nxv32i16( define @intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -615,8 +615,8 @@ define @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(< ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -639,8 +639,8 @@ declare @llvm.riscv.vaadd.nxv1i32.nxv1i32( define @intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i32.nxv1i32( define @intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -687,8 +687,8 @@ declare @llvm.riscv.vaadd.nxv2i32.nxv2i32( define @intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -711,8 +711,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i32.nxv2i32( define @intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -735,8 +735,8 @@ declare @llvm.riscv.vaadd.nxv4i32.nxv4i32( define @intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -759,8 +759,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i32.nxv4i32( define @intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -783,8 +783,8 @@ declare @llvm.riscv.vaadd.nxv8i32.nxv8i32( define @intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -807,8 +807,8 @@ declare @llvm.riscv.vaadd.mask.nxv8i32.nxv8i32( define @intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vaadd.nxv16i32.nxv16i32( define @intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -856,8 +856,8 @@ define @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(< ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -880,8 +880,8 @@ declare @llvm.riscv.vaadd.nxv1i64.nxv1i64( define @intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -904,8 +904,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64( define @intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -928,8 +928,8 @@ declare @llvm.riscv.vaadd.nxv2i64.nxv2i64( define @intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -952,8 +952,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i64.nxv2i64( define @intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -976,8 +976,8 @@ declare @llvm.riscv.vaadd.nxv4i64.nxv4i64( define @intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -1000,8 +1000,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i64.nxv4i64( define @intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1024,8 +1024,8 @@ declare @llvm.riscv.vaadd.nxv8i64.nxv8i64( define @intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -1049,8 +1049,8 @@ define @intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( @llvm.riscv.vaadd.nxv1i8.i8( define @intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i8.i8( define @intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1121,8 +1121,8 @@ declare @llvm.riscv.vaadd.nxv2i8.i8( define @intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1145,8 +1145,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i8.i8( define @intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1169,8 +1169,8 @@ declare @llvm.riscv.vaadd.nxv4i8.i8( define @intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1193,8 +1193,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i8.i8( define @intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1217,8 +1217,8 @@ declare @llvm.riscv.vaadd.nxv8i8.i8( define @intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1241,8 +1241,8 @@ declare @llvm.riscv.vaadd.mask.nxv8i8.i8( define @intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1265,8 +1265,8 @@ declare @llvm.riscv.vaadd.nxv16i8.i8( define @intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1289,8 +1289,8 @@ declare @llvm.riscv.vaadd.mask.nxv16i8.i8( define @intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1313,8 +1313,8 @@ declare @llvm.riscv.vaadd.nxv32i8.i8( define @intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1337,8 +1337,8 @@ declare @llvm.riscv.vaadd.mask.nxv32i8.i8( define @intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1361,8 +1361,8 @@ declare @llvm.riscv.vaadd.nxv64i8.i8( define @intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1385,8 +1385,8 @@ declare @llvm.riscv.vaadd.mask.nxv64i8.i8( define @intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1409,8 +1409,8 @@ declare @llvm.riscv.vaadd.nxv1i16.i16( define @intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1433,8 +1433,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i16.i16( define @intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1457,8 +1457,8 @@ declare @llvm.riscv.vaadd.nxv2i16.i16( define @intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1481,8 +1481,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i16.i16( define @intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1505,8 +1505,8 @@ declare @llvm.riscv.vaadd.nxv4i16.i16( define @intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1529,8 +1529,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i16.i16( define @intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1553,8 +1553,8 @@ declare @llvm.riscv.vaadd.nxv8i16.i16( define @intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1577,8 +1577,8 @@ declare @llvm.riscv.vaadd.mask.nxv8i16.i16( define @intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1601,8 +1601,8 @@ declare @llvm.riscv.vaadd.nxv16i16.i16( define @intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1625,8 +1625,8 @@ declare @llvm.riscv.vaadd.mask.nxv16i16.i16( define @intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1649,8 +1649,8 @@ declare @llvm.riscv.vaadd.nxv32i16.i16( define @intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1673,8 +1673,8 @@ declare @llvm.riscv.vaadd.mask.nxv32i16.i16( define @intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1697,8 +1697,8 @@ declare @llvm.riscv.vaadd.nxv1i32.i32( define @intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1721,8 +1721,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i32.i32( define @intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1745,8 +1745,8 @@ declare @llvm.riscv.vaadd.nxv2i32.i32( define @intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i32.i32( define @intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1793,8 +1793,8 @@ declare @llvm.riscv.vaadd.nxv4i32.i32( define @intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1817,8 +1817,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i32.i32( define @intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1841,8 +1841,8 @@ declare @llvm.riscv.vaadd.nxv8i32.i32( define @intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1865,8 +1865,8 @@ declare @llvm.riscv.vaadd.mask.nxv8i32.i32( define @intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1889,8 +1889,8 @@ declare @llvm.riscv.vaadd.nxv16i32.i32( define @intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1913,8 +1913,8 @@ declare @llvm.riscv.vaadd.mask.nxv16i32.i32( define @intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1950,8 +1950,8 @@ define @intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64( @intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64( @intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64( @intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64( @intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64( @vaaddu_vv_nxv8i8_floor( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i8_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext %x to @@ -20,8 +20,8 @@ define @vaaddu_vv_nxv8i8_floor( %x, @vaaddu_vx_nxv8i8_floor( %x, i8 %y) { ; CHECK-LABEL: vaaddu_vx_nxv8i8_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext %x to @@ -52,8 +52,8 @@ define @vaaddu_vv_nxv8i8_floor_sexti16( %x, < define @vaaddu_vv_nxv8i8_floor_zexti32( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i8_floor_zexti32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext %x to @@ -82,8 +82,8 @@ define @vaaddu_vv_nxv8i8_floor_lshr2( %x, @vaaddu_vv_nxv8i16_floor( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i16_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret %xzv = zext %x to @@ -97,8 +97,8 @@ define @vaaddu_vv_nxv8i16_floor( %x, @vaaddu_vx_nxv8i16_floor( %x, i16 %y) { ; CHECK-LABEL: vaaddu_vx_nxv8i16_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext %x to @@ -114,8 +114,8 @@ define @vaaddu_vx_nxv8i16_floor( %x, i16 %y define @vaaddu_vv_nxv8i32_floor( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i32_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret %xzv = zext %x to @@ -129,8 +129,8 @@ define @vaaddu_vv_nxv8i32_floor( %x, @vaaddu_vx_nxv8i32_floor( %x, i32 %y) { ; CHECK-LABEL: vaaddu_vx_nxv8i32_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext %x to @@ -146,8 +146,8 @@ define @vaaddu_vx_nxv8i32_floor( %x, i32 %y define @vaaddu_vv_nxv8i64_floor( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i64_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v16 ; CHECK-NEXT: ret %xzv = zext %x to @@ -175,8 +175,8 @@ define @vaaddu_vx_nxv8i64_floor( %x, i64 %y ; ; RV64-LABEL: vaaddu_vx_nxv8i64_floor: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: csrwi vxrm, 2 +; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vaaddu.vx v8, v8, a0 ; RV64-NEXT: ret %xzv = zext %x to @@ -192,8 +192,8 @@ define @vaaddu_vx_nxv8i64_floor( %x, i64 %y define @vaaddu_vv_nxv8i8_ceil( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext %x to @@ -208,8 +208,8 @@ define @vaaddu_vv_nxv8i8_ceil( %x, @vaaddu_vx_nxv8i8_ceil( %x, i8 %y) { ; CHECK-LABEL: vaaddu_vx_nxv8i8_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext %x to @@ -245,8 +245,8 @@ define @vaaddu_vv_nxv8i8_ceil_sexti16( %x, @vaaddu_vv_nxv8i8_ceil_zexti32( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_zexti32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext %x to @@ -299,8 +299,8 @@ define @vaaddu_vv_nxv8i8_ceil_add2( %x, @vaaddu_vv_nxv8i16_ceil( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i16_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret %xzv = zext %x to @@ -315,8 +315,8 @@ define @vaaddu_vv_nxv8i16_ceil( %x, @vaaddu_vx_nxv8i16_ceil( %x, i16 %y) { ; CHECK-LABEL: vaaddu_vx_nxv8i16_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext %x to @@ -333,8 +333,8 @@ define @vaaddu_vx_nxv8i16_ceil( %x, i16 %y) define @vaaddu_vv_nxv8i32_ceil( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i32_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret %xzv = zext %x to @@ -349,8 +349,8 @@ define @vaaddu_vv_nxv8i32_ceil( %x, @vaaddu_vx_nxv8i32_ceil( %x, i32 %y) { ; CHECK-LABEL: vaaddu_vx_nxv8i32_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext %x to @@ -367,8 +367,8 @@ define @vaaddu_vx_nxv8i32_ceil( %x, i32 %y) define @vaaddu_vv_nxv8i64_ceil( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i64_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v16 ; CHECK-NEXT: ret %xzv = zext %x to @@ -397,8 +397,8 @@ define @vaaddu_vx_nxv8i64_ceil( %x, i64 %y) ; ; RV64-LABEL: vaaddu_vx_nxv8i64_ceil: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: csrwi vxrm, 0 +; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vaaddu.vx v8, v8, a0 ; RV64-NEXT: ret %xzv = zext %x to diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll index eba87d7061d3..a15a1932360a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll @@ -13,8 +13,8 @@ declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8( define @intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -37,8 +37,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i8.nxv1i8( define @intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8( define @intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -85,8 +85,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i8.nxv2i8( define @intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -109,8 +109,8 @@ declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8( define @intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i8.nxv4i8( define @intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -157,8 +157,8 @@ declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8( define @intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -181,8 +181,8 @@ declare @llvm.riscv.vaaddu.mask.nxv8i8.nxv8i8( define @intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -205,8 +205,8 @@ declare @llvm.riscv.vaaddu.nxv16i8.nxv16i8( define @intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vaaddu.mask.nxv16i8.nxv16i8( define @intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -253,8 +253,8 @@ declare @llvm.riscv.vaaddu.nxv32i8.nxv32i8( define @intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -277,8 +277,8 @@ declare @llvm.riscv.vaaddu.mask.nxv32i8.nxv32i8( define @intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -301,8 +301,8 @@ declare @llvm.riscv.vaaddu.nxv64i8.nxv64i8( define @intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -326,8 +326,8 @@ define @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8( @llvm.riscv.vaaddu.nxv1i16.nxv1i16( define @intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -374,8 +374,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i16.nxv1i16( define @intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -398,8 +398,8 @@ declare @llvm.riscv.vaaddu.nxv2i16.nxv2i16( define @intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -422,8 +422,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i16.nxv2i16( define @intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -446,8 +446,8 @@ declare @llvm.riscv.vaaddu.nxv4i16.nxv4i16( define @intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -470,8 +470,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i16.nxv4i16( define @intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -494,8 +494,8 @@ declare @llvm.riscv.vaaddu.nxv8i16.nxv8i16( define @intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -518,8 +518,8 @@ declare @llvm.riscv.vaaddu.mask.nxv8i16.nxv8i16( define @intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -542,8 +542,8 @@ declare @llvm.riscv.vaaddu.nxv16i16.nxv16i16( define @intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -566,8 +566,8 @@ declare @llvm.riscv.vaaddu.mask.nxv16i16.nxv16i16( define @intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -590,8 +590,8 @@ declare @llvm.riscv.vaaddu.nxv32i16.nxv32i16( define @intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -615,8 +615,8 @@ define @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16( ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -639,8 +639,8 @@ declare @llvm.riscv.vaaddu.nxv1i32.nxv1i32( define @intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i32.nxv1i32( define @intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -687,8 +687,8 @@ declare @llvm.riscv.vaaddu.nxv2i32.nxv2i32( define @intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -711,8 +711,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i32.nxv2i32( define @intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -735,8 +735,8 @@ declare @llvm.riscv.vaaddu.nxv4i32.nxv4i32( define @intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -759,8 +759,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i32.nxv4i32( define @intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -783,8 +783,8 @@ declare @llvm.riscv.vaaddu.nxv8i32.nxv8i32( define @intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -807,8 +807,8 @@ declare @llvm.riscv.vaaddu.mask.nxv8i32.nxv8i32( define @intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vaaddu.nxv16i32.nxv16i32( define @intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -856,8 +856,8 @@ define @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32( ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -880,8 +880,8 @@ declare @llvm.riscv.vaaddu.nxv1i64.nxv1i64( define @intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -904,8 +904,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64( define @intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -928,8 +928,8 @@ declare @llvm.riscv.vaaddu.nxv2i64.nxv2i64( define @intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -952,8 +952,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i64.nxv2i64( define @intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -976,8 +976,8 @@ declare @llvm.riscv.vaaddu.nxv4i64.nxv4i64( define @intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -1000,8 +1000,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i64.nxv4i64( define @intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1024,8 +1024,8 @@ declare @llvm.riscv.vaaddu.nxv8i64.nxv8i64( define @intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -1049,8 +1049,8 @@ define @intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64( @llvm.riscv.vaaddu.nxv1i8.i8( define @intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i8.i8( define @intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1121,8 +1121,8 @@ declare @llvm.riscv.vaaddu.nxv2i8.i8( define @intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1145,8 +1145,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i8.i8( define @intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1169,8 +1169,8 @@ declare @llvm.riscv.vaaddu.nxv4i8.i8( define @intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1193,8 +1193,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i8.i8( define @intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1217,8 +1217,8 @@ declare @llvm.riscv.vaaddu.nxv8i8.i8( define @intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1241,8 +1241,8 @@ declare @llvm.riscv.vaaddu.mask.nxv8i8.i8( define @intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1265,8 +1265,8 @@ declare @llvm.riscv.vaaddu.nxv16i8.i8( define @intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1289,8 +1289,8 @@ declare @llvm.riscv.vaaddu.mask.nxv16i8.i8( define @intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1313,8 +1313,8 @@ declare @llvm.riscv.vaaddu.nxv32i8.i8( define @intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1337,8 +1337,8 @@ declare @llvm.riscv.vaaddu.mask.nxv32i8.i8( define @intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1361,8 +1361,8 @@ declare @llvm.riscv.vaaddu.nxv64i8.i8( define @intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1385,8 +1385,8 @@ declare @llvm.riscv.vaaddu.mask.nxv64i8.i8( define @intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1409,8 +1409,8 @@ declare @llvm.riscv.vaaddu.nxv1i16.i16( define @intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1433,8 +1433,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i16.i16( define @intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1457,8 +1457,8 @@ declare @llvm.riscv.vaaddu.nxv2i16.i16( define @intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1481,8 +1481,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i16.i16( define @intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1505,8 +1505,8 @@ declare @llvm.riscv.vaaddu.nxv4i16.i16( define @intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1529,8 +1529,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i16.i16( define @intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1553,8 +1553,8 @@ declare @llvm.riscv.vaaddu.nxv8i16.i16( define @intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1577,8 +1577,8 @@ declare @llvm.riscv.vaaddu.mask.nxv8i16.i16( define @intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1601,8 +1601,8 @@ declare @llvm.riscv.vaaddu.nxv16i16.i16( define @intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1625,8 +1625,8 @@ declare @llvm.riscv.vaaddu.mask.nxv16i16.i16( define @intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1649,8 +1649,8 @@ declare @llvm.riscv.vaaddu.nxv32i16.i16( define @intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1673,8 +1673,8 @@ declare @llvm.riscv.vaaddu.mask.nxv32i16.i16( define @intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1697,8 +1697,8 @@ declare @llvm.riscv.vaaddu.nxv1i32.i32( define @intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1721,8 +1721,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i32.i32( define @intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1745,8 +1745,8 @@ declare @llvm.riscv.vaaddu.nxv2i32.i32( define @intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i32.i32( define @intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1793,8 +1793,8 @@ declare @llvm.riscv.vaaddu.nxv4i32.i32( define @intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1817,8 +1817,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i32.i32( define @intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1841,8 +1841,8 @@ declare @llvm.riscv.vaaddu.nxv8i32.i32( define @intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1865,8 +1865,8 @@ declare @llvm.riscv.vaaddu.mask.nxv8i32.i32( define @intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1889,8 +1889,8 @@ declare @llvm.riscv.vaaddu.nxv16i32.i32( define @intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1913,8 +1913,8 @@ declare @llvm.riscv.vaaddu.mask.nxv16i32.i32( define @intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1950,8 +1950,8 @@ define @intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64( @intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64( @llvm.riscv.vasub.nxv1i8.nxv1i8( define @intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -37,8 +37,8 @@ declare @llvm.riscv.vasub.mask.nxv1i8.nxv1i8( define @intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vasub.nxv2i8.nxv2i8( define @intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -85,8 +85,8 @@ declare @llvm.riscv.vasub.mask.nxv2i8.nxv2i8( define @intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -109,8 +109,8 @@ declare @llvm.riscv.vasub.nxv4i8.nxv4i8( define @intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vasub.mask.nxv4i8.nxv4i8( define @intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -157,8 +157,8 @@ declare @llvm.riscv.vasub.nxv8i8.nxv8i8( define @intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -181,8 +181,8 @@ declare @llvm.riscv.vasub.mask.nxv8i8.nxv8i8( define @intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -205,8 +205,8 @@ declare @llvm.riscv.vasub.nxv16i8.nxv16i8( define @intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vasub.mask.nxv16i8.nxv16i8( define @intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -253,8 +253,8 @@ declare @llvm.riscv.vasub.nxv32i8.nxv32i8( define @intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -277,8 +277,8 @@ declare @llvm.riscv.vasub.mask.nxv32i8.nxv32i8( define @intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -301,8 +301,8 @@ declare @llvm.riscv.vasub.nxv64i8.nxv64i8( define @intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -326,8 +326,8 @@ define @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8( @llvm.riscv.vasub.nxv1i16.nxv1i16( define @intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -374,8 +374,8 @@ declare @llvm.riscv.vasub.mask.nxv1i16.nxv1i16( define @intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -398,8 +398,8 @@ declare @llvm.riscv.vasub.nxv2i16.nxv2i16( define @intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -422,8 +422,8 @@ declare @llvm.riscv.vasub.mask.nxv2i16.nxv2i16( define @intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -446,8 +446,8 @@ declare @llvm.riscv.vasub.nxv4i16.nxv4i16( define @intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -470,8 +470,8 @@ declare @llvm.riscv.vasub.mask.nxv4i16.nxv4i16( define @intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -494,8 +494,8 @@ declare @llvm.riscv.vasub.nxv8i16.nxv8i16( define @intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -518,8 +518,8 @@ declare @llvm.riscv.vasub.mask.nxv8i16.nxv8i16( define @intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -542,8 +542,8 @@ declare @llvm.riscv.vasub.nxv16i16.nxv16i16( define @intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -566,8 +566,8 @@ declare @llvm.riscv.vasub.mask.nxv16i16.nxv16i16( define @intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -590,8 +590,8 @@ declare @llvm.riscv.vasub.nxv32i16.nxv32i16( define @intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -615,8 +615,8 @@ define @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16(< ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -639,8 +639,8 @@ declare @llvm.riscv.vasub.nxv1i32.nxv1i32( define @intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vasub.mask.nxv1i32.nxv1i32( define @intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -687,8 +687,8 @@ declare @llvm.riscv.vasub.nxv2i32.nxv2i32( define @intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -711,8 +711,8 @@ declare @llvm.riscv.vasub.mask.nxv2i32.nxv2i32( define @intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -735,8 +735,8 @@ declare @llvm.riscv.vasub.nxv4i32.nxv4i32( define @intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -759,8 +759,8 @@ declare @llvm.riscv.vasub.mask.nxv4i32.nxv4i32( define @intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -783,8 +783,8 @@ declare @llvm.riscv.vasub.nxv8i32.nxv8i32( define @intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -807,8 +807,8 @@ declare @llvm.riscv.vasub.mask.nxv8i32.nxv8i32( define @intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vasub.nxv16i32.nxv16i32( define @intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -856,8 +856,8 @@ define @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32(< ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -880,8 +880,8 @@ declare @llvm.riscv.vasub.nxv1i64.nxv1i64( define @intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -904,8 +904,8 @@ declare @llvm.riscv.vasub.mask.nxv1i64.nxv1i64( define @intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -928,8 +928,8 @@ declare @llvm.riscv.vasub.nxv2i64.nxv2i64( define @intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -952,8 +952,8 @@ declare @llvm.riscv.vasub.mask.nxv2i64.nxv2i64( define @intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -976,8 +976,8 @@ declare @llvm.riscv.vasub.nxv4i64.nxv4i64( define @intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -1000,8 +1000,8 @@ declare @llvm.riscv.vasub.mask.nxv4i64.nxv4i64( define @intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1024,8 +1024,8 @@ declare @llvm.riscv.vasub.nxv8i64.nxv8i64( define @intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -1049,8 +1049,8 @@ define @intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64( @llvm.riscv.vasub.nxv1i8.i8( define @intrinsic_vasub_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vasub.mask.nxv1i8.i8( define @intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1121,8 +1121,8 @@ declare @llvm.riscv.vasub.nxv2i8.i8( define @intrinsic_vasub_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1145,8 +1145,8 @@ declare @llvm.riscv.vasub.mask.nxv2i8.i8( define @intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1169,8 +1169,8 @@ declare @llvm.riscv.vasub.nxv4i8.i8( define @intrinsic_vasub_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1193,8 +1193,8 @@ declare @llvm.riscv.vasub.mask.nxv4i8.i8( define @intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1217,8 +1217,8 @@ declare @llvm.riscv.vasub.nxv8i8.i8( define @intrinsic_vasub_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1241,8 +1241,8 @@ declare @llvm.riscv.vasub.mask.nxv8i8.i8( define @intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1265,8 +1265,8 @@ declare @llvm.riscv.vasub.nxv16i8.i8( define @intrinsic_vasub_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1289,8 +1289,8 @@ declare @llvm.riscv.vasub.mask.nxv16i8.i8( define @intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1313,8 +1313,8 @@ declare @llvm.riscv.vasub.nxv32i8.i8( define @intrinsic_vasub_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1337,8 +1337,8 @@ declare @llvm.riscv.vasub.mask.nxv32i8.i8( define @intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1361,8 +1361,8 @@ declare @llvm.riscv.vasub.nxv64i8.i8( define @intrinsic_vasub_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1385,8 +1385,8 @@ declare @llvm.riscv.vasub.mask.nxv64i8.i8( define @intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1409,8 +1409,8 @@ declare @llvm.riscv.vasub.nxv1i16.i16( define @intrinsic_vasub_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1433,8 +1433,8 @@ declare @llvm.riscv.vasub.mask.nxv1i16.i16( define @intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1457,8 +1457,8 @@ declare @llvm.riscv.vasub.nxv2i16.i16( define @intrinsic_vasub_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1481,8 +1481,8 @@ declare @llvm.riscv.vasub.mask.nxv2i16.i16( define @intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1505,8 +1505,8 @@ declare @llvm.riscv.vasub.nxv4i16.i16( define @intrinsic_vasub_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1529,8 +1529,8 @@ declare @llvm.riscv.vasub.mask.nxv4i16.i16( define @intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1553,8 +1553,8 @@ declare @llvm.riscv.vasub.nxv8i16.i16( define @intrinsic_vasub_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1577,8 +1577,8 @@ declare @llvm.riscv.vasub.mask.nxv8i16.i16( define @intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1601,8 +1601,8 @@ declare @llvm.riscv.vasub.nxv16i16.i16( define @intrinsic_vasub_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1625,8 +1625,8 @@ declare @llvm.riscv.vasub.mask.nxv16i16.i16( define @intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1649,8 +1649,8 @@ declare @llvm.riscv.vasub.nxv32i16.i16( define @intrinsic_vasub_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1673,8 +1673,8 @@ declare @llvm.riscv.vasub.mask.nxv32i16.i16( define @intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1697,8 +1697,8 @@ declare @llvm.riscv.vasub.nxv1i32.i32( define @intrinsic_vasub_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1721,8 +1721,8 @@ declare @llvm.riscv.vasub.mask.nxv1i32.i32( define @intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1745,8 +1745,8 @@ declare @llvm.riscv.vasub.nxv2i32.i32( define @intrinsic_vasub_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ declare @llvm.riscv.vasub.mask.nxv2i32.i32( define @intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1793,8 +1793,8 @@ declare @llvm.riscv.vasub.nxv4i32.i32( define @intrinsic_vasub_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1817,8 +1817,8 @@ declare @llvm.riscv.vasub.mask.nxv4i32.i32( define @intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1841,8 +1841,8 @@ declare @llvm.riscv.vasub.nxv8i32.i32( define @intrinsic_vasub_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1865,8 +1865,8 @@ declare @llvm.riscv.vasub.mask.nxv8i32.i32( define @intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1889,8 +1889,8 @@ declare @llvm.riscv.vasub.nxv16i32.i32( define @intrinsic_vasub_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1913,8 +1913,8 @@ declare @llvm.riscv.vasub.mask.nxv16i32.i32( define @intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1950,8 +1950,8 @@ define @intrinsic_vasub_vx_nxv1i64_nxv1i64_i64( @intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vasub_vx_nxv2i64_nxv2i64_i64( @intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vasub_vx_nxv4i64_nxv4i64_i64( @intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vasub_vx_nxv8i64_nxv8i64_i64( @intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64( @llvm.riscv.vasubu.nxv1i8.nxv1i8( define @intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -37,8 +37,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i8.nxv1i8( define @intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vasubu.nxv2i8.nxv2i8( define @intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -85,8 +85,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i8.nxv2i8( define @intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -109,8 +109,8 @@ declare @llvm.riscv.vasubu.nxv4i8.nxv4i8( define @intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i8.nxv4i8( define @intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -157,8 +157,8 @@ declare @llvm.riscv.vasubu.nxv8i8.nxv8i8( define @intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -181,8 +181,8 @@ declare @llvm.riscv.vasubu.mask.nxv8i8.nxv8i8( define @intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -205,8 +205,8 @@ declare @llvm.riscv.vasubu.nxv16i8.nxv16i8( define @intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vasubu.mask.nxv16i8.nxv16i8( define @intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -253,8 +253,8 @@ declare @llvm.riscv.vasubu.nxv32i8.nxv32i8( define @intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -277,8 +277,8 @@ declare @llvm.riscv.vasubu.mask.nxv32i8.nxv32i8( define @intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -301,8 +301,8 @@ declare @llvm.riscv.vasubu.nxv64i8.nxv64i8( define @intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -326,8 +326,8 @@ define @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8( @llvm.riscv.vasubu.nxv1i16.nxv1i16( define @intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -374,8 +374,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i16.nxv1i16( define @intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -398,8 +398,8 @@ declare @llvm.riscv.vasubu.nxv2i16.nxv2i16( define @intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -422,8 +422,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i16.nxv2i16( define @intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -446,8 +446,8 @@ declare @llvm.riscv.vasubu.nxv4i16.nxv4i16( define @intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -470,8 +470,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i16.nxv4i16( define @intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -494,8 +494,8 @@ declare @llvm.riscv.vasubu.nxv8i16.nxv8i16( define @intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -518,8 +518,8 @@ declare @llvm.riscv.vasubu.mask.nxv8i16.nxv8i16( define @intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -542,8 +542,8 @@ declare @llvm.riscv.vasubu.nxv16i16.nxv16i16( define @intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -566,8 +566,8 @@ declare @llvm.riscv.vasubu.mask.nxv16i16.nxv16i16( define @intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -590,8 +590,8 @@ declare @llvm.riscv.vasubu.nxv32i16.nxv32i16( define @intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -615,8 +615,8 @@ define @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16( ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -639,8 +639,8 @@ declare @llvm.riscv.vasubu.nxv1i32.nxv1i32( define @intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i32.nxv1i32( define @intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -687,8 +687,8 @@ declare @llvm.riscv.vasubu.nxv2i32.nxv2i32( define @intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -711,8 +711,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i32.nxv2i32( define @intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -735,8 +735,8 @@ declare @llvm.riscv.vasubu.nxv4i32.nxv4i32( define @intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -759,8 +759,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i32.nxv4i32( define @intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -783,8 +783,8 @@ declare @llvm.riscv.vasubu.nxv8i32.nxv8i32( define @intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -807,8 +807,8 @@ declare @llvm.riscv.vasubu.mask.nxv8i32.nxv8i32( define @intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vasubu.nxv16i32.nxv16i32( define @intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -856,8 +856,8 @@ define @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32( ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -880,8 +880,8 @@ declare @llvm.riscv.vasubu.nxv1i64.nxv1i64( define @intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -904,8 +904,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i64.nxv1i64( define @intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -928,8 +928,8 @@ declare @llvm.riscv.vasubu.nxv2i64.nxv2i64( define @intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -952,8 +952,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i64.nxv2i64( define @intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -976,8 +976,8 @@ declare @llvm.riscv.vasubu.nxv4i64.nxv4i64( define @intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -1000,8 +1000,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i64.nxv4i64( define @intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1024,8 +1024,8 @@ declare @llvm.riscv.vasubu.nxv8i64.nxv8i64( define @intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -1049,8 +1049,8 @@ define @intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64( @llvm.riscv.vasubu.nxv1i8.i8( define @intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i8.i8( define @intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1121,8 +1121,8 @@ declare @llvm.riscv.vasubu.nxv2i8.i8( define @intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1145,8 +1145,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i8.i8( define @intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1169,8 +1169,8 @@ declare @llvm.riscv.vasubu.nxv4i8.i8( define @intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1193,8 +1193,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i8.i8( define @intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1217,8 +1217,8 @@ declare @llvm.riscv.vasubu.nxv8i8.i8( define @intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1241,8 +1241,8 @@ declare @llvm.riscv.vasubu.mask.nxv8i8.i8( define @intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1265,8 +1265,8 @@ declare @llvm.riscv.vasubu.nxv16i8.i8( define @intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1289,8 +1289,8 @@ declare @llvm.riscv.vasubu.mask.nxv16i8.i8( define @intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1313,8 +1313,8 @@ declare @llvm.riscv.vasubu.nxv32i8.i8( define @intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1337,8 +1337,8 @@ declare @llvm.riscv.vasubu.mask.nxv32i8.i8( define @intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1361,8 +1361,8 @@ declare @llvm.riscv.vasubu.nxv64i8.i8( define @intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1385,8 +1385,8 @@ declare @llvm.riscv.vasubu.mask.nxv64i8.i8( define @intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1409,8 +1409,8 @@ declare @llvm.riscv.vasubu.nxv1i16.i16( define @intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1433,8 +1433,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i16.i16( define @intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1457,8 +1457,8 @@ declare @llvm.riscv.vasubu.nxv2i16.i16( define @intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1481,8 +1481,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i16.i16( define @intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1505,8 +1505,8 @@ declare @llvm.riscv.vasubu.nxv4i16.i16( define @intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1529,8 +1529,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i16.i16( define @intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1553,8 +1553,8 @@ declare @llvm.riscv.vasubu.nxv8i16.i16( define @intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1577,8 +1577,8 @@ declare @llvm.riscv.vasubu.mask.nxv8i16.i16( define @intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1601,8 +1601,8 @@ declare @llvm.riscv.vasubu.nxv16i16.i16( define @intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1625,8 +1625,8 @@ declare @llvm.riscv.vasubu.mask.nxv16i16.i16( define @intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1649,8 +1649,8 @@ declare @llvm.riscv.vasubu.nxv32i16.i16( define @intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1673,8 +1673,8 @@ declare @llvm.riscv.vasubu.mask.nxv32i16.i16( define @intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1697,8 +1697,8 @@ declare @llvm.riscv.vasubu.nxv1i32.i32( define @intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1721,8 +1721,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i32.i32( define @intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1745,8 +1745,8 @@ declare @llvm.riscv.vasubu.nxv2i32.i32( define @intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i32.i32( define @intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1793,8 +1793,8 @@ declare @llvm.riscv.vasubu.nxv4i32.i32( define @intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1817,8 +1817,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i32.i32( define @intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1841,8 +1841,8 @@ declare @llvm.riscv.vasubu.nxv8i32.i32( define @intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1865,8 +1865,8 @@ declare @llvm.riscv.vasubu.mask.nxv8i32.i32( define @intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1889,8 +1889,8 @@ declare @llvm.riscv.vasubu.nxv16i32.i32( define @intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1913,8 +1913,8 @@ declare @llvm.riscv.vasubu.mask.nxv16i32.i32( define @intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1950,8 +1950,8 @@ define @intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64( @intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64( @llvm.riscv.vfadd.nxv1f16.nxv1f16( define @intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv1f16.nxv1f16( @@ -48,10 +48,10 @@ declare @llvm.riscv.vfadd.mask.nxv1f16.nxv1f16( define @intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv1f16.nxv1f16( @@ -73,10 +73,10 @@ declare @llvm.riscv.vfadd.nxv2f16.nxv2f16( define @intrinsic_vfadd_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv2f16.nxv2f16( @@ -98,10 +98,10 @@ declare @llvm.riscv.vfadd.mask.nxv2f16.nxv2f16( define @intrinsic_vfadd_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv2f16.nxv2f16( @@ -123,10 +123,10 @@ declare @llvm.riscv.vfadd.nxv4f16.nxv4f16( define @intrinsic_vfadd_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv4f16.nxv4f16( @@ -148,10 +148,10 @@ declare @llvm.riscv.vfadd.mask.nxv4f16.nxv4f16( define @intrinsic_vfadd_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv4f16.nxv4f16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfadd.nxv8f16.nxv8f16( define @intrinsic_vfadd_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv8f16.nxv8f16( @@ -198,10 +198,10 @@ declare @llvm.riscv.vfadd.mask.nxv8f16.nxv8f16( define @intrinsic_vfadd_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv8f16.nxv8f16( @@ -223,10 +223,10 @@ declare @llvm.riscv.vfadd.nxv16f16.nxv16f16( define @intrinsic_vfadd_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv16f16.nxv16f16( @@ -248,10 +248,10 @@ declare @llvm.riscv.vfadd.mask.nxv16f16.nxv16f16( define @intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv16f16.nxv16f16( @@ -273,10 +273,10 @@ declare @llvm.riscv.vfadd.nxv32f16.nxv32f16( define @intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv32f16.nxv32f16( @@ -299,8 +299,8 @@ define @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16( ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -324,10 +324,10 @@ declare @llvm.riscv.vfadd.nxv1f32.nxv1f32( define @intrinsic_vfadd_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv1f32.nxv1f32( @@ -349,10 +349,10 @@ declare @llvm.riscv.vfadd.mask.nxv1f32.nxv1f32( define @intrinsic_vfadd_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv1f32.nxv1f32( @@ -374,10 +374,10 @@ declare @llvm.riscv.vfadd.nxv2f32.nxv2f32( define @intrinsic_vfadd_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv2f32.nxv2f32( @@ -399,10 +399,10 @@ declare @llvm.riscv.vfadd.mask.nxv2f32.nxv2f32( define @intrinsic_vfadd_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv2f32.nxv2f32( @@ -424,10 +424,10 @@ declare @llvm.riscv.vfadd.nxv4f32.nxv4f32( define @intrinsic_vfadd_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv4f32.nxv4f32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfadd.mask.nxv4f32.nxv4f32( define @intrinsic_vfadd_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv4f32.nxv4f32( @@ -474,10 +474,10 @@ declare @llvm.riscv.vfadd.nxv8f32.nxv8f32( define @intrinsic_vfadd_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv8f32.nxv8f32( @@ -499,10 +499,10 @@ declare @llvm.riscv.vfadd.mask.nxv8f32.nxv8f32( define @intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv8f32.nxv8f32( @@ -524,10 +524,10 @@ declare @llvm.riscv.vfadd.nxv16f32.nxv16f32( define @intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv16f32.nxv16f32( @@ -550,8 +550,8 @@ define @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32 ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -575,10 +575,10 @@ declare @llvm.riscv.vfadd.nxv1f64.nxv1f64( define @intrinsic_vfadd_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv1f64.nxv1f64( @@ -600,10 +600,10 @@ declare @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64( define @intrinsic_vfadd_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64( @@ -625,10 +625,10 @@ declare @llvm.riscv.vfadd.nxv2f64.nxv2f64( define @intrinsic_vfadd_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv2f64.nxv2f64( @@ -650,10 +650,10 @@ declare @llvm.riscv.vfadd.mask.nxv2f64.nxv2f64( define @intrinsic_vfadd_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv2f64.nxv2f64( @@ -675,10 +675,10 @@ declare @llvm.riscv.vfadd.nxv4f64.nxv4f64( define @intrinsic_vfadd_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv4f64.nxv4f64( @@ -700,10 +700,10 @@ declare @llvm.riscv.vfadd.mask.nxv4f64.nxv4f64( define @intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv4f64.nxv4f64( @@ -725,10 +725,10 @@ declare @llvm.riscv.vfadd.nxv8f64.nxv8f64( define @intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv8f64.nxv8f64( @@ -751,8 +751,8 @@ define @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64( @llvm.riscv.vfadd.nxv1f16.f16( define @intrinsic_vfadd_vf_nxv1f16_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv1f16.f16( @@ -801,10 +801,10 @@ declare @llvm.riscv.vfadd.mask.nxv1f16.f16( define @intrinsic_vfadd_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv1f16.f16( @@ -826,10 +826,10 @@ declare @llvm.riscv.vfadd.nxv2f16.f16( define @intrinsic_vfadd_vf_nxv2f16_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv2f16.f16( @@ -851,10 +851,10 @@ declare @llvm.riscv.vfadd.mask.nxv2f16.f16( define @intrinsic_vfadd_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv2f16.f16( @@ -876,10 +876,10 @@ declare @llvm.riscv.vfadd.nxv4f16.f16( define @intrinsic_vfadd_vf_nxv4f16_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv4f16.f16( @@ -901,10 +901,10 @@ declare @llvm.riscv.vfadd.mask.nxv4f16.f16( define @intrinsic_vfadd_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv4f16.f16( @@ -926,10 +926,10 @@ declare @llvm.riscv.vfadd.nxv8f16.f16( define @intrinsic_vfadd_vf_nxv8f16_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv8f16.f16( @@ -951,10 +951,10 @@ declare @llvm.riscv.vfadd.mask.nxv8f16.f16( define @intrinsic_vfadd_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv8f16.f16( @@ -976,10 +976,10 @@ declare @llvm.riscv.vfadd.nxv16f16.f16( define @intrinsic_vfadd_vf_nxv16f16_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv16f16.f16( @@ -1001,10 +1001,10 @@ declare @llvm.riscv.vfadd.mask.nxv16f16.f16( define @intrinsic_vfadd_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv16f16.f16( @@ -1026,10 +1026,10 @@ declare @llvm.riscv.vfadd.nxv32f16.f16( define @intrinsic_vfadd_vf_nxv32f16_nxv32f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv32f16.f16( @@ -1051,10 +1051,10 @@ declare @llvm.riscv.vfadd.mask.nxv32f16.f16( define @intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv32f16.f16( @@ -1076,10 +1076,10 @@ declare @llvm.riscv.vfadd.nxv1f32.f32( define @intrinsic_vfadd_vf_nxv1f32_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv1f32.f32( @@ -1101,10 +1101,10 @@ declare @llvm.riscv.vfadd.mask.nxv1f32.f32( define @intrinsic_vfadd_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv1f32.f32( @@ -1126,10 +1126,10 @@ declare @llvm.riscv.vfadd.nxv2f32.f32( define @intrinsic_vfadd_vf_nxv2f32_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv2f32.f32( @@ -1151,10 +1151,10 @@ declare @llvm.riscv.vfadd.mask.nxv2f32.f32( define @intrinsic_vfadd_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv2f32.f32( @@ -1176,10 +1176,10 @@ declare @llvm.riscv.vfadd.nxv4f32.f32( define @intrinsic_vfadd_vf_nxv4f32_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv4f32.f32( @@ -1201,10 +1201,10 @@ declare @llvm.riscv.vfadd.mask.nxv4f32.f32( define @intrinsic_vfadd_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv4f32.f32( @@ -1226,10 +1226,10 @@ declare @llvm.riscv.vfadd.nxv8f32.f32( define @intrinsic_vfadd_vf_nxv8f32_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv8f32.f32( @@ -1251,10 +1251,10 @@ declare @llvm.riscv.vfadd.mask.nxv8f32.f32( define @intrinsic_vfadd_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv8f32.f32( @@ -1276,10 +1276,10 @@ declare @llvm.riscv.vfadd.nxv16f32.f32( define @intrinsic_vfadd_vf_nxv16f32_nxv16f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv16f32.f32( @@ -1301,10 +1301,10 @@ declare @llvm.riscv.vfadd.mask.nxv16f32.f32( define @intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv16f32.f32( @@ -1326,10 +1326,10 @@ declare @llvm.riscv.vfadd.nxv1f64.f64( define @intrinsic_vfadd_vf_nxv1f64_nxv1f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv1f64.f64( @@ -1351,10 +1351,10 @@ declare @llvm.riscv.vfadd.mask.nxv1f64.f64( define @intrinsic_vfadd_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv1f64.f64( @@ -1376,10 +1376,10 @@ declare @llvm.riscv.vfadd.nxv2f64.f64( define @intrinsic_vfadd_vf_nxv2f64_nxv2f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv2f64.f64( @@ -1401,10 +1401,10 @@ declare @llvm.riscv.vfadd.mask.nxv2f64.f64( define @intrinsic_vfadd_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv2f64.f64( @@ -1426,10 +1426,10 @@ declare @llvm.riscv.vfadd.nxv4f64.f64( define @intrinsic_vfadd_vf_nxv4f64_nxv4f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv4f64.f64( @@ -1451,10 +1451,10 @@ declare @llvm.riscv.vfadd.mask.nxv4f64.f64( define @intrinsic_vfadd_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv4f64.f64( @@ -1476,10 +1476,10 @@ declare @llvm.riscv.vfadd.nxv8f64.f64( define @intrinsic_vfadd_vf_nxv8f64_nxv8f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv8f64.f64( @@ -1501,10 +1501,10 @@ declare @llvm.riscv.vfadd.mask.nxv8f64.f64( define @intrinsic_vfadd_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv8f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll index 626848839b07..bc8440920cd8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( define @intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( @@ -35,10 +35,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16( define @intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16( @@ -58,10 +58,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16( define @intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16( @@ -81,10 +81,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16( define @intrinsic_vfcvt_mask_f.x.v_nxv2f16_nxv2i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16( @@ -104,10 +104,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16( define @intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16( @@ -127,10 +127,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16( define @intrinsic_vfcvt_mask_f.x.v_nxv4f16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16( @@ -150,10 +150,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16( define @intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16( define @intrinsic_vfcvt_mask_f.x.v_nxv8f16_nxv8i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16( @@ -196,10 +196,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16( define @intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16( @@ -219,10 +219,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16( define @intrinsic_vfcvt_mask_f.x.v_nxv16f16_nxv16i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16( @@ -242,10 +242,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16( define @intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16( @@ -265,10 +265,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16( define @intrinsic_vfcvt_mask_f.x.v_nxv32f16_nxv32i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32( define @intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32( @@ -311,10 +311,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32( define @intrinsic_vfcvt_mask_f.x.v_nxv1f32_nxv1i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32( @@ -334,10 +334,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32( define @intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32( @@ -357,10 +357,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32( define @intrinsic_vfcvt_mask_f.x.v_nxv2f32_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32( @@ -380,10 +380,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32( define @intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32( @@ -403,10 +403,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32( define @intrinsic_vfcvt_mask_f.x.v_nxv4f32_nxv4i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32( @@ -426,10 +426,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32( define @intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32( define @intrinsic_vfcvt_mask_f.x.v_nxv8f32_nxv8i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32( define @intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32( @@ -495,10 +495,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32( define @intrinsic_vfcvt_mask_f.x.v_nxv16f32_nxv16i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32( @@ -518,10 +518,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64( define @intrinsic_vfcvt_f.x.v_nxv1f64_nxv1i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64( @@ -541,10 +541,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64( define @intrinsic_vfcvt_mask_f.x.v_nxv1f64_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64( @@ -564,10 +564,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64( define @intrinsic_vfcvt_f.x.v_nxv2f64_nxv2i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64( @@ -587,10 +587,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64( define @intrinsic_vfcvt_mask_f.x.v_nxv2f64_nxv2i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64( @@ -610,10 +610,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64( define @intrinsic_vfcvt_f.x.v_nxv4f64_nxv4i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64( @@ -633,10 +633,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64( define @intrinsic_vfcvt_mask_f.x.v_nxv4f64_nxv4i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64( @@ -656,10 +656,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64( define @intrinsic_vfcvt_f.x.v_nxv8f64_nxv8i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64( @@ -679,10 +679,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64( define @intrinsic_vfcvt_mask_f.x.v_nxv8f64_nxv8i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll index 9109df44ec7f..9cf47f993ee4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( define @intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( @@ -35,10 +35,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16( define @intrinsic_vfcvt_mask_f.xu.v_nxv1f16_nxv1i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16( @@ -58,10 +58,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16( define @intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16( @@ -81,10 +81,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16( define @intrinsic_vfcvt_mask_f.xu.v_nxv2f16_nxv2i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16( @@ -104,10 +104,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16( define @intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16( @@ -127,10 +127,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16( define @intrinsic_vfcvt_mask_f.xu.v_nxv4f16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16( @@ -150,10 +150,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16( define @intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16( define @intrinsic_vfcvt_mask_f.xu.v_nxv8f16_nxv8i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16( @@ -196,10 +196,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16( define @intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16( @@ -219,10 +219,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16( define @intrinsic_vfcvt_mask_f.xu.v_nxv16f16_nxv16i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16( @@ -242,10 +242,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16( define @intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16( @@ -265,10 +265,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16( define @intrinsic_vfcvt_mask_f.xu.v_nxv32f16_nxv32i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32( define @intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32( @@ -311,10 +311,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32( define @intrinsic_vfcvt_mask_f.xu.v_nxv1f32_nxv1i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32( @@ -334,10 +334,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32( define @intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32( @@ -357,10 +357,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32( define @intrinsic_vfcvt_mask_f.xu.v_nxv2f32_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32( @@ -380,10 +380,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32( define @intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32( @@ -403,10 +403,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32( define @intrinsic_vfcvt_mask_f.xu.v_nxv4f32_nxv4i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32( @@ -426,10 +426,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32( define @intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32( define @intrinsic_vfcvt_mask_f.xu.v_nxv8f32_nxv8i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32( define @intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32( @@ -495,10 +495,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32( define @intrinsic_vfcvt_mask_f.xu.v_nxv16f32_nxv16i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32( @@ -518,10 +518,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64( define @intrinsic_vfcvt_f.xu.v_nxv1f64_nxv1i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64( @@ -541,10 +541,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64( define @intrinsic_vfcvt_mask_f.xu.v_nxv1f64_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64( @@ -564,10 +564,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64( define @intrinsic_vfcvt_f.xu.v_nxv2f64_nxv2i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64( @@ -587,10 +587,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64( define @intrinsic_vfcvt_mask_f.xu.v_nxv2f64_nxv2i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64( @@ -610,10 +610,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64( define @intrinsic_vfcvt_f.xu.v_nxv4f64_nxv4i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64( @@ -633,10 +633,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64( define @intrinsic_vfcvt_mask_f.xu.v_nxv4f64_nxv4i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64( @@ -656,10 +656,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64( define @intrinsic_vfcvt_f.xu.v_nxv8f64_nxv8i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64( @@ -679,10 +679,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64( define @intrinsic_vfcvt_mask_f.xu.v_nxv8f64_nxv8i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll index 1147ec331b78..68a85530ea24 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( define @intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( @@ -35,10 +35,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16( define @intrinsic_vfcvt_mask_x.f.v_nxv1i16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16( @@ -58,10 +58,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16( define @intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16( @@ -81,10 +81,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16( define @intrinsic_vfcvt_mask_x.f.v_nxv2i16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16( @@ -104,10 +104,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16( define @intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16( @@ -127,10 +127,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16( define @intrinsic_vfcvt_mask_x.f.v_nxv4i16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16( @@ -150,10 +150,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16( define @intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16( define @intrinsic_vfcvt_mask_x.f.v_nxv8i16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16( @@ -196,10 +196,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16( define @intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16( @@ -219,10 +219,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16( define @intrinsic_vfcvt_mask_x.f.v_nxv16i16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv16i16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16( @@ -242,10 +242,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16( define @intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16( @@ -265,10 +265,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16( define @intrinsic_vfcvt_mask_x.f.v_nxv32i16_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv32i16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32( define @intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32( @@ -311,10 +311,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32( define @intrinsic_vfcvt_mask_x.f.v_nxv1i32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32( @@ -334,10 +334,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32( define @intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32( @@ -357,10 +357,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32( define @intrinsic_vfcvt_mask_x.f.v_nxv2i32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32( @@ -380,10 +380,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32( define @intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32( @@ -403,10 +403,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32( define @intrinsic_vfcvt_mask_x.f.v_nxv4i32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32( @@ -426,10 +426,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32( define @intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32( define @intrinsic_vfcvt_mask_x.f.v_nxv8i32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32( define @intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32( @@ -495,10 +495,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32( define @intrinsic_vfcvt_mask_x.f.v_nxv16i32_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv16i32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32( @@ -518,10 +518,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64( define @intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64( @@ -541,10 +541,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64( define @intrinsic_vfcvt_mask_x.f.v_nxv1i64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64( @@ -564,10 +564,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64( define @intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64( @@ -587,10 +587,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64( define @intrinsic_vfcvt_mask_x.f.v_nxv2i64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64( @@ -610,10 +610,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64( define @intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64( @@ -633,10 +633,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64( define @intrinsic_vfcvt_mask_x.f.v_nxv4i64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64( @@ -656,10 +656,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64( define @intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64( @@ -679,10 +679,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64( define @intrinsic_vfcvt_mask_x.f.v_nxv8i64_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll index cd227196b4f4..93716ba7f451 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( define @intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( @@ -35,10 +35,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16( define @intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16( @@ -58,10 +58,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16( define @intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16( @@ -81,10 +81,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16( define @intrinsic_vfcvt_mask_xu.f.v_nxv2i16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16( @@ -104,10 +104,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16( define @intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16( @@ -127,10 +127,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16( define @intrinsic_vfcvt_mask_xu.f.v_nxv4i16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16( @@ -150,10 +150,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16( define @intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16( define @intrinsic_vfcvt_mask_xu.f.v_nxv8i16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16( @@ -196,10 +196,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16( define @intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16( @@ -219,10 +219,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16( define @intrinsic_vfcvt_mask_xu.f.v_nxv16i16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv16i16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16( @@ -242,10 +242,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16( define @intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16( @@ -265,10 +265,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16( define @intrinsic_vfcvt_mask_xu.f.v_nxv32i16_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv32i16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32( define @intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32( @@ -311,10 +311,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32( define @intrinsic_vfcvt_mask_xu.f.v_nxv1i32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32( @@ -334,10 +334,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32( define @intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32( @@ -357,10 +357,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32( define @intrinsic_vfcvt_mask_xu.f.v_nxv2i32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32( @@ -380,10 +380,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32( define @intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32( @@ -403,10 +403,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32( define @intrinsic_vfcvt_mask_xu.f.v_nxv4i32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32( @@ -426,10 +426,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32( define @intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32( define @intrinsic_vfcvt_mask_xu.f.v_nxv8i32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32( define @intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32( @@ -495,10 +495,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32( define @intrinsic_vfcvt_mask_xu.f.v_nxv16i32_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv16i32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32( @@ -518,10 +518,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64( define @intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64( @@ -541,10 +541,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64( define @intrinsic_vfcvt_mask_xu.f.v_nxv1i64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64( @@ -564,10 +564,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64( define @intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64( @@ -587,10 +587,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64( define @intrinsic_vfcvt_mask_xu.f.v_nxv2i64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64( @@ -610,10 +610,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64( define @intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64( @@ -633,10 +633,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64( define @intrinsic_vfcvt_mask_xu.f.v_nxv4i64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64( @@ -656,10 +656,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64( define @intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64( @@ -679,10 +679,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64( define @intrinsic_vfcvt_mask_xu.f.v_nxv8i64_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll index 7e77fb7dc2ed..3f67c433bcbf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16( define @intrinsic_vfdiv_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfdiv.mask.nxv1f16.nxv1f16( define @intrinsic_vfdiv_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16( define @intrinsic_vfdiv_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfdiv.mask.nxv2f16.nxv2f16( define @intrinsic_vfdiv_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16( define @intrinsic_vfdiv_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfdiv.mask.nxv4f16.nxv4f16( define @intrinsic_vfdiv_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16( define @intrinsic_vfdiv_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfdiv.mask.nxv8f16.nxv8f16( define @intrinsic_vfdiv_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfdiv.nxv16f16.nxv16f16( define @intrinsic_vfdiv_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfdiv.mask.nxv16f16.nxv16f16( define @intrinsic_vfdiv_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfdiv.nxv32f16.nxv32f16( define @intrinsic_vfdiv_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv32f16.nxv32f16( @@ -289,8 +289,8 @@ define @intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16( ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -314,10 +314,10 @@ declare @llvm.riscv.vfdiv.nxv1f32.nxv1f32( define @intrinsic_vfdiv_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv1f32.nxv1f32( @@ -339,10 +339,10 @@ declare @llvm.riscv.vfdiv.mask.nxv1f32.nxv1f32( define @intrinsic_vfdiv_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f32.nxv1f32( @@ -364,10 +364,10 @@ declare @llvm.riscv.vfdiv.nxv2f32.nxv2f32( define @intrinsic_vfdiv_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv2f32.nxv2f32( @@ -389,10 +389,10 @@ declare @llvm.riscv.vfdiv.mask.nxv2f32.nxv2f32( define @intrinsic_vfdiv_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f32.nxv2f32( @@ -414,10 +414,10 @@ declare @llvm.riscv.vfdiv.nxv4f32.nxv4f32( define @intrinsic_vfdiv_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv4f32.nxv4f32( @@ -439,10 +439,10 @@ declare @llvm.riscv.vfdiv.mask.nxv4f32.nxv4f32( define @intrinsic_vfdiv_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f32.nxv4f32( @@ -464,10 +464,10 @@ declare @llvm.riscv.vfdiv.nxv8f32.nxv8f32( define @intrinsic_vfdiv_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv8f32.nxv8f32( @@ -489,10 +489,10 @@ declare @llvm.riscv.vfdiv.mask.nxv8f32.nxv8f32( define @intrinsic_vfdiv_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f32.nxv8f32( @@ -514,10 +514,10 @@ declare @llvm.riscv.vfdiv.nxv16f32.nxv16f32( define @intrinsic_vfdiv_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv16f32.nxv16f32( @@ -540,8 +540,8 @@ define @intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32 ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -565,10 +565,10 @@ declare @llvm.riscv.vfdiv.nxv1f64.nxv1f64( define @intrinsic_vfdiv_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv1f64.nxv1f64( @@ -590,10 +590,10 @@ declare @llvm.riscv.vfdiv.mask.nxv1f64.nxv1f64( define @intrinsic_vfdiv_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f64.nxv1f64( @@ -615,10 +615,10 @@ declare @llvm.riscv.vfdiv.nxv2f64.nxv2f64( define @intrinsic_vfdiv_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv2f64.nxv2f64( @@ -640,10 +640,10 @@ declare @llvm.riscv.vfdiv.mask.nxv2f64.nxv2f64( define @intrinsic_vfdiv_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f64.nxv2f64( @@ -665,10 +665,10 @@ declare @llvm.riscv.vfdiv.nxv4f64.nxv4f64( define @intrinsic_vfdiv_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv4f64.nxv4f64( @@ -690,10 +690,10 @@ declare @llvm.riscv.vfdiv.mask.nxv4f64.nxv4f64( define @intrinsic_vfdiv_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f64.nxv4f64( @@ -715,10 +715,10 @@ declare @llvm.riscv.vfdiv.nxv8f64.nxv8f64( define @intrinsic_vfdiv_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv8f64.nxv8f64( @@ -741,8 +741,8 @@ define @intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64_nxv8f64( @llvm.riscv.vfdiv.nxv1f16.f16( define @intrinsic_vfdiv_vf_nxv1f16_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv1f16.f16( @@ -791,10 +791,10 @@ declare @llvm.riscv.vfdiv.mask.nxv1f16.f16( define @intrinsic_vfdiv_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f16.f16( @@ -816,10 +816,10 @@ declare @llvm.riscv.vfdiv.nxv2f16.f16( define @intrinsic_vfdiv_vf_nxv2f16_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv2f16.f16( @@ -841,10 +841,10 @@ declare @llvm.riscv.vfdiv.mask.nxv2f16.f16( define @intrinsic_vfdiv_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f16.f16( @@ -866,10 +866,10 @@ declare @llvm.riscv.vfdiv.nxv4f16.f16( define @intrinsic_vfdiv_vf_nxv4f16_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv4f16.f16( @@ -891,10 +891,10 @@ declare @llvm.riscv.vfdiv.mask.nxv4f16.f16( define @intrinsic_vfdiv_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f16.f16( @@ -916,10 +916,10 @@ declare @llvm.riscv.vfdiv.nxv8f16.f16( define @intrinsic_vfdiv_vf_nxv8f16_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv8f16.f16( @@ -941,10 +941,10 @@ declare @llvm.riscv.vfdiv.mask.nxv8f16.f16( define @intrinsic_vfdiv_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f16.f16( @@ -966,10 +966,10 @@ declare @llvm.riscv.vfdiv.nxv16f16.f16( define @intrinsic_vfdiv_vf_nxv16f16_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv16f16.f16( @@ -991,10 +991,10 @@ declare @llvm.riscv.vfdiv.mask.nxv16f16.f16( define @intrinsic_vfdiv_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv16f16.f16( @@ -1016,10 +1016,10 @@ declare @llvm.riscv.vfdiv.nxv32f16.f16( define @intrinsic_vfdiv_vf_nxv32f16_nxv32f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv32f16.f16( @@ -1041,10 +1041,10 @@ declare @llvm.riscv.vfdiv.mask.nxv32f16.f16( define @intrinsic_vfdiv_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv32f16.f16( @@ -1066,10 +1066,10 @@ declare @llvm.riscv.vfdiv.nxv1f32.f32( define @intrinsic_vfdiv_vf_nxv1f32_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv1f32.f32( @@ -1091,10 +1091,10 @@ declare @llvm.riscv.vfdiv.mask.nxv1f32.f32( define @intrinsic_vfdiv_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f32.f32( @@ -1116,10 +1116,10 @@ declare @llvm.riscv.vfdiv.nxv2f32.f32( define @intrinsic_vfdiv_vf_nxv2f32_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv2f32.f32( @@ -1141,10 +1141,10 @@ declare @llvm.riscv.vfdiv.mask.nxv2f32.f32( define @intrinsic_vfdiv_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f32.f32( @@ -1166,10 +1166,10 @@ declare @llvm.riscv.vfdiv.nxv4f32.f32( define @intrinsic_vfdiv_vf_nxv4f32_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv4f32.f32( @@ -1191,10 +1191,10 @@ declare @llvm.riscv.vfdiv.mask.nxv4f32.f32( define @intrinsic_vfdiv_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f32.f32( @@ -1216,10 +1216,10 @@ declare @llvm.riscv.vfdiv.nxv8f32.f32( define @intrinsic_vfdiv_vf_nxv8f32_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv8f32.f32( @@ -1241,10 +1241,10 @@ declare @llvm.riscv.vfdiv.mask.nxv8f32.f32( define @intrinsic_vfdiv_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f32.f32( @@ -1266,10 +1266,10 @@ declare @llvm.riscv.vfdiv.nxv16f32.f32( define @intrinsic_vfdiv_vf_nxv16f32_nxv16f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv16f32.f32( @@ -1291,10 +1291,10 @@ declare @llvm.riscv.vfdiv.mask.nxv16f32.f32( define @intrinsic_vfdiv_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv16f32.f32( @@ -1316,10 +1316,10 @@ declare @llvm.riscv.vfdiv.nxv1f64.f64( define @intrinsic_vfdiv_vf_nxv1f64_nxv1f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv1f64.f64( @@ -1341,10 +1341,10 @@ declare @llvm.riscv.vfdiv.mask.nxv1f64.f64( define @intrinsic_vfdiv_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f64.f64( @@ -1366,10 +1366,10 @@ declare @llvm.riscv.vfdiv.nxv2f64.f64( define @intrinsic_vfdiv_vf_nxv2f64_nxv2f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv2f64.f64( @@ -1391,10 +1391,10 @@ declare @llvm.riscv.vfdiv.mask.nxv2f64.f64( define @intrinsic_vfdiv_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f64.f64( @@ -1416,10 +1416,10 @@ declare @llvm.riscv.vfdiv.nxv4f64.f64( define @intrinsic_vfdiv_vf_nxv4f64_nxv4f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv4f64.f64( @@ -1441,10 +1441,10 @@ declare @llvm.riscv.vfdiv.mask.nxv4f64.f64( define @intrinsic_vfdiv_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f64.f64( @@ -1466,10 +1466,10 @@ declare @llvm.riscv.vfdiv.nxv8f64.f64( define @intrinsic_vfdiv_vf_nxv8f64_nxv8f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv8f64.f64( @@ -1491,10 +1491,10 @@ declare @llvm.riscv.vfdiv.mask.nxv8f64.f64( define @intrinsic_vfdiv_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmacc.ll b/llvm/test/CodeGen/RISCV/rvv/vfmacc.ll index 73d0178a939c..5586b52b64ec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmacc.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16( define @intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( define @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16( define @intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16( define @intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16( define @intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16( define @intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16( define @intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16( define @intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfmacc.nxv16f16.nxv16f16( define @intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16( define @intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfmacc.nxv1f32.nxv1f32( define @intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32( define @intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfmacc.nxv2f32.nxv2f32( define @intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32( define @intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfmacc.nxv4f32.nxv4f32( define @intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32( define @intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfmacc.nxv8f32.nxv8f32( define @intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32( define @intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfmacc.nxv1f64.nxv1f64( define @intrinsic_vfmacc_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64( define @intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfmacc.nxv2f64.nxv2f64( define @intrinsic_vfmacc_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64( define @intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfmacc.nxv4f64.nxv4f64( define @intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64( define @intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfmacc.nxv1f16.f16( define @intrinsic_vfmacc_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfmacc.mask.nxv1f16.f16( define @intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfmacc.nxv2f16.f16( define @intrinsic_vfmacc_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfmacc.mask.nxv2f16.f16( define @intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfmacc.nxv4f16.f16( define @intrinsic_vfmacc_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfmacc.mask.nxv4f16.f16( define @intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfmacc.nxv8f16.f16( define @intrinsic_vfmacc_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfmacc.mask.nxv8f16.f16( define @intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfmacc.nxv16f16.f16( define @intrinsic_vfmacc_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfmacc.mask.nxv16f16.f16( define @intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfmacc.nxv1f32.f32( define @intrinsic_vfmacc_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfmacc.mask.nxv1f32.f32( define @intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfmacc.nxv2f32.f32( define @intrinsic_vfmacc_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfmacc.mask.nxv2f32.f32( define @intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfmacc.nxv4f32.f32( define @intrinsic_vfmacc_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfmacc.mask.nxv4f32.f32( define @intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfmacc.nxv8f32.f32( define @intrinsic_vfmacc_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfmacc.mask.nxv8f32.f32( define @intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfmacc.nxv1f64.f64( define @intrinsic_vfmacc_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfmacc.mask.nxv1f64.f64( define @intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfmacc.nxv2f64.f64( define @intrinsic_vfmacc_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfmacc.mask.nxv2f64.f64( define @intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfmacc.nxv4f64.f64( define @intrinsic_vfmacc_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfmacc.mask.nxv4f64.f64( define @intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmadd.ll b/llvm/test/CodeGen/RISCV/rvv/vfmadd.ll index caad65c78e66..c44690d23f08 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmadd.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16( define @intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16( define @intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16( define @intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16( define @intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16( define @intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16( define @intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16( define @intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16( define @intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfmadd.nxv16f16.nxv16f16( define @intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16( define @intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfmadd.nxv1f32.nxv1f32( define @intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32( define @intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfmadd.nxv2f32.nxv2f32( define @intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32( define @intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfmadd.nxv4f32.nxv4f32( define @intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32( define @intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfmadd.nxv8f32.nxv8f32( define @intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32( define @intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfmadd.nxv1f64.nxv1f64( define @intrinsic_vfmadd_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64( define @intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfmadd.nxv2f64.nxv2f64( define @intrinsic_vfmadd_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64( define @intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfmadd.nxv4f64.nxv4f64( define @intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64( define @intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfmadd.nxv1f16.f16( define @intrinsic_vfmadd_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfmadd.mask.nxv1f16.f16( define @intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfmadd.nxv2f16.f16( define @intrinsic_vfmadd_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfmadd.mask.nxv2f16.f16( define @intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfmadd.nxv4f16.f16( define @intrinsic_vfmadd_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfmadd.mask.nxv4f16.f16( define @intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfmadd.nxv8f16.f16( define @intrinsic_vfmadd_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfmadd.mask.nxv8f16.f16( define @intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfmadd.nxv16f16.f16( define @intrinsic_vfmadd_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfmadd.mask.nxv16f16.f16( define @intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfmadd.nxv1f32.f32( define @intrinsic_vfmadd_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfmadd.mask.nxv1f32.f32( define @intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfmadd.nxv2f32.f32( define @intrinsic_vfmadd_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfmadd.mask.nxv2f32.f32( define @intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfmadd.nxv4f32.f32( define @intrinsic_vfmadd_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfmadd.mask.nxv4f32.f32( define @intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfmadd.nxv8f32.f32( define @intrinsic_vfmadd_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfmadd.mask.nxv8f32.f32( define @intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfmadd.nxv1f64.f64( define @intrinsic_vfmadd_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfmadd.mask.nxv1f64.f64( define @intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfmadd.nxv2f64.f64( define @intrinsic_vfmadd_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfmadd.mask.nxv2f64.f64( define @intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfmadd.nxv4f64.f64( define @intrinsic_vfmadd_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfmadd.mask.nxv4f64.f64( define @intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsac.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsac.ll index e668a70050e4..4eac7b63fd88 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsac.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsac.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16( define @intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16( define @intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16( define @intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16( define @intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16( define @intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16( define @intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16( define @intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16( define @intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfmsac.nxv16f16.nxv16f16( define @intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16( define @intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfmsac.nxv1f32.nxv1f32( define @intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32( define @intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfmsac.nxv2f32.nxv2f32( define @intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32( define @intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfmsac.nxv4f32.nxv4f32( define @intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32( define @intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfmsac.nxv8f32.nxv8f32( define @intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32( define @intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfmsac.nxv1f64.nxv1f64( define @intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64( define @intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfmsac.nxv2f64.nxv2f64( define @intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64( define @intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfmsac.nxv4f64.nxv4f64( define @intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64( define @intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfmsac.nxv1f16.f16( define @intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfmsac.mask.nxv1f16.f16( define @intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfmsac.nxv2f16.f16( define @intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfmsac.mask.nxv2f16.f16( define @intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfmsac.nxv4f16.f16( define @intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfmsac.mask.nxv4f16.f16( define @intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfmsac.nxv8f16.f16( define @intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfmsac.mask.nxv8f16.f16( define @intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfmsac.nxv16f16.f16( define @intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfmsac.mask.nxv16f16.f16( define @intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfmsac.nxv1f32.f32( define @intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfmsac.mask.nxv1f32.f32( define @intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfmsac.nxv2f32.f32( define @intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfmsac.mask.nxv2f32.f32( define @intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfmsac.nxv4f32.f32( define @intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfmsac.mask.nxv4f32.f32( define @intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfmsac.nxv8f32.f32( define @intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfmsac.mask.nxv8f32.f32( define @intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfmsac.nxv1f64.f64( define @intrinsic_vfmsac_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfmsac.mask.nxv1f64.f64( define @intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfmsac.nxv2f64.f64( define @intrinsic_vfmsac_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfmsac.mask.nxv2f64.f64( define @intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfmsac.nxv4f64.f64( define @intrinsic_vfmsac_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfmsac.mask.nxv4f64.f64( define @intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsub.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsub.ll index 4cda25e18911..626b40e132c7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsub.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16( define @intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16( define @intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16( define @intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16( define @intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16( define @intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16( define @intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16( define @intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16( define @intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfmsub.nxv16f16.nxv16f16( define @intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16( define @intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfmsub.nxv1f32.nxv1f32( define @intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32( define @intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfmsub.nxv2f32.nxv2f32( define @intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32( define @intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfmsub.nxv4f32.nxv4f32( define @intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32( define @intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfmsub.nxv8f32.nxv8f32( define @intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32( define @intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfmsub.nxv1f64.nxv1f64( define @intrinsic_vfmsub_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64( define @intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfmsub.nxv2f64.nxv2f64( define @intrinsic_vfmsub_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64( define @intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfmsub.nxv4f64.nxv4f64( define @intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64( define @intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfmsub.nxv1f16.f16( define @intrinsic_vfmsub_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfmsub.mask.nxv1f16.f16( define @intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfmsub.nxv2f16.f16( define @intrinsic_vfmsub_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfmsub.mask.nxv2f16.f16( define @intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfmsub.nxv4f16.f16( define @intrinsic_vfmsub_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfmsub.mask.nxv4f16.f16( define @intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfmsub.nxv8f16.f16( define @intrinsic_vfmsub_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfmsub.mask.nxv8f16.f16( define @intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfmsub.nxv16f16.f16( define @intrinsic_vfmsub_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfmsub.mask.nxv16f16.f16( define @intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfmsub.nxv1f32.f32( define @intrinsic_vfmsub_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfmsub.mask.nxv1f32.f32( define @intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfmsub.nxv2f32.f32( define @intrinsic_vfmsub_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfmsub.mask.nxv2f32.f32( define @intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfmsub.nxv4f32.f32( define @intrinsic_vfmsub_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfmsub.mask.nxv4f32.f32( define @intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfmsub.nxv8f32.f32( define @intrinsic_vfmsub_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfmsub.mask.nxv8f32.f32( define @intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfmsub.nxv1f64.f64( define @intrinsic_vfmsub_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfmsub.mask.nxv1f64.f64( define @intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfmsub.nxv2f64.f64( define @intrinsic_vfmsub_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfmsub.mask.nxv2f64.f64( define @intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfmsub.nxv4f64.f64( define @intrinsic_vfmsub_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfmsub.mask.nxv4f64.f64( define @intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul.ll index ee1d197e091f..b73d03fe36c7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfmul.nxv1f16.nxv1f16( define @intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfmul.mask.nxv1f16.nxv1f16( define @intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfmul.nxv2f16.nxv2f16( define @intrinsic_vfmul_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfmul.mask.nxv2f16.nxv2f16( define @intrinsic_vfmul_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfmul.nxv4f16.nxv4f16( define @intrinsic_vfmul_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfmul.mask.nxv4f16.nxv4f16( define @intrinsic_vfmul_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfmul.nxv8f16.nxv8f16( define @intrinsic_vfmul_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfmul.mask.nxv8f16.nxv8f16( define @intrinsic_vfmul_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfmul.nxv16f16.nxv16f16( define @intrinsic_vfmul_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfmul.mask.nxv16f16.nxv16f16( define @intrinsic_vfmul_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfmul.nxv32f16.nxv32f16( define @intrinsic_vfmul_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv32f16.nxv32f16( @@ -289,8 +289,8 @@ define @intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16( ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -314,10 +314,10 @@ declare @llvm.riscv.vfmul.nxv1f32.nxv1f32( define @intrinsic_vfmul_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv1f32.nxv1f32( @@ -339,10 +339,10 @@ declare @llvm.riscv.vfmul.mask.nxv1f32.nxv1f32( define @intrinsic_vfmul_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv1f32.nxv1f32( @@ -364,10 +364,10 @@ declare @llvm.riscv.vfmul.nxv2f32.nxv2f32( define @intrinsic_vfmul_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv2f32.nxv2f32( @@ -389,10 +389,10 @@ declare @llvm.riscv.vfmul.mask.nxv2f32.nxv2f32( define @intrinsic_vfmul_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv2f32.nxv2f32( @@ -414,10 +414,10 @@ declare @llvm.riscv.vfmul.nxv4f32.nxv4f32( define @intrinsic_vfmul_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv4f32.nxv4f32( @@ -439,10 +439,10 @@ declare @llvm.riscv.vfmul.mask.nxv4f32.nxv4f32( define @intrinsic_vfmul_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv4f32.nxv4f32( @@ -464,10 +464,10 @@ declare @llvm.riscv.vfmul.nxv8f32.nxv8f32( define @intrinsic_vfmul_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv8f32.nxv8f32( @@ -489,10 +489,10 @@ declare @llvm.riscv.vfmul.mask.nxv8f32.nxv8f32( define @intrinsic_vfmul_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv8f32.nxv8f32( @@ -514,10 +514,10 @@ declare @llvm.riscv.vfmul.nxv16f32.nxv16f32( define @intrinsic_vfmul_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv16f32.nxv16f32( @@ -540,8 +540,8 @@ define @intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32 ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -565,10 +565,10 @@ declare @llvm.riscv.vfmul.nxv1f64.nxv1f64( define @intrinsic_vfmul_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv1f64.nxv1f64( @@ -590,10 +590,10 @@ declare @llvm.riscv.vfmul.mask.nxv1f64.nxv1f64( define @intrinsic_vfmul_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv1f64.nxv1f64( @@ -615,10 +615,10 @@ declare @llvm.riscv.vfmul.nxv2f64.nxv2f64( define @intrinsic_vfmul_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv2f64.nxv2f64( @@ -640,10 +640,10 @@ declare @llvm.riscv.vfmul.mask.nxv2f64.nxv2f64( define @intrinsic_vfmul_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv2f64.nxv2f64( @@ -665,10 +665,10 @@ declare @llvm.riscv.vfmul.nxv4f64.nxv4f64( define @intrinsic_vfmul_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv4f64.nxv4f64( @@ -690,10 +690,10 @@ declare @llvm.riscv.vfmul.mask.nxv4f64.nxv4f64( define @intrinsic_vfmul_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv4f64.nxv4f64( @@ -715,10 +715,10 @@ declare @llvm.riscv.vfmul.nxv8f64.nxv8f64( define @intrinsic_vfmul_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv8f64.nxv8f64( @@ -741,8 +741,8 @@ define @intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64( @llvm.riscv.vfmul.nxv1f16.f16( define @intrinsic_vfmul_vf_nxv1f16_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv1f16.f16( @@ -791,10 +791,10 @@ declare @llvm.riscv.vfmul.mask.nxv1f16.f16( define @intrinsic_vfmul_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv1f16.f16( @@ -816,10 +816,10 @@ declare @llvm.riscv.vfmul.nxv2f16.f16( define @intrinsic_vfmul_vf_nxv2f16_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv2f16.f16( @@ -841,10 +841,10 @@ declare @llvm.riscv.vfmul.mask.nxv2f16.f16( define @intrinsic_vfmul_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv2f16.f16( @@ -866,10 +866,10 @@ declare @llvm.riscv.vfmul.nxv4f16.f16( define @intrinsic_vfmul_vf_nxv4f16_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv4f16.f16( @@ -891,10 +891,10 @@ declare @llvm.riscv.vfmul.mask.nxv4f16.f16( define @intrinsic_vfmul_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv4f16.f16( @@ -916,10 +916,10 @@ declare @llvm.riscv.vfmul.nxv8f16.f16( define @intrinsic_vfmul_vf_nxv8f16_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv8f16.f16( @@ -941,10 +941,10 @@ declare @llvm.riscv.vfmul.mask.nxv8f16.f16( define @intrinsic_vfmul_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv8f16.f16( @@ -966,10 +966,10 @@ declare @llvm.riscv.vfmul.nxv16f16.f16( define @intrinsic_vfmul_vf_nxv16f16_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv16f16.f16( @@ -991,10 +991,10 @@ declare @llvm.riscv.vfmul.mask.nxv16f16.f16( define @intrinsic_vfmul_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv16f16.f16( @@ -1016,10 +1016,10 @@ declare @llvm.riscv.vfmul.nxv32f16.f16( define @intrinsic_vfmul_vf_nxv32f16_nxv32f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv32f16.f16( @@ -1041,10 +1041,10 @@ declare @llvm.riscv.vfmul.mask.nxv32f16.f16( define @intrinsic_vfmul_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv32f16.f16( @@ -1066,10 +1066,10 @@ declare @llvm.riscv.vfmul.nxv1f32.f32( define @intrinsic_vfmul_vf_nxv1f32_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv1f32.f32( @@ -1091,10 +1091,10 @@ declare @llvm.riscv.vfmul.mask.nxv1f32.f32( define @intrinsic_vfmul_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv1f32.f32( @@ -1116,10 +1116,10 @@ declare @llvm.riscv.vfmul.nxv2f32.f32( define @intrinsic_vfmul_vf_nxv2f32_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv2f32.f32( @@ -1141,10 +1141,10 @@ declare @llvm.riscv.vfmul.mask.nxv2f32.f32( define @intrinsic_vfmul_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv2f32.f32( @@ -1166,10 +1166,10 @@ declare @llvm.riscv.vfmul.nxv4f32.f32( define @intrinsic_vfmul_vf_nxv4f32_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv4f32.f32( @@ -1191,10 +1191,10 @@ declare @llvm.riscv.vfmul.mask.nxv4f32.f32( define @intrinsic_vfmul_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv4f32.f32( @@ -1216,10 +1216,10 @@ declare @llvm.riscv.vfmul.nxv8f32.f32( define @intrinsic_vfmul_vf_nxv8f32_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv8f32.f32( @@ -1241,10 +1241,10 @@ declare @llvm.riscv.vfmul.mask.nxv8f32.f32( define @intrinsic_vfmul_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv8f32.f32( @@ -1266,10 +1266,10 @@ declare @llvm.riscv.vfmul.nxv16f32.f32( define @intrinsic_vfmul_vf_nxv16f32_nxv16f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv16f32.f32( @@ -1291,10 +1291,10 @@ declare @llvm.riscv.vfmul.mask.nxv16f32.f32( define @intrinsic_vfmul_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv16f32.f32( @@ -1316,10 +1316,10 @@ declare @llvm.riscv.vfmul.nxv1f64.f64( define @intrinsic_vfmul_vf_nxv1f64_nxv1f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv1f64.f64( @@ -1341,10 +1341,10 @@ declare @llvm.riscv.vfmul.mask.nxv1f64.f64( define @intrinsic_vfmul_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv1f64.f64( @@ -1366,10 +1366,10 @@ declare @llvm.riscv.vfmul.nxv2f64.f64( define @intrinsic_vfmul_vf_nxv2f64_nxv2f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv2f64.f64( @@ -1391,10 +1391,10 @@ declare @llvm.riscv.vfmul.mask.nxv2f64.f64( define @intrinsic_vfmul_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv2f64.f64( @@ -1416,10 +1416,10 @@ declare @llvm.riscv.vfmul.nxv4f64.f64( define @intrinsic_vfmul_vf_nxv4f64_nxv4f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv4f64.f64( @@ -1441,10 +1441,10 @@ declare @llvm.riscv.vfmul.mask.nxv4f64.f64( define @intrinsic_vfmul_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv4f64.f64( @@ -1466,10 +1466,10 @@ declare @llvm.riscv.vfmul.nxv8f64.f64( define @intrinsic_vfmul_vf_nxv8f64_nxv8f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv8f64.f64( @@ -1491,10 +1491,10 @@ declare @llvm.riscv.vfmul.mask.nxv8f64.f64( define @intrinsic_vfmul_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv8f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll index 2de7d78df881..183ffa8a668a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll @@ -15,10 +15,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( define @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -39,10 +39,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32( define @intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32( @@ -62,10 +62,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32( define @intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -86,10 +86,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32( define @intrinsic_vfncvt_mask_f.f.w_nxv2f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32( @@ -109,10 +109,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32( define @intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -133,10 +133,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv4f16.nxv4f32( define @intrinsic_vfncvt_mask_f.f.w_nxv4f16_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f16_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv4f16.nxv4f32( @@ -156,10 +156,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32( define @intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -180,10 +180,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv8f16.nxv8f32( define @intrinsic_vfncvt_mask_f.f.w_nxv8f16_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f16_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv8f16.nxv8f32( @@ -203,10 +203,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32( define @intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -227,10 +227,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv16f16.nxv16f32( define @intrinsic_vfncvt_mask_f.f.w_nxv16f16_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv16f16_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv16f16.nxv16f32( @@ -250,10 +250,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64( define @intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -274,10 +274,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv1f32.nxv1f64( define @intrinsic_vfncvt_mask_f.f.w_nxv1f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f32.nxv1f64( @@ -297,10 +297,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64( define @intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -321,10 +321,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv2f32.nxv2f64( define @intrinsic_vfncvt_mask_f.f.w_nxv2f32_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f32_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f32.nxv2f64( @@ -344,10 +344,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64( define @intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -368,10 +368,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv4f32.nxv4f64( define @intrinsic_vfncvt_mask_f.f.w_nxv4f32_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f32_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv4f32.nxv4f64( @@ -391,10 +391,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64( define @intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -415,10 +415,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv8f32.nxv8f64( define @intrinsic_vfncvt_mask_f.f.w_nxv8f32_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f32_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv8f32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll index 7f2714b2fbfc..aef119faf5f7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( define @intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -36,10 +36,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32( define @intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32( @@ -59,10 +59,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32( define @intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -83,10 +83,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32( define @intrinsic_vfncvt_mask_f.x.w_nxv2f16_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32( @@ -106,10 +106,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32( define @intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -130,10 +130,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32( define @intrinsic_vfncvt_mask_f.x.w_nxv4f16_nxv4i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32( @@ -153,10 +153,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32( define @intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -177,10 +177,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32( define @intrinsic_vfncvt_mask_f.x.w_nxv8f16_nxv8i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32( @@ -200,10 +200,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32( define @intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -224,10 +224,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32( define @intrinsic_vfncvt_mask_f.x.w_nxv16f16_nxv16i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32( @@ -247,10 +247,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64( define @intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -271,10 +271,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64( define @intrinsic_vfncvt_mask_f.x.w_nxv1f32_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64( @@ -294,10 +294,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64( define @intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -318,10 +318,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64( define @intrinsic_vfncvt_mask_f.x.w_nxv2f32_nxv2i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64( @@ -341,10 +341,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64( define @intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -365,10 +365,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64( define @intrinsic_vfncvt_mask_f.x.w_nxv4f32_nxv4i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64( define @intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -412,10 +412,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64( define @intrinsic_vfncvt_mask_f.x.w_nxv8f32_nxv8i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll index 1aeee4317cb3..bc287e4bdef1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( define @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -36,10 +36,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32( define @intrinsic_vfncvt_mask_f.xu.w_nxv1f16_nxv1i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32( @@ -59,10 +59,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32( define @intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -83,10 +83,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32( define @intrinsic_vfncvt_mask_f.xu.w_nxv2f16_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32( @@ -106,10 +106,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32( define @intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -130,10 +130,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32( define @intrinsic_vfncvt_mask_f.xu.w_nxv4f16_nxv4i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32( @@ -153,10 +153,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32( define @intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -177,10 +177,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32( define @intrinsic_vfncvt_mask_f.xu.w_nxv8f16_nxv8i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32( @@ -200,10 +200,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32( define @intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -224,10 +224,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32( define @intrinsic_vfncvt_mask_f.xu.w_nxv16f16_nxv16i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32( @@ -247,10 +247,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64( define @intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -271,10 +271,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64( define @intrinsic_vfncvt_mask_f.xu.w_nxv1f32_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64( @@ -294,10 +294,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64( define @intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -318,10 +318,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64( define @intrinsic_vfncvt_mask_f.xu.w_nxv2f32_nxv2i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64( @@ -341,10 +341,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64( define @intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -365,10 +365,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64( define @intrinsic_vfncvt_mask_f.xu.w_nxv4f32_nxv4i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64( define @intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -412,10 +412,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64( define @intrinsic_vfncvt_mask_f.xu.w_nxv8f32_nxv8i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll index 8309e3fb857f..e4b39c655a10 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( define @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -36,10 +36,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16( define @intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16( @@ -59,10 +59,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16( define @intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -83,10 +83,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16( define @intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16( @@ -106,10 +106,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16( define @intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -130,10 +130,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16( define @intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16( @@ -153,10 +153,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16( define @intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -177,10 +177,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16( define @intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16( @@ -200,10 +200,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16( define @intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -224,10 +224,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16( define @intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16( @@ -247,10 +247,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16( define @intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -271,10 +271,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16( define @intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16( @@ -294,10 +294,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32( define @intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -318,10 +318,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32( define @intrinsic_vfncvt_mask_x.f.w_nxv1i16_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i16_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32( @@ -341,10 +341,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32( define @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -365,10 +365,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32( define @intrinsic_vfncvt_mask_x.f.w_nxv2i16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32( define @intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -412,10 +412,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32( define @intrinsic_vfncvt_mask_x.f.w_nxv4i16_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i16_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32( @@ -435,10 +435,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32( define @intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -459,10 +459,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32( define @intrinsic_vfncvt_mask_x.f.w_nxv8i16_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i16_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32( @@ -482,10 +482,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32( define @intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -506,10 +506,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32( define @intrinsic_vfncvt_mask_x.f.w_nxv16i16_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i16_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32( @@ -529,10 +529,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64( define @intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -553,10 +553,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64( define @intrinsic_vfncvt_mask_x.f.w_nxv1i32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64( @@ -576,10 +576,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64( define @intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -600,10 +600,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64( define @intrinsic_vfncvt_mask_x.f.w_nxv2i32_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i32_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64( @@ -623,10 +623,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64( define @intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -647,10 +647,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64( define @intrinsic_vfncvt_mask_x.f.w_nxv4i32_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i32_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64( @@ -670,10 +670,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64( define @intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -694,10 +694,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64( define @intrinsic_vfncvt_mask_x.f.w_nxv8i32_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i32_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll index 3a3abacc8fc3..fd922438d05b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( define @intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -36,10 +36,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16( define @intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16( @@ -59,10 +59,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16( define @intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -83,10 +83,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16( define @intrinsic_vfncvt_mask_xu.f.w_nxv2i8_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i8_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16( @@ -106,10 +106,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16( define @intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -130,10 +130,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16( define @intrinsic_vfncvt_mask_xu.f.w_nxv4i8_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i8_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16( @@ -153,10 +153,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16( define @intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -177,10 +177,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16( define @intrinsic_vfncvt_mask_xu.f.w_nxv8i8_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i8_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16( @@ -200,10 +200,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16( define @intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -224,10 +224,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16( define @intrinsic_vfncvt_mask_xu.f.w_nxv16i8_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv16i8_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16( @@ -247,10 +247,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16( define @intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -271,10 +271,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16( define @intrinsic_vfncvt_mask_xu.f.w_nxv32i8_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv32i8_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16( @@ -294,10 +294,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32( define @intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -318,10 +318,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32( define @intrinsic_vfncvt_mask_xu.f.w_nxv1i16_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i16_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32( @@ -341,10 +341,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32( define @intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -365,10 +365,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32( define @intrinsic_vfncvt_mask_xu.f.w_nxv2i16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32( define @intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -412,10 +412,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32( define @intrinsic_vfncvt_mask_xu.f.w_nxv4i16_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i16_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32( @@ -435,10 +435,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32( define @intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -459,10 +459,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32( define @intrinsic_vfncvt_mask_xu.f.w_nxv8i16_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i16_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32( @@ -482,10 +482,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32( define @intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -506,10 +506,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32( define @intrinsic_vfncvt_mask_xu.f.w_nxv16i16_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv16i16_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32( @@ -529,10 +529,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64( define @intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -553,10 +553,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64( define @intrinsic_vfncvt_mask_xu.f.w_nxv1i32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64( @@ -576,10 +576,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64( define @intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -600,10 +600,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64( define @intrinsic_vfncvt_mask_xu.f.w_nxv2i32_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i32_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64( @@ -623,10 +623,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64( define @intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -647,10 +647,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64( define @intrinsic_vfncvt_mask_xu.f.w_nxv4i32_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i32_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64( @@ -670,10 +670,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64( define @intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -694,10 +694,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64( define @intrinsic_vfncvt_mask_xu.f.w_nxv8i32_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i32_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll index bdfa211dfdcb..01f4715274b6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( define @intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16( define @intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16( define @intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16( define @intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16( define @intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16( define @intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16( define @intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16( define @intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfnmacc.nxv16f16.nxv16f16( define @intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16( define @intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfnmacc.nxv1f32.nxv1f32( define @intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32( define @intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfnmacc.nxv2f32.nxv2f32( define @intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32( define @intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfnmacc.nxv4f32.nxv4f32( define @intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32( define @intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfnmacc.nxv8f32.nxv8f32( define @intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32( define @intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfnmacc.nxv1f64.nxv1f64( define @intrinsic_vfnmacc_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64( define @intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfnmacc.nxv2f64.nxv2f64( define @intrinsic_vfnmacc_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64( define @intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfnmacc.nxv4f64.nxv4f64( define @intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64( define @intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfnmacc.nxv1f16.f16( define @intrinsic_vfnmacc_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv1f16.f16( define @intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfnmacc.nxv2f16.f16( define @intrinsic_vfnmacc_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv2f16.f16( define @intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfnmacc.nxv4f16.f16( define @intrinsic_vfnmacc_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv4f16.f16( define @intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfnmacc.nxv8f16.f16( define @intrinsic_vfnmacc_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv8f16.f16( define @intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfnmacc.nxv16f16.f16( define @intrinsic_vfnmacc_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv16f16.f16( define @intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfnmacc.nxv1f32.f32( define @intrinsic_vfnmacc_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv1f32.f32( define @intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfnmacc.nxv2f32.f32( define @intrinsic_vfnmacc_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv2f32.f32( define @intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfnmacc.nxv4f32.f32( define @intrinsic_vfnmacc_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv4f32.f32( define @intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfnmacc.nxv8f32.f32( define @intrinsic_vfnmacc_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv8f32.f32( define @intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfnmacc.nxv1f64.f64( define @intrinsic_vfnmacc_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv1f64.f64( define @intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfnmacc.nxv2f64.f64( define @intrinsic_vfnmacc_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv2f64.f64( define @intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfnmacc.nxv4f64.f64( define @intrinsic_vfnmacc_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv4f64.f64( define @intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll index 4eb2e7caba24..ae4cfef35e61 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( define @intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16( define @intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16( define @intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16( define @intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16( define @intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16( define @intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16( define @intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16( define @intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfnmadd.nxv16f16.nxv16f16( define @intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16( define @intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfnmadd.nxv1f32.nxv1f32( define @intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32( define @intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfnmadd.nxv2f32.nxv2f32( define @intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32( define @intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfnmadd.nxv4f32.nxv4f32( define @intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32( define @intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfnmadd.nxv8f32.nxv8f32( define @intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32( define @intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfnmadd.nxv1f64.nxv1f64( define @intrinsic_vfnmadd_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64( define @intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfnmadd.nxv2f64.nxv2f64( define @intrinsic_vfnmadd_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64( define @intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfnmadd.nxv4f64.nxv4f64( define @intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64( define @intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfnmadd.nxv1f16.f16( define @intrinsic_vfnmadd_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv1f16.f16( define @intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfnmadd.nxv2f16.f16( define @intrinsic_vfnmadd_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv2f16.f16( define @intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfnmadd.nxv4f16.f16( define @intrinsic_vfnmadd_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv4f16.f16( define @intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfnmadd.nxv8f16.f16( define @intrinsic_vfnmadd_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv8f16.f16( define @intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfnmadd.nxv16f16.f16( define @intrinsic_vfnmadd_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv16f16.f16( define @intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfnmadd.nxv1f32.f32( define @intrinsic_vfnmadd_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv1f32.f32( define @intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfnmadd.nxv2f32.f32( define @intrinsic_vfnmadd_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv2f32.f32( define @intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfnmadd.nxv4f32.f32( define @intrinsic_vfnmadd_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv4f32.f32( define @intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfnmadd.nxv8f32.f32( define @intrinsic_vfnmadd_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv8f32.f32( define @intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfnmadd.nxv1f64.f64( define @intrinsic_vfnmadd_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv1f64.f64( define @intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfnmadd.nxv2f64.f64( define @intrinsic_vfnmadd_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv2f64.f64( define @intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfnmadd.nxv4f64.f64( define @intrinsic_vfnmadd_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv4f64.f64( define @intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll index dc30540bc0af..071f546b4f60 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( define @intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16( define @intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16( define @intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16( define @intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16( define @intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16( define @intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16( define @intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16( define @intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfnmsac.nxv16f16.nxv16f16( define @intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16( define @intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfnmsac.nxv1f32.nxv1f32( define @intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32( define @intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfnmsac.nxv2f32.nxv2f32( define @intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32( define @intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfnmsac.nxv4f32.nxv4f32( define @intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32( define @intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfnmsac.nxv8f32.nxv8f32( define @intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32( define @intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfnmsac.nxv1f64.nxv1f64( define @intrinsic_vfnmsac_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64( define @intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfnmsac.nxv2f64.nxv2f64( define @intrinsic_vfnmsac_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64( define @intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfnmsac.nxv4f64.nxv4f64( define @intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64( define @intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfnmsac.nxv1f16.f16( define @intrinsic_vfnmsac_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv1f16.f16( define @intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfnmsac.nxv2f16.f16( define @intrinsic_vfnmsac_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv2f16.f16( define @intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfnmsac.nxv4f16.f16( define @intrinsic_vfnmsac_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv4f16.f16( define @intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfnmsac.nxv8f16.f16( define @intrinsic_vfnmsac_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv8f16.f16( define @intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfnmsac.nxv16f16.f16( define @intrinsic_vfnmsac_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv16f16.f16( define @intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfnmsac.nxv1f32.f32( define @intrinsic_vfnmsac_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv1f32.f32( define @intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfnmsac.nxv2f32.f32( define @intrinsic_vfnmsac_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv2f32.f32( define @intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfnmsac.nxv4f32.f32( define @intrinsic_vfnmsac_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv4f32.f32( define @intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfnmsac.nxv8f32.f32( define @intrinsic_vfnmsac_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv8f32.f32( define @intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfnmsac.nxv1f64.f64( define @intrinsic_vfnmsac_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv1f64.f64( define @intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfnmsac.nxv2f64.f64( define @intrinsic_vfnmsac_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv2f64.f64( define @intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfnmsac.nxv4f64.f64( define @intrinsic_vfnmsac_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv4f64.f64( define @intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll index cadddb016c4f..4922cf40e503 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( define @intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16( define @intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16( define @intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16( define @intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16( define @intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16( define @intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16( define @intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16( define @intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfnmsub.nxv16f16.nxv16f16( define @intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16( define @intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfnmsub.nxv1f32.nxv1f32( define @intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32( define @intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfnmsub.nxv2f32.nxv2f32( define @intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32( define @intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfnmsub.nxv4f32.nxv4f32( define @intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32( define @intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfnmsub.nxv8f32.nxv8f32( define @intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32( define @intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfnmsub.nxv1f64.nxv1f64( define @intrinsic_vfnmsub_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64( define @intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfnmsub.nxv2f64.nxv2f64( define @intrinsic_vfnmsub_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64( define @intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfnmsub.nxv4f64.nxv4f64( define @intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64( define @intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfnmsub.nxv1f16.f16( define @intrinsic_vfnmsub_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv1f16.f16( define @intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfnmsub.nxv2f16.f16( define @intrinsic_vfnmsub_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv2f16.f16( define @intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfnmsub.nxv4f16.f16( define @intrinsic_vfnmsub_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv4f16.f16( define @intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfnmsub.nxv8f16.f16( define @intrinsic_vfnmsub_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv8f16.f16( define @intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfnmsub.nxv16f16.f16( define @intrinsic_vfnmsub_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv16f16.f16( define @intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfnmsub.nxv1f32.f32( define @intrinsic_vfnmsub_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv1f32.f32( define @intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfnmsub.nxv2f32.f32( define @intrinsic_vfnmsub_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv2f32.f32( define @intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfnmsub.nxv4f32.f32( define @intrinsic_vfnmsub_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv4f32.f32( define @intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfnmsub.nxv8f32.f32( define @intrinsic_vfnmsub_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv8f32.f32( define @intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfnmsub.nxv1f64.f64( define @intrinsic_vfnmsub_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv1f64.f64( define @intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfnmsub.nxv2f64.f64( define @intrinsic_vfnmsub_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv2f64.f64( define @intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfnmsub.nxv4f64.f64( define @intrinsic_vfnmsub_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv4f64.f64( define @intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll b/llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll index f17c226ada0d..f73e7dce9212 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfrdiv.nxv1f16.f16( define @intrinsic_vfrdiv_vf_nxv1f16_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv1f16.f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv1f16.f16( define @intrinsic_vfrdiv_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv1f16.f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfrdiv.nxv2f16.f16( define @intrinsic_vfrdiv_vf_nxv2f16_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv2f16.f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv2f16.f16( define @intrinsic_vfrdiv_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv2f16.f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfrdiv.nxv4f16.f16( define @intrinsic_vfrdiv_vf_nxv4f16_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv4f16.f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv4f16.f16( define @intrinsic_vfrdiv_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv4f16.f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfrdiv.nxv8f16.f16( define @intrinsic_vfrdiv_vf_nxv8f16_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv8f16.f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv8f16.f16( define @intrinsic_vfrdiv_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv8f16.f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfrdiv.nxv16f16.f16( define @intrinsic_vfrdiv_vf_nxv16f16_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv16f16.f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv16f16.f16( define @intrinsic_vfrdiv_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv16f16.f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfrdiv.nxv32f16.f16( define @intrinsic_vfrdiv_vf_nxv32f16_nxv32f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv32f16.f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv32f16.f16( define @intrinsic_vfrdiv_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv32f16.f16( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfrdiv.nxv1f32.f32( define @intrinsic_vfrdiv_vf_nxv1f32_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv1f32.f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv1f32.f32( define @intrinsic_vfrdiv_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv1f32.f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfrdiv.nxv2f32.f32( define @intrinsic_vfrdiv_vf_nxv2f32_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv2f32.f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv2f32.f32( define @intrinsic_vfrdiv_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv2f32.f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfrdiv.nxv4f32.f32( define @intrinsic_vfrdiv_vf_nxv4f32_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv4f32.f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv4f32.f32( define @intrinsic_vfrdiv_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv4f32.f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfrdiv.nxv8f32.f32( define @intrinsic_vfrdiv_vf_nxv8f32_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv8f32.f32( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv8f32.f32( define @intrinsic_vfrdiv_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv8f32.f32( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfrdiv.nxv16f32.f32( define @intrinsic_vfrdiv_vf_nxv16f32_nxv16f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv16f32.f32( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv16f32.f32( define @intrinsic_vfrdiv_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv16f32.f32( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfrdiv.nxv1f64.f64( define @intrinsic_vfrdiv_vf_nxv1f64_nxv1f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv1f64.f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv1f64.f64( define @intrinsic_vfrdiv_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv1f64.f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfrdiv.nxv2f64.f64( define @intrinsic_vfrdiv_vf_nxv2f64_nxv2f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv2f64.f64( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv2f64.f64( define @intrinsic_vfrdiv_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv2f64.f64( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfrdiv.nxv4f64.f64( define @intrinsic_vfrdiv_vf_nxv4f64_nxv4f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv4f64.f64( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv4f64.f64( define @intrinsic_vfrdiv_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv4f64.f64( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfrdiv.nxv8f64.f64( define @intrinsic_vfrdiv_vf_nxv8f64_nxv8f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv8f64.f64( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv8f64.f64( define @intrinsic_vfrdiv_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv8f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrec7.ll b/llvm/test/CodeGen/RISCV/rvv/vfrec7.ll index 0204f0373d93..914b3b33fbe5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrec7.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrec7.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfrec7.nxv1f16( define @intrinsic_vfrec7_v_nxv1f16_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv1f16( @@ -35,10 +35,10 @@ declare @llvm.riscv.vfrec7.mask.nxv1f16( define @intrinsic_vfrec7_mask_v_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv1f16( @@ -58,10 +58,10 @@ declare @llvm.riscv.vfrec7.nxv2f16( define @intrinsic_vfrec7_v_nxv2f16_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv2f16( @@ -81,10 +81,10 @@ declare @llvm.riscv.vfrec7.mask.nxv2f16( define @intrinsic_vfrec7_mask_v_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv2f16( @@ -104,10 +104,10 @@ declare @llvm.riscv.vfrec7.nxv4f16( define @intrinsic_vfrec7_v_nxv4f16_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv4f16( @@ -127,10 +127,10 @@ declare @llvm.riscv.vfrec7.mask.nxv4f16( define @intrinsic_vfrec7_mask_v_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv4f16( @@ -150,10 +150,10 @@ declare @llvm.riscv.vfrec7.nxv8f16( define @intrinsic_vfrec7_v_nxv8f16_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv8f16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfrec7.mask.nxv8f16( define @intrinsic_vfrec7_mask_v_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv8f16( @@ -196,10 +196,10 @@ declare @llvm.riscv.vfrec7.nxv16f16( define @intrinsic_vfrec7_v_nxv16f16_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv16f16( @@ -219,10 +219,10 @@ declare @llvm.riscv.vfrec7.mask.nxv16f16( define @intrinsic_vfrec7_mask_v_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv16f16( @@ -242,10 +242,10 @@ declare @llvm.riscv.vfrec7.nxv32f16( define @intrinsic_vfrec7_v_nxv32f16_nxv32f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv32f16( @@ -265,10 +265,10 @@ declare @llvm.riscv.vfrec7.mask.nxv32f16( define @intrinsic_vfrec7_mask_v_nxv32f16_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfrec7.nxv1f32( define @intrinsic_vfrec7_v_nxv1f32_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv1f32( @@ -311,10 +311,10 @@ declare @llvm.riscv.vfrec7.mask.nxv1f32( define @intrinsic_vfrec7_mask_v_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv1f32( @@ -334,10 +334,10 @@ declare @llvm.riscv.vfrec7.nxv2f32( define @intrinsic_vfrec7_v_nxv2f32_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv2f32( @@ -357,10 +357,10 @@ declare @llvm.riscv.vfrec7.mask.nxv2f32( define @intrinsic_vfrec7_mask_v_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv2f32( @@ -380,10 +380,10 @@ declare @llvm.riscv.vfrec7.nxv4f32( define @intrinsic_vfrec7_v_nxv4f32_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv4f32( @@ -403,10 +403,10 @@ declare @llvm.riscv.vfrec7.mask.nxv4f32( define @intrinsic_vfrec7_mask_v_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv4f32( @@ -426,10 +426,10 @@ declare @llvm.riscv.vfrec7.nxv8f32( define @intrinsic_vfrec7_v_nxv8f32_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv8f32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfrec7.mask.nxv8f32( define @intrinsic_vfrec7_mask_v_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfrec7.nxv16f32( define @intrinsic_vfrec7_v_nxv16f32_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv16f32( @@ -495,10 +495,10 @@ declare @llvm.riscv.vfrec7.mask.nxv16f32( define @intrinsic_vfrec7_mask_v_nxv16f32_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv16f32( @@ -518,10 +518,10 @@ declare @llvm.riscv.vfrec7.nxv1f64( define @intrinsic_vfrec7_v_nxv1f64_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv1f64( @@ -541,10 +541,10 @@ declare @llvm.riscv.vfrec7.mask.nxv1f64( define @intrinsic_vfrec7_mask_v_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv1f64( @@ -564,10 +564,10 @@ declare @llvm.riscv.vfrec7.nxv2f64( define @intrinsic_vfrec7_v_nxv2f64_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv2f64( @@ -587,10 +587,10 @@ declare @llvm.riscv.vfrec7.mask.nxv2f64( define @intrinsic_vfrec7_mask_v_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv2f64( @@ -610,10 +610,10 @@ declare @llvm.riscv.vfrec7.nxv4f64( define @intrinsic_vfrec7_v_nxv4f64_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv4f64( @@ -633,10 +633,10 @@ declare @llvm.riscv.vfrec7.mask.nxv4f64( define @intrinsic_vfrec7_mask_v_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv4f64( @@ -656,10 +656,10 @@ declare @llvm.riscv.vfrec7.nxv8f64( define @intrinsic_vfrec7_v_nxv8f64_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv8f64( @@ -679,10 +679,10 @@ declare @llvm.riscv.vfrec7.mask.nxv8f64( define @intrinsic_vfrec7_mask_v_nxv8f64_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll b/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll index 19dde75969e3..6de9c82002f5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16( define @intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1( define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16( define @intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1( define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16( define @intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1( define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16( define @intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1( define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16( define @intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1( define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16( define @intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1( define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32( define @intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1( define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfredosum.nxv2f32.nxv2f32( define @intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv2f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1( define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfredosum.nxv2f32.nxv4f32( define @intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv4f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1( define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfredosum.nxv2f32.nxv8f32( define @intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv8f32( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1( define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfredosum.nxv2f32.nxv16f32( define @intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv16f32( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1 define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfredosum.nxv1f64.nxv1f64( define @intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv1f64.nxv1f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1( define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfredosum.nxv1f64.nxv2f64( define @intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv1f64.nxv2f64( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1( define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfredosum.nxv1f64.nxv4f64( define @intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv1f64.nxv4f64( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1( define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfredosum.nxv1f64.nxv8f64( define @intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv1f64.nxv8f64( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1( define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll b/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll index bd2a5a901fb8..ffef9ef728a1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16( define @intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.nxv1i1( define @intrinsic_vfredusum_mask_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.nxv1i1( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16( define @intrinsic_vfredusum_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.nxv2i1( define @intrinsic_vfredusum_mask_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.nxv2i1( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16( define @intrinsic_vfredusum_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.nxv4i1( define @intrinsic_vfredusum_mask_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.nxv4i1( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16( define @intrinsic_vfredusum_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.nxv8i1( define @intrinsic_vfredusum_mask_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.nxv8i1( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16( define @intrinsic_vfredusum_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.nxv16i1( define @intrinsic_vfredusum_mask_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.nxv16i1( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16( define @intrinsic_vfredusum_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.nxv32i1( define @intrinsic_vfredusum_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.nxv32i1( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32( define @intrinsic_vfredusum_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.nxv1i1( define @intrinsic_vfredusum_mask_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.nxv1i1( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfredusum.nxv2f32.nxv2f32( define @intrinsic_vfredusum_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.nxv2i1( define @intrinsic_vfredusum_mask_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.nxv2i1( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfredusum.nxv2f32.nxv4f32( define @intrinsic_vfredusum_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv2f32.nxv4f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.nxv4i1( define @intrinsic_vfredusum_mask_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.nxv4i1( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfredusum.nxv2f32.nxv8f32( define @intrinsic_vfredusum_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv2f32.nxv8f32( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.nxv8i1( define @intrinsic_vfredusum_mask_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.nxv8i1( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfredusum.nxv2f32.nxv16f32( define @intrinsic_vfredusum_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv2f32.nxv16f32( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.nxv16i1 define @intrinsic_vfredusum_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.nxv16i1( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfredusum.nxv1f64.nxv1f64( define @intrinsic_vfredusum_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv1f64.nxv1f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.nxv1i1( define @intrinsic_vfredusum_mask_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.nxv1i1( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfredusum.nxv1f64.nxv2f64( define @intrinsic_vfredusum_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv1f64.nxv2f64( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.nxv2i1( define @intrinsic_vfredusum_mask_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.nxv2i1( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfredusum.nxv1f64.nxv4f64( define @intrinsic_vfredusum_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv1f64.nxv4f64( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.nxv4i1( define @intrinsic_vfredusum_mask_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.nxv4i1( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfredusum.nxv1f64.nxv8f64( define @intrinsic_vfredusum_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv1f64.nxv8f64( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.nxv8i1( define @intrinsic_vfredusum_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.nxv8i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll index 0f61e6a7d406..3e3eea9f353c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfsqrt.nxv1f16( define @intrinsic_vfsqrt_v_nxv1f16_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv1f16( @@ -35,10 +35,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv1f16( define @intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv1f16( @@ -58,10 +58,10 @@ declare @llvm.riscv.vfsqrt.nxv2f16( define @intrinsic_vfsqrt_v_nxv2f16_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv2f16( @@ -81,10 +81,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv2f16( define @intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv2f16( @@ -104,10 +104,10 @@ declare @llvm.riscv.vfsqrt.nxv4f16( define @intrinsic_vfsqrt_v_nxv4f16_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv4f16( @@ -127,10 +127,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv4f16( define @intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv4f16( @@ -150,10 +150,10 @@ declare @llvm.riscv.vfsqrt.nxv8f16( define @intrinsic_vfsqrt_v_nxv8f16_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv8f16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv8f16( define @intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv8f16( @@ -196,10 +196,10 @@ declare @llvm.riscv.vfsqrt.nxv16f16( define @intrinsic_vfsqrt_v_nxv16f16_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv16f16( @@ -219,10 +219,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv16f16( define @intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv16f16( @@ -242,10 +242,10 @@ declare @llvm.riscv.vfsqrt.nxv32f16( define @intrinsic_vfsqrt_v_nxv32f16_nxv32f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv32f16( @@ -265,10 +265,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv32f16( define @intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfsqrt.nxv1f32( define @intrinsic_vfsqrt_v_nxv1f32_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv1f32( @@ -311,10 +311,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv1f32( define @intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv1f32( @@ -334,10 +334,10 @@ declare @llvm.riscv.vfsqrt.nxv2f32( define @intrinsic_vfsqrt_v_nxv2f32_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv2f32( @@ -357,10 +357,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv2f32( define @intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv2f32( @@ -380,10 +380,10 @@ declare @llvm.riscv.vfsqrt.nxv4f32( define @intrinsic_vfsqrt_v_nxv4f32_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv4f32( @@ -403,10 +403,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv4f32( define @intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv4f32( @@ -426,10 +426,10 @@ declare @llvm.riscv.vfsqrt.nxv8f32( define @intrinsic_vfsqrt_v_nxv8f32_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv8f32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv8f32( define @intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfsqrt.nxv16f32( define @intrinsic_vfsqrt_v_nxv16f32_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv16f32( @@ -495,10 +495,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv16f32( define @intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv16f32( @@ -518,10 +518,10 @@ declare @llvm.riscv.vfsqrt.nxv1f64( define @intrinsic_vfsqrt_v_nxv1f64_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv1f64( @@ -541,10 +541,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv1f64( define @intrinsic_vfsqrt_mask_v_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv1f64( @@ -564,10 +564,10 @@ declare @llvm.riscv.vfsqrt.nxv2f64( define @intrinsic_vfsqrt_v_nxv2f64_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv2f64( @@ -587,10 +587,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv2f64( define @intrinsic_vfsqrt_mask_v_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv2f64( @@ -610,10 +610,10 @@ declare @llvm.riscv.vfsqrt.nxv4f64( define @intrinsic_vfsqrt_v_nxv4f64_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv4f64( @@ -633,10 +633,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv4f64( define @intrinsic_vfsqrt_mask_v_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv4f64( @@ -656,10 +656,10 @@ declare @llvm.riscv.vfsqrt.nxv8f64( define @intrinsic_vfsqrt_v_nxv8f64_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv8f64( @@ -679,10 +679,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv8f64( define @intrinsic_vfsqrt_mask_v_nxv8f64_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.ll index cb7047be9753..b42a1fe46e67 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( define @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -39,10 +39,10 @@ declare @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16( define @intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16( @@ -64,10 +64,10 @@ declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16( define @intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -90,10 +90,10 @@ declare @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16( define @intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16( @@ -115,10 +115,10 @@ declare @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16( define @intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -141,10 +141,10 @@ declare @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16( define @intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16( @@ -166,10 +166,10 @@ declare @llvm.riscv.vfwadd.nxv8f32.nxv8f16.nxv8f16( define @intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v12, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -192,10 +192,10 @@ declare @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16( define @intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16( @@ -217,10 +217,10 @@ declare @llvm.riscv.vfwadd.nxv16f32.nxv16f16.nxv16f16( define @intrinsic_vfwadd_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v16, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -243,10 +243,10 @@ declare @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16 define @intrinsic_vfwadd_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16( @@ -268,10 +268,10 @@ declare @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32( define @intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -294,10 +294,10 @@ declare @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32( define @intrinsic_vfwadd_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32( @@ -319,10 +319,10 @@ declare @llvm.riscv.vfwadd.nxv2f64.nxv2f32.nxv2f32( define @intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -345,10 +345,10 @@ declare @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32( define @intrinsic_vfwadd_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32( @@ -370,10 +370,10 @@ declare @llvm.riscv.vfwadd.nxv4f64.nxv4f32.nxv4f32( define @intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v12, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -396,10 +396,10 @@ declare @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32( define @intrinsic_vfwadd_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32( @@ -421,10 +421,10 @@ declare @llvm.riscv.vfwadd.nxv8f64.nxv8f32.nxv8f32( define @intrinsic_vfwadd_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v16, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -447,10 +447,10 @@ declare @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32( define @intrinsic_vfwadd_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16( define @intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -498,10 +498,10 @@ declare @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16( define @intrinsic_vfwadd_mask_vf_nxv1f32_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f32_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16( @@ -523,10 +523,10 @@ declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16( define @intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -549,10 +549,10 @@ declare @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16( define @intrinsic_vfwadd_mask_vf_nxv2f32_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f32_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16( @@ -574,10 +574,10 @@ declare @llvm.riscv.vfwadd.nxv4f32.nxv4f16.f16( define @intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -600,10 +600,10 @@ declare @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16( define @intrinsic_vfwadd_mask_vf_nxv4f32_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f32_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16( @@ -625,10 +625,10 @@ declare @llvm.riscv.vfwadd.nxv8f32.nxv8f16.f16( define @intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -651,10 +651,10 @@ declare @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16( define @intrinsic_vfwadd_mask_vf_nxv8f32_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f32_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16( @@ -676,10 +676,10 @@ declare @llvm.riscv.vfwadd.nxv16f32.nxv16f16.f16( define @intrinsic_vfwadd_vf_nxv16f32_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv16f32_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -702,10 +702,10 @@ declare @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16( define @intrinsic_vfwadd_mask_vf_nxv16f32_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv16f32_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16( @@ -727,10 +727,10 @@ declare @llvm.riscv.vfwadd.nxv1f64.nxv1f32.f32( define @intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -753,10 +753,10 @@ declare @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32( define @intrinsic_vfwadd_mask_vf_nxv1f64_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f64_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32( @@ -778,10 +778,10 @@ declare @llvm.riscv.vfwadd.nxv2f64.nxv2f32.f32( define @intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -804,10 +804,10 @@ declare @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32( define @intrinsic_vfwadd_mask_vf_nxv2f64_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f64_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32( @@ -829,10 +829,10 @@ declare @llvm.riscv.vfwadd.nxv4f64.nxv4f32.f32( define @intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -855,10 +855,10 @@ declare @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32( define @intrinsic_vfwadd_mask_vf_nxv4f64_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f64_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32( @@ -880,10 +880,10 @@ declare @llvm.riscv.vfwadd.nxv8f64.nxv8f32.f32( define @intrinsic_vfwadd_vf_nxv8f64_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f64_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -906,10 +906,10 @@ declare @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32( define @intrinsic_vfwadd_mask_vf_nxv8f64_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f64_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll index 2a318c53a5fb..76246eba9480 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( define @intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16( define @intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16( define @intrinsic_vfwadd.w_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16( define @intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwadd.w.nxv4f32.nxv4f16( define @intrinsic_vfwadd.w_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv4f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16( define @intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwadd.w.nxv8f32.nxv8f16( define @intrinsic_vfwadd.w_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv8f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16( define @intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwadd.w.nxv16f32.nxv16f16( define @intrinsic_vfwadd.w_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv16f32.nxv16f16( @@ -239,8 +239,8 @@ define @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16 ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl4re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -264,10 +264,10 @@ declare @llvm.riscv.vfwadd.w.nxv1f64.nxv1f32( define @intrinsic_vfwadd.w_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv1f64.nxv1f32( @@ -289,10 +289,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32( define @intrinsic_vfwadd.w_mask_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32( @@ -314,10 +314,10 @@ declare @llvm.riscv.vfwadd.w.nxv2f64.nxv2f32( define @intrinsic_vfwadd.w_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv2f64.nxv2f32( @@ -339,10 +339,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32( define @intrinsic_vfwadd.w_mask_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32( @@ -364,10 +364,10 @@ declare @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32( define @intrinsic_vfwadd.w_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32( @@ -389,10 +389,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32( define @intrinsic_vfwadd.w_mask_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32( @@ -414,10 +414,10 @@ declare @llvm.riscv.vfwadd.w.nxv8f64.nxv8f32( define @intrinsic_vfwadd.w_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv8f64.nxv8f32( @@ -440,8 +440,8 @@ define @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32 ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl4re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -465,10 +465,10 @@ declare @llvm.riscv.vfwadd.w.nxv1f32.f16( define @intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv1f32.f16( @@ -490,10 +490,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv1f32.f16( define @intrinsic_vfwadd.w_mask_wf_nxv1f32_nxv1f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f32_nxv1f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f32.f16( @@ -515,10 +515,10 @@ declare @llvm.riscv.vfwadd.w.nxv2f32.f16( define @intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv2f32.f16( @@ -540,10 +540,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv2f32.f16( define @intrinsic_vfwadd.w_mask_wf_nxv2f32_nxv2f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f32_nxv2f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f32.f16( @@ -565,10 +565,10 @@ declare @llvm.riscv.vfwadd.w.nxv4f32.f16( define @intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv4f32.f16( @@ -590,10 +590,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv4f32.f16( define @intrinsic_vfwadd.w_mask_wf_nxv4f32_nxv4f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f32_nxv4f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f32.f16( @@ -615,10 +615,10 @@ declare @llvm.riscv.vfwadd.w.nxv8f32.f16( define @intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv8f32.f16( @@ -640,10 +640,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv8f32.f16( define @intrinsic_vfwadd.w_mask_wf_nxv8f32_nxv8f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f32_nxv8f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f32.f16( @@ -665,10 +665,10 @@ declare @llvm.riscv.vfwadd.w.nxv16f32.f16( define @intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv16f32.f16( @@ -690,10 +690,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv16f32.f16( define @intrinsic_vfwadd.w_mask_wf_nxv16f32_nxv16f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv16f32_nxv16f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv16f32.f16( @@ -715,10 +715,10 @@ declare @llvm.riscv.vfwadd.w.nxv1f64.f32( define @intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv1f64.f32( @@ -740,10 +740,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv1f64.f32( define @intrinsic_vfwadd.w_mask_wf_nxv1f64_nxv1f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f64_nxv1f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f64.f32( @@ -765,10 +765,10 @@ declare @llvm.riscv.vfwadd.w.nxv2f64.f32( define @intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv2f64.f32( @@ -790,10 +790,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv2f64.f32( define @intrinsic_vfwadd.w_mask_wf_nxv2f64_nxv2f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f64_nxv2f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f64.f32( @@ -815,10 +815,10 @@ declare @llvm.riscv.vfwadd.w.nxv4f64.f32( define @intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv4f64.f32( @@ -840,10 +840,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv4f64.f32( define @intrinsic_vfwadd.w_mask_wf_nxv4f64_nxv4f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f64_nxv4f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f64.f32( @@ -865,10 +865,10 @@ declare @llvm.riscv.vfwadd.w.nxv8f64.f32( define @intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv8f64.f32( @@ -890,10 +890,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv8f64.f32( define @intrinsic_vfwadd.w_mask_wf_nxv8f64_nxv8f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f64_nxv8f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f64.f32( @@ -909,10 +909,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv1f32_nxv1f32_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16( @@ -928,10 +928,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv2f32_nxv2f32_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16( @@ -947,10 +947,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv4f32_nxv4f32_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16( @@ -966,10 +966,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv8f32_nxv8f32_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16( @@ -985,10 +985,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16( @@ -1004,10 +1004,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv1f64_nxv1f64_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32( @@ -1023,10 +1023,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv2f64_nxv2f64_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32( @@ -1042,10 +1042,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv4f64_nxv4f64_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32( @@ -1061,10 +1061,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32( @@ -1080,10 +1080,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv1f32_nxv1f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv1f32_nxv1f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f32.f16( @@ -1099,10 +1099,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv2f32_nxv2f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv2f32_nxv2f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f32.f16( @@ -1118,10 +1118,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv4f32_nxv4f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv4f32_nxv4f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f32.f16( @@ -1137,10 +1137,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv8f32_nxv8f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv8f32_nxv8f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f32.f16( @@ -1156,10 +1156,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv16f32_nxv16f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv16f32_nxv16f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv16f32.f16( @@ -1175,10 +1175,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv1f64_nxv1f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv1f64_nxv1f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f64.f32( @@ -1194,10 +1194,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv2f64_nxv2f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv2f64_nxv2f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f64.f32( @@ -1213,10 +1213,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv4f64_nxv4f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv4f64_nxv4f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f64.f32( @@ -1232,10 +1232,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv8f64_nxv8f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv8f64_nxv8f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f64.f32( @@ -1251,10 +1251,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v10, v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -1270,10 +1270,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v10, v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -1289,10 +1289,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v12, v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -1308,10 +1308,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v16, v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -1327,10 +1327,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv1f64_nxv1f64_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v10, v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -1346,10 +1346,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv2f64_nxv2f64_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v12, v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -1365,10 +1365,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv4f64_nxv4f64_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v16, v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -1384,10 +1384,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv8f64_nxv8f64_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v24, v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll index ba7ba4e4c2bb..23b10250dfa4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( define @intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -36,10 +36,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16( define @intrinsic_vfwcvt_mask_x.f.v_nxv1i32_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv1i32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16( @@ -59,10 +59,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16( define @intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -83,10 +83,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16( define @intrinsic_vfwcvt_mask_x.f.v_nxv2i32_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv2i32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16( @@ -106,10 +106,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16( define @intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -130,10 +130,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16( define @intrinsic_vfwcvt_mask_x.f.v_nxv4i32_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv4i32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16( @@ -153,10 +153,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16( define @intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -177,10 +177,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16( define @intrinsic_vfwcvt_mask_x.f.v_nxv8i32_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv8i32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16( @@ -200,10 +200,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv16i32.nxv16f16( define @intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -224,10 +224,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16( define @intrinsic_vfwcvt_mask_x.f.v_nxv16i32_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv16i32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16( @@ -247,10 +247,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32( define @intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -271,10 +271,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32( define @intrinsic_vfwcvt_mask_x.f.v_nxv1i64_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv1i64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32( @@ -294,10 +294,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32( define @intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -318,10 +318,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32( define @intrinsic_vfwcvt_mask_x.f.v_nxv2i64_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv2i64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32( @@ -341,10 +341,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32( define @intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -365,10 +365,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32( define @intrinsic_vfwcvt_mask_x.f.v_nxv4i64_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv4i64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32( define @intrinsic_vfwcvt_x.f.v_nxv8i64_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -412,10 +412,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32( define @intrinsic_vfwcvt_mask_x.f.v_nxv8i64_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv8i64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll index 82cea184920b..f6779ec9ba5a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( define @intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -36,10 +36,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16( define @intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16( @@ -59,10 +59,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16( define @intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -83,10 +83,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16( define @intrinsic_vfwcvt_mask_xu.f.v_nxv2i32_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv2i32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16( @@ -106,10 +106,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16( define @intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -130,10 +130,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16( define @intrinsic_vfwcvt_mask_xu.f.v_nxv4i32_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv4i32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16( @@ -153,10 +153,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16( define @intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -177,10 +177,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16( define @intrinsic_vfwcvt_mask_xu.f.v_nxv8i32_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv8i32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16( @@ -200,10 +200,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv16i32.nxv16f16( define @intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -224,10 +224,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16( define @intrinsic_vfwcvt_mask_xu.f.v_nxv16i32_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv16i32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16( @@ -247,10 +247,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32( define @intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -271,10 +271,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32( define @intrinsic_vfwcvt_mask_xu.f.v_nxv1i64_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv1i64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32( @@ -294,10 +294,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32( define @intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -318,10 +318,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32( define @intrinsic_vfwcvt_mask_xu.f.v_nxv2i64_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv2i64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32( @@ -341,10 +341,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32( define @intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -365,10 +365,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32( define @intrinsic_vfwcvt_mask_xu.f.v_nxv4i64_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv4i64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32( define @intrinsic_vfwcvt_xu.f.v_nxv8i64_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -412,10 +412,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32( define @intrinsic_vfwcvt_mask_xu.f.v_nxv8i64_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv8i64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll index b3ff91d92ce9..225ba1c14031 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16( define @intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16( define @intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16( define @intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16( define @intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16( define @intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16( define @intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16( define @intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16( define @intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwmacc.nxv16f32.nxv16f16( define @intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv16f32.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16( define @intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfwmacc.nxv1f64.nxv1f32( define @intrinsic_vfwmacc_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv1f64.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32( define @intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfwmacc.nxv2f64.nxv2f32( define @intrinsic_vfwmacc_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv2f64.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32( define @intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfwmacc.nxv4f64.nxv4f32( define @intrinsic_vfwmacc_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv4f64.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32( define @intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfwmacc.nxv8f64.nxv8f32( define @intrinsic_vfwmacc_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv8f64.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32( define @intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfwmacc.nxv1f32.f16( define @intrinsic_vfwmacc_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv1f32.f16( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv1f32.f16( define @intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f32.f16( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfwmacc.nxv2f32.f16( define @intrinsic_vfwmacc_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv2f32.f16( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv2f32.f16( define @intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f32.f16( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfwmacc.nxv4f32.f16( define @intrinsic_vfwmacc_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv4f32.f16( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv4f32.f16( define @intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f32.f16( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfwmacc.nxv8f32.f16( define @intrinsic_vfwmacc_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv8f32.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv8f32.f16( define @intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f32.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfwmacc.nxv16f32.f16( define @intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv16f32.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv16f32.f16( define @intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv16f32.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfwmacc.nxv1f64.f32( define @intrinsic_vfwmacc_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv1f64.f32( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv1f64.f32( define @intrinsic_vfwmacc_mask_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f64.f32( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfwmacc.nxv2f64.f32( define @intrinsic_vfwmacc_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv2f64.f32( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv2f64.f32( define @intrinsic_vfwmacc_mask_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f64.f32( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfwmacc.nxv4f64.f32( define @intrinsic_vfwmacc_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv4f64.f32( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv4f64.f32( define @intrinsic_vfwmacc_mask_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f64.f32( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfwmacc.nxv8f64.f32( define @intrinsic_vfwmacc_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv8f64.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv8f64.f32( define @intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll index 103eeb08f8c8..5e3f63b95b2f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16( define @intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16( define @intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16( define @intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16( define @intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16( define @intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16( define @intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16( define @intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16( define @intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwmsac.nxv16f32.nxv16f16( define @intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv16f32.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16( define @intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfwmsac.nxv1f64.nxv1f32( define @intrinsic_vfwmsac_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv1f64.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32( define @intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfwmsac.nxv2f64.nxv2f32( define @intrinsic_vfwmsac_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv2f64.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32( define @intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfwmsac.nxv4f64.nxv4f32( define @intrinsic_vfwmsac_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv4f64.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32( define @intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfwmsac.nxv8f64.nxv8f32( define @intrinsic_vfwmsac_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv8f64.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32( define @intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfwmsac.nxv1f32.f16( define @intrinsic_vfwmsac_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv1f32.f16( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv1f32.f16( define @intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f32.f16( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfwmsac.nxv2f32.f16( define @intrinsic_vfwmsac_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv2f32.f16( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv2f32.f16( define @intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f32.f16( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfwmsac.nxv4f32.f16( define @intrinsic_vfwmsac_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv4f32.f16( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv4f32.f16( define @intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f32.f16( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfwmsac.nxv8f32.f16( define @intrinsic_vfwmsac_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv8f32.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv8f32.f16( define @intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f32.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfwmsac.nxv16f32.f16( define @intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv16f32.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv16f32.f16( define @intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv16f32.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfwmsac.nxv1f64.f32( define @intrinsic_vfwmsac_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv1f64.f32( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv1f64.f32( define @intrinsic_vfwmsac_mask_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f64.f32( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfwmsac.nxv2f64.f32( define @intrinsic_vfwmsac_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv2f64.f32( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv2f64.f32( define @intrinsic_vfwmsac_mask_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f64.f32( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfwmsac.nxv4f64.f32( define @intrinsic_vfwmsac_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv4f64.f32( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv4f64.f32( define @intrinsic_vfwmsac_mask_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f64.f32( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfwmsac.nxv8f64.f32( define @intrinsic_vfwmsac_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv8f64.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv8f64.f32( define @intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul.ll index 2f9fc24de3aa..bc5759f469ad 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( define @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -39,10 +39,10 @@ declare @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.nxv1f16( define @intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.nxv1f16( @@ -64,10 +64,10 @@ declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16( define @intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -90,10 +90,10 @@ declare @llvm.riscv.vfwmul.mask.nxv2f32.nxv2f16.nxv2f16( define @intrinsic_vfwmul_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv2f32.nxv2f16.nxv2f16( @@ -115,10 +115,10 @@ declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16( define @intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -141,10 +141,10 @@ declare @llvm.riscv.vfwmul.mask.nxv4f32.nxv4f16.nxv4f16( define @intrinsic_vfwmul_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv4f32.nxv4f16.nxv4f16( @@ -166,10 +166,10 @@ declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16( define @intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v12, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -192,10 +192,10 @@ declare @llvm.riscv.vfwmul.mask.nxv8f32.nxv8f16.nxv8f16( define @intrinsic_vfwmul_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv8f32.nxv8f16.nxv8f16( @@ -217,10 +217,10 @@ declare @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16( define @intrinsic_vfwmul_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v16, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -243,10 +243,10 @@ declare @llvm.riscv.vfwmul.mask.nxv16f32.nxv16f16.nxv16f16 define @intrinsic_vfwmul_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv16f32.nxv16f16.nxv16f16( @@ -268,10 +268,10 @@ declare @llvm.riscv.vfwmul.nxv1f64.nxv1f32.nxv1f32( define @intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -294,10 +294,10 @@ declare @llvm.riscv.vfwmul.mask.nxv1f64.nxv1f32.nxv1f32( define @intrinsic_vfwmul_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv1f64.nxv1f32.nxv1f32( @@ -319,10 +319,10 @@ declare @llvm.riscv.vfwmul.nxv2f64.nxv2f32.nxv2f32( define @intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -345,10 +345,10 @@ declare @llvm.riscv.vfwmul.mask.nxv2f64.nxv2f32.nxv2f32( define @intrinsic_vfwmul_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv2f64.nxv2f32.nxv2f32( @@ -370,10 +370,10 @@ declare @llvm.riscv.vfwmul.nxv4f64.nxv4f32.nxv4f32( define @intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v12, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -396,10 +396,10 @@ declare @llvm.riscv.vfwmul.mask.nxv4f64.nxv4f32.nxv4f32( define @intrinsic_vfwmul_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv4f64.nxv4f32.nxv4f32( @@ -421,10 +421,10 @@ declare @llvm.riscv.vfwmul.nxv8f64.nxv8f32.nxv8f32( define @intrinsic_vfwmul_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v16, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -447,10 +447,10 @@ declare @llvm.riscv.vfwmul.mask.nxv8f64.nxv8f32.nxv8f32( define @intrinsic_vfwmul_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv8f64.nxv8f32.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16( define @intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -498,10 +498,10 @@ declare @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.f16( define @intrinsic_vfwmul_mask_vf_nxv1f32_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv1f32_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.f16( @@ -523,10 +523,10 @@ declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16( define @intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -549,10 +549,10 @@ declare @llvm.riscv.vfwmul.mask.nxv2f32.nxv2f16.f16( define @intrinsic_vfwmul_mask_vf_nxv2f32_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv2f32_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv2f32.nxv2f16.f16( @@ -574,10 +574,10 @@ declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16( define @intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -600,10 +600,10 @@ declare @llvm.riscv.vfwmul.mask.nxv4f32.nxv4f16.f16( define @intrinsic_vfwmul_mask_vf_nxv4f32_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv4f32_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv4f32.nxv4f16.f16( @@ -625,10 +625,10 @@ declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16( define @intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -651,10 +651,10 @@ declare @llvm.riscv.vfwmul.mask.nxv8f32.nxv8f16.f16( define @intrinsic_vfwmul_mask_vf_nxv8f32_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv8f32_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv8f32.nxv8f16.f16( @@ -676,10 +676,10 @@ declare @llvm.riscv.vfwmul.nxv16f32.nxv16f16.f16( define @intrinsic_vfwmul_vf_nxv16f32_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv16f32_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -702,10 +702,10 @@ declare @llvm.riscv.vfwmul.mask.nxv16f32.nxv16f16.f16( define @intrinsic_vfwmul_mask_vf_nxv16f32_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv16f32_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv16f32.nxv16f16.f16( @@ -727,10 +727,10 @@ declare @llvm.riscv.vfwmul.nxv1f64.nxv1f32.f32( define @intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -753,10 +753,10 @@ declare @llvm.riscv.vfwmul.mask.nxv1f64.nxv1f32.f32( define @intrinsic_vfwmul_mask_vf_nxv1f64_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv1f64_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv1f64.nxv1f32.f32( @@ -778,10 +778,10 @@ declare @llvm.riscv.vfwmul.nxv2f64.nxv2f32.f32( define @intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -804,10 +804,10 @@ declare @llvm.riscv.vfwmul.mask.nxv2f64.nxv2f32.f32( define @intrinsic_vfwmul_mask_vf_nxv2f64_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv2f64_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv2f64.nxv2f32.f32( @@ -829,10 +829,10 @@ declare @llvm.riscv.vfwmul.nxv4f64.nxv4f32.f32( define @intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -855,10 +855,10 @@ declare @llvm.riscv.vfwmul.mask.nxv4f64.nxv4f32.f32( define @intrinsic_vfwmul_mask_vf_nxv4f64_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv4f64_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv4f64.nxv4f32.f32( @@ -880,10 +880,10 @@ declare @llvm.riscv.vfwmul.nxv8f64.nxv8f32.f32( define @intrinsic_vfwmul_vf_nxv8f64_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv8f64_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -906,10 +906,10 @@ declare @llvm.riscv.vfwmul.mask.nxv8f64.nxv8f32.f32( define @intrinsic_vfwmul_mask_vf_nxv8f64_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv8f64_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv8f64.nxv8f32.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll index ca2d2a33159b..fc8e15273f08 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16( define @intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16( define @intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16( define @intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16( define @intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16( define @intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16( define @intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16( define @intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16( define @intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16( define @intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16( define @intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32( define @intrinsic_vfwnmacc_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32( define @intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32( define @intrinsic_vfwnmacc_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32( define @intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32( define @intrinsic_vfwnmacc_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32( define @intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32( define @intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32( define @intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfwnmacc.nxv1f32.f16( define @intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv1f32.f16( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv1f32.f16( define @intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv1f32.f16( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfwnmacc.nxv2f32.f16( define @intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv2f32.f16( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv2f32.f16( define @intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv2f32.f16( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfwnmacc.nxv4f32.f16( define @intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv4f32.f16( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv4f32.f16( define @intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv4f32.f16( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfwnmacc.nxv8f32.f16( define @intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv8f32.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv8f32.f16( define @intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv8f32.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfwnmacc.nxv16f32.f16( define @intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv16f32.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv16f32.f16( define @intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv16f32.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfwnmacc.nxv1f64.f32( define @intrinsic_vfwnmacc_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv1f64.f32( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv1f64.f32( define @intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv1f64.f32( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfwnmacc.nxv2f64.f32( define @intrinsic_vfwnmacc_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv2f64.f32( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv2f64.f32( define @intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv2f64.f32( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfwnmacc.nxv4f64.f32( define @intrinsic_vfwnmacc_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv4f64.f32( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv4f64.f32( define @intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv4f64.f32( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfwnmacc.nxv8f64.f32( define @intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv8f64.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv8f64.f32( define @intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll index 648727dce246..b51faf9082c8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16( define @intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16( define @intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16( define @intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16( define @intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16( define @intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16( define @intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16( define @intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16( define @intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16( define @intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16( define @intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32( define @intrinsic_vfwnmsac_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32( define @intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfwnmsac.nxv2f64.nxv2f32( define @intrinsic_vfwnmsac_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv2f64.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32( define @intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfwnmsac.nxv4f64.nxv4f32( define @intrinsic_vfwnmsac_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv4f64.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32( define @intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfwnmsac.nxv8f64.nxv8f32( define @intrinsic_vfwnmsac_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv8f64.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32( define @intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfwnmsac.nxv1f32.f16( define @intrinsic_vfwnmsac_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv1f32.f16( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv1f32.f16( define @intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f32.f16( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfwnmsac.nxv2f32.f16( define @intrinsic_vfwnmsac_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv2f32.f16( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv2f32.f16( define @intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f32.f16( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfwnmsac.nxv4f32.f16( define @intrinsic_vfwnmsac_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv4f32.f16( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv4f32.f16( define @intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f32.f16( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfwnmsac.nxv8f32.f16( define @intrinsic_vfwnmsac_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv8f32.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv8f32.f16( define @intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f32.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfwnmsac.nxv16f32.f16( define @intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv16f32.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv16f32.f16( define @intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv16f32.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfwnmsac.nxv1f64.f32( define @intrinsic_vfwnmsac_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv1f64.f32( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv1f64.f32( define @intrinsic_vfwnmsac_mask_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f64.f32( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfwnmsac.nxv2f64.f32( define @intrinsic_vfwnmsac_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv2f64.f32( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv2f64.f32( define @intrinsic_vfwnmsac_mask_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f64.f32( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfwnmsac.nxv4f64.f32( define @intrinsic_vfwnmsac_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv4f64.f32( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv4f64.f32( define @intrinsic_vfwnmsac_mask_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f64.f32( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfwnmsac.nxv8f64.f32( define @intrinsic_vfwnmsac_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv8f64.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv8f64.f32( define @intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll index 2184ab413c55..cb2bea0b50e1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( define @intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32 define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16( define @intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32 define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16( define @intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32 define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16( define @intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32 define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16( define @intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f3 define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16( define @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16( define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32( define @intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f6 define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfwredosum.nxv1f64.nxv2f32( define @intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv2f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f6 define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfwredosum.nxv1f64.nxv4f32( define @intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv4f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f6 define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfwredosum.nxv1f64.nxv8f32( define @intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv8f32( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f6 define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfwredosum.nxv1f64.nxv16f32( define @intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv16f32( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv1f define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv1f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll index d3d76e575978..66c2da047cfa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16( define @intrinsic_vfwredusum_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.nxv2f32 define @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.nxv2f32( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16( define @intrinsic_vfwredusum_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.nxv2f32 define @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.nxv2f32( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16( define @intrinsic_vfwredusum_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.nxv2f32 define @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.nxv2f32( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16( define @intrinsic_vfwredusum_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.nxv2f32 define @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.nxv2f32( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16( define @intrinsic_vfwredusum_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.nxv2f3 define @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.nxv2f32( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16( define @intrinsic_vfwredusum_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16( define @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32( define @intrinsic_vfwredusum_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.nxv1f6 define @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.nxv1f64( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfwredusum.nxv1f64.nxv2f32( define @intrinsic_vfwredusum_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv1f64.nxv2f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.nxv1f6 define @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.nxv1f64( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfwredusum.nxv1f64.nxv4f32( define @intrinsic_vfwredusum_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv1f64.nxv4f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.nxv1f6 define @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.nxv1f64( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfwredusum.nxv1f64.nxv8f32( define @intrinsic_vfwredusum_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv1f64.nxv8f32( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.nxv1f6 define @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfwredusum.nxv1f64.nxv16f32( define @intrinsic_vfwredusum_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv1f64.nxv16f32( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.nxv1f define @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.nxv1f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.ll index bb72f70f111b..0e3e5f8aabfd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( define @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -39,10 +39,10 @@ declare @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.nxv1f16( define @intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.nxv1f16( @@ -64,10 +64,10 @@ declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16( define @intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -90,10 +90,10 @@ declare @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.nxv2f16( define @intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.nxv2f16( @@ -115,10 +115,10 @@ declare @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16( define @intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -141,10 +141,10 @@ declare @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.nxv4f16( define @intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.nxv4f16( @@ -166,10 +166,10 @@ declare @llvm.riscv.vfwsub.nxv8f32.nxv8f16.nxv8f16( define @intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v12, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -192,10 +192,10 @@ declare @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.nxv8f16( define @intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.nxv8f16( @@ -217,10 +217,10 @@ declare @llvm.riscv.vfwsub.nxv16f32.nxv16f16.nxv16f16( define @intrinsic_vfwsub_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v16, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -243,10 +243,10 @@ declare @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.nxv16f16 define @intrinsic_vfwsub_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.nxv16f16( @@ -268,10 +268,10 @@ declare @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32( define @intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -294,10 +294,10 @@ declare @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.nxv1f32( define @intrinsic_vfwsub_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.nxv1f32( @@ -319,10 +319,10 @@ declare @llvm.riscv.vfwsub.nxv2f64.nxv2f32.nxv2f32( define @intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -345,10 +345,10 @@ declare @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.nxv2f32( define @intrinsic_vfwsub_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.nxv2f32( @@ -370,10 +370,10 @@ declare @llvm.riscv.vfwsub.nxv4f64.nxv4f32.nxv4f32( define @intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v12, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -396,10 +396,10 @@ declare @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.nxv4f32( define @intrinsic_vfwsub_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.nxv4f32( @@ -421,10 +421,10 @@ declare @llvm.riscv.vfwsub.nxv8f64.nxv8f32.nxv8f32( define @intrinsic_vfwsub_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v16, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -447,10 +447,10 @@ declare @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.nxv8f32( define @intrinsic_vfwsub_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16( define @intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -498,10 +498,10 @@ declare @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.f16( define @intrinsic_vfwsub_mask_vf_nxv1f32_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f32_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.f16( @@ -523,10 +523,10 @@ declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16( define @intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -549,10 +549,10 @@ declare @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.f16( define @intrinsic_vfwsub_mask_vf_nxv2f32_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f32_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.f16( @@ -574,10 +574,10 @@ declare @llvm.riscv.vfwsub.nxv4f32.nxv4f16.f16( define @intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -600,10 +600,10 @@ declare @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.f16( define @intrinsic_vfwsub_mask_vf_nxv4f32_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f32_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.f16( @@ -625,10 +625,10 @@ declare @llvm.riscv.vfwsub.nxv8f32.nxv8f16.f16( define @intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -651,10 +651,10 @@ declare @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.f16( define @intrinsic_vfwsub_mask_vf_nxv8f32_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f32_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.f16( @@ -676,10 +676,10 @@ declare @llvm.riscv.vfwsub.nxv16f32.nxv16f16.f16( define @intrinsic_vfwsub_vf_nxv16f32_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv16f32_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -702,10 +702,10 @@ declare @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.f16( define @intrinsic_vfwsub_mask_vf_nxv16f32_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv16f32_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.f16( @@ -727,10 +727,10 @@ declare @llvm.riscv.vfwsub.nxv1f64.nxv1f32.f32( define @intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -753,10 +753,10 @@ declare @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.f32( define @intrinsic_vfwsub_mask_vf_nxv1f64_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f64_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.f32( @@ -778,10 +778,10 @@ declare @llvm.riscv.vfwsub.nxv2f64.nxv2f32.f32( define @intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -804,10 +804,10 @@ declare @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.f32( define @intrinsic_vfwsub_mask_vf_nxv2f64_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f64_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.f32( @@ -829,10 +829,10 @@ declare @llvm.riscv.vfwsub.nxv4f64.nxv4f32.f32( define @intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -855,10 +855,10 @@ declare @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.f32( define @intrinsic_vfwsub_mask_vf_nxv4f64_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f64_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.f32( @@ -880,10 +880,10 @@ declare @llvm.riscv.vfwsub.nxv8f64.nxv8f32.f32( define @intrinsic_vfwsub_vf_nxv8f64_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f64_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -906,10 +906,10 @@ declare @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.f32( define @intrinsic_vfwsub_mask_vf_nxv8f64_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f64_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll index 722fed5138f7..90f92226dcdd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( define @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv1f32.nxv1f16( define @intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f32.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16( define @intrinsic_vfwsub.w_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv2f32.nxv2f16( define @intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f32.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwsub.w.nxv4f32.nxv4f16( define @intrinsic_vfwsub.w_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv4f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv4f32.nxv4f16( define @intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f32.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwsub.w.nxv8f32.nxv8f16( define @intrinsic_vfwsub.w_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv8f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv8f32.nxv8f16( define @intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f32.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16( define @intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16( @@ -239,8 +239,8 @@ define @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16 ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl4re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -264,10 +264,10 @@ declare @llvm.riscv.vfwsub.w.nxv1f64.nxv1f32( define @intrinsic_vfwsub.w_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv1f64.nxv1f32( @@ -289,10 +289,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv1f64.nxv1f32( define @intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f64.nxv1f32( @@ -314,10 +314,10 @@ declare @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32( define @intrinsic_vfwsub.w_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32( @@ -339,10 +339,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv2f64.nxv2f32( define @intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f64.nxv2f32( @@ -364,10 +364,10 @@ declare @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32( define @intrinsic_vfwsub.w_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32( @@ -389,10 +389,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv4f64.nxv4f32( define @intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f64.nxv4f32( @@ -414,10 +414,10 @@ declare @llvm.riscv.vfwsub.w.nxv8f64.nxv8f32( define @intrinsic_vfwsub.w_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv8f64.nxv8f32( @@ -440,8 +440,8 @@ define @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32 ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl4re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -465,10 +465,10 @@ declare @llvm.riscv.vfwsub.w.nxv1f32.f16( define @intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv1f32.f16( @@ -490,10 +490,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv1f32.f16( define @intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f32.f16( @@ -515,10 +515,10 @@ declare @llvm.riscv.vfwsub.w.nxv2f32.f16( define @intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv2f32.f16( @@ -540,10 +540,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv2f32.f16( define @intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f32.f16( @@ -565,10 +565,10 @@ declare @llvm.riscv.vfwsub.w.nxv4f32.f16( define @intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv4f32.f16( @@ -590,10 +590,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv4f32.f16( define @intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f32.f16( @@ -615,10 +615,10 @@ declare @llvm.riscv.vfwsub.w.nxv8f32.f16( define @intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv8f32.f16( @@ -640,10 +640,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv8f32.f16( define @intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f32.f16( @@ -665,10 +665,10 @@ declare @llvm.riscv.vfwsub.w.nxv16f32.f16( define @intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv16f32.f16( @@ -690,10 +690,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv16f32.f16( define @intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv16f32.f16( @@ -715,10 +715,10 @@ declare @llvm.riscv.vfwsub.w.nxv1f64.f32( define @intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv1f64.f32( @@ -740,10 +740,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv1f64.f32( define @intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f64.f32( @@ -765,10 +765,10 @@ declare @llvm.riscv.vfwsub.w.nxv2f64.f32( define @intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv2f64.f32( @@ -790,10 +790,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv2f64.f32( define @intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f64.f32( @@ -815,10 +815,10 @@ declare @llvm.riscv.vfwsub.w.nxv4f64.f32( define @intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv4f64.f32( @@ -840,10 +840,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv4f64.f32( define @intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f64.f32( @@ -865,10 +865,10 @@ declare @llvm.riscv.vfwsub.w.nxv8f64.f32( define @intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv8f64.f32( @@ -890,10 +890,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv8f64.f32( define @intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f64.f32( @@ -909,10 +909,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv1f32_nxv1f32_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f32.nxv1f16( @@ -928,10 +928,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv2f32_nxv2f32_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f32.nxv2f16( @@ -947,10 +947,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv4f32_nxv4f32_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f32.nxv4f16( @@ -966,10 +966,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv8f32_nxv8f32_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f32.nxv8f16( @@ -985,10 +985,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16( @@ -1004,10 +1004,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv1f64_nxv1f64_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f64.nxv1f32( @@ -1023,10 +1023,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv2f64_nxv2f64_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f64.nxv2f32( @@ -1042,10 +1042,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv4f64_nxv4f64_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f64.nxv4f32( @@ -1061,10 +1061,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32( @@ -1080,10 +1080,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv1f32_nxv1f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv1f32_nxv1f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f32.f16( @@ -1099,10 +1099,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv2f32_nxv2f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv2f32_nxv2f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f32.f16( @@ -1118,10 +1118,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv4f32_nxv4f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv4f32_nxv4f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f32.f16( @@ -1137,10 +1137,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv8f32_nxv8f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv8f32_nxv8f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f32.f16( @@ -1156,10 +1156,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv16f32_nxv16f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv16f32_nxv16f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv16f32.f16( @@ -1175,10 +1175,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv1f64_nxv1f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv1f64_nxv1f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f64.f32( @@ -1194,10 +1194,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv2f64_nxv2f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv2f64_nxv2f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f64.f32( @@ -1213,10 +1213,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv4f64_nxv4f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv4f64_nxv4f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f64.f32( @@ -1232,10 +1232,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv8f64_nxv8f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv8f64_nxv8f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f64.f32( @@ -1251,10 +1251,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v10, v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -1270,10 +1270,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v10, v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -1289,10 +1289,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v12, v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -1308,10 +1308,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v16, v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -1327,10 +1327,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v10, v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -1346,10 +1346,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v12, v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -1365,10 +1365,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v16, v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -1384,10 +1384,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv8f64_nxv8f64_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v24, v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclip.ll b/llvm/test/CodeGen/RISCV/rvv/vnclip.ll index 54f4c17dd7ed..8902b1a28f8c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnclip.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnclip.ll @@ -13,8 +13,8 @@ declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -37,8 +37,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8( define @intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -85,8 +85,8 @@ declare @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.nxv2i8( define @intrinsic_vnclip_mask_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i8_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -109,8 +109,8 @@ declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8( define @intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.nxv4i8( define @intrinsic_vnclip_mask_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i8_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -157,8 +157,8 @@ declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8( define @intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnclip.wv v11, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: ret @@ -182,8 +182,8 @@ declare @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.nxv8i8( define @intrinsic_vnclip_mask_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i8_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: @@ -206,8 +206,8 @@ declare @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8( define @intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vnclip.wv v14, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: ret @@ -231,8 +231,8 @@ declare @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.nxv16i8( define @intrinsic_vnclip_mask_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i8_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t ; CHECK-NEXT: ret entry: @@ -255,8 +255,8 @@ declare @llvm.riscv.vnclip.nxv32i8.nxv32i16.nxv32i8( define @intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vnclip.wv v20, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v20 ; CHECK-NEXT: ret @@ -280,8 +280,8 @@ declare @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.nxv32i8( define @intrinsic_vnclip_mask_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv32i8_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t ; CHECK-NEXT: ret entry: @@ -304,8 +304,8 @@ declare @llvm.riscv.vnclip.nxv1i16.nxv1i32.nxv1i16( define @intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -328,8 +328,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.nxv1i16( define @intrinsic_vnclip_mask_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i16_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -352,8 +352,8 @@ declare @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16( define @intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -376,8 +376,8 @@ declare @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.nxv2i16( define @intrinsic_vnclip_mask_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i16_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -400,8 +400,8 @@ declare @llvm.riscv.vnclip.nxv4i16.nxv4i32.nxv4i16( define @intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vnclip.wv v11, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: ret @@ -425,8 +425,8 @@ declare @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.nxv4i16( define @intrinsic_vnclip_mask_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i16_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: @@ -449,8 +449,8 @@ declare @llvm.riscv.vnclip.nxv8i16.nxv8i32.nxv8i16( define @intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vnclip.wv v14, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: ret @@ -474,8 +474,8 @@ declare @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.nxv8i16( define @intrinsic_vnclip_mask_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i16_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t ; CHECK-NEXT: ret entry: @@ -498,8 +498,8 @@ declare @llvm.riscv.vnclip.nxv16i16.nxv16i32.nxv16i16( define @intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vnclip.wv v20, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v20 ; CHECK-NEXT: ret @@ -523,8 +523,8 @@ declare @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.nxv16i16( define @intrinsic_vnclip_mask_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i16_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t ; CHECK-NEXT: ret entry: @@ -547,8 +547,8 @@ declare @llvm.riscv.vnclip.nxv1i32.nxv1i64.nxv1i32( define @intrinsic_vnclip_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i32_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -571,8 +571,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64.nxv1i32( define @intrinsic_vnclip_mask_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i32_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -595,8 +595,8 @@ declare @llvm.riscv.vnclip.nxv2i32.nxv2i64.nxv2i32( define @intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vnclip.wv v11, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: ret @@ -620,8 +620,8 @@ declare @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64.nxv2i32( define @intrinsic_vnclip_mask_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i32_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: @@ -644,8 +644,8 @@ declare @llvm.riscv.vnclip.nxv4i32.nxv4i64.nxv4i32( define @intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vnclip.wv v14, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: ret @@ -669,8 +669,8 @@ declare @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64.nxv4i32( define @intrinsic_vnclip_mask_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i32_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t ; CHECK-NEXT: ret entry: @@ -693,8 +693,8 @@ declare @llvm.riscv.vnclip.nxv8i32.nxv8i64.nxv8i32( define @intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vnclip.wv v20, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v20 ; CHECK-NEXT: ret @@ -718,8 +718,8 @@ declare @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64.nxv8i32( define @intrinsic_vnclip_mask_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i32_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t ; CHECK-NEXT: ret entry: @@ -741,8 +741,8 @@ declare @llvm.riscv.vnclip.nxv1i8.nxv1i16( define @intrinsic_vnclip_vx_nxv1i8_nxv1i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vnclip.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -765,8 +765,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16( define @intrinsic_vnclip_mask_vx_nxv1i8_nxv1i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -788,8 +788,8 @@ declare @llvm.riscv.vnclip.nxv2i8.nxv2i16( define @intrinsic_vnclip_vx_nxv2i8_nxv2i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vnclip.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -812,8 +812,8 @@ declare @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16( define @intrinsic_vnclip_mask_vx_nxv2i8_nxv2i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -835,8 +835,8 @@ declare @llvm.riscv.vnclip.nxv4i8.nxv4i16( define @intrinsic_vnclip_vx_nxv4i8_nxv4i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vnclip.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -859,8 +859,8 @@ declare @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16( define @intrinsic_vnclip_mask_vx_nxv4i8_nxv4i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -882,8 +882,8 @@ declare @llvm.riscv.vnclip.nxv8i8.nxv8i16( define @intrinsic_vnclip_vx_nxv8i8_nxv8i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vnclip.wx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -907,8 +907,8 @@ declare @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16( define @intrinsic_vnclip_mask_vx_nxv8i8_nxv8i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -930,8 +930,8 @@ declare @llvm.riscv.vnclip.nxv16i8.nxv16i16( define @intrinsic_vnclip_vx_nxv16i8_nxv16i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vnclip.wx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -955,8 +955,8 @@ declare @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16( define @intrinsic_vnclip_mask_vx_nxv16i8_nxv16i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -978,8 +978,8 @@ declare @llvm.riscv.vnclip.nxv32i8.nxv32i16( define @intrinsic_vnclip_vx_nxv32i8_nxv32i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vnclip.wx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1003,8 +1003,8 @@ declare @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16( define @intrinsic_vnclip_mask_vx_nxv32i8_nxv32i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1026,8 +1026,8 @@ declare @llvm.riscv.vnclip.nxv1i16.nxv1i32( define @intrinsic_vnclip_vx_nxv1i16_nxv1i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vnclip.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1050,8 +1050,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32( define @intrinsic_vnclip_mask_vx_nxv1i16_nxv1i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1073,8 +1073,8 @@ declare @llvm.riscv.vnclip.nxv2i16.nxv2i32( define @intrinsic_vnclip_vx_nxv2i16_nxv2i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vnclip.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32( define @intrinsic_vnclip_mask_vx_nxv2i16_nxv2i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1120,8 +1120,8 @@ declare @llvm.riscv.vnclip.nxv4i16.nxv4i32( define @intrinsic_vnclip_vx_nxv4i16_nxv4i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vnclip.wx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1145,8 +1145,8 @@ declare @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32( define @intrinsic_vnclip_mask_vx_nxv4i16_nxv4i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1168,8 +1168,8 @@ declare @llvm.riscv.vnclip.nxv8i16.nxv8i32( define @intrinsic_vnclip_vx_nxv8i16_nxv8i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vnclip.wx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1193,8 +1193,8 @@ declare @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32( define @intrinsic_vnclip_mask_vx_nxv8i16_nxv8i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1216,8 +1216,8 @@ declare @llvm.riscv.vnclip.nxv16i16.nxv16i32( define @intrinsic_vnclip_vx_nxv16i16_nxv16i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vnclip.wx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1241,8 +1241,8 @@ declare @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32( define @intrinsic_vnclip_mask_vx_nxv16i16_nxv16i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1264,8 +1264,8 @@ declare @llvm.riscv.vnclip.nxv1i32.nxv1i64( define @intrinsic_vnclip_vx_nxv1i32_nxv1i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vnclip.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1288,8 +1288,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64( define @intrinsic_vnclip_mask_vx_nxv1i32_nxv1i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1311,8 +1311,8 @@ declare @llvm.riscv.vnclip.nxv2i32.nxv2i64( define @intrinsic_vnclip_vx_nxv2i32_nxv2i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vnclip.wx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1336,8 +1336,8 @@ declare @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64( define @intrinsic_vnclip_mask_vx_nxv2i32_nxv2i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1359,8 +1359,8 @@ declare @llvm.riscv.vnclip.nxv4i32.nxv4i64( define @intrinsic_vnclip_vx_nxv4i32_nxv4i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vnclip.wx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1384,8 +1384,8 @@ declare @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64( define @intrinsic_vnclip_mask_vx_nxv4i32_nxv4i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1407,8 +1407,8 @@ declare @llvm.riscv.vnclip.nxv8i32.nxv8i64( define @intrinsic_vnclip_vx_nxv8i32_nxv8i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vnclip.wx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1432,8 +1432,8 @@ declare @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64( define @intrinsic_vnclip_mask_vx_nxv8i32_nxv8i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1450,8 +1450,8 @@ entry: define @intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnclip.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1467,8 +1467,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv1i8_nxv1i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i8_nxv1i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1485,8 +1485,8 @@ entry: define @intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vnclip.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1502,8 +1502,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv2i8_nxv2i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i8_nxv2i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1520,8 +1520,8 @@ entry: define @intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vnclip.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1537,8 +1537,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv4i8_nxv4i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i8_nxv4i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1555,8 +1555,8 @@ entry: define @intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnclip.wi v10, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1573,8 +1573,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv8i8_nxv8i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i8_nxv8i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1591,8 +1591,8 @@ entry: define @intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vnclip.wi v12, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1609,8 +1609,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv16i8_nxv16i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv16i8_nxv16i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1627,8 +1627,8 @@ entry: define @intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vnclip.wi v16, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1645,8 +1645,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv32i8_nxv32i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv32i8_nxv32i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1663,8 +1663,8 @@ entry: define @intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vnclip.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1680,8 +1680,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv1i16_nxv1i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i16_nxv1i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1698,8 +1698,8 @@ entry: define @intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vnclip.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1715,8 +1715,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv2i16_nxv2i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i16_nxv2i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1733,8 +1733,8 @@ entry: define @intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vnclip.wi v10, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1751,8 +1751,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv4i16_nxv4i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i16_nxv4i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ entry: define @intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vnclip.wi v12, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1787,8 +1787,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv8i16_nxv8i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i16_nxv8i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1805,8 +1805,8 @@ entry: define @intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vnclip.wi v16, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1823,8 +1823,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv16i16_nxv16i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv16i16_nxv16i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1841,8 +1841,8 @@ entry: define @intrinsic_vnclip_vi_nxv1i32_nxv1i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i32_nxv1i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vnclip.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1858,8 +1858,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv1i32_nxv1i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i32_nxv1i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1876,8 +1876,8 @@ entry: define @intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vnclip.wi v10, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1894,8 +1894,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv2i32_nxv2i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i32_nxv2i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1912,8 +1912,8 @@ entry: define @intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vnclip.wi v12, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1930,8 +1930,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv4i32_nxv4i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i32_nxv4i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1948,8 +1948,8 @@ entry: define @intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vnclip.wi v16, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1966,8 +1966,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv8i32_nxv8i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i32_nxv8i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclipu.ll b/llvm/test/CodeGen/RISCV/rvv/vnclipu.ll index 39980504f887..a1804e7d98a4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnclipu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnclipu.ll @@ -13,8 +13,8 @@ declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnclipu.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -37,8 +37,8 @@ declare @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclipu_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8( define @intrinsic_vnclipu_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i8_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vnclipu.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -85,8 +85,8 @@ declare @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.nxv2i8( define @intrinsic_vnclipu_mask_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i8_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -109,8 +109,8 @@ declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8( define @intrinsic_vnclipu_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i8_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vnclipu.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.nxv4i8( define @intrinsic_vnclipu_mask_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i8_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -157,8 +157,8 @@ declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8( define @intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnclipu.wv v11, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: ret @@ -182,8 +182,8 @@ declare @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.nxv8i8( define @intrinsic_vnclipu_mask_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i8_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: @@ -206,8 +206,8 @@ declare @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8( define @intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vnclipu.wv v14, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: ret @@ -231,8 +231,8 @@ declare @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.nxv16i8( define @intrinsic_vnclipu_mask_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv16i8_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v12, v10, v0.t ; CHECK-NEXT: ret entry: @@ -255,8 +255,8 @@ declare @llvm.riscv.vnclipu.nxv32i8.nxv32i16.nxv32i8( define @intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vnclipu.wv v20, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v20 ; CHECK-NEXT: ret @@ -280,8 +280,8 @@ declare @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.nxv32i8( define @intrinsic_vnclipu_mask_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv32i8_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v16, v12, v0.t ; CHECK-NEXT: ret entry: @@ -304,8 +304,8 @@ declare @llvm.riscv.vnclipu.nxv1i16.nxv1i32.nxv1i16( define @intrinsic_vnclipu_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i16_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vnclipu.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -328,8 +328,8 @@ declare @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.nxv1i16( define @intrinsic_vnclipu_mask_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i16_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -352,8 +352,8 @@ declare @llvm.riscv.vnclipu.nxv2i16.nxv2i32.nxv2i16( define @intrinsic_vnclipu_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i16_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vnclipu.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -376,8 +376,8 @@ declare @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.nxv2i16( define @intrinsic_vnclipu_mask_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i16_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -400,8 +400,8 @@ declare @llvm.riscv.vnclipu.nxv4i16.nxv4i32.nxv4i16( define @intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vnclipu.wv v11, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: ret @@ -425,8 +425,8 @@ declare @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.nxv4i16( define @intrinsic_vnclipu_mask_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i16_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: @@ -449,8 +449,8 @@ declare @llvm.riscv.vnclipu.nxv8i16.nxv8i32.nxv8i16( define @intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vnclipu.wv v14, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: ret @@ -474,8 +474,8 @@ declare @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.nxv8i16( define @intrinsic_vnclipu_mask_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i16_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v12, v10, v0.t ; CHECK-NEXT: ret entry: @@ -498,8 +498,8 @@ declare @llvm.riscv.vnclipu.nxv16i16.nxv16i32.nxv16i16( define @intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vnclipu.wv v20, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v20 ; CHECK-NEXT: ret @@ -523,8 +523,8 @@ declare @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.nxv16i16( define @intrinsic_vnclipu_mask_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv16i16_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v16, v12, v0.t ; CHECK-NEXT: ret entry: @@ -547,8 +547,8 @@ declare @llvm.riscv.vnclipu.nxv1i32.nxv1i64.nxv1i32( define @intrinsic_vnclipu_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i32_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vnclipu.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -571,8 +571,8 @@ declare @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64.nxv1i32( define @intrinsic_vnclipu_mask_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i32_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -595,8 +595,8 @@ declare @llvm.riscv.vnclipu.nxv2i32.nxv2i64.nxv2i32( define @intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vnclipu.wv v11, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: ret @@ -620,8 +620,8 @@ declare @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64.nxv2i32( define @intrinsic_vnclipu_mask_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i32_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: @@ -644,8 +644,8 @@ declare @llvm.riscv.vnclipu.nxv4i32.nxv4i64.nxv4i32( define @intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vnclipu.wv v14, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: ret @@ -669,8 +669,8 @@ declare @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64.nxv4i32( define @intrinsic_vnclipu_mask_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i32_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v12, v10, v0.t ; CHECK-NEXT: ret entry: @@ -693,8 +693,8 @@ declare @llvm.riscv.vnclipu.nxv8i32.nxv8i64.nxv8i32( define @intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vnclipu.wv v20, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v20 ; CHECK-NEXT: ret @@ -718,8 +718,8 @@ declare @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64.nxv8i32( define @intrinsic_vnclipu_mask_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i32_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v16, v12, v0.t ; CHECK-NEXT: ret entry: @@ -741,8 +741,8 @@ declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16( define @intrinsic_vnclipu_vx_nxv1i8_nxv1i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vnclipu.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -765,8 +765,8 @@ declare @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16( define @intrinsic_vnclipu_mask_vx_nxv1i8_nxv1i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -788,8 +788,8 @@ declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16( define @intrinsic_vnclipu_vx_nxv2i8_nxv2i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vnclipu.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -812,8 +812,8 @@ declare @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16( define @intrinsic_vnclipu_mask_vx_nxv2i8_nxv2i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -835,8 +835,8 @@ declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16( define @intrinsic_vnclipu_vx_nxv4i8_nxv4i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vnclipu.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -859,8 +859,8 @@ declare @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16( define @intrinsic_vnclipu_mask_vx_nxv4i8_nxv4i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -882,8 +882,8 @@ declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16( define @intrinsic_vnclipu_vx_nxv8i8_nxv8i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vnclipu.wx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -907,8 +907,8 @@ declare @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16( define @intrinsic_vnclipu_mask_vx_nxv8i8_nxv8i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -930,8 +930,8 @@ declare @llvm.riscv.vnclipu.nxv16i8.nxv16i16( define @intrinsic_vnclipu_vx_nxv16i8_nxv16i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vnclipu.wx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -955,8 +955,8 @@ declare @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16( define @intrinsic_vnclipu_mask_vx_nxv16i8_nxv16i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -978,8 +978,8 @@ declare @llvm.riscv.vnclipu.nxv32i8.nxv32i16( define @intrinsic_vnclipu_vx_nxv32i8_nxv32i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vnclipu.wx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1003,8 +1003,8 @@ declare @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16( define @intrinsic_vnclipu_mask_vx_nxv32i8_nxv32i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1026,8 +1026,8 @@ declare @llvm.riscv.vnclipu.nxv1i16.nxv1i32( define @intrinsic_vnclipu_vx_nxv1i16_nxv1i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vnclipu.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1050,8 +1050,8 @@ declare @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32( define @intrinsic_vnclipu_mask_vx_nxv1i16_nxv1i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1073,8 +1073,8 @@ declare @llvm.riscv.vnclipu.nxv2i16.nxv2i32( define @intrinsic_vnclipu_vx_nxv2i16_nxv2i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vnclipu.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32( define @intrinsic_vnclipu_mask_vx_nxv2i16_nxv2i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1120,8 +1120,8 @@ declare @llvm.riscv.vnclipu.nxv4i16.nxv4i32( define @intrinsic_vnclipu_vx_nxv4i16_nxv4i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vnclipu.wx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1145,8 +1145,8 @@ declare @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32( define @intrinsic_vnclipu_mask_vx_nxv4i16_nxv4i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1168,8 +1168,8 @@ declare @llvm.riscv.vnclipu.nxv8i16.nxv8i32( define @intrinsic_vnclipu_vx_nxv8i16_nxv8i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vnclipu.wx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1193,8 +1193,8 @@ declare @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32( define @intrinsic_vnclipu_mask_vx_nxv8i16_nxv8i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1216,8 +1216,8 @@ declare @llvm.riscv.vnclipu.nxv16i16.nxv16i32( define @intrinsic_vnclipu_vx_nxv16i16_nxv16i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vnclipu.wx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1241,8 +1241,8 @@ declare @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32( define @intrinsic_vnclipu_mask_vx_nxv16i16_nxv16i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1264,8 +1264,8 @@ declare @llvm.riscv.vnclipu.nxv1i32.nxv1i64( define @intrinsic_vnclipu_vx_nxv1i32_nxv1i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vnclipu.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1288,8 +1288,8 @@ declare @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64( define @intrinsic_vnclipu_mask_vx_nxv1i32_nxv1i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1311,8 +1311,8 @@ declare @llvm.riscv.vnclipu.nxv2i32.nxv2i64( define @intrinsic_vnclipu_vx_nxv2i32_nxv2i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vnclipu.wx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1336,8 +1336,8 @@ declare @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64( define @intrinsic_vnclipu_mask_vx_nxv2i32_nxv2i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1359,8 +1359,8 @@ declare @llvm.riscv.vnclipu.nxv4i32.nxv4i64( define @intrinsic_vnclipu_vx_nxv4i32_nxv4i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vnclipu.wx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1384,8 +1384,8 @@ declare @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64( define @intrinsic_vnclipu_mask_vx_nxv4i32_nxv4i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1407,8 +1407,8 @@ declare @llvm.riscv.vnclipu.nxv8i32.nxv8i64( define @intrinsic_vnclipu_vx_nxv8i32_nxv8i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vnclipu.wx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1432,8 +1432,8 @@ declare @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64( define @intrinsic_vnclipu_mask_vx_nxv8i32_nxv8i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1450,8 +1450,8 @@ entry: define @intrinsic_vnclipu_vi_nxv1i8_nxv1i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i8_nxv1i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnclipu.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1467,8 +1467,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv1i8_nxv1i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv1i8_nxv1i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1485,8 +1485,8 @@ entry: define @intrinsic_vnclipu_vi_nxv2i8_nxv2i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i8_nxv2i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vnclipu.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1502,8 +1502,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv2i8_nxv2i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv2i8_nxv2i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1520,8 +1520,8 @@ entry: define @intrinsic_vnclipu_vi_nxv4i8_nxv4i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i8_nxv4i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vnclipu.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1537,8 +1537,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv4i8_nxv4i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv4i8_nxv4i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1555,8 +1555,8 @@ entry: define @intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnclipu.wi v10, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1573,8 +1573,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv8i8_nxv8i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv8i8_nxv8i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1591,8 +1591,8 @@ entry: define @intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vnclipu.wi v12, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1609,8 +1609,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv16i8_nxv16i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv16i8_nxv16i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1627,8 +1627,8 @@ entry: define @intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vnclipu.wi v16, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1645,8 +1645,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv32i8_nxv32i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv32i8_nxv32i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1663,8 +1663,8 @@ entry: define @intrinsic_vnclipu_vi_nxv1i16_nxv1i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i16_nxv1i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vnclipu.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1680,8 +1680,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv1i16_nxv1i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv1i16_nxv1i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1698,8 +1698,8 @@ entry: define @intrinsic_vnclipu_vi_nxv2i16_nxv2i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i16_nxv2i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vnclipu.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1715,8 +1715,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv2i16_nxv2i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv2i16_nxv2i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1733,8 +1733,8 @@ entry: define @intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vnclipu.wi v10, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1751,8 +1751,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv4i16_nxv4i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv4i16_nxv4i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ entry: define @intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vnclipu.wi v12, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1787,8 +1787,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv8i16_nxv8i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv8i16_nxv8i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1805,8 +1805,8 @@ entry: define @intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vnclipu.wi v16, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1823,8 +1823,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv16i16_nxv16i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv16i16_nxv16i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1841,8 +1841,8 @@ entry: define @intrinsic_vnclipu_vi_nxv1i32_nxv1i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i32_nxv1i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vnclipu.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1858,8 +1858,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv1i32_nxv1i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv1i32_nxv1i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1876,8 +1876,8 @@ entry: define @intrinsic_vnclipu_vi_nxv2i32_nxv2i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i32_nxv2i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vnclipu.wi v10, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1894,8 +1894,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv2i32_nxv2i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv2i32_nxv2i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1912,8 +1912,8 @@ entry: define @intrinsic_vnclipu_vi_nxv4i32_nxv4i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i32_nxv4i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vnclipu.wi v12, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1930,8 +1930,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv4i32_nxv4i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv4i32_nxv4i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1948,8 +1948,8 @@ entry: define @intrinsic_vnclipu_vi_nxv8i32_nxv8i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i32_nxv8i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vnclipu.wi v16, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1966,8 +1966,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv8i32_nxv8i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv8i32_nxv8i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll index d1fcb0f47cb5..e7d8ae635f75 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll @@ -15,8 +15,8 @@ declare @llvm.riscv.vsmul.nxv1i8.nxv1i8( define @intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -39,8 +39,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -63,8 +63,8 @@ declare @llvm.riscv.vsmul.nxv2i8.nxv2i8( define @intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -87,8 +87,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i8.nxv2i8( define @intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -111,8 +111,8 @@ declare @llvm.riscv.vsmul.nxv4i8.nxv4i8( define @intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -135,8 +135,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i8.nxv4i8( define @intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -159,8 +159,8 @@ declare @llvm.riscv.vsmul.nxv8i8.nxv8i8( define @intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -183,8 +183,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i8.nxv8i8( define @intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -207,8 +207,8 @@ declare @llvm.riscv.vsmul.nxv16i8.nxv16i8( define @intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -231,8 +231,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i8.nxv16i8( define @intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -255,8 +255,8 @@ declare @llvm.riscv.vsmul.nxv32i8.nxv32i8( define @intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -279,8 +279,8 @@ declare @llvm.riscv.vsmul.mask.nxv32i8.nxv32i8( define @intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -303,8 +303,8 @@ declare @llvm.riscv.vsmul.nxv64i8.nxv64i8( define @intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -328,8 +328,8 @@ define @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( @llvm.riscv.vsmul.nxv1i16.nxv1i16( define @intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -376,8 +376,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i16.nxv1i16( define @intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -400,8 +400,8 @@ declare @llvm.riscv.vsmul.nxv2i16.nxv2i16( define @intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -424,8 +424,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i16.nxv2i16( define @intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -448,8 +448,8 @@ declare @llvm.riscv.vsmul.nxv4i16.nxv4i16( define @intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -472,8 +472,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i16.nxv4i16( define @intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -496,8 +496,8 @@ declare @llvm.riscv.vsmul.nxv8i16.nxv8i16( define @intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -520,8 +520,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i16.nxv8i16( define @intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -544,8 +544,8 @@ declare @llvm.riscv.vsmul.nxv16i16.nxv16i16( define @intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -568,8 +568,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i16.nxv16i16( define @intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -592,8 +592,8 @@ declare @llvm.riscv.vsmul.nxv32i16.nxv32i16( define @intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -617,8 +617,8 @@ define @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(< ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -641,8 +641,8 @@ declare @llvm.riscv.vsmul.nxv1i32.nxv1i32( define @intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -665,8 +665,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i32.nxv1i32( define @intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -689,8 +689,8 @@ declare @llvm.riscv.vsmul.nxv2i32.nxv2i32( define @intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -713,8 +713,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i32.nxv2i32( define @intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -737,8 +737,8 @@ declare @llvm.riscv.vsmul.nxv4i32.nxv4i32( define @intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -761,8 +761,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i32.nxv4i32( define @intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -785,8 +785,8 @@ declare @llvm.riscv.vsmul.nxv8i32.nxv8i32( define @intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -809,8 +809,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i32.nxv8i32( define @intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -833,8 +833,8 @@ declare @llvm.riscv.vsmul.nxv16i32.nxv16i32( define @intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -858,8 +858,8 @@ define @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(< ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -882,8 +882,8 @@ declare @llvm.riscv.vsmul.nxv1i64.nxv1i64( define @intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -906,8 +906,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64( define @intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -930,8 +930,8 @@ declare @llvm.riscv.vsmul.nxv2i64.nxv2i64( define @intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -954,8 +954,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i64.nxv2i64( define @intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -978,8 +978,8 @@ declare @llvm.riscv.vsmul.nxv4i64.nxv4i64( define @intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -1002,8 +1002,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i64.nxv4i64( define @intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1026,8 +1026,8 @@ declare @llvm.riscv.vsmul.nxv8i64.nxv8i64( define @intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -1051,8 +1051,8 @@ define @intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64( @llvm.riscv.vsmul.nxv1i8.i8( define @intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1099,8 +1099,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.i8( define @intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1123,8 +1123,8 @@ declare @llvm.riscv.vsmul.nxv2i8.i8( define @intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1147,8 +1147,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i8.i8( define @intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1171,8 +1171,8 @@ declare @llvm.riscv.vsmul.nxv4i8.i8( define @intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1195,8 +1195,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i8.i8( define @intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1219,8 +1219,8 @@ declare @llvm.riscv.vsmul.nxv8i8.i8( define @intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1243,8 +1243,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i8.i8( define @intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1267,8 +1267,8 @@ declare @llvm.riscv.vsmul.nxv16i8.i8( define @intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1291,8 +1291,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i8.i8( define @intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1315,8 +1315,8 @@ declare @llvm.riscv.vsmul.nxv32i8.i8( define @intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1339,8 +1339,8 @@ declare @llvm.riscv.vsmul.mask.nxv32i8.i8( define @intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1363,8 +1363,8 @@ declare @llvm.riscv.vsmul.nxv64i8.i8( define @intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1387,8 +1387,8 @@ declare @llvm.riscv.vsmul.mask.nxv64i8.i8( define @intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1411,8 +1411,8 @@ declare @llvm.riscv.vsmul.nxv1i16.i16( define @intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1435,8 +1435,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i16.i16( define @intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1459,8 +1459,8 @@ declare @llvm.riscv.vsmul.nxv2i16.i16( define @intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1483,8 +1483,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i16.i16( define @intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1507,8 +1507,8 @@ declare @llvm.riscv.vsmul.nxv4i16.i16( define @intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1531,8 +1531,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i16.i16( define @intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1555,8 +1555,8 @@ declare @llvm.riscv.vsmul.nxv8i16.i16( define @intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1579,8 +1579,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i16.i16( define @intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1603,8 +1603,8 @@ declare @llvm.riscv.vsmul.nxv16i16.i16( define @intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1627,8 +1627,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i16.i16( define @intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1651,8 +1651,8 @@ declare @llvm.riscv.vsmul.nxv32i16.i16( define @intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1675,8 +1675,8 @@ declare @llvm.riscv.vsmul.mask.nxv32i16.i16( define @intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1698,8 +1698,8 @@ declare @llvm.riscv.vsmul.nxv1i32.i32( define @intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1722,8 +1722,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i32.i32( define @intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1745,8 +1745,8 @@ declare @llvm.riscv.vsmul.nxv2i32.i32( define @intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i32.i32( define @intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1792,8 +1792,8 @@ declare @llvm.riscv.vsmul.nxv4i32.i32( define @intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1816,8 +1816,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i32.i32( define @intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1839,8 +1839,8 @@ declare @llvm.riscv.vsmul.nxv8i32.i32( define @intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1863,8 +1863,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i32.i32( define @intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1886,8 +1886,8 @@ declare @llvm.riscv.vsmul.nxv16i32.i32( define @intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1910,8 +1910,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i32.i32( define @intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll index 1fe1baf1cef2..66bc5c9103a4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll @@ -15,8 +15,8 @@ declare @llvm.riscv.vsmul.nxv1i8.nxv1i8( define @intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -39,8 +39,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -63,8 +63,8 @@ declare @llvm.riscv.vsmul.nxv2i8.nxv2i8( define @intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -87,8 +87,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i8.nxv2i8( define @intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -111,8 +111,8 @@ declare @llvm.riscv.vsmul.nxv4i8.nxv4i8( define @intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -135,8 +135,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i8.nxv4i8( define @intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -159,8 +159,8 @@ declare @llvm.riscv.vsmul.nxv8i8.nxv8i8( define @intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -183,8 +183,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i8.nxv8i8( define @intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -207,8 +207,8 @@ declare @llvm.riscv.vsmul.nxv16i8.nxv16i8( define @intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -231,8 +231,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i8.nxv16i8( define @intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -255,8 +255,8 @@ declare @llvm.riscv.vsmul.nxv32i8.nxv32i8( define @intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -279,8 +279,8 @@ declare @llvm.riscv.vsmul.mask.nxv32i8.nxv32i8( define @intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -303,8 +303,8 @@ declare @llvm.riscv.vsmul.nxv64i8.nxv64i8( define @intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -328,8 +328,8 @@ define @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( @llvm.riscv.vsmul.nxv1i16.nxv1i16( define @intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -376,8 +376,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i16.nxv1i16( define @intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -400,8 +400,8 @@ declare @llvm.riscv.vsmul.nxv2i16.nxv2i16( define @intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -424,8 +424,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i16.nxv2i16( define @intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -448,8 +448,8 @@ declare @llvm.riscv.vsmul.nxv4i16.nxv4i16( define @intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -472,8 +472,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i16.nxv4i16( define @intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -496,8 +496,8 @@ declare @llvm.riscv.vsmul.nxv8i16.nxv8i16( define @intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -520,8 +520,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i16.nxv8i16( define @intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -544,8 +544,8 @@ declare @llvm.riscv.vsmul.nxv16i16.nxv16i16( define @intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -568,8 +568,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i16.nxv16i16( define @intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -592,8 +592,8 @@ declare @llvm.riscv.vsmul.nxv32i16.nxv32i16( define @intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -617,8 +617,8 @@ define @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(< ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -641,8 +641,8 @@ declare @llvm.riscv.vsmul.nxv1i32.nxv1i32( define @intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -665,8 +665,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i32.nxv1i32( define @intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -689,8 +689,8 @@ declare @llvm.riscv.vsmul.nxv2i32.nxv2i32( define @intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -713,8 +713,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i32.nxv2i32( define @intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -737,8 +737,8 @@ declare @llvm.riscv.vsmul.nxv4i32.nxv4i32( define @intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -761,8 +761,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i32.nxv4i32( define @intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -785,8 +785,8 @@ declare @llvm.riscv.vsmul.nxv8i32.nxv8i32( define @intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -809,8 +809,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i32.nxv8i32( define @intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -833,8 +833,8 @@ declare @llvm.riscv.vsmul.nxv16i32.nxv16i32( define @intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -858,8 +858,8 @@ define @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(< ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -882,8 +882,8 @@ declare @llvm.riscv.vsmul.nxv1i64.nxv1i64( define @intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -906,8 +906,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64( define @intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -930,8 +930,8 @@ declare @llvm.riscv.vsmul.nxv2i64.nxv2i64( define @intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -954,8 +954,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i64.nxv2i64( define @intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -978,8 +978,8 @@ declare @llvm.riscv.vsmul.nxv4i64.nxv4i64( define @intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -1002,8 +1002,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i64.nxv4i64( define @intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1026,8 +1026,8 @@ declare @llvm.riscv.vsmul.nxv8i64.nxv8i64( define @intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -1051,8 +1051,8 @@ define @intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64( @llvm.riscv.vsmul.nxv1i8.i8( define @intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1099,8 +1099,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.i8( define @intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1123,8 +1123,8 @@ declare @llvm.riscv.vsmul.nxv2i8.i8( define @intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1147,8 +1147,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i8.i8( define @intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1171,8 +1171,8 @@ declare @llvm.riscv.vsmul.nxv4i8.i8( define @intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1195,8 +1195,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i8.i8( define @intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1219,8 +1219,8 @@ declare @llvm.riscv.vsmul.nxv8i8.i8( define @intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1243,8 +1243,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i8.i8( define @intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1267,8 +1267,8 @@ declare @llvm.riscv.vsmul.nxv16i8.i8( define @intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1291,8 +1291,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i8.i8( define @intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1315,8 +1315,8 @@ declare @llvm.riscv.vsmul.nxv32i8.i8( define @intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1339,8 +1339,8 @@ declare @llvm.riscv.vsmul.mask.nxv32i8.i8( define @intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1363,8 +1363,8 @@ declare @llvm.riscv.vsmul.nxv64i8.i8( define @intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1387,8 +1387,8 @@ declare @llvm.riscv.vsmul.mask.nxv64i8.i8( define @intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1411,8 +1411,8 @@ declare @llvm.riscv.vsmul.nxv1i16.i16( define @intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1435,8 +1435,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i16.i16( define @intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1459,8 +1459,8 @@ declare @llvm.riscv.vsmul.nxv2i16.i16( define @intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1483,8 +1483,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i16.i16( define @intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1507,8 +1507,8 @@ declare @llvm.riscv.vsmul.nxv4i16.i16( define @intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1531,8 +1531,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i16.i16( define @intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1555,8 +1555,8 @@ declare @llvm.riscv.vsmul.nxv8i16.i16( define @intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1579,8 +1579,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i16.i16( define @intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1603,8 +1603,8 @@ declare @llvm.riscv.vsmul.nxv16i16.i16( define @intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1627,8 +1627,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i16.i16( define @intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1651,8 +1651,8 @@ declare @llvm.riscv.vsmul.nxv32i16.i16( define @intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1675,8 +1675,8 @@ declare @llvm.riscv.vsmul.mask.nxv32i16.i16( define @intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1699,8 +1699,8 @@ declare @llvm.riscv.vsmul.nxv1i32.i32( define @intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1723,8 +1723,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i32.i32( define @intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1747,8 +1747,8 @@ declare @llvm.riscv.vsmul.nxv2i32.i32( define @intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1771,8 +1771,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i32.i32( define @intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1795,8 +1795,8 @@ declare @llvm.riscv.vsmul.nxv4i32.i32( define @intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1819,8 +1819,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i32.i32( define @intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1843,8 +1843,8 @@ declare @llvm.riscv.vsmul.nxv8i32.i32( define @intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1867,8 +1867,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i32.i32( define @intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1891,8 +1891,8 @@ declare @llvm.riscv.vsmul.nxv16i32.i32( define @intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1915,8 +1915,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i32.i32( define @intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1938,8 +1938,8 @@ declare @llvm.riscv.vsmul.nxv1i64.i64( define @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1962,8 +1962,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i64.i64( define @intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1985,8 +1985,8 @@ declare @llvm.riscv.vsmul.nxv2i64.i64( define @intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -2009,8 +2009,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i64.i64( define @intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -2032,8 +2032,8 @@ declare @llvm.riscv.vsmul.nxv4i64.i64( define @intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -2056,8 +2056,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i64.i64( define @intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -2079,8 +2079,8 @@ declare @llvm.riscv.vsmul.nxv8i64.i64( define @intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -2103,8 +2103,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i64.i64( define @intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll index 8e28dd490a87..7fd1b05bb444 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll @@ -5,8 +5,8 @@ define @test_vssra_vv_i8mf8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -19,8 +19,8 @@ declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i32(, define @test_vssra_vx_i8mf8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -33,8 +33,8 @@ declare @llvm.riscv.vssra.nxv1i8.i32.i32(, @test_vssra_vv_i8mf4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -47,8 +47,8 @@ declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i32(, define @test_vssra_vx_i8mf4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vssra.nxv2i8.i32.i32(, @test_vssra_vv_i8mf2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -75,8 +75,8 @@ declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i32(, define @test_vssra_vx_i8mf2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -89,8 +89,8 @@ declare @llvm.riscv.vssra.nxv4i8.i32.i32(, @test_vssra_vv_i8m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -103,8 +103,8 @@ declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i32(, define @test_vssra_vx_i8m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -117,8 +117,8 @@ declare @llvm.riscv.vssra.nxv8i8.i32.i32(, @test_vssra_vv_i8m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -131,8 +131,8 @@ declare @llvm.riscv.vssra.nxv16i8.nxv16i8.i32( @test_vssra_vx_i8m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -145,8 +145,8 @@ declare @llvm.riscv.vssra.nxv16i8.i32.i32(, define @test_vssra_vv_i8m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -159,8 +159,8 @@ declare @llvm.riscv.vssra.nxv32i8.nxv32i8.i32( @test_vssra_vx_i8m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -173,8 +173,8 @@ declare @llvm.riscv.vssra.nxv32i8.i32.i32(, define @test_vssra_vv_i8m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -187,8 +187,8 @@ declare @llvm.riscv.vssra.nxv64i8.nxv64i8.i32( @test_vssra_vx_i8m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -201,8 +201,8 @@ declare @llvm.riscv.vssra.nxv64i8.i32.i32(, define @test_vssra_vv_i16mf4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -215,8 +215,8 @@ declare @llvm.riscv.vssra.nxv1i16.nxv1i16.i32( @test_vssra_vx_i16mf4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vssra.nxv1i16.i32.i32(, define @test_vssra_vv_i16mf2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -243,8 +243,8 @@ declare @llvm.riscv.vssra.nxv2i16.nxv2i16.i32( @test_vssra_vx_i16mf2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -257,8 +257,8 @@ declare @llvm.riscv.vssra.nxv2i16.i32.i32(, define @test_vssra_vv_i16m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -271,8 +271,8 @@ declare @llvm.riscv.vssra.nxv4i16.nxv4i16.i32( @test_vssra_vx_i16m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -285,8 +285,8 @@ declare @llvm.riscv.vssra.nxv4i16.i32.i32(, define @test_vssra_vv_i16m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -299,8 +299,8 @@ declare @llvm.riscv.vssra.nxv8i16.nxv8i16.i32( @test_vssra_vx_i16m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -313,8 +313,8 @@ declare @llvm.riscv.vssra.nxv8i16.i32.i32(, define @test_vssra_vv_i16m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -327,8 +327,8 @@ declare @llvm.riscv.vssra.nxv16i16.nxv16i16.i32( @test_vssra_vx_i16m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -341,8 +341,8 @@ declare @llvm.riscv.vssra.nxv16i16.i32.i32( @test_vssra_vv_i16m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -355,8 +355,8 @@ declare @llvm.riscv.vssra.nxv32i16.nxv32i16.i32( @test_vssra_vx_i16m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -369,8 +369,8 @@ declare @llvm.riscv.vssra.nxv32i16.i32.i32( @test_vssra_vv_i32mf2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -383,8 +383,8 @@ declare @llvm.riscv.vssra.nxv1i32.nxv1i32.i32( @test_vssra_vx_i32mf2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -397,8 +397,8 @@ declare @llvm.riscv.vssra.nxv1i32.i32.i32(, define @test_vssra_vv_i32m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -411,8 +411,8 @@ declare @llvm.riscv.vssra.nxv2i32.nxv2i32.i32( @test_vssra_vx_i32m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -425,8 +425,8 @@ declare @llvm.riscv.vssra.nxv2i32.i32.i32(, define @test_vssra_vv_i32m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -439,8 +439,8 @@ declare @llvm.riscv.vssra.nxv4i32.nxv4i32.i32( @test_vssra_vx_i32m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -453,8 +453,8 @@ declare @llvm.riscv.vssra.nxv4i32.i32.i32(, define @test_vssra_vv_i32m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -467,8 +467,8 @@ declare @llvm.riscv.vssra.nxv8i32.nxv8i32.i32( @test_vssra_vx_i32m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -481,8 +481,8 @@ declare @llvm.riscv.vssra.nxv8i32.i32.i32(, define @test_vssra_vv_i32m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -495,8 +495,8 @@ declare @llvm.riscv.vssra.nxv16i32.nxv16i32.i32( @test_vssra_vx_i32m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -509,8 +509,8 @@ declare @llvm.riscv.vssra.nxv16i32.i32.i32( @test_vssra_vv_i64m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -523,8 +523,8 @@ declare @llvm.riscv.vssra.nxv1i64.nxv1i64.i32( @test_vssra_vx_i64m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -537,8 +537,8 @@ declare @llvm.riscv.vssra.nxv1i64.i32.i32(, define @test_vssra_vv_i64m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -551,8 +551,8 @@ declare @llvm.riscv.vssra.nxv2i64.nxv2i64.i32( @test_vssra_vx_i64m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -565,8 +565,8 @@ declare @llvm.riscv.vssra.nxv2i64.i32.i32(, define @test_vssra_vv_i64m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -579,8 +579,8 @@ declare @llvm.riscv.vssra.nxv4i64.nxv4i64.i32( @test_vssra_vx_i64m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -593,8 +593,8 @@ declare @llvm.riscv.vssra.nxv4i64.i32.i32(, define @test_vssra_vv_i64m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -607,8 +607,8 @@ declare @llvm.riscv.vssra.nxv8i64.nxv8i64.i32( @test_vssra_vx_i64m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -621,8 +621,8 @@ declare @llvm.riscv.vssra.nxv8i64.i32.i32(, define @test_vssra_vv_i8mf8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -635,8 +635,8 @@ declare @llvm.riscv.vssra.mask.nxv1i8.nxv1i8.i32( @test_vssra_vx_i8mf8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -649,8 +649,8 @@ declare @llvm.riscv.vssra.mask.nxv1i8.i32.i32( @test_vssra_vv_i8mf4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vssra.mask.nxv2i8.nxv2i8.i32( @test_vssra_vx_i8mf4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -677,8 +677,8 @@ declare @llvm.riscv.vssra.mask.nxv2i8.i32.i32( @test_vssra_vv_i8mf2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -691,8 +691,8 @@ declare @llvm.riscv.vssra.mask.nxv4i8.nxv4i8.i32( @test_vssra_vx_i8mf2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -705,8 +705,8 @@ declare @llvm.riscv.vssra.mask.nxv4i8.i32.i32( @test_vssra_vv_i8m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ declare @llvm.riscv.vssra.mask.nxv8i8.nxv8i8.i32( @test_vssra_vx_i8m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -733,8 +733,8 @@ declare @llvm.riscv.vssra.mask.nxv8i8.i32.i32( @test_vssra_vv_i8m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -747,8 +747,8 @@ declare @llvm.riscv.vssra.mask.nxv16i8.nxv16i8.i32( @test_vssra_vx_i8m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -761,8 +761,8 @@ declare @llvm.riscv.vssra.mask.nxv16i8.i32.i32( @test_vssra_vv_i8m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -775,8 +775,8 @@ declare @llvm.riscv.vssra.mask.nxv32i8.nxv32i8.i32( @test_vssra_vx_i8m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -789,8 +789,8 @@ declare @llvm.riscv.vssra.mask.nxv32i8.i32.i32( @test_vssra_vv_i8m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -803,8 +803,8 @@ declare @llvm.riscv.vssra.mask.nxv64i8.nxv64i8.i32( @test_vssra_vx_i8m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -817,8 +817,8 @@ declare @llvm.riscv.vssra.mask.nxv64i8.i32.i32( @test_vssra_vv_i16mf4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vssra.mask.nxv1i16.nxv1i16.i32( @test_vssra_vx_i16mf4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -845,8 +845,8 @@ declare @llvm.riscv.vssra.mask.nxv1i16.i32.i32( @test_vssra_vv_i16mf2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -859,8 +859,8 @@ declare @llvm.riscv.vssra.mask.nxv2i16.nxv2i16.i32( @test_vssra_vx_i16mf2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -873,8 +873,8 @@ declare @llvm.riscv.vssra.mask.nxv2i16.i32.i32( @test_vssra_vv_i16m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -887,8 +887,8 @@ declare @llvm.riscv.vssra.mask.nxv4i16.nxv4i16.i32( @test_vssra_vx_i16m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -901,8 +901,8 @@ declare @llvm.riscv.vssra.mask.nxv4i16.i32.i32( @test_vssra_vv_i16m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -915,8 +915,8 @@ declare @llvm.riscv.vssra.mask.nxv8i16.nxv8i16.i32( @test_vssra_vx_i16m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -929,8 +929,8 @@ declare @llvm.riscv.vssra.mask.nxv8i16.i32.i32( @test_vssra_vv_i16m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -943,8 +943,8 @@ declare @llvm.riscv.vssra.mask.nxv16i16.nxv16i16.i32( @test_vssra_vx_i16m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -957,8 +957,8 @@ declare @llvm.riscv.vssra.mask.nxv16i16.i32.i32( @test_vssra_vv_i16m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -971,8 +971,8 @@ declare @llvm.riscv.vssra.mask.nxv32i16.nxv32i16.i32( @test_vssra_vx_i16m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -985,8 +985,8 @@ declare @llvm.riscv.vssra.mask.nxv32i16.i32.i32( @test_vssra_vv_i32mf2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -999,8 +999,8 @@ declare @llvm.riscv.vssra.mask.nxv1i32.nxv1i32.i32( @test_vssra_vx_i32mf2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1013,8 +1013,8 @@ declare @llvm.riscv.vssra.mask.nxv1i32.i32.i32( @test_vssra_vv_i32m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1027,8 +1027,8 @@ declare @llvm.riscv.vssra.mask.nxv2i32.nxv2i32.i32( @test_vssra_vx_i32m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1041,8 +1041,8 @@ declare @llvm.riscv.vssra.mask.nxv2i32.i32.i32( @test_vssra_vv_i32m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1055,8 +1055,8 @@ declare @llvm.riscv.vssra.mask.nxv4i32.nxv4i32.i32( @test_vssra_vx_i32m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1069,8 +1069,8 @@ declare @llvm.riscv.vssra.mask.nxv4i32.i32.i32( @test_vssra_vv_i32m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1083,8 +1083,8 @@ declare @llvm.riscv.vssra.mask.nxv8i32.nxv8i32.i32( @test_vssra_vx_i32m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vssra.mask.nxv8i32.i32.i32( @test_vssra_vv_i32m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1111,8 +1111,8 @@ declare @llvm.riscv.vssra.mask.nxv16i32.nxv16i32.i32( @test_vssra_vx_i32m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1125,8 +1125,8 @@ declare @llvm.riscv.vssra.mask.nxv16i32.i32.i32( @test_vssra_vv_i64m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1139,8 +1139,8 @@ declare @llvm.riscv.vssra.mask.nxv1i64.nxv1i64.i32( @test_vssra_vx_i64m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1153,8 +1153,8 @@ declare @llvm.riscv.vssra.mask.nxv1i64.i32.i32( @test_vssra_vv_i64m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1167,8 +1167,8 @@ declare @llvm.riscv.vssra.mask.nxv2i64.nxv2i64.i32( @test_vssra_vx_i64m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1181,8 +1181,8 @@ declare @llvm.riscv.vssra.mask.nxv2i64.i32.i32( @test_vssra_vv_i64m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1195,8 +1195,8 @@ declare @llvm.riscv.vssra.mask.nxv4i64.nxv4i64.i32( @test_vssra_vx_i64m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1209,8 +1209,8 @@ declare @llvm.riscv.vssra.mask.nxv4i64.i32.i32( @test_vssra_vv_i64m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1223,8 +1223,8 @@ declare @llvm.riscv.vssra.mask.nxv8i64.nxv8i64.i32( @test_vssra_vx_i64m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll index 96ca5e32cf36..b7a84e58e6e6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll @@ -5,8 +5,8 @@ define @test_vssra_vv_i8mf8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -19,8 +19,8 @@ declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, define @test_vssra_vx_i8mf8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -33,8 +33,8 @@ declare @llvm.riscv.vssra.nxv1i8.i64.i64(, @test_vssra_vv_i8mf4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -47,8 +47,8 @@ declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, define @test_vssra_vx_i8mf4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vssra.nxv2i8.i64.i64(, @test_vssra_vv_i8mf2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -75,8 +75,8 @@ declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, define @test_vssra_vx_i8mf2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -89,8 +89,8 @@ declare @llvm.riscv.vssra.nxv4i8.i64.i64(, @test_vssra_vv_i8m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -103,8 +103,8 @@ declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, define @test_vssra_vx_i8m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -117,8 +117,8 @@ declare @llvm.riscv.vssra.nxv8i8.i64.i64(, @test_vssra_vv_i8m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -131,8 +131,8 @@ declare @llvm.riscv.vssra.nxv16i8.nxv16i8.i64( @test_vssra_vx_i8m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -145,8 +145,8 @@ declare @llvm.riscv.vssra.nxv16i8.i64.i64(, define @test_vssra_vv_i8m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -159,8 +159,8 @@ declare @llvm.riscv.vssra.nxv32i8.nxv32i8.i64( @test_vssra_vx_i8m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -173,8 +173,8 @@ declare @llvm.riscv.vssra.nxv32i8.i64.i64(, define @test_vssra_vv_i8m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -187,8 +187,8 @@ declare @llvm.riscv.vssra.nxv64i8.nxv64i8.i64( @test_vssra_vx_i8m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -201,8 +201,8 @@ declare @llvm.riscv.vssra.nxv64i8.i64.i64(, define @test_vssra_vv_i16mf4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -215,8 +215,8 @@ declare @llvm.riscv.vssra.nxv1i16.nxv1i16.i64( @test_vssra_vx_i16mf4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vssra.nxv1i16.i64.i64(, define @test_vssra_vv_i16mf2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -243,8 +243,8 @@ declare @llvm.riscv.vssra.nxv2i16.nxv2i16.i64( @test_vssra_vx_i16mf2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -257,8 +257,8 @@ declare @llvm.riscv.vssra.nxv2i16.i64.i64(, define @test_vssra_vv_i16m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -271,8 +271,8 @@ declare @llvm.riscv.vssra.nxv4i16.nxv4i16.i64( @test_vssra_vx_i16m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -285,8 +285,8 @@ declare @llvm.riscv.vssra.nxv4i16.i64.i64(, define @test_vssra_vv_i16m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -299,8 +299,8 @@ declare @llvm.riscv.vssra.nxv8i16.nxv8i16.i64( @test_vssra_vx_i16m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -313,8 +313,8 @@ declare @llvm.riscv.vssra.nxv8i16.i64.i64(, define @test_vssra_vv_i16m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -327,8 +327,8 @@ declare @llvm.riscv.vssra.nxv16i16.nxv16i16.i64( @test_vssra_vx_i16m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -341,8 +341,8 @@ declare @llvm.riscv.vssra.nxv16i16.i64.i64( @test_vssra_vv_i16m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -355,8 +355,8 @@ declare @llvm.riscv.vssra.nxv32i16.nxv32i16.i64( @test_vssra_vx_i16m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -369,8 +369,8 @@ declare @llvm.riscv.vssra.nxv32i16.i64.i64( @test_vssra_vv_i32mf2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -383,8 +383,8 @@ declare @llvm.riscv.vssra.nxv1i32.nxv1i32.i64( @test_vssra_vx_i32mf2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -397,8 +397,8 @@ declare @llvm.riscv.vssra.nxv1i32.i64.i64(, define @test_vssra_vv_i32m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -411,8 +411,8 @@ declare @llvm.riscv.vssra.nxv2i32.nxv2i32.i64( @test_vssra_vx_i32m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -425,8 +425,8 @@ declare @llvm.riscv.vssra.nxv2i32.i64.i64(, define @test_vssra_vv_i32m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -439,8 +439,8 @@ declare @llvm.riscv.vssra.nxv4i32.nxv4i32.i64( @test_vssra_vx_i32m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -453,8 +453,8 @@ declare @llvm.riscv.vssra.nxv4i32.i64.i64(, define @test_vssra_vv_i32m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -467,8 +467,8 @@ declare @llvm.riscv.vssra.nxv8i32.nxv8i32.i64( @test_vssra_vx_i32m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -481,8 +481,8 @@ declare @llvm.riscv.vssra.nxv8i32.i64.i64(, define @test_vssra_vv_i32m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -495,8 +495,8 @@ declare @llvm.riscv.vssra.nxv16i32.nxv16i32.i64( @test_vssra_vx_i32m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -509,8 +509,8 @@ declare @llvm.riscv.vssra.nxv16i32.i64.i64( @test_vssra_vv_i64m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -523,8 +523,8 @@ declare @llvm.riscv.vssra.nxv1i64.nxv1i64.i64( @test_vssra_vx_i64m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -537,8 +537,8 @@ declare @llvm.riscv.vssra.nxv1i64.i64.i64(, define @test_vssra_vv_i64m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -551,8 +551,8 @@ declare @llvm.riscv.vssra.nxv2i64.nxv2i64.i64( @test_vssra_vx_i64m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -565,8 +565,8 @@ declare @llvm.riscv.vssra.nxv2i64.i64.i64(, define @test_vssra_vv_i64m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -579,8 +579,8 @@ declare @llvm.riscv.vssra.nxv4i64.nxv4i64.i64( @test_vssra_vx_i64m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -593,8 +593,8 @@ declare @llvm.riscv.vssra.nxv4i64.i64.i64(, define @test_vssra_vv_i64m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -607,8 +607,8 @@ declare @llvm.riscv.vssra.nxv8i64.nxv8i64.i64( @test_vssra_vx_i64m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -621,8 +621,8 @@ declare @llvm.riscv.vssra.nxv8i64.i64.i64(, define @test_vssra_vv_i8mf8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -635,8 +635,8 @@ declare @llvm.riscv.vssra.mask.nxv1i8.nxv1i8.i64( @test_vssra_vx_i8mf8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -649,8 +649,8 @@ declare @llvm.riscv.vssra.mask.nxv1i8.i64.i64( @test_vssra_vv_i8mf4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vssra.mask.nxv2i8.nxv2i8.i64( @test_vssra_vx_i8mf4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -677,8 +677,8 @@ declare @llvm.riscv.vssra.mask.nxv2i8.i64.i64( @test_vssra_vv_i8mf2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -691,8 +691,8 @@ declare @llvm.riscv.vssra.mask.nxv4i8.nxv4i8.i64( @test_vssra_vx_i8mf2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -705,8 +705,8 @@ declare @llvm.riscv.vssra.mask.nxv4i8.i64.i64( @test_vssra_vv_i8m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ declare @llvm.riscv.vssra.mask.nxv8i8.nxv8i8.i64( @test_vssra_vx_i8m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -733,8 +733,8 @@ declare @llvm.riscv.vssra.mask.nxv8i8.i64.i64( @test_vssra_vv_i8m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -747,8 +747,8 @@ declare @llvm.riscv.vssra.mask.nxv16i8.nxv16i8.i64( @test_vssra_vx_i8m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -761,8 +761,8 @@ declare @llvm.riscv.vssra.mask.nxv16i8.i64.i64( @test_vssra_vv_i8m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -775,8 +775,8 @@ declare @llvm.riscv.vssra.mask.nxv32i8.nxv32i8.i64( @test_vssra_vx_i8m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -789,8 +789,8 @@ declare @llvm.riscv.vssra.mask.nxv32i8.i64.i64( @test_vssra_vv_i8m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -803,8 +803,8 @@ declare @llvm.riscv.vssra.mask.nxv64i8.nxv64i8.i64( @test_vssra_vx_i8m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -817,8 +817,8 @@ declare @llvm.riscv.vssra.mask.nxv64i8.i64.i64( @test_vssra_vv_i16mf4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vssra.mask.nxv1i16.nxv1i16.i64( @test_vssra_vx_i16mf4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -845,8 +845,8 @@ declare @llvm.riscv.vssra.mask.nxv1i16.i64.i64( @test_vssra_vv_i16mf2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -859,8 +859,8 @@ declare @llvm.riscv.vssra.mask.nxv2i16.nxv2i16.i64( @test_vssra_vx_i16mf2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -873,8 +873,8 @@ declare @llvm.riscv.vssra.mask.nxv2i16.i64.i64( @test_vssra_vv_i16m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -887,8 +887,8 @@ declare @llvm.riscv.vssra.mask.nxv4i16.nxv4i16.i64( @test_vssra_vx_i16m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -901,8 +901,8 @@ declare @llvm.riscv.vssra.mask.nxv4i16.i64.i64( @test_vssra_vv_i16m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -915,8 +915,8 @@ declare @llvm.riscv.vssra.mask.nxv8i16.nxv8i16.i64( @test_vssra_vx_i16m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -929,8 +929,8 @@ declare @llvm.riscv.vssra.mask.nxv8i16.i64.i64( @test_vssra_vv_i16m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -943,8 +943,8 @@ declare @llvm.riscv.vssra.mask.nxv16i16.nxv16i16.i64( @test_vssra_vx_i16m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -957,8 +957,8 @@ declare @llvm.riscv.vssra.mask.nxv16i16.i64.i64( @test_vssra_vv_i16m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -971,8 +971,8 @@ declare @llvm.riscv.vssra.mask.nxv32i16.nxv32i16.i64( @test_vssra_vx_i16m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -985,8 +985,8 @@ declare @llvm.riscv.vssra.mask.nxv32i16.i64.i64( @test_vssra_vv_i32mf2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -999,8 +999,8 @@ declare @llvm.riscv.vssra.mask.nxv1i32.nxv1i32.i64( @test_vssra_vx_i32mf2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1013,8 +1013,8 @@ declare @llvm.riscv.vssra.mask.nxv1i32.i64.i64( @test_vssra_vv_i32m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1027,8 +1027,8 @@ declare @llvm.riscv.vssra.mask.nxv2i32.nxv2i32.i64( @test_vssra_vx_i32m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1041,8 +1041,8 @@ declare @llvm.riscv.vssra.mask.nxv2i32.i64.i64( @test_vssra_vv_i32m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1055,8 +1055,8 @@ declare @llvm.riscv.vssra.mask.nxv4i32.nxv4i32.i64( @test_vssra_vx_i32m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1069,8 +1069,8 @@ declare @llvm.riscv.vssra.mask.nxv4i32.i64.i64( @test_vssra_vv_i32m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1083,8 +1083,8 @@ declare @llvm.riscv.vssra.mask.nxv8i32.nxv8i32.i64( @test_vssra_vx_i32m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vssra.mask.nxv8i32.i64.i64( @test_vssra_vv_i32m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1111,8 +1111,8 @@ declare @llvm.riscv.vssra.mask.nxv16i32.nxv16i32.i64( @test_vssra_vx_i32m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1125,8 +1125,8 @@ declare @llvm.riscv.vssra.mask.nxv16i32.i64.i64( @test_vssra_vv_i64m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1139,8 +1139,8 @@ declare @llvm.riscv.vssra.mask.nxv1i64.nxv1i64.i64( @test_vssra_vx_i64m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1153,8 +1153,8 @@ declare @llvm.riscv.vssra.mask.nxv1i64.i64.i64( @test_vssra_vv_i64m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1167,8 +1167,8 @@ declare @llvm.riscv.vssra.mask.nxv2i64.nxv2i64.i64( @test_vssra_vx_i64m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1181,8 +1181,8 @@ declare @llvm.riscv.vssra.mask.nxv2i64.i64.i64( @test_vssra_vv_i64m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1195,8 +1195,8 @@ declare @llvm.riscv.vssra.mask.nxv4i64.nxv4i64.i64( @test_vssra_vx_i64m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1209,8 +1209,8 @@ declare @llvm.riscv.vssra.mask.nxv4i64.i64.i64( @test_vssra_vv_i64m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1223,8 +1223,8 @@ declare @llvm.riscv.vssra.mask.nxv8i64.nxv8i64.i64( @test_vssra_vx_i64m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll index c1a064984dcc..0c2cdff65776 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll @@ -5,8 +5,8 @@ define @test_vssrl_vv_u8mf8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -19,8 +19,8 @@ declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i32(, define @test_vssrl_vx_u8mf8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -33,8 +33,8 @@ declare @llvm.riscv.vssrl.nxv1i8.i32.i32(, @test_vssrl_vv_u8mf4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -47,8 +47,8 @@ declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i32(, define @test_vssrl_vx_u8mf4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vssrl.nxv2i8.i32.i32(, @test_vssrl_vv_u8mf2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -75,8 +75,8 @@ declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i32(, define @test_vssrl_vx_u8mf2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -89,8 +89,8 @@ declare @llvm.riscv.vssrl.nxv4i8.i32.i32(, @test_vssrl_vv_u8m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -103,8 +103,8 @@ declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i32(, define @test_vssrl_vx_u8m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -117,8 +117,8 @@ declare @llvm.riscv.vssrl.nxv8i8.i32.i32(, @test_vssrl_vv_u8m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -131,8 +131,8 @@ declare @llvm.riscv.vssrl.nxv16i8.nxv16i8.i32( @test_vssrl_vx_u8m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -145,8 +145,8 @@ declare @llvm.riscv.vssrl.nxv16i8.i32.i32(, define @test_vssrl_vv_u8m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -159,8 +159,8 @@ declare @llvm.riscv.vssrl.nxv32i8.nxv32i8.i32( @test_vssrl_vx_u8m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -173,8 +173,8 @@ declare @llvm.riscv.vssrl.nxv32i8.i32.i32(, define @test_vssrl_vv_u8m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -187,8 +187,8 @@ declare @llvm.riscv.vssrl.nxv64i8.nxv64i8.i32( @test_vssrl_vx_u8m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -201,8 +201,8 @@ declare @llvm.riscv.vssrl.nxv64i8.i32.i32(, define @test_vssrl_vv_u16mf4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -215,8 +215,8 @@ declare @llvm.riscv.vssrl.nxv1i16.nxv1i16.i32( @test_vssrl_vx_u16mf4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vssrl.nxv1i16.i32.i32(, define @test_vssrl_vv_u16mf2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -243,8 +243,8 @@ declare @llvm.riscv.vssrl.nxv2i16.nxv2i16.i32( @test_vssrl_vx_u16mf2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -257,8 +257,8 @@ declare @llvm.riscv.vssrl.nxv2i16.i32.i32(, define @test_vssrl_vv_u16m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -271,8 +271,8 @@ declare @llvm.riscv.vssrl.nxv4i16.nxv4i16.i32( @test_vssrl_vx_u16m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -285,8 +285,8 @@ declare @llvm.riscv.vssrl.nxv4i16.i32.i32(, define @test_vssrl_vv_u16m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -299,8 +299,8 @@ declare @llvm.riscv.vssrl.nxv8i16.nxv8i16.i32( @test_vssrl_vx_u16m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -313,8 +313,8 @@ declare @llvm.riscv.vssrl.nxv8i16.i32.i32(, define @test_vssrl_vv_u16m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -327,8 +327,8 @@ declare @llvm.riscv.vssrl.nxv16i16.nxv16i16.i32( @test_vssrl_vx_u16m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -341,8 +341,8 @@ declare @llvm.riscv.vssrl.nxv16i16.i32.i32( @test_vssrl_vv_u16m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -355,8 +355,8 @@ declare @llvm.riscv.vssrl.nxv32i16.nxv32i16.i32( @test_vssrl_vx_u16m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -369,8 +369,8 @@ declare @llvm.riscv.vssrl.nxv32i16.i32.i32( @test_vssrl_vv_u32mf2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -383,8 +383,8 @@ declare @llvm.riscv.vssrl.nxv1i32.nxv1i32.i32( @test_vssrl_vx_u32mf2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -397,8 +397,8 @@ declare @llvm.riscv.vssrl.nxv1i32.i32.i32(, define @test_vssrl_vv_u32m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -411,8 +411,8 @@ declare @llvm.riscv.vssrl.nxv2i32.nxv2i32.i32( @test_vssrl_vx_u32m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -425,8 +425,8 @@ declare @llvm.riscv.vssrl.nxv2i32.i32.i32(, define @test_vssrl_vv_u32m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -439,8 +439,8 @@ declare @llvm.riscv.vssrl.nxv4i32.nxv4i32.i32( @test_vssrl_vx_u32m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -453,8 +453,8 @@ declare @llvm.riscv.vssrl.nxv4i32.i32.i32(, define @test_vssrl_vv_u32m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -467,8 +467,8 @@ declare @llvm.riscv.vssrl.nxv8i32.nxv8i32.i32( @test_vssrl_vx_u32m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -481,8 +481,8 @@ declare @llvm.riscv.vssrl.nxv8i32.i32.i32(, define @test_vssrl_vv_u32m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -495,8 +495,8 @@ declare @llvm.riscv.vssrl.nxv16i32.nxv16i32.i32( @test_vssrl_vx_u32m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -509,8 +509,8 @@ declare @llvm.riscv.vssrl.nxv16i32.i32.i32( @test_vssrl_vv_u64m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -523,8 +523,8 @@ declare @llvm.riscv.vssrl.nxv1i64.nxv1i64.i32( @test_vssrl_vx_u64m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -537,8 +537,8 @@ declare @llvm.riscv.vssrl.nxv1i64.i32.i32(, define @test_vssrl_vv_u64m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -551,8 +551,8 @@ declare @llvm.riscv.vssrl.nxv2i64.nxv2i64.i32( @test_vssrl_vx_u64m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -565,8 +565,8 @@ declare @llvm.riscv.vssrl.nxv2i64.i32.i32(, define @test_vssrl_vv_u64m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -579,8 +579,8 @@ declare @llvm.riscv.vssrl.nxv4i64.nxv4i64.i32( @test_vssrl_vx_u64m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -593,8 +593,8 @@ declare @llvm.riscv.vssrl.nxv4i64.i32.i32(, define @test_vssrl_vv_u64m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -607,8 +607,8 @@ declare @llvm.riscv.vssrl.nxv8i64.nxv8i64.i32( @test_vssrl_vx_u64m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -621,8 +621,8 @@ declare @llvm.riscv.vssrl.nxv8i64.i32.i32(, define @test_vssrl_vv_u8mf8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -635,8 +635,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8.i32( @test_vssrl_vx_u8mf8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -649,8 +649,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.i32.i32( @test_vssrl_vv_u8mf4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i8.nxv2i8.i32( @test_vssrl_vx_u8mf4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -677,8 +677,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i8.i32.i32( @test_vssrl_vv_u8mf2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -691,8 +691,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i8.nxv4i8.i32( @test_vssrl_vx_u8mf2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -705,8 +705,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i8.i32.i32( @test_vssrl_vv_u8m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i8.nxv8i8.i32( @test_vssrl_vx_u8m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -733,8 +733,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i8.i32.i32( @test_vssrl_vv_u8m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -747,8 +747,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i8.nxv16i8.i32( @test_vssrl_vx_u8m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -761,8 +761,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i8.i32.i32( @test_vssrl_vv_u8m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -775,8 +775,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i8.nxv32i8.i32( @test_vssrl_vx_u8m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -789,8 +789,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i8.i32.i32( @test_vssrl_vv_u8m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -803,8 +803,8 @@ declare @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8.i32( @test_vssrl_vx_u8m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -817,8 +817,8 @@ declare @llvm.riscv.vssrl.mask.nxv64i8.i32.i32( @test_vssrl_vv_u16mf4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i16.nxv1i16.i32( @test_vssrl_vx_u16mf4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -845,8 +845,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i16.i32.i32( @test_vssrl_vv_u16mf2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -859,8 +859,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i16.nxv2i16.i32( @test_vssrl_vx_u16mf2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -873,8 +873,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i16.i32.i32( @test_vssrl_vv_u16m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -887,8 +887,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i16.nxv4i16.i32( @test_vssrl_vx_u16m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -901,8 +901,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i16.i32.i32( @test_vssrl_vv_u16m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -915,8 +915,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i16.nxv8i16.i32( @test_vssrl_vx_u16m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -929,8 +929,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i16.i32.i32( @test_vssrl_vv_u16m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -943,8 +943,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i16.nxv16i16.i32( @test_vssrl_vx_u16m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -957,8 +957,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i16.i32.i32( @test_vssrl_vv_u16m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -971,8 +971,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16.i32( @test_vssrl_vx_u16m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -985,8 +985,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i16.i32.i32( @test_vssrl_vv_u32mf2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -999,8 +999,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i32.nxv1i32.i32( @test_vssrl_vx_u32mf2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1013,8 +1013,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i32.i32.i32( @test_vssrl_vv_u32m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1027,8 +1027,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i32.nxv2i32.i32( @test_vssrl_vx_u32m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1041,8 +1041,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i32.i32.i32( @test_vssrl_vv_u32m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1055,8 +1055,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i32.nxv4i32.i32( @test_vssrl_vx_u32m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1069,8 +1069,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i32.i32.i32( @test_vssrl_vv_u32m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1083,8 +1083,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i32.nxv8i32.i32( @test_vssrl_vx_u32m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i32.i32.i32( @test_vssrl_vv_u32m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1111,8 +1111,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32.i32( @test_vssrl_vx_u32m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1125,8 +1125,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i32.i32.i32( @test_vssrl_vv_u64m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1139,8 +1139,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i64.nxv1i64.i32( @test_vssrl_vx_u64m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1153,8 +1153,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i64.i32.i32( @test_vssrl_vv_u64m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1167,8 +1167,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i64.nxv2i64.i32( @test_vssrl_vx_u64m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1181,8 +1181,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i64.i32.i32( @test_vssrl_vv_u64m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1195,8 +1195,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i64.nxv4i64.i32( @test_vssrl_vx_u64m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1209,8 +1209,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i64.i32.i32( @test_vssrl_vv_u64m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1223,8 +1223,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64.i32( @test_vssrl_vx_u64m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll index 0a465db64b7a..fe80854bb264 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll @@ -5,8 +5,8 @@ define @test_vssrl_vv_u8mf8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -19,8 +19,8 @@ declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, define @test_vssrl_vx_u8mf8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -33,8 +33,8 @@ declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, @test_vssrl_vv_u8mf4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -47,8 +47,8 @@ declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, define @test_vssrl_vx_u8mf4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, @test_vssrl_vv_u8mf2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -75,8 +75,8 @@ declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, define @test_vssrl_vx_u8mf2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -89,8 +89,8 @@ declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, @test_vssrl_vv_u8m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -103,8 +103,8 @@ declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, define @test_vssrl_vx_u8m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -117,8 +117,8 @@ declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, @test_vssrl_vv_u8m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -131,8 +131,8 @@ declare @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64( @test_vssrl_vx_u8m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -145,8 +145,8 @@ declare @llvm.riscv.vssrl.nxv16i8.i64.i64(, define @test_vssrl_vv_u8m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -159,8 +159,8 @@ declare @llvm.riscv.vssrl.nxv32i8.nxv32i8.i64( @test_vssrl_vx_u8m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -173,8 +173,8 @@ declare @llvm.riscv.vssrl.nxv32i8.i64.i64(, define @test_vssrl_vv_u8m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -187,8 +187,8 @@ declare @llvm.riscv.vssrl.nxv64i8.nxv64i8.i64( @test_vssrl_vx_u8m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -201,8 +201,8 @@ declare @llvm.riscv.vssrl.nxv64i8.i64.i64(, define @test_vssrl_vv_u16mf4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -215,8 +215,8 @@ declare @llvm.riscv.vssrl.nxv1i16.nxv1i16.i64( @test_vssrl_vx_u16mf4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vssrl.nxv1i16.i64.i64(, define @test_vssrl_vv_u16mf2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -243,8 +243,8 @@ declare @llvm.riscv.vssrl.nxv2i16.nxv2i16.i64( @test_vssrl_vx_u16mf2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -257,8 +257,8 @@ declare @llvm.riscv.vssrl.nxv2i16.i64.i64(, define @test_vssrl_vv_u16m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -271,8 +271,8 @@ declare @llvm.riscv.vssrl.nxv4i16.nxv4i16.i64( @test_vssrl_vx_u16m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -285,8 +285,8 @@ declare @llvm.riscv.vssrl.nxv4i16.i64.i64(, define @test_vssrl_vv_u16m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -299,8 +299,8 @@ declare @llvm.riscv.vssrl.nxv8i16.nxv8i16.i64( @test_vssrl_vx_u16m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -313,8 +313,8 @@ declare @llvm.riscv.vssrl.nxv8i16.i64.i64(, define @test_vssrl_vv_u16m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -327,8 +327,8 @@ declare @llvm.riscv.vssrl.nxv16i16.nxv16i16.i64( @test_vssrl_vx_u16m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -341,8 +341,8 @@ declare @llvm.riscv.vssrl.nxv16i16.i64.i64( @test_vssrl_vv_u16m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -355,8 +355,8 @@ declare @llvm.riscv.vssrl.nxv32i16.nxv32i16.i64( @test_vssrl_vx_u16m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -369,8 +369,8 @@ declare @llvm.riscv.vssrl.nxv32i16.i64.i64( @test_vssrl_vv_u32mf2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -383,8 +383,8 @@ declare @llvm.riscv.vssrl.nxv1i32.nxv1i32.i64( @test_vssrl_vx_u32mf2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -397,8 +397,8 @@ declare @llvm.riscv.vssrl.nxv1i32.i64.i64(, define @test_vssrl_vv_u32m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -411,8 +411,8 @@ declare @llvm.riscv.vssrl.nxv2i32.nxv2i32.i64( @test_vssrl_vx_u32m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -425,8 +425,8 @@ declare @llvm.riscv.vssrl.nxv2i32.i64.i64(, define @test_vssrl_vv_u32m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -439,8 +439,8 @@ declare @llvm.riscv.vssrl.nxv4i32.nxv4i32.i64( @test_vssrl_vx_u32m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -453,8 +453,8 @@ declare @llvm.riscv.vssrl.nxv4i32.i64.i64(, define @test_vssrl_vv_u32m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -467,8 +467,8 @@ declare @llvm.riscv.vssrl.nxv8i32.nxv8i32.i64( @test_vssrl_vx_u32m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -481,8 +481,8 @@ declare @llvm.riscv.vssrl.nxv8i32.i64.i64(, define @test_vssrl_vv_u32m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -495,8 +495,8 @@ declare @llvm.riscv.vssrl.nxv16i32.nxv16i32.i64( @test_vssrl_vx_u32m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -509,8 +509,8 @@ declare @llvm.riscv.vssrl.nxv16i32.i64.i64( @test_vssrl_vv_u64m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -523,8 +523,8 @@ declare @llvm.riscv.vssrl.nxv1i64.nxv1i64.i64( @test_vssrl_vx_u64m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -537,8 +537,8 @@ declare @llvm.riscv.vssrl.nxv1i64.i64.i64(, define @test_vssrl_vv_u64m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -551,8 +551,8 @@ declare @llvm.riscv.vssrl.nxv2i64.nxv2i64.i64( @test_vssrl_vx_u64m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -565,8 +565,8 @@ declare @llvm.riscv.vssrl.nxv2i64.i64.i64(, define @test_vssrl_vv_u64m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -579,8 +579,8 @@ declare @llvm.riscv.vssrl.nxv4i64.nxv4i64.i64( @test_vssrl_vx_u64m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -593,8 +593,8 @@ declare @llvm.riscv.vssrl.nxv4i64.i64.i64(, define @test_vssrl_vv_u64m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -607,8 +607,8 @@ declare @llvm.riscv.vssrl.nxv8i64.nxv8i64.i64( @test_vssrl_vx_u64m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -621,8 +621,8 @@ declare @llvm.riscv.vssrl.nxv8i64.i64.i64(, define @test_vssrl_vv_u8mf8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -635,8 +635,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8.i64( @test_vssrl_vx_u8mf8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -649,8 +649,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.i64.i64( @test_vssrl_vv_u8mf4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i8.nxv2i8.i64( @test_vssrl_vx_u8mf4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -677,8 +677,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i8.i64.i64( @test_vssrl_vv_u8mf2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -691,8 +691,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i8.nxv4i8.i64( @test_vssrl_vx_u8mf2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -705,8 +705,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i8.i64.i64( @test_vssrl_vv_u8m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i8.nxv8i8.i64( @test_vssrl_vx_u8m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -733,8 +733,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i8.i64.i64( @test_vssrl_vv_u8m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -747,8 +747,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i8.nxv16i8.i64( @test_vssrl_vx_u8m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -761,8 +761,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i8.i64.i64( @test_vssrl_vv_u8m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -775,8 +775,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i8.nxv32i8.i64( @test_vssrl_vx_u8m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -789,8 +789,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i8.i64.i64( @test_vssrl_vv_u8m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -803,8 +803,8 @@ declare @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8.i64( @test_vssrl_vx_u8m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -817,8 +817,8 @@ declare @llvm.riscv.vssrl.mask.nxv64i8.i64.i64( @test_vssrl_vv_u16mf4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i16.nxv1i16.i64( @test_vssrl_vx_u16mf4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -845,8 +845,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i16.i64.i64( @test_vssrl_vv_u16mf2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -859,8 +859,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i16.nxv2i16.i64( @test_vssrl_vx_u16mf2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -873,8 +873,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i16.i64.i64( @test_vssrl_vv_u16m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -887,8 +887,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i16.nxv4i16.i64( @test_vssrl_vx_u16m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -901,8 +901,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i16.i64.i64( @test_vssrl_vv_u16m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -915,8 +915,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i16.nxv8i16.i64( @test_vssrl_vx_u16m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -929,8 +929,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i16.i64.i64( @test_vssrl_vv_u16m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -943,8 +943,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i16.nxv16i16.i64( @test_vssrl_vx_u16m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -957,8 +957,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i16.i64.i64( @test_vssrl_vv_u16m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -971,8 +971,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16.i64( @test_vssrl_vx_u16m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -985,8 +985,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i16.i64.i64( @test_vssrl_vv_u32mf2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -999,8 +999,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i32.nxv1i32.i64( @test_vssrl_vx_u32mf2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1013,8 +1013,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i32.i64.i64( @test_vssrl_vv_u32m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1027,8 +1027,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i32.nxv2i32.i64( @test_vssrl_vx_u32m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1041,8 +1041,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i32.i64.i64( @test_vssrl_vv_u32m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1055,8 +1055,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i32.nxv4i32.i64( @test_vssrl_vx_u32m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1069,8 +1069,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i32.i64.i64( @test_vssrl_vv_u32m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1083,8 +1083,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i32.nxv8i32.i64( @test_vssrl_vx_u32m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i32.i64.i64( @test_vssrl_vv_u32m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1111,8 +1111,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32.i64( @test_vssrl_vx_u32m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1125,8 +1125,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i32.i64.i64( @test_vssrl_vv_u64m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1139,8 +1139,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i64.nxv1i64.i64( @test_vssrl_vx_u64m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1153,8 +1153,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i64.i64.i64( @test_vssrl_vv_u64m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1167,8 +1167,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i64.nxv2i64.i64( @test_vssrl_vx_u64m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1181,8 +1181,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i64.i64.i64( @test_vssrl_vv_u64m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1195,8 +1195,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i64.nxv4i64.i64( @test_vssrl_vx_u64m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1209,8 +1209,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i64.i64.i64( @test_vssrl_vv_u64m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1223,8 +1223,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64.i64( @test_vssrl_vx_u64m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll index 10175218a440..c5f34eee3118 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll @@ -20,8 +20,8 @@ declare @llvm.riscv.vasub.nxv1i8.nxv1i8( define @test1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: test1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: vaadd.vv v8, v8, v10 ; CHECK-NEXT: ret @@ -44,8 +44,8 @@ entry: define @test2( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: test2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vaadd.vv v8, v8, v10 @@ -80,12 +80,12 @@ define @test3( %0, %1, @test3( %0, %1, @test4( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: test4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -174,8 +174,8 @@ define @test5( %0, %1, @test7( %0, %1, @test12(i1 %c1, %0, ; CHECK-LABEL: test12: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi a0, a0, 1 -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v9, v8, v9 ; CHECK-NEXT: beqz a0, .LBB11_2 ; CHECK-NEXT: # %bb.1: # %block1 @@ -513,8 +513,8 @@ define @test13(i1 %c1, i1 %c2, i1 %c3, %0, < ; CHECK-LABEL: test13: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi a0, a0, 1 -; CHECK-NEXT: vsetvli zero, a3, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a3, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v10, v8, v9 ; CHECK-NEXT: beqz a0, .LBB12_2 ; CHECK-NEXT: # %bb.1: # %block1 diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm.mir b/llvm/test/CodeGen/RISCV/rvv/vxrm.mir index eac3cfca209e..2bac1eeb9060 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxrm.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vxrm.mir @@ -11,14 +11,14 @@ body: | ; MIR-LABEL: name: verify_vxrm ; MIR: liveins: $v8, $v9, $x10 ; MIR-NEXT: {{ $}} - ; MIR-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype ; MIR-NEXT: WriteVXRMImm 0, implicit-def $vxrm - ; MIR-NEXT: renamable $v8 = PseudoVAADD_VV_MF8 undef $v8, killed renamable $v8, killed renamable $v9, 0, $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit $vxrm + ; MIR-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype + ; MIR-NEXT: renamable $v8 = PseudoVAADD_VV_MF8 undef $v8, killed renamable $v8, killed renamable $v9, 0, $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vxrm, implicit $vl, implicit $vtype ; MIR-NEXT: PseudoRET implicit $v8 ; ASM-LABEL: verify_vxrm: ; ASM: # %bb.0: - ; ASM-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; ASM-NEXT: csrwi vxrm, 0 + ; ASM-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; ASM-NEXT: vaadd.vv v8, v8, v9 ; ASM-NEXT: ret %0:vr = COPY $v8 -- GitLab From 5bde2aa1080ba90021f8f5e0c48744ddfc0d6f15 Mon Sep 17 00:00:00 2001 From: Pavel Labath Date: Fri, 10 May 2024 08:34:42 +0200 Subject: [PATCH 232/328] [lldb] Improve type name parsing (#91586) Parsing of '::' scopes in TypeQuery was very naive and failed for names with '::''s in template arguments. Interestingly, one of the functions it was calling (Type::GetTypeScopeAndBasename) was already doing the same thing, and getting it (mostly (*)) right. This refactors the function so that it can return the scope results, fixing the parsing of names like std::vector>::iterator. Two callers of GetTypeScopeAndBasename are deleted as the functions are not used (I presume they stopped being used once we started pruning type search results more eagerly). (*) This implementation is still not correct when one takes c++ operators into account -- e.g., something like `X<&A::operator<>::T` is a legitimate type name. We do have an implementation that is able to handle names like these (CPlusPlusLanguage::MethodName), but using it is not trivial, because it is hidden in a language plugin and specific to method name parsing. --------- Co-authored-by: Michael Buch --- lldb/include/lldb/Symbol/Type.h | 35 ++++- lldb/include/lldb/Symbol/TypeList.h | 9 -- lldb/include/lldb/Symbol/TypeMap.h | 4 - lldb/source/Symbol/Type.cpp | 130 ++++++++---------- lldb/source/Symbol/TypeList.cpp | 109 --------------- lldb/source/Symbol/TypeMap.cpp | 73 ---------- .../python_api/sbmodule/FindTypes/Makefile | 3 + .../FindTypes/TestSBModuleFindTypes.py | 40 ++++++ .../python_api/sbmodule/FindTypes/main.cpp | 17 +++ lldb/unittests/Symbol/TestType.cpp | 62 ++++----- 10 files changed, 180 insertions(+), 302 deletions(-) create mode 100644 lldb/test/API/python_api/sbmodule/FindTypes/Makefile create mode 100644 lldb/test/API/python_api/sbmodule/FindTypes/TestSBModuleFindTypes.py create mode 100644 lldb/test/API/python_api/sbmodule/FindTypes/main.cpp diff --git a/lldb/include/lldb/Symbol/Type.h b/lldb/include/lldb/Symbol/Type.h index 1c4f7b5601b0..7aa0852676e4 100644 --- a/lldb/include/lldb/Symbol/Type.h +++ b/lldb/include/lldb/Symbol/Type.h @@ -21,6 +21,8 @@ #include "llvm/ADT/APSInt.h" #include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/STLForwardCompat.h" +#include "llvm/Support/raw_ostream.h" #include #include @@ -492,12 +494,37 @@ public: static int Compare(const Type &a, const Type &b); + // Represents a parsed type name coming out of GetTypeScopeAndBasename. The + // structure holds StringRefs pointing to portions of the original name, and + // so must not be used after the name is destroyed. + struct ParsedName { + lldb::TypeClass type_class = lldb::eTypeClassAny; + + // Scopes of the type, starting with the outermost. Absolute type references + // have a "::" as the first scope. + llvm::SmallVector scope; + + llvm::StringRef basename; + + friend bool operator==(const ParsedName &lhs, const ParsedName &rhs) { + return lhs.type_class == rhs.type_class && lhs.scope == rhs.scope && + lhs.basename == rhs.basename; + } + + friend llvm::raw_ostream &operator<<(llvm::raw_ostream &os, + const ParsedName &name) { + return os << llvm::formatv( + "Type::ParsedName({0:x}, [{1}], {2})", + llvm::to_underlying(name.type_class), + llvm::make_range(name.scope.begin(), name.scope.end()), + name.basename); + } + }; // From a fully qualified typename, split the type into the type basename and // the remaining type scope (namespaces/classes). - static bool GetTypeScopeAndBasename(llvm::StringRef name, - llvm::StringRef &scope, - llvm::StringRef &basename, - lldb::TypeClass &type_class); + static std::optional + GetTypeScopeAndBasename(llvm::StringRef name); + void SetEncodingType(Type *encoding_type) { m_encoding_type = encoding_type; } uint32_t GetEncodingMask(); diff --git a/lldb/include/lldb/Symbol/TypeList.h b/lldb/include/lldb/Symbol/TypeList.h index 403469c989f5..d58772ad5b62 100644 --- a/lldb/include/lldb/Symbol/TypeList.h +++ b/lldb/include/lldb/Symbol/TypeList.h @@ -49,15 +49,6 @@ public: void ForEach(std::function const &callback); - void RemoveMismatchedTypes(llvm::StringRef qualified_typename, - bool exact_match); - - void RemoveMismatchedTypes(llvm::StringRef type_scope, - llvm::StringRef type_basename, - lldb::TypeClass type_class, bool exact_match); - - void RemoveMismatchedTypes(lldb::TypeClass type_class); - private: typedef collection::iterator iterator; typedef collection::const_iterator const_iterator; diff --git a/lldb/include/lldb/Symbol/TypeMap.h b/lldb/include/lldb/Symbol/TypeMap.h index 433711875e55..89011efab5c3 100644 --- a/lldb/include/lldb/Symbol/TypeMap.h +++ b/lldb/include/lldb/Symbol/TypeMap.h @@ -55,10 +55,6 @@ public: bool Remove(const lldb::TypeSP &type_sp); - void RemoveMismatchedTypes(llvm::StringRef type_scope, - llvm::StringRef type_basename, - lldb::TypeClass type_class, bool exact_match); - private: typedef collection::iterator iterator; typedef collection::const_iterator const_iterator; diff --git a/lldb/source/Symbol/Type.cpp b/lldb/source/Symbol/Type.cpp index b85c38097ebe..6bf69c2ded28 100644 --- a/lldb/source/Symbol/Type.cpp +++ b/lldb/source/Symbol/Type.cpp @@ -29,6 +29,7 @@ #include "lldb/Target/ExecutionContext.h" #include "lldb/Target/Process.h" #include "lldb/Target/Target.h" +#include "lldb/lldb-enumerations.h" #include "llvm/ADT/StringRef.h" @@ -85,27 +86,23 @@ static CompilerContextKind ConvertTypeClass(lldb::TypeClass type_class) { TypeQuery::TypeQuery(llvm::StringRef name, TypeQueryOptions options) : m_options(options) { - llvm::StringRef scope, basename; - lldb::TypeClass type_class = lldb::eTypeClassAny; - if (Type::GetTypeScopeAndBasename(name, scope, basename, type_class)) { - if (scope.consume_front("::")) - m_options |= e_exact_match; + if (std::optional parsed_name = + Type::GetTypeScopeAndBasename(name)) { + llvm::ArrayRef scope = parsed_name->scope; if (!scope.empty()) { - std::pair scope_pair = - scope.split("::"); - while (!scope_pair.second.empty()) { - m_context.push_back({CompilerContextKind::AnyDeclContext, - ConstString(scope_pair.first.str())}); - scope_pair = scope_pair.second.split("::"); + if (scope[0] == "::") { + m_options |= e_exact_match; + scope = scope.drop_front(); + } + for (llvm::StringRef s : scope) { + m_context.push_back( + {CompilerContextKind::AnyDeclContext, ConstString(s)}); } - m_context.push_back({CompilerContextKind::AnyDeclContext, - ConstString(scope_pair.first.str())}); } - m_context.push_back( - {ConvertTypeClass(type_class), ConstString(basename.str())}); + m_context.push_back({ConvertTypeClass(parsed_name->type_class), + ConstString(parsed_name->basename)}); } else { - m_context.push_back( - {CompilerContextKind::AnyType, ConstString(name.str())}); + m_context.push_back({CompilerContextKind::AnyType, ConstString(name)}); } } @@ -773,65 +770,56 @@ ConstString Type::GetQualifiedName() { return GetForwardCompilerType().GetTypeName(); } -bool Type::GetTypeScopeAndBasename(llvm::StringRef name, - llvm::StringRef &scope, - llvm::StringRef &basename, - TypeClass &type_class) { - type_class = eTypeClassAny; +std::optional +Type::GetTypeScopeAndBasename(llvm::StringRef name) { + ParsedName result; if (name.empty()) - return false; - - // Clear the scope in case we have just a type class and a basename. - scope = llvm::StringRef(); - basename = name; - if (basename.consume_front("struct ")) - type_class = eTypeClassStruct; - else if (basename.consume_front("class ")) - type_class = eTypeClassClass; - else if (basename.consume_front("union ")) - type_class = eTypeClassUnion; - else if (basename.consume_front("enum ")) - type_class = eTypeClassEnumeration; - else if (basename.consume_front("typedef ")) - type_class = eTypeClassTypedef; - - size_t namespace_separator = basename.find("::"); - if (namespace_separator == llvm::StringRef::npos) { - // If "name" started a type class we need to return true with no scope. - return type_class != eTypeClassAny; - } - - size_t template_begin = basename.find('<'); - while (namespace_separator != llvm::StringRef::npos) { - if (template_begin != llvm::StringRef::npos && - namespace_separator > template_begin) { - size_t template_depth = 1; - llvm::StringRef template_arg = - basename.drop_front(template_begin + 1); - while (template_depth > 0 && !template_arg.empty()) { - if (template_arg.front() == '<') - template_depth++; - else if (template_arg.front() == '>') - template_depth--; - template_arg = template_arg.drop_front(1); + return std::nullopt; + + if (name.consume_front("struct ")) + result.type_class = eTypeClassStruct; + else if (name.consume_front("class ")) + result.type_class = eTypeClassClass; + else if (name.consume_front("union ")) + result.type_class = eTypeClassUnion; + else if (name.consume_front("enum ")) + result.type_class = eTypeClassEnumeration; + else if (name.consume_front("typedef ")) + result.type_class = eTypeClassTypedef; + + if (name.consume_front("::")) + result.scope.push_back("::"); + + bool prev_is_colon = false; + size_t template_depth = 0; + size_t name_begin = 0; + for (const auto &pos : llvm::enumerate(name)) { + switch (pos.value()) { + case ':': + if (prev_is_colon && template_depth == 0) { + result.scope.push_back(name.slice(name_begin, pos.index() - 1)); + name_begin = pos.index() + 1; } - if (template_depth != 0) - return false; // We have an invalid type name. Bail out. - if (template_arg.empty()) - break; // The template ends at the end of the full name. - basename = template_arg; - } else { - basename = basename.drop_front(namespace_separator + 2); + break; + case '<': + ++template_depth; + break; + case '>': + if (template_depth == 0) + return std::nullopt; // Invalid name. + --template_depth; + break; } - template_begin = basename.find('<'); - namespace_separator = basename.find("::"); - } - if (basename.size() < name.size()) { - scope = name.take_front(name.size() - basename.size()); - return true; + prev_is_colon = pos.value() == ':'; } - return false; + + if (name_begin < name.size() && template_depth == 0) + result.basename = name.substr(name_begin); + else + return std::nullopt; + + return result; } ModuleSP Type::GetModule() { diff --git a/lldb/source/Symbol/TypeList.cpp b/lldb/source/Symbol/TypeList.cpp index 2e101e0a8f57..574887189315 100644 --- a/lldb/source/Symbol/TypeList.cpp +++ b/lldb/source/Symbol/TypeList.cpp @@ -96,112 +96,3 @@ void TypeList::Dump(Stream *s, bool show_context) { if (Type *t = pos->get()) t->Dump(s, show_context); } - -void TypeList::RemoveMismatchedTypes(llvm::StringRef qualified_typename, - bool exact_match) { - llvm::StringRef type_scope; - llvm::StringRef type_basename; - TypeClass type_class = eTypeClassAny; - if (!Type::GetTypeScopeAndBasename(qualified_typename, type_scope, - type_basename, type_class)) { - type_basename = qualified_typename; - type_scope = ""; - } - return RemoveMismatchedTypes(type_scope, type_basename, type_class, - exact_match); -} - -void TypeList::RemoveMismatchedTypes(llvm::StringRef type_scope, - llvm::StringRef type_basename, - TypeClass type_class, bool exact_match) { - // Our "collection" type currently is a std::map which doesn't have any good - // way to iterate and remove items from the map so we currently just make a - // new list and add all of the matching types to it, and then swap it into - // m_types at the end - collection matching_types; - - iterator pos, end = m_types.end(); - - for (pos = m_types.begin(); pos != end; ++pos) { - Type *the_type = pos->get(); - bool keep_match = false; - TypeClass match_type_class = eTypeClassAny; - - if (type_class != eTypeClassAny) { - match_type_class = the_type->GetForwardCompilerType().GetTypeClass(); - if ((match_type_class & type_class) == 0) - continue; - } - - ConstString match_type_name_const_str(the_type->GetQualifiedName()); - if (match_type_name_const_str) { - const char *match_type_name = match_type_name_const_str.GetCString(); - llvm::StringRef match_type_scope; - llvm::StringRef match_type_basename; - if (Type::GetTypeScopeAndBasename(match_type_name, match_type_scope, - match_type_basename, - match_type_class)) { - if (match_type_basename == type_basename) { - const size_t type_scope_size = type_scope.size(); - const size_t match_type_scope_size = match_type_scope.size(); - if (exact_match || (type_scope_size == match_type_scope_size)) { - keep_match = match_type_scope == type_scope; - } else { - if (match_type_scope_size > type_scope_size) { - const size_t type_scope_pos = match_type_scope.rfind(type_scope); - if (type_scope_pos == match_type_scope_size - type_scope_size) { - if (type_scope_pos >= 2) { - // Our match scope ends with the type scope we were looking - // for, but we need to make sure what comes before the - // matching type scope is a namespace boundary in case we are - // trying to match: type_basename = "d" type_scope = "b::c::" - // We want to match: - // match_type_scope "a::b::c::" - // But not: - // match_type_scope "a::bb::c::" - // So below we make sure what comes before "b::c::" in - // match_type_scope is "::", or the namespace boundary - if (match_type_scope[type_scope_pos - 1] == ':' && - match_type_scope[type_scope_pos - 2] == ':') { - keep_match = true; - } - } - } - } - } - } - } else { - // The type we are currently looking at doesn't exists in a namespace - // or class, so it only matches if there is no type scope... - keep_match = type_scope.empty() && type_basename == match_type_name; - } - } - - if (keep_match) { - matching_types.push_back(*pos); - } - } - m_types.swap(matching_types); -} - -void TypeList::RemoveMismatchedTypes(TypeClass type_class) { - if (type_class == eTypeClassAny) - return; - - // Our "collection" type currently is a std::map which doesn't have any good - // way to iterate and remove items from the map so we currently just make a - // new list and add all of the matching types to it, and then swap it into - // m_types at the end - collection matching_types; - - iterator pos, end = m_types.end(); - - for (pos = m_types.begin(); pos != end; ++pos) { - Type *the_type = pos->get(); - TypeClass match_type_class = - the_type->GetForwardCompilerType().GetTypeClass(); - if (match_type_class & type_class) - matching_types.push_back(*pos); - } - m_types.swap(matching_types); -} diff --git a/lldb/source/Symbol/TypeMap.cpp b/lldb/source/Symbol/TypeMap.cpp index 8933de53749c..9d7c05f318a1 100644 --- a/lldb/source/Symbol/TypeMap.cpp +++ b/lldb/source/Symbol/TypeMap.cpp @@ -132,76 +132,3 @@ void TypeMap::Dump(Stream *s, bool show_context, for (const auto &pair : m_types) pair.second->Dump(s, show_context, level); } - -void TypeMap::RemoveMismatchedTypes(llvm::StringRef type_scope, - llvm::StringRef type_basename, - TypeClass type_class, bool exact_match) { - // Our "collection" type currently is a std::map which doesn't have any good - // way to iterate and remove items from the map so we currently just make a - // new list and add all of the matching types to it, and then swap it into - // m_types at the end - collection matching_types; - - iterator pos, end = m_types.end(); - - for (pos = m_types.begin(); pos != end; ++pos) { - Type *the_type = pos->second.get(); - bool keep_match = false; - TypeClass match_type_class = eTypeClassAny; - - if (type_class != eTypeClassAny) { - match_type_class = the_type->GetForwardCompilerType().GetTypeClass(); - if ((match_type_class & type_class) == 0) - continue; - } - - ConstString match_type_name_const_str(the_type->GetQualifiedName()); - if (match_type_name_const_str) { - const char *match_type_name = match_type_name_const_str.GetCString(); - llvm::StringRef match_type_scope; - llvm::StringRef match_type_basename; - if (Type::GetTypeScopeAndBasename(match_type_name, match_type_scope, - match_type_basename, - match_type_class)) { - if (match_type_basename == type_basename) { - const size_t type_scope_size = type_scope.size(); - const size_t match_type_scope_size = match_type_scope.size(); - if (exact_match || (type_scope_size == match_type_scope_size)) { - keep_match = match_type_scope == type_scope; - } else { - if (match_type_scope_size > type_scope_size) { - const size_t type_scope_pos = match_type_scope.rfind(type_scope); - if (type_scope_pos == match_type_scope_size - type_scope_size) { - if (type_scope_pos >= 2) { - // Our match scope ends with the type scope we were looking - // for, but we need to make sure what comes before the - // matching type scope is a namespace boundary in case we are - // trying to match: type_basename = "d" type_scope = "b::c::" - // We want to match: - // match_type_scope "a::b::c::" - // But not: - // match_type_scope "a::bb::c::" - // So below we make sure what comes before "b::c::" in - // match_type_scope is "::", or the namespace boundary - if (match_type_scope[type_scope_pos - 1] == ':' && - match_type_scope[type_scope_pos - 2] == ':') { - keep_match = true; - } - } - } - } - } - } - } else { - // The type we are currently looking at doesn't exists in a namespace - // or class, so it only matches if there is no type scope... - keep_match = type_scope.empty() && type_basename == match_type_name; - } - } - - if (keep_match) { - matching_types.insert(*pos); - } - } - m_types.swap(matching_types); -} diff --git a/lldb/test/API/python_api/sbmodule/FindTypes/Makefile b/lldb/test/API/python_api/sbmodule/FindTypes/Makefile new file mode 100644 index 000000000000..99998b20bcb0 --- /dev/null +++ b/lldb/test/API/python_api/sbmodule/FindTypes/Makefile @@ -0,0 +1,3 @@ +CXX_SOURCES := main.cpp + +include Makefile.rules diff --git a/lldb/test/API/python_api/sbmodule/FindTypes/TestSBModuleFindTypes.py b/lldb/test/API/python_api/sbmodule/FindTypes/TestSBModuleFindTypes.py new file mode 100644 index 000000000000..5c3d2b4187dd --- /dev/null +++ b/lldb/test/API/python_api/sbmodule/FindTypes/TestSBModuleFindTypes.py @@ -0,0 +1,40 @@ +"""Test the SBModule::FindTypes.""" + +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + + +class TestSBModuleFindTypes(TestBase): + def test_lookup_in_template_scopes(self): + self.build() + spec = lldb.SBModuleSpec() + spec.SetFileSpec(lldb.SBFileSpec(self.getBuildArtifact())) + module = lldb.SBModule(spec) + + self.assertEqual( + set([t.GetName() for t in module.FindTypes("LookMeUp")]), + set( + [ + "ns1::Foo::LookMeUp", + "ns2::Bar::LookMeUp", + "ns1::Foo >::LookMeUp", + ] + ), + ) + + self.assertEqual( + set([t.GetName() for t in module.FindTypes("ns1::Foo::LookMeUp")]), + set(["ns1::Foo::LookMeUp"]), + ) + + self.assertEqual( + set( + [ + t.GetName() + for t in module.FindTypes("ns1::Foo >::LookMeUp") + ] + ), + set(["ns1::Foo >::LookMeUp"]), + ) diff --git a/lldb/test/API/python_api/sbmodule/FindTypes/main.cpp b/lldb/test/API/python_api/sbmodule/FindTypes/main.cpp new file mode 100644 index 000000000000..cb2646ce312a --- /dev/null +++ b/lldb/test/API/python_api/sbmodule/FindTypes/main.cpp @@ -0,0 +1,17 @@ +namespace ns1 { +template struct Foo { + struct LookMeUp {}; +}; +} // namespace ns1 + +namespace ns2 { +template struct Bar { + struct LookMeUp {}; +}; +} // namespace ns2 + +ns1::Foo::LookMeUp l1; +ns2::Bar::LookMeUp l2; +ns1::Foo>::LookMeUp l3; + +int main() {} diff --git a/lldb/unittests/Symbol/TestType.cpp b/lldb/unittests/Symbol/TestType.cpp index 73f5811434fd..da849d804e4d 100644 --- a/lldb/unittests/Symbol/TestType.cpp +++ b/lldb/unittests/Symbol/TestType.cpp @@ -10,43 +10,41 @@ #include "gtest/gtest.h" #include "lldb/Symbol/Type.h" +#include "lldb/lldb-enumerations.h" using namespace lldb; using namespace lldb_private; -namespace { -void TestGetTypeScopeAndBasenameHelper(const char *full_type, - bool expected_is_scoped, - const char *expected_scope, - const char *expected_name) { - llvm::StringRef scope, name; - lldb::TypeClass type_class; - bool is_scoped = - Type::GetTypeScopeAndBasename(full_type, scope, name, type_class); - EXPECT_EQ(is_scoped, expected_is_scoped); - if (expected_is_scoped) { - EXPECT_EQ(scope, expected_scope); - EXPECT_EQ(name, expected_name); - } -} -} - TEST(Type, GetTypeScopeAndBasename) { - TestGetTypeScopeAndBasenameHelper("int", false, "", ""); - TestGetTypeScopeAndBasenameHelper("std::string", true, "std::", "string"); - TestGetTypeScopeAndBasenameHelper("std::set", true, "std::", "set"); - TestGetTypeScopeAndBasenameHelper("std::set>", true, - "std::", "set>"); - TestGetTypeScopeAndBasenameHelper("std::string::iterator", true, - "std::string::", "iterator"); - TestGetTypeScopeAndBasenameHelper("std::set::iterator", true, - "std::set::", "iterator"); - TestGetTypeScopeAndBasenameHelper( - "std::set>::iterator", true, - "std::set>::", "iterator"); - TestGetTypeScopeAndBasenameHelper( - "std::set>::iterator", true, - "std::set>::", "iterator"); + EXPECT_EQ(Type::GetTypeScopeAndBasename("int"), + (Type::ParsedName{eTypeClassAny, {}, "int"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename("std::string"), + (Type::ParsedName{eTypeClassAny, {"std"}, "string"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename("::std::string"), + (Type::ParsedName{eTypeClassAny, {"::", "std"}, "string"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename("struct std::string"), + (Type::ParsedName{eTypeClassStruct, {"std"}, "string"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename("std::set"), + (Type::ParsedName{eTypeClassAny, {"std"}, "set"})); + EXPECT_EQ( + Type::GetTypeScopeAndBasename("std::set>"), + (Type::ParsedName{eTypeClassAny, {"std"}, "set>"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename("std::string::iterator"), + (Type::ParsedName{eTypeClassAny, {"std", "string"}, "iterator"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename("std::set::iterator"), + (Type::ParsedName{eTypeClassAny, {"std", "set"}, "iterator"})); + EXPECT_EQ( + Type::GetTypeScopeAndBasename("std::set>::iterator"), + (Type::ParsedName{ + eTypeClassAny, {"std", "set>"}, "iterator"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename( + "std::set>::iterator"), + (Type::ParsedName{eTypeClassAny, + {"std", "set>"}, + "iterator"})); + + EXPECT_EQ(Type::GetTypeScopeAndBasename("std::"), std::nullopt); + EXPECT_EQ(Type::GetTypeScopeAndBasename("foo<::bar"), std::nullopt); } TEST(Type, CompilerContextPattern) { -- GitLab From 2dbe89d15046bedcc36a5de1242e20aa91a5e598 Mon Sep 17 00:00:00 2001 From: cor3ntin Date: Fri, 10 May 2024 08:50:44 +0200 Subject: [PATCH 233/328] [Clang] Implement __reference_converts_from_temporary (#91199) This completes the required language support for P2255R2. --- clang/docs/LanguageExtensions.rst | 5 +- clang/docs/ReleaseNotes.rst | 3 + clang/include/clang/Basic/TokenKinds.def | 1 + clang/lib/Lex/PPMacroExpansion.cpp | 2 - clang/lib/Parse/ParseDeclCXX.cpp | 5 +- clang/lib/Parse/ParseExpr.cpp | 1 - clang/lib/Sema/SemaExprCXX.cpp | 157 +++++++++++++---------- clang/test/SemaCXX/type-traits.cpp | 80 ++++++++++++ clang/www/cxx_status.html | 10 +- 9 files changed, 182 insertions(+), 82 deletions(-) diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 3627a780886a..a09c409f8f91 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -1662,8 +1662,11 @@ The following type trait primitives are supported by Clang. Those traits marked ``T`` from ``U`` is ill-formed. Deprecated, use ``__reference_constructs_from_temporary``. * ``__reference_constructs_from_temporary(T, U)`` (C++) - Returns true if a reference ``T`` can be constructed from a temporary of type + Returns true if a reference ``T`` can be direct-initialized from a temporary of type a non-cv-qualified ``U``. +* ``__reference_converts_from_temporary(T, U)`` (C++) + Returns true if a reference ``T`` can be copy-initialized from a temporary of type + a non-cv-qualified ``U``. * ``__underlying_type`` (C++, GNU, Microsoft) In addition, the following expression traits are supported: diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 4547636318a7..eef627ff2e31 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -182,6 +182,9 @@ C++23 Feature Support - Implemented `P2448R2: Relaxing some constexpr restrictions `_. +- Added a ``__reference_converts_from_temporary`` builtin, completing the necessary compiler support for + `P2255R2: Type trait to determine if a reference binds to a temporary `_. + C++2c Feature Support ^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/TokenKinds.def b/clang/include/clang/Basic/TokenKinds.def index a27fbed358a6..56c4b17f769d 100644 --- a/clang/include/clang/Basic/TokenKinds.def +++ b/clang/include/clang/Basic/TokenKinds.def @@ -537,6 +537,7 @@ TYPE_TRAIT_1(__is_referenceable, IsReferenceable, KEYCXX) TYPE_TRAIT_1(__can_pass_in_regs, CanPassInRegs, KEYCXX) TYPE_TRAIT_2(__reference_binds_to_temporary, ReferenceBindsToTemporary, KEYCXX) TYPE_TRAIT_2(__reference_constructs_from_temporary, ReferenceConstructsFromTemporary, KEYCXX) +TYPE_TRAIT_2(__reference_converts_from_temporary, ReferenceConvertsFromTemporary, KEYCXX) // Embarcadero Expression Traits EXPRESSION_TRAIT(__is_lvalue_expr, IsLValueExpr, KEYCXX) diff --git a/clang/lib/Lex/PPMacroExpansion.cpp b/clang/lib/Lex/PPMacroExpansion.cpp index a5f22f01682d..a478e0badb0c 100644 --- a/clang/lib/Lex/PPMacroExpansion.cpp +++ b/clang/lib/Lex/PPMacroExpansion.cpp @@ -1714,8 +1714,6 @@ void Preprocessor::ExpandBuiltinMacro(Token &Tok) { return llvm::StringSwitch(II->getName()) .Case("__array_rank", true) .Case("__array_extent", true) - .Case("__reference_binds_to_temporary", true) - .Case("__reference_constructs_from_temporary", true) #define TRANSFORM_TYPE_TRAIT_DEF(_, Trait) .Case("__" #Trait, true) #include "clang/Basic/TransformTypeTraits.def" .Default(false); diff --git a/clang/lib/Parse/ParseDeclCXX.cpp b/clang/lib/Parse/ParseDeclCXX.cpp index 8e0e86824829..96c9708c3711 100644 --- a/clang/lib/Parse/ParseDeclCXX.cpp +++ b/clang/lib/Parse/ParseDeclCXX.cpp @@ -1779,9 +1779,8 @@ void Parser::ParseClassSpecifier(tok::TokenKind TagTokKind, tok::kw___is_union, tok::kw___is_unsigned, tok::kw___is_void, - tok::kw___is_volatile, - tok::kw___reference_binds_to_temporary, - tok::kw___reference_constructs_from_temporary)) + tok::kw___is_volatile + )) // GNU libstdc++ 4.2 and libc++ use certain intrinsic names as the // name of struct templates, but some are keywords in GCC >= 4.3 // and Clang. Therefore, when we see the token sequence "struct diff --git a/clang/lib/Parse/ParseExpr.cpp b/clang/lib/Parse/ParseExpr.cpp index 5f5f9a79c8c4..0551b8314f9f 100644 --- a/clang/lib/Parse/ParseExpr.cpp +++ b/clang/lib/Parse/ParseExpr.cpp @@ -1166,7 +1166,6 @@ ExprResult Parser::ParseCastExpression(CastParseKind ParseKind, REVERTIBLE_TYPE_TRAIT(__is_void); REVERTIBLE_TYPE_TRAIT(__is_volatile); REVERTIBLE_TYPE_TRAIT(__reference_binds_to_temporary); - REVERTIBLE_TYPE_TRAIT(__reference_constructs_from_temporary); #define TRANSFORM_TYPE_TRAIT_DEF(_, Trait) \ REVERTIBLE_TYPE_TRAIT(RTT_JOIN(__, Trait)); #include "clang/Basic/TransformTypeTraits.def" diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index c1cb03e4ec7a..ae844bc69914 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -5627,6 +5627,77 @@ static bool EvaluateUnaryTypeTrait(Sema &Self, TypeTrait UTT, static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceInfo *Lhs, const TypeSourceInfo *Rhs, SourceLocation KeyLoc); +static ExprResult CheckConvertibilityForTypeTraits(Sema &Self, + const TypeSourceInfo *Lhs, + const TypeSourceInfo *Rhs, + SourceLocation KeyLoc) { + + QualType LhsT = Lhs->getType(); + QualType RhsT = Rhs->getType(); + + // C++0x [meta.rel]p4: + // Given the following function prototype: + // + // template + // typename add_rvalue_reference::type create(); + // + // the predicate condition for a template specialization + // is_convertible shall be satisfied if and only if + // the return expression in the following code would be + // well-formed, including any implicit conversions to the return + // type of the function: + // + // To test() { + // return create(); + // } + // + // Access checking is performed as if in a context unrelated to To and + // From. Only the validity of the immediate context of the expression + // of the return-statement (including conversions to the return type) + // is considered. + // + // We model the initialization as a copy-initialization of a temporary + // of the appropriate type, which for this expression is identical to the + // return statement (since NRVO doesn't apply). + + // Functions aren't allowed to return function or array types. + if (RhsT->isFunctionType() || RhsT->isArrayType()) + return ExprError(); + + // A function definition requires a complete, non-abstract return type. + if (!Self.isCompleteType(Rhs->getTypeLoc().getBeginLoc(), RhsT) || + Self.isAbstractType(Rhs->getTypeLoc().getBeginLoc(), RhsT)) + return ExprError(); + + // Compute the result of add_rvalue_reference. + if (LhsT->isObjectType() || LhsT->isFunctionType()) + LhsT = Self.Context.getRValueReferenceType(LhsT); + + // Build a fake source and destination for initialization. + InitializedEntity To(InitializedEntity::InitializeTemporary(RhsT)); + OpaqueValueExpr From(KeyLoc, LhsT.getNonLValueExprType(Self.Context), + Expr::getValueKindForType(LhsT)); + Expr *FromPtr = &From; + InitializationKind Kind = + InitializationKind::CreateCopy(KeyLoc, SourceLocation()); + + // Perform the initialization in an unevaluated context within a SFINAE + // trap at translation unit scope. + EnterExpressionEvaluationContext Unevaluated( + Self, Sema::ExpressionEvaluationContext::Unevaluated); + Sema::SFINAETrap SFINAE(Self, /*AccessCheckingSFINAE=*/true); + Sema::ContextRAII TUContext(Self, Self.Context.getTranslationUnitDecl()); + InitializationSequence Init(Self, To, Kind, FromPtr); + if (Init.Failed()) + return ExprError(); + + ExprResult Result = Init.Perform(Self, To, Kind, FromPtr); + if (Result.isInvalid() || SFINAE.hasErrorOccurred()) + return ExprError(); + + return Result; +} + static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, SourceLocation KWLoc, ArrayRef Args, @@ -5640,13 +5711,16 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, // Evaluate ReferenceBindsToTemporary and ReferenceConstructsFromTemporary // alongside the IsConstructible traits to avoid duplication. - if (Kind <= BTT_Last && Kind != BTT_ReferenceBindsToTemporary && Kind != BTT_ReferenceConstructsFromTemporary) + if (Kind <= BTT_Last && Kind != BTT_ReferenceBindsToTemporary && + Kind != BTT_ReferenceConstructsFromTemporary && + Kind != BTT_ReferenceConvertsFromTemporary) return EvaluateBinaryTypeTrait(S, Kind, Args[0], Args[1], RParenLoc); switch (Kind) { case clang::BTT_ReferenceBindsToTemporary: case clang::BTT_ReferenceConstructsFromTemporary: + case clang::BTT_ReferenceConvertsFromTemporary: case clang::TT_IsConstructible: case clang::TT_IsNothrowConstructible: case clang::TT_IsTriviallyConstructible: { @@ -5710,8 +5784,10 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, Sema::ContextRAII TUContext(S, S.Context.getTranslationUnitDecl()); InitializedEntity To( InitializedEntity::InitializeTemporary(S.Context, Args[0])); - InitializationKind InitKind(InitializationKind::CreateDirect(KWLoc, KWLoc, - RParenLoc)); + InitializationKind InitKind( + Kind == clang::BTT_ReferenceConvertsFromTemporary + ? InitializationKind::CreateCopy(KWLoc, KWLoc) + : InitializationKind::CreateDirect(KWLoc, KWLoc, RParenLoc)); InitializationSequence Init(S, To, InitKind, ArgExprs); if (Init.Failed()) return false; @@ -5723,7 +5799,9 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, if (Kind == clang::TT_IsConstructible) return true; - if (Kind == clang::BTT_ReferenceBindsToTemporary || Kind == clang::BTT_ReferenceConstructsFromTemporary) { + if (Kind == clang::BTT_ReferenceBindsToTemporary || + Kind == clang::BTT_ReferenceConstructsFromTemporary || + Kind == clang::BTT_ReferenceConvertsFromTemporary) { if (!T->isReferenceType()) return false; @@ -5737,9 +5815,12 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, if (U->isReferenceType()) return false; - TypeSourceInfo *TPtr = S.Context.CreateTypeSourceInfo(S.Context.getPointerType(S.BuiltinRemoveReference(T, UnaryTransformType::RemoveCVRef, {}))); - TypeSourceInfo *UPtr = S.Context.CreateTypeSourceInfo(S.Context.getPointerType(S.BuiltinRemoveReference(U, UnaryTransformType::RemoveCVRef, {}))); - return EvaluateBinaryTypeTrait(S, TypeTrait::BTT_IsConvertibleTo, UPtr, TPtr, RParenLoc); + TypeSourceInfo *TPtr = S.Context.CreateTypeSourceInfo( + S.Context.getPointerType(T.getNonReferenceType())); + TypeSourceInfo *UPtr = S.Context.CreateTypeSourceInfo( + S.Context.getPointerType(U.getNonReferenceType())); + return !CheckConvertibilityForTypeTraits(S, UPtr, TPtr, RParenLoc) + .isInvalid(); } if (Kind == clang::TT_IsNothrowConstructible) @@ -5945,68 +6026,12 @@ static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceI case BTT_IsConvertible: case BTT_IsConvertibleTo: case BTT_IsNothrowConvertible: { - // C++0x [meta.rel]p4: - // Given the following function prototype: - // - // template - // typename add_rvalue_reference::type create(); - // - // the predicate condition for a template specialization - // is_convertible shall be satisfied if and only if - // the return expression in the following code would be - // well-formed, including any implicit conversions to the return - // type of the function: - // - // To test() { - // return create(); - // } - // - // Access checking is performed as if in a context unrelated to To and - // From. Only the validity of the immediate context of the expression - // of the return-statement (including conversions to the return type) - // is considered. - // - // We model the initialization as a copy-initialization of a temporary - // of the appropriate type, which for this expression is identical to the - // return statement (since NRVO doesn't apply). - - // Functions aren't allowed to return function or array types. - if (RhsT->isFunctionType() || RhsT->isArrayType()) - return false; - - // A return statement in a void function must have void type. if (RhsT->isVoidType()) return LhsT->isVoidType(); - // A function definition requires a complete, non-abstract return type. - if (!Self.isCompleteType(Rhs->getTypeLoc().getBeginLoc(), RhsT) || - Self.isAbstractType(Rhs->getTypeLoc().getBeginLoc(), RhsT)) - return false; - - // Compute the result of add_rvalue_reference. - if (LhsT->isObjectType() || LhsT->isFunctionType()) - LhsT = Self.Context.getRValueReferenceType(LhsT); - - // Build a fake source and destination for initialization. - InitializedEntity To(InitializedEntity::InitializeTemporary(RhsT)); - OpaqueValueExpr From(KeyLoc, LhsT.getNonLValueExprType(Self.Context), - Expr::getValueKindForType(LhsT)); - Expr *FromPtr = &From; - InitializationKind Kind(InitializationKind::CreateCopy(KeyLoc, - SourceLocation())); - - // Perform the initialization in an unevaluated context within a SFINAE - // trap at translation unit scope. - EnterExpressionEvaluationContext Unevaluated( - Self, Sema::ExpressionEvaluationContext::Unevaluated); - Sema::SFINAETrap SFINAE(Self, /*AccessCheckingSFINAE=*/true); - Sema::ContextRAII TUContext(Self, Self.Context.getTranslationUnitDecl()); - InitializationSequence Init(Self, To, Kind, FromPtr); - if (Init.Failed()) - return false; - - ExprResult Result = Init.Perform(Self, To, Kind, FromPtr); - if (Result.isInvalid() || SFINAE.hasErrorOccurred()) + ExprResult Result = + CheckConvertibilityForTypeTraits(Self, Lhs, Rhs, KeyLoc); + if (Result.isInvalid()) return false; if (BTT != BTT_IsNothrowConvertible) diff --git a/clang/test/SemaCXX/type-traits.cpp b/clang/test/SemaCXX/type-traits.cpp index 01991887b284..f2fd45762abf 100644 --- a/clang/test/SemaCXX/type-traits.cpp +++ b/clang/test/SemaCXX/type-traits.cpp @@ -2908,6 +2908,12 @@ struct ConvertsToRef { operator RefType() const { return static_cast(obj); } mutable T obj = 42; }; +template +class ConvertsToRefPrivate { + operator RefType() const { return static_cast(obj); } + mutable T obj = 42; +}; + void reference_binds_to_temporary_checks() { static_assert(!(__reference_binds_to_temporary(int &, int &))); @@ -2937,6 +2943,8 @@ void reference_binds_to_temporary_checks() { static_assert((__is_constructible(int const &, LongRef))); static_assert((__reference_binds_to_temporary(int const &, LongRef))); + static_assert(!__reference_binds_to_temporary(int const &, ConvertsToRefPrivate)); + // Test that it doesn't accept non-reference types as input. static_assert(!(__reference_binds_to_temporary(int, long))); @@ -2944,6 +2952,17 @@ void reference_binds_to_temporary_checks() { static_assert((__reference_binds_to_temporary(const int &, long))); } + +struct ExplicitConversionRvalueRef { + operator int(); + explicit operator int&&(); +}; + +struct ExplicitConversionRef { + operator int(); + explicit operator int&(); +}; + void reference_constructs_from_temporary_checks() { static_assert(!__reference_constructs_from_temporary(int &, int &)); static_assert(!__reference_constructs_from_temporary(int &, int &&)); @@ -2973,6 +2992,8 @@ void reference_constructs_from_temporary_checks() { static_assert(__is_constructible(int const &, LongRef)); static_assert(__reference_constructs_from_temporary(int const &, LongRef)); + static_assert(!__reference_constructs_from_temporary(int const &, ConvertsToRefPrivate)); + // Test that it doesn't accept non-reference types as input. static_assert(!__reference_constructs_from_temporary(int, long)); @@ -2987,6 +3008,65 @@ void reference_constructs_from_temporary_checks() { static_assert(!__reference_constructs_from_temporary(const int&, int&&)); static_assert(__reference_constructs_from_temporary(int&&, long&&)); static_assert(__reference_constructs_from_temporary(int&&, long)); + + + static_assert(!__reference_constructs_from_temporary(int&, ExplicitConversionRef)); + static_assert(!__reference_constructs_from_temporary(const int&, ExplicitConversionRef)); + static_assert(!__reference_constructs_from_temporary(int&&, ExplicitConversionRvalueRef)); + + +} + +void reference_converts_from_temporary_checks() { + static_assert(!__reference_converts_from_temporary(int &, int &)); + static_assert(!__reference_converts_from_temporary(int &, int &&)); + + static_assert(!__reference_converts_from_temporary(int const &, int &)); + static_assert(!__reference_converts_from_temporary(int const &, int const &)); + static_assert(!__reference_converts_from_temporary(int const &, int &&)); + + static_assert(!__reference_converts_from_temporary(int &, long &)); // doesn't construct + + static_assert(__reference_converts_from_temporary(int const &, long &)); + static_assert(__reference_converts_from_temporary(int const &, long &&)); + static_assert(__reference_converts_from_temporary(int &&, long &)); + + using LRef = ConvertsToRef; + using RRef = ConvertsToRef; + using CLRef = ConvertsToRef; + using LongRef = ConvertsToRef; + static_assert(__is_constructible(int &, LRef)); + static_assert(!__reference_converts_from_temporary(int &, LRef)); + + static_assert(__is_constructible(int &&, RRef)); + static_assert(!__reference_converts_from_temporary(int &&, RRef)); + + static_assert(__is_constructible(int const &, CLRef)); + static_assert(!__reference_converts_from_temporary(int &&, CLRef)); + + static_assert(__is_constructible(int const &, LongRef)); + static_assert(__reference_converts_from_temporary(int const &, LongRef)); + static_assert(!__reference_converts_from_temporary(int const &, ConvertsToRefPrivate)); + + + // Test that it doesn't accept non-reference types as input. + static_assert(!__reference_converts_from_temporary(int, long)); + + static_assert(__reference_converts_from_temporary(const int &, long)); + + // Additional checks + static_assert(__reference_converts_from_temporary(POD const&, Derives)); + static_assert(__reference_converts_from_temporary(int&&, int)); + static_assert(__reference_converts_from_temporary(const int&, int)); + static_assert(!__reference_converts_from_temporary(int&&, int&&)); + static_assert(!__reference_converts_from_temporary(const int&, int&&)); + static_assert(__reference_converts_from_temporary(int&&, long&&)); + static_assert(__reference_converts_from_temporary(int&&, long)); + + static_assert(!__reference_converts_from_temporary(int&, ExplicitConversionRef)); + static_assert(__reference_converts_from_temporary(const int&, ExplicitConversionRef)); + static_assert(__reference_converts_from_temporary(int&&, ExplicitConversionRvalueRef)); + } void array_rank() { diff --git a/clang/www/cxx_status.html b/clang/www/cxx_status.html index 6e0599cc9fe0..1338f544ffcb 100755 --- a/clang/www/cxx_status.html +++ b/clang/www/cxx_status.html @@ -347,15 +347,7 @@ C++23, informally referred to as C++26.

Type trait to determine if a reference binds to a temporary P2255R2 - -
Partial - Clang provides __reference_constructs_from_temporary type - trait builtin, with which std::reference_constructs_from_temporary - is implemented. __reference_converts_from_temporary needs to be - provided, following the normal cross-vendor convention to implement - traits requiring compiler support directly. -
- + Clang 19 -- GitLab From 7e52ad3b5b9509d0873965e8492ab01141342822 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Fri, 10 May 2024 15:49:53 +0900 Subject: [PATCH 234/328] Fix a warning for #91455 [-Wc++20-extensions] --- .../Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp b/clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp index 0a2514a2d7c1..d194742dbea7 100644 --- a/clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp @@ -20,7 +20,7 @@ SolverTest::createSolverWithLowTimeout() { namespace { INSTANTIATE_TYPED_TEST_SUITE_P(WatchedLiteralsSolverTest, SolverTest, - WatchedLiteralsSolver); + WatchedLiteralsSolver, ); } // namespace } // namespace clang::dataflow::test -- GitLab From 2a61eebc66c0903cf3834a520b1f975ac3cdf92b Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Thu, 9 May 2024 19:34:43 +0900 Subject: [PATCH 235/328] Cleanup asserts in BranchParameters and DecisionParameters --- clang/lib/CodeGen/CoverageMappingGen.cpp | 5 +---- llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h | 5 +---- llvm/include/llvm/ProfileData/Coverage/MCDCTypes.h | 8 ++++++-- llvm/lib/ProfileData/Coverage/CoverageMapping.cpp | 2 -- llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp | 1 - 5 files changed, 8 insertions(+), 13 deletions(-) diff --git a/clang/lib/CodeGen/CoverageMappingGen.cpp b/clang/lib/CodeGen/CoverageMappingGen.cpp index 733686d4946b..ce2f39aeb082 100644 --- a/clang/lib/CodeGen/CoverageMappingGen.cpp +++ b/clang/lib/CodeGen/CoverageMappingGen.cpp @@ -191,10 +191,7 @@ public: bool isBranch() const { return FalseCount.has_value(); } bool isMCDCDecision() const { - const auto *DecisionParams = - std::get_if(&MCDCParams); - assert(!DecisionParams || DecisionParams->NumConditions > 0); - return DecisionParams; + return std::holds_alternative(MCDCParams); } const auto &getMCDCDecisionParams() const { diff --git a/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h b/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h index 7a8b6639f297..da0310404524 100644 --- a/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h +++ b/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h @@ -462,10 +462,7 @@ public: CounterMappingRegion getDecisionRegion() const { return Region; } unsigned getNumConditions() const { - unsigned NumConditions = Region.getDecisionParams().NumConditions; - assert(NumConditions != 0 && - "In MC/DC, NumConditions should never be zero!"); - return NumConditions; + return Region.getDecisionParams().NumConditions; } unsigned getNumTestVectors() const { return TV.size(); } bool isCondFolded(unsigned Condition) const { return Folded[Condition]; } diff --git a/llvm/include/llvm/ProfileData/Coverage/MCDCTypes.h b/llvm/include/llvm/ProfileData/Coverage/MCDCTypes.h index 8c78bed4dec5..191e4ead95ea 100644 --- a/llvm/include/llvm/ProfileData/Coverage/MCDCTypes.h +++ b/llvm/include/llvm/ProfileData/Coverage/MCDCTypes.h @@ -33,7 +33,9 @@ struct DecisionParameters { DecisionParameters() = delete; DecisionParameters(unsigned BitmapIdx, unsigned NumConditions) - : BitmapIdx(BitmapIdx), NumConditions(NumConditions) {} + : BitmapIdx(BitmapIdx), NumConditions(NumConditions) { + assert(NumConditions > 0); + } }; struct BranchParameters { @@ -44,7 +46,9 @@ struct BranchParameters { BranchParameters() = delete; BranchParameters(ConditionID ID, const ConditionIDs &Conds) - : ID(ID), Conds(Conds) {} + : ID(ID), Conds(Conds) { + assert(ID >= 0); + } }; /// The type of MC/DC-specific parameters. diff --git a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp index 6c77ce017c03..8c81bbe8e9c4 100644 --- a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp +++ b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp @@ -338,7 +338,6 @@ public: #endif for (const auto *Branch : Branches) { const auto &BranchParams = Branch->getBranchParams(); - assert(BranchParams.ID >= 0 && "CondID isn't set"); assert(SeenIDs.insert(BranchParams.ID).second && "Duplicate CondID"); NextIDs[BranchParams.ID] = BranchParams.Conds; } @@ -694,7 +693,6 @@ private: assert(Branch.Kind == CounterMappingRegion::MCDCBranchRegion); auto ConditionID = Branch.getBranchParams().ID; - assert(ConditionID >= 0 && "ConditionID should be positive"); if (ConditionIDs.contains(ConditionID) || ConditionID >= DecisionParams.NumConditions) diff --git a/llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp b/llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp index 5036bde5aca7..adfd22804356 100644 --- a/llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp +++ b/llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp @@ -256,7 +256,6 @@ void CoverageMappingWriter::write(raw_ostream &OS) { // They are written as internal values plus 1. const auto &BranchParams = I->getBranchParams(); ParamsShouldBeNull = false; - assert(BranchParams.ID >= 0); unsigned ID1 = BranchParams.ID + 1; unsigned TID1 = BranchParams.Conds[true] + 1; unsigned FID1 = BranchParams.Conds[false] + 1; -- GitLab From 6ce4c4ca2bb846c2b8d64dc2b3d3496785c9edff Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Thu, 9 May 2024 23:56:56 -0700 Subject: [PATCH 236/328] [clang-format][NFC] Drop a redundant clang::format:: --- clang/lib/Format/UnwrappedLineParser.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index 71557b127fb7..310b75485e08 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -3385,7 +3385,7 @@ void UnwrappedLineParser::parseAccessSpecifier() { /// \brief Parses a requires, decides if it is a clause or an expression. /// \pre The current token has to be the requires keyword. /// \returns true if it parsed a clause. -bool clang::format::UnwrappedLineParser::parseRequires() { +bool UnwrappedLineParser::parseRequires() { assert(FormatTok->is(tok::kw_requires) && "'requires' expected"); auto RequiresToken = FormatTok; -- GitLab From 6aac30fa43f094ac25269bda163dc89a88cb8da7 Mon Sep 17 00:00:00 2001 From: Jack Styles Date: Fri, 10 May 2024 08:09:02 +0100 Subject: [PATCH 237/328] Update FEAT_PAuth_LR behaviour for AArch64 (#90614) Currently, LLVM enables `-mbranch-protection=standard` as `bti+pac-ret`. To align LLVM with the behaviour in GNU, this has been updated to `bti+pac-ret+pc` when FEAT_PAuth_LR is enabled as an optional feature via the `-mcpu=` options. If this is not enabled, then this will revert to the existing behaviour. --- clang/lib/Basic/Targets/AArch64.cpp | 2 +- clang/lib/Driver/ToolChains/Clang.cpp | 20 ++++++++++++++++++- .../Preprocessor/aarch64-target-features.c | 4 ++++ llvm/docs/ReleaseNotes.rst | 5 +++++ .../llvm/TargetParser/AArch64TargetParser.h | 2 ++ .../llvm/TargetParser/ARMTargetParserCommon.h | 2 +- llvm/lib/TargetParser/AArch64TargetParser.cpp | 5 +++++ .../TargetParser/ARMTargetParserCommon.cpp | 3 ++- 8 files changed, 39 insertions(+), 4 deletions(-) diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index 4b1545339f69..5db1ce78c657 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -225,7 +225,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef, BranchProtectionInfo &BPI, StringRef &Err) const { llvm::ARM::ParsedBranchProtection PBP; - if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err)) + if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err, HasPAuthLR)) return false; BPI.SignReturnAddr = diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 449eb9b2a965..f81c2024ae48 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -55,6 +55,7 @@ #include "llvm/Support/Path.h" #include "llvm/Support/Process.h" #include "llvm/Support/YAMLParser.h" +#include "llvm/TargetParser/AArch64TargetParser.h" #include "llvm/TargetParser/ARMTargetParserCommon.h" #include "llvm/TargetParser/Host.h" #include "llvm/TargetParser/LoongArchTargetParser.h" @@ -1511,7 +1512,24 @@ static void CollectARMPACBTIOptions(const ToolChain &TC, const ArgList &Args, } else { StringRef DiagMsg; llvm::ARM::ParsedBranchProtection PBP; - if (!llvm::ARM::parseBranchProtection(A->getValue(), PBP, DiagMsg)) + bool EnablePAuthLR = false; + + // To know if we need to enable PAuth-LR As part of the standard branch + // protection option, it needs to be determined if the feature has been + // activated in the `march` argument. This information is stored within the + // CmdArgs variable and can be found using a search. + if (isAArch64) { + auto isPAuthLR = [](const char *member) { + llvm::AArch64::ExtensionInfo pauthlr_extension = + llvm::AArch64::getExtensionByID(llvm::AArch64::AEK_PAUTHLR); + return (pauthlr_extension.Feature.compare(member) == 0); + }; + + if (std::any_of(CmdArgs.begin(), CmdArgs.end(), isPAuthLR)) + EnablePAuthLR = true; + } + if (!llvm::ARM::parseBranchProtection(A->getValue(), PBP, DiagMsg, + EnablePAuthLR)) D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << DiagMsg; if (!isAArch64 && PBP.Key == "b_key") diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index 4d10eeafa884..82304a15a04a 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -616,6 +616,9 @@ // ================== Check Armv9.5-A Pointer Authentication Enhancements(PAuth_LR). // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-LR-OFF %s // RUN: %clang -target arm64-none-linux-gnu -march=armv9.5-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-LR-OFF %s +// RUN: %clang -target arm64-none-linux-gnu -march=armv9.5-a -mbranch-protection=standard -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-LR-OFF,CHECK-BRANCH-PROTECTION-NO-PC %s +// RUN: %clang -target arm64-none-linux-gnu -march=armv9.5-a+pauth-lr -mbranch-protection=standard -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-LR,CHECK-BRANCH-PROTECTION-PC %s +// RUN: %clang -target arm64-none-linux-gnu -march=armv9.5-a+nopauth-lr -mbranch-protection=standard -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-LR-OFF,CHECK-BRANCH-PROTECTION-NO-PC %s // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth -mbranch-protection=none -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-LR-OFF %s // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth-lr -mbranch-protection=none -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-LR %s // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth-lr -mbranch-protection=bti -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-LR %s @@ -636,6 +639,7 @@ // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth-lr -mbranch-protection=pac-ret+pc+b-key -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-LR,CHECK-BRANCH-PROTECTION-PC-BKEY %s // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth-lr -mbranch-protection=pac-ret+pc+leaf -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-LR,CHECK-BRANCH-PROTECTION-PC-LEAF %s // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth-lr -mbranch-protection=pac-ret+pc+leaf+b-key -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-LR,CHECK-BRANCH-PROTECTION-PC-LEAF-BKEY %s +// CHECK-BRANCH-PROTECTION-NO-PC: #define __ARM_FEATURE_PAC_DEFAULT 1 // CHECK-BRANCH-PROTECTION-PC: #define __ARM_FEATURE_PAC_DEFAULT 9 // CHECK-BRANCH-PROTECTION-PC-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 10 // CHECK-BRANCH-PROTECTION-PC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 13 diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 26f1d33f6800..f2577e1684f5 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -76,6 +76,11 @@ Changes to the AArch64 Backend * Added support for Cortex-A78AE, Cortex-A520AE, Cortex-A720AE, Cortex-R82AE, Neoverse-N3, Neoverse-V3 and Neoverse-V3AE CPUs. +* ``-mbranch-protection=standard`` now enables FEAT_PAuth_LR by + default when the feature is enabled. The new behaviour results + in ``standard`` being equal to ``bti+pac-ret+pc`` when ``+pauth-lr`` + is passed as part of ``-mcpu=`` options. + Changes to the AMDGPU Backend ----------------------------- diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 1124420daf8d..20c3f95173c2 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -676,6 +676,8 @@ inline constexpr Alias CpuAliases[] = {{"cobalt-100", "neoverse-n2"}, inline constexpr Alias ExtAliases[] = {{"rdma", "rdm"}}; +const ExtensionInfo &getExtensionByID(ArchExtKind(ExtID)); + bool getExtensionFeatures( const AArch64::ExtensionBitset &Extensions, std::vector &Features); diff --git a/llvm/include/llvm/TargetParser/ARMTargetParserCommon.h b/llvm/include/llvm/TargetParser/ARMTargetParserCommon.h index 8ae553ca80dd..f6115718e9f5 100644 --- a/llvm/include/llvm/TargetParser/ARMTargetParserCommon.h +++ b/llvm/include/llvm/TargetParser/ARMTargetParserCommon.h @@ -46,7 +46,7 @@ struct ParsedBranchProtection { }; bool parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP, - StringRef &Err); + StringRef &Err, bool EnablePAuthLR = false); } // namespace ARM } // namespace llvm diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp index 71099462d5ec..026214e7e2ea 100644 --- a/llvm/lib/TargetParser/AArch64TargetParser.cpp +++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp @@ -280,3 +280,8 @@ bool AArch64::ExtensionSet::parseModifier(StringRef Modifier) { } return false; } + +const AArch64::ExtensionInfo & +AArch64::getExtensionByID(AArch64::ArchExtKind ExtID) { + return lookupExtensionByID(ExtID); +} diff --git a/llvm/lib/TargetParser/ARMTargetParserCommon.cpp b/llvm/lib/TargetParser/ARMTargetParserCommon.cpp index 45d04f9bcbfb..d6ce6581bb1a 100644 --- a/llvm/lib/TargetParser/ARMTargetParserCommon.cpp +++ b/llvm/lib/TargetParser/ARMTargetParserCommon.cpp @@ -139,7 +139,7 @@ ARM::EndianKind ARM::parseArchEndian(StringRef Arch) { // returned in `PBP`. Returns false in error, with `Err` containing // an erroneous part of the spec. bool ARM::parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP, - StringRef &Err) { + StringRef &Err, bool EnablePAuthLR) { PBP = {"none", "a_key", false, false, false}; if (Spec == "none") return true; // defaults are ok @@ -148,6 +148,7 @@ bool ARM::parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP, PBP.Scope = "non-leaf"; PBP.BranchTargetEnforcement = true; PBP.GuardedControlStack = true; + PBP.BranchProtectionPAuthLR = EnablePAuthLR; return true; } -- GitLab From 5d24217c2c1c06358168cae65d3ff8632b28cd7d Mon Sep 17 00:00:00 2001 From: Petr Hosek Date: Fri, 10 May 2024 00:38:52 -0700 Subject: [PATCH 238/328] [Clang] Pass -fseparate-named-sections from the driver (#91567) This is a follow up to #91028. --- clang/lib/Driver/ToolChains/Clang.cpp | 2 ++ clang/test/Driver/fseparate-named-sections.c | 4 ++++ 2 files changed, 6 insertions(+) create mode 100644 clang/test/Driver/fseparate-named-sections.c diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index f81c2024ae48..42feb1650574 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -6146,6 +6146,8 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.addOptOutFlag(CmdArgs, options::OPT_funique_section_names, options::OPT_fno_unique_section_names); + Args.addOptInFlag(CmdArgs, options::OPT_fseparate_named_sections, + options::OPT_fno_separate_named_sections); Args.addOptInFlag(CmdArgs, options::OPT_funique_internal_linkage_names, options::OPT_fno_unique_internal_linkage_names); Args.addOptInFlag(CmdArgs, options::OPT_funique_basic_block_section_names, diff --git a/clang/test/Driver/fseparate-named-sections.c b/clang/test/Driver/fseparate-named-sections.c new file mode 100644 index 000000000000..6264b8fcf0d8 --- /dev/null +++ b/clang/test/Driver/fseparate-named-sections.c @@ -0,0 +1,4 @@ +// RUN: %clang -### -fseparate-named-sections %s -c 2>&1 | FileCheck -check-prefix=CHECK-OPT %s +// RUN: %clang -### -fseparate-named-sections -fno-separate-named-sections %s -c 2>&1 | FileCheck -check-prefix=CHECK-NOOPT %s +// CHECK-OPT: "-fseparate-named-sections" +// CHECK-NOOPT-NOT: "-fseparate-named-sections" -- GitLab From a76518cadc5eaa6b6d07334e2b5bc08382aabe49 Mon Sep 17 00:00:00 2001 From: David Spickett Date: Fri, 10 May 2024 09:20:48 +0100 Subject: [PATCH 239/328] [lldb][ELF] Return address class map changes from symbol table parsing methods (#91585) Instead of updating the member of the ObjectFileELF instance. This means that if one object file asks another to parse the symbol table, that first object's can update its address class map with the same changes that the other object did. (I'm not returning a reference to the other object's m_address_class_map member because there may be other things in there not related to the symbol table being parsed) This will fix the code added in https://github.com/llvm/llvm-project/pull/90622 which broke the test `Expr/TestStringLiteralExpr.test` on 32 bit Arm Linux. This happened because we had the program file, then asked for a better object file, which returned the same program file again. This creates a second ObjectFileELF for the same file, so when we tell the second instance to parse the symbol table it actually calls into the first instance, leaving the address class map of the second instance empty. Which caused us to put an Arm breakpoint instuction at a Thumb return address and broke the ability to call mmap. --- .../Plugins/ObjectFile/ELF/ObjectFileELF.cpp | 77 ++++++++++++------- .../Plugins/ObjectFile/ELF/ObjectFileELF.h | 21 ++--- 2 files changed, 60 insertions(+), 38 deletions(-) diff --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp index 1646ee9aa34a..d88f2d083019 100644 --- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp +++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp @@ -2060,13 +2060,17 @@ static char FindArmAarch64MappingSymbol(const char *symbol_name) { #define IS_MICROMIPS(ST_OTHER) (((ST_OTHER)&STO_MIPS_ISA) == STO_MICROMIPS) // private -unsigned ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, - SectionList *section_list, - const size_t num_symbols, - const DataExtractor &symtab_data, - const DataExtractor &strtab_data) { +std::pair +ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, + SectionList *section_list, const size_t num_symbols, + const DataExtractor &symtab_data, + const DataExtractor &strtab_data) { ELFSymbol symbol; lldb::offset_t offset = 0; + // The changes these symbols would make to the class map. We will also update + // m_address_class_map but need to tell the caller what changed because the + // caller may be another object file. + FileAddressToAddressClassMap address_class_map; static ConstString text_section_name(".text"); static ConstString init_section_name(".init"); @@ -2213,18 +2217,18 @@ unsigned ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, switch (mapping_symbol) { case 'a': // $a[.]* - marks an ARM instruction sequence - m_address_class_map[symbol.st_value] = AddressClass::eCode; + address_class_map[symbol.st_value] = AddressClass::eCode; break; case 'b': case 't': // $b[.]* - marks a THUMB BL instruction sequence // $t[.]* - marks a THUMB instruction sequence - m_address_class_map[symbol.st_value] = + address_class_map[symbol.st_value] = AddressClass::eCodeAlternateISA; break; case 'd': // $d[.]* - marks a data item sequence (e.g. lit pool) - m_address_class_map[symbol.st_value] = AddressClass::eData; + address_class_map[symbol.st_value] = AddressClass::eData; break; } } @@ -2238,11 +2242,11 @@ unsigned ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, switch (mapping_symbol) { case 'x': // $x[.]* - marks an A64 instruction sequence - m_address_class_map[symbol.st_value] = AddressClass::eCode; + address_class_map[symbol.st_value] = AddressClass::eCode; break; case 'd': // $d[.]* - marks a data item sequence (e.g. lit pool) - m_address_class_map[symbol.st_value] = AddressClass::eData; + address_class_map[symbol.st_value] = AddressClass::eData; break; } } @@ -2260,11 +2264,11 @@ unsigned ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, // conjunction with symbol.st_value to produce the final // symbol_value that we store in the symtab. symbol_value_offset = -1; - m_address_class_map[symbol.st_value ^ 1] = + address_class_map[symbol.st_value ^ 1] = AddressClass::eCodeAlternateISA; } else { // This address is ARM - m_address_class_map[symbol.st_value] = AddressClass::eCode; + address_class_map[symbol.st_value] = AddressClass::eCode; } } } @@ -2285,17 +2289,17 @@ unsigned ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, */ if (arch.IsMIPS()) { if (IS_MICROMIPS(symbol.st_other)) - m_address_class_map[symbol.st_value] = AddressClass::eCodeAlternateISA; + address_class_map[symbol.st_value] = AddressClass::eCodeAlternateISA; else if ((symbol.st_value & 1) && (symbol_type == eSymbolTypeCode)) { symbol.st_value = symbol.st_value & (~1ull); - m_address_class_map[symbol.st_value] = AddressClass::eCodeAlternateISA; + address_class_map[symbol.st_value] = AddressClass::eCodeAlternateISA; } else { if (symbol_type == eSymbolTypeCode) - m_address_class_map[symbol.st_value] = AddressClass::eCode; + address_class_map[symbol.st_value] = AddressClass::eCode; else if (symbol_type == eSymbolTypeData) - m_address_class_map[symbol.st_value] = AddressClass::eData; + address_class_map[symbol.st_value] = AddressClass::eData; else - m_address_class_map[symbol.st_value] = AddressClass::eUnknown; + address_class_map[symbol.st_value] = AddressClass::eUnknown; } } } @@ -2392,24 +2396,33 @@ unsigned ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, dc_symbol.SetIsWeak(true); symtab->AddSymbol(dc_symbol); } - return i; + + m_address_class_map.merge(address_class_map); + return {i, address_class_map}; } -unsigned ObjectFileELF::ParseSymbolTable(Symtab *symbol_table, - user_id_t start_id, - lldb_private::Section *symtab) { +std::pair +ObjectFileELF::ParseSymbolTable(Symtab *symbol_table, user_id_t start_id, + lldb_private::Section *symtab) { if (symtab->GetObjectFile() != this) { // If the symbol table section is owned by a different object file, have it // do the parsing. ObjectFileELF *obj_file_elf = static_cast(symtab->GetObjectFile()); - return obj_file_elf->ParseSymbolTable(symbol_table, start_id, symtab); + auto [num_symbols, address_class_map] = + obj_file_elf->ParseSymbolTable(symbol_table, start_id, symtab); + + // The other object file returned the changes it made to its address + // class map, make the same changes to ours. + m_address_class_map.merge(address_class_map); + + return {num_symbols, address_class_map}; } // Get section list for this object file. SectionList *section_list = m_sections_up.get(); if (!section_list) - return 0; + return {}; user_id_t symtab_id = symtab->GetID(); const ELFSectionHeaderInfo *symtab_hdr = GetSectionHeaderByIndex(symtab_id); @@ -2435,7 +2448,7 @@ unsigned ObjectFileELF::ParseSymbolTable(Symtab *symbol_table, } } - return 0; + return {0, {}}; } size_t ObjectFileELF::ParseDynamicSymbols() { @@ -2972,8 +2985,12 @@ void ObjectFileELF::ParseSymtab(Symtab &lldb_symtab) { // while the reverse is not necessarily true. Section *symtab = section_list->FindSectionByType(eSectionTypeELFSymbolTable, true).get(); - if (symtab) - symbol_id += ParseSymbolTable(&lldb_symtab, symbol_id, symtab); + if (symtab) { + auto [num_symbols, address_class_map] = + ParseSymbolTable(&lldb_symtab, symbol_id, symtab); + m_address_class_map.merge(address_class_map); + symbol_id += num_symbols; + } // The symtab section is non-allocable and can be stripped, while the // .dynsym section which should always be always be there. To support the @@ -2986,8 +3003,12 @@ void ObjectFileELF::ParseSymtab(Symtab &lldb_symtab) { Section *dynsym = section_list->FindSectionByType(eSectionTypeELFDynamicSymbols, true) .get(); - if (dynsym) - symbol_id += ParseSymbolTable(&lldb_symtab, symbol_id, dynsym); + if (dynsym) { + auto [num_symbols, address_class_map] = + ParseSymbolTable(&lldb_symtab, symbol_id, dynsym); + symbol_id += num_symbols; + m_address_class_map.merge(address_class_map); + } } // DT_JMPREL diff --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h index bc8e34981a9d..716bbe01638f 100644 --- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h +++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h @@ -285,18 +285,19 @@ private: /// Populates the symbol table with all non-dynamic linker symbols. This /// method will parse the symbols only once. Returns the number of symbols - /// parsed. - unsigned ParseSymbolTable(lldb_private::Symtab *symbol_table, - lldb::user_id_t start_id, - lldb_private::Section *symtab); + /// parsed and a map of address types (used by targets like Arm that have + /// an alternative ISA mode like Thumb). + std::pair + ParseSymbolTable(lldb_private::Symtab *symbol_table, lldb::user_id_t start_id, + lldb_private::Section *symtab); /// Helper routine for ParseSymbolTable(). - unsigned ParseSymbols(lldb_private::Symtab *symbol_table, - lldb::user_id_t start_id, - lldb_private::SectionList *section_list, - const size_t num_symbols, - const lldb_private::DataExtractor &symtab_data, - const lldb_private::DataExtractor &strtab_data); + std::pair + ParseSymbols(lldb_private::Symtab *symbol_table, lldb::user_id_t start_id, + lldb_private::SectionList *section_list, + const size_t num_symbols, + const lldb_private::DataExtractor &symtab_data, + const lldb_private::DataExtractor &strtab_data); /// Scans the relocation entries and adds a set of artificial symbols to the /// given symbol table for each PLT slot. Returns the number of symbols -- GitLab From 23b673e5b4b73b42864fcd7d63c1e974317ed4d6 Mon Sep 17 00:00:00 2001 From: David Green Date: Fri, 10 May 2024 09:27:02 +0100 Subject: [PATCH 240/328] [DAG][AArch64] Handle vscale addressing modes in reassociationCanBreakAddressingModePattern (#89908) reassociationCanBreakAddressingModePattern tries to prevent bad add reassociations that would break adrressing mode patterns. This adds support for vscale offset addressing modes, making sure we don't break patterns that already exist. It does not optimize _to_ the correct addressing modes yet, but prevents us from optimizating _away_ from them. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 42 ++++++++++++++- llvm/test/CodeGen/AArch64/sve-reassocadd.ll | 54 +++++++------------ 2 files changed, 58 insertions(+), 38 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 4589d201d620..fddc97d8901a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1083,7 +1083,44 @@ bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc, // (load/store (add, (add, x, y), offset2)) -> // (load/store (add, (add, x, offset2), y)). - if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD) + if (N0.getOpcode() != ISD::ADD) + return false; + + // Check for vscale addressing modes. + // (load/store (add/sub (add x, y), vscale)) + // (load/store (add/sub (add x, y), (lsl vscale, C))) + // (load/store (add/sub (add x, y), (mul vscale, C))) + if ((N1.getOpcode() == ISD::VSCALE || + ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::MUL) && + N1.getOperand(0).getOpcode() == ISD::VSCALE && + isa(N1.getOperand(1)))) && + N1.getValueType().getFixedSizeInBits() <= 64) { + int64_t ScalableOffset = + N1.getOpcode() == ISD::VSCALE + ? N1.getConstantOperandVal(0) + : (N1.getOperand(0).getConstantOperandVal(0) * + (N1.getOpcode() == ISD::SHL ? (1 << N1.getConstantOperandVal(1)) + : N1.getConstantOperandVal(1))); + if (Opc == ISD::SUB) + ScalableOffset = -ScalableOffset; + if (all_of(N->uses(), [&](SDNode *Node) { + if (auto *LoadStore = dyn_cast(Node); + LoadStore && LoadStore->getBasePtr().getNode() == N) { + TargetLoweringBase::AddrMode AM; + AM.HasBaseReg = true; + AM.ScalableOffset = ScalableOffset; + EVT VT = LoadStore->getMemoryVT(); + unsigned AS = LoadStore->getAddressSpace(); + Type *AccessTy = VT.getTypeForEVT(*DAG.getContext()); + return TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, + AS); + } + return false; + })) + return true; + } + + if (Opc != ISD::ADD) return false; auto *C2 = dyn_cast(N1); @@ -3971,7 +4008,8 @@ SDValue DAGCombiner::visitSUB(SDNode *N) { // Hoist one-use addition by non-opaque constant: // (x + C) - y -> (x - y) + C - if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && + if (!reassociationCanBreakAddressingModePattern(ISD::SUB, DL, N, N0, N1) && + N0.getOpcode() == ISD::ADD && N0.hasOneUse() && isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) { SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1); return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1)); diff --git a/llvm/test/CodeGen/AArch64/sve-reassocadd.ll b/llvm/test/CodeGen/AArch64/sve-reassocadd.ll index c7261200a567..f54098b29a27 100644 --- a/llvm/test/CodeGen/AArch64/sve-reassocadd.ll +++ b/llvm/test/CodeGen/AArch64/sve-reassocadd.ll @@ -22,11 +22,9 @@ entry: define @i8_4s_1v(ptr %b) { ; CHECK-LABEL: i8_4s_1v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: rdvl x8, #1 ; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: mov w9, #4 // =0x4 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8, x9] +; CHECK-NEXT: add x8, x0, #4 +; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8, #1, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 4 @@ -58,11 +56,9 @@ entry: define @i16_8s_1v(ptr %b) { ; CHECK-LABEL: i16_8s_1v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: rdvl x8, #1 ; CHECK-NEXT: ptrue p0.h -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, x9, lsl #1] +; CHECK-NEXT: add x8, x0, #8 +; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, #1, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 8 @@ -94,11 +90,9 @@ entry: define @i16_8s_2v(ptr %b) { ; CHECK-LABEL: i16_8s_2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: rdvl x8, #2 ; CHECK-NEXT: ptrue p0.h -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, x9, lsl #1] +; CHECK-NEXT: add x8, x0, #8 +; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, #2, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 8 @@ -130,11 +124,9 @@ entry: define @i32_16s_2v(ptr %b) { ; CHECK-LABEL: i32_16s_2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: rdvl x8, #1 ; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2] +; CHECK-NEXT: add x8, x0, #16 +; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, #1, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 16 @@ -166,11 +158,9 @@ entry: define @i64_32s_2v(ptr %b) { ; CHECK-LABEL: i64_32s_2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: rdvl x8, #1 ; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, x9, lsl #3] +; CHECK-NEXT: add x8, x0, #32 +; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #1, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 32 @@ -203,11 +193,9 @@ entry: define @i8_4s_m2v(ptr %b) { ; CHECK-LABEL: i8_4s_m2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: cnth x8, all, mul #4 ; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: mov w9, #4 // =0x4 -; CHECK-NEXT: sub x8, x0, x8 -; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8, x9] +; CHECK-NEXT: add x8, x0, #4 +; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8, #-2, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 4 @@ -239,11 +227,9 @@ entry: define @i16_8s_m2v(ptr %b) { ; CHECK-LABEL: i16_8s_m2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: cnth x8, all, mul #4 ; CHECK-NEXT: ptrue p0.h -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: sub x8, x0, x8 -; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, x9, lsl #1] +; CHECK-NEXT: add x8, x0, #8 +; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, #-2, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 8 @@ -275,11 +261,9 @@ entry: define @i32_16s_m2v(ptr %b) { ; CHECK-LABEL: i32_16s_m2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: cnth x8, all, mul #4 ; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: sub x8, x0, x8 -; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2] +; CHECK-NEXT: add x8, x0, #16 +; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, #-2, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 16 @@ -311,11 +295,9 @@ entry: define @i64_32s_m2v(ptr %b) { ; CHECK-LABEL: i64_32s_m2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: cnth x8, all, mul #4 ; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: sub x8, x0, x8 -; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, x9, lsl #3] +; CHECK-NEXT: add x8, x0, #32 +; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #-2, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 32 -- GitLab From e6d29be566d19a6558597ed1ede4783e85485749 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 10 May 2024 09:56:11 +0100 Subject: [PATCH 241/328] [clang] fix FMV test for Win x Arm builds (#91490) --- clang/test/Driver/aarch64-fmv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/test/Driver/aarch64-fmv.c b/clang/test/Driver/aarch64-fmv.c index 873a88964e9b..e7d01d1d5906 100644 --- a/clang/test/Driver/aarch64-fmv.c +++ b/clang/test/Driver/aarch64-fmv.c @@ -11,8 +11,8 @@ // RUN: %clang --target=aarch64-linux-android23 --rtlib=compiler-rt -### -c %s 2>&1 | FileCheck -check-prefix=FMV-ENABLED %s // FMV is disabled without compiler-rt: -// RUN: %clang --target=aarch64 -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s -// RUN: %clang --target=aarch64-linux-gnu -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s +// RUN: %clang --rtlib=libgcc --target=aarch64 -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s +// RUN: %clang --rtlib=libgcc --target=aarch64-linux-gnu -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s // Disabled for older android versions: // RUN: %clang --rtlib=compiler-rt --target=aarch64-linux-android -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s -- GitLab From 641949654910a533076e35517d084e2961adbdfa Mon Sep 17 00:00:00 2001 From: Abid Qadeer Date: Fri, 10 May 2024 10:12:24 +0100 Subject: [PATCH 242/328] [flang][OMPIRBuilder] Keep debug location in sync with insert point. (#89953) A customer reported an issue which I have reduced to the test in the PR. If built with debug info enabled, the build fails with the following error in the verifier. !dbg attachment points at wrong subprogram for function The problem happened because some of the functions in OMPIRBuilder.cpp updated the insertion point with the passed in location but did not change the current debug location. This caused a stale debug location to be attached to the instruction. I have solved it by replacing restoreIP with updateToLocation which updates both the insertion point and debug location. The updateToLocation is used in many places already, so this PR brings functions that I have changed in line with rest of the file. Slight issue is that I am not checking the return type of updateToLocation as there is no good value I could return in that case. But if we have a condition where updateToLocation will return false, these functions will fail in any case. I have added a test that checks that build does not fail. I was not sure what is the correct location for the test should be. Happy to move it to more appropriate location. --- flang/test/Integration/debug-loc-1.f90 | 30 +++++++++++++++++++++++ llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 12 ++++----- 2 files changed, 36 insertions(+), 6 deletions(-) create mode 100644 flang/test/Integration/debug-loc-1.f90 diff --git a/flang/test/Integration/debug-loc-1.f90 b/flang/test/Integration/debug-loc-1.f90 new file mode 100644 index 000000000000..5fe2c8e31dd9 --- /dev/null +++ b/flang/test/Integration/debug-loc-1.f90 @@ -0,0 +1,30 @@ +!RUN: %flang_fc1 -emit-llvm -debug-info-kind=line-tables-only -fopenmp %s -o - | FileCheck %s + +! Test that this file builds without an error. + +module debugloc +contains +subroutine test1 +implicit none + integer :: i + real, save :: var + +! CHECK: DILocation(line: [[@LINE+1]], {{.*}}) +!$omp parallel do +do i=1,100 + var = var + 0.1 +end do +!$omp end parallel do + +end subroutine test1 + +subroutine test2 + +real, save :: tp +!$omp threadprivate (tp) +! CHECK: DILocation(line: [[@LINE+1]], {{.*}}) + tp = tp + 1 + +end subroutine test2 + +end module debugloc diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp index 9f0c07ef0da9..42ea20919a5e 100644 --- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp +++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp @@ -4401,7 +4401,7 @@ CallInst *OpenMPIRBuilder::createOMPAlloc(const LocationDescription &Loc, Value *Size, Value *Allocator, std::string Name) { IRBuilder<>::InsertPointGuard IPG(Builder); - Builder.restoreIP(Loc.IP); + updateToLocation(Loc); uint32_t SrcLocStrSize; Constant *SrcLocStr = getOrCreateSrcLocStr(Loc, SrcLocStrSize); @@ -4418,7 +4418,7 @@ CallInst *OpenMPIRBuilder::createOMPFree(const LocationDescription &Loc, Value *Addr, Value *Allocator, std::string Name) { IRBuilder<>::InsertPointGuard IPG(Builder); - Builder.restoreIP(Loc.IP); + updateToLocation(Loc); uint32_t SrcLocStrSize; Constant *SrcLocStr = getOrCreateSrcLocStr(Loc, SrcLocStrSize); @@ -4434,7 +4434,7 @@ CallInst *OpenMPIRBuilder::createOMPInteropInit( omp::OMPInteropType InteropType, Value *Device, Value *NumDependences, Value *DependenceAddress, bool HaveNowaitClause) { IRBuilder<>::InsertPointGuard IPG(Builder); - Builder.restoreIP(Loc.IP); + updateToLocation(Loc); uint32_t SrcLocStrSize; Constant *SrcLocStr = getOrCreateSrcLocStr(Loc, SrcLocStrSize); @@ -4462,7 +4462,7 @@ CallInst *OpenMPIRBuilder::createOMPInteropDestroy( const LocationDescription &Loc, Value *InteropVar, Value *Device, Value *NumDependences, Value *DependenceAddress, bool HaveNowaitClause) { IRBuilder<>::InsertPointGuard IPG(Builder); - Builder.restoreIP(Loc.IP); + updateToLocation(Loc); uint32_t SrcLocStrSize; Constant *SrcLocStr = getOrCreateSrcLocStr(Loc, SrcLocStrSize); @@ -4491,7 +4491,7 @@ CallInst *OpenMPIRBuilder::createOMPInteropUse(const LocationDescription &Loc, Value *DependenceAddress, bool HaveNowaitClause) { IRBuilder<>::InsertPointGuard IPG(Builder); - Builder.restoreIP(Loc.IP); + updateToLocation(Loc); uint32_t SrcLocStrSize; Constant *SrcLocStr = getOrCreateSrcLocStr(Loc, SrcLocStrSize); Value *Ident = getOrCreateIdent(SrcLocStr, SrcLocStrSize); @@ -4517,7 +4517,7 @@ CallInst *OpenMPIRBuilder::createCachedThreadPrivate( const LocationDescription &Loc, llvm::Value *Pointer, llvm::ConstantInt *Size, const llvm::Twine &Name) { IRBuilder<>::InsertPointGuard IPG(Builder); - Builder.restoreIP(Loc.IP); + updateToLocation(Loc); uint32_t SrcLocStrSize; Constant *SrcLocStr = getOrCreateSrcLocStr(Loc, SrcLocStrSize); -- GitLab From fc57f88f007497a4ead0ec8607ac66e1847b02d6 Mon Sep 17 00:00:00 2001 From: cor3ntin Date: Fri, 10 May 2024 11:15:26 +0200 Subject: [PATCH 243/328] [Clang] Fix Undefined Behavior introduced by #91199 (#91718) We stack allocated an OpaqueExpr that would be used after it was destroyed. e.g https://lab.llvm.org/buildbot/#/builders/57/builds/34909 --- clang/lib/Sema/SemaExprCXX.cpp | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index ae844bc69914..c181092113e1 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -5627,10 +5627,9 @@ static bool EvaluateUnaryTypeTrait(Sema &Self, TypeTrait UTT, static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceInfo *Lhs, const TypeSourceInfo *Rhs, SourceLocation KeyLoc); -static ExprResult CheckConvertibilityForTypeTraits(Sema &Self, - const TypeSourceInfo *Lhs, - const TypeSourceInfo *Rhs, - SourceLocation KeyLoc) { +static ExprResult CheckConvertibilityForTypeTraits( + Sema &Self, const TypeSourceInfo *Lhs, const TypeSourceInfo *Rhs, + SourceLocation KeyLoc, llvm::BumpPtrAllocator &OpaqueExprAllocator) { QualType LhsT = Lhs->getType(); QualType RhsT = Rhs->getType(); @@ -5675,9 +5674,9 @@ static ExprResult CheckConvertibilityForTypeTraits(Sema &Self, // Build a fake source and destination for initialization. InitializedEntity To(InitializedEntity::InitializeTemporary(RhsT)); - OpaqueValueExpr From(KeyLoc, LhsT.getNonLValueExprType(Self.Context), - Expr::getValueKindForType(LhsT)); - Expr *FromPtr = &From; + Expr *From = new (OpaqueExprAllocator.Allocate()) + OpaqueValueExpr(KeyLoc, LhsT.getNonLValueExprType(Self.Context), + Expr::getValueKindForType(LhsT)); InitializationKind Kind = InitializationKind::CreateCopy(KeyLoc, SourceLocation()); @@ -5687,11 +5686,11 @@ static ExprResult CheckConvertibilityForTypeTraits(Sema &Self, Self, Sema::ExpressionEvaluationContext::Unevaluated); Sema::SFINAETrap SFINAE(Self, /*AccessCheckingSFINAE=*/true); Sema::ContextRAII TUContext(Self, Self.Context.getTranslationUnitDecl()); - InitializationSequence Init(Self, To, Kind, FromPtr); + InitializationSequence Init(Self, To, Kind, From); if (Init.Failed()) return ExprError(); - ExprResult Result = Init.Perform(Self, To, Kind, FromPtr); + ExprResult Result = Init.Perform(Self, To, Kind, From); if (Result.isInvalid() || SFINAE.hasErrorOccurred()) return ExprError(); @@ -5819,7 +5818,8 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, S.Context.getPointerType(T.getNonReferenceType())); TypeSourceInfo *UPtr = S.Context.CreateTypeSourceInfo( S.Context.getPointerType(U.getNonReferenceType())); - return !CheckConvertibilityForTypeTraits(S, UPtr, TPtr, RParenLoc) + return !CheckConvertibilityForTypeTraits(S, UPtr, TPtr, RParenLoc, + OpaqueExprAllocator) .isInvalid(); } @@ -6028,9 +6028,9 @@ static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceI case BTT_IsNothrowConvertible: { if (RhsT->isVoidType()) return LhsT->isVoidType(); - - ExprResult Result = - CheckConvertibilityForTypeTraits(Self, Lhs, Rhs, KeyLoc); + llvm::BumpPtrAllocator OpaqueExprAllocator; + ExprResult Result = CheckConvertibilityForTypeTraits(Self, Lhs, Rhs, KeyLoc, + OpaqueExprAllocator); if (Result.isInvalid()) return false; -- GitLab From 1aca8ed5a7eeed264fdc2694deca8a4a4dba3689 Mon Sep 17 00:00:00 2001 From: David Spickett Date: Fri, 10 May 2024 09:25:03 +0000 Subject: [PATCH 244/328] [lldb][ELF] Add a comment to explain address class map type It was pointed out that ordering is crucial here, so note that. I also looked into using a vector instead, as described in https://llvm.org/docs/ProgrammersManual.html#dss-sortedvectorset. Which this is in theory perfect for, but we have at least 2 places that update the map and both would need to sort/unique each time. Plus this code is pretty bug prone. If there is future refactoring it's one thing to consider. --- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h index 716bbe01638f..844e981b1d89 100644 --- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h +++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h @@ -187,6 +187,9 @@ private: typedef DynamicSymbolColl::iterator DynamicSymbolCollIter; typedef DynamicSymbolColl::const_iterator DynamicSymbolCollConstIter; + /// An ordered map of file address to address class. Used on architectures + /// like Arm where there is an alternative ISA mode like Thumb. The container + /// is ordered so that it can be binary searched. typedef std::map FileAddressToAddressClassMap; -- GitLab From b277bf56d7654877a1c4b59dc08bc96b4d75b649 Mon Sep 17 00:00:00 2001 From: Paul Walker Date: Fri, 10 May 2024 10:53:57 +0100 Subject: [PATCH 245/328] [LLVM][CodeGen][SVE] Clean up lowering of VECTOR_SPLICE operations. (#91330) Remove DAG combine that is performing type legalisation and instead add isel patterns for all legal types. --- .../SelectionDAG/SelectionDAGBuilder.cpp | 3 +- .../Target/AArch64/AArch64ISelLowering.cpp | 38 ++----- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 23 ++-- llvm/lib/Target/AArch64/SVEInstrFormats.td | 17 +-- .../AArch64/named-vector-shuffles-sve.ll | 104 ++++++++++++++++++ 5 files changed, 136 insertions(+), 49 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index eac4297b89b5..b76036a22992 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -12240,9 +12240,8 @@ void SelectionDAGBuilder::visitVectorSplice(const CallInst &I) { // VECTOR_SHUFFLE doesn't support a scalable mask so use a dedicated node. if (VT.isScalableVector()) { - MVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout()); setValue(&I, DAG.getNode(ISD::VECTOR_SPLICE, DL, VT, V1, V2, - DAG.getConstant(Imm, DL, IdxVT))); + DAG.getVectorIdxConstant(Imm, DL))); return; } diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 7344387ffe55..29b66a72d21d 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1048,9 +1048,9 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); setTargetDAGCombine({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND, - ISD::VECTOR_SPLICE, ISD::SIGN_EXTEND_INREG, - ISD::CONCAT_VECTORS, ISD::EXTRACT_SUBVECTOR, - ISD::INSERT_SUBVECTOR, ISD::STORE, ISD::BUILD_VECTOR}); + ISD::SIGN_EXTEND_INREG, ISD::CONCAT_VECTORS, + ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, + ISD::STORE, ISD::BUILD_VECTOR}); setTargetDAGCombine(ISD::TRUNCATE); setTargetDAGCombine(ISD::LOAD); @@ -1580,6 +1580,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setOperationAction(ISD::MLOAD, VT, Custom); setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); + setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); if (!Subtarget->isLittleEndian()) setOperationAction(ISD::BITCAST, VT, Expand); @@ -10102,10 +10103,9 @@ SDValue AArch64TargetLowering::LowerVECTOR_SPLICE(SDValue Op, Op.getOperand(1)); } - // This will select to an EXT instruction, which has a maximum immediate - // value of 255, hence 2048-bits is the maximum value we can lower. - if (IdxVal >= 0 && - IdxVal < int64_t(2048 / Ty.getVectorElementType().getSizeInBits())) + // We can select to an EXT instruction when indexing the first 256 bytes. + unsigned BlockSize = AArch64::SVEBitsPerBlock / Ty.getVectorMinNumElements(); + if (IdxVal >= 0 && (IdxVal * BlockSize / 8) < 256) return Op; return SDValue(); @@ -24255,28 +24255,6 @@ performInsertVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { return performPostLD1Combine(N, DCI, true); } -static SDValue performSVESpliceCombine(SDNode *N, SelectionDAG &DAG) { - EVT Ty = N->getValueType(0); - if (Ty.isInteger()) - return SDValue(); - - EVT IntTy = Ty.changeVectorElementTypeToInteger(); - EVT ExtIntTy = getPackedSVEVectorVT(IntTy.getVectorElementCount()); - if (ExtIntTy.getVectorElementType().getScalarSizeInBits() < - IntTy.getVectorElementType().getScalarSizeInBits()) - return SDValue(); - - SDLoc DL(N); - SDValue LHS = DAG.getAnyExtOrTrunc(DAG.getBitcast(IntTy, N->getOperand(0)), - DL, ExtIntTy); - SDValue RHS = DAG.getAnyExtOrTrunc(DAG.getBitcast(IntTy, N->getOperand(1)), - DL, ExtIntTy); - SDValue Idx = N->getOperand(2); - SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, ExtIntTy, LHS, RHS, Idx); - SDValue Trunc = DAG.getAnyExtOrTrunc(Splice, DL, IntTy); - return DAG.getBitcast(Ty, Trunc); -} - static SDValue performFPExtendCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) { @@ -24661,8 +24639,6 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N, case ISD::MGATHER: case ISD::MSCATTER: return performMaskedGatherScatterCombine(N, DCI, DAG); - case ISD::VECTOR_SPLICE: - return performSVESpliceCombine(N, DAG); case ISD::FP_EXTEND: return performFPExtendCombine(N, DAG, DCI, Subtarget); case AArch64ISD::BRCOND: diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 62e68de1359f..64e545aa26b4 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1994,14 +1994,21 @@ let Predicates = [HasSVEorSME] in { (LASTB_VPZ_D (PTRUE_D 31), ZPR:$Z1), dsub))>; // Splice with lane bigger or equal to 0 - def : Pat<(nxv16i8 (vector_splice (nxv16i8 ZPR:$Z1), (nxv16i8 ZPR:$Z2), (i64 (sve_ext_imm_0_255 i32:$index)))), - (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; - def : Pat<(nxv8i16 (vector_splice (nxv8i16 ZPR:$Z1), (nxv8i16 ZPR:$Z2), (i64 (sve_ext_imm_0_127 i32:$index)))), - (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; - def : Pat<(nxv4i32 (vector_splice (nxv4i32 ZPR:$Z1), (nxv4i32 ZPR:$Z2), (i64 (sve_ext_imm_0_63 i32:$index)))), - (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; - def : Pat<(nxv2i64 (vector_splice (nxv2i64 ZPR:$Z1), (nxv2i64 ZPR:$Z2), (i64 (sve_ext_imm_0_31 i32:$index)))), - (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; + foreach VT = [nxv16i8] in + def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_255 i32:$index)))), + (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; + + foreach VT = [nxv8i16, nxv8f16, nxv8bf16] in + def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_127 i32:$index)))), + (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; + + foreach VT = [nxv4i32, nxv4f16, nxv4f32, nxv4bf16] in + def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_63 i32:$index)))), + (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; + + foreach VT = [nxv2i64, nxv2f16, nxv2f32, nxv2f64, nxv2bf16] in + def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_31 i32:$index)))), + (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs", SETUGE, SETULE>; defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi", SETUGT, SETULT>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 69c3238c7d61..fc7d3cdda4ac 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -7060,16 +7060,17 @@ multiclass sve_int_perm_splice { def _S : sve_int_perm_splice<0b10, asm, ZPR32>; def _D : sve_int_perm_splice<0b11, asm, ZPR64>; - def : SVE_3_Op_Pat(NAME # _B)>; - def : SVE_3_Op_Pat(NAME # _H)>; - def : SVE_3_Op_Pat(NAME # _S)>; - def : SVE_3_Op_Pat(NAME # _D)>; + foreach VT = [nxv16i8] in + def : SVE_3_Op_Pat(NAME # _B)>; - def : SVE_3_Op_Pat(NAME # _H)>; - def : SVE_3_Op_Pat(NAME # _S)>; - def : SVE_3_Op_Pat(NAME # _D)>; + foreach VT = [nxv8i16, nxv8f16, nxv8bf16] in + def : SVE_3_Op_Pat(NAME # _H)>; - def : SVE_3_Op_Pat(NAME # _H)>; + foreach VT = [nxv4i32, nxv4f16, nxv4f32, nxv4bf16] in + def : SVE_3_Op_Pat(NAME # _S)>; + + foreach VT = [nxv2i64, nxv2f16, nxv2f32, nxv2f64, nxv2bf16] in + def : SVE_3_Op_Pat(NAME # _D)>; } class sve2_int_perm_splice_cons sz8_64, string asm, diff --git a/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll b/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll index f5763cd61033..d1171bc31247 100644 --- a/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll +++ b/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll @@ -692,6 +692,104 @@ define @splice_nxv2f64_neg3( %a, %res } +define @splice_nxv2bf16_neg_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv2bf16_neg_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d, vl1 +; CHECK-NEXT: rev p0.d, p0.d +; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv2bf16( %a, %b, i32 -1) + ret %res +} + +define @splice_nxv2bf16_neg2_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv2bf16_neg2_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: rev p0.d, p0.d +; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv2bf16( %a, %b, i32 -2) + ret %res +} + +define @splice_nxv2bf16_first_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv2bf16_first_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8 +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv2bf16( %a, %b, i32 1) + ret %res +} + +define @splice_nxv2bf16_last_idx( %a, %b) vscale_range(16,16) #0 { +; CHECK-LABEL: splice_nxv2bf16_last_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ext z0.b, z0.b, z1.b, #248 +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv2bf16( %a, %b, i32 31) + ret %res +} + +define @splice_nxv4bf16_neg_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv4bf16_neg_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s, vl1 +; CHECK-NEXT: rev p0.s, p0.s +; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv4bf16( %a, %b, i32 -1) + ret %res +} + +define @splice_nxv4bf16_neg3_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv4bf16_neg3_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s, vl3 +; CHECK-NEXT: rev p0.s, p0.s +; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv4bf16( %a, %b, i32 -3) + ret %res +} + +define @splice_nxv4bf16_first_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv4bf16_first_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4 +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv4bf16( %a, %b, i32 1) + ret %res +} + +define @splice_nxv4bf16_last_idx( %a, %b) vscale_range(16,16) #0 { +; CHECK-LABEL: splice_nxv4bf16_last_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ext z0.b, z0.b, z1.b, #252 +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv4bf16( %a, %b, i32 63) + ret %res +} + +define @splice_nxv8bf16_first_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv8bf16_first_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ext z0.b, z0.b, z1.b, #2 +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv8bf16( %a, %b, i32 1) + ret %res +} + +define @splice_nxv8bf16_last_idx( %a, %b) vscale_range(16,16) #0 { +; CHECK-LABEL: splice_nxv8bf16_last_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ext z0.b, z0.b, z1.b, #254 +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv8bf16( %a, %b, i32 127) + ret %res +} + ; Ensure predicate based splice is promoted to use ZPRs. define @splice_nxv2i1( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i1: @@ -834,12 +932,14 @@ declare @llvm.vector.splice.nxv2i1(, @llvm.vector.splice.nxv4i1(, , i32) declare @llvm.vector.splice.nxv8i1(, , i32) declare @llvm.vector.splice.nxv16i1(, , i32) + declare @llvm.vector.splice.nxv2i8(, , i32) declare @llvm.vector.splice.nxv16i8(, , i32) declare @llvm.vector.splice.nxv8i16(, , i32) declare @llvm.vector.splice.nxv4i32(, , i32) declare @llvm.vector.splice.nxv8i32(, , i32) declare @llvm.vector.splice.nxv2i64(, , i32) + declare @llvm.vector.splice.nxv2f16(, , i32) declare @llvm.vector.splice.nxv4f16(, , i32) declare @llvm.vector.splice.nxv8f16(, , i32) @@ -848,4 +948,8 @@ declare @llvm.vector.splice.nxv4f32(, < declare @llvm.vector.splice.nxv16f32(, , i32) declare @llvm.vector.splice.nxv2f64(, , i32) +declare @llvm.vector.splice.nxv2bf16(, , i32) +declare @llvm.vector.splice.nxv4bf16(, , i32) +declare @llvm.vector.splice.nxv8bf16(, , i32) + attributes #0 = { nounwind "target-features"="+sve" } -- GitLab From 64d4ade3bb7d0d8cc87a777f4964e68f2f25edf9 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Fri, 10 May 2024 11:14:26 +0100 Subject: [PATCH 246/328] [AArch64] Add intrinsics for 16-bit non-widening FMLA/FMLS (#88553) According to the specification in https://github.com/ARM-software/acle/pull/309 add the following intrinsics void svmla[_single]_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) void svmla[_single]_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) void svmls[_single]_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) void svmls[_single]_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) void svmla_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16x2_t zm) void svmla_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16x4_t zm) void svmls_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16x2_t zm) void svmls_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16x4_t zm) void svmla_lane_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm, uint64_t imm_idx) void svmla_lane_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm, uint64_t imm_idx) void svmls_lane_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm, uint64_t imm_idx) void svmls_lane_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm, uint64_t imm_idx) as well as the corresponding `_bf16` variants. --- clang/include/clang/Basic/arm_sme.td | 34 + .../acle_sme2_fmlas16.c | 592 ++++++++++++++++++ .../acle_sme2_fmlas16.c | 90 +++ .../lib/Target/AArch64/AArch64SMEInstrInfo.td | 59 +- llvm/lib/Target/AArch64/SMEInstrFormats.td | 54 +- .../AArch64/sme2-intrinsics-fmlas16.ll | 462 ++++++++++++++ 6 files changed, 1254 insertions(+), 37 deletions(-) create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c create mode 100644 clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c create mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas16.ll diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index 1ac6d5170ea2..77ea53fb83fa 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -458,6 +458,40 @@ let TargetGuard = "sme2,sme-f64f64" in { def SVMLS_LANE_VG1x4_F64 : Inst<"svmls_lane_za64[_{d}]_vg1x4", "vm4di", "d", MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; } +let TargetGuard = "sme-f16f16" in { + def SVMLA_MULTI_VG1x2_F16 : Inst<"svmla_za16[_f16]_vg1x2", "vm22", "h", MergeNone, "aarch64_sme_fmla_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLA_MULTI_VG1x4_F16 : Inst<"svmla_za16[_f16]_vg1x4", "vm44", "h", MergeNone, "aarch64_sme_fmla_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVMLS_MULTI_VG1x2_F16 : Inst<"svmls_za16[_f16]_vg1x2", "vm22", "h", MergeNone, "aarch64_sme_fmls_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLS_MULTI_VG1x4_F16 : Inst<"svmls_za16[_f16]_vg1x4", "vm44", "h", MergeNone, "aarch64_sme_fmls_vg1x4", [IsStreaming, IsInOutZA], []>; + + def SVMLA_SINGLE_VG1x2_F16 : Inst<"svmla[_single]_za16[_f16]_vg1x2", "vm2d", "h", MergeNone, "aarch64_sme_fmla_single_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLA_SINGLE_VG1x4_F16 : Inst<"svmla[_single]_za16[_f16]_vg1x4", "vm4d", "h", MergeNone, "aarch64_sme_fmla_single_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVMLS_SINGLE_VG1x2_F16 : Inst<"svmls[_single]_za16[_f16]_vg1x2", "vm2d", "h", MergeNone, "aarch64_sme_fmls_single_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLS_SINGLE_VG1x4_F16 : Inst<"svmls[_single]_za16[_f16]_vg1x4", "vm4d", "h", MergeNone, "aarch64_sme_fmls_single_vg1x4", [IsStreaming, IsInOutZA], []>; + + def SVMLA_LANE_VG1x2_F16 : Inst<"svmla_lane_za16[_f16]_vg1x2", "vm2di", "h", MergeNone, "aarch64_sme_fmla_lane_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLA_LANE_VG1x4_F16 : Inst<"svmla_lane_za16[_f16]_vg1x4", "vm4di", "h", MergeNone, "aarch64_sme_fmla_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLS_LANE_VG1x2_F16 : Inst<"svmls_lane_za16[_f16]_vg1x2", "vm2di", "h", MergeNone, "aarch64_sme_fmls_lane_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLS_LANE_VG1x4_F16 : Inst<"svmls_lane_za16[_f16]_vg1x4", "vm4di", "h", MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; +} + +let TargetGuard = "sme2,b16b16" in { + def SVMLA_MULTI_VG1x2_BF16 : Inst<"svmla_za16[_bf16]_vg1x2", "vm22", "b", MergeNone, "aarch64_sme_fmla_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLA_MULTI_VG1x4_BF16 : Inst<"svmla_za16[_bf16]_vg1x4", "vm44", "b", MergeNone, "aarch64_sme_fmla_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVMLS_MULTI_VG1x2_BF16 : Inst<"svmls_za16[_bf16]_vg1x2", "vm22", "b", MergeNone, "aarch64_sme_fmls_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLS_MULTI_VG1x4_BF16 : Inst<"svmls_za16[_bf16]_vg1x4", "vm44", "b", MergeNone, "aarch64_sme_fmls_vg1x4", [IsStreaming, IsInOutZA], []>; + + def SVMLA_SINGLE_VG1x2_BF16 : Inst<"svmla[_single]_za16[_bf16]_vg1x2", "vm2d", "b", MergeNone, "aarch64_sme_fmla_single_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLA_SINGLE_VG1x4_BF16 : Inst<"svmla[_single]_za16[_bf16]_vg1x4", "vm4d", "b", MergeNone, "aarch64_sme_fmla_single_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVMLS_SINGLE_VG1x2_BF16 : Inst<"svmls[_single]_za16[_bf16]_vg1x2", "vm2d", "b", MergeNone, "aarch64_sme_fmls_single_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLS_SINGLE_VG1x4_BF16 : Inst<"svmls[_single]_za16[_bf16]_vg1x4", "vm4d", "b", MergeNone, "aarch64_sme_fmls_single_vg1x4", [IsStreaming, IsInOutZA], []>; + + def SVMLA_LANE_VG1x2_BF16 : Inst<"svmla_lane_za16[_bf16]_vg1x2", "vm2di", "b", MergeNone, "aarch64_sme_fmla_lane_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLA_LANE_VG1x4_BF16 : Inst<"svmla_lane_za16[_bf16]_vg1x4", "vm4di", "b", MergeNone, "aarch64_sme_fmla_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLS_LANE_VG1x2_BF16 : Inst<"svmls_lane_za16[_bf16]_vg1x2", "vm2di", "b", MergeNone, "aarch64_sme_fmls_lane_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLS_LANE_VG1x4_BF16 : Inst<"svmls_lane_za16[_bf16]_vg1x4", "vm4di", "b", MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; +} + // FMLAL/FMLSL/UMLAL/SMLAL // SMLALL/UMLALL/USMLALL/SUMLALL let TargetGuard = "sme2" in { diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c new file mode 100644 index 000000000000..ecc415545414 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c @@ -0,0 +1,592 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -Werror -Wall -emit-llvm -o - %s | FileCheck %s --check-prefix CHECK-CXX +// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -Werror -Wall -emit-llvm -o - %s | FileCheck %s --check-prefix CHECK-CXX + +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall %s -o /dev/null + +// REQUIRES: aarch64-registered-target +#include + +#ifdef SME_OVERLOADED_FORMS +#define SME_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED, A5) A1##A3##A5 +#else +#define SME_ACLE_FUNC(A1, A2, A3, A4, A5) A1##A2##A3##A4##A5 +#endif + +// CHECK-LABEL: define dso_local void @test_svmla_single_za16_f16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z32test_svmla_single_za16_f16_vg1x2j13svfloat16x2_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_single_za16_f16_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla,_single,_za16,_f16,_vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_single_za16_f16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z32test_svmla_single_za16_f16_vg1x4j13svfloat16x4_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_single_za16_f16_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla,_single,_za16,_f16,_vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_single_za16_f16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z32test_svmls_single_za16_f16_vg1x2j13svfloat16x2_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_single_za16_f16_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls,_single,_za16,_f16,_vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_single_za16_f16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z32test_svmls_single_za16_f16_vg1x4j13svfloat16x4_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_single_za16_f16_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls,_single,_za16,_f16,_vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_za16_f16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z25test_svmla_za16_f16_vg1x2j13svfloat16x2_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_za16_f16_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16x2_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla,,_za16,_f16,_vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_za16_f16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 8) +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z25test_svmla_za16_f16_vg1x4j13svfloat16x4_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 16) +// CHECK-CXX-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_za16_f16_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16x4_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla,,_za16,_f16,_vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_za16_f16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z25test_svmls_za16_f16_vg1x2j13svfloat16x2_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_za16_f16_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16x2_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls,,_za16,_f16,_vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_za16_f16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 8) +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z25test_svmls_za16_f16_vg1x4j13svfloat16x4_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 16) +// CHECK-CXX-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_za16_f16_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16x4_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls,,_za16,_f16,_vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_f16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z30test_svmla_lane_za16_f16_vg1x2j13svfloat16x2_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_lane_za16_f16_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla_lane,,_za16,_f16,_vg1x2)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_f16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z30test_svmla_lane_za16_f16_vg1x4j13svfloat16x4_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_lane_za16_f16_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla_lane,,_za16,_f16,_vg1x4)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmls_lane_za16_f16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z30test_svmls_lane_za16_f16_vg1x2j13svfloat16x2_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_lane_za16_f16_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls_lane,,_za16,_f16,_vg1x2)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmls_lane_za16_f16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z30test_svmls_lane_za16_f16_vg1x4j13svfloat16x4_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_lane_za16_f16_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls_lane,,_za16,_f16,_vg1x4)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmla_single_za16_bf16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z33test_svmla_single_za16_bf16_vg1x2j14svbfloat16x2_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_single_za16_bf16_vg1x2(uint32_t slice, svbfloat16x2_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla, _single, _za16, _bf16, _vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_single_za16_bf16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z33test_svmla_single_za16_bf16_vg1x4j14svbfloat16x4_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_single_za16_bf16_vg1x4(uint32_t slice, svbfloat16x4_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla, _single, _za16, _bf16, _vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_single_za16_bf16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z33test_svmls_single_za16_bf16_vg1x2j14svbfloat16x2_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_single_za16_bf16_vg1x2(uint32_t slice, svbfloat16x2_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls, _single, _za16, _bf16, _vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_single_za16_bf16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z33test_svmls_single_za16_bf16_vg1x4j14svbfloat16x4_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_single_za16_bf16_vg1x4(uint32_t slice, svbfloat16x4_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls, _single, _za16, _bf16, _vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_za16_bf16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svmla_za16_bf16_vg1x2j14svbfloat16x2_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_za16_bf16_vg1x2(uint32_t slice, svbfloat16x2_t zn, svbfloat16x2_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla, , _za16, _bf16, _vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_za16_bf16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 8) +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svmla_za16_bf16_vg1x4j14svbfloat16x4_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 16) +// CHECK-CXX-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_za16_bf16_vg1x4(uint32_t slice, svbfloat16x4_t zn, svbfloat16x4_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla, , _za16, _bf16, _vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_za16_bf16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svmls_za16_bf16_vg1x2j14svbfloat16x2_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_za16_bf16_vg1x2(uint32_t slice, svbfloat16x2_t zn, svbfloat16x2_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls, , _za16, _bf16, _vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_za16_bf16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 8) +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svmls_za16_bf16_vg1x4j14svbfloat16x4_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 16) +// CHECK-CXX-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_za16_bf16_vg1x4(uint32_t slice, svbfloat16x4_t zn, svbfloat16x4_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls, , _za16, _bf16, _vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_bf16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z31test_svmla_lane_za16_bf16_vg1x2j14svbfloat16x2_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_lane_za16_bf16_vg1x2(uint32_t slice, svbfloat16x2_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla_lane, , _za16, _bf16, _vg1x2)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_bf16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z31test_svmla_lane_za16_bf16_vg1x4j14svbfloat16x4_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_lane_za16_bf16_vg1x4(uint32_t slice, svbfloat16x4_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla_lane, , _za16, _bf16, _vg1x4)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmls_lane_za16_bf16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z31test_svmls_lane_za16_bf16_vg1x2j14svbfloat16x2_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_lane_za16_bf16_vg1x2(uint32_t slice, svbfloat16x2_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls_lane, , _za16, _bf16, _vg1x2)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmls_lane_za16_bf16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z31test_svmls_lane_za16_bf16_vg1x4j14svbfloat16x4_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_lane_za16_bf16_vg1x4(uint32_t slice, svbfloat16x4_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls_lane, , _za16, _bf16, _vg1x4)(slice, zn, zm, 7); +} diff --git a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c new file mode 100644 index 000000000000..b1582569971d --- /dev/null +++ b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c @@ -0,0 +1,90 @@ +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -verify -emit-llvm %s + +// REQUIRES: aarch64-registered-target + +#include + + +void test_features_f16f16(uint32_t slice, + svfloat16_t zm, + svfloat16x2_t zn2, svfloat16x2_t zm2, + svfloat16x4_t zn4, svfloat16x4_t zm4, + svbfloat16_t bzm, + svbfloat16x2_t bzn2, svbfloat16x2_t bzm2, + svbfloat16x4_t bzn4, svbfloat16x4_t bzm4) + + __arm_streaming __arm_inout("za") { + // expected-error@+1 {{'svmla_single_za16_f16_vg1x2' needs target feature sme-f16f16}} + svmla_single_za16_f16_vg1x2(slice, zn2, zm); + // expected-error@+1 {{'svmla_single_za16_f16_vg1x4' needs target feature sme-f16f16}} + svmla_single_za16_f16_vg1x4(slice, zn4, zm); + // expected-error@+1 {{'svmls_single_za16_f16_vg1x2' needs target feature sme-f16f16}} + svmls_single_za16_f16_vg1x2(slice, zn2, zm); + // expected-error@+1 {{'svmls_single_za16_f16_vg1x4' needs target feature sme-f16f16}} + svmls_single_za16_f16_vg1x4(slice, zn4, zm); + // expected-error@+1 {{'svmla_za16_f16_vg1x2' needs target feature sme-f16f16}} + svmla_za16_f16_vg1x2(slice, zn2, zm2); + // expected-error@+1 {{'svmla_za16_f16_vg1x4' needs target feature sme-f16f16}} + svmla_za16_f16_vg1x4(slice, zn4, zm4); + // expected-error@+1 {{'svmls_za16_f16_vg1x2' needs target feature sme-f16f16}} + svmls_za16_f16_vg1x2(slice, zn2, zm2); + // expected-error@+1 {{'svmls_za16_f16_vg1x4' needs target feature sme-f16f16}} + svmls_za16_f16_vg1x4(slice, zn4, zm4); + // expected-error@+1 {{'svmla_lane_za16_f16_vg1x2' needs target feature sme-f16f16}} + svmla_lane_za16_f16_vg1x2(slice, zn2, zm, 7); + // expected-error@+1 {{'svmla_lane_za16_f16_vg1x4' needs target feature sme-f16f16}} + svmla_lane_za16_f16_vg1x4(slice, zn4, zm, 7); + // expected-error@+1 {{'svmls_lane_za16_f16_vg1x2' needs target feature sme-f16f16}} + svmls_lane_za16_f16_vg1x2(slice, zn2, zm, 7); + // expected-error@+1 {{'svmls_lane_za16_f16_vg1x4' needs target feature sme-f16f16}} + svmls_lane_za16_f16_vg1x4(slice, zn4, zm, 7); + + // expected-error@+1 {{'svmla_single_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svmla_single_za16_bf16_vg1x2(slice, bzn2, bzm); + // expected-error@+1 {{'svmla_single_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svmla_single_za16_bf16_vg1x4(slice, bzn4, bzm); + // expected-error@+1 {{'svmls_single_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svmls_single_za16_bf16_vg1x2(slice, bzn2, bzm); + // expected-error@+1 {{'svmls_single_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svmls_single_za16_bf16_vg1x4(slice, bzn4, bzm); + // expected-error@+1 {{'svmla_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svmla_za16_bf16_vg1x2(slice, bzn2, bzm2); + // expected-error@+1 {{'svmla_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svmla_za16_bf16_vg1x4(slice, bzn4, bzm4); + // expected-error@+1 {{'svmls_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svmls_za16_bf16_vg1x2(slice, bzn2, bzm2); + // expected-error@+1 {{'svmls_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svmls_za16_bf16_vg1x4(slice, bzn4, bzm4); + // expected-error@+1 {{'svmla_lane_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svmla_lane_za16_bf16_vg1x2(slice, bzn2, bzm, 7); + // expected-error@+1 {{'svmla_lane_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svmla_lane_za16_bf16_vg1x4(slice, bzn4, bzm, 7); + // expected-error@+1 {{'svmls_lane_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svmls_lane_za16_bf16_vg1x2(slice, bzn2, bzm, 7); + // expected-error@+1 {{'svmls_lane_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svmls_lane_za16_bf16_vg1x4(slice, bzn4, bzm, 7); +} + + +void test_imm(uint32_t slice, svfloat16_t zm, svfloat16x2_t zn2,svfloat16x4_t zn4, + svbfloat16_t bzm, svbfloat16x2_t bzn2, svbfloat16x4_t bzn4) + __arm_streaming __arm_inout("za") { + + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmla_lane_za16_f16_vg1x2(slice, zn2, zm, -1); + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmla_lane_za16_f16_vg1x4(slice, zn4, zm, -1); + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmls_lane_za16_f16_vg1x2(slice, zn2, zm, -1); + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmls_lane_za16_f16_vg1x4(slice, zn4, zm, -1); + + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmla_lane_za16_bf16_vg1x2(slice, bzn2, bzm, -1); + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmla_lane_za16_bf16_vg1x4(slice, bzn4, bzm, -1); + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmls_lane_za16_bf16_vg1x2(slice, bzn2, bzm, -1); + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmls_lane_za16_bf16_vg1x4(slice, bzn4, bzm, -1); +} \ No newline at end of file diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index 574178c8d524..a2e8c530c1df 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -797,22 +797,20 @@ defm FADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fadd", 0b0100, MatrixOp16 defm FADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fadd", 0b0100, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; defm FSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fsub", 0b0101, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>; defm FSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fsub", 0b0101, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; -} -let Predicates = [HasSMEF16F16] in { -defm FMLA_VG2_M2ZZI_H : sme2p1_multi_vec_array_vg2_index_16b<"fmla", 0b00, 0b100, ZZ_h_mul_r, ZPR4b16>; -defm FMLA_VG4_M4ZZI_H : sme2p1_multi_vec_array_vg4_index_16b<"fmla", 0b000, ZZZZ_h_mul_r, ZPR4b16>; -defm FMLA_VG2_M2ZZ_H : sme2_dot_mla_add_sub_array_vg24_single<"fmla", 0b0011100, MatrixOp16, ZZ_h, ZPR4b16>; -defm FMLA_VG4_M4ZZ_H : sme2_dot_mla_add_sub_array_vg24_single<"fmla", 0b0111100, MatrixOp16, ZZZZ_h, ZPR4b16>; -defm FMLA_VG2_M2Z4Z_H : sme2_dot_mla_add_sub_array_vg2_multi<"fmla", 0b0100001, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>; -defm FMLA_VG4_M4Z4Z_H : sme2_dot_mla_add_sub_array_vg4_multi<"fmla", 0b0100001, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; - -defm FMLS_VG2_M2ZZI_H : sme2p1_multi_vec_array_vg2_index_16b<"fmls", 0b00, 0b101, ZZ_h_mul_r, ZPR4b16>; -defm FMLS_VG4_M4ZZI_H : sme2p1_multi_vec_array_vg4_index_16b<"fmls", 0b001, ZZZZ_h_mul_r, ZPR4b16>; -defm FMLS_VG2_M2ZZ_H : sme2_dot_mla_add_sub_array_vg24_single<"fmls", 0b0011101, MatrixOp16, ZZ_h, ZPR4b16>; -defm FMLS_VG4_M4ZZ_H : sme2_dot_mla_add_sub_array_vg24_single<"fmls", 0b0111101, MatrixOp16, ZZZZ_h, ZPR4b16>; -defm FMLS_VG2_M2Z2Z_H : sme2_dot_mla_add_sub_array_vg2_multi<"fmls", 0b0100011, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>; -defm FMLS_VG4_M4Z2Z_H : sme2_dot_mla_add_sub_array_vg4_multi<"fmls", 0b0100011, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; +defm FMLA_VG2_M2ZZI_H : sme2p1_multi_vec_array_vg2_index_16b<"fmla", 0b00, 0b100, ZZ_h_mul_r, ZPR4b16, nxv8f16, int_aarch64_sme_fmla_lane_vg1x2>; +defm FMLA_VG4_M4ZZI_H : sme2p1_multi_vec_array_vg4_index_16b<"fmla", 0b000, ZZZZ_h_mul_r, ZPR4b16, nxv8f16, int_aarch64_sme_fmla_lane_vg1x4>; +defm FMLA_VG2_M2ZZ_H : sme2_dot_mla_add_sub_array_vg2_single<"fmla", 0b0011100, MatrixOp16, ZZ_h, ZPR4b16, nxv8f16, int_aarch64_sme_fmla_single_vg1x2>; +defm FMLA_VG4_M4ZZ_H : sme2_dot_mla_add_sub_array_vg4_single<"fmla", 0b0111100, MatrixOp16, ZZZZ_h, ZPR4b16, nxv8f16, int_aarch64_sme_fmla_single_vg1x4>; +defm FMLA_VG2_M2Z4Z_H : sme2_dot_mla_add_sub_array_vg2_multi<"fmla", 0b0100001, MatrixOp16, ZZ_h_mul_r, nxv8f16, int_aarch64_sme_fmla_vg1x2>; +defm FMLA_VG4_M4Z4Z_H : sme2_dot_mla_add_sub_array_vg4_multi<"fmla", 0b0100001, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, int_aarch64_sme_fmla_vg1x4>; + +defm FMLS_VG2_M2ZZI_H : sme2p1_multi_vec_array_vg2_index_16b<"fmls", 0b00, 0b101, ZZ_h_mul_r, ZPR4b16, nxv8f16, int_aarch64_sme_fmls_lane_vg1x2>; +defm FMLS_VG4_M4ZZI_H : sme2p1_multi_vec_array_vg4_index_16b<"fmls", 0b001, ZZZZ_h_mul_r, ZPR4b16, nxv8f16, int_aarch64_sme_fmls_lane_vg1x4>; +defm FMLS_VG2_M2ZZ_H : sme2_dot_mla_add_sub_array_vg2_single<"fmls", 0b0011101, MatrixOp16, ZZ_h, ZPR4b16, nxv8f16, int_aarch64_sme_fmls_single_vg1x2>; +defm FMLS_VG4_M4ZZ_H : sme2_dot_mla_add_sub_array_vg4_single<"fmls", 0b0111101, MatrixOp16, ZZZZ_h, ZPR4b16, nxv8f16, int_aarch64_sme_fmls_single_vg1x4>; +defm FMLS_VG2_M2Z2Z_H : sme2_dot_mla_add_sub_array_vg2_multi<"fmls", 0b0100011, MatrixOp16, ZZ_h_mul_r, nxv8f16, int_aarch64_sme_fmls_vg1x2>; +defm FMLS_VG4_M4Z2Z_H : sme2_dot_mla_add_sub_array_vg4_multi<"fmls", 0b0100011, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, int_aarch64_sme_fmls_vg1x4>; defm FCVT_2ZZ_H : sme2p1_fp_cvt_vector_vg2_single<"fcvt", 0b0>; defm FCVTL_2ZZ_H : sme2p1_fp_cvt_vector_vg2_single<"fcvtl", 0b1>; @@ -827,20 +825,19 @@ defm BFADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"bfadd", 0b1100, MatrixOp defm BFSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"bfsub", 0b1101, MatrixOp16, ZZ_h_mul_r, nxv8bf16, null_frag>; defm BFSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"bfsub", 0b1101, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, null_frag>; -defm BFMLA_VG2_M2ZZI : sme2p1_multi_vec_array_vg2_index_16b<"bfmla", 0b00, 0b110, ZZ_h_mul_r, ZPR4b16>; -defm BFMLA_VG4_M4ZZI : sme2p1_multi_vec_array_vg4_index_16b<"bfmla", 0b010, ZZZZ_h_mul_r, ZPR4b16>; -defm BFMLA_VG2_M2ZZ : sme2_dot_mla_add_sub_array_vg24_single<"bfmla", 0b1011100, MatrixOp16, ZZ_h, ZPR4b16>; -defm BFMLA_VG4_M4ZZ : sme2_dot_mla_add_sub_array_vg24_single<"bfmla", 0b1111100, MatrixOp16, ZZZZ_h, ZPR4b16>; -defm BFMLA_VG2_M2Z2Z : sme2_dot_mla_add_sub_array_vg2_multi<"bfmla", 0b1100001, MatrixOp16, ZZ_h_mul_r, nxv8bf16, null_frag>; -defm BFMLA_VG4_M4Z4Z : sme2_dot_mla_add_sub_array_vg4_multi<"bfmla", 0b1100001, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, null_frag>; - -defm BFMLS_VG2_M2ZZI : sme2p1_multi_vec_array_vg2_index_16b<"bfmls", 0b00, 0b111, ZZ_h_mul_r, ZPR4b16>; -defm BFMLS_VG4_M4ZZI : sme2p1_multi_vec_array_vg4_index_16b<"bfmls", 0b011, ZZZZ_h_mul_r, ZPR4b16>; -defm BFMLS_VG2_M2ZZ : sme2_dot_mla_add_sub_array_vg24_single<"bfmls", 0b1011101, MatrixOp16, ZZ_h, ZPR4b16>; -defm BFMLS_VG4_M4ZZ : sme2_dot_mla_add_sub_array_vg24_single<"bfmls", 0b1111101, MatrixOp16, ZZZZ_h, ZPR4b16>; -defm BFMLS_VG2_M2Z2Z : sme2_dot_mla_add_sub_array_vg2_multi<"bfmls", 0b1100011, MatrixOp16, ZZ_h_mul_r, nxv8bf16, null_frag>; -defm BFMLS_VG4_M4Z4Z : sme2_dot_mla_add_sub_array_vg4_multi<"bfmls", 0b1100011, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, null_frag>; +defm BFMLA_VG2_M2ZZI : sme2p1_multi_vec_array_vg2_index_16b<"bfmla", 0b00, 0b110, ZZ_h_mul_r, ZPR4b16, nxv8bf16, int_aarch64_sme_fmla_lane_vg1x2>; +defm BFMLA_VG4_M4ZZI : sme2p1_multi_vec_array_vg4_index_16b<"bfmla", 0b010, ZZZZ_h_mul_r, ZPR4b16, nxv8bf16, int_aarch64_sme_fmla_lane_vg1x4>; +defm BFMLA_VG2_M2ZZ : sme2_dot_mla_add_sub_array_vg2_single<"bfmla", 0b1011100, MatrixOp16, ZZ_h, ZPR4b16, nxv8bf16, int_aarch64_sme_fmla_single_vg1x2>; +defm BFMLA_VG4_M4ZZ : sme2_dot_mla_add_sub_array_vg4_single<"bfmla", 0b1111100, MatrixOp16, ZZZZ_h, ZPR4b16, nxv8bf16, int_aarch64_sme_fmla_single_vg1x4>; +defm BFMLA_VG2_M2Z2Z : sme2_dot_mla_add_sub_array_vg2_multi<"bfmla", 0b1100001, MatrixOp16, ZZ_h_mul_r, nxv8bf16, int_aarch64_sme_fmla_vg1x2>; +defm BFMLA_VG4_M4Z4Z : sme2_dot_mla_add_sub_array_vg4_multi<"bfmla", 0b1100001, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, int_aarch64_sme_fmla_vg1x4>; +defm BFMLS_VG2_M2ZZI : sme2p1_multi_vec_array_vg2_index_16b<"bfmls", 0b00, 0b111, ZZ_h_mul_r, ZPR4b16, nxv8bf16, int_aarch64_sme_fmls_lane_vg1x2>; +defm BFMLS_VG4_M4ZZI : sme2p1_multi_vec_array_vg4_index_16b<"bfmls", 0b011, ZZZZ_h_mul_r, ZPR4b16, nxv8bf16, int_aarch64_sme_fmls_lane_vg1x4>; +defm BFMLS_VG2_M2ZZ : sme2_dot_mla_add_sub_array_vg2_single<"bfmls", 0b1011101, MatrixOp16, ZZ_h, ZPR4b16, nxv8bf16, int_aarch64_sme_fmls_single_vg1x2>; +defm BFMLS_VG4_M4ZZ : sme2_dot_mla_add_sub_array_vg4_single<"bfmls", 0b1111101, MatrixOp16, ZZZZ_h, ZPR4b16, nxv8bf16, int_aarch64_sme_fmls_single_vg1x4>; +defm BFMLS_VG2_M2Z2Z : sme2_dot_mla_add_sub_array_vg2_multi<"bfmls", 0b1100011, MatrixOp16, ZZ_h_mul_r, nxv8bf16, int_aarch64_sme_fmls_vg1x2>; +defm BFMLS_VG4_M4Z4Z : sme2_dot_mla_add_sub_array_vg4_multi<"bfmls", 0b1100011, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, int_aarch64_sme_fmls_vg1x4>; defm BFMAX_VG2_2ZZ : sme2p1_bf_max_min_vector_vg2_single<"bfmax", 0b0010000>; defm BFMAX_VG4_4ZZ : sme2p1_bf_max_min_vector_vg4_single<"bfmax", 0b0010000>; @@ -909,9 +906,9 @@ def LUTI4_S_4ZZT2Z : sme2_luti4_vector_vg4_strided<0b00, 0b00, "luti4">; } //[HasSME2p1, HasSME_LUTv2] let Predicates = [HasSMEF8F16] in { -defm FVDOT_VG2_M2ZZI_BtoH : sme2p1_multi_vec_array_vg2_index_16b<"fvdot", 0b11, 0b110, ZZ_b_mul_r, ZPR4b8>; -defm FDOT_VG2_M2ZZI_BtoH : sme2p1_multi_vec_array_vg2_index_16b<"fdot", 0b11, 0b010, ZZ_b_mul_r, ZPR4b8>; -defm FDOT_VG4_M4ZZI_BtoH : sme2p1_multi_vec_array_vg4_index_16b<"fdot", 0b100, ZZZZ_b_mul_r, ZPR4b8>; +defm FVDOT_VG2_M2ZZI_BtoH : sme2p1_multi_vec_array_vg2_index_f8f16<"fvdot", 0b11, 0b110, ZZ_b_mul_r, ZPR4b8>; +defm FDOT_VG2_M2ZZI_BtoH : sme2p1_multi_vec_array_vg2_index_f8f16<"fdot", 0b11, 0b010, ZZ_b_mul_r, ZPR4b8>; +defm FDOT_VG4_M4ZZI_BtoH : sme2p1_multi_vec_array_vg4_index_f8f16<"fdot", 0b100, ZZZZ_b_mul_r, ZPR4b8>; defm FDOT_VG2_M2ZZ_BtoH : sme2_dot_mla_add_sub_array_vg24_single<"fdot", 0b0010001, MatrixOp16, ZZ_b, ZPR4b8>; defm FDOT_VG4_M4ZZ_BtoH : sme2_dot_mla_add_sub_array_vg24_single<"fdot", 0b0110001, MatrixOp16, ZZZZ_b, ZPR4b8>; // TODO: Replace nxv16i8 by nxv16f8 diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 3363aab4b093..724dd07225cd 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -2448,9 +2448,29 @@ multiclass sme2_multi_vec_array_vg2_index_32b sz, bits< } // SME2.1 multi-vec ternary indexed two registers 16-bit -// SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers multiclass sme2p1_multi_vec_array_vg2_index_16b sz, bits<3> op, - RegisterOperand multi_vector_ty, ZPRRegOp zpr_ty> { + RegisterOperand multi_vector_ty, ZPRRegOp vector_ty, + ValueType vt, SDPatternOperator intrinsic> { + def NAME : sme2_multi_vec_array_vg2_index, SMEPseudo2Instr { + bits<3> i; + let Inst{11-10} = i{2-1}; + let Inst{3} = i{0}; + } + + def _PSEUDO : sme2_za_array_2op_multi_index_pseudo; + + def : SME2_ZA_TwoOp_VG2_Multi_Index_Pat; + + def : InstAlias(NAME) MatrixOp16:$ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, + multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexH:$i), 0>; +} + +// SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers +multiclass sme2p1_multi_vec_array_vg2_index_f8f16 sz, bits<3> op, + RegisterOperand multi_vector_ty, ZPRRegOp zpr_ty> { def NAME : sme2_multi_vec_array_vg2_index { @@ -2569,10 +2589,10 @@ multiclass sme2_multi_vec_array_vg4_index_32b op, multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexS32b_timm:$i), 0>; } -// SME2.1 multi-vec ternary indexed four registers 16-bit -multiclass sme2p1_multi_vec_array_vg4_index_16b op, - RegisterOperand multi_vector_ty, - ZPRRegOp zpr_ty> { +// SME2.1 multi-vec ternary indexed four registers 16-bit (FP8) +multiclass sme2p1_multi_vec_array_vg4_index_f8f16 op, + RegisterOperand multi_vector_ty, + ZPRRegOp zpr_ty> { def NAME : sme2_multi_vec_array_vg4_index<0b0,{0b1,?,?,op,?}, MatrixOp16, multi_vector_ty, zpr_ty, VectorIndexH, mnemonic>{ @@ -2586,6 +2606,28 @@ multiclass sme2p1_multi_vec_array_vg4_index_16b op, sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, zpr_ty:$Zm, VectorIndexH:$i), 0>; } +// SME2.1 multi-vec ternary indexed four registers 16-bit +multiclass sme2p1_multi_vec_array_vg4_index_16b op, + RegisterOperand multi_vector_ty, + ZPRRegOp vector_ty, ValueType vt, + SDPatternOperator intrinsic> { + def NAME : sme2_multi_vec_array_vg4_index<0b0,{0b1,?,?,op,?}, MatrixOp16, + multi_vector_ty, vector_ty, + VectorIndexH, mnemonic>, SMEPseudo2Instr { + bits<3> i; + let Inst{11-10} = i{2-1}; + let Inst{3} = i{0}; + } + + def _PSEUDO : sme2_za_array_2op_multi_index_pseudo; + + def : SME2_ZA_TwoOp_VG4_Multi_Index_Pat; + + def : InstAlias(NAME) MatrixOp16:$ZAda, MatrixIndexGPR32Op8_11:$Rv, + sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexH:$i), 0>; +} + // SME2 multi-vec ternary indexed four registers 64-bit class sme2_multi_vec_array_vg4_index_64b op, RegisterOperand multi_vector_ty, diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas16.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas16.ll new file mode 100644 index 000000000000..3e807b7e6338 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas16.ll @@ -0,0 +1,462 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "// kill:.*$" --version 4 +; RUN: llc -verify-machineinstrs < %s | FileCheck %s + +target triple = "aarch64-linux" + +define void @test_fmla_f16_vg2_single(i32 %slice, %a0, %a1, %b) #0 { +; CHECK-LABEL: test_fmla_f16_vg2_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h +; CHECK: fmla za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h +; CHECK: ret + call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8f16(i32 %slice, %a0, %a1, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8f16(i32 %slice.7, %a0, %a1, %b) + ret void +} + +define void @test_fmla_f16_vg4_single(i32 %slice, %a0, %a1, +; CHECK-LABEL: test_fmla_f16_vg4_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h +; CHECK: fmla za.h[w8, 7, vgx4], { z0.h - z3.h }, z4.h +; CHECK: ret + %a2, %a3, %b) #0 { + call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8f16(i32 %slice, %a0, %a1, + %a2, %a3, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8f16(i32 %slice.7, %a0, %a1, + %a2, %a3, %b) + ret void +} + +define void @test_fmls_f16_vg2_single(i32 %slice, %a0, %a1, %b) #0 { +; CHECK-LABEL: test_fmls_f16_vg2_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h +; CHECK: fmls za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h +; CHECK: ret + call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8f16(i32 %slice, %a0, %a1, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8f16(i32 %slice.7, %a0, %a1, %b) + ret void +} + +define void @test_fmls_f16_vg4_single(i32 %slice, %a0, %a1, +; CHECK-LABEL: test_fmls_f16_vg4_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h +; CHECK: fmls za.h[w8, 7, vgx4], { z0.h - z3.h }, z4.h +; CHECK: ret + %a2, %a3, %b) #0 { + call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8f16(i32 %slice, %a0, %a1, + %a2, %a3, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8f16(i32 %slice.7, %a0, %a1, + %a2, %a3, %b) + ret void +} + +define void @test_fmla_f16_vg2_multi(i32 %slice, +; CHECK-LABEL: test_fmla_f16_vg2_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: fmla za.h[w8, 7, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: ret + %a0, %a1, + %b0, %b1) #0 { + call void @llvm.aarch64.sme.fmla.vg1x2.nxv8f16(i32 %slice, + %a0, %a1, + %b0, %b1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.vg1x2.nxv8f16(i32 %slice.7, + %a0, %a1, + %b0, %b1) + ret void +} + +define void @test_fmla_f16_vg4_multi(i32 %slice, +; CHECK-LABEL: test_fmla_f16_vg4_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: fmla za.h[w8, 7, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) #0 { + call void @llvm.aarch64.sme.fmla.vg1x4.nxv8f16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.vg1x4.nxv8f16(i32 %slice.7, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + ret void +} + +define void @test_fmls_f16_vg2_multi(i32 %slice, +; CHECK-LABEL: test_fmls_f16_vg2_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: fmls za.h[w8, 7, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: ret + %a0, %a1, + %b0, %b1) #0 { + call void @llvm.aarch64.sme.fmls.vg1x2.nxv8f16(i32 %slice, + %a0, %a1, + %b0, %b1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.vg1x2.nxv8f16(i32 %slice.7, + %a0, %a1, + %b0, %b1) + ret void +} + +define void @test_fmls_f16_vg4_multi(i32 %slice, +; CHECK-LABEL: test_fmls_f16_vg4_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: fmls za.h[w8, 7, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) #0 { + call void @llvm.aarch64.sme.fmls.vg1x4.nxv8f16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.vg1x4.nxv8f16(i32 %slice.7, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + ret void +} + +define void @test_fmla_f16_vg2_index(i32 %slice, +; CHECK-LABEL: test_fmla_f16_vg2_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: fmla za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: ret + %a0, %a1, + %b) #0 { + call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8f16(i32 %slice, + %a0, %a1, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8f16(i32 %slice.7, + %a0, %a1, + %b, i32 7); + ret void +} + +define void @test_fmla_f16_vg4_index(i32 %slice, +; CHECK-LABEL: test_fmla_f16_vg4_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b) #0 { + call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8f16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8f16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + ret void +} + +define void @test_fmls_f16_vg2_index(i32 %slice, +; CHECK-LABEL: test_fmls_f16_vg2_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: fmls za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: ret + %a0, %a1, + %b) #0 { + call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8f16(i32 %slice, + %a0, %a1, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8f16(i32 %slice.7, + %a0, %a1, + %b, i32 7); + ret void +} + +define void @test_fmls_f16_vg4_index(i32 %slice, +; CHECK-LABEL: test_fmls_f16_vg4_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b) #0 { + call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8f16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8f16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + ret void +} + +define void @test_fmla_bf16_vg2_single(i32 %slice, %a0, %a1, %b) #0 { +; CHECK-LABEL: test_fmla_bf16_vg2_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h +; CHECK: bfmla za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h +; CHECK: ret + call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8bf16(i32 %slice, %a0, %a1, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8bf16(i32 %slice.7, %a0, %a1, %b) + ret void +} + +define void @test_fmla_bf16_vg4_single(i32 %slice, %a0, %a1, +; CHECK-LABEL: test_fmla_bf16_vg4_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h +; CHECK: bfmla za.h[w8, 7, vgx4], { z0.h - z3.h }, z4.h +; CHECK: ret + %a2, %a3, %b) #0 { + call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8bf16(i32 %slice, %a0, %a1, + %a2, %a3, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8bf16(i32 %slice.7, %a0, %a1, + %a2, %a3, %b) + ret void +} + +define void @test_fmls_bf16_vg2_single(i32 %slice, %a0, %a1, %b) #0 { +; CHECK-LABEL: test_fmls_bf16_vg2_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h +; CHECK: bfmls za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h +; CHECK: ret + call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8bf16(i32 %slice, %a0, %a1, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8bf16(i32 %slice.7, %a0, %a1, %b) + ret void +} + +define void @test_fmls_bf16_vg4_single(i32 %slice, %a0, %a1, +; CHECK-LABEL: test_fmls_bf16_vg4_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h +; CHECK: bfmls za.h[w8, 7, vgx4], { z0.h - z3.h }, z4.h +; CHECK: ret + %a2, %a3, %b) #0 { + call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8bf16(i32 %slice, %a0, %a1, + %a2, %a3, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8bf16(i32 %slice.7, %a0, %a1, + %a2, %a3, %b) + ret void +} + +define void @test_fmla_bf16_vg2_multi(i32 %slice, +; CHECK-LABEL: test_fmla_bf16_vg2_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: bfmla za.h[w8, 7, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: ret + %a0, %a1, + %b0, %b1) #0 { + call void @llvm.aarch64.sme.fmla.vg1x2.nxv8bf16(i32 %slice, + %a0, %a1, + %b0, %b1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.vg1x2.nxv8bf16(i32 %slice.7, + %a0, %a1, + %b0, %b1) + ret void +} + +define void @test_fmla_bf16_vg4_multi(i32 %slice, +; CHECK-LABEL: test_fmla_bf16_vg4_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: bfmla za.h[w8, 7, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) #0 { + call void @llvm.aarch64.sme.fmla.vg1x4.nxv8bf16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.vg1x4.nxv8bf16(i32 %slice.7, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + ret void +} + +define void @test_fmls_bf16_vg2_multi(i32 %slice, +; CHECK-LABEL: test_fmls_bf16_vg2_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: bfmls za.h[w8, 7, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: ret + %a0, %a1, + %b0, %b1) #0 { + call void @llvm.aarch64.sme.fmls.vg1x2.nxv8bf16(i32 %slice, + %a0, %a1, + %b0, %b1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.vg1x2.nxv8bf16(i32 %slice.7, + %a0, %a1, + %b0, %b1) + ret void +} + +define void @test_fmls_bf16_vg4_multi(i32 %slice, +; CHECK-LABEL: test_fmls_bf16_vg4_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: bfmls za.h[w8, 7, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) #0 { + call void @llvm.aarch64.sme.fmls.vg1x4.nxv8bf16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.vg1x4.nxv8bf16(i32 %slice.7, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + ret void +} + +define void @test_fmla_bf16_vg2_index(i32 %slice, +; CHECK-LABEL: test_fmla_bf16_vg2_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: bfmla za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: ret + %a0, %a1, + %b) #0 { + call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8bf16(i32 %slice, + %a0, %a1, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8bf16(i32 %slice.7, + %a0, %a1, + %b, i32 7); + ret void +} + +define void @test_fmla_bf16_vg4_index(i32 %slice, +; CHECK-LABEL: test_fmla_bf16_vg4_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b) #0 { + call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8bf16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8bf16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + ret void +} + +define void @test_fmls_bf16_vg2_index(i32 %slice, +; CHECK-LABEL: test_fmls_bf16_vg2_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: bfmls za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: ret + %a0, %a1, + %b) #0 { + call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8bf16(i32 %slice, + %a0, %a1, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8bf16(i32 %slice.7, + %a0, %a1, + %b, i32 7); + ret void +} + +define void @test_fmls_bf16_vg4_index(i32 %slice, +; CHECK-LABEL: test_fmls_bf16_vg4_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b) #0 { + call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8bf16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8bf16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + ret void +} + +attributes #0 = { nounwind "target-features"="+sme2p1,+sme-f16f16,+b16b16" } -- GitLab From 2e8d8155969f90b8f17634ce9a8e4541fb21dbab Mon Sep 17 00:00:00 2001 From: Graham Hunter Date: Fri, 10 May 2024 11:22:11 +0100 Subject: [PATCH 247/328] [TTI] Support scalable offsets in getScalingFactorCost (#88113) Part of the work to support vscale-relative immediates in LSR. --- llvm/include/llvm/Analysis/TargetTransformInfo.h | 6 +++--- llvm/include/llvm/Analysis/TargetTransformInfoImpl.h | 8 +++++--- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 5 +++-- llvm/lib/Analysis/TargetTransformInfo.cpp | 2 +- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 5 +++-- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h | 2 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 5 +++-- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 2 +- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 5 +++-- llvm/lib/Target/X86/X86TargetTransformInfo.h | 2 +- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp | 6 ++++-- 11 files changed, 28 insertions(+), 20 deletions(-) diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index 1c76821fe5e4..f0eb83c143e2 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -834,7 +834,7 @@ public: /// If the AM is not supported, it returns a negative value. /// TODO: Handle pre/postinc as well. InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace = 0) const; @@ -1891,7 +1891,7 @@ public: virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0; virtual bool prefersVectorizedAddressing() = 0; virtual InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) = 0; virtual bool LSRWithInstrQueries() = 0; @@ -2403,7 +2403,7 @@ public: return Impl.prefersVectorizedAddressing(); } InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) override { return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index 4d5cd963e092..262ebdb3cbef 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -32,6 +32,7 @@ class Function; /// Base class for use as a mix-in that aids implementing /// a TargetTransformInfo-compatible class. class TargetTransformInfoImplBase { + protected: typedef TargetTransformInfo TTI; @@ -326,12 +327,13 @@ public: bool prefersVectorizedAddressing() const { return true; } InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const { // Guess that all legal addressing mode are free. - if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, - AddrSpace)) + if (isLegalAddressingMode(Ty, BaseGV, BaseOffset.getFixed(), HasBaseReg, + Scale, AddrSpace, /*I=*/nullptr, + BaseOffset.getScalable())) return 0; return -1; } diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index bcb60c656296..fa481886b268 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -404,13 +404,14 @@ public: } InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { TargetLoweringBase::AddrMode AM; AM.BaseGV = BaseGV; - AM.BaseOffs = BaseOffset; + AM.BaseOffs = BaseOffset.getFixed(); AM.HasBaseReg = HasBaseReg; AM.Scale = Scale; + AM.ScalableOffset = BaseOffset.getScalable(); if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace)) return 0; return -1; diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index 33c899fe8899..00443ace46f7 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -531,7 +531,7 @@ bool TargetTransformInfo::prefersVectorizedAddressing() const { } InstructionCost TargetTransformInfo::getScalingFactorCost( - Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, + Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const { InstructionCost Cost = TTIImpl->getScalingFactorCost( Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace); diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index 4b410826f4bb..f49c73dc7951 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -4183,7 +4183,7 @@ bool AArch64TTIImpl::preferPredicateOverEpilogue(TailFoldingInfo *TFI) { InstructionCost AArch64TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const { // Scaling factors are not free at all. // Operands | Rt Latency @@ -4194,9 +4194,10 @@ AArch64TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, // Rt, [Xn, Wm, #imm] | TargetLoweringBase::AddrMode AM; AM.BaseGV = BaseGV; - AM.BaseOffs = BaseOffset; + AM.BaseOffs = BaseOffset.getFixed(); AM.HasBaseReg = HasBaseReg; AM.Scale = Scale; + AM.ScalableOffset = BaseOffset.getScalable(); if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace)) // Scale represents reg2 * scale, thus account for 1 if // it is not equal to 0 or 1. diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index 678c132e6a80..2f44aaa3e26a 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -407,7 +407,7 @@ public: /// If the AM is supported, the return value must be >= 0. /// If the AM is not supported, it returns a negative value. InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const; /// @} diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp index ee87f7f0e555..7db2e8ee7e6f 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -2571,14 +2571,15 @@ bool ARMTTIImpl::preferPredicatedReductionSelect( } InstructionCost ARMTTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const { TargetLoweringBase::AddrMode AM; AM.BaseGV = BaseGV; - AM.BaseOffs = BaseOffset; + AM.BaseOffs = BaseOffset.getFixed(); AM.HasBaseReg = HasBaseReg; AM.Scale = Scale; + AM.ScalableOffset = BaseOffset.getScalable(); if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace)) { if (ST->hasFPAO()) return AM.Scale < 0 ? 1 : 0; // positive offsets execute faster diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h index 58eab45b9641..8c4b92b85688 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -303,7 +303,7 @@ public: /// If the AM is supported, the return value must be >= 0. /// If the AM is not supported, the return value must be negative. InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const; bool maybeLoweredToCall(Instruction &I); diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 6b7cddc6d72e..d43480d0a012 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -6741,7 +6741,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( } InstructionCost X86TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const { // Scaling factors are not free at all. @@ -6764,9 +6764,10 @@ InstructionCost X86TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, // vmovaps %ymm1, (%r8) can use port 2, 3, or 7. TargetLoweringBase::AddrMode AM; AM.BaseGV = BaseGV; - AM.BaseOffs = BaseOffset; + AM.BaseOffs = BaseOffset.getFixed(); AM.HasBaseReg = HasBaseReg; AM.Scale = Scale; + AM.ScalableOffset = BaseOffset.getScalable(); if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace)) // Scale represents reg2 * scale, thus account for 1 // as soon as we use a second register. diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h index b50193074573..d720cc136b8a 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.h +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -253,7 +253,7 @@ public: /// If the AM is supported, the return value must be >= 0. /// If the AM is not supported, it returns a negative value. InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const; bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp index ec42e2d6e193..eb1904ccaff3 100644 --- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp +++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp @@ -1817,10 +1817,12 @@ static InstructionCost getScalingFactorCost(const TargetTransformInfo &TTI, case LSRUse::Address: { // Check the scaling factor cost with both the min and max offsets. InstructionCost ScaleCostMinOffset = TTI.getScalingFactorCost( - LU.AccessTy.MemTy, F.BaseGV, F.BaseOffset + LU.MinOffset, F.HasBaseReg, + LU.AccessTy.MemTy, F.BaseGV, + StackOffset::getFixed(F.BaseOffset + LU.MinOffset), F.HasBaseReg, F.Scale, LU.AccessTy.AddrSpace); InstructionCost ScaleCostMaxOffset = TTI.getScalingFactorCost( - LU.AccessTy.MemTy, F.BaseGV, F.BaseOffset + LU.MaxOffset, F.HasBaseReg, + LU.AccessTy.MemTy, F.BaseGV, + StackOffset::getFixed(F.BaseOffset + LU.MaxOffset), F.HasBaseReg, F.Scale, LU.AccessTy.AddrSpace); assert(ScaleCostMinOffset.isValid() && ScaleCostMaxOffset.isValid() && -- GitLab From 28767afd53353d9333b0adf6f0fafa1592092532 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Fri, 10 May 2024 11:47:13 +0100 Subject: [PATCH 248/328] [LAA] Support backward dependences with non-constant distance. (#91525) Following up to 933f49248, also update the code reasoning about backwards dependences to support non-constant distances. Update the code to use the signed minimum distance instead of a constant distance This means e checked the lower bound of the dependence distance and the distance may be larger at runtime (and safe for vectorization). Whether to classify it as Unknown or Backwards depends on the vector width and LAA was updated to take TTI to get the maximum vector register width. If the minimum dependence distance is larger than the max vector width, we consider it as backwards-vectorizable. Otherwise we classify them as Unknown, so we re-try with runtime checks. PR: https://github.com/llvm/llvm-project/pull/91525 --- .../llvm/Analysis/LoopAccessAnalysis.h | 23 +- llvm/lib/Analysis/LoopAccessAnalysis.cpp | 93 ++++-- llvm/lib/Transforms/Scalar/LoopFlatten.cpp | 2 +- .../Transforms/Scalar/LoopVersioningLICM.cpp | 2 +- .../multiple-strides-rt-memory-checks.ll | 2 +- .../non-constant-distance-backward.ll | 292 ++++++++++-------- .../Transforms/Vectorize/VPlanSlpTest.cpp | 2 +- 7 files changed, 247 insertions(+), 169 deletions(-) diff --git a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h index cf998e66ee48..6ebd0fb8477a 100644 --- a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h +++ b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h @@ -181,8 +181,10 @@ public: const SmallVectorImpl &Instrs) const; }; - MemoryDepChecker(PredicatedScalarEvolution &PSE, const Loop *L) - : PSE(PSE), InnermostLoop(L) {} + MemoryDepChecker(PredicatedScalarEvolution &PSE, const Loop *L, + unsigned MaxTargetVectorWidthInBits) + : PSE(PSE), InnermostLoop(L), + MaxTargetVectorWidthInBits(MaxTargetVectorWidthInBits) {} /// Register the location (instructions are given increasing numbers) /// of a write access. @@ -314,6 +316,12 @@ private: /// RecordDependences is true. SmallVector Dependences; + /// The maximum width of a target's vector registers multiplied by 2 to also + /// roughly account for additional interleaving. Is used to decide if a + /// backwards dependence with non-constant stride should be classified as + /// backwards-vectorizable or unknown (triggering a runtime check). + unsigned MaxTargetVectorWidthInBits = 0; + /// Check whether there is a plausible dependence between the two /// accesses. /// @@ -575,8 +583,9 @@ private: /// PSE must be emitted in order for the results of this analysis to be valid. class LoopAccessInfo { public: - LoopAccessInfo(Loop *L, ScalarEvolution *SE, const TargetLibraryInfo *TLI, - AAResults *AA, DominatorTree *DT, LoopInfo *LI); + LoopAccessInfo(Loop *L, ScalarEvolution *SE, const TargetTransformInfo *TTI, + const TargetLibraryInfo *TLI, AAResults *AA, DominatorTree *DT, + LoopInfo *LI); /// Return true we can analyze the memory accesses in the loop and there are /// no memory dependence cycles. Note that for dependences between loads & @@ -799,12 +808,14 @@ class LoopAccessInfoManager { AAResults &AA; DominatorTree &DT; LoopInfo &LI; + TargetTransformInfo *TTI; const TargetLibraryInfo *TLI = nullptr; public: LoopAccessInfoManager(ScalarEvolution &SE, AAResults &AA, DominatorTree &DT, - LoopInfo &LI, const TargetLibraryInfo *TLI) - : SE(SE), AA(AA), DT(DT), LI(LI), TLI(TLI) {} + LoopInfo &LI, TargetTransformInfo *TTI, + const TargetLibraryInfo *TLI) + : SE(SE), AA(AA), DT(DT), LI(LI), TTI(TTI), TLI(TLI) {} const LoopAccessInfo &getInfo(Loop &L); diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp index 6fc7da168b42..d071e5332440 100644 --- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp +++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp @@ -31,6 +31,7 @@ #include "llvm/Analysis/ScalarEvolution.h" #include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/Analysis/TargetLibraryInfo.h" +#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/ValueTracking.h" #include "llvm/Analysis/VectorUtils.h" #include "llvm/IR/BasicBlock.h" @@ -2122,17 +2123,24 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( return Dependence::Forward; } - if (!C) { - // TODO: FoundNonConstantDistanceDependence is used as a necessary condition - // to consider retrying with runtime checks. Historically, we did not set it - // when strides were different but there is no inherent reason to. + int64_t MinDistance = SE.getSignedRangeMin(Dist).getSExtValue(); + // Below we only handle strictly positive distances. + if (MinDistance <= 0) { FoundNonConstantDistanceDependence |= CommonStride.has_value(); - LLVM_DEBUG(dbgs() << "LAA: Dependence because of non-constant distance\n"); return Dependence::Unknown; } - if (!SE.isKnownPositive(Dist)) - return Dependence::Unknown; + if (!isa(Dist)) { + // Previously this case would be treated as Unknown, possibly setting + // FoundNonConstantDistanceDependence to force re-trying with runtime + // checks. Until the TODO below is addressed, set it here to preserve + // original behavior w.r.t. re-trying with runtime checks. + // TODO: FoundNonConstantDistanceDependence is used as a necessary + // condition to consider retrying with runtime checks. Historically, we + // did not set it when strides were different but there is no inherent + // reason to. + FoundNonConstantDistanceDependence |= CommonStride.has_value(); + } if (!HasSameSize) { LLVM_DEBUG(dbgs() << "LAA: ReadWrite-Write positive dependency with " @@ -2140,14 +2148,9 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( return Dependence::Unknown; } - // The logic below currently only supports StrideA == StrideB, i.e. there's a - // common stride. if (!CommonStride) return Dependence::Unknown; - const APInt &Val = C->getAPInt(); - int64_t Distance = Val.getSExtValue(); - // Bail out early if passed-in parameters make vectorization not feasible. unsigned ForcedFactor = (VectorizerParams::VectorizationFactor ? VectorizerParams::VectorizationFactor : 1); @@ -2172,8 +2175,8 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( // | A[0] | | A[2] | | A[4] | | A[6] | | // | B[0] | | B[2] | | B[4] | // - // Distance needs for vectorizing iterations except the last iteration: - // 4 * 2 * (MinNumIter - 1). Distance needs for the last iteration: 4. + // MinDistance needs for vectorizing iterations except the last iteration: + // 4 * 2 * (MinNumIter - 1). MinDistance needs for the last iteration: 4. // So the minimum distance needed is: 4 * 2 * (MinNumIter - 1) + 4. // // If MinNumIter is 2, it is vectorizable as the minimum distance needed is @@ -2182,11 +2185,22 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( // If MinNumIter is 4 (Say if a user forces the vectorization factor to be 4), // the minimum distance needed is 28, which is greater than distance. It is // not safe to do vectorization. + + // We know that Dist is positive, but it may not be constant. Use the signed + // minimum for computations below, as this ensures we compute the closest + // possible dependence distance. uint64_t MinDistanceNeeded = - TypeByteSize * (*CommonStride) * (MinNumIter - 1) + TypeByteSize; - if (MinDistanceNeeded > static_cast(Distance)) { - LLVM_DEBUG(dbgs() << "LAA: Failure because of positive distance " - << Distance << '\n'); + TypeByteSize * *CommonStride * (MinNumIter - 1) + TypeByteSize; + if (MinDistanceNeeded > static_cast(MinDistance)) { + if (!isa(Dist)) { + // For non-constant distances, we checked the lower bound of the + // dependence distance and the distance may be larger at runtime (and safe + // for vectorization). Classify it as Unknown, so we re-try with runtime + // checks. + return Dependence::Unknown; + } + LLVM_DEBUG(dbgs() << "LAA: Failure because of positive minimum distance " + << MinDistance << '\n'); return Dependence::Backward; } @@ -2215,12 +2229,13 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( // is 8, which is less than 2 and forbidden vectorization, But actually // both A and B could be vectorized by 2 iterations. MinDepDistBytes = - std::min(static_cast(Distance), MinDepDistBytes); + std::min(static_cast(MinDistance), MinDepDistBytes); bool IsTrueDataDependence = (!AIsWrite && BIsWrite); uint64_t MinDepDistBytesOld = MinDepDistBytes; if (IsTrueDataDependence && EnableForwardingConflictDetection && - couldPreventStoreLoadForward(Distance, TypeByteSize)) { + isa(Dist) && + couldPreventStoreLoadForward(MinDistance, TypeByteSize)) { // Sanity check that we didn't update MinDepDistBytes when calling // couldPreventStoreLoadForward assert(MinDepDistBytes == MinDepDistBytesOld && @@ -2232,10 +2247,18 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( // An update to MinDepDistBytes requires an update to MaxSafeVectorWidthInBits // since there is a backwards dependency. - uint64_t MaxVF = MinDepDistBytes / (TypeByteSize * (*CommonStride)); - LLVM_DEBUG(dbgs() << "LAA: Positive distance " << Val.getSExtValue() + uint64_t MaxVF = MinDepDistBytes / (TypeByteSize * *CommonStride); + LLVM_DEBUG(dbgs() << "LAA: Positive min distance " << MinDistance << " with max VF = " << MaxVF << '\n'); + uint64_t MaxVFInBits = MaxVF * TypeByteSize * 8; + if (!isa(Dist) && MaxVFInBits < MaxTargetVectorWidthInBits) { + // For non-constant distances, we checked the lower bound of the dependence + // distance and the distance may be larger at runtime (and safe for + // vectorization). Classify it as Unknown, so we re-try with runtime checks. + return Dependence::Unknown; + } + MaxSafeVectorWidthInBits = std::min(MaxSafeVectorWidthInBits, MaxVFInBits); return Dependence::BackwardVectorizable; } @@ -3018,11 +3041,28 @@ void LoopAccessInfo::collectStridedAccess(Value *MemAccess) { } LoopAccessInfo::LoopAccessInfo(Loop *L, ScalarEvolution *SE, + const TargetTransformInfo *TTI, const TargetLibraryInfo *TLI, AAResults *AA, DominatorTree *DT, LoopInfo *LI) : PSE(std::make_unique(*SE, *L)), - PtrRtChecking(nullptr), - DepChecker(std::make_unique(*PSE, L)), TheLoop(L) { + PtrRtChecking(nullptr), TheLoop(L) { + unsigned MaxTargetVectorWidthInBits = std::numeric_limits::max(); + if (TTI) { + TypeSize FixedWidth = + TTI->getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector); + if (FixedWidth.isNonZero()) { + // Scale the vector width by 2 as rough estimate to also consider + // interleaving. + MaxTargetVectorWidthInBits = FixedWidth.getFixedValue() * 2; + } + + TypeSize ScalableWidth = + TTI->getRegisterBitWidth(TargetTransformInfo::RGK_ScalableVector); + if (ScalableWidth.isNonZero()) + MaxTargetVectorWidthInBits = std::numeric_limits::max(); + } + DepChecker = + std::make_unique(*PSE, L, MaxTargetVectorWidthInBits); PtrRtChecking = std::make_unique(*DepChecker, SE); if (canAnalyzeLoop()) { analyzeLoop(AA, LI, TLI, DT); @@ -3082,7 +3122,7 @@ const LoopAccessInfo &LoopAccessInfoManager::getInfo(Loop &L) { if (I.second) I.first->second = - std::make_unique(&L, &SE, TLI, &AA, &DT, &LI); + std::make_unique(&L, &SE, TTI, TLI, &AA, &DT, &LI); return *I.first->second; } @@ -3111,8 +3151,9 @@ LoopAccessInfoManager LoopAccessAnalysis::run(Function &F, auto &AA = FAM.getResult(F); auto &DT = FAM.getResult(F); auto &LI = FAM.getResult(F); + auto &TTI = FAM.getResult(F); auto &TLI = FAM.getResult(F); - return LoopAccessInfoManager(SE, AA, DT, LI, &TLI); + return LoopAccessInfoManager(SE, AA, DT, LI, &TTI, &TLI); } AnalysisKey LoopAccessAnalysis::Key; diff --git a/llvm/lib/Transforms/Scalar/LoopFlatten.cpp b/llvm/lib/Transforms/Scalar/LoopFlatten.cpp index 0e9cf328f149..a7f8a22ece27 100644 --- a/llvm/lib/Transforms/Scalar/LoopFlatten.cpp +++ b/llvm/lib/Transforms/Scalar/LoopFlatten.cpp @@ -1005,7 +1005,7 @@ PreservedAnalyses LoopFlattenPass::run(LoopNest &LN, LoopAnalysisManager &LAM, // in simplified form, and also needs LCSSA. Running // this pass will simplify all loops that contain inner loops, // regardless of whether anything ends up being flattened. - LoopAccessInfoManager LAIM(AR.SE, AR.AA, AR.DT, AR.LI, nullptr); + LoopAccessInfoManager LAIM(AR.SE, AR.AA, AR.DT, AR.LI, &AR.TTI, nullptr); for (Loop *InnerLoop : LN.getLoops()) { auto *OuterLoop = InnerLoop->getParentLoop(); if (!OuterLoop) diff --git a/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp b/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp index f39c24484840..663715948241 100644 --- a/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp +++ b/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp @@ -582,7 +582,7 @@ PreservedAnalyses LoopVersioningLICMPass::run(Loop &L, LoopAnalysisManager &AM, const Function *F = L.getHeader()->getParent(); OptimizationRemarkEmitter ORE(F); - LoopAccessInfoManager LAIs(*SE, *AA, *DT, LAR.LI, nullptr); + LoopAccessInfoManager LAIs(*SE, *AA, *DT, LAR.LI, nullptr, nullptr); if (!LoopVersioningLICM(AA, SE, &ORE, LAIs, LAR.LI, &L).run(DT)) return PreservedAnalyses::all(); return getLoopPassPreservedAnalyses(); diff --git a/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll b/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll index 3b4f2a170d8c..d96a6ea7c555 100644 --- a/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll +++ b/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll @@ -23,7 +23,7 @@ ; CHECK: function 'Test': ; CHECK: .inner: -; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Memory dependences are safe with a maximum safe vector width of 2048 bits with run-time checks ; CHECK-NEXT: Dependences: ; CHECK-NEXT: Run-time memory checks: ; CHECK: Check 0: diff --git a/llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll b/llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll index 5a95dcca1050..0058135a30d6 100644 --- a/llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll +++ b/llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll @@ -1,45 +1,47 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4 -; RUN: opt -passes='print' -disable-output %s 2>&1 | FileCheck %s -; RUN: opt -passes='print' -disable-output -mtriple=arm64-apple-macosx %s 2>&1 | FileCheck %s -; RUN: opt -passes='print' -disable-output -mtriple=arm64-apple-macosx -mattr=+sve %s 2>&1 | FileCheck %s +; RUN: opt -passes='print' -disable-output %s 2>&1 | FileCheck --check-prefixes=COMMON,MAXLEN %s +; RUN: opt -passes='print' -disable-output -mtriple=arm64-apple-macosx %s 2>&1 | FileCheck --check-prefixes=COMMON,VW128 %s +; RUN: opt -passes='print' -disable-output -mtriple=arm64-apple-macosx -mattr=+sve %s 2>&1 | FileCheck --check-prefixes=COMMON,MAXLEN %s ; REQUIRES: aarch64-registered-target target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +; If the dependence distance is not a constant, whether it gets identified as backwards or unknown depends on the minimum distance and the target's vector length. + define void @backward_min_distance_8(ptr %A, i64 %N) { -; CHECK-LABEL: 'backward_min_distance_8' -; CHECK-NEXT: loop: -; CHECK-NEXT: Memory dependences are safe with run-time checks -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP1:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv -; CHECK-NEXT: Against group ([[GRP2:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv -; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP1]]: -; CHECK-NEXT: (Low: {(1 + %A),+,1}<%outer.header> High: {(257 + %A),+,1}<%outer.header>) -; CHECK-NEXT: Member: {{\{\{}}(1 + %A),+,1}<%outer.header>,+,1}<%loop> -; CHECK-NEXT: Group [[GRP2]]: -; CHECK-NEXT: (Low: %A High: (256 + %A)) -; CHECK-NEXT: Member: {%A,+,1}<%loop> -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: -; CHECK-NEXT: outer.header: -; CHECK-NEXT: Report: loop is not the innermost loop -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Grouped accesses: -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: +; COMMON-LABEL: 'backward_min_distance_8' +; COMMON-NEXT: loop: +; COMMON-NEXT: Memory dependences are safe with run-time checks +; COMMON-NEXT: Dependences: +; COMMON-NEXT: Run-time memory checks: +; COMMON-NEXT: Check 0: +; COMMON-NEXT: Comparing group ([[GRP1:0x[0-9a-f]+]]): +; COMMON-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv +; COMMON-NEXT: Against group ([[GRP2:0x[0-9a-f]+]]): +; COMMON-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; COMMON-NEXT: Grouped accesses: +; COMMON-NEXT: Group [[GRP1]]: +; COMMON-NEXT: (Low: {(1 + %A),+,1}<%outer.header> High: {(257 + %A),+,1}<%outer.header>) +; COMMON-NEXT: Member: {{\{\{}}(1 + %A),+,1}<%outer.header>,+,1}<%loop> +; COMMON-NEXT: Group [[GRP2]]: +; COMMON-NEXT: (Low: %A High: (256 + %A)) +; COMMON-NEXT: Member: {%A,+,1}<%loop> +; COMMON-EMPTY: +; COMMON-NEXT: Non vectorizable stores to invariant address were not found in loop. +; COMMON-NEXT: SCEV assumptions: +; COMMON-EMPTY: +; COMMON-NEXT: Expressions re-written: +; COMMON-NEXT: outer.header: +; COMMON-NEXT: Report: loop is not the innermost loop +; COMMON-NEXT: Dependences: +; COMMON-NEXT: Run-time memory checks: +; COMMON-NEXT: Grouped accesses: +; COMMON-EMPTY: +; COMMON-NEXT: Non vectorizable stores to invariant address were not found in loop. +; COMMON-NEXT: SCEV assumptions: +; COMMON-EMPTY: +; COMMON-NEXT: Expressions re-written: ; entry: br label %outer.header @@ -70,38 +72,38 @@ exit: } define void @backward_min_distance_120(ptr %A, i64 %N) { -; CHECK-LABEL: 'backward_min_distance_120' -; CHECK-NEXT: loop: -; CHECK-NEXT: Memory dependences are safe with run-time checks -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP3:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv -; CHECK-NEXT: Against group ([[GRP4:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv -; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP3]]: -; CHECK-NEXT: (Low: {(15 + %A),+,1}<%outer.header> High: {(271 + %A),+,1}<%outer.header>) -; CHECK-NEXT: Member: {{\{\{}}(15 + %A),+,1}<%outer.header>,+,1}<%loop> -; CHECK-NEXT: Group [[GRP4]]: -; CHECK-NEXT: (Low: %A High: (256 + %A)) -; CHECK-NEXT: Member: {%A,+,1}<%loop> -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: -; CHECK-NEXT: outer.header: -; CHECK-NEXT: Report: loop is not the innermost loop -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Grouped accesses: -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: +; COMMON-LABEL: 'backward_min_distance_120' +; COMMON-NEXT: loop: +; COMMON-NEXT: Memory dependences are safe with run-time checks +; COMMON-NEXT: Dependences: +; COMMON-NEXT: Run-time memory checks: +; COMMON-NEXT: Check 0: +; COMMON-NEXT: Comparing group ([[GRP3:0x[0-9a-f]+]]): +; COMMON-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv +; COMMON-NEXT: Against group ([[GRP4:0x[0-9a-f]+]]): +; COMMON-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; COMMON-NEXT: Grouped accesses: +; COMMON-NEXT: Group [[GRP3]]: +; COMMON-NEXT: (Low: {(15 + %A),+,1}<%outer.header> High: {(271 + %A),+,1}<%outer.header>) +; COMMON-NEXT: Member: {{\{\{}}(15 + %A),+,1}<%outer.header>,+,1}<%loop> +; COMMON-NEXT: Group [[GRP4]]: +; COMMON-NEXT: (Low: %A High: (256 + %A)) +; COMMON-NEXT: Member: {%A,+,1}<%loop> +; COMMON-EMPTY: +; COMMON-NEXT: Non vectorizable stores to invariant address were not found in loop. +; COMMON-NEXT: SCEV assumptions: +; COMMON-EMPTY: +; COMMON-NEXT: Expressions re-written: +; COMMON-NEXT: outer.header: +; COMMON-NEXT: Report: loop is not the innermost loop +; COMMON-NEXT: Dependences: +; COMMON-NEXT: Run-time memory checks: +; COMMON-NEXT: Grouped accesses: +; COMMON-EMPTY: +; COMMON-NEXT: Non vectorizable stores to invariant address were not found in loop. +; COMMON-NEXT: SCEV assumptions: +; COMMON-EMPTY: +; COMMON-NEXT: Expressions re-written: ; entry: br label %outer.header @@ -131,41 +133,39 @@ exit: ret void } - -declare void @llvm.assume(i1) define void @backward_min_distance_128(ptr %A, i64 %N) { -; CHECK-LABEL: 'backward_min_distance_128' -; CHECK-NEXT: loop: -; CHECK-NEXT: Memory dependences are safe with run-time checks -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP5:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv -; CHECK-NEXT: Against group ([[GRP6:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv -; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP5]]: -; CHECK-NEXT: (Low: {(16 + %A),+,1}<%outer.header> High: {(272 + %A),+,1}<%outer.header>) -; CHECK-NEXT: Member: {{\{\{}}(16 + %A),+,1}<%outer.header>,+,1}<%loop> -; CHECK-NEXT: Group [[GRP6]]: -; CHECK-NEXT: (Low: %A High: (256 + %A)) -; CHECK-NEXT: Member: {%A,+,1}<%loop> -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: -; CHECK-NEXT: outer.header: -; CHECK-NEXT: Report: loop is not the innermost loop -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Grouped accesses: -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: +; COMMON-LABEL: 'backward_min_distance_128' +; COMMON-NEXT: loop: +; COMMON-NEXT: Memory dependences are safe with run-time checks +; COMMON-NEXT: Dependences: +; COMMON-NEXT: Run-time memory checks: +; COMMON-NEXT: Check 0: +; COMMON-NEXT: Comparing group ([[GRP13:0x[0-9a-f]+]]): +; COMMON-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv +; COMMON-NEXT: Against group ([[GRP14:0x[0-9a-f]+]]): +; COMMON-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; COMMON-NEXT: Grouped accesses: +; COMMON-NEXT: Group [[GRP13]]: +; COMMON-NEXT: (Low: {(16 + %A),+,1}<%outer.header> High: {(272 + %A),+,1}<%outer.header>) +; COMMON-NEXT: Member: {{\{\{}}(16 + %A),+,1}<%outer.header>,+,1}<%loop> +; COMMON-NEXT: Group [[GRP14]]: +; COMMON-NEXT: (Low: %A High: (256 + %A)) +; COMMON-NEXT: Member: {%A,+,1}<%loop> +; COMMON-EMPTY: +; COMMON-NEXT: Non vectorizable stores to invariant address were not found in loop. +; COMMON-NEXT: SCEV assumptions: +; COMMON-EMPTY: +; COMMON-NEXT: Expressions re-written: +; COMMON-NEXT: outer.header: +; COMMON-NEXT: Report: loop is not the innermost loop +; COMMON-NEXT: Dependences: +; COMMON-NEXT: Run-time memory checks: +; COMMON-NEXT: Grouped accesses: +; COMMON-EMPTY: +; COMMON-NEXT: Non vectorizable stores to invariant address were not found in loop. +; COMMON-NEXT: SCEV assumptions: +; COMMON-EMPTY: +; COMMON-NEXT: Expressions re-written: ; entry: br label %outer.header @@ -196,38 +196,64 @@ exit: } define void @backward_min_distance_256(ptr %A, i64 %N) { -; CHECK-LABEL: 'backward_min_distance_256' -; CHECK-NEXT: loop: -; CHECK-NEXT: Memory dependences are safe with run-time checks -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP7:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv -; CHECK-NEXT: Against group ([[GRP8:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv -; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP7]]: -; CHECK-NEXT: (Low: {(32 + %A),+,1}<%outer.header> High: {(288 + %A),+,1}<%outer.header>) -; CHECK-NEXT: Member: {{\{\{}}(32 + %A),+,1}<%outer.header>,+,1}<%loop> -; CHECK-NEXT: Group [[GRP8]]: -; CHECK-NEXT: (Low: %A High: (256 + %A)) -; CHECK-NEXT: Member: {%A,+,1}<%loop> -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: -; CHECK-NEXT: outer.header: -; CHECK-NEXT: Report: loop is not the innermost loop -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Grouped accesses: -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: +; MAXLEN-LABEL: 'backward_min_distance_256' +; MAXLEN-NEXT: loop: +; MAXLEN-NEXT: Memory dependences are safe with run-time checks +; MAXLEN-NEXT: Dependences: +; MAXLEN-NEXT: Run-time memory checks: +; MAXLEN-NEXT: Check 0: +; MAXLEN-NEXT: Comparing group ([[GRP17:0x[0-9a-f]+]]): +; MAXLEN-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv +; MAXLEN-NEXT: Against group ([[GRP18:0x[0-9a-f]+]]): +; MAXLEN-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; MAXLEN-NEXT: Grouped accesses: +; MAXLEN-NEXT: Group [[GRP17]]: +; MAXLEN-NEXT: (Low: {(32 + %A),+,1}<%outer.header> High: {(288 + %A),+,1}<%outer.header>) +; MAXLEN-NEXT: Member: {{\{\{}}(32 + %A),+,1}<%outer.header>,+,1}<%loop> +; MAXLEN-NEXT: Group [[GRP18]]: +; MAXLEN-NEXT: (Low: %A High: (256 + %A)) +; MAXLEN-NEXT: Member: {%A,+,1}<%loop> +; MAXLEN-EMPTY: +; MAXLEN-NEXT: Non vectorizable stores to invariant address were not found in loop. +; MAXLEN-NEXT: SCEV assumptions: +; MAXLEN-EMPTY: +; MAXLEN-NEXT: Expressions re-written: +; MAXLEN-NEXT: outer.header: +; MAXLEN-NEXT: Report: loop is not the innermost loop +; MAXLEN-NEXT: Dependences: +; MAXLEN-NEXT: Run-time memory checks: +; MAXLEN-NEXT: Grouped accesses: +; MAXLEN-EMPTY: +; MAXLEN-NEXT: Non vectorizable stores to invariant address were not found in loop. +; MAXLEN-NEXT: SCEV assumptions: +; MAXLEN-EMPTY: +; MAXLEN-NEXT: Expressions re-written: +; +; VW128-LABEL: 'backward_min_distance_256' +; VW128-NEXT: loop: +; VW128-NEXT: Memory dependences are safe with a maximum safe vector width of 256 bits +; VW128-NEXT: Dependences: +; VW128-NEXT: BackwardVectorizable: +; VW128-NEXT: %l = load i8, ptr %gep, align 4 -> +; VW128-NEXT: store i8 %add, ptr %gep.off.iv, align 4 +; VW128-EMPTY: +; VW128-NEXT: Run-time memory checks: +; VW128-NEXT: Grouped accesses: +; VW128-EMPTY: +; VW128-NEXT: Non vectorizable stores to invariant address were not found in loop. +; VW128-NEXT: SCEV assumptions: +; VW128-EMPTY: +; VW128-NEXT: Expressions re-written: +; VW128-NEXT: outer.header: +; VW128-NEXT: Report: loop is not the innermost loop +; VW128-NEXT: Dependences: +; VW128-NEXT: Run-time memory checks: +; VW128-NEXT: Grouped accesses: +; VW128-EMPTY: +; VW128-NEXT: Non vectorizable stores to invariant address were not found in loop. +; VW128-NEXT: SCEV assumptions: +; VW128-EMPTY: +; VW128-NEXT: Expressions re-written: ; entry: br label %outer.header diff --git a/llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp index 396919763c93..910fc24455a6 100644 --- a/llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp +++ b/llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp @@ -44,7 +44,7 @@ protected: AARes.reset(new AAResults(TLI)); AARes->addAAResult(*BasicAA); PSE.reset(new PredicatedScalarEvolution(*SE, *L)); - LAI.reset(new LoopAccessInfo(L, &*SE, &TLI, &*AARes, &*DT, &*LI)); + LAI.reset(new LoopAccessInfo(L, &*SE, nullptr, &TLI, &*AARes, &*DT, &*LI)); IAI.reset(new InterleavedAccessInfo(*PSE, L, &*DT, &*LI, &*LAI)); IAI->analyzeInterleaving(false); return {Plan, *IAI}; -- GitLab From fa4e8995cb6b6281a94261bee34242a39fd9f462 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 10 May 2024 11:47:05 +0100 Subject: [PATCH 249/328] [AArch64] Make wfxt a full Extension (#90987) Before #90987 WFxT did not have an AEK_WFXT, so it was assumed to be an FMV-only extension. However it also had a SubtargetFeature. This commit combines the two. This fixes an issue where -mattr=+wfxt was ignored, but has the side effect of allowing +wfxt as an option to -march. --- llvm/lib/Target/AArch64/AArch64Features.td | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index ddc324ea14ed..755a1bdc8e23 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -90,7 +90,6 @@ def : FMVOnlyExtension<"FEAT_SVE_BF16", "sve-bf16", "+sve,+bf16,+fullfp16,+fp-ar def : FMVOnlyExtension<"FEAT_SVE_EBF16", "sve-ebf16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>; def : FMVOnlyExtension<"FEAT_SVE_I8MM", "sve-i8mm", "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340>; def : FMVOnlyExtension<"FEAT_SVE_PMULL128", "sve2-pmull128", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390>; -def : FMVOnlyExtension<"FEAT_WFXT", "wfxt", "+wfxt", 550>; // Each SubtargetFeature which corresponds to an Arm Architecture feature should @@ -596,9 +595,9 @@ def FeatureMatMulFP64 : Extension<"f64mm", "MatMulFP64", def FeatureXS : SubtargetFeature<"xs", "HasXS", "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">; -// FIXME link with FMVExtension? -def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", - "true", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">; +def FeatureWFxT : Extension<"wfxt", "WFxT", + "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)", [], + "FEAT_WFXT", "", 550>; def FeatureHCX : SubtargetFeature< "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">; -- GitLab From 2371a6410dd83e82862e1c4dce1f7411efbe6b1c Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Fri, 10 May 2024 11:57:08 +0100 Subject: [PATCH 250/328] [AArch64] Add intrinsics for non-widening FMOPA/FMOPS (#88105) According to the specification in https://github.com/ARM-software/acle/pull/309 this adds the intrinsics void svmopa_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za"); void svmops_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za"); as well as the corresponding `bf16` variants. --- clang/include/clang/Basic/arm_sme.td | 24 +++++ .../acle_sme2_mopa_nonwide.c | 97 +++++++++++++++++++ .../acle_sme2_mopa_nonwide.c | 34 +++++++ llvm/include/llvm/IR/IntrinsicsAArch64.td | 3 + .../lib/Target/AArch64/AArch64SMEInstrInfo.td | 10 +- llvm/lib/Target/AArch64/SMEInstrFormats.td | 16 ++- .../CodeGen/AArch64/sme2-intrinsics-mopa.ll | 42 ++++++++ 7 files changed, 219 insertions(+), 7 deletions(-) create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c create mode 100644 clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c create mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-mopa.ll diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index 77ea53fb83fa..7808ee559932 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -708,3 +708,27 @@ let TargetGuard = "sme2" in { def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>; def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>; } + +//////////////////////////////////////////////////////////////////////////////// +// SME2p1 - FMOPA, FMOPS (non-widening) +let TargetGuard = "sme2,b16b16" in { + def SVMOPA_BF16_NW : SInst<"svmopa_za16[_bf16]_m", "viPPdd", "b", + MergeNone, "aarch64_sme_mopa", + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_1>]>; + def SVMOPS_BF16_NW : SInst<"svmops_za16[_bf16]_m", "viPPdd", "b", + MergeNone, "aarch64_sme_mops", + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_1>]>; +} + +let TargetGuard = "sme-f16f16" in { + def SVMOPA_F16_NW : SInst<"svmopa_za16[_f16]_m", "viPPdd", "h", + MergeNone, "aarch64_sme_mopa", + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_1>]>; + def SVMOPS_F16_NW : SInst<"svmops_za16[_f16]_m", "viPPdd", "h", + MergeNone, "aarch64_sme_mops", + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_1>]>; +} diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c new file mode 100644 index 000000000000..626bb6d3cf6f --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c @@ -0,0 +1,97 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +b16b16 -target-feature +sme-f16f16 -O2 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK +// RUN: %clang_cc1 -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +b16b16 -target-feature +sme-f16f16 -O2 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK-CXX +// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +b16b16 -target-feature +sme-f16f16 -O2 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK +// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +b16b16 -target-feature +sme-f16f16 -O2 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK-CXX + +// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +b16b16 -target-feature +sme-f16f16 -S -O2 -Werror -o /dev/null %s + +// REQUIRES: aarch64-registered-target + +#include + +#ifdef SME_OVERLOADED_FORMS +#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3 +#else +#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3 +#endif + +// CHECK-LABEL: define dso_local void @test_svmopa_za16_bf16( +// CHECK-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv8bf16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svmopa_za16_bf16u10__SVBool_tS_u14__SVBfloat16_tS0_( +// CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv8bf16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmopa_za16_bf16(svbool_t pn, svbool_t pm, svbfloat16_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmopa_za16, _bf16, _m)(0, pn, pm, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmops_za16_bf16( +// CHECK-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.mops.nxv8bf16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svmops_za16_bf16u10__SVBool_tS_u14__SVBfloat16_tS0_( +// CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.mops.nxv8bf16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmops_za16_bf16(svbool_t pn, svbool_t pm, svbfloat16_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmops_za16, _bf16, _m)(0, pn, pm, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmopa_za16_f16( +// CHECK-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv8f16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmopa_za16_f16u10__SVBool_tS_u13__SVFloat16_tS0_( +// CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv8f16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmopa_za16_f16(svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmopa_za16, _f16, _m)(0, pn, pm, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmops_za16_f16( +// CHECK-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.mops.nxv8f16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmops_za16_f16u10__SVBool_tS_u13__SVFloat16_tS0_( +// CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.mops.nxv8f16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmops_za16_f16(svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmops_za16, _f16, _m)(0, pn, pm, zn, zm); +} diff --git a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c new file mode 100644 index 000000000000..201ad4b8ff7f --- /dev/null +++ b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c @@ -0,0 +1,34 @@ +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -verify -emit-llvm %s + +// REQUIRES: aarch64-registered-target + +#include + +void test_features(svbool_t pn, svbool_t pm, + svfloat16_t zn, svfloat16_t zm, + svbfloat16_t znb, svbfloat16_t zmb) + __arm_streaming __arm_inout("za") { +// expected-error@+1 {{'svmopa_za16_bf16_m' needs target feature sme2,b16b16}} + svmopa_za16_bf16_m(0, pn, pm, znb, zmb); +// expected-error@+1 {{'svmops_za16_bf16_m' needs target feature sme2,b16b16}} + svmops_za16_bf16_m(0, pn, pm, znb, zmb); +// expected-error@+1 {{'svmopa_za16_f16_m' needs target feature sme-f16f16}} + svmopa_za16_f16_m(0, pn, pm, zn, zm); +// expected-error@+1 {{'svmops_za16_f16_m' needs target feature sme-f16f16}} + svmops_za16_f16_m(0, pn, pm, zn, zm); +} + +void test_imm(svbool_t pn, svbool_t pm, + svfloat16_t zn, svfloat16_t zm, + svbfloat16_t znb, svbfloat16_t zmb) + __arm_streaming __arm_inout("za") { +// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 1]}} + svmopa_za16_bf16_m(-1, pn, pm, znb, zmb); +// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 1]}} + svmops_za16_bf16_m(-1, pn, pm, znb, zmb); +// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 1]}} + svmopa_za16_f16_m(-1, pn, pm, zn, zm); +// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 1]}} + svmops_za16_f16_m(-1, pn, pm, zn, zm); +} + diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index e31e00a9c76f..e0630a6649dd 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -3649,3 +3649,6 @@ def int_aarch64_sve_pmov_to_pred_lane_zero : SVE2_1VectorArg_Pred_Intrinsic; def int_aarch64_sve_pmov_to_vector_lane_merging : SVE2_Pred_1VectorArgIndexed_Intrinsic; def int_aarch64_sve_pmov_to_vector_lane_zeroing : SVE2_Pred_1VectorArg_Intrinsic; + +def int_aarch64_sme_mopa_nonwide : SME_OuterProduct_Intrinsic; +def int_aarch64_sme_mops_nonwide : SME_OuterProduct_Intrinsic; diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index a2e8c530c1df..c5cbdce476ca 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -815,8 +815,8 @@ defm FMLS_VG4_M4Z2Z_H : sme2_dot_mla_add_sub_array_vg4_multi<"fmls", 0b0100011, defm FCVT_2ZZ_H : sme2p1_fp_cvt_vector_vg2_single<"fcvt", 0b0>; defm FCVTL_2ZZ_H : sme2p1_fp_cvt_vector_vg2_single<"fcvtl", 0b1>; -defm FMOPA_MPPZZ_H : sme2p1_fmop_tile_fp16<"fmopa", 0b0, 0b0, 0b11, ZPR16>; -defm FMOPS_MPPZZ_H : sme2p1_fmop_tile_fp16<"fmops", 0b0, 0b1, 0b11, ZPR16>; +defm FMOPA_MPPZZ_H : sme2p1_fmop_tile_fp16<"fmopa", 0b0, 0b0, nxv8f16, int_aarch64_sme_mopa>; +defm FMOPS_MPPZZ_H : sme2p1_fmop_tile_fp16<"fmops", 0b0, 0b1, nxv8f16, int_aarch64_sme_mops>; } let Predicates = [HasSME2, HasB16B16] in { @@ -862,8 +862,8 @@ defm BFMINNM_VG4_4Z2Z : sme2p1_bf_max_min_vector_vg4_multi<"bfminnm", 0b0010011 defm BFCLAMP_VG2_2ZZZ: sme2p1_bfclamp_vector_vg2_multi<"bfclamp">; defm BFCLAMP_VG4_4ZZZ: sme2p1_bfclamp_vector_vg4_multi<"bfclamp">; -defm BFMOPA_MPPZZ_H : sme2p1_fmop_tile_fp16<"bfmopa", 0b1, 0b0, 0b11, ZPR16>; -defm BFMOPS_MPPZZ_H : sme2p1_fmop_tile_fp16<"bfmops", 0b1, 0b1, 0b11, ZPR16>; +defm BFMOPA_MPPZZ_H : sme2p1_fmop_tile_fp16<"bfmopa", 0b1, 0b0, nxv8bf16, int_aarch64_sme_mopa>; +defm BFMOPS_MPPZZ_H : sme2p1_fmop_tile_fp16<"bfmops", 0b1, 0b1, nxv8bf16, int_aarch64_sme_mops>; } let Predicates = [HasSME2, HasFP8] in { @@ -925,7 +925,7 @@ defm FMLAL_VG4_M4ZZ_BtoH : sme2_fp_mla_long_array_vg4_single<"fmlal", 0b001, M defm FMLAL_VG2_M2Z2Z_BtoH : sme2_fp_mla_long_array_vg2_multi<"fmlal", 0b100, MatrixOp16, ZZ_b_mul_r, nxv16i8, null_frag>; defm FMLAL_VG4_M4Z4Z_BtoH : sme2_fp_mla_long_array_vg4_multi<"fmlal", 0b100, MatrixOp16, ZZZZ_b_mul_r, nxv16i8, null_frag>; -defm FMOPA_MPPZZ_BtoH : sme2p1_fmop_tile_fp16<"fmopa", 0b1, 0b0, 0b01, ZPR8>; +defm FMOPA_MPPZZ_BtoH : sme2p1_fmop_tile_f8f16<"fmopa", 0b1, 0b0, 0b01>; } //[HasSMEF8F16] diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 724dd07225cd..50ee37b0dfeb 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -286,14 +286,26 @@ multiclass sme_outer_product_fp64 def : SME_ZA_Tile_TwoPred_TwoVec_Pat; } -multiclass sme2p1_fmop_tile_fp16 op, ZPRRegOp zpr_ty>{ - def NAME : sme_fp_outer_product_inst { +multiclass sme2p1_fmop_tile_f8f16 op> { + def NAME : sme_fp_outer_product_inst { bits<1> ZAda; let Inst{2-1} = 0b00; let Inst{0} = ZAda; } } +multiclass sme2p1_fmop_tile_fp16 { + def NAME : sme_fp_outer_product_inst, SMEPseudo2Instr { + bits<1> ZAda; + let Inst{2-1} = 0b00; + let Inst{0} = ZAda; + } + + def NAME # _PSEUDO : sme_outer_product_pseudo, SMEPseudo2Instr; + + def : SME_ZA_Tile_TwoPred_TwoVec_Pat; +} + class sme_int_outer_product_inst opc, bit sz, bit sme2, MatrixTileOperand za_ty, ZPRRegOp zpr_ty, string mnemonic> diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-mopa.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-mopa.ll new file mode 100644 index 000000000000..fa0fd4360702 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-mopa.ll @@ -0,0 +1,42 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -verify-machineinstrs < %s | FileCheck %s + +target triple = "aarch64-linux" + +define void @mopa_bf16( %pn, %pm, %zn, %zm) #0 { +; CHECK-LABEL: mopa_bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: bfmopa za0.h, p0/m, p1/m, z0.h, z1.h +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.mopa.nxv8bf16(i32 0, %pn, %pm, %zn, %zm) + ret void +} + +define void @mopa_f16( %pn, %pm, %zn, %zm) #0 { +; CHECK-LABEL: mopa_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: fmopa za1.h, p0/m, p1/m, z0.h, z1.h +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.mopa.nxv8f16(i32 1, %pn, %pm, %zn, %zm) + ret void +} + +define void @mops_bf16( %pn, %pm, %zn, %zm) #0 { +; CHECK-LABEL: mops_bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: bfmops za0.h, p0/m, p1/m, z0.h, z1.h +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.mops.nxv8bf16(i32 0, %pn, %pm, %zn, %zm) + ret void +} + +define void @mops_f16( %pn, %pm, %zn, %zm) #0 { +; CHECK-LABEL: mops_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: fmops za1.h, p0/m, p1/m, z0.h, z1.h +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.mops.nxv8f16(i32 1, %pn, %pm, %zn, %zm) + ret void +} + +attributes #0 = {nounwind "target-features" = "+sme,+sme2p1,+bf16,+sme-f16f16,+b16b16" } -- GitLab From f5e49279c01436971001e107a0a3435510b9ae98 Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Fri, 10 May 2024 13:02:05 +0200 Subject: [PATCH 251/328] AMDGPU: fix isSafeToSink expecting exactly one predecessor (#89224) isSafeToSink needs to check if machine cycle has divergent exit branch but first it needs the MBB that contains cycle exit branch. Early-tailduplication can delete exit block created by structurize-cfg so there is still exactly one cycle exit block but the new cycle exit block can have multiple predecessors. Simplify search for MBBs that contain cycle exit branch by introducing helper method getExitingBlocks in GenericCycle. Fixes #89200 --- llvm/include/llvm/ADT/GenericCycleImpl.h | 15 +++ llvm/include/llvm/ADT/GenericCycleInfo.h | 4 + llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 12 +-- .../AMDGPU/GlobalISel/is-safe-to-sink-bug.ll | 93 +++++++++++++++++++ 4 files changed, 117 insertions(+), 7 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll diff --git a/llvm/include/llvm/ADT/GenericCycleImpl.h b/llvm/include/llvm/ADT/GenericCycleImpl.h index 74faff98b903..ab9c421a4469 100644 --- a/llvm/include/llvm/ADT/GenericCycleImpl.h +++ b/llvm/include/llvm/ADT/GenericCycleImpl.h @@ -66,6 +66,21 @@ void GenericCycle::getExitBlocks( } } +template +void GenericCycle::getExitingBlocks( + SmallVectorImpl &TmpStorage) const { + TmpStorage.clear(); + + for (BlockT *Block : blocks()) { + for (BlockT *Succ : successors(Block)) { + if (!contains(Succ)) { + TmpStorage.push_back(Block); + break; + } + } + } +} + template auto GenericCycle::getCyclePreheader() const -> BlockT * { BlockT *Predecessor = getCyclePredecessor(); diff --git a/llvm/include/llvm/ADT/GenericCycleInfo.h b/llvm/include/llvm/ADT/GenericCycleInfo.h index 83c4c2759d46..b601fc9bae38 100644 --- a/llvm/include/llvm/ADT/GenericCycleInfo.h +++ b/llvm/include/llvm/ADT/GenericCycleInfo.h @@ -126,6 +126,10 @@ public: /// branched to. void getExitBlocks(SmallVectorImpl &TmpStorage) const; + /// Return all blocks of this cycle that have successor outside of this cycle. + /// These blocks have cycle exit branch. + void getExitingBlocks(SmallVectorImpl &TmpStorage) const; + /// Return the preheader block for this cycle. Pre-header is well-defined for /// reducible cycle in docs/LoopTerminology.rst as: the only one entering /// block and its only edge is to the entry block. Return null for irreducible diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 6599d0abd135..08351c49b223 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -213,15 +213,13 @@ bool SIInstrInfo::isSafeToSink(MachineInstr &MI, // Check if there is a FromCycle that contains SgprDef's basic block but // does not contain SuccToSinkTo and also has divergent exit condition. while (FromCycle && !FromCycle->contains(ToCycle)) { - // After structurize-cfg, there should be exactly one cycle exit. - SmallVector ExitBlocks; - FromCycle->getExitBlocks(ExitBlocks); - assert(ExitBlocks.size() == 1); - assert(ExitBlocks[0]->getSinglePredecessor()); + SmallVector ExitingBlocks; + FromCycle->getExitingBlocks(ExitingBlocks); // FromCycle has divergent exit condition. - if (hasDivergentBranch(ExitBlocks[0]->getSinglePredecessor())) { - return false; + for (MachineBasicBlock *ExitingBlock : ExitingBlocks) { + if (hasDivergentBranch(ExitingBlock)) + return false; } FromCycle = FromCycle->getParentCycle(); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll new file mode 100644 index 000000000000..d3bc661f5940 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll @@ -0,0 +1,93 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -global-isel -verify-machineinstrs < %s | FileCheck %s + +; early-tailduplication deletes cycle exit block created by structurize-cfg +; that had exactly one predecessor. Now, new cycle exit block has two +; predecessors, we need to find predecessor that belongs to the cycle. + +define amdgpu_ps void @_amdgpu_ps_main(i1 %arg) { +; CHECK-LABEL: _amdgpu_ps_main: +; CHECK: ; %bb.0: ; %bb +; CHECK-NEXT: s_mov_b32 s4, 0 +; CHECK-NEXT: v_and_b32_e32 v0, 1, v0 +; CHECK-NEXT: s_mov_b32 s5, s4 +; CHECK-NEXT: s_mov_b32 s6, s4 +; CHECK-NEXT: s_mov_b32 s7, s4 +; CHECK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 +; CHECK-NEXT: s_buffer_load_dword s1, s[4:7], 0x0 +; CHECK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 +; CHECK-NEXT: s_mov_b32 s10, -1 +; CHECK-NEXT: s_mov_b32 s11, 0x31c16000 +; CHECK-NEXT: s_add_u32 s8, s8, s0 +; CHECK-NEXT: v_cmp_ne_u32_e64 s0, 0, v0 +; CHECK-NEXT: s_addc_u32 s9, s9, 0 +; CHECK-NEXT: s_mov_b32 s32, 0 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_cmp_ge_i32 s1, 0 +; CHECK-NEXT: s_cbranch_scc0 .LBB0_2 +; CHECK-NEXT: .LBB0_1: ; %bb12 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s4 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, 0 +; CHECK-NEXT: v_mov_b32_e32 v3, 0 +; CHECK-NEXT: v_mov_b32_e32 v4, 0 +; CHECK-NEXT: s_mov_b64 s[0:1], s[8:9] +; CHECK-NEXT: s_mov_b64 s[2:3], s[10:11] +; CHECK-NEXT: s_swappc_b64 s[30:31], 0 +; CHECK-NEXT: .LBB0_2: ; %bb2.preheader +; CHECK-NEXT: s_mov_b32 s1, 0 +; CHECK-NEXT: v_mov_b32_e32 v0, s1 +; CHECK-NEXT: s_branch .LBB0_4 +; CHECK-NEXT: .p2align 6 +; CHECK-NEXT: .LBB0_3: ; %bb6 +; CHECK-NEXT: ; in Loop: Header=BB0_4 Depth=1 +; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s3 +; CHECK-NEXT: s_and_b32 s2, 1, s2 +; CHECK-NEXT: v_or_b32_e32 v1, 1, v0 +; CHECK-NEXT: v_cmp_ne_u32_e64 s2, 0, s2 +; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v0 +; CHECK-NEXT: v_mov_b32_e32 v0, v1 +; CHECK-NEXT: s_and_b32 s4, s2, s1 +; CHECK-NEXT: s_andn2_b32 s1, s1, exec_lo +; CHECK-NEXT: s_and_b32 s2, exec_lo, s4 +; CHECK-NEXT: s_or_b32 s1, s1, s2 +; CHECK-NEXT: s_cbranch_vccz .LBB0_1 +; CHECK-NEXT: .LBB0_4: ; %bb2 +; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: s_mov_b32 s2, 0 +; CHECK-NEXT: s_and_saveexec_b32 s3, s0 +; CHECK-NEXT: s_cbranch_execz .LBB0_3 +; CHECK-NEXT: ; %bb.5: ; %bb5 +; CHECK-NEXT: ; in Loop: Header=BB0_4 Depth=1 +; CHECK-NEXT: s_mov_b32 s2, 1 +; CHECK-NEXT: s_branch .LBB0_3 +bb: + %i = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> zeroinitializer, i32 0, i32 0) + %i1 = icmp slt i32 %i, 0 + br i1 %i1, label %bb2, label %bb12 + +bb2: + %i3 = phi i1 [ %i9, %bb6 ], [ false, %bb ] + %i4 = phi i32 [ %i10, %bb6 ], [ 0, %bb ] + br i1 %arg, label %bb5, label %bb6 + +bb5: + br label %bb6 + +bb6: + %i7 = phi i32 [ 0, %bb2 ], [ 1, %bb5 ] + %i8 = icmp ne i32 %i7, 0 + %i9 = select i1 %i8, i1 %i3, i1 false + %i10 = or i32 %i4, 1 + %i11 = icmp slt i32 %i4, 0 + br i1 %i11, label %bb2, label %bb12 + +bb12: + %i13 = phi i1 [ false, %bb ], [ %i9, %bb6 ] + %i14 = select i1 %i13, float 0.000000e+00, float 1.000000e+00 + %i15 = insertelement <4 x float> zeroinitializer, float %i14, i64 0 + call amdgpu_gfx addrspace(4) void null(<4 x float> %i15, i32 0) + unreachable +} + +declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) -- GitLab From 73681b8fee930274e6dc11d4471b44666d6d0dfd Mon Sep 17 00:00:00 2001 From: Paul Walker Date: Fri, 10 May 2024 12:12:44 +0100 Subject: [PATCH 252/328] [NFC][LLVM] Simplify SVE isel DAG patterns. (#91510) We have many instances of (Ty ZPR:$op) than can be written as Ty:$Op. Whilst other operands can also be simplified this patch focuses on removing redundant instances of PPR, PNR and ZPR only. --- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 624 +++++++++--------- 1 file changed, 311 insertions(+), 313 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 64e545aa26b4..d4405a230613 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1269,33 +1269,33 @@ let Predicates = [HasSVE] in { multiclass sve_masked_gather_x2_scaled { // base + vector of scaled offsets - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (nxv2i64 ZPR:$offs))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, GPR64:$base, nxv2i64:$offs)), (!cast(Inst # _SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of signed 32bit scaled offsets - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (sext_inreg (nxv2i64 ZPR:$offs), nxv2i32))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, GPR64:$base, (sext_inreg nxv2i64:$offs, nxv2i32))), (!cast(Inst # _SXTW_SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of unsigned 32bit scaled offsets - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (and (nxv2i64 ZPR:$offs), (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, GPR64:$base, (and nxv2i64:$offs, (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))))), (!cast(Inst # _UXTW_SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>; } multiclass sve_masked_gather_x2_unscaled { // vector of pointers + immediate offset (includes zero) - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), (i64 ImmTy:$imm), (nxv2i64 ZPR:$ptrs))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, (i64 ImmTy:$imm), nxv2i64:$ptrs)), (!cast(Inst # _IMM) PPR:$gp, ZPR:$ptrs, ImmTy:$imm)>; // base + vector of offsets - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (nxv2i64 ZPR:$offs))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, GPR64:$base, nxv2i64:$offs)), (!cast(Inst) PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of signed 32bit offsets - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (sext_inreg (nxv2i64 ZPR:$offs), nxv2i32))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, GPR64:$base, (sext_inreg nxv2i64:$offs, nxv2i32))), (!cast(Inst # _SXTW) PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of unsigned 32bit offsets - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (and (nxv2i64 ZPR:$offs), (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, GPR64:$base, (and nxv2i64:$offs, (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))))), (!cast(Inst # _UXTW) PPR:$gp, GPR64:$base, ZPR:$offs)>; } multiclass sve_masked_gather_x4 { - def : Pat<(Ty (Load (SVEDup0Undef), (nxv4i1 PPR:$gp), GPR64:$base, (nxv4i32 ZPR:$offs))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv4i1:$gp, GPR64:$base, nxv4i32:$offs)), (Inst PPR:$gp, GPR64:$base, ZPR:$offs)>; } @@ -1503,33 +1503,33 @@ let Predicates = [HasSVE] in { multiclass sve_masked_scatter_x2_scaled { // base + vector of scaled offsets - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), GPR64:$base, (nxv2i64 ZPR:$offs)), + def : Pat<(Store Ty:$data, nxv2i1:$gp, GPR64:$base, nxv2i64:$offs), (!cast(Inst # _SCALED) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of signed 32bit scaled offsets - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), GPR64:$base, (sext_inreg (nxv2i64 ZPR:$offs), nxv2i32)), + def : Pat<(Store Ty:$data, nxv2i1:$gp, GPR64:$base, (sext_inreg nxv2i64:$offs, nxv2i32)), (!cast(Inst # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of unsigned 32bit scaled offsets - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), GPR64:$base, (and (nxv2i64 ZPR:$offs), (nxv2i64 (splat_vector (i64 0xFFFFFFFF))))), + def : Pat<(Store Ty:$data, nxv2i1:$gp, GPR64:$base, (and nxv2i64:$offs, (nxv2i64 (splat_vector (i64 0xFFFFFFFF))))), (!cast(Inst # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; } multiclass sve_masked_scatter_x2_unscaled { // vector of pointers + immediate offset (includes zero) - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), (i64 ImmTy:$imm), (nxv2i64 ZPR:$ptrs)), + def : Pat<(Store Ty:$data, nxv2i1:$gp, (i64 ImmTy:$imm), nxv2i64:$ptrs), (!cast(Inst # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, ImmTy:$imm)>; // base + vector of offsets - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), GPR64:$base, (nxv2i64 ZPR:$offs)), + def : Pat<(Store Ty:$data, nxv2i1:$gp, GPR64:$base, nxv2i64:$offs), (!cast(Inst) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of signed 32bit offsets - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), GPR64:$base, (sext_inreg (nxv2i64 ZPR:$offs), nxv2i32)), + def : Pat<(Store Ty:$data, nxv2i1:$gp, GPR64:$base, (sext_inreg nxv2i64:$offs, nxv2i32)), (!cast(Inst # _SXTW) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of unsigned 32bit offsets - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), GPR64:$base, (and (nxv2i64 ZPR:$offs), (nxv2i64 (splat_vector (i64 0xFFFFFFFF))))), + def : Pat<(Store Ty:$data, nxv2i1:$gp, GPR64:$base, (and nxv2i64:$offs, (nxv2i64 (splat_vector (i64 0xFFFFFFFF))))), (!cast(Inst # _UXTW) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; } multiclass sve_masked_scatter_x4 { - def : Pat<(Store (Ty ZPR:$data), (nxv4i1 PPR:$gp), GPR64:$base, (nxv4i32 ZPR:$offs)), + def : Pat<(Store Ty:$data, nxv4i1:$gp, GPR64:$base, nxv4i32:$offs), (Inst ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; } @@ -1791,159 +1791,159 @@ let Predicates = [HasSVEorSME] in { defm TRN2_PPP : sve_int_perm_bin_perm_pp<0b101, "trn2", AArch64trn2, int_aarch64_sve_trn2_b16, int_aarch64_sve_trn2_b32, int_aarch64_sve_trn2_b64>; // Extract lo/hi halves of legal predicate types. - def : Pat<(nxv1i1 (extract_subvector (nxv2i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv1i1 (extract_subvector nxv2i1:$Ps, (i64 0))), (PUNPKLO_PP PPR:$Ps)>; - def : Pat<(nxv1i1 (extract_subvector (nxv2i1 PPR:$Ps), (i64 1))), + def : Pat<(nxv1i1 (extract_subvector nxv2i1:$Ps, (i64 1))), (PUNPKHI_PP PPR:$Ps)>; - def : Pat<(nxv2i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv2i1 (extract_subvector nxv4i1:$Ps, (i64 0))), (PUNPKLO_PP PPR:$Ps)>; - def : Pat<(nxv2i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 2))), + def : Pat<(nxv2i1 (extract_subvector nxv4i1:$Ps, (i64 2))), (PUNPKHI_PP PPR:$Ps)>; - def : Pat<(nxv4i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv4i1 (extract_subvector nxv8i1:$Ps, (i64 0))), (PUNPKLO_PP PPR:$Ps)>; - def : Pat<(nxv4i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 4))), + def : Pat<(nxv4i1 (extract_subvector nxv8i1:$Ps, (i64 4))), (PUNPKHI_PP PPR:$Ps)>; - def : Pat<(nxv8i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv8i1 (extract_subvector nxv16i1:$Ps, (i64 0))), (PUNPKLO_PP PPR:$Ps)>; - def : Pat<(nxv8i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 8))), + def : Pat<(nxv8i1 (extract_subvector nxv16i1:$Ps, (i64 8))), (PUNPKHI_PP PPR:$Ps)>; - def : Pat<(nxv1i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv1i1 (extract_subvector nxv4i1:$Ps, (i64 0))), (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))>; - def : Pat<(nxv1i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 1))), + def : Pat<(nxv1i1 (extract_subvector nxv4i1:$Ps, (i64 1))), (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))>; - def : Pat<(nxv1i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 2))), + def : Pat<(nxv1i1 (extract_subvector nxv4i1:$Ps, (i64 2))), (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))>; - def : Pat<(nxv1i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 3))), + def : Pat<(nxv1i1 (extract_subvector nxv4i1:$Ps, (i64 3))), (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))>; - def : Pat<(nxv2i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv2i1 (extract_subvector nxv8i1:$Ps, (i64 0))), (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))>; - def : Pat<(nxv2i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 2))), + def : Pat<(nxv2i1 (extract_subvector nxv8i1:$Ps, (i64 2))), (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))>; - def : Pat<(nxv2i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 4))), + def : Pat<(nxv2i1 (extract_subvector nxv8i1:$Ps, (i64 4))), (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))>; - def : Pat<(nxv2i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 6))), + def : Pat<(nxv2i1 (extract_subvector nxv8i1:$Ps, (i64 6))), (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))>; - def : Pat<(nxv4i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv4i1 (extract_subvector nxv16i1:$Ps, (i64 0))), (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))>; - def : Pat<(nxv4i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 4))), + def : Pat<(nxv4i1 (extract_subvector nxv16i1:$Ps, (i64 4))), (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))>; - def : Pat<(nxv4i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 8))), + def : Pat<(nxv4i1 (extract_subvector nxv16i1:$Ps, (i64 8))), (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))>; - def : Pat<(nxv4i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 12))), + def : Pat<(nxv4i1 (extract_subvector nxv16i1:$Ps, (i64 12))), (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 0))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 1))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 1))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 2))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 2))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 3))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 3))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 4))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 4))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 5))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 5))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 6))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 6))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 7))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 7))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 0))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 2))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 2))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 4))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 4))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 6))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 6))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 8))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 8))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 10))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 10))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 12))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 12))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 14))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 14))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 0))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 1))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 1))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 2))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 2))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 3))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 3))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 4))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 4))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 5))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 5))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 6))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 6))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 7))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 7))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 8))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 8))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 9))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 9))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 10))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 10))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 11))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 11))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 12))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 12))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 13))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 13))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 14))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 14))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 15))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 15))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))))>; // Extract subvectors from FP SVE vectors - def : Pat<(nxv2f16 (extract_subvector (nxv4f16 ZPR:$Zs), (i64 0))), + def : Pat<(nxv2f16 (extract_subvector nxv4f16:$Zs, (i64 0))), (UUNPKLO_ZZ_D ZPR:$Zs)>; - def : Pat<(nxv2f16 (extract_subvector (nxv4f16 ZPR:$Zs), (i64 2))), + def : Pat<(nxv2f16 (extract_subvector nxv4f16:$Zs, (i64 2))), (UUNPKHI_ZZ_D ZPR:$Zs)>; - def : Pat<(nxv4f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 0))), + def : Pat<(nxv4f16 (extract_subvector nxv8f16:$Zs, (i64 0))), (UUNPKLO_ZZ_S ZPR:$Zs)>; - def : Pat<(nxv4f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 4))), + def : Pat<(nxv4f16 (extract_subvector nxv8f16:$Zs, (i64 4))), (UUNPKHI_ZZ_S ZPR:$Zs)>; - def : Pat<(nxv2f32 (extract_subvector (nxv4f32 ZPR:$Zs), (i64 0))), + def : Pat<(nxv2f32 (extract_subvector nxv4f32:$Zs, (i64 0))), (UUNPKLO_ZZ_D ZPR:$Zs)>; - def : Pat<(nxv2f32 (extract_subvector (nxv4f32 ZPR:$Zs), (i64 2))), + def : Pat<(nxv2f32 (extract_subvector nxv4f32:$Zs, (i64 2))), (UUNPKHI_ZZ_D ZPR:$Zs)>; - def : Pat<(nxv2bf16 (extract_subvector (nxv4bf16 ZPR:$Zs), (i64 0))), + def : Pat<(nxv2bf16 (extract_subvector nxv4bf16:$Zs, (i64 0))), (UUNPKLO_ZZ_D ZPR:$Zs)>; - def : Pat<(nxv2bf16 (extract_subvector (nxv4bf16 ZPR:$Zs), (i64 2))), + def : Pat<(nxv2bf16 (extract_subvector nxv4bf16:$Zs, (i64 2))), (UUNPKHI_ZZ_D ZPR:$Zs)>; - def : Pat<(nxv4bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 0))), + def : Pat<(nxv4bf16 (extract_subvector nxv8bf16:$Zs, (i64 0))), (UUNPKLO_ZZ_S ZPR:$Zs)>; - def : Pat<(nxv4bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 4))), + def : Pat<(nxv4bf16 (extract_subvector nxv8bf16:$Zs, (i64 4))), (UUNPKHI_ZZ_S ZPR:$Zs)>; - def : Pat<(nxv2f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 0))), + def : Pat<(nxv2f16 (extract_subvector nxv8f16:$Zs, (i64 0))), (UUNPKLO_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 2))), + def : Pat<(nxv2f16 (extract_subvector nxv8f16:$Zs, (i64 2))), (UUNPKHI_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 4))), + def : Pat<(nxv2f16 (extract_subvector nxv8f16:$Zs, (i64 4))), (UUNPKLO_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 6))), + def : Pat<(nxv2f16 (extract_subvector nxv8f16:$Zs, (i64 6))), (UUNPKHI_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 0))), + def : Pat<(nxv2bf16 (extract_subvector nxv8bf16:$Zs, (i64 0))), (UUNPKLO_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 2))), + def : Pat<(nxv2bf16 (extract_subvector nxv8bf16:$Zs, (i64 2))), (UUNPKHI_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 4))), + def : Pat<(nxv2bf16 (extract_subvector nxv8bf16:$Zs, (i64 4))), (UUNPKLO_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 6))), + def : Pat<(nxv2bf16 (extract_subvector nxv8bf16:$Zs, (i64 6))), (UUNPKHI_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>; // extract/insert 64-bit fixed length vector from/into a scalable vector foreach VT = [v8i8, v4i16, v2i32, v1i64, v4f16, v2f32, v1f64, v4bf16] in { - def : Pat<(VT (vector_extract_subvec (SVEContainerVT.Value ZPR:$Zs), (i64 0))), + def : Pat<(VT (vector_extract_subvec SVEContainerVT.Value:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, dsub)>; def : Pat<(SVEContainerVT.Value (vector_insert_subvec undef, (VT V64:$src), (i64 0))), (INSERT_SUBREG (IMPLICIT_DEF), $src, dsub)>; @@ -1951,7 +1951,7 @@ let Predicates = [HasSVEorSME] in { // extract/insert 128-bit fixed length vector from/into a scalable vector foreach VT = [v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64, v8bf16] in { - def : Pat<(VT (vector_extract_subvec (SVEContainerVT.Value ZPR:$Zs), (i64 0))), + def : Pat<(VT (vector_extract_subvec SVEContainerVT.Value:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, zsub)>; def : Pat<(SVEContainerVT.Value (vector_insert_subvec undef, (VT V128:$src), (i64 0))), (INSERT_SUBREG (IMPLICIT_DEF), $src, zsub)>; @@ -1980,34 +1980,34 @@ let Predicates = [HasSVEorSME] in { (UZP1_ZZZ_H $v1, $v2)>; // Splice with lane equal to -1 - def : Pat<(nxv16i8 (vector_splice (nxv16i8 ZPR:$Z1), (nxv16i8 ZPR:$Z2), (i64 -1))), + def : Pat<(nxv16i8 (vector_splice nxv16i8:$Z1, nxv16i8:$Z2, (i64 -1))), (INSR_ZV_B ZPR:$Z2, (INSERT_SUBREG (IMPLICIT_DEF), (LASTB_VPZ_B (PTRUE_B 31), ZPR:$Z1), bsub))>; - def : Pat<(nxv8i16 (vector_splice (nxv8i16 ZPR:$Z1), (nxv8i16 ZPR:$Z2), (i64 -1))), + def : Pat<(nxv8i16 (vector_splice nxv8i16:$Z1, nxv8i16:$Z2, (i64 -1))), (INSR_ZV_H ZPR:$Z2, (INSERT_SUBREG (IMPLICIT_DEF), (LASTB_VPZ_H (PTRUE_H 31), ZPR:$Z1), hsub))>; - def : Pat<(nxv4i32 (vector_splice (nxv4i32 ZPR:$Z1), (nxv4i32 ZPR:$Z2), (i64 -1))), + def : Pat<(nxv4i32 (vector_splice nxv4i32:$Z1, nxv4i32:$Z2, (i64 -1))), (INSR_ZV_S ZPR:$Z2, (INSERT_SUBREG (IMPLICIT_DEF), (LASTB_VPZ_S (PTRUE_S 31), ZPR:$Z1), ssub))>; - def : Pat<(nxv2i64 (vector_splice (nxv2i64 ZPR:$Z1), (nxv2i64 ZPR:$Z2), (i64 -1))), + def : Pat<(nxv2i64 (vector_splice nxv2i64:$Z1, nxv2i64:$Z2, (i64 -1))), (INSR_ZV_D ZPR:$Z2, (INSERT_SUBREG (IMPLICIT_DEF), (LASTB_VPZ_D (PTRUE_D 31), ZPR:$Z1), dsub))>; // Splice with lane bigger or equal to 0 foreach VT = [nxv16i8] in - def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_255 i32:$index)))), + def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_255 i32:$index)))), (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; foreach VT = [nxv8i16, nxv8f16, nxv8bf16] in - def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_127 i32:$index)))), + def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_127 i32:$index)))), (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; foreach VT = [nxv4i32, nxv4f16, nxv4f32, nxv4bf16] in - def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_63 i32:$index)))), + def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_63 i32:$index)))), (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; foreach VT = [nxv2i64, nxv2f16, nxv2f32, nxv2f64, nxv2bf16] in - def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_31 i32:$index)))), + def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_31 i32:$index)))), (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs", SETUGE, SETULE>; @@ -2263,59 +2263,59 @@ let Predicates = [HasSVEorSME] in { defm FCVTZU_ZPmZ_DtoD : sve_fp_2op_p_zd< 0b1111111, "fcvtzu", ZPR64, ZPR64, null_frag, AArch64fcvtzu_mt, nxv2i64, nxv2i1, nxv2f64, ElementSizeD>; //These patterns exist to improve the code quality of conversions on unpacked types. - def : Pat<(nxv2f32 (AArch64fcvte_mt (nxv2i1 (SVEAllActive):$Pg), (nxv2f16 ZPR:$Zs), (nxv2f32 ZPR:$Zd))), + def : Pat<(nxv2f32 (AArch64fcvte_mt (nxv2i1 (SVEAllActive:$Pg)), nxv2f16:$Zs, nxv2f32:$Zd)), (FCVT_ZPmZ_HtoS_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; // FP_ROUND has an additional 'precise' flag which indicates the type of rounding. // This is ignored by the pattern below where it is matched by (i64 timm0_1) - def : Pat<(nxv2f16 (AArch64fcvtr_mt (nxv2i1 (SVEAllActive):$Pg), (nxv2f32 ZPR:$Zs), (i64 timm0_1), (nxv2f16 ZPR:$Zd))), + def : Pat<(nxv2f16 (AArch64fcvtr_mt (nxv2i1 (SVEAllActive:$Pg)), nxv2f32:$Zs, (i64 timm0_1), nxv2f16:$Zd)), (FCVT_ZPmZ_StoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; // Signed integer -> Floating-point def : Pat<(nxv2f16 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (nxv2f16 ZPR:$Zd))), + (sext_inreg nxv2i64:$Zs, nxv2i16), nxv2f16:$Zd)), (SCVTF_ZPmZ_HtoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; def : Pat<(nxv4f16 (AArch64scvtf_mt (nxv4i1 (SVEAllActive):$Pg), - (sext_inreg (nxv4i32 ZPR:$Zs), nxv4i16), (nxv4f16 ZPR:$Zd))), + (sext_inreg nxv4i32:$Zs, nxv4i16), nxv4f16:$Zd)), (SCVTF_ZPmZ_HtoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; def : Pat<(nxv2f16 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (nxv2f16 ZPR:$Zd))), + (sext_inreg nxv2i64:$Zs, nxv2i32), nxv2f16:$Zd)), (SCVTF_ZPmZ_StoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; def : Pat<(nxv2f32 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (nxv2f32 ZPR:$Zd))), + (sext_inreg nxv2i64:$Zs, nxv2i32), nxv2f32:$Zd)), (SCVTF_ZPmZ_StoS_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; def : Pat<(nxv2f64 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (nxv2f64 ZPR:$Zd))), + (sext_inreg nxv2i64:$Zs, nxv2i32), nxv2f64:$Zd)), (SCVTF_ZPmZ_StoD_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; // Unsigned integer -> Floating-point - def : Pat<(nxv2f16 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (and (nxv2i64 ZPR:$Zs), - (nxv2i64 (splat_vector (i64 0xFFFF)))), (nxv2f16 ZPR:$Zd))), + def : Pat<(nxv2f16 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive:$Pg)), + (and nxv2i64:$Zs, + (nxv2i64 (splat_vector (i64 0xFFFF)))), nxv2f16:$Zd)), (UCVTF_ZPmZ_HtoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv2f16 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (and (nxv2i64 ZPR:$Zs), - (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))), (nxv2f16 ZPR:$Zd))), + def : Pat<(nxv2f16 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive:$Pg)), + (and nxv2i64:$Zs, + (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))), nxv2f16:$Zd)), (UCVTF_ZPmZ_StoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv4f16 (AArch64ucvtf_mt (nxv4i1 (SVEAllActive):$Pg), - (and (nxv4i32 ZPR:$Zs), - (nxv4i32 (splat_vector (i32 0xFFFF)))), (nxv4f16 ZPR:$Zd))), + def : Pat<(nxv4f16 (AArch64ucvtf_mt (nxv4i1 (SVEAllActive:$Pg)), + (and nxv4i32:$Zs, + (nxv4i32 (splat_vector (i32 0xFFFF)))), nxv4f16:$Zd)), (UCVTF_ZPmZ_HtoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv2f32 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (and (nxv2i64 ZPR:$Zs), - (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))), (nxv2f32 ZPR:$Zd))), + def : Pat<(nxv2f32 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive:$Pg)), + (and nxv2i64:$Zs, + (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))), nxv2f32:$Zd)), (UCVTF_ZPmZ_StoS_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv2f64 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (and (nxv2i64 ZPR:$Zs), - (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))), (nxv2f64 ZPR:$Zd))), + def : Pat<(nxv2f64 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive:$Pg)), + (and nxv2i64:$Zs, + (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))), nxv2f64:$Zd)), (UCVTF_ZPmZ_StoD_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; defm FRINTN_ZPmZ : sve_fp_2op_p_zd_HSD<0b00000, "frintn", AArch64frintn_mt>; @@ -2510,12 +2510,12 @@ let Predicates = [HasSVEorSME] in { defm : ld1rq_pat; defm : ld1rq_pat; - def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (SXTW_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; - def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (SXTH_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; - def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i8), (SXTB_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; - def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i16), (SXTH_ZPmZ_S_UNDEF (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>; - def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i8), (SXTB_ZPmZ_S_UNDEF (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>; - def : Pat<(sext_inreg (nxv8i16 ZPR:$Zs), nxv8i8), (SXTB_ZPmZ_H_UNDEF (IMPLICIT_DEF), (PTRUE_H 31), ZPR:$Zs)>; + def : Pat<(sext_inreg nxv2i64:$Zs, nxv2i32), (SXTW_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; + def : Pat<(sext_inreg nxv2i64:$Zs, nxv2i16), (SXTH_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; + def : Pat<(sext_inreg nxv2i64:$Zs, nxv2i8), (SXTB_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; + def : Pat<(sext_inreg nxv4i32:$Zs, nxv4i16), (SXTH_ZPmZ_S_UNDEF (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>; + def : Pat<(sext_inreg nxv4i32:$Zs, nxv4i8), (SXTB_ZPmZ_S_UNDEF (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>; + def : Pat<(sext_inreg nxv8i16:$Zs, nxv8i8), (SXTB_ZPmZ_H_UNDEF (IMPLICIT_DEF), (PTRUE_H 31), ZPR:$Zs)>; // General case that we ideally never want to match. def : Pat<(vscale GPR64:$scale), (MADDXrrr (UBFMXri (RDVLI_XI 1), 4, 63), $scale, XZR)>; @@ -2621,109 +2621,109 @@ let Predicates = [HasSVEorSME] in { // constraint that none of the bits change when stored to memory as one // type, and reloaded as another type. let Predicates = [IsLE] in { - def : Pat<(nxv16i8 (bitconvert (nxv8i16 ZPR:$src))), (nxv16i8 ZPR:$src)>; - def : Pat<(nxv16i8 (bitconvert (nxv4i32 ZPR:$src))), (nxv16i8 ZPR:$src)>; - def : Pat<(nxv16i8 (bitconvert (nxv2i64 ZPR:$src))), (nxv16i8 ZPR:$src)>; - def : Pat<(nxv16i8 (bitconvert (nxv8f16 ZPR:$src))), (nxv16i8 ZPR:$src)>; - def : Pat<(nxv16i8 (bitconvert (nxv4f32 ZPR:$src))), (nxv16i8 ZPR:$src)>; - def : Pat<(nxv16i8 (bitconvert (nxv2f64 ZPR:$src))), (nxv16i8 ZPR:$src)>; - - def : Pat<(nxv8i16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8i16 ZPR:$src)>; - def : Pat<(nxv8i16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8i16 ZPR:$src)>; - def : Pat<(nxv8i16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8i16 ZPR:$src)>; - def : Pat<(nxv8i16 (bitconvert (nxv8f16 ZPR:$src))), (nxv8i16 ZPR:$src)>; - def : Pat<(nxv8i16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8i16 ZPR:$src)>; - def : Pat<(nxv8i16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8i16 ZPR:$src)>; - - def : Pat<(nxv4i32 (bitconvert (nxv16i8 ZPR:$src))), (nxv4i32 ZPR:$src)>; - def : Pat<(nxv4i32 (bitconvert (nxv8i16 ZPR:$src))), (nxv4i32 ZPR:$src)>; - def : Pat<(nxv4i32 (bitconvert (nxv2i64 ZPR:$src))), (nxv4i32 ZPR:$src)>; - def : Pat<(nxv4i32 (bitconvert (nxv8f16 ZPR:$src))), (nxv4i32 ZPR:$src)>; - def : Pat<(nxv4i32 (bitconvert (nxv4f32 ZPR:$src))), (nxv4i32 ZPR:$src)>; - def : Pat<(nxv4i32 (bitconvert (nxv2f64 ZPR:$src))), (nxv4i32 ZPR:$src)>; - - def : Pat<(nxv2i64 (bitconvert (nxv16i8 ZPR:$src))), (nxv2i64 ZPR:$src)>; - def : Pat<(nxv2i64 (bitconvert (nxv8i16 ZPR:$src))), (nxv2i64 ZPR:$src)>; - def : Pat<(nxv2i64 (bitconvert (nxv4i32 ZPR:$src))), (nxv2i64 ZPR:$src)>; - def : Pat<(nxv2i64 (bitconvert (nxv8f16 ZPR:$src))), (nxv2i64 ZPR:$src)>; - def : Pat<(nxv2i64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2i64 ZPR:$src)>; - def : Pat<(nxv2i64 (bitconvert (nxv2f64 ZPR:$src))), (nxv2i64 ZPR:$src)>; - - def : Pat<(nxv8f16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8f16 ZPR:$src)>; - def : Pat<(nxv8f16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8f16 ZPR:$src)>; - def : Pat<(nxv8f16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8f16 ZPR:$src)>; - def : Pat<(nxv8f16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8f16 ZPR:$src)>; - def : Pat<(nxv8f16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8f16 ZPR:$src)>; - def : Pat<(nxv8f16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8f16 ZPR:$src)>; - - def : Pat<(nxv4f32 (bitconvert (nxv16i8 ZPR:$src))), (nxv4f32 ZPR:$src)>; - def : Pat<(nxv4f32 (bitconvert (nxv8i16 ZPR:$src))), (nxv4f32 ZPR:$src)>; - def : Pat<(nxv4f32 (bitconvert (nxv4i32 ZPR:$src))), (nxv4f32 ZPR:$src)>; - def : Pat<(nxv4f32 (bitconvert (nxv2i64 ZPR:$src))), (nxv4f32 ZPR:$src)>; - def : Pat<(nxv4f32 (bitconvert (nxv8f16 ZPR:$src))), (nxv4f32 ZPR:$src)>; - def : Pat<(nxv4f32 (bitconvert (nxv2f64 ZPR:$src))), (nxv4f32 ZPR:$src)>; - - def : Pat<(nxv2f64 (bitconvert (nxv16i8 ZPR:$src))), (nxv2f64 ZPR:$src)>; - def : Pat<(nxv2f64 (bitconvert (nxv8i16 ZPR:$src))), (nxv2f64 ZPR:$src)>; - def : Pat<(nxv2f64 (bitconvert (nxv4i32 ZPR:$src))), (nxv2f64 ZPR:$src)>; - def : Pat<(nxv2f64 (bitconvert (nxv2i64 ZPR:$src))), (nxv2f64 ZPR:$src)>; - def : Pat<(nxv2f64 (bitconvert (nxv8f16 ZPR:$src))), (nxv2f64 ZPR:$src)>; - def : Pat<(nxv2f64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2f64 ZPR:$src)>; - - def : Pat<(nxv8bf16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - def : Pat<(nxv8bf16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - def : Pat<(nxv8bf16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - def : Pat<(nxv8bf16 (bitconvert (nxv8f16 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - def : Pat<(nxv8bf16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - def : Pat<(nxv8bf16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - - def : Pat<(nxv16i8 (bitconvert (nxv8bf16 ZPR:$src))), (nxv16i8 ZPR:$src)>; - def : Pat<(nxv8i16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8i16 ZPR:$src)>; - def : Pat<(nxv4i32 (bitconvert (nxv8bf16 ZPR:$src))), (nxv4i32 ZPR:$src)>; - def : Pat<(nxv2i64 (bitconvert (nxv8bf16 ZPR:$src))), (nxv2i64 ZPR:$src)>; - def : Pat<(nxv8f16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8f16 ZPR:$src)>; - def : Pat<(nxv4f32 (bitconvert (nxv8bf16 ZPR:$src))), (nxv4f32 ZPR:$src)>; - def : Pat<(nxv2f64 (bitconvert (nxv8bf16 ZPR:$src))), (nxv2f64 ZPR:$src)>; - - def : Pat<(nxv16i1 (bitconvert (aarch64svcount PNR:$src))), (nxv16i1 PPR:$src)>; - def : Pat<(aarch64svcount (bitconvert (nxv16i1 PPR:$src))), (aarch64svcount PNR:$src)>; + def : Pat<(nxv16i8 (bitconvert nxv8i16:$src)), (nxv16i8 ZPR:$src)>; + def : Pat<(nxv16i8 (bitconvert nxv4i32:$src)), (nxv16i8 ZPR:$src)>; + def : Pat<(nxv16i8 (bitconvert nxv2i64:$src)), (nxv16i8 ZPR:$src)>; + def : Pat<(nxv16i8 (bitconvert nxv8f16:$src)), (nxv16i8 ZPR:$src)>; + def : Pat<(nxv16i8 (bitconvert nxv4f32:$src)), (nxv16i8 ZPR:$src)>; + def : Pat<(nxv16i8 (bitconvert nxv2f64:$src)), (nxv16i8 ZPR:$src)>; + + def : Pat<(nxv8i16 (bitconvert nxv16i8:$src)), (nxv8i16 ZPR:$src)>; + def : Pat<(nxv8i16 (bitconvert nxv4i32:$src)), (nxv8i16 ZPR:$src)>; + def : Pat<(nxv8i16 (bitconvert nxv2i64:$src)), (nxv8i16 ZPR:$src)>; + def : Pat<(nxv8i16 (bitconvert nxv8f16:$src)), (nxv8i16 ZPR:$src)>; + def : Pat<(nxv8i16 (bitconvert nxv4f32:$src)), (nxv8i16 ZPR:$src)>; + def : Pat<(nxv8i16 (bitconvert nxv2f64:$src)), (nxv8i16 ZPR:$src)>; + + def : Pat<(nxv4i32 (bitconvert nxv16i8:$src)), (nxv4i32 ZPR:$src)>; + def : Pat<(nxv4i32 (bitconvert nxv8i16:$src)), (nxv4i32 ZPR:$src)>; + def : Pat<(nxv4i32 (bitconvert nxv2i64:$src)), (nxv4i32 ZPR:$src)>; + def : Pat<(nxv4i32 (bitconvert nxv8f16:$src)), (nxv4i32 ZPR:$src)>; + def : Pat<(nxv4i32 (bitconvert nxv4f32:$src)), (nxv4i32 ZPR:$src)>; + def : Pat<(nxv4i32 (bitconvert nxv2f64:$src)), (nxv4i32 ZPR:$src)>; + + def : Pat<(nxv2i64 (bitconvert nxv16i8:$src)), (nxv2i64 ZPR:$src)>; + def : Pat<(nxv2i64 (bitconvert nxv8i16:$src)), (nxv2i64 ZPR:$src)>; + def : Pat<(nxv2i64 (bitconvert nxv4i32:$src)), (nxv2i64 ZPR:$src)>; + def : Pat<(nxv2i64 (bitconvert nxv8f16:$src)), (nxv2i64 ZPR:$src)>; + def : Pat<(nxv2i64 (bitconvert nxv4f32:$src)), (nxv2i64 ZPR:$src)>; + def : Pat<(nxv2i64 (bitconvert nxv2f64:$src)), (nxv2i64 ZPR:$src)>; + + def : Pat<(nxv8f16 (bitconvert nxv16i8:$src)), (nxv8f16 ZPR:$src)>; + def : Pat<(nxv8f16 (bitconvert nxv8i16:$src)), (nxv8f16 ZPR:$src)>; + def : Pat<(nxv8f16 (bitconvert nxv4i32:$src)), (nxv8f16 ZPR:$src)>; + def : Pat<(nxv8f16 (bitconvert nxv2i64:$src)), (nxv8f16 ZPR:$src)>; + def : Pat<(nxv8f16 (bitconvert nxv4f32:$src)), (nxv8f16 ZPR:$src)>; + def : Pat<(nxv8f16 (bitconvert nxv2f64:$src)), (nxv8f16 ZPR:$src)>; + + def : Pat<(nxv4f32 (bitconvert nxv16i8:$src)), (nxv4f32 ZPR:$src)>; + def : Pat<(nxv4f32 (bitconvert nxv8i16:$src)), (nxv4f32 ZPR:$src)>; + def : Pat<(nxv4f32 (bitconvert nxv4i32:$src)), (nxv4f32 ZPR:$src)>; + def : Pat<(nxv4f32 (bitconvert nxv2i64:$src)), (nxv4f32 ZPR:$src)>; + def : Pat<(nxv4f32 (bitconvert nxv8f16:$src)), (nxv4f32 ZPR:$src)>; + def : Pat<(nxv4f32 (bitconvert nxv2f64:$src)), (nxv4f32 ZPR:$src)>; + + def : Pat<(nxv2f64 (bitconvert nxv16i8:$src)), (nxv2f64 ZPR:$src)>; + def : Pat<(nxv2f64 (bitconvert nxv8i16:$src)), (nxv2f64 ZPR:$src)>; + def : Pat<(nxv2f64 (bitconvert nxv4i32:$src)), (nxv2f64 ZPR:$src)>; + def : Pat<(nxv2f64 (bitconvert nxv2i64:$src)), (nxv2f64 ZPR:$src)>; + def : Pat<(nxv2f64 (bitconvert nxv8f16:$src)), (nxv2f64 ZPR:$src)>; + def : Pat<(nxv2f64 (bitconvert nxv4f32:$src)), (nxv2f64 ZPR:$src)>; + + def : Pat<(nxv8bf16 (bitconvert nxv16i8:$src)), (nxv8bf16 ZPR:$src)>; + def : Pat<(nxv8bf16 (bitconvert nxv8i16:$src)), (nxv8bf16 ZPR:$src)>; + def : Pat<(nxv8bf16 (bitconvert nxv4i32:$src)), (nxv8bf16 ZPR:$src)>; + def : Pat<(nxv8bf16 (bitconvert nxv2i64:$src)), (nxv8bf16 ZPR:$src)>; + def : Pat<(nxv8bf16 (bitconvert nxv8f16:$src)), (nxv8bf16 ZPR:$src)>; + def : Pat<(nxv8bf16 (bitconvert nxv4f32:$src)), (nxv8bf16 ZPR:$src)>; + def : Pat<(nxv8bf16 (bitconvert nxv2f64:$src)), (nxv8bf16 ZPR:$src)>; + + def : Pat<(nxv16i8 (bitconvert nxv8bf16:$src)), (nxv16i8 ZPR:$src)>; + def : Pat<(nxv8i16 (bitconvert nxv8bf16:$src)), (nxv8i16 ZPR:$src)>; + def : Pat<(nxv4i32 (bitconvert nxv8bf16:$src)), (nxv4i32 ZPR:$src)>; + def : Pat<(nxv2i64 (bitconvert nxv8bf16:$src)), (nxv2i64 ZPR:$src)>; + def : Pat<(nxv8f16 (bitconvert nxv8bf16:$src)), (nxv8f16 ZPR:$src)>; + def : Pat<(nxv4f32 (bitconvert nxv8bf16:$src)), (nxv4f32 ZPR:$src)>; + def : Pat<(nxv2f64 (bitconvert nxv8bf16:$src)), (nxv2f64 ZPR:$src)>; + + def : Pat<(nxv16i1 (bitconvert aarch64svcount:$src)), (nxv16i1 PPR:$src)>; + def : Pat<(aarch64svcount (bitconvert nxv16i1:$src)), (aarch64svcount PNR:$src)>; } // These allow casting from/to unpacked predicate types. - def : Pat<(nxv16i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv16i1 (reinterpret_cast (nxv8i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv16i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv16i1 (reinterpret_cast (nxv2i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv16i1 (reinterpret_cast (nxv1i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv8i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv8i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv8i1 (reinterpret_cast (nxv2i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv8i1 (reinterpret_cast (nxv1i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv4i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv4i1 (reinterpret_cast (nxv8i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv4i1 (reinterpret_cast (nxv2i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv4i1 (reinterpret_cast (nxv1i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv2i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv2i1 (reinterpret_cast (nxv8i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv2i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv2i1 (reinterpret_cast (nxv1i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv1i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv1i1 (reinterpret_cast (nxv8i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv1i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv1i1 (reinterpret_cast (nxv2i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv16i1 (reinterpret_cast nxv16i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv16i1 (reinterpret_cast nxv8i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv16i1 (reinterpret_cast nxv4i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv16i1 (reinterpret_cast nxv2i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv16i1 (reinterpret_cast nxv1i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv8i1 (reinterpret_cast nxv16i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv8i1 (reinterpret_cast nxv4i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv8i1 (reinterpret_cast nxv2i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv8i1 (reinterpret_cast nxv1i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv4i1 (reinterpret_cast nxv16i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv4i1 (reinterpret_cast nxv8i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv4i1 (reinterpret_cast nxv2i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv4i1 (reinterpret_cast nxv1i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv2i1 (reinterpret_cast nxv16i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv2i1 (reinterpret_cast nxv8i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv2i1 (reinterpret_cast nxv4i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv2i1 (reinterpret_cast nxv1i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv1i1 (reinterpret_cast nxv16i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv1i1 (reinterpret_cast nxv8i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv1i1 (reinterpret_cast nxv4i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv1i1 (reinterpret_cast nxv2i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; // These allow casting from/to unpacked floating-point types. - def : Pat<(nxv2f16 (reinterpret_cast (nxv8f16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv8f16 (reinterpret_cast (nxv2f16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv4f16 (reinterpret_cast (nxv8f16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv8f16 (reinterpret_cast (nxv4f16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv2f32 (reinterpret_cast (nxv4f32 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv4f32 (reinterpret_cast (nxv2f32 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv2bf16 (reinterpret_cast (nxv8bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv8bf16 (reinterpret_cast (nxv2bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv4bf16 (reinterpret_cast (nxv8bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv8bf16 (reinterpret_cast (nxv4bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv2f16 (reinterpret_cast nxv8f16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv8f16 (reinterpret_cast nxv2f16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv4f16 (reinterpret_cast nxv8f16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv8f16 (reinterpret_cast nxv4f16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv2f32 (reinterpret_cast nxv4f32:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv4f32 (reinterpret_cast nxv2f32:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv2bf16 (reinterpret_cast nxv8bf16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv8bf16 (reinterpret_cast nxv2bf16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv4bf16 (reinterpret_cast nxv8bf16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv8bf16 (reinterpret_cast nxv4bf16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; def : Pat<(nxv16i1 (and PPR:$Ps1, PPR:$Ps2)), (AND_PPzPP (PTRUE_B 31), PPR:$Ps1, PPR:$Ps2)>; @@ -2788,14 +2788,14 @@ let Predicates = [HasSVEorSME] in { multiclass pred_store { let AddedComplexity = 1 in { - def _reg_reg : Pat<(Store (Ty ZPR:$vec), (AddrCP GPR64:$base, GPR64:$offset), (PredTy PPR:$gp)), + def _reg_reg : Pat<(Store Ty:$vec, (AddrCP GPR64:$base, GPR64:$offset), PredTy:$gp), (RegRegInst ZPR:$vec, PPR:$gp, GPR64:$base, GPR64:$offset)>; } let AddedComplexity = 2 in { - def _reg_imm : Pat<(Store (Ty ZPR:$vec), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), (PredTy PPR:$gp)), + def _reg_imm : Pat<(Store Ty:$vec, (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), PredTy:$gp), (RegImmInst ZPR:$vec, PPR:$gp, GPR64:$base, simm4s1:$offset)>; } - def _default : Pat<(Store (Ty ZPR:$vec), GPR64:$base, (PredTy PPR:$gp)), + def _default : Pat<(Store Ty:$vec, GPR64:$base, PredTy:$gp), (RegImmInst ZPR:$vec, PPR:$gp, GPR64:$base, (i64 0))>; } @@ -2840,15 +2840,15 @@ let Predicates = [HasSVEorSME] in { Instruction RegImmInst, Instruction PTrue, ComplexPattern AddrCP> { let AddedComplexity = 1 in { - def _reg : Pat<(Store (Ty ZPR:$val), (AddrCP GPR64sp:$base, GPR64:$offset)), + def _reg : Pat<(Store Ty:$val, (AddrCP GPR64sp:$base, GPR64:$offset)), (RegRegInst ZPR:$val, (PTrue 31), GPR64sp:$base, GPR64:$offset)>; } let AddedComplexity = 2 in { - def _imm : Pat<(Store (Ty ZPR:$val), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset)), + def _imm : Pat<(Store Ty:$val, (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset)), (RegImmInst ZPR:$val, (PTrue 31), GPR64sp:$base, simm4s1:$offset)>; } - def : Pat<(Store (Ty ZPR:$val), GPR64:$base), + def : Pat<(Store Ty:$val, GPR64:$base), (RegImmInst ZPR:$val, (PTrue 31), GPR64:$base, (i64 0))>; } @@ -2927,7 +2927,7 @@ let Predicates = [HasSVEorSME] in { let Predicates = [IsLE] in { def : Pat<(Ty (load (am_sve_regreg_lsl0 GPR64sp:$base, GPR64:$offset))), (LD1B (PTRUE_B 31), GPR64sp:$base, GPR64:$offset)>; - def : Pat<(store (Ty ZPR:$val), (am_sve_regreg_lsl0 GPR64sp:$base, GPR64:$offset)), + def : Pat<(store Ty:$val, (am_sve_regreg_lsl0 GPR64sp:$base, GPR64:$offset)), (ST1B ZPR:$val, (PTRUE_B 31), GPR64sp:$base, GPR64:$offset)>; } } @@ -3095,18 +3095,18 @@ let Predicates = [HasSVEorSME] in { SDPatternOperator Store, ValueType PredTy, ValueType MemVT, ComplexPattern AddrCP> { // reg + reg let AddedComplexity = 1 in { - def : Pat<(Store (Ty ZPR:$vec), (AddrCP GPR64:$base, GPR64:$offset), (PredTy PPR:$gp), MemVT), + def : Pat<(Store Ty:$vec, (AddrCP GPR64:$base, GPR64:$offset), PredTy:$gp, MemVT), (RegRegInst ZPR:$vec, PPR:$gp, GPR64sp:$base, GPR64:$offset)>; } // scalar + immediate (mul vl) let AddedComplexity = 2 in { - def : Pat<(Store (Ty ZPR:$vec), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), (PredTy PPR:$gp), MemVT), + def : Pat<(Store Ty:$vec, (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), PredTy:$gp, MemVT), (RegImmInst ZPR:$vec, PPR:$gp, GPR64sp:$base, simm4s1:$offset)>; } // base - def : Pat<(Store (Ty ZPR:$vec), GPR64:$base, (PredTy PPR:$gp), MemVT), + def : Pat<(Store Ty:$vec, GPR64:$base, (PredTy PPR:$gp), MemVT), (RegImmInst ZPR:$vec, PPR:$gp, GPR64:$base, (i64 0))>; } @@ -3158,44 +3158,44 @@ let Predicates = [HasSVEorSME] in { (INSERT_SUBREG (nxv2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>; // Insert scalar into vector[0] - def : Pat<(nxv16i8 (vector_insert (nxv16i8 ZPR:$vec), (i32 GPR32:$src), 0)), + def : Pat<(nxv16i8 (vector_insert nxv16i8:$vec, (i32 GPR32:$src), 0)), (CPY_ZPmR_B ZPR:$vec, (PTRUE_B 1), GPR32:$src)>; - def : Pat<(nxv8i16 (vector_insert (nxv8i16 ZPR:$vec), (i32 GPR32:$src), 0)), + def : Pat<(nxv8i16 (vector_insert nxv8i16:$vec, (i32 GPR32:$src), 0)), (CPY_ZPmR_H ZPR:$vec, (PTRUE_H 1), GPR32:$src)>; - def : Pat<(nxv4i32 (vector_insert (nxv4i32 ZPR:$vec), (i32 GPR32:$src), 0)), + def : Pat<(nxv4i32 (vector_insert nxv4i32:$vec, (i32 GPR32:$src), 0)), (CPY_ZPmR_S ZPR:$vec, (PTRUE_S 1), GPR32:$src)>; - def : Pat<(nxv2i64 (vector_insert (nxv2i64 ZPR:$vec), (i64 GPR64:$src), 0)), + def : Pat<(nxv2i64 (vector_insert nxv2i64:$vec, (i64 GPR64:$src), 0)), (CPY_ZPmR_D ZPR:$vec, (PTRUE_D 1), GPR64:$src)>; - def : Pat<(nxv8f16 (vector_insert (nxv8f16 ZPR:$vec), (f16 FPR16:$src), 0)), + def : Pat<(nxv8f16 (vector_insert nxv8f16:$vec, (f16 FPR16:$src), 0)), (SEL_ZPZZ_H (PTRUE_H 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), ZPR:$vec)>; - def : Pat<(nxv8bf16 (vector_insert (nxv8bf16 ZPR:$vec), (bf16 FPR16:$src), 0)), + def : Pat<(nxv8bf16 (vector_insert nxv8bf16:$vec, (bf16 FPR16:$src), 0)), (SEL_ZPZZ_H (PTRUE_H 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), ZPR:$vec)>; - def : Pat<(nxv4f32 (vector_insert (nxv4f32 ZPR:$vec), (f32 FPR32:$src), 0)), + def : Pat<(nxv4f32 (vector_insert nxv4f32:$vec, (f32 FPR32:$src), 0)), (SEL_ZPZZ_S (PTRUE_S 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$src, ssub), ZPR:$vec)>; - def : Pat<(nxv2f64 (vector_insert (nxv2f64 ZPR:$vec), (f64 FPR64:$src), 0)), + def : Pat<(nxv2f64 (vector_insert nxv2f64:$vec, (f64 FPR64:$src), 0)), (SEL_ZPZZ_D (PTRUE_D 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$src, dsub), ZPR:$vec)>; // Insert scalar into vector with scalar index - def : Pat<(nxv16i8 (vector_insert (nxv16i8 ZPR:$vec), GPR32:$src, GPR64:$index)), + def : Pat<(nxv16i8 (vector_insert nxv16i8:$vec, GPR32:$src, GPR64:$index)), (CPY_ZPmR_B ZPR:$vec, (CMPEQ_PPzZZ_B (PTRUE_B 31), (INDEX_II_B 0, 1), (DUP_ZR_B (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), GPR32:$src)>; - def : Pat<(nxv8i16 (vector_insert (nxv8i16 ZPR:$vec), GPR32:$src, GPR64:$index)), + def : Pat<(nxv8i16 (vector_insert nxv8i16:$vec, GPR32:$src, GPR64:$index)), (CPY_ZPmR_H ZPR:$vec, (CMPEQ_PPzZZ_H (PTRUE_H 31), (INDEX_II_H 0, 1), (DUP_ZR_H (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), GPR32:$src)>; - def : Pat<(nxv4i32 (vector_insert (nxv4i32 ZPR:$vec), GPR32:$src, GPR64:$index)), + def : Pat<(nxv4i32 (vector_insert nxv4i32:$vec, GPR32:$src, GPR64:$index)), (CPY_ZPmR_S ZPR:$vec, (CMPEQ_PPzZZ_S (PTRUE_S 31), (INDEX_II_S 0, 1), (DUP_ZR_S (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), GPR32:$src)>; - def : Pat<(nxv2i64 (vector_insert (nxv2i64 ZPR:$vec), GPR64:$src, GPR64:$index)), + def : Pat<(nxv2i64 (vector_insert nxv2i64:$vec, GPR64:$src, GPR64:$index)), (CPY_ZPmR_D ZPR:$vec, (CMPEQ_PPzZZ_D (PTRUE_D 31), (INDEX_II_D 0, 1), @@ -3203,55 +3203,55 @@ let Predicates = [HasSVEorSME] in { GPR64:$src)>; // Insert FP scalar into vector with scalar index - def : Pat<(nxv2f16 (vector_insert (nxv2f16 ZPR:$vec), (f16 FPR16:$src), GPR64:$index)), + def : Pat<(nxv2f16 (vector_insert nxv2f16:$vec, (f16 FPR16:$src), GPR64:$index)), (CPY_ZPmV_H ZPR:$vec, (CMPEQ_PPzZZ_D (PTRUE_D 31), (INDEX_II_D 0, 1), (DUP_ZR_D GPR64:$index)), $src)>; - def : Pat<(nxv4f16 (vector_insert (nxv4f16 ZPR:$vec), (f16 FPR16:$src), GPR64:$index)), + def : Pat<(nxv4f16 (vector_insert nxv4f16:$vec, (f16 FPR16:$src), GPR64:$index)), (CPY_ZPmV_H ZPR:$vec, (CMPEQ_PPzZZ_S (PTRUE_S 31), (INDEX_II_S 0, 1), (DUP_ZR_S (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), $src)>; - def : Pat<(nxv8f16 (vector_insert (nxv8f16 ZPR:$vec), (f16 FPR16:$src), GPR64:$index)), + def : Pat<(nxv8f16 (vector_insert nxv8f16:$vec, (f16 FPR16:$src), GPR64:$index)), (CPY_ZPmV_H ZPR:$vec, (CMPEQ_PPzZZ_H (PTRUE_H 31), (INDEX_II_H 0, 1), (DUP_ZR_H (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), $src)>; - def : Pat<(nxv2bf16 (vector_insert (nxv2bf16 ZPR:$vec), (bf16 FPR16:$src), GPR64:$index)), + def : Pat<(nxv2bf16 (vector_insert nxv2bf16:$vec, (bf16 FPR16:$src), GPR64:$index)), (CPY_ZPmV_H ZPR:$vec, (CMPEQ_PPzZZ_D (PTRUE_D 31), (INDEX_II_D 0, 1), (DUP_ZR_D GPR64:$index)), $src)>; - def : Pat<(nxv4bf16 (vector_insert (nxv4bf16 ZPR:$vec), (bf16 FPR16:$src), GPR64:$index)), + def : Pat<(nxv4bf16 (vector_insert nxv4bf16:$vec, (bf16 FPR16:$src), GPR64:$index)), (CPY_ZPmV_H ZPR:$vec, (CMPEQ_PPzZZ_S (PTRUE_S 31), (INDEX_II_S 0, 1), (DUP_ZR_S (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), $src)>; - def : Pat<(nxv8bf16 (vector_insert (nxv8bf16 ZPR:$vec), (bf16 FPR16:$src), GPR64:$index)), + def : Pat<(nxv8bf16 (vector_insert nxv8bf16:$vec, (bf16 FPR16:$src), GPR64:$index)), (CPY_ZPmV_H ZPR:$vec, (CMPEQ_PPzZZ_H (PTRUE_H 31), (INDEX_II_H 0, 1), (DUP_ZR_H (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), $src)>; - def : Pat<(nxv2f32 (vector_insert (nxv2f32 ZPR:$vec), (f32 FPR32:$src), GPR64:$index)), + def : Pat<(nxv2f32 (vector_insert nxv2f32:$vec, (f32 FPR32:$src), GPR64:$index)), (CPY_ZPmV_S ZPR:$vec, (CMPEQ_PPzZZ_D (PTRUE_D 31), (INDEX_II_D 0, 1), (DUP_ZR_D GPR64:$index)), $src) >; - def : Pat<(nxv4f32 (vector_insert (nxv4f32 ZPR:$vec), (f32 FPR32:$src), GPR64:$index)), + def : Pat<(nxv4f32 (vector_insert nxv4f32:$vec, (f32 FPR32:$src), GPR64:$index)), (CPY_ZPmV_S ZPR:$vec, (CMPEQ_PPzZZ_S (PTRUE_S 31), (INDEX_II_S 0, 1), (DUP_ZR_S (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), $src)>; - def : Pat<(nxv2f64 (vector_insert (nxv2f64 ZPR:$vec), (f64 FPR64:$src), GPR64:$index)), + def : Pat<(nxv2f64 (vector_insert nxv2f64:$vec, (f64 FPR64:$src), GPR64:$index)), (CPY_ZPmV_D ZPR:$vec, (CMPEQ_PPzZZ_D (PTRUE_D 31), (INDEX_II_D 0, 1), @@ -3259,139 +3259,139 @@ let Predicates = [HasSVEorSME] in { $src)>; // Extract element from vector with scalar index - def : Pat<(i32 (vector_extract (nxv16i8 ZPR:$vec), GPR64:$index)), + def : Pat<(i32 (vector_extract nxv16i8:$vec, GPR64:$index)), (LASTB_RPZ_B (WHILELS_PXX_B XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(i32 (vector_extract (nxv8i16 ZPR:$vec), GPR64:$index)), + def : Pat<(i32 (vector_extract nxv8i16:$vec, GPR64:$index)), (LASTB_RPZ_H (WHILELS_PXX_H XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(i32 (vector_extract (nxv4i32 ZPR:$vec), GPR64:$index)), + def : Pat<(i32 (vector_extract nxv4i32:$vec, GPR64:$index)), (LASTB_RPZ_S (WHILELS_PXX_S XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(i64 (vector_extract (nxv2i64 ZPR:$vec), GPR64:$index)), + def : Pat<(i64 (vector_extract nxv2i64:$vec, GPR64:$index)), (LASTB_RPZ_D (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(f16 (vector_extract (nxv8f16 ZPR:$vec), GPR64:$index)), + def : Pat<(f16 (vector_extract nxv8f16:$vec, GPR64:$index)), (LASTB_VPZ_H (WHILELS_PXX_H XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(f16 (vector_extract (nxv4f16 ZPR:$vec), GPR64:$index)), + def : Pat<(f16 (vector_extract nxv4f16:$vec, GPR64:$index)), (LASTB_VPZ_H (WHILELS_PXX_S XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(f16 (vector_extract (nxv2f16 ZPR:$vec), GPR64:$index)), + def : Pat<(f16 (vector_extract nxv2f16:$vec, GPR64:$index)), (LASTB_VPZ_H (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(bf16 (vector_extract (nxv8bf16 ZPR:$vec), GPR64:$index)), + def : Pat<(bf16 (vector_extract nxv8bf16:$vec, GPR64:$index)), (LASTB_VPZ_H (WHILELS_PXX_H XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(bf16 (vector_extract (nxv4bf16 ZPR:$vec), GPR64:$index)), + def : Pat<(bf16 (vector_extract nxv4bf16:$vec, GPR64:$index)), (LASTB_VPZ_H (WHILELS_PXX_S XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(bf16 (vector_extract (nxv2bf16 ZPR:$vec), GPR64:$index)), + def : Pat<(bf16 (vector_extract nxv2bf16:$vec, GPR64:$index)), (LASTB_VPZ_H (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(f32 (vector_extract (nxv4f32 ZPR:$vec), GPR64:$index)), + def : Pat<(f32 (vector_extract nxv4f32:$vec, GPR64:$index)), (LASTB_VPZ_S (WHILELS_PXX_S XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(f32 (vector_extract (nxv2f32 ZPR:$vec), GPR64:$index)), + def : Pat<(f32 (vector_extract nxv2f32:$vec, GPR64:$index)), (LASTB_VPZ_S (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(f64 (vector_extract (nxv2f64 ZPR:$vec), GPR64:$index)), + def : Pat<(f64 (vector_extract nxv2f64:$vec, GPR64:$index)), (LASTB_VPZ_D (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>; // Extract element from vector with immediate index - def : Pat<(i32 (vector_extract (nxv16i8 ZPR:$vec), sve_elm_idx_extdup_b:$index)), + def : Pat<(i32 (vector_extract nxv16i8:$vec, sve_elm_idx_extdup_b:$index)), (EXTRACT_SUBREG (DUP_ZZI_B ZPR:$vec, sve_elm_idx_extdup_b:$index), ssub)>; - def : Pat<(i32 (vector_extract (nxv8i16 ZPR:$vec), sve_elm_idx_extdup_h:$index)), + def : Pat<(i32 (vector_extract nxv8i16:$vec, sve_elm_idx_extdup_h:$index)), (EXTRACT_SUBREG (DUP_ZZI_H ZPR:$vec, sve_elm_idx_extdup_h:$index), ssub)>; - def : Pat<(i32 (vector_extract (nxv4i32 ZPR:$vec), sve_elm_idx_extdup_s:$index)), + def : Pat<(i32 (vector_extract nxv4i32:$vec, sve_elm_idx_extdup_s:$index)), (EXTRACT_SUBREG (DUP_ZZI_S ZPR:$vec, sve_elm_idx_extdup_s:$index), ssub)>; - def : Pat<(i64 (vector_extract (nxv2i64 ZPR:$vec), sve_elm_idx_extdup_d:$index)), + def : Pat<(i64 (vector_extract nxv2i64:$vec, sve_elm_idx_extdup_d:$index)), (EXTRACT_SUBREG (DUP_ZZI_D ZPR:$vec, sve_elm_idx_extdup_d:$index), dsub)>; - def : Pat<(f16 (vector_extract (nxv8f16 ZPR:$vec), sve_elm_idx_extdup_h:$index)), + def : Pat<(f16 (vector_extract nxv8f16:$vec, sve_elm_idx_extdup_h:$index)), (EXTRACT_SUBREG (DUP_ZZI_H ZPR:$vec, sve_elm_idx_extdup_h:$index), hsub)>; - def : Pat<(f16 (vector_extract (nxv4f16 ZPR:$vec), sve_elm_idx_extdup_s:$index)), + def : Pat<(f16 (vector_extract nxv4f16:$vec, sve_elm_idx_extdup_s:$index)), (EXTRACT_SUBREG (DUP_ZZI_S ZPR:$vec, sve_elm_idx_extdup_s:$index), hsub)>; - def : Pat<(f16 (vector_extract (nxv2f16 ZPR:$vec), sve_elm_idx_extdup_d:$index)), + def : Pat<(f16 (vector_extract nxv2f16:$vec, sve_elm_idx_extdup_d:$index)), (EXTRACT_SUBREG (DUP_ZZI_D ZPR:$vec, sve_elm_idx_extdup_d:$index), hsub)>; - def : Pat<(bf16 (vector_extract (nxv8bf16 ZPR:$vec), sve_elm_idx_extdup_h:$index)), + def : Pat<(bf16 (vector_extract nxv8bf16:$vec, sve_elm_idx_extdup_h:$index)), (EXTRACT_SUBREG (DUP_ZZI_H ZPR:$vec, sve_elm_idx_extdup_h:$index), hsub)>; - def : Pat<(bf16 (vector_extract (nxv4bf16 ZPR:$vec), sve_elm_idx_extdup_s:$index)), + def : Pat<(bf16 (vector_extract nxv4bf16:$vec, sve_elm_idx_extdup_s:$index)), (EXTRACT_SUBREG (DUP_ZZI_S ZPR:$vec, sve_elm_idx_extdup_s:$index), hsub)>; - def : Pat<(bf16 (vector_extract (nxv2bf16 ZPR:$vec), sve_elm_idx_extdup_d:$index)), + def : Pat<(bf16 (vector_extract nxv2bf16:$vec, sve_elm_idx_extdup_d:$index)), (EXTRACT_SUBREG (DUP_ZZI_D ZPR:$vec, sve_elm_idx_extdup_d:$index), hsub)>; - def : Pat<(f32 (vector_extract (nxv4f32 ZPR:$vec), sve_elm_idx_extdup_s:$index)), + def : Pat<(f32 (vector_extract nxv4f32:$vec, sve_elm_idx_extdup_s:$index)), (EXTRACT_SUBREG (DUP_ZZI_S ZPR:$vec, sve_elm_idx_extdup_s:$index), ssub)>; - def : Pat<(f32 (vector_extract (nxv2f32 ZPR:$vec), sve_elm_idx_extdup_d:$index)), + def : Pat<(f32 (vector_extract nxv2f32:$vec, sve_elm_idx_extdup_d:$index)), (EXTRACT_SUBREG (DUP_ZZI_D ZPR:$vec, sve_elm_idx_extdup_d:$index), ssub)>; - def : Pat<(f64 (vector_extract (nxv2f64 ZPR:$vec), sve_elm_idx_extdup_d:$index)), + def : Pat<(f64 (vector_extract nxv2f64:$vec, sve_elm_idx_extdup_d:$index)), (EXTRACT_SUBREG (DUP_ZZI_D ZPR:$vec, sve_elm_idx_extdup_d:$index), dsub)>; // Extract element from vector with immediate index that's within the bottom 128-bits. let Predicates = [IsNeonAvailable], AddedComplexity = 1 in { - def : Pat<(i32 (vector_extract (nxv16i8 ZPR:$vec), VectorIndexB:$index)), + def : Pat<(i32 (vector_extract nxv16i8:$vec, VectorIndexB:$index)), (UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>; - def : Pat<(i32 (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index)), + def : Pat<(i32 (vector_extract nxv8i16:$vec, VectorIndexH:$index)), (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>; - def : Pat<(i32 (vector_extract (nxv4i32 ZPR:$vec), VectorIndexS:$index)), + def : Pat<(i32 (vector_extract nxv4i32:$vec, VectorIndexS:$index)), (UMOVvi32 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>; - def : Pat<(i64 (vector_extract (nxv2i64 ZPR:$vec), VectorIndexD:$index)), + def : Pat<(i64 (vector_extract nxv2i64:$vec, VectorIndexD:$index)), (UMOVvi64 (v2i64 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexD:$index)>; } // End IsNeonAvailable let Predicates = [IsNeonAvailable] in { - def : Pat<(sext_inreg (vector_extract (nxv16i8 ZPR:$vec), VectorIndexB:$index), i8), + def : Pat<(sext_inreg (vector_extract nxv16i8:$vec, VectorIndexB:$index), i8), (SMOVvi8to32 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>; - def : Pat<(sext_inreg (anyext (i32 (vector_extract (nxv16i8 ZPR:$vec), VectorIndexB:$index))), i8), + def : Pat<(sext_inreg (anyext (i32 (vector_extract nxv16i8:$vec, VectorIndexB:$index))), i8), (SMOVvi8to64 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>; - def : Pat<(sext_inreg (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index), i16), + def : Pat<(sext_inreg (vector_extract nxv8i16:$vec, VectorIndexH:$index), i16), (SMOVvi16to32 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>; - def : Pat<(sext_inreg (anyext (i32 (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index))), i16), + def : Pat<(sext_inreg (anyext (i32 (vector_extract nxv8i16:$vec, VectorIndexH:$index))), i16), (SMOVvi16to64 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>; - def : Pat<(sext (i32 (vector_extract (nxv4i32 ZPR:$vec), VectorIndexS:$index))), + def : Pat<(sext (i32 (vector_extract nxv4i32:$vec, VectorIndexS:$index))), (SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>; } // End IsNeonAvailable // Extract first element from vector. let AddedComplexity = 2 in { - def : Pat<(i32 (vector_extract (nxv16i8 ZPR:$Zs), (i64 0))), + def : Pat<(i32 (vector_extract nxv16i8:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, ssub)>; - def : Pat<(i32 (vector_extract (nxv8i16 ZPR:$Zs), (i64 0))), + def : Pat<(i32 (vector_extract nxv8i16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, ssub)>; - def : Pat<(i32 (vector_extract (nxv4i32 ZPR:$Zs), (i64 0))), + def : Pat<(i32 (vector_extract nxv4i32:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, ssub)>; - def : Pat<(i64 (vector_extract (nxv2i64 ZPR:$Zs), (i64 0))), + def : Pat<(i64 (vector_extract nxv2i64:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, dsub)>; - def : Pat<(f16 (vector_extract (nxv8f16 ZPR:$Zs), (i64 0))), + def : Pat<(f16 (vector_extract nxv8f16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, hsub)>; - def : Pat<(f16 (vector_extract (nxv4f16 ZPR:$Zs), (i64 0))), + def : Pat<(f16 (vector_extract nxv4f16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, hsub)>; - def : Pat<(f16 (vector_extract (nxv2f16 ZPR:$Zs), (i64 0))), + def : Pat<(f16 (vector_extract nxv2f16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, hsub)>; - def : Pat<(bf16 (vector_extract (nxv8bf16 ZPR:$Zs), (i64 0))), + def : Pat<(bf16 (vector_extract nxv8bf16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, hsub)>; - def : Pat<(bf16 (vector_extract (nxv4bf16 ZPR:$Zs), (i64 0))), + def : Pat<(bf16 (vector_extract nxv4bf16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, hsub)>; - def : Pat<(bf16 (vector_extract (nxv2bf16 ZPR:$Zs), (i64 0))), + def : Pat<(bf16 (vector_extract nxv2bf16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, hsub)>; - def : Pat<(f32 (vector_extract (nxv4f32 ZPR:$Zs), (i64 0))), + def : Pat<(f32 (vector_extract nxv4f32:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, ssub)>; - def : Pat<(f32 (vector_extract (nxv2f32 ZPR:$Zs), (i64 0))), + def : Pat<(f32 (vector_extract nxv2f32:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, ssub)>; - def : Pat<(f64 (vector_extract (nxv2f64 ZPR:$Zs), (i64 0))), + def : Pat<(f64 (vector_extract nxv2f64:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, dsub)>; } multiclass sve_predicated_add { - def : Pat<(nxv16i8 (add ZPR:$op, (extend (nxv16i1 PPR:$pred)))), + def : Pat<(nxv16i8 (add ZPR:$op, (extend nxv16i1:$pred))), (ADD_ZPmZ_B PPR:$pred, ZPR:$op, (DUP_ZI_B value, 0))>; - def : Pat<(nxv8i16 (add ZPR:$op, (extend (nxv8i1 PPR:$pred)))), + def : Pat<(nxv8i16 (add ZPR:$op, (extend nxv8i1:$pred))), (ADD_ZPmZ_H PPR:$pred, ZPR:$op, (DUP_ZI_H value, 0))>; - def : Pat<(nxv4i32 (add ZPR:$op, (extend (nxv4i1 PPR:$pred)))), + def : Pat<(nxv4i32 (add ZPR:$op, (extend nxv4i1:$pred))), (ADD_ZPmZ_S PPR:$pred, ZPR:$op, (DUP_ZI_S value, 0))>; - def : Pat<(nxv2i64 (add ZPR:$op, (extend (nxv2i1 PPR:$pred)))), + def : Pat<(nxv2i64 (add ZPR:$op, (extend nxv2i1:$pred))), (ADD_ZPmZ_D PPR:$pred, ZPR:$op, (DUP_ZI_D value, 0))>; } defm : sve_predicated_add; defm : sve_predicated_add; - def : Pat<(nxv16i8 (sub ZPR:$op, (sext (nxv16i1 PPR:$pred)))), + def : Pat<(nxv16i8 (sub ZPR:$op, (sext nxv16i1:$pred))), (SUB_ZPmZ_B PPR:$pred, ZPR:$op, (DUP_ZI_B 255, 0))>; - def : Pat<(nxv8i16 (sub ZPR:$op, (sext (nxv8i1 PPR:$pred)))), + def : Pat<(nxv8i16 (sub ZPR:$op, (sext nxv8i1:$pred))), (SUB_ZPmZ_H PPR:$pred, ZPR:$op, (DUP_ZI_H 255, 0))>; - def : Pat<(nxv4i32 (sub ZPR:$op, (sext (nxv4i1 PPR:$pred)))), + def : Pat<(nxv4i32 (sub ZPR:$op, (sext nxv4i1:$pred))), (SUB_ZPmZ_S PPR:$pred, ZPR:$op, (DUP_ZI_S 255, 0))>; - def : Pat<(nxv2i64 (sub ZPR:$op, (sext (nxv2i1 PPR:$pred)))), + def : Pat<(nxv2i64 (sub ZPR:$op, (sext nxv2i1:$pred))), (SUB_ZPmZ_D PPR:$pred, ZPR:$op, (DUP_ZI_D 255, 0))>; } // End HasSVEorSME @@ -3995,8 +3995,7 @@ defm STNT1D_4Z_IMM : sve2p1_mem_cst_si_4z<"stnt1d", 0b11, 0b1, ZZZZ_d_mul_r>; multiclass store_pn_x2 { - def : Pat<(Store (Ty ZPR:$vec0), (Ty ZPR:$vec1), - (aarch64svcount PNR:$PNg), GPR64:$base), + def : Pat<(Store Ty:$vec0, Ty:$vec1, aarch64svcount:$PNg, GPR64:$base), (RegImmInst (REG_SEQUENCE ZPR2Mul2, Ty:$vec0, zsub0, Ty:$vec1, zsub1), PNR:$PNg, GPR64:$base, (i64 0))>; } @@ -4021,8 +4020,7 @@ defm : store_pn_x2; multiclass store_pn_x4 { - def : Pat<(Store (Ty ZPR:$vec0), (Ty ZPR:$vec1), (Ty ZPR:$vec2), (Ty ZPR:$vec3), - (aarch64svcount PNR:$PNg), GPR64:$base), + def : Pat<(Store Ty:$vec0, Ty:$vec1, Ty:$vec2, Ty:$vec3, aarch64svcount:$PNg, GPR64:$base), (RegImmInst (REG_SEQUENCE ZPR4Mul4, Ty:$vec0, zsub0, Ty:$vec1, zsub1, Ty:$vec2, zsub2, Ty:$vec3, zsub3), PNR:$PNg, GPR64:$base, (i64 0))>; -- GitLab From 5ad7a210ff850eed1f255f81f0609efedabe3bb7 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 10 May 2024 12:14:11 +0100 Subject: [PATCH 253/328] [AArch64] wfxt must depend on itself (#90987) --- llvm/lib/Target/AArch64/AArch64Features.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 755a1bdc8e23..3425ac413302 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -597,7 +597,7 @@ def FeatureXS : SubtargetFeature<"xs", "HasXS", def FeatureWFxT : Extension<"wfxt", "WFxT", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)", [], - "FEAT_WFXT", "", 550>; + "FEAT_WFXT", "+wfxt", 550>; def FeatureHCX : SubtargetFeature< "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">; -- GitLab From f52ca632787a5d4227689726e14dae6749e1e650 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Fri, 10 May 2024 12:26:45 +0100 Subject: [PATCH 254/328] [LAA] Drop x86_64 target triple to fix test on builds with X86. Follow-up o fix test after 28767afd53353d9333b0adf6f0fafa1592092532. --- .../LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll b/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll index d96a6ea7c555..cb50b2c75ccb 100644 --- a/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll +++ b/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll @@ -23,14 +23,13 @@ ; CHECK: function 'Test': ; CHECK: .inner: -; CHECK-NEXT: Memory dependences are safe with a maximum safe vector width of 2048 bits with run-time checks +; CHECK-NEXT: Memory dependences are safe with run-time checks ; CHECK-NEXT: Dependences: ; CHECK-NEXT: Run-time memory checks: ; CHECK: Check 0: ; CHECK: Check 1: target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" -target triple = "x86_64-unknown-linux-gnu" %struct.s = type { [32 x i32], [32 x i32], [32 x [32 x i32]] } -- GitLab From 200f3bd39562f4d605f13567398025d30fa27d61 Mon Sep 17 00:00:00 2001 From: Qizhi Hu <836744285@qq.com> Date: Fri, 10 May 2024 20:14:08 +0800 Subject: [PATCH 255/328] [Clang][Sema] access checking of friend declaration should not be delayed (#91430) attempt to fix https://github.com/llvm/llvm-project/issues/12361 Consider this example: ```cpp class D { class E{ class F{}; friend void foo(D::E::F& q); }; friend void foo(D::E::F& q); }; void foo(D::E::F& q) {} ``` The first friend declaration of foo is correct. After that, the second friend declaration delayed access checking and set its previous declaration to be the first one. When doing access checking of `F`(which is private filed of `E`), we put its canonical declaration(the first friend declaration) into `EffectiveContext.Functions`. Actually, we are still checking the first one. This is incorrect due to the delayed checking. Creating a new scope to indicate we are parsing a friend declaration and doing access checking in time. --- clang/docs/ReleaseNotes.rst | 1 + clang/include/clang/Sema/Scope.h | 6 ++++++ clang/lib/Parse/ParseDecl.cpp | 7 +++++-- clang/lib/Sema/Scope.cpp | 1 + clang/lib/Sema/SemaAccess.cpp | 30 +++++++++++++++++++++++++----- clang/test/SemaCXX/PR12361.cpp | 30 ++++++++++++++++++++++++++++++ 6 files changed, 68 insertions(+), 7 deletions(-) create mode 100644 clang/test/SemaCXX/PR12361.cpp diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index eef627ff2e31..7c5dcc59c701 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -706,6 +706,7 @@ Bug Fixes to C++ Support within initializers for variables that are usable in constant expressions or are constant initialized, rather than evaluating them as a part of the larger manifestly constant evaluated expression. +- Fix a bug in access control checking due to dealyed checking of friend declaration. Fixes (#GH12361). Bug Fixes to AST Handling ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Sema/Scope.h b/clang/include/clang/Sema/Scope.h index 1752a25111a7..084db7303421 100644 --- a/clang/include/clang/Sema/Scope.h +++ b/clang/include/clang/Sema/Scope.h @@ -159,6 +159,9 @@ public: /// This is a scope of type alias declaration. TypeAliasScope = 0x20000000, + + /// This is a scope of friend declaration. + FriendScope = 0x40000000, }; private: @@ -586,6 +589,9 @@ public: /// Determine whether this scope is a type alias scope. bool isTypeAliasScope() const { return getFlags() & Scope::TypeAliasScope; } + /// Determine whether this scope is a friend scope. + bool isFriendScope() const { return getFlags() & Scope::FriendScope; } + /// Returns if rhs has a higher scope depth than this. /// /// The caller is responsible for calling this only if one of the two scopes diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp index 2c11ae693c35..5b5fc02ad402 100644 --- a/clang/lib/Parse/ParseDecl.cpp +++ b/clang/lib/Parse/ParseDecl.cpp @@ -4331,9 +4331,12 @@ void Parser::ParseDeclarationSpecifiers( // friend case tok::kw_friend: - if (DSContext == DeclSpecContext::DSC_class) + if (DSContext == DeclSpecContext::DSC_class) { isInvalid = DS.SetFriendSpec(Loc, PrevSpec, DiagID); - else { + Scope *CurS = getCurScope(); + if (!isInvalid && CurS) + CurS->setFlags(CurS->getFlags() | Scope::FriendScope); + } else { PrevSpec = ""; // not actually used by the diagnostic DiagID = diag::err_friend_invalid_in_context; isInvalid = true; diff --git a/clang/lib/Sema/Scope.cpp b/clang/lib/Sema/Scope.cpp index 11a41753a1bd..c08073e80ff3 100644 --- a/clang/lib/Sema/Scope.cpp +++ b/clang/lib/Sema/Scope.cpp @@ -229,6 +229,7 @@ void Scope::dumpImpl(raw_ostream &OS) const { {ClassInheritanceScope, "ClassInheritanceScope"}, {CatchScope, "CatchScope"}, {OpenACCComputeConstructScope, "OpenACCComputeConstructScope"}, + {FriendScope, "FriendScope"}, }; for (auto Info : FlagInfo) { diff --git a/clang/lib/Sema/SemaAccess.cpp b/clang/lib/Sema/SemaAccess.cpp index 6a707eeb66d0..979a64b065f3 100644 --- a/clang/lib/Sema/SemaAccess.cpp +++ b/clang/lib/Sema/SemaAccess.cpp @@ -1473,12 +1473,32 @@ static Sema::AccessResult CheckAccess(Sema &S, SourceLocation Loc, // specifier, like this: // A::private_type A::foo() { ... } // - // Or we might be parsing something that will turn out to be a friend: - // void foo(A::private_type); - // void B::foo(A::private_type); + // friend declaration should not be delayed because it may lead to incorrect + // redeclaration chain, such as: + // class D { + // class E{ + // class F{}; + // friend void foo(D::E::F& q); + // }; + // friend void foo(D::E::F& q); + // }; if (S.DelayedDiagnostics.shouldDelayDiagnostics()) { - S.DelayedDiagnostics.add(DelayedDiagnostic::makeAccess(Loc, Entity)); - return Sema::AR_delayed; + // [class.friend]p9: + // A member nominated by a friend declaration shall be accessible in the + // class containing the friend declaration. The meaning of the friend + // declaration is the same whether the friend declaration appears in the + // private, protected, or public ([class.mem]) portion of the class + // member-specification. + Scope *TS = S.getCurScope(); + bool IsFriendDeclaration = false; + while (TS && !IsFriendDeclaration) { + IsFriendDeclaration = TS->isFriendScope(); + TS = TS->getParent(); + } + if (!IsFriendDeclaration) { + S.DelayedDiagnostics.add(DelayedDiagnostic::makeAccess(Loc, Entity)); + return Sema::AR_delayed; + } } EffectiveContext EC(S.CurContext); diff --git a/clang/test/SemaCXX/PR12361.cpp b/clang/test/SemaCXX/PR12361.cpp new file mode 100644 index 000000000000..95ceb45b7ba0 --- /dev/null +++ b/clang/test/SemaCXX/PR12361.cpp @@ -0,0 +1,30 @@ + // RUN: %clang_cc1 -fsyntax-only -verify -std=c++98 %s + // RUN: %clang_cc1 -fsyntax-only -verify -std=c++17 %s + +class D { + class E{ + class F{}; // expected-note{{implicitly declared private here}} + friend void foo(D::E::F& q); + }; + friend void foo(D::E::F& q); // expected-error{{'F' is a private member of 'D::E'}} + }; + +void foo(D::E::F& q) {} + +class D1 { + class E1{ + class F1{}; // expected-note{{implicitly declared private here}} + friend D1::E1::F1 foo1(); + }; + friend D1::E1::F1 foo1(); // expected-error{{'F1' is a private member of 'D1::E1'}} + }; + +D1::E1::F1 foo1() { return D1::E1::F1(); } + +class D2 { + class E2{ + class F2{}; + friend void foo2(); + }; + friend void foo2(){ D2::E2::F2 c;} + }; -- GitLab From 8c852ab57932a5cd954cb0d050c3d2ab486428df Mon Sep 17 00:00:00 2001 From: Younan Zhang Date: Fri, 10 May 2024 20:47:15 +0800 Subject: [PATCH 256/328] [Clang][Sema] Revise the transformation of CTAD parameters of nested class templates (#91628) This fixes a regression introduced by bee78b88f. When we form a deduction guide for a constructor, basically, we do the following work: - Collect template parameters from the constructor's surrounding class template, if present. - Collect template parameters from the constructor. - Splice these template parameters together into a new template parameter list. - Turn all the references (e.g. the function parameter list) to the invented parameter list by applying a `TreeTransform` to the function type. In the previous fix, we handled cases of nested class templates by substituting the "outer" template parameters (i.e. those not declared at the surrounding class template or the constructor) with the instantiating template arguments. The approach per se makes sense, but there was a flaw in the following case: ```cpp template struct X { template struct Y { template Y(T) {} }; template Y(T) -> Y; }; X::Y y(42); ``` While we're transforming the parameters for `Y(T)`, we first attempt to transform all references to `V` and `T`; then, we handle the references to outer parameters `U` and `Us` using the template arguments from `X` by transforming the same `ParamDecl`. However, the first step results in the reference `T` being `` because the invented `T` is the last of the parameter list of the deduction guide, and what we're substituting with is a corresponding parameter pack (which is `Us`, though empty). Hence we're messing up the substitution. I think we can resolve it by reversing the substitution order, which means handling outer template parameters first and then the inner parameters. There's no release note because this is a regression in 18, and I hope we can catch up with the last release. Fixes https://github.com/llvm/llvm-project/issues/88142 --- clang/lib/Sema/SemaTemplate.cpp | 25 ++++++++++++++----- .../nested-implicit-deduction-guides.cpp | 14 +++++++++++ 2 files changed, 33 insertions(+), 6 deletions(-) diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index 2fce2238f9c1..480c0103ae33 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -2492,9 +2492,6 @@ struct ConvertConstructorToDeductionGuideTransform { Args.addOuterRetainedLevel(); } - if (NestedPattern) - Args.addOuterRetainedLevels(NestedPattern->getTemplateDepth()); - FunctionProtoTypeLoc FPTL = CD->getTypeSourceInfo()->getTypeLoc() .getAsAdjusted(); assert(FPTL && "no prototype for constructor declaration"); @@ -2584,11 +2581,27 @@ private: // -- The types of the function parameters are those of the constructor. for (auto *OldParam : TL.getParams()) { - ParmVarDecl *NewParam = - transformFunctionTypeParam(OldParam, Args, MaterializedTypedefs); - if (NestedPattern && NewParam) + ParmVarDecl *NewParam = OldParam; + // Given + // template struct C { + // template struct D { + // template D(U, V); + // }; + // }; + // First, transform all the references to template parameters that are + // defined outside of the surrounding class template. That is T in the + // above example. + if (NestedPattern) { NewParam = transformFunctionTypeParam(NewParam, OuterInstantiationArgs, MaterializedTypedefs); + if (!NewParam) + return QualType(); + } + // Then, transform all the references to template parameters that are + // defined at the class template and the constructor. In this example, + // they're U and V, respectively. + NewParam = + transformFunctionTypeParam(NewParam, Args, MaterializedTypedefs); if (!NewParam) return QualType(); ParamTypes.push_back(NewParam->getType()); diff --git a/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp b/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp index 38b6706595a1..f289dc045286 100644 --- a/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp +++ b/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp @@ -84,3 +84,17 @@ nested_init_list::concept_fail nil_invalid{1, ""}; // expected-note@#INIT_LIST_INNER_INVALID {{candidate template ignored: substitution failure [with F = const char *]: constraints not satisfied for class template 'concept_fail' [with F = const char *]}} // expected-note@#INIT_LIST_INNER_INVALID {{candidate function template not viable: requires 1 argument, but 2 were provided}} // expected-note@#INIT_LIST_INNER_INVALID {{candidate function template not viable: requires 0 arguments, but 2 were provided}} + +namespace GH88142 { + +template struct X { + template struct Y { + template Y(T) {} + }; + + template Y(T) -> Y; +}; + +X::Y y(42); + +} // namespace PR88142 -- GitLab From 452f4393c70e0ffecf8e394f82b1eaeaa8d224af Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Fri, 10 May 2024 13:47:22 +0100 Subject: [PATCH 257/328] [InstCombine] Precommit tests for #86111 The upcoming patch adds logic to prefer to use constants close to power-of-two in these ashr exact + slt/ult patterns when it has a choice on which constant can be used. --- .../Transforms/InstCombine/icmp-shr-lt-gt.ll | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll b/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll index 1b8efe4351c6..4dd5b0925914 100644 --- a/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll +++ b/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll @@ -3800,3 +3800,64 @@ define i1 @ashrslt_03_15_exact(i4 %x) { ret i1 %c } +; TODO: The resulting compared constant can be safely replaced with one that +; is closer to a power of two. +define i1 @ashr_slt_exact_near_pow2_cmpval(i8 %x) { +; CHECK-LABEL: @ashr_slt_exact_near_pow2_cmpval( +; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[X:%.*]], 10 +; CHECK-NEXT: ret i1 [[C]] +; + %s = ashr exact i8 %x, 1 + %c = icmp slt i8 %s, 5 + ret i1 %c +} + +define i1 @ashr_ult_exact_near_pow2_cmpval(i8 %x) { +; CHECK-LABEL: @ashr_ult_exact_near_pow2_cmpval( +; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[X:%.*]], 10 +; CHECK-NEXT: ret i1 [[C]] +; + %s = ashr exact i8 %x, 1 + %c = icmp ult i8 %s, 5 + ret i1 %c +} + +define i1 @negtest_near_pow2_cmpval_ashr_slt_noexact(i8 %x) { +; CHECK-LABEL: @negtest_near_pow2_cmpval_ashr_slt_noexact( +; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[X:%.*]], 10 +; CHECK-NEXT: ret i1 [[C]] +; + %s = ashr i8 %x, 1 + %c = icmp slt i8 %s, 5 + ret i1 %c +} + +define i1 @negtest_near_pow2_cmpval_ashr_wrong_cmp_pred(i8 %x) { +; CHECK-LABEL: @negtest_near_pow2_cmpval_ashr_wrong_cmp_pred( +; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[X:%.*]], 10 +; CHECK-NEXT: ret i1 [[C]] +; + %s = ashr exact i8 %x, 1 + %c = icmp eq i8 %s, 5 + ret i1 %c +} + +define i1 @negtest_near_pow2_cmpval_isnt_close_to_pow2(i8 %x) { +; CHECK-LABEL: @negtest_near_pow2_cmpval_isnt_close_to_pow2( +; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[X:%.*]], 12 +; CHECK-NEXT: ret i1 [[C]] +; + %s = ashr exact i8 %x, 1 + %c = icmp slt i8 %s, 6 + ret i1 %c +} + +define i1 @negtest_near_pow2_cmpval_would_overflow_into_signbit(i8 %x) { +; CHECK-LABEL: @negtest_near_pow2_cmpval_would_overflow_into_signbit( +; CHECK-NEXT: [[C:%.*]] = icmp sgt i8 [[X:%.*]], -1 +; CHECK-NEXT: ret i1 [[C]] +; + %s = ashr exact i8 %x, 2 + %c = icmp ult i8 %s, 33 + ret i1 %c +} -- GitLab From 3be8e2c95d3dca5b2fdea889649a69dce8605e65 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Fri, 10 May 2024 13:50:03 +0100 Subject: [PATCH 258/328] [InstCombine] Prefer to keep power-of-2 constants when combining ashr exact and slt/ult of a constant (#86111) We have flexibility in what constant to use when combining an `ashr exact` with a slt or ult of a constant, and it's not possible to revisit this decision later in the compilation pipeline after the `ashr exact` is removed. Keeping a constant close to power-of-2 (pow2val + 1) should be no worse than neutral, and in some cases may allow better codegen later on for targets that can more cheaply generate power of 2 (which may be selectable if converting back to setle/setge) or near power of 2 constants. Alive2 proofs: and --- .../lib/Transforms/InstCombine/InstCombineCompares.cpp | 10 ++++++++++ llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll | 10 ++++------ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index e1a3194a1beb..9883d02c87a3 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -2479,6 +2479,16 @@ Instruction *InstCombinerImpl::foldICmpShrConstant(ICmpInst &Cmp, // those conditions rather than checking them. This is difficult because of // undef/poison (PR34838). if (IsAShr && Shr->hasOneUse()) { + if (IsExact && (Pred == CmpInst::ICMP_SLT || Pred == CmpInst::ICMP_ULT) && + (C - 1).isPowerOf2() && C.countLeadingZeros() > ShAmtVal) { + // When C - 1 is a power of two and the transform can be legally + // performed, prefer this form so the produced constant is close to a + // power of two. + // icmp slt/ult (ashr exact X, ShAmtC), C + // --> icmp slt/ult X, (C - 1) << ShAmtC) + 1 + APInt ShiftedC = (C - 1).shl(ShAmtVal) + 1; + return new ICmpInst(Pred, X, ConstantInt::get(ShrTy, ShiftedC)); + } if (IsExact || Pred == CmpInst::ICMP_SLT || Pred == CmpInst::ICMP_ULT) { // When ShAmtC can be shifted losslessly: // icmp PRED (ashr exact X, ShAmtC), C --> icmp PRED X, (C << ShAmtC) diff --git a/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll b/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll index 4dd5b0925914..5f09964fd93a 100644 --- a/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll +++ b/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll @@ -3379,7 +3379,7 @@ define i1 @ashrslt_01_01_exact(i4 %x) { define i1 @ashrslt_01_02_exact(i4 %x) { ; CHECK-LABEL: @ashrslt_01_02_exact( -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[X:%.*]], 4 +; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[X:%.*]], 3 ; CHECK-NEXT: ret i1 [[C]] ; %s = ashr exact i4 %x, 1 @@ -3389,7 +3389,7 @@ define i1 @ashrslt_01_02_exact(i4 %x) { define i1 @ashrslt_01_03_exact(i4 %x) { ; CHECK-LABEL: @ashrslt_01_03_exact( -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[X:%.*]], 6 +; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[X:%.*]], 5 ; CHECK-NEXT: ret i1 [[C]] ; %s = ashr exact i4 %x, 1 @@ -3800,11 +3800,9 @@ define i1 @ashrslt_03_15_exact(i4 %x) { ret i1 %c } -; TODO: The resulting compared constant can be safely replaced with one that -; is closer to a power of two. define i1 @ashr_slt_exact_near_pow2_cmpval(i8 %x) { ; CHECK-LABEL: @ashr_slt_exact_near_pow2_cmpval( -; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[X:%.*]], 10 +; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[X:%.*]], 9 ; CHECK-NEXT: ret i1 [[C]] ; %s = ashr exact i8 %x, 1 @@ -3814,7 +3812,7 @@ define i1 @ashr_slt_exact_near_pow2_cmpval(i8 %x) { define i1 @ashr_ult_exact_near_pow2_cmpval(i8 %x) { ; CHECK-LABEL: @ashr_ult_exact_near_pow2_cmpval( -; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[X:%.*]], 10 +; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[X:%.*]], 9 ; CHECK-NEXT: ret i1 [[C]] ; %s = ashr exact i8 %x, 1 -- GitLab From d48bf8aef2abeb915b1e04e1b78051869088df42 Mon Sep 17 00:00:00 2001 From: DianQK Date: Fri, 10 May 2024 19:19:51 +0800 Subject: [PATCH 259/328] Reapply "[InlineCost] Correct the default branch cost for the switch statement (#85160)" This reverts commit c6e4f6309184814dfc4bb855ddbdb5375cc971e0. --- llvm/lib/Analysis/InlineCost.cpp | 25 ++-- .../Inline/inline-cost-switch-default.ll | 130 ++++++++++++++++++ .../Inline/inline-switch-default-2.ll | 21 +-- .../Inline/inline-switch-default.ll | 26 +--- 4 files changed, 153 insertions(+), 49 deletions(-) create mode 100644 llvm/test/Transforms/Inline/inline-cost-switch-default.ll diff --git a/llvm/lib/Analysis/InlineCost.cpp b/llvm/lib/Analysis/InlineCost.cpp index a531064e304d..f5b17dca4973 100644 --- a/llvm/lib/Analysis/InlineCost.cpp +++ b/llvm/lib/Analysis/InlineCost.cpp @@ -701,21 +701,26 @@ class InlineCostCallAnalyzer final : public CallAnalyzer { void onFinalizeSwitch(unsigned JumpTableSize, unsigned NumCaseCluster, bool DefaultDestUndefined) override { - if (!DefaultDestUndefined) - addCost(2 * InstrCost); // If suitable for a jump table, consider the cost for the table size and // branch to destination. // Maximum valid cost increased in this function. if (JumpTableSize) { + // Suppose a default branch includes one compare and one conditional + // branch if it's reachable. + if (!DefaultDestUndefined) + addCost(2 * InstrCost); + // Suppose a jump table requires one load and one jump instruction. int64_t JTCost = - static_cast(JumpTableSize) * InstrCost + 4 * InstrCost; + static_cast(JumpTableSize) * InstrCost + 2 * InstrCost; addCost(JTCost); return; } if (NumCaseCluster <= 3) { // Suppose a comparison includes one compare and one conditional branch. - addCost(NumCaseCluster * 2 * InstrCost); + // We can reduce a set of instructions if the default branch is + // undefined. + addCost((NumCaseCluster - DefaultDestUndefined) * 2 * InstrCost); return; } @@ -1152,7 +1157,7 @@ private: // FIXME: These constants are taken from the heuristic-based cost visitor. // These should be removed entirely in a later revision to avoid reliance on // heuristics in the ML inliner. - static constexpr int JTCostMultiplier = 4; + static constexpr int JTCostMultiplier = 2; static constexpr int CaseClusterCostMultiplier = 2; static constexpr int SwitchDefaultDestCostMultiplier = 2; static constexpr int SwitchCostMultiplier = 2; @@ -1235,11 +1240,10 @@ private: void onFinalizeSwitch(unsigned JumpTableSize, unsigned NumCaseCluster, bool DefaultDestUndefined) override { - if (!DefaultDestUndefined) - increment(InlineCostFeatureIndex::switch_default_dest_penalty, - SwitchDefaultDestCostMultiplier * InstrCost); - if (JumpTableSize) { + if (!DefaultDestUndefined) + increment(InlineCostFeatureIndex::switch_default_dest_penalty, + SwitchDefaultDestCostMultiplier * InstrCost); int64_t JTCost = static_cast(JumpTableSize) * InstrCost + JTCostMultiplier * InstrCost; increment(InlineCostFeatureIndex::jump_table_penalty, JTCost); @@ -1248,7 +1252,8 @@ private: if (NumCaseCluster <= 3) { increment(InlineCostFeatureIndex::case_cluster_penalty, - NumCaseCluster * CaseClusterCostMultiplier * InstrCost); + (NumCaseCluster - DefaultDestUndefined) * + CaseClusterCostMultiplier * InstrCost); return; } diff --git a/llvm/test/Transforms/Inline/inline-cost-switch-default.ll b/llvm/test/Transforms/Inline/inline-cost-switch-default.ll new file mode 100644 index 000000000000..e3768ac8233a --- /dev/null +++ b/llvm/test/Transforms/Inline/inline-cost-switch-default.ll @@ -0,0 +1,130 @@ +; RUN: opt -S -passes=inline %s -debug-only=inline-cost -min-jump-table-entries=4 --disable-output 2>&1 | FileCheck %s -check-prefix=LOOKUPTABLE -match-full-lines +; RUN: opt -S -passes=inline %s -debug-only=inline-cost -min-jump-table-entries=5 --disable-output 2>&1 | FileCheck %s -check-prefix=SWITCH -match-full-lines +; REQUIRES: x86_64-linux, asserts + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i64 @main(i64 %a) { + %b = call i64 @small_switch_default(i64 %a) + %c = call i64 @small_switch_no_default(i64 %a) + %d = call i64 @lookup_table_default(i64 %a) + %e = call i64 @lookup_table_no_default(i64 %a) + ret i64 %b +} + +; SWITCH-LABEL: Analyzing call of small_switch_default{{.*}} +; SWITCH: Cost: 0 +define i64 @small_switch_default(i64 %a) { + switch i64 %a, label %default_branch [ + i64 -1, label %branch_0 + i64 8, label %branch_1 + i64 52, label %branch_2 + ] + +branch_0: + br label %exit + +branch_1: + br label %exit + +branch_2: + br label %exit + +default_branch: + br label %exit + +exit: + %b = phi i64 [ 5, %branch_0 ], [ 9, %branch_1 ], [ 2, %branch_2 ], [ 3, %default_branch ] + ret i64 %b +} + +; SWITCH-LABEL: Analyzing call of small_switch_no_default{{.*}} +; SWITCH: Cost: -10 +define i64 @small_switch_no_default(i64 %a) { + switch i64 %a, label %unreachabledefault [ + i64 -1, label %branch_0 + i64 8, label %branch_1 + i64 52, label %branch_2 + ] + +branch_0: + br label %exit + +branch_1: + br label %exit + +branch_2: + br label %exit + +unreachabledefault: + unreachable + +exit: + %b = phi i64 [ 5, %branch_0 ], [ 9, %branch_1 ], [ 2, %branch_2 ] + ret i64 %b +} + +; LOOKUPTABLE-LABEL: Analyzing call of lookup_table_default{{.*}} +; LOOKUPTABLE: Cost: 10 +; SWITCH-LABEL: Analyzing call of lookup_table_default{{.*}} +; SWITCH: Cost: 20 +define i64 @lookup_table_default(i64 %a) { + switch i64 %a, label %default_branch [ + i64 0, label %branch_0 + i64 1, label %branch_1 + i64 2, label %branch_2 + i64 3, label %branch_3 + ] + +branch_0: + br label %exit + +branch_1: + br label %exit + +branch_2: + br label %exit + +branch_3: + br label %exit + +default_branch: + br label %exit + +exit: + %b = phi i64 [ 5, %branch_0 ], [ 9, %branch_1 ], [ 2, %branch_2 ], [ 7, %branch_3 ], [ 3, %default_branch ] + ret i64 %b +} + +; LOOKUPTABLE-LABEL: Analyzing call of lookup_table_no_default{{.*}} +; LOOKUPTABLE: Cost: 0 +; SWITCH-LABEL: Analyzing call of lookup_table_no_default{{.*}} +; SWITCH: Cost: 20 +define i64 @lookup_table_no_default(i64 %a) { + switch i64 %a, label %unreachabledefault [ + i64 0, label %branch_0 + i64 1, label %branch_1 + i64 2, label %branch_2 + i64 3, label %branch_3 + ] + +branch_0: + br label %exit + +branch_1: + br label %exit + +branch_2: + br label %exit + +branch_3: + br label %exit + +unreachabledefault: + unreachable + +exit: + %b = phi i64 [ 5, %branch_0 ], [ 9, %branch_1 ], [ 2, %branch_2 ], [ 7, %branch_3 ] + ret i64 %b +} diff --git a/llvm/test/Transforms/Inline/inline-switch-default-2.ll b/llvm/test/Transforms/Inline/inline-switch-default-2.ll index 82dae1c27648..169cb2cff9b8 100644 --- a/llvm/test/Transforms/Inline/inline-switch-default-2.ll +++ b/llvm/test/Transforms/Inline/inline-switch-default-2.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt %s -S -passes=inline -inline-threshold=21 | FileCheck %s +; RUN: opt %s -S -passes=inline -inline-threshold=11 | FileCheck %s ; Check for scenarios without TTI. @@ -16,24 +16,7 @@ define i64 @foo1(i64 %a) { define i64 @foo2(i64 %a) { ; CHECK-LABEL: define i64 @foo2( ; CHECK-SAME: i64 [[A:%.*]]) { -; CHECK-NEXT: switch i64 [[A]], label [[UNREACHABLEDEFAULT_I:%.*]] [ -; CHECK-NEXT: i64 0, label [[BRANCH_0_I:%.*]] -; CHECK-NEXT: i64 2, label [[BRANCH_2_I:%.*]] -; CHECK-NEXT: i64 4, label [[BRANCH_4_I:%.*]] -; CHECK-NEXT: i64 6, label [[BRANCH_6_I:%.*]] -; CHECK-NEXT: ] -; CHECK: branch_0.i: -; CHECK-NEXT: br label [[BAR2_EXIT:%.*]] -; CHECK: branch_2.i: -; CHECK-NEXT: br label [[BAR2_EXIT]] -; CHECK: branch_4.i: -; CHECK-NEXT: br label [[BAR2_EXIT]] -; CHECK: branch_6.i: -; CHECK-NEXT: br label [[BAR2_EXIT]] -; CHECK: unreachabledefault.i: -; CHECK-NEXT: unreachable -; CHECK: bar2.exit: -; CHECK-NEXT: [[B_I:%.*]] = phi i64 [ 5, [[BRANCH_0_I]] ], [ 9, [[BRANCH_2_I]] ], [ 2, [[BRANCH_4_I]] ], [ 7, [[BRANCH_6_I]] ] +; CHECK-NEXT: [[B_I:%.*]] = call i64 @bar2(i64 [[A]]) ; CHECK-NEXT: ret i64 [[B_I]] ; %b = call i64 @bar2(i64 %a) diff --git a/llvm/test/Transforms/Inline/inline-switch-default.ll b/llvm/test/Transforms/Inline/inline-switch-default.ll index 44f1304e82df..288d414fe0e0 100644 --- a/llvm/test/Transforms/Inline/inline-switch-default.ll +++ b/llvm/test/Transforms/Inline/inline-switch-default.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt %s -S -passes=inline -inline-threshold=26 -min-jump-table-entries=4 | FileCheck %s -check-prefix=LOOKUPTABLE -; RUN: opt %s -S -passes=inline -inline-threshold=21 -min-jump-table-entries=5 | FileCheck %s -check-prefix=SWITCH +; RUN: opt %s -S -passes=inline -inline-threshold=16 -min-jump-table-entries=4 | FileCheck %s -check-prefix=LOOKUPTABLE +; RUN: opt %s -S -passes=inline -inline-threshold=11 -min-jump-table-entries=5 | FileCheck %s -check-prefix=SWITCH +; REQUIRES: x86_64-linux target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @@ -22,6 +23,8 @@ define i64 @foo1(i64 %a) { ret i64 %b } +; Since the default branch is undefined behavior, +; we can inline `bar2`: https://github.com/llvm/llvm-project/issues/90929 define i64 @foo2(i64 %a) { ; LOOKUPTABLE-LABEL: define i64 @foo2( ; LOOKUPTABLE-SAME: i64 [[A:%.*]]) { @@ -47,24 +50,7 @@ define i64 @foo2(i64 %a) { ; ; SWITCH-LABEL: define i64 @foo2( ; SWITCH-SAME: i64 [[A:%.*]]) { -; SWITCH-NEXT: switch i64 [[A]], label [[UNREACHABLEDEFAULT_I:%.*]] [ -; SWITCH-NEXT: i64 0, label [[BRANCH_0_I:%.*]] -; SWITCH-NEXT: i64 2, label [[BRANCH_2_I:%.*]] -; SWITCH-NEXT: i64 4, label [[BRANCH_4_I:%.*]] -; SWITCH-NEXT: i64 6, label [[BRANCH_6_I:%.*]] -; SWITCH-NEXT: ] -; SWITCH: branch_0.i: -; SWITCH-NEXT: br label [[BAR2_EXIT:%.*]] -; SWITCH: branch_2.i: -; SWITCH-NEXT: br label [[BAR2_EXIT]] -; SWITCH: branch_4.i: -; SWITCH-NEXT: br label [[BAR2_EXIT]] -; SWITCH: branch_6.i: -; SWITCH-NEXT: br label [[BAR2_EXIT]] -; SWITCH: unreachabledefault.i: -; SWITCH-NEXT: unreachable -; SWITCH: bar2.exit: -; SWITCH-NEXT: [[B_I:%.*]] = phi i64 [ 5, [[BRANCH_0_I]] ], [ 9, [[BRANCH_2_I]] ], [ 2, [[BRANCH_4_I]] ], [ 7, [[BRANCH_6_I]] ] +; SWITCH-NEXT: [[B_I:%.*]] = call i64 @bar2(i64 [[A]]) ; SWITCH-NEXT: ret i64 [[B_I]] ; %b = call i64 @bar2(i64 %a) -- GitLab From 561b6ab96e9d5b38a5d2672e6cc6823389b75a3f Mon Sep 17 00:00:00 2001 From: Xing Xue Date: Fri, 10 May 2024 09:23:02 -0400 Subject: [PATCH 260/328] [OpenMP][AIX] Implement __kmp_get_load_balance() for AIX (#91520) AIX has the `/proc` filesystem where `/proc//lwp//lwpsinfo` has the thread state in binary, similar to Linux's `/proc//task//stat` where the state is in ASCII. However, the definition of state info `R` in `lwpsinfo` is `runnable`. In Linux, state `R` means the thread is `running`. Therefore, `lwpsinfo` is not ideal for our purpose of getting the current load of the system. This patch uses `perfstat_cpu()` in AIX system library `libperfstat.a` to obtain the number of threads current running on logical CPUs. --- openmp/runtime/CMakeLists.txt | 9 ++-- openmp/runtime/src/z_Linux_util.cpp | 83 +++++++++++++++++++++++++---- 2 files changed, 80 insertions(+), 12 deletions(-) diff --git a/openmp/runtime/CMakeLists.txt b/openmp/runtime/CMakeLists.txt index 57ed54bcdc7b..bcae02eba6a5 100644 --- a/openmp/runtime/CMakeLists.txt +++ b/openmp/runtime/CMakeLists.txt @@ -132,10 +132,13 @@ set(LIBOMP_ASMFLAGS "" CACHE STRING "Appended user specified assembler flags.") set(LIBOMP_LDFLAGS "" CACHE STRING "Appended user specified linker flags.") -if("${LIBOMP_ARCH}" STREQUAL "ppc" AND ${CMAKE_SYSTEM_NAME} MATCHES "AIX") - # PPC (32-bit) on AIX needs libatomic for __atomic_load_8, etc. - set(LIBOMP_LIBFLAGS "-latomic" CACHE STRING +if(${CMAKE_SYSTEM_NAME} MATCHES "AIX") + set(LIBOMP_LIBFLAGS "-lperfstat" CACHE STRING "Appended user specified linked libs flags. (e.g., -lm)") + if("${LIBOMP_ARCH}" STREQUAL "ppc") + # PPC (32-bit) on AIX needs libatomic for __atomic_load_8, etc. + set(LIBOMP_LIBFLAGS "${LIBOMP_LIBFLAGS} -latomic") + endif() else() set(LIBOMP_LIBFLAGS "" CACHE STRING "Appended user specified linked libs flags. (e.g., -lm)") diff --git a/openmp/runtime/src/z_Linux_util.cpp b/openmp/runtime/src/z_Linux_util.cpp index affb577a5393..7c90740ae5bd 100644 --- a/openmp/runtime/src/z_Linux_util.cpp +++ b/openmp/runtime/src/z_Linux_util.cpp @@ -31,6 +31,7 @@ #include #if KMP_OS_AIX #include +#include #else #include #endif @@ -2427,6 +2428,79 @@ int __kmp_get_load_balance(int max) { return ret_avg; } +#elif KMP_OS_AIX + +// The function returns number of running (not sleeping) threads, or -1 in case +// of error. +int __kmp_get_load_balance(int max) { + + static int glb_running_threads = 0; // Saved count of the running threads for + // the thread balance algorithm. + static double glb_call_time = 0; // Thread balance algorithm call time. + int running_threads = 0; // Number of running threads in the system. + + double call_time = 0.0; + + __kmp_elapsed(&call_time); + + if (glb_call_time && + (call_time - glb_call_time < __kmp_load_balance_interval)) + return glb_running_threads; + + glb_call_time = call_time; + + if (max <= 0) { + max = INT_MAX; + } + + // Check how many perfstat_cpu_t structures are available. + int logical_cpus = perfstat_cpu(NULL, NULL, sizeof(perfstat_cpu_t), 0); + if (logical_cpus <= 0) { + glb_call_time = -1; + return -1; + } + + perfstat_cpu_t *cpu_stat = (perfstat_cpu_t *)KMP_INTERNAL_MALLOC( + logical_cpus * sizeof(perfstat_cpu_t)); + if (cpu_stat == NULL) { + glb_call_time = -1; + return -1; + } + + // Set first CPU as the name of the first logical CPU for which the info is + // desired. + perfstat_id_t first_cpu_name; + strcpy(first_cpu_name.name, FIRST_CPU); + + // Get the stat info of logical CPUs. + int rc = perfstat_cpu(&first_cpu_name, cpu_stat, sizeof(perfstat_cpu_t), + logical_cpus); + KMP_DEBUG_ASSERT(rc == logical_cpus); + if (rc <= 0) { + KMP_INTERNAL_FREE(cpu_stat); + glb_call_time = -1; + return -1; + } + for (int i = 0; i < logical_cpus; ++i) { + running_threads += cpu_stat[i].runque; + if (running_threads >= max) + break; + } + + // There _might_ be a timing hole where the thread executing this + // code gets skipped in the load balance, and running_threads is 0. + // Assert in the debug builds only!!! + KMP_DEBUG_ASSERT(running_threads > 0); + if (running_threads <= 0) + running_threads = 1; + + KMP_INTERNAL_FREE(cpu_stat); + + glb_running_threads = running_threads; + + return running_threads; +} + #else // Linux* OS // The function returns number of running (not sleeping) threads, or -1 in case @@ -2498,14 +2572,9 @@ int __kmp_get_load_balance(int max) { proc_entry = readdir(proc_dir); while (proc_entry != NULL) { -#if KMP_OS_AIX - // Proc entry name starts with a digit. Assume it is a process' directory. - if (isdigit(proc_entry->d_name[0])) { -#else // Proc entry is a directory and name starts with a digit. Assume it is a // process' directory. if (proc_entry->d_type == DT_DIR && isdigit(proc_entry->d_name[0])) { -#endif #ifdef KMP_DEBUG ++total_processes; @@ -2549,11 +2618,7 @@ int __kmp_get_load_balance(int max) { task_entry = readdir(task_dir); while (task_entry != NULL) { // It is a directory and name starts with a digit. -#if KMP_OS_AIX - if (isdigit(task_entry->d_name[0])) { -#else if (proc_entry->d_type == DT_DIR && isdigit(task_entry->d_name[0])) { -#endif // Construct complete stat file path. Easiest way would be: // __kmp_str_buf_print( & stat_path, "%s/%s/stat", task_path.str, -- GitLab From 195d8ac26d91ca798733c3a5f58d67992d43503d Mon Sep 17 00:00:00 2001 From: Xiang Li Date: Fri, 10 May 2024 06:29:23 -0700 Subject: [PATCH 261/328] [DirectX] Fix DXIL part header version encoding (#91506) Move MinorVersion be the lower 8 bit. Set DXIL version in DXContainerObjectWriter::writeObject. Fixes #89952 --- llvm/include/llvm/BinaryFormat/DXContainer.h | 2 +- llvm/include/llvm/TargetParser/Triple.h | 2 +- llvm/lib/MC/MCDXContainerWriter.cpp | 3 + llvm/lib/TargetParser/Triple.cpp | 2 + llvm/test/CodeGen/DirectX/embed-dxil.ll | 4 +- llvm/unittests/Object/DXContainerTest.cpp | 59 +++++++++++++++++--- 6 files changed, 61 insertions(+), 11 deletions(-) diff --git a/llvm/include/llvm/BinaryFormat/DXContainer.h b/llvm/include/llvm/BinaryFormat/DXContainer.h index e8d03f806715..e5fcda63910d 100644 --- a/llvm/include/llvm/BinaryFormat/DXContainer.h +++ b/llvm/include/llvm/BinaryFormat/DXContainer.h @@ -103,8 +103,8 @@ struct PartHeader { struct BitcodeHeader { uint8_t Magic[4]; // ACSII "DXIL". - uint8_t MajorVersion; // DXIL version. uint8_t MinorVersion; // DXIL version. + uint8_t MajorVersion; // DXIL version. uint16_t Unused; uint32_t Offset; // Offset to LLVM bitcode (from start of header). uint32_t Size; // Size of LLVM bitcode (in bytes). diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h index 8f9d99816931..b3bb354b38ff 100644 --- a/llvm/include/llvm/TargetParser/Triple.h +++ b/llvm/include/llvm/TargetParser/Triple.h @@ -429,7 +429,7 @@ public: /// (SubArch). This should only be called with Vulkan SPIR-V triples. VersionTuple getVulkanVersion() const; - /// Parse the DXIL version number from the DXIL version + /// Parse the DXIL version number from the OSVersion and DXIL version /// (SubArch). This should only be called with DXIL triples. VersionTuple getDXILVersion() const; diff --git a/llvm/lib/MC/MCDXContainerWriter.cpp b/llvm/lib/MC/MCDXContainerWriter.cpp index 0580dc7e4282..015899278f37 100644 --- a/llvm/lib/MC/MCDXContainerWriter.cpp +++ b/llvm/lib/MC/MCDXContainerWriter.cpp @@ -127,6 +127,9 @@ uint64_t DXContainerObjectWriter::writeObject(MCAssembler &Asm, // The program header's size field is in 32-bit words. Header.Size = (SectionSize + sizeof(dxbc::ProgramHeader) + 3) / 4; memcpy(Header.Bitcode.Magic, "DXIL", 4); + VersionTuple DXILVersion = TT.getDXILVersion(); + Header.Bitcode.MajorVersion = DXILVersion.getMajor(); + Header.Bitcode.MinorVersion = DXILVersion.getMinor().value_or(0); Header.Bitcode.Offset = sizeof(dxbc::BitcodeHeader); Header.Bitcode.Size = SectionSize; if (sys::IsBigEndianHost) diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp index f8269a51dc0b..4fc1ff5aaa05 100644 --- a/llvm/lib/TargetParser/Triple.cpp +++ b/llvm/lib/TargetParser/Triple.cpp @@ -1510,6 +1510,8 @@ VersionTuple Triple::getDXILVersion() const { if (getArch() != dxil || getOS() != ShaderModel) llvm_unreachable("invalid DXIL triple"); StringRef Arch = getArchName(); + if (getSubArch() == NoSubArch) + Arch = getDXILArchNameFromShaderModel(getOSName()); Arch.consume_front("dxilv"); VersionTuple DXILVersion = parseVersionFromName(Arch); // FIXME: validate DXIL version against Shader Model version. diff --git a/llvm/test/CodeGen/DirectX/embed-dxil.ll b/llvm/test/CodeGen/DirectX/embed-dxil.ll index 306e5c385b5a..9f4fb19d86fa 100644 --- a/llvm/test/CodeGen/DirectX/embed-dxil.ll +++ b/llvm/test/CodeGen/DirectX/embed-dxil.ll @@ -42,8 +42,8 @@ define i32 @add(i32 %a, i32 %b) { ; DXC-NEXT: MinorVersion: 5 ; DXC-NEXT: ShaderKind: 6 ; DXC-NEXT: Size: [[#div(SIZE,4)]] -; DXC-NEXT: DXILMajorVersion: [[#]] -; DXC-NEXT: DXILMinorVersion: [[#]] +; DXC-NEXT: DXILMajorVersion: 1 +; DXC-NEXT: DXILMinorVersion: 5 ; DXC-NEXT: DXILSize: [[#SIZE - 24]] ; DXC-NEXT: DXIL: [ 0x42, 0x43, 0xC0, 0xDE, ; DXC: - Name: SFI0 diff --git a/llvm/unittests/Object/DXContainerTest.cpp b/llvm/unittests/Object/DXContainerTest.cpp index da640225617d..098da331ab56 100644 --- a/llvm/unittests/Object/DXContainerTest.cpp +++ b/llvm/unittests/Object/DXContainerTest.cpp @@ -126,6 +126,51 @@ TEST(DXCFile, ParseOverlappingParts) { "Part offset for part 1 begins before the previous part ends")); } +// This test verify DXILMajorVersion and DXILMinorVersion are correctly parsed. +// This test is based on the binary output constructed from this yaml. +// --- !dxcontainer +// Header: +// Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, +// 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ] +// Version: +// Major: 1 +// Minor: 0 +// PartCount: 1 +// Parts: +// - Name: DXIL +// Size: 28 +// Program: +// MajorVersion: 6 +// MinorVersion: 5 +// ShaderKind: 5 +// Size: 8 +// DXILMajorVersion: 1 +// DXILMinorVersion: 5 +// DXILSize: 4 +// DXIL: [ 0x42, 0x43, 0xC0, 0xDE, ] +// ... +TEST(DXCFile, ParseDXILPart) { + uint8_t Buffer[] = { + 0x44, 0x58, 0x42, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, + 0x44, 0x58, 0x49, 0x4c, 0x1c, 0x00, 0x00, 0x00, 0x65, 0x00, 0x05, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x44, 0x58, 0x49, 0x4c, 0x05, 0x01, 0x00, 0x00, + 0x10, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x42, 0x43, 0xc0, 0xde}; + DXContainer C = + llvm::cantFail(DXContainer::create(getMemoryBuffer<116>(Buffer))); + EXPECT_EQ(C.getHeader().PartCount, 1u); + const std::optional &DXIL = C.getDXIL(); + EXPECT_TRUE(DXIL.has_value()); + dxbc::ProgramHeader Header = DXIL->first; + EXPECT_EQ(Header.MajorVersion, 6u); + EXPECT_EQ(Header.MinorVersion, 5u); + EXPECT_EQ(Header.ShaderKind, 5u); + EXPECT_EQ(Header.Size, 8u); + EXPECT_EQ(Header.Bitcode.MajorVersion, 1u); + EXPECT_EQ(Header.Bitcode.MinorVersion, 5u); +} + TEST(DXCFile, ParseEmptyParts) { uint8_t Buffer[] = { 0x44, 0x58, 0x42, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -240,8 +285,8 @@ Parts: MinorVersion: 0 ShaderKind: 14 Size: 6 - DXILMajorVersion: 0 - DXILMinorVersion: 1 + DXILMajorVersion: 1 + DXILMinorVersion: 0 DXILSize: 0 ... )"; @@ -361,8 +406,8 @@ Parts: // MinorVersion: 0 // ShaderKind: 14 // Size: 6 -// DXILMajorVersion: 0 -// DXILMinorVersion: 1 +// DXILMajorVersion: 1 +// DXILMinorVersion: 0 // DXILSize: 0 // - Name: PSV0 // Size: 36 @@ -477,7 +522,7 @@ TEST(DXCFile, MaliciousFiles) { // // --- !dxcontainer // Header: -// Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, +// Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, // 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ] // Version: // Major: 1 @@ -491,8 +536,8 @@ TEST(DXCFile, MaliciousFiles) { // MinorVersion: 0 // ShaderKind: 14 // Size: 6 -// DXILMajorVersion: 0 -// DXILMinorVersion: 1 +// DXILMajorVersion: 1 +// DXILMinorVersion: 0 // DXILSize: 0 // - Name: PSV0 // Size: 100 -- GitLab From 4cf3f032283d8426c9b7829c7ccf0ab01939c7db Mon Sep 17 00:00:00 2001 From: Congcong Cai Date: Fri, 10 May 2024 21:51:07 +0800 Subject: [PATCH 262/328] [clang-tidy] use llvm::any_of refactor getAnalyzerCheckersAndPackages [NFC] (#91713) --- clang-tools-extra/clang-tidy/ClangTidy.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/clang-tools-extra/clang-tidy/ClangTidy.cpp b/clang-tools-extra/clang-tidy/ClangTidy.cpp index b877ea06dc05..1cd7cdd10bc2 100644 --- a/clang-tools-extra/clang-tidy/ClangTidy.cpp +++ b/clang-tools-extra/clang-tidy/ClangTidy.cpp @@ -373,11 +373,11 @@ static CheckersList getAnalyzerCheckersAndPackages(ClangTidyContext &Context, const auto &RegisteredCheckers = AnalyzerOptions::getRegisteredCheckers(IncludeExperimental); - bool AnalyzerChecksEnabled = false; - for (StringRef CheckName : RegisteredCheckers) { - std::string ClangTidyCheckName((AnalyzerCheckNamePrefix + CheckName).str()); - AnalyzerChecksEnabled |= Context.isCheckEnabled(ClangTidyCheckName); - } + const bool AnalyzerChecksEnabled = + llvm::any_of(RegisteredCheckers, [&](StringRef CheckName) -> bool { + return Context.isCheckEnabled( + (AnalyzerCheckNamePrefix + CheckName).str()); + }); if (!AnalyzerChecksEnabled) return List; -- GitLab From 8fc9e3d577c02d2b97c952fbafb75db0100462a9 Mon Sep 17 00:00:00 2001 From: David Green Date: Fri, 10 May 2024 14:58:48 +0100 Subject: [PATCH 263/328] [DAG] Lower frem of power-2 using div/trunc/mul+sub (#91148) If we are lowering a frem and the divisor is known to be an integer power-2, we can use the formula 'frem = x - trunc(x / d) * d'. This avoids the more expensive call to fmod. The results are identical as fmod so long as d is a power-2 (so the mul does not round incorrectly), and the sign of the return is either always positive or not important for zeroes (nsz). Unfortunately Alive2 does not handle this well at the moment. I was using exhaustive checking to test this: (https://gist.github.com/davemgreen/6078015f30d3bacd1e9572f8db5d4b64). I found this in cpythons implementation of float_pow. I currently added it as a DAG combine for frem with power-2 fp constants. --- llvm/include/llvm/CodeGen/SelectionDAG.h | 8 + llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 20 +- .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 17 + llvm/test/CodeGen/AArch64/frem-power2.ll | 373 ++++++++++-------- llvm/test/CodeGen/ARM/frem-power2.ll | 18 +- 5 files changed, 273 insertions(+), 163 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index 4b1b58d4af0b..c08e57ba3f67 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -1996,6 +1996,10 @@ public: /// is set. bool isKnownToBeAPowerOfTwo(SDValue Val, unsigned Depth = 0) const; + /// Test if the given _fp_ value is known to be an integer power-of-2, either + /// positive or negative. + bool isKnownToBeAPowerOfTwoFP(SDValue Val, unsigned Depth = 0) const; + /// Return the number of times the sign bit of the register is replicated into /// the other bits. We know that at least 1 bit is always equal to the sign /// bit (itself), but other cases can give us information. For example, @@ -2111,6 +2115,10 @@ public: /// Test whether the given SDValue is known to contain non-zero value(s). bool isKnownNeverZero(SDValue Op, unsigned Depth = 0) const; + /// Test whether the given float value is known to be positive. +0.0, +inf and + /// +nan are considered positive, -0.0, -inf and -nan are not. + bool cannotBeOrderedNegativeFP(SDValue Op) const; + /// Test whether two SDValues are known to compare equal. This /// is true if they are the same value, or if one is negative zero and the /// other positive zero. diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index fddc97d8901a..be919b7a8922 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -17365,17 +17365,35 @@ SDValue DAGCombiner::visitFREM(SDNode *N) { EVT VT = N->getValueType(0); SDNodeFlags Flags = N->getFlags(); SelectionDAG::FlagInserter FlagsInserter(DAG, N); + SDLoc DL(N); if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) return R; // fold (frem c1, c2) -> fmod(c1,c2) - if (SDValue C = DAG.FoldConstantArithmetic(ISD::FREM, SDLoc(N), VT, {N0, N1})) + if (SDValue C = DAG.FoldConstantArithmetic(ISD::FREM, DL, VT, {N0, N1})) return C; if (SDValue NewSel = foldBinOpIntoSelect(N)) return NewSel; + // Lower frem N0, N1 => x - trunc(N0 / N1) * N1, providing N1 is an integer + // power of 2. + if (!TLI.isOperationLegal(ISD::FREM, VT) && + TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && + TLI.isOperationLegalOrCustom(ISD::FDIV, VT) && + TLI.isOperationLegalOrCustom(ISD::FTRUNC, VT) && + DAG.isKnownToBeAPowerOfTwoFP(N1) && + (Flags.hasNoSignedZeros() || DAG.cannotBeOrderedNegativeFP(N0))) { + SDValue Div = DAG.getNode(ISD::FDIV, DL, VT, N0, N1); + SDValue Rnd = DAG.getNode(ISD::FTRUNC, DL, VT, Div); + if (TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT)) + return DAG.getNode(ISD::FMA, DL, VT, DAG.getNode(ISD::FNEG, DL, VT, Rnd), + N1, N0); + SDValue Mul = DAG.getNode(ISD::FMUL, DL, VT, Rnd, N1); + return DAG.getNode(ISD::FSUB, DL, VT, N0, Mul); + } + return SDValue(); } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index eef5acd03234..9c1f3c1e3431 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -4373,6 +4373,16 @@ bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val, unsigned Depth) const { return false; } +bool SelectionDAG::isKnownToBeAPowerOfTwoFP(SDValue Val, unsigned Depth) const { + if (ConstantFPSDNode *C1 = isConstOrConstSplatFP(Val, true)) + return C1->getValueAPF().getExactLog2Abs() >= 0; + + if (Val.getOpcode() == ISD::UINT_TO_FP || Val.getOpcode() == ISD::SINT_TO_FP) + return isKnownToBeAPowerOfTwo(Val.getOperand(0), Depth + 1); + + return false; +} + unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const { EVT VT = Op.getValueType(); @@ -5555,6 +5565,13 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const { return computeKnownBits(Op, Depth).isNonZero(); } +bool SelectionDAG::cannotBeOrderedNegativeFP(SDValue Op) const { + if (ConstantFPSDNode *C1 = isConstOrConstSplatFP(Op, true)) + return !C1->isNegative(); + + return Op.getOpcode() == ISD::FABS; +} + bool SelectionDAG::isEqualTo(SDValue A, SDValue B) const { // Check the obvious case. if (A == B) return true; diff --git a/llvm/test/CodeGen/AArch64/frem-power2.ll b/llvm/test/CodeGen/AArch64/frem-power2.ll index 5d627fcd6b65..402e03c5e265 100644 --- a/llvm/test/CodeGen/AArch64/frem-power2.ll +++ b/llvm/test/CodeGen/AArch64/frem-power2.ll @@ -13,31 +13,57 @@ entry: } define float @frem2_nsz(float %x) { -; CHECK-LABEL: frem2_nsz: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov s1, #2.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem2_nsz: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fmov s1, #2.00000000 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem2_nsz: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov s1, #2.00000000 +; CHECK-GI-NEXT: b fmodf entry: %fmod = frem nsz float %x, 2.0 ret float %fmod } define float @frem2_fast(float %x) { -; CHECK-LABEL: frem2_fast: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov s1, #2.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem2_fast: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fmov s1, #0.50000000 +; CHECK-SD-NEXT: fmov s2, #-2.00000000 +; CHECK-SD-NEXT: fmul s1, s0, s1 +; CHECK-SD-NEXT: frintz s1, s1 +; CHECK-SD-NEXT: fmadd s0, s1, s2, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem2_fast: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov s1, #2.00000000 +; CHECK-GI-NEXT: b fmodf entry: %fmod = frem fast float %x, 2.0 ret float %fmod } define float @frem2_abs(float %x) { -; CHECK-LABEL: frem2_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: fmov s1, #2.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem2_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: fmov s1, #2.00000000 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem2_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: fmov s1, #2.00000000 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 2.0 @@ -47,14 +73,11 @@ entry: define half @hrem2_nsz(half %x) { ; CHECK-SD-LABEL: hrem2_nsz: ; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 -; CHECK-SD-NEXT: .cfi_offset w30, -16 -; CHECK-SD-NEXT: fcvt s0, h0 -; CHECK-SD-NEXT: fmov s1, #2.00000000 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: fcvt h0, s0 -; CHECK-SD-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-SD-NEXT: fmov h1, #2.00000000 +; CHECK-SD-NEXT: fmov h2, #-2.00000000 +; CHECK-SD-NEXT: fdiv h1, h0, h1 +; CHECK-SD-NEXT: frintz h1, h1 +; CHECK-SD-NEXT: fmadd h0, h1, h2, h0 ; CHECK-SD-NEXT: ret ; ; CHECK-GI-LABEL: hrem2_nsz: @@ -75,10 +98,18 @@ entry: } define double @drem2_nsz(double %x) { -; CHECK-LABEL: drem2_nsz: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov d1, #2.00000000 -; CHECK-NEXT: b fmod +; CHECK-SD-LABEL: drem2_nsz: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fmov d1, #2.00000000 +; CHECK-SD-NEXT: fdiv d2, d0, d1 +; CHECK-SD-NEXT: frintz d2, d2 +; CHECK-SD-NEXT: fmsub d0, d2, d1, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: drem2_nsz: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov d1, #2.00000000 +; CHECK-GI-NEXT: b fmod entry: %fmod = frem nsz double %x, 2.0 ret double %fmod @@ -105,10 +136,16 @@ entry: } define float @frem1_nsz(float %x) { -; CHECK-LABEL: frem1_nsz: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov s1, #1.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem1_nsz: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: frintz s1, s0 +; CHECK-SD-NEXT: fsub s0, s0, s1 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem1_nsz: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov s1, #1.00000000 +; CHECK-GI-NEXT: b fmodf entry: %fmod = frem nsz float %x, 1.0 ret float %fmod @@ -125,21 +162,38 @@ entry: } define float @fremm2_nsz(float %x) { -; CHECK-LABEL: fremm2_nsz: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov s1, #-2.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: fremm2_nsz: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fmov s1, #-2.00000000 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: fremm2_nsz: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov s1, #-2.00000000 +; CHECK-GI-NEXT: b fmodf entry: %fmod = frem nsz float %x, -2.0 ret float %fmod } define float @frem4_abs(float %x) { -; CHECK-LABEL: frem4_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: fmov s1, #4.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem4_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: fmov s1, #4.00000000 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem4_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: fmov s1, #4.00000000 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 4.0 @@ -147,11 +201,20 @@ entry: } define float @frem16_abs(float %x) { -; CHECK-LABEL: frem16_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: fmov s1, #16.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem16_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: fmov s1, #16.00000000 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem16_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: fmov s1, #16.00000000 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 16.0 @@ -159,12 +222,22 @@ entry: } define float @frem4294967296_abs(float %x) { -; CHECK-LABEL: frem4294967296_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: mov w8, #1333788672 // =0x4f800000 -; CHECK-NEXT: fmov s1, w8 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem4294967296_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: mov w8, #1333788672 // =0x4f800000 +; CHECK-SD-NEXT: fmov s1, w8 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem4294967296_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000 +; CHECK-GI-NEXT: fmov s1, w8 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 4294967296.0 @@ -172,12 +245,22 @@ entry: } define float @frem1152921504606846976_abs(float %x) { -; CHECK-LABEL: frem1152921504606846976_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: mov w8, #1568669696 // =0x5d800000 -; CHECK-NEXT: fmov s1, w8 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem1152921504606846976_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: mov w8, #1568669696 // =0x5d800000 +; CHECK-SD-NEXT: fmov s1, w8 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem1152921504606846976_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: mov w8, #1568669696 // =0x5d800000 +; CHECK-GI-NEXT: fmov s1, w8 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 1152921504606846976.0 @@ -185,12 +268,22 @@ entry: } define float @frem4611686018427387904_abs(float %x) { -; CHECK-LABEL: frem4611686018427387904_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: mov w8, #1585446912 // =0x5e800000 -; CHECK-NEXT: fmov s1, w8 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem4611686018427387904_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: mov w8, #1585446912 // =0x5e800000 +; CHECK-SD-NEXT: fmov s1, w8 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem4611686018427387904_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: mov w8, #1585446912 // =0x5e800000 +; CHECK-GI-NEXT: fmov s1, w8 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 4611686018427387904.0 @@ -198,11 +291,20 @@ entry: } define float @frem9223372036854775808_abs(float %x) { -; CHECK-LABEL: frem9223372036854775808_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: movi v1.2s, #95, lsl #24 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem9223372036854775808_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: movi v1.2s, #95, lsl #24 +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem9223372036854775808_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: movi v1.2s, #95, lsl #24 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 9223372036854775808.0 @@ -212,42 +314,10 @@ entry: define <4 x float> @frem2_nsz_vec(<4 x float> %x) { ; CHECK-SD-LABEL: frem2_nsz_vec: ; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: sub sp, sp, #48 -; CHECK-SD-NEXT: str x30, [sp, #32] // 8-byte Folded Spill -; CHECK-SD-NEXT: .cfi_def_cfa_offset 48 -; CHECK-SD-NEXT: .cfi_offset w30, -16 -; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Folded Spill -; CHECK-SD-NEXT: mov s0, v0.s[1] -; CHECK-SD-NEXT: fmov s1, #2.00000000 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: fmov s1, #2.00000000 -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill -; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: mov v0.s[1], v1.s[0] -; CHECK-SD-NEXT: fmov s1, #2.00000000 -; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill -; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload -; CHECK-SD-NEXT: mov s0, v0.s[2] -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: mov v1.s[2], v0.s[0] -; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload -; CHECK-SD-NEXT: mov s0, v0.s[3] -; CHECK-SD-NEXT: str q1, [sp] // 16-byte Folded Spill -; CHECK-SD-NEXT: fmov s1, #2.00000000 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload -; CHECK-SD-NEXT: mov v1.s[3], v0.s[0] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: add sp, sp, #48 +; CHECK-SD-NEXT: movi v1.4s, #64, lsl #24 +; CHECK-SD-NEXT: fdiv v2.4s, v0.4s, v1.4s +; CHECK-SD-NEXT: frintz v2.4s, v2.4s +; CHECK-SD-NEXT: fmls v0.4s, v1.4s, v2.4s ; CHECK-SD-NEXT: ret ; ; CHECK-GI-LABEL: frem2_nsz_vec: @@ -302,48 +372,12 @@ entry: define <4 x float> @frem1152921504606846976_absv(<4 x float> %x) { ; CHECK-SD-LABEL: frem1152921504606846976_absv: ; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: sub sp, sp, #48 -; CHECK-SD-NEXT: str d8, [sp, #32] // 8-byte Folded Spill -; CHECK-SD-NEXT: str x30, [sp, #40] // 8-byte Folded Spill -; CHECK-SD-NEXT: .cfi_def_cfa_offset 48 -; CHECK-SD-NEXT: .cfi_offset w30, -8 -; CHECK-SD-NEXT: .cfi_offset b8, -16 -; CHECK-SD-NEXT: fabs v0.4s, v0.4s ; CHECK-SD-NEXT: mov w8, #1568669696 // =0x5d800000 -; CHECK-SD-NEXT: fmov s8, w8 -; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Folded Spill -; CHECK-SD-NEXT: mov s0, v0.s[1] -; CHECK-SD-NEXT: fmov s1, s8 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: fmov s1, s8 -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill -; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: mov v0.s[1], v1.s[0] -; CHECK-SD-NEXT: fmov s1, s8 -; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill -; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload -; CHECK-SD-NEXT: mov s0, v0.s[2] -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: mov v1.s[2], v0.s[0] -; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload -; CHECK-SD-NEXT: mov s0, v0.s[3] -; CHECK-SD-NEXT: str q1, [sp] // 16-byte Folded Spill -; CHECK-SD-NEXT: fmov s1, s8 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload -; CHECK-SD-NEXT: ldr d8, [sp, #32] // 8-byte Folded Reload -; CHECK-SD-NEXT: mov v1.s[3], v0.s[0] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: add sp, sp, #48 +; CHECK-SD-NEXT: fabs v0.4s, v0.4s +; CHECK-SD-NEXT: dup v1.4s, w8 +; CHECK-SD-NEXT: fdiv v2.4s, v0.4s, v1.4s +; CHECK-SD-NEXT: frintz v2.4s, v2.4s +; CHECK-SD-NEXT: fmls v0.4s, v1.4s, v2.4s ; CHECK-SD-NEXT: ret ; ; CHECK-GI-LABEL: frem1152921504606846976_absv: @@ -401,12 +435,22 @@ entry: } define float @frem2_nsz_sitofp(float %x, i32 %sa) { -; CHECK-LABEL: frem2_nsz_sitofp: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: mov w8, #1 // =0x1 -; CHECK-NEXT: lsl w8, w8, w0 -; CHECK-NEXT: scvtf s1, w8 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem2_nsz_sitofp: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: mov w8, #1 // =0x1 +; CHECK-SD-NEXT: lsl w8, w8, w0 +; CHECK-SD-NEXT: scvtf s1, w8 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem2_nsz_sitofp: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov w8, #1 // =0x1 +; CHECK-GI-NEXT: lsl w8, w8, w0 +; CHECK-GI-NEXT: scvtf s1, w8 +; CHECK-GI-NEXT: b fmodf entry: %s = shl i32 1, %sa %y = sitofp i32 %s to float @@ -415,12 +459,22 @@ entry: } define float @frem2_nsz_uitofp(float %x, i32 %sa) { -; CHECK-LABEL: frem2_nsz_uitofp: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: mov w8, #1 // =0x1 -; CHECK-NEXT: lsl w8, w8, w0 -; CHECK-NEXT: ucvtf s1, w8 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem2_nsz_uitofp: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: mov w8, #1 // =0x1 +; CHECK-SD-NEXT: lsl w8, w8, w0 +; CHECK-SD-NEXT: ucvtf s1, w8 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem2_nsz_uitofp: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov w8, #1 // =0x1 +; CHECK-GI-NEXT: lsl w8, w8, w0 +; CHECK-GI-NEXT: ucvtf s1, w8 +; CHECK-GI-NEXT: b fmodf entry: %s = shl i32 1, %sa %y = uitofp i32 %s to float @@ -432,10 +486,13 @@ define float @frem2_const_sitofp(float %x, i32 %sa) { ; CHECK-SD-LABEL: frem2_const_sitofp: ; CHECK-SD: // %bb.0: // %entry ; CHECK-SD-NEXT: mov w8, #1 // =0x1 -; CHECK-SD-NEXT: fmov s0, #12.50000000 +; CHECK-SD-NEXT: fmov s1, #12.50000000 ; CHECK-SD-NEXT: lsl w8, w8, w0 -; CHECK-SD-NEXT: scvtf s1, w8 -; CHECK-SD-NEXT: b fmodf +; CHECK-SD-NEXT: scvtf s0, w8 +; CHECK-SD-NEXT: fdiv s2, s1, s0 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s0, s1 +; CHECK-SD-NEXT: ret ; ; CHECK-GI-LABEL: frem2_const_sitofp: ; CHECK-GI: // %bb.0: // %entry diff --git a/llvm/test/CodeGen/ARM/frem-power2.ll b/llvm/test/CodeGen/ARM/frem-power2.ll index 8052c8c35bcf..7f52943175ac 100644 --- a/llvm/test/CodeGen/ARM/frem-power2.ll +++ b/llvm/test/CodeGen/ARM/frem-power2.ll @@ -37,13 +37,23 @@ define float @frem4_nsz(float %x) { ; ; CHECK-FP-LABEL: frem4_nsz: ; CHECK-FP: @ %bb.0: @ %entry -; CHECK-FP-NEXT: mov.w r1, #1082130432 -; CHECK-FP-NEXT: b fmodf +; CHECK-FP-NEXT: vmov.f32 s0, #4.000000e+00 +; CHECK-FP-NEXT: vmov s2, r0 +; CHECK-FP-NEXT: vdiv.f32 s4, s2, s0 +; CHECK-FP-NEXT: vrintz.f32 s4, s4 +; CHECK-FP-NEXT: vfms.f32 s2, s4, s0 +; CHECK-FP-NEXT: vmov r0, s2 +; CHECK-FP-NEXT: bx lr ; ; CHECK-M33-LABEL: frem4_nsz: ; CHECK-M33: @ %bb.0: @ %entry -; CHECK-M33-NEXT: mov.w r1, #1082130432 -; CHECK-M33-NEXT: b fmodf +; CHECK-M33-NEXT: vmov.f32 s0, #4.000000e+00 +; CHECK-M33-NEXT: vmov s2, r0 +; CHECK-M33-NEXT: vdiv.f32 s4, s2, s0 +; CHECK-M33-NEXT: vrintz.f32 s4, s4 +; CHECK-M33-NEXT: vmls.f32 s2, s4, s0 +; CHECK-M33-NEXT: vmov r0, s2 +; CHECK-M33-NEXT: bx lr entry: %fmod = frem nsz float %x, 4.0 ret float %fmod -- GitLab From 63177422a834f4b81d59b827b5f2a1c5a9083749 Mon Sep 17 00:00:00 2001 From: erichkeane Date: Fri, 10 May 2024 07:02:10 -0700 Subject: [PATCH 264/328] [OpenACC][NFC] Fix isa behavior for OpenACC types I discovered while working on a different patch that I'd not implemented the 'classof' for any of the Clauses, which resulted in 'isa' always returning 'true' for all of the types. This patch goes through all the existing clauses and adds 'classof' such that it will work correctly. Additionally, in doing this, I found a bug where I was doing a cast to the wrong type in the ASTWriter, so this fixes that problem as well. --- clang/include/clang/AST/OpenACCClause.h | 71 ++++++++++++++++++++++++- clang/include/clang/AST/StmtOpenACC.h | 4 ++ clang/lib/AST/OpenACCClause.cpp | 27 ++++++++++ clang/lib/Serialization/ASTWriter.cpp | 2 +- 4 files changed, 102 insertions(+), 2 deletions(-) diff --git a/clang/include/clang/AST/OpenACCClause.h b/clang/include/clang/AST/OpenACCClause.h index d8332816a499..3d0b1ab9d31e 100644 --- a/clang/include/clang/AST/OpenACCClause.h +++ b/clang/include/clang/AST/OpenACCClause.h @@ -36,7 +36,7 @@ public: SourceLocation getBeginLoc() const { return Location.getBegin(); } SourceLocation getEndLoc() const { return Location.getEnd(); } - static bool classof(const OpenACCClause *) { return true; } + static bool classof(const OpenACCClause *) { return false; } using child_iterator = StmtIterator; using const_child_iterator = ConstStmtIterator; @@ -63,6 +63,8 @@ protected: : OpenACCClause(K, BeginLoc, EndLoc), LParenLoc(LParenLoc) {} public: + static bool classof(const OpenACCClause *C); + SourceLocation getLParenLoc() const { return LParenLoc; } child_range children() { @@ -92,6 +94,9 @@ protected: } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Default; + } OpenACCDefaultClauseKind getDefaultClauseKind() const { return DefaultClauseKind; } @@ -116,6 +121,8 @@ protected: ConditionExpr(ConditionExpr) {} public: + static bool classof(const OpenACCClause *C); + bool hasConditionExpr() const { return ConditionExpr; } const Expr *getConditionExpr() const { return ConditionExpr; } Expr *getConditionExpr() { return ConditionExpr; } @@ -143,6 +150,9 @@ protected: Expr *ConditionExpr, SourceLocation EndLoc); public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::If; + } static OpenACCIfClause *Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, Expr *ConditionExpr, SourceLocation EndLoc); @@ -154,6 +164,9 @@ class OpenACCSelfClause : public OpenACCClauseWithCondition { Expr *ConditionExpr, SourceLocation EndLoc); public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Self; + } static OpenACCSelfClause *Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, Expr *ConditionExpr, SourceLocation EndLoc); @@ -180,6 +193,7 @@ protected: llvm::ArrayRef getExprs() const { return Exprs; } public: + static bool classof(const OpenACCClause *C); child_range children() { return child_range(reinterpret_cast(Exprs.begin()), reinterpret_cast(Exprs.end())); @@ -214,6 +228,9 @@ class OpenACCWaitClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Wait; + } static OpenACCWaitClause *Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, Expr *DevNumExpr, SourceLocation QueuesLoc, @@ -246,6 +263,9 @@ class OpenACCNumGangsClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::NumGangs; + } static OpenACCNumGangsClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef IntExprs, SourceLocation EndLoc); @@ -275,6 +295,7 @@ protected: } public: + static bool classof(const OpenACCClause *C); bool hasIntExpr() const { return !getExprs().empty(); } const Expr *getIntExpr() const { return hasIntExpr() ? getExprs()[0] : nullptr; @@ -288,6 +309,9 @@ class OpenACCNumWorkersClause : public OpenACCClauseWithSingleIntExpr { Expr *IntExpr, SourceLocation EndLoc); public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::NumWorkers; + } static OpenACCNumWorkersClause *Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, @@ -299,6 +323,9 @@ class OpenACCVectorLengthClause : public OpenACCClauseWithSingleIntExpr { Expr *IntExpr, SourceLocation EndLoc); public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::VectorLength; + } static OpenACCVectorLengthClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, Expr *IntExpr, SourceLocation EndLoc); @@ -309,6 +336,9 @@ class OpenACCAsyncClause : public OpenACCClauseWithSingleIntExpr { Expr *IntExpr, SourceLocation EndLoc); public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Async; + } static OpenACCAsyncClause *Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, Expr *IntExpr, @@ -326,6 +356,7 @@ protected: : OpenACCClauseWithExprs(K, BeginLoc, LParenLoc, EndLoc) {} public: + static bool classof(const OpenACCClause *C); ArrayRef getVarList() { return getExprs(); } ArrayRef getVarList() const { return getExprs(); } }; @@ -344,6 +375,9 @@ class OpenACCPrivateClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Private; + } static OpenACCPrivateClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef VarList, SourceLocation EndLoc); @@ -363,6 +397,9 @@ class OpenACCFirstPrivateClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::FirstPrivate; + } static OpenACCFirstPrivateClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef VarList, SourceLocation EndLoc); @@ -382,6 +419,9 @@ class OpenACCDevicePtrClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::DevicePtr; + } static OpenACCDevicePtrClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef VarList, SourceLocation EndLoc); @@ -401,6 +441,9 @@ class OpenACCAttachClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Attach; + } static OpenACCAttachClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef VarList, SourceLocation EndLoc); @@ -420,6 +463,9 @@ class OpenACCNoCreateClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::NoCreate; + } static OpenACCNoCreateClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef VarList, SourceLocation EndLoc); @@ -439,6 +485,9 @@ class OpenACCPresentClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Present; + } static OpenACCPresentClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef VarList, SourceLocation EndLoc); @@ -462,6 +511,11 @@ class OpenACCCopyClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Copy || + C->getClauseKind() == OpenACCClauseKind::PCopy || + C->getClauseKind() == OpenACCClauseKind::PresentOrCopy; + } static OpenACCCopyClause * Create(const ASTContext &C, OpenACCClauseKind Spelling, SourceLocation BeginLoc, SourceLocation LParenLoc, @@ -488,6 +542,11 @@ class OpenACCCopyInClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::CopyIn || + C->getClauseKind() == OpenACCClauseKind::PCopyIn || + C->getClauseKind() == OpenACCClauseKind::PresentOrCopyIn; + } bool isReadOnly() const { return IsReadOnly; } static OpenACCCopyInClause * Create(const ASTContext &C, OpenACCClauseKind Spelling, @@ -515,6 +574,11 @@ class OpenACCCopyOutClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::CopyOut || + C->getClauseKind() == OpenACCClauseKind::PCopyOut || + C->getClauseKind() == OpenACCClauseKind::PresentOrCopyOut; + } bool isZero() const { return IsZero; } static OpenACCCopyOutClause * Create(const ASTContext &C, OpenACCClauseKind Spelling, @@ -542,6 +606,11 @@ class OpenACCCreateClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Create || + C->getClauseKind() == OpenACCClauseKind::PCreate || + C->getClauseKind() == OpenACCClauseKind::PresentOrCreate; + } bool isZero() const { return IsZero; } static OpenACCCreateClause * Create(const ASTContext &C, OpenACCClauseKind Spelling, diff --git a/clang/include/clang/AST/StmtOpenACC.h b/clang/include/clang/AST/StmtOpenACC.h index 66f8f844e0b2..b706864798ba 100644 --- a/clang/include/clang/AST/StmtOpenACC.h +++ b/clang/include/clang/AST/StmtOpenACC.h @@ -93,6 +93,10 @@ protected: } public: + static bool classof(const Stmt *T) { + return false; + } + child_range children() { if (getAssociatedStmt()) return child_range(&AssociatedStmt, &AssociatedStmt + 1); diff --git a/clang/lib/AST/OpenACCClause.cpp b/clang/lib/AST/OpenACCClause.cpp index be079556a87a..ee13437b97b4 100644 --- a/clang/lib/AST/OpenACCClause.cpp +++ b/clang/lib/AST/OpenACCClause.cpp @@ -17,6 +17,33 @@ using namespace clang; +bool OpenACCClauseWithParams::classof(const OpenACCClause *C) { + return OpenACCClauseWithCondition::classof(C) || + OpenACCClauseWithExprs::classof(C); +} +bool OpenACCClauseWithExprs::classof(const OpenACCClause *C) { + return OpenACCWaitClause::classof(C) || OpenACCNumGangsClause::classof(C) || + OpenACCClauseWithSingleIntExpr::classof(C) || + OpenACCClauseWithVarList::classof(C); +} +bool OpenACCClauseWithVarList::classof(const OpenACCClause *C) { + return OpenACCPrivateClause::classof(C) || + OpenACCFirstPrivateClause::classof(C) || + OpenACCDevicePtrClause::classof(C) || + OpenACCDevicePtrClause::classof(C) || + OpenACCAttachClause::classof(C) || OpenACCNoCreateClause::classof(C) || + OpenACCPresentClause::classof(C) || OpenACCCopyClause::classof(C) || + OpenACCCopyInClause::classof(C) || OpenACCCopyOutClause::classof(C) || + OpenACCCreateClause::classof(C); +} +bool OpenACCClauseWithCondition::classof(const OpenACCClause *C) { + return OpenACCIfClause::classof(C) || OpenACCSelfClause::classof(C); +} +bool OpenACCClauseWithSingleIntExpr::classof(const OpenACCClause *C) { + return OpenACCNumWorkersClause::classof(C) || + OpenACCVectorLengthClause::classof(C) || + OpenACCAsyncClause::classof(C); +} OpenACCDefaultClause *OpenACCDefaultClause::Create(const ASTContext &C, OpenACCDefaultClauseKind K, SourceLocation BeginLoc, diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index e7b9050165bb..ab07cf3efa45 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -7816,7 +7816,7 @@ void ASTRecordWriter::writeOpenACCClause(const OpenACCClause *C) { return; } case OpenACCClauseKind::Self: { - const auto *SC = cast(C); + const auto *SC = cast(C); writeSourceLocation(SC->getLParenLoc()); writeBool(SC->hasConditionExpr()); if (SC->hasConditionExpr()) -- GitLab From 331f22af4b4c849a97c97e6803e0c8cab57fa10b Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Fri, 10 May 2024 15:04:38 +0100 Subject: [PATCH 265/328] [AMDGPU] Remove unnecessary predicates from aliases. NFC. (#91602) So long as the target of the alias is predicated with HasImageInsts or similar, the alias itself does not need this predicate. --- llvm/lib/Target/AMDGPU/EXPInstructions.td | 1 - llvm/lib/Target/AMDGPU/MIMGInstructions.td | 1 - 2 files changed, 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/EXPInstructions.td b/llvm/lib/Target/AMDGPU/EXPInstructions.td index e02652e62a57..5e426b5acd50 100644 --- a/llvm/lib/Target/AMDGPU/EXPInstructions.td +++ b/llvm/lib/Target/AMDGPU/EXPInstructions.td @@ -125,7 +125,6 @@ multiclass VEXPORT_Real_gfx12 { } def : AMDGPUMnemonicAlias<"exp", "export"> { let AssemblerPredicate = isGFX12Plus; - let OtherPredicates = [HasExportInsts]; } } diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td index 9f6277f1257f..351263d07976 100644 --- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td +++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td @@ -1079,7 +1079,6 @@ multiclass MIMG_Atomic_Addr_Helper_m { let AssemblerPredicate = isGFX12Plus; - let OtherPredicates = [HasImageInsts]; bit IsAtomicRet; // Unused MIMGBaseOpcode BaseOpcode; // Unused int VDataDwords; // Unused -- GitLab From 52271a5c11f6abde1fa1221db304212b5eb8ec7c Mon Sep 17 00:00:00 2001 From: Hui Date: Fri, 10 May 2024 15:13:00 +0100 Subject: [PATCH 266/328] [libc++] Make `constexpr std::variant`. Implement P2231R1 (#83335) Fixes #86686 --- libcxx/docs/ReleaseNotes/19.rst | 1 + libcxx/docs/Status/Cxx20.rst | 1 - libcxx/docs/Status/Cxx20Papers.csv | 2 +- libcxx/include/variant | 212 ++++---- .../variant.variant/variant.assign/T.pass.cpp | 202 ++++++- .../variant.assign/copy.pass.cpp | 430 +++++++++------ .../variant.assign/move.pass.cpp | 316 ++++++----- .../variant.ctor/copy.pass.cpp | 106 ++-- .../variant.ctor/default.pass.cpp | 26 +- .../variant.ctor/move.pass.cpp | 113 ++-- .../variant.dtor/dtor.pass.cpp | 71 ++- .../variant.mod/emplace_index_args.pass.cpp | 44 +- .../emplace_index_init_list_args.pass.cpp | 35 +- .../variant.mod/emplace_type_args.pass.cpp | 51 +- .../emplace_type_init_list_args.pass.cpp | 44 +- .../variant.swap/swap.pass.cpp | 504 +++++++++--------- 16 files changed, 1322 insertions(+), 836 deletions(-) diff --git a/libcxx/docs/ReleaseNotes/19.rst b/libcxx/docs/ReleaseNotes/19.rst index 3fc007f45985..83fcd40bb80c 100644 --- a/libcxx/docs/ReleaseNotes/19.rst +++ b/libcxx/docs/ReleaseNotes/19.rst @@ -52,6 +52,7 @@ Implemented Papers - P3029R1 - Better ``mdspan``'s CTAD - P2387R3 - Pipe support for user-defined range adaptors - P2713R1 - Escaping improvements in ``std::format`` +- P2231R1 - Missing ``constexpr`` in ``std::optional`` and ``std::variant`` Improvements and New Features ----------------------------- diff --git a/libcxx/docs/Status/Cxx20.rst b/libcxx/docs/Status/Cxx20.rst index 23289dc6e596..b08b99394fbb 100644 --- a/libcxx/docs/Status/Cxx20.rst +++ b/libcxx/docs/Status/Cxx20.rst @@ -47,7 +47,6 @@ Paper Status .. [#note-P0619] P0619: Only sections D.8, D.9, D.10 and D.13 are implemented. Sections D.4, D.7, D.11, and D.12 remain undone. .. [#note-P0883.1] P0883: shared_ptr and floating-point changes weren't applied as they themselves aren't implemented yet. .. [#note-P0883.2] P0883: ``ATOMIC_FLAG_INIT`` was marked deprecated in version 14.0, but was undeprecated with the implementation of LWG3659 in version 15.0. - .. [#note-P2231] P2231: Optional is complete. The changes to variant haven't been implemented yet. .. [#note-P0660] P0660: The paper is implemented but the features are experimental and can be enabled via ``-fexperimental-library``. .. [#note-P0355] P0355: The implementation status is: diff --git a/libcxx/docs/Status/Cxx20Papers.csv b/libcxx/docs/Status/Cxx20Papers.csv index d31720b7576d..955aa5f614af 100644 --- a/libcxx/docs/Status/Cxx20Papers.csv +++ b/libcxx/docs/Status/Cxx20Papers.csv @@ -192,7 +192,7 @@ "`P2106R0 `__","LWG","Alternative wording for GB315 and GB316","Prague","|Complete|","15.0","|ranges|" "`P2116R0 `__","LWG","Remove tuple-like protocol support from fixed-extent span","Prague","|Complete|","11.0" "","","","","","","" -"`P2231R1 `__","LWG","Missing constexpr in std::optional and std::variant","June 2021","|Partial| [#note-P2231]_","13.0" +"`P2231R1 `__","LWG","Missing constexpr in std::optional and std::variant","June 2021","|Complete|","19.0" "`P2325R3 `__","LWG","Views should not be required to be default constructible","June 2021","|Complete|","16.0","|ranges|" "`P2210R2 `__","LWG","Superior String Splitting","June 2021","|Complete|","16.0","|ranges|" "`P2216R3 `__","LWG","std::format improvements","June 2021","|Complete|","15.0" diff --git a/libcxx/include/variant b/libcxx/include/variant index 34150bd45284..631ffceab5f6 100644 --- a/libcxx/include/variant +++ b/libcxx/include/variant @@ -42,26 +42,28 @@ namespace std { in_place_index_t, initializer_list, Args&&...); // 20.7.2.2, destructor - ~variant(); + constexpr ~variant(); // constexpr since c++20 // 20.7.2.3, assignment constexpr variant& operator=(const variant&); constexpr variant& operator=(variant&&) noexcept(see below); - template variant& operator=(T&&) noexcept(see below); + template + constexpr variant& operator=(T&&) noexcept(see below); // constexpr since c++20 // 20.7.2.4, modifiers template - T& emplace(Args&&...); + constexpr T& emplace(Args&&...); // constexpr since c++20 template - T& emplace(initializer_list, Args&&...); + constexpr T& emplace(initializer_list, Args&&...); // constexpr since c++20 template - variant_alternative_t& emplace(Args&&...); + constexpr variant_alternative_t& emplace(Args&&...); // constexpr since c++20 template - variant_alternative_t& emplace(initializer_list, Args&&...); + constexpr variant_alternative_t& + emplace(initializer_list, Args&&...); // constexpr since c++20 // 20.7.2.5, value status constexpr bool valueless_by_exception() const noexcept; @@ -221,6 +223,7 @@ namespace std { #include <__functional/operations.h> #include <__functional/unary_function.h> #include <__memory/addressof.h> +#include <__memory/construct_at.h> #include <__tuple/find_index.h> #include <__tuple/sfinae_helpers.h> #include <__type_traits/add_const.h> @@ -663,7 +666,8 @@ private: template struct _LIBCPP_TEMPLATE_VIS __alt { - using __value_type = _Tp; + using __value_type = _Tp; + static constexpr size_t __index = _Index; template _LIBCPP_HIDE_FROM_ABI explicit constexpr __alt(in_place_t, _Args&&... __args) @@ -678,7 +682,7 @@ union _LIBCPP_TEMPLATE_VIS __union; template <_Trait _DestructibleTrait, size_t _Index> union _LIBCPP_TEMPLATE_VIS __union<_DestructibleTrait, _Index> {}; -# define _LIBCPP_VARIANT_UNION(destructible_trait, destructor) \ +# define _LIBCPP_VARIANT_UNION(destructible_trait, destructor_definition) \ template \ union _LIBCPP_TEMPLATE_VIS __union { \ public: \ @@ -692,13 +696,11 @@ union _LIBCPP_TEMPLATE_VIS __union<_DestructibleTrait, _Index> {}; _LIBCPP_HIDE_FROM_ABI explicit constexpr __union(in_place_index_t<_Ip>, _Args&&... __args) \ : __tail(in_place_index<_Ip - 1>, std::forward<_Args>(__args)...) {} \ \ - __union(const __union&) = default; \ - __union(__union&&) = default; \ - \ - destructor; \ - \ - __union& operator=(const __union&) = default; \ - __union& operator=(__union&&) = default; \ + _LIBCPP_HIDE_FROM_ABI __union(const __union&) = default; \ + _LIBCPP_HIDE_FROM_ABI __union(__union&&) = default; \ + _LIBCPP_HIDE_FROM_ABI __union& operator=(const __union&) = default; \ + _LIBCPP_HIDE_FROM_ABI __union& operator=(__union&&) = default; \ + destructor_definition; \ \ private: \ char __dummy; \ @@ -708,10 +710,11 @@ union _LIBCPP_TEMPLATE_VIS __union<_DestructibleTrait, _Index> {}; friend struct __access::__union; \ } -_LIBCPP_VARIANT_UNION(_Trait::_TriviallyAvailable, ~__union() = default); +_LIBCPP_VARIANT_UNION(_Trait::_TriviallyAvailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~__union() = default); _LIBCPP_VARIANT_UNION( - _Trait::_Available, _LIBCPP_HIDE_FROM_ABI ~__union() {} _LIBCPP_EAT_SEMICOLON); -_LIBCPP_VARIANT_UNION(_Trait::_Unavailable, ~__union() = delete); + _Trait::_Available, _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~__union() {} _LIBCPP_EAT_SEMICOLON); +_LIBCPP_VARIANT_UNION(_Trait::_Unavailable, _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~__union() = delete); # undef _LIBCPP_VARIANT_UNION @@ -754,7 +757,7 @@ protected: template class _LIBCPP_TEMPLATE_VIS __dtor; -# define _LIBCPP_VARIANT_DESTRUCTOR(destructible_trait, destructor, destroy) \ +# define _LIBCPP_VARIANT_DESTRUCTOR(destructible_trait, destructor_definition, destroy) \ template \ class _LIBCPP_TEMPLATE_VIS __dtor<__traits<_Types...>, destructible_trait> \ : public __base { \ @@ -764,28 +767,27 @@ class _LIBCPP_TEMPLATE_VIS __dtor; public: \ using __base_type::__base_type; \ using __base_type::operator=; \ - \ - __dtor(const __dtor&) = default; \ - __dtor(__dtor&&) = default; \ - __dtor& operator=(const __dtor&) = default; \ - __dtor& operator=(__dtor&&) = default; \ - destructor; \ + _LIBCPP_HIDE_FROM_ABI __dtor(const __dtor&) = default; \ + _LIBCPP_HIDE_FROM_ABI __dtor(__dtor&&) = default; \ + _LIBCPP_HIDE_FROM_ABI __dtor& operator=(const __dtor&) = default; \ + _LIBCPP_HIDE_FROM_ABI __dtor& operator=(__dtor&&) = default; \ + destructor_definition; \ \ protected: \ - inline _LIBCPP_HIDE_FROM_ABI destroy; \ + destroy; \ } _LIBCPP_VARIANT_DESTRUCTOR( _Trait::_TriviallyAvailable, - ~__dtor() = default, // - _LIBCPP_HIDE_FROM_ABI void __destroy() noexcept { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~__dtor() = default, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __destroy() noexcept { this->__index = __variant_npos<__index_t>; } _LIBCPP_EAT_SEMICOLON); _LIBCPP_VARIANT_DESTRUCTOR( _Trait::_Available, - _LIBCPP_HIDE_FROM_ABI ~__dtor() { __destroy(); } _LIBCPP_EAT_SEMICOLON, - _LIBCPP_HIDE_FROM_ABI void __destroy() noexcept { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~__dtor() { __destroy(); } _LIBCPP_EAT_SEMICOLON, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __destroy() noexcept { if (!this->valueless_by_exception()) { __visitation::__base::__visit_alt( [](auto& __alt) noexcept { @@ -797,7 +799,9 @@ _LIBCPP_VARIANT_DESTRUCTOR( this->__index = __variant_npos<__index_t>; } _LIBCPP_EAT_SEMICOLON); -_LIBCPP_VARIANT_DESTRUCTOR(_Trait::_Unavailable, ~__dtor() = delete, void __destroy() noexcept = delete); +_LIBCPP_VARIANT_DESTRUCTOR(_Trait::_Unavailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~__dtor() = delete, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __destroy() noexcept = delete); # undef _LIBCPP_VARIANT_DESTRUCTOR @@ -810,23 +814,18 @@ public: using __base_type::operator=; protected: - template - _LIBCPP_HIDE_FROM_ABI static _Tp& __construct_alt(__alt<_Ip, _Tp>& __a, _Args&&... __args) { - ::new ((void*)std::addressof(__a)) __alt<_Ip, _Tp>(in_place, std::forward<_Args>(__args)...); - return __a.__value; - } - template - _LIBCPP_HIDE_FROM_ABI static void __generic_construct(__ctor& __lhs, _Rhs&& __rhs) { + _LIBCPP_HIDE_FROM_ABI static _LIBCPP_CONSTEXPR_SINCE_CXX20 void __generic_construct(__ctor& __lhs, _Rhs&& __rhs) { __lhs.__destroy(); if (!__rhs.valueless_by_exception()) { auto __rhs_index = __rhs.index(); __visitation::__base::__visit_alt_at( __rhs_index, - [](auto& __lhs_alt, auto&& __rhs_alt) { - __construct_alt(__lhs_alt, std::forward(__rhs_alt).__value); + [&__lhs](auto&& __rhs_alt) { + std::__construct_at(std::addressof(__lhs.__data), + in_place_index<__decay_t::__index>, + std::forward(__rhs_alt).__value); }, - __lhs, std::forward<_Rhs>(__rhs)); __lhs.__index = __rhs_index; } @@ -836,7 +835,7 @@ protected: template class _LIBCPP_TEMPLATE_VIS __move_constructor; -# define _LIBCPP_VARIANT_MOVE_CONSTRUCTOR(move_constructible_trait, move_constructor) \ +# define _LIBCPP_VARIANT_MOVE_CONSTRUCTOR(move_constructible_trait, move_constructor_definition) \ template \ class _LIBCPP_TEMPLATE_VIS __move_constructor<__traits<_Types...>, move_constructible_trait> \ : public __ctor<__traits<_Types...>> { \ @@ -846,32 +845,35 @@ class _LIBCPP_TEMPLATE_VIS __move_constructor; using __base_type::__base_type; \ using __base_type::operator=; \ \ - __move_constructor(const __move_constructor&) = default; \ - ~__move_constructor() = default; \ - __move_constructor& operator=(const __move_constructor&) = default; \ - __move_constructor& operator=(__move_constructor&&) = default; \ - move_constructor; \ + _LIBCPP_HIDE_FROM_ABI __move_constructor(const __move_constructor&) = default; \ + _LIBCPP_HIDE_FROM_ABI ~__move_constructor() = default; \ + _LIBCPP_HIDE_FROM_ABI __move_constructor& operator=(const __move_constructor&) = default; \ + _LIBCPP_HIDE_FROM_ABI __move_constructor& operator=(__move_constructor&&) = default; \ + move_constructor_definition; \ } -_LIBCPP_VARIANT_MOVE_CONSTRUCTOR(_Trait::_TriviallyAvailable, - __move_constructor(__move_constructor&& __that) = default); +_LIBCPP_VARIANT_MOVE_CONSTRUCTOR( + _Trait::_TriviallyAvailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __move_constructor(__move_constructor&& __that) = default); _LIBCPP_VARIANT_MOVE_CONSTRUCTOR( _Trait::_Available, - _LIBCPP_HIDE_FROM_ABI __move_constructor(__move_constructor&& __that) noexcept( + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __move_constructor(__move_constructor&& __that) noexcept( __all...>::value) : __move_constructor(__valueless_t{}) { this->__generic_construct(*this, std::move(__that)); } _LIBCPP_EAT_SEMICOLON); -_LIBCPP_VARIANT_MOVE_CONSTRUCTOR(_Trait::_Unavailable, __move_constructor(__move_constructor&&) = delete); +_LIBCPP_VARIANT_MOVE_CONSTRUCTOR( + _Trait::_Unavailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __move_constructor(__move_constructor&&) = delete); # undef _LIBCPP_VARIANT_MOVE_CONSTRUCTOR template class _LIBCPP_TEMPLATE_VIS __copy_constructor; -# define _LIBCPP_VARIANT_COPY_CONSTRUCTOR(copy_constructible_trait, copy_constructor) \ +# define _LIBCPP_VARIANT_COPY_CONSTRUCTOR(copy_constructible_trait, copy_constructor_definition) \ template \ class _LIBCPP_TEMPLATE_VIS __copy_constructor<__traits<_Types...>, copy_constructible_trait> \ : public __move_constructor<__traits<_Types...>> { \ @@ -881,21 +883,25 @@ class _LIBCPP_TEMPLATE_VIS __copy_constructor; using __base_type::__base_type; \ using __base_type::operator=; \ \ - __copy_constructor(__copy_constructor&&) = default; \ - ~__copy_constructor() = default; \ - __copy_constructor& operator=(const __copy_constructor&) = default; \ - __copy_constructor& operator=(__copy_constructor&&) = default; \ - copy_constructor; \ - } // namespace __variant_detail + _LIBCPP_HIDE_FROM_ABI __copy_constructor(__copy_constructor&&) = default; \ + _LIBCPP_HIDE_FROM_ABI ~__copy_constructor() = default; \ + _LIBCPP_HIDE_FROM_ABI __copy_constructor& operator=(const __copy_constructor&) = default; \ + _LIBCPP_HIDE_FROM_ABI __copy_constructor& operator=(__copy_constructor&&) = default; \ + copy_constructor_definition; \ + } -_LIBCPP_VARIANT_COPY_CONSTRUCTOR(_Trait::_TriviallyAvailable, - __copy_constructor(const __copy_constructor& __that) = default); +_LIBCPP_VARIANT_COPY_CONSTRUCTOR( + _Trait::_TriviallyAvailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __copy_constructor(const __copy_constructor& __that) = default); _LIBCPP_VARIANT_COPY_CONSTRUCTOR( - _Trait::_Available, _LIBCPP_HIDE_FROM_ABI __copy_constructor(const __copy_constructor& __that) + _Trait::_Available, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __copy_constructor(const __copy_constructor& __that) : __copy_constructor(__valueless_t{}) { this->__generic_construct(*this, __that); } _LIBCPP_EAT_SEMICOLON); -_LIBCPP_VARIANT_COPY_CONSTRUCTOR(_Trait::_Unavailable, __copy_constructor(const __copy_constructor&) = delete); +_LIBCPP_VARIANT_COPY_CONSTRUCTOR( + _Trait::_Unavailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __copy_constructor(const __copy_constructor&) = delete); # undef _LIBCPP_VARIANT_COPY_CONSTRUCTOR @@ -908,22 +914,24 @@ public: using __base_type::operator=; template - _LIBCPP_HIDE_FROM_ABI auto& __emplace(_Args&&... __args) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 auto& __emplace(_Args&&... __args) { this->__destroy(); - auto& __res = this->__construct_alt(__access::__base::__get_alt<_Ip>(*this), std::forward<_Args>(__args)...); + std::__construct_at(std::addressof(this->__data), in_place_index<_Ip>, std::forward<_Args>(__args)...); this->__index = _Ip; - return __res; + return __access::__base::__get_alt<_Ip>(*this).__value; } protected: template - _LIBCPP_HIDE_FROM_ABI void __assign_alt(__alt<_Ip, _Tp>& __a, _Arg&& __arg) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __assign_alt(__alt<_Ip, _Tp>& __a, _Arg&& __arg) { if (this->index() == _Ip) { __a.__value = std::forward<_Arg>(__arg); } else { struct { - _LIBCPP_HIDDEN void operator()(true_type) const { __this->__emplace<_Ip>(std::forward<_Arg>(__arg)); } - _LIBCPP_HIDDEN void operator()(false_type) const { + _LIBCPP_HIDDEN _LIBCPP_CONSTEXPR_SINCE_CXX20 void operator()(true_type) const { + __this->__emplace<_Ip>(std::forward<_Arg>(__arg)); + } + _LIBCPP_HIDDEN _LIBCPP_CONSTEXPR_SINCE_CXX20 void operator()(false_type) const { __this->__emplace<_Ip>(_Tp(std::forward<_Arg>(__arg))); } __assignment* __this; @@ -934,7 +942,7 @@ protected: } template - _LIBCPP_HIDE_FROM_ABI void __generic_assign(_That&& __that) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __generic_assign(_That&& __that) { if (this->valueless_by_exception() && __that.valueless_by_exception()) { // do nothing. } else if (__that.valueless_by_exception()) { @@ -954,7 +962,7 @@ protected: template class _LIBCPP_TEMPLATE_VIS __move_assignment; -# define _LIBCPP_VARIANT_MOVE_ASSIGNMENT(move_assignable_trait, move_assignment) \ +# define _LIBCPP_VARIANT_MOVE_ASSIGNMENT(move_assignable_trait, move_assignment_definition) \ template \ class _LIBCPP_TEMPLATE_VIS __move_assignment<__traits<_Types...>, move_assignable_trait> \ : public __assignment<__traits<_Types...>> { \ @@ -964,33 +972,36 @@ class _LIBCPP_TEMPLATE_VIS __move_assignment; using __base_type::__base_type; \ using __base_type::operator=; \ \ - __move_assignment(const __move_assignment&) = default; \ - __move_assignment(__move_assignment&&) = default; \ - ~__move_assignment() = default; \ - __move_assignment& operator=(const __move_assignment&) = default; \ - move_assignment; \ + _LIBCPP_HIDE_FROM_ABI __move_assignment(const __move_assignment&) = default; \ + _LIBCPP_HIDE_FROM_ABI __move_assignment(__move_assignment&&) = default; \ + _LIBCPP_HIDE_FROM_ABI ~__move_assignment() = default; \ + _LIBCPP_HIDE_FROM_ABI __move_assignment& operator=(const __move_assignment&) = default; \ + move_assignment_definition; \ } _LIBCPP_VARIANT_MOVE_ASSIGNMENT(_Trait::_TriviallyAvailable, - __move_assignment& operator=(__move_assignment&& __that) = default); + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __move_assignment& operator=( + __move_assignment&& __that) = default); _LIBCPP_VARIANT_MOVE_ASSIGNMENT( _Trait::_Available, - _LIBCPP_HIDE_FROM_ABI __move_assignment& + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __move_assignment& operator=(__move_assignment&& __that) noexcept( __all<(is_nothrow_move_constructible_v<_Types> && is_nothrow_move_assignable_v<_Types>)...>::value) { this->__generic_assign(std::move(__that)); return *this; } _LIBCPP_EAT_SEMICOLON); -_LIBCPP_VARIANT_MOVE_ASSIGNMENT(_Trait::_Unavailable, __move_assignment& operator=(__move_assignment&&) = delete); +_LIBCPP_VARIANT_MOVE_ASSIGNMENT( + _Trait::_Unavailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __move_assignment& operator=(__move_assignment&&) = delete); # undef _LIBCPP_VARIANT_MOVE_ASSIGNMENT template class _LIBCPP_TEMPLATE_VIS __copy_assignment; -# define _LIBCPP_VARIANT_COPY_ASSIGNMENT(copy_assignable_trait, copy_assignment) \ +# define _LIBCPP_VARIANT_COPY_ASSIGNMENT(copy_assignable_trait, copy_assignment_definition) \ template \ class _LIBCPP_TEMPLATE_VIS __copy_assignment<__traits<_Types...>, copy_assignable_trait> \ : public __move_assignment<__traits<_Types...>> { \ @@ -1000,23 +1011,28 @@ class _LIBCPP_TEMPLATE_VIS __copy_assignment; using __base_type::__base_type; \ using __base_type::operator=; \ \ - __copy_assignment(const __copy_assignment&) = default; \ - __copy_assignment(__copy_assignment&&) = default; \ - ~__copy_assignment() = default; \ - __copy_assignment& operator=(__copy_assignment&&) = default; \ - copy_assignment; \ + _LIBCPP_HIDE_FROM_ABI __copy_assignment(const __copy_assignment&) = default; \ + _LIBCPP_HIDE_FROM_ABI __copy_assignment(__copy_assignment&&) = default; \ + _LIBCPP_HIDE_FROM_ABI ~__copy_assignment() = default; \ + _LIBCPP_HIDE_FROM_ABI __copy_assignment& operator=(__copy_assignment&&) = default; \ + copy_assignment_definition; \ } _LIBCPP_VARIANT_COPY_ASSIGNMENT(_Trait::_TriviallyAvailable, - __copy_assignment& operator=(const __copy_assignment& __that) = default); + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __copy_assignment& operator=( + const __copy_assignment& __that) = default); _LIBCPP_VARIANT_COPY_ASSIGNMENT( - _Trait::_Available, _LIBCPP_HIDE_FROM_ABI __copy_assignment& operator=(const __copy_assignment& __that) { + _Trait::_Available, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __copy_assignment& + operator=(const __copy_assignment& __that) { this->__generic_assign(__that); return *this; } _LIBCPP_EAT_SEMICOLON); -_LIBCPP_VARIANT_COPY_ASSIGNMENT(_Trait::_Unavailable, __copy_assignment& operator=(const __copy_assignment&) = delete); +_LIBCPP_VARIANT_COPY_ASSIGNMENT(_Trait::_Unavailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __copy_assignment& operator=( + const __copy_assignment&) = delete); # undef _LIBCPP_VARIANT_COPY_ASSIGNMENT @@ -1032,11 +1048,11 @@ public: _LIBCPP_HIDE_FROM_ABI __impl& operator=(__impl&&) = default; template - _LIBCPP_HIDE_FROM_ABI void __assign(_Arg&& __arg) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __assign(_Arg&& __arg) { this->__assign_alt(__access::__base::__get_alt<_Ip>(*this), std::forward<_Arg>(__arg)); } - inline _LIBCPP_HIDE_FROM_ABI void __swap(__impl& __that) { + inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __swap(__impl& __that) { if (this->valueless_by_exception() && __that.valueless_by_exception()) { // do nothing. } else if (this->index() == __that.index()) { @@ -1081,7 +1097,7 @@ public: } private: - inline _LIBCPP_HIDE_FROM_ABI bool __move_nothrow() const { + constexpr inline _LIBCPP_HIDE_FROM_ABI bool __move_nothrow() const { constexpr bool __results[] = {is_nothrow_move_constructible_v<_Types>...}; return this->valueless_by_exception() || __results[this->index()]; } @@ -1223,7 +1239,7 @@ public: _Args&&... __args) noexcept(is_nothrow_constructible_v<_Tp, initializer_list< _Up>&, _Args...>) : __impl_(in_place_index<_Ip>, __il, std::forward<_Args>(__args)...) {} - _LIBCPP_HIDE_FROM_ABI ~variant() = default; + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~variant() = default; _LIBCPP_HIDE_FROM_ABI constexpr variant& operator=(const variant&) = default; _LIBCPP_HIDE_FROM_ABI constexpr variant& operator=(variant&&) = default; @@ -1233,7 +1249,7 @@ public: class _Tp = __variant_detail::__best_match_t<_Arg, _Types...>, size_t _Ip = __find_detail::__find_unambiguous_index_sfinae<_Tp, _Types...>::value, enable_if_t && is_constructible_v<_Tp, _Arg>, int> = 0> - _LIBCPP_HIDE_FROM_ABI variant& + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 variant& operator=(_Arg&& __arg) noexcept(is_nothrow_assignable_v<_Tp&, _Arg> && is_nothrow_constructible_v<_Tp, _Arg>) { __impl_.template __assign<_Ip>(std::forward<_Arg>(__arg)); return *this; @@ -1244,7 +1260,7 @@ public: enable_if_t<(_Ip < sizeof...(_Types)), int> = 0, class _Tp = variant_alternative_t<_Ip, variant<_Types...>>, enable_if_t, int> = 0> - _LIBCPP_HIDE_FROM_ABI _Tp& emplace(_Args&&... __args) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _Tp& emplace(_Args&&... __args) { return __impl_.template __emplace<_Ip>(std::forward<_Args>(__args)...); } @@ -1254,7 +1270,7 @@ public: enable_if_t<(_Ip < sizeof...(_Types)), int> = 0, class _Tp = variant_alternative_t<_Ip, variant<_Types...>>, enable_if_t&, _Args...>, int> = 0> - _LIBCPP_HIDE_FROM_ABI _Tp& emplace(initializer_list<_Up> __il, _Args&&... __args) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _Tp& emplace(initializer_list<_Up> __il, _Args&&... __args) { return __impl_.template __emplace<_Ip>(__il, std::forward<_Args>(__args)...); } @@ -1262,7 +1278,7 @@ public: class... _Args, size_t _Ip = __find_detail::__find_unambiguous_index_sfinae<_Tp, _Types...>::value, enable_if_t, int> = 0> - _LIBCPP_HIDE_FROM_ABI _Tp& emplace(_Args&&... __args) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _Tp& emplace(_Args&&... __args) { return __impl_.template __emplace<_Ip>(std::forward<_Args>(__args)...); } @@ -1271,7 +1287,7 @@ public: class... _Args, size_t _Ip = __find_detail::__find_unambiguous_index_sfinae<_Tp, _Types...>::value, enable_if_t&, _Args...>, int> = 0> - _LIBCPP_HIDE_FROM_ABI _Tp& emplace(initializer_list<_Up> __il, _Args&&... __args) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _Tp& emplace(initializer_list<_Up> __il, _Args&&... __args) { return __impl_.template __emplace<_Ip>(__il, std::forward<_Args>(__args)...); } @@ -1285,7 +1301,7 @@ public: enable_if_t< __all<(__dependent_type, _Dummy>::value && __dependent_type, _Dummy>::value)...>::value, int> = 0> - _LIBCPP_HIDE_FROM_ABI void swap(variant& __that) noexcept( + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void swap(variant& __that) noexcept( __all<(is_nothrow_move_constructible_v<_Types> && is_nothrow_swappable_v<_Types>)...>::value) { __impl_.__swap(__that.__impl_); } @@ -1568,7 +1584,7 @@ visit(_Visitor&& __visitor, _Vs&&... __vs) { # endif template -_LIBCPP_HIDE_FROM_ABI auto +_LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 auto swap(variant<_Types...>& __lhs, variant<_Types...>& __rhs) noexcept(noexcept(__lhs.swap(__rhs))) -> decltype(__lhs.swap(__rhs)) { return __lhs.swap(__rhs); diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/T.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/T.pass.cpp index 4b9eaba2d2ba..98faf84fa52d 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/T.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/T.pass.cpp @@ -33,17 +33,17 @@ struct Dummy { struct ThrowsCtorT { ThrowsCtorT(int) noexcept(false) {} - ThrowsCtorT &operator=(int) noexcept { return *this; } + ThrowsCtorT& operator=(int) noexcept { return *this; } }; struct ThrowsAssignT { ThrowsAssignT(int) noexcept {} - ThrowsAssignT &operator=(int) noexcept(false) { return *this; } + ThrowsAssignT& operator=(int) noexcept(false) { return *this; } }; struct NoThrowT { NoThrowT(int) noexcept {} - NoThrowT &operator=(int) noexcept { return *this; } + NoThrowT& operator=(int) noexcept { return *this; } }; } // namespace MetaHelpers @@ -55,7 +55,7 @@ struct ThrowsCtorT { int value; ThrowsCtorT() : value(0) {} ThrowsCtorT(int) noexcept(false) { throw 42; } - ThrowsCtorT &operator=(int v) noexcept { + ThrowsCtorT& operator=(int v) noexcept { value = v; return *this; } @@ -64,9 +64,12 @@ struct ThrowsCtorT { struct MoveCrashes { int value; MoveCrashes(int v = 0) noexcept : value{v} {} - MoveCrashes(MoveCrashes &&) noexcept { assert(false); } - MoveCrashes &operator=(MoveCrashes &&) noexcept { assert(false); return *this; } - MoveCrashes &operator=(int v) noexcept { + MoveCrashes(MoveCrashes&&) noexcept { assert(false); } + MoveCrashes& operator=(MoveCrashes&&) noexcept { + assert(false); + return *this; + } + MoveCrashes& operator=(int v) noexcept { value = v; return *this; } @@ -76,8 +79,8 @@ struct ThrowsCtorTandMove { int value; ThrowsCtorTandMove() : value(0) {} ThrowsCtorTandMove(int) noexcept(false) { throw 42; } - ThrowsCtorTandMove(ThrowsCtorTandMove &&) noexcept(false) { assert(false); } - ThrowsCtorTandMove &operator=(int v) noexcept { + ThrowsCtorTandMove(ThrowsCtorTandMove&&) noexcept(false) { assert(false); } + ThrowsCtorTandMove& operator=(int v) noexcept { value = v; return *this; } @@ -87,14 +90,14 @@ struct ThrowsAssignT { int value; ThrowsAssignT() : value(0) {} ThrowsAssignT(int v) noexcept : value(v) {} - ThrowsAssignT &operator=(int) noexcept(false) { throw 42; } + ThrowsAssignT& operator=(int) noexcept(false) { throw 42; } }; struct NoThrowT { int value; NoThrowT() : value(0) {} NoThrowT(int v) noexcept : value(v) {} - NoThrowT &operator=(int v) noexcept { + NoThrowT& operator=(int v) noexcept { value = v; return *this; } @@ -103,7 +106,7 @@ struct NoThrowT { #endif // !defined(TEST_HAS_NO_EXCEPTIONS) } // namespace RuntimeHelpers -void test_T_assignment_noexcept() { +constexpr void test_T_assignment_noexcept() { using namespace MetaHelpers; { using V = std::variant; @@ -119,17 +122,17 @@ void test_T_assignment_noexcept() { } } -void test_T_assignment_sfinae() { +constexpr void test_T_assignment_sfinae() { { using V = std::variant; static_assert(!std::is_assignable::value, "ambiguous"); } { using V = std::variant; - static_assert(!std::is_assignable::value, "ambiguous"); + static_assert(!std::is_assignable::value, "ambiguous"); } { - using V = std::variant; + using V = std::variant; static_assert(!std::is_assignable::value, "no matching operator="); } { @@ -138,8 +141,7 @@ void test_T_assignment_sfinae() { } { using V = std::variant, bool>; - static_assert(!std::is_assignable>::value, - "no explicit bool in operator="); + static_assert(!std::is_assignable>::value, "no explicit bool in operator="); struct X { operator void*(); }; @@ -152,12 +154,11 @@ void test_T_assignment_sfinae() { operator X(); }; using V = std::variant; - static_assert(std::is_assignable::value, - "regression on user-defined conversions in operator="); + static_assert(std::is_assignable::value, "regression on user-defined conversions in operator="); } } -void test_T_assignment_basic() { +TEST_CONSTEXPR_CXX20 void test_T_assignment_basic() { { std::variant v(43); v = 42; @@ -184,19 +185,146 @@ void test_T_assignment_basic() { } { std::variant v = true; - v = "bar"; + v = "bar"; assert(v.index() == 0); assert(std::get<0>(v) == "bar"); } +} + +void test_T_assignment_basic_no_constexpr() { + std::variant> v; + v = nullptr; + assert(v.index() == 1); + assert(std::get<1>(v) == nullptr); +} + +struct TraceStat { + int construct = 0; + int copy_construct = 0; + int copy_assign = 0; + int move_construct = 0; + int move_assign = 0; + int T_copy_assign = 0; + int T_move_assign = 0; + int destroy = 0; +}; + +template +struct Trace { + struct T {}; + + constexpr Trace(TraceStat* s) noexcept(CtorNoexcept) : stat(s) { ++s->construct; } + constexpr Trace(T) noexcept(CtorNoexcept) : stat(nullptr) {} + constexpr Trace(const Trace& o) : stat(o.stat) { ++stat->copy_construct; } + constexpr Trace(Trace&& o) noexcept(MoveCtorNoexcept) : stat(o.stat) { ++stat->move_construct; } + constexpr Trace& operator=(const Trace&) { + ++stat->copy_assign; + return *this; + } + constexpr Trace& operator=(Trace&&) noexcept { + ++stat->move_assign; + return *this; + } + + constexpr Trace& operator=(const T&) { + ++stat->T_copy_assign; + return *this; + } + constexpr Trace& operator=(T&&) noexcept { + ++stat->T_move_assign; + return *this; + } + TEST_CONSTEXPR_CXX20 ~Trace() { ++stat->destroy; } + + TraceStat* stat; +}; + +TEST_CONSTEXPR_CXX20 void test_T_assignment_performs_construction() { { - std::variant> v; - v = nullptr; - assert(v.index() == 1); - assert(std::get<1>(v) == nullptr); + using V = std::variant>; + TraceStat stat; + V v{1}; + v = &stat; + assert(stat.construct == 1); + assert(stat.copy_construct == 0); + assert(stat.move_construct == 0); + assert(stat.copy_assign == 0); + assert(stat.move_assign == 0); + assert(stat.destroy == 0); + } + { + using V = std::variant>; + TraceStat stat; + V v{1}; + v = &stat; + assert(stat.construct == 1); + assert(stat.copy_construct == 0); + assert(stat.move_construct == 1); + assert(stat.copy_assign == 0); + assert(stat.move_assign == 0); + assert(stat.destroy == 1); + } + + { + using V = std::variant>; + TraceStat stat; + V v{1}; + v = &stat; + assert(stat.construct == 1); + assert(stat.copy_construct == 0); + assert(stat.move_construct == 0); + assert(stat.copy_assign == 0); + assert(stat.move_assign == 0); + assert(stat.destroy == 0); + } + + { + using V = std::variant>; + TraceStat stat; + V v{1}; + v = &stat; + assert(stat.construct == 1); + assert(stat.copy_construct == 0); + assert(stat.move_construct == 0); + assert(stat.copy_assign == 0); + assert(stat.move_assign == 0); + assert(stat.destroy == 0); } } -void test_T_assignment_performs_construction() { +TEST_CONSTEXPR_CXX20 void test_T_assignment_performs_assignment() { + { + using V = std::variant>; + TraceStat stat; + V v{&stat}; + v = Trace::T{}; + assert(stat.construct == 1); + assert(stat.copy_construct == 0); + assert(stat.move_construct == 0); + assert(stat.copy_assign == 0); + assert(stat.move_assign == 0); + assert(stat.T_copy_assign == 0); + assert(stat.T_move_assign == 1); + assert(stat.destroy == 0); + } + { + using V = std::variant>; + TraceStat stat; + V v{&stat}; + Trace::T t; + v = t; + assert(stat.construct == 1); + assert(stat.copy_construct == 0); + assert(stat.move_construct == 0); + assert(stat.copy_assign == 0); + assert(stat.move_assign == 0); + assert(stat.T_copy_assign == 1); + assert(stat.T_move_assign == 0); + assert(stat.destroy == 0); + } +} + +void test_T_assignment_performs_construction_throw() { using namespace RuntimeHelpers; #ifndef TEST_HAS_NO_EXCEPTIONS { @@ -220,7 +348,7 @@ void test_T_assignment_performs_construction() { #endif // TEST_HAS_NO_EXCEPTIONS } -void test_T_assignment_performs_assignment() { +void test_T_assignment_performs_assignment_throw() { using namespace RuntimeHelpers; #ifndef TEST_HAS_NO_EXCEPTIONS { @@ -262,7 +390,7 @@ void test_T_assignment_performs_assignment() { #endif // TEST_HAS_NO_EXCEPTIONS } -void test_T_assignment_vector_bool() { +TEST_CONSTEXPR_CXX20 void test_T_assignment_vector_bool() { std::vector vec = {true}; std::variant v; v = vec[0]; @@ -270,7 +398,13 @@ void test_T_assignment_vector_bool() { assert(std::get<0>(v) == true); } -int main(int, char**) { +void non_constexpr_test() { + test_T_assignment_basic_no_constexpr(); + test_T_assignment_performs_construction_throw(); + test_T_assignment_performs_assignment_throw(); +} + +TEST_CONSTEXPR_CXX20 bool test() { test_T_assignment_basic(); test_T_assignment_performs_construction(); test_T_assignment_performs_assignment(); @@ -278,5 +412,15 @@ int main(int, char**) { test_T_assignment_sfinae(); test_T_assignment_vector_bool(); + return true; +} + +int main(int, char**) { + test(); + non_constexpr_test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp index 096d365d2d75..a6d3f34114eb 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp @@ -22,88 +22,108 @@ #include "test_macros.h" struct NoCopy { - NoCopy(const NoCopy &) = delete; - NoCopy &operator=(const NoCopy &) = default; + NoCopy(const NoCopy&) = delete; + NoCopy& operator=(const NoCopy&) = default; }; struct CopyOnly { - CopyOnly(const CopyOnly &) = default; - CopyOnly(CopyOnly &&) = delete; - CopyOnly &operator=(const CopyOnly &) = default; - CopyOnly &operator=(CopyOnly &&) = delete; + CopyOnly(const CopyOnly&) = default; + CopyOnly(CopyOnly&&) = delete; + CopyOnly& operator=(const CopyOnly&) = default; + CopyOnly& operator=(CopyOnly&&) = delete; }; struct MoveOnly { - MoveOnly(const MoveOnly &) = delete; - MoveOnly(MoveOnly &&) = default; - MoveOnly &operator=(const MoveOnly &) = default; + MoveOnly(const MoveOnly&) = delete; + MoveOnly(MoveOnly&&) = default; + MoveOnly& operator=(const MoveOnly&) = default; }; struct MoveOnlyNT { - MoveOnlyNT(const MoveOnlyNT &) = delete; - MoveOnlyNT(MoveOnlyNT &&) {} - MoveOnlyNT &operator=(const MoveOnlyNT &) = default; + MoveOnlyNT(const MoveOnlyNT&) = delete; + MoveOnlyNT(MoveOnlyNT&&) {} + MoveOnlyNT& operator=(const MoveOnlyNT&) = default; }; struct CopyAssign { - static int alive; - static int copy_construct; - static int copy_assign; - static int move_construct; - static int move_assign; - static void reset() { - copy_construct = copy_assign = move_construct = move_assign = alive = 0; - } - CopyAssign(int v) : value(v) { ++alive; } - CopyAssign(const CopyAssign &o) : value(o.value) { - ++alive; - ++copy_construct; - } - CopyAssign(CopyAssign &&o) noexcept : value(o.value) { + constexpr CopyAssign(int v, int* alv, int* cpy_ctr, int* cpy_assi, int* move_ctr, int* move_assi) + : value(v), + alive(alv), + copy_construct(cpy_ctr), + copy_assign(cpy_assi), + move_construct(move_ctr), + move_assign(move_assi) { + ++*alive; + } + constexpr CopyAssign(const CopyAssign& o) + : value(o.value), + alive(o.alive), + copy_construct(o.copy_construct), + copy_assign(o.copy_assign), + move_construct(o.move_construct), + move_assign(o.move_assign) { + ++*alive; + ++*copy_construct; + } + constexpr CopyAssign(CopyAssign&& o) noexcept + : value(o.value), + alive(o.alive), + copy_construct(o.copy_construct), + copy_assign(o.copy_assign), + move_construct(o.move_construct), + move_assign(o.move_assign) { o.value = -1; - ++alive; - ++move_construct; - } - CopyAssign &operator=(const CopyAssign &o) { - value = o.value; - ++copy_assign; + ++*alive; + ++*move_construct; + } + constexpr CopyAssign& operator=(const CopyAssign& o) { + value = o.value; + alive = o.alive; + copy_construct = o.copy_construct; + copy_assign = o.copy_assign; + move_construct = o.move_construct; + move_assign = o.move_assign; + ++*copy_assign; return *this; } - CopyAssign &operator=(CopyAssign &&o) noexcept { - value = o.value; - o.value = -1; - ++move_assign; + constexpr CopyAssign& operator=(CopyAssign&& o) noexcept { + value = o.value; + alive = o.alive; + copy_construct = o.copy_construct; + copy_assign = o.copy_assign; + move_construct = o.move_construct; + move_assign = o.move_assign; + o.value = -1; + ++*move_assign; return *this; } - ~CopyAssign() { --alive; } + TEST_CONSTEXPR_CXX20 ~CopyAssign() { --*alive; } int value; + int* alive; + int* copy_construct; + int* copy_assign; + int* move_construct; + int* move_assign; }; -int CopyAssign::alive = 0; -int CopyAssign::copy_construct = 0; -int CopyAssign::copy_assign = 0; -int CopyAssign::move_construct = 0; -int CopyAssign::move_assign = 0; - struct CopyMaybeThrows { - CopyMaybeThrows(const CopyMaybeThrows &); - CopyMaybeThrows &operator=(const CopyMaybeThrows &); + CopyMaybeThrows(const CopyMaybeThrows&); + CopyMaybeThrows& operator=(const CopyMaybeThrows&); }; struct CopyDoesThrow { - CopyDoesThrow(const CopyDoesThrow &) noexcept(false); - CopyDoesThrow &operator=(const CopyDoesThrow &) noexcept(false); + CopyDoesThrow(const CopyDoesThrow&) noexcept(false); + CopyDoesThrow& operator=(const CopyDoesThrow&) noexcept(false); }; - struct NTCopyAssign { constexpr NTCopyAssign(int v) : value(v) {} - NTCopyAssign(const NTCopyAssign &) = default; - NTCopyAssign(NTCopyAssign &&) = default; - NTCopyAssign &operator=(const NTCopyAssign &that) { + NTCopyAssign(const NTCopyAssign&) = default; + NTCopyAssign(NTCopyAssign&&) = default; + NTCopyAssign& operator=(const NTCopyAssign& that) { value = that.value; return *this; }; - NTCopyAssign &operator=(NTCopyAssign &&) = delete; + NTCopyAssign& operator=(NTCopyAssign&&) = delete; int value; }; @@ -112,10 +132,10 @@ static_assert(std::is_copy_assignable::value, ""); struct TCopyAssign { constexpr TCopyAssign(int v) : value(v) {} - TCopyAssign(const TCopyAssign &) = default; - TCopyAssign(TCopyAssign &&) = default; - TCopyAssign &operator=(const TCopyAssign &) = default; - TCopyAssign &operator=(TCopyAssign &&) = delete; + TCopyAssign(const TCopyAssign&) = default; + TCopyAssign(TCopyAssign&&) = default; + TCopyAssign& operator=(const TCopyAssign&) = default; + TCopyAssign& operator=(TCopyAssign&&) = delete; int value; }; @@ -123,11 +143,11 @@ static_assert(std::is_trivially_copy_assignable::value, ""); struct TCopyAssignNTMoveAssign { constexpr TCopyAssignNTMoveAssign(int v) : value(v) {} - TCopyAssignNTMoveAssign(const TCopyAssignNTMoveAssign &) = default; - TCopyAssignNTMoveAssign(TCopyAssignNTMoveAssign &&) = default; - TCopyAssignNTMoveAssign &operator=(const TCopyAssignNTMoveAssign &) = default; - TCopyAssignNTMoveAssign &operator=(TCopyAssignNTMoveAssign &&that) { - value = that.value; + TCopyAssignNTMoveAssign(const TCopyAssignNTMoveAssign&) = default; + TCopyAssignNTMoveAssign(TCopyAssignNTMoveAssign&&) = default; + TCopyAssignNTMoveAssign& operator=(const TCopyAssignNTMoveAssign&) = default; + TCopyAssignNTMoveAssign& operator=(TCopyAssignNTMoveAssign&& that) { + value = that.value; that.value = -1; return *this; } @@ -139,17 +159,20 @@ static_assert(std::is_trivially_copy_assignable_v, ""); #ifndef TEST_HAS_NO_EXCEPTIONS struct CopyThrows { CopyThrows() = default; - CopyThrows(const CopyThrows &) { throw 42; } - CopyThrows &operator=(const CopyThrows &) { throw 42; } + CopyThrows(const CopyThrows&) { throw 42; } + CopyThrows& operator=(const CopyThrows&) { throw 42; } }; struct CopyCannotThrow { static int alive; CopyCannotThrow() { ++alive; } - CopyCannotThrow(const CopyCannotThrow &) noexcept { ++alive; } - CopyCannotThrow(CopyCannotThrow &&) noexcept { assert(false); } - CopyCannotThrow &operator=(const CopyCannotThrow &) noexcept = default; - CopyCannotThrow &operator=(CopyCannotThrow &&) noexcept { assert(false); return *this; } + CopyCannotThrow(const CopyCannotThrow&) noexcept { ++alive; } + CopyCannotThrow(CopyCannotThrow&&) noexcept { assert(false); } + CopyCannotThrow& operator=(const CopyCannotThrow&) noexcept = default; + CopyCannotThrow& operator=(CopyCannotThrow&&) noexcept { + assert(false); + return *this; + } }; int CopyCannotThrow::alive = 0; @@ -157,10 +180,10 @@ int CopyCannotThrow::alive = 0; struct MoveThrows { static int alive; MoveThrows() { ++alive; } - MoveThrows(const MoveThrows &) { ++alive; } - MoveThrows(MoveThrows &&) { throw 42; } - MoveThrows &operator=(const MoveThrows &) { return *this; } - MoveThrows &operator=(MoveThrows &&) { throw 42; } + MoveThrows(const MoveThrows&) { ++alive; } + MoveThrows(MoveThrows&&) { throw 42; } + MoveThrows& operator=(const MoveThrows&) { return *this; } + MoveThrows& operator=(MoveThrows&&) { throw 42; } ~MoveThrows() { --alive; } }; @@ -169,20 +192,21 @@ int MoveThrows::alive = 0; struct MakeEmptyT { static int alive; MakeEmptyT() { ++alive; } - MakeEmptyT(const MakeEmptyT &) { + MakeEmptyT(const MakeEmptyT&) { ++alive; // Don't throw from the copy constructor since variant's assignment // operator performs a copy before committing to the assignment. } - MakeEmptyT(MakeEmptyT &&) { throw 42; } - MakeEmptyT &operator=(const MakeEmptyT &) { throw 42; } - MakeEmptyT &operator=(MakeEmptyT &&) { throw 42; } + MakeEmptyT(MakeEmptyT&&) { throw 42; } + MakeEmptyT& operator=(const MakeEmptyT&) { throw 42; } + MakeEmptyT& operator=(MakeEmptyT&&) { throw 42; } ~MakeEmptyT() { --alive; } }; int MakeEmptyT::alive = 0; -template void makeEmpty(Variant &v) { +template +void makeEmpty(Variant& v) { Variant v2(std::in_place_type); try { v = std::move(v2); @@ -193,7 +217,7 @@ template void makeEmpty(Variant &v) { } #endif // TEST_HAS_NO_EXCEPTIONS -void test_copy_assignment_not_noexcept() { +constexpr void test_copy_assignment_not_noexcept() { { using V = std::variant; static_assert(!std::is_nothrow_copy_assignable::value, ""); @@ -204,7 +228,7 @@ void test_copy_assignment_not_noexcept() { } } -void test_copy_assignment_sfinae() { +constexpr void test_copy_assignment_sfinae() { { using V = std::variant; static_assert(std::is_copy_assignable::value, ""); @@ -259,7 +283,7 @@ void test_copy_assignment_empty_empty() { makeEmpty(v1); V v2(std::in_place_index<0>); makeEmpty(v2); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.valueless_by_exception()); assert(v1.index() == std::variant_npos); @@ -275,7 +299,7 @@ void test_copy_assignment_non_empty_empty() { V v1(std::in_place_index<0>, 42); V v2(std::in_place_index<0>); makeEmpty(v2); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.valueless_by_exception()); assert(v1.index() == std::variant_npos); @@ -285,7 +309,7 @@ void test_copy_assignment_non_empty_empty() { V v1(std::in_place_index<2>, "hello"); V v2(std::in_place_index<0>); makeEmpty(v2); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.valueless_by_exception()); assert(v1.index() == std::variant_npos); @@ -301,7 +325,7 @@ void test_copy_assignment_empty_non_empty() { V v1(std::in_place_index<0>); makeEmpty(v1); V v2(std::in_place_index<0>, 42); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 0); assert(std::get<0>(v1) == 42); @@ -311,7 +335,7 @@ void test_copy_assignment_empty_non_empty() { V v1(std::in_place_index<0>); makeEmpty(v1); V v2(std::in_place_type, "hello"); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 2); assert(std::get<2>(v1) == "hello"); @@ -319,14 +343,18 @@ void test_copy_assignment_empty_non_empty() { #endif // TEST_HAS_NO_EXCEPTIONS } -template struct Result { std::size_t index; T value; }; +template +struct Result { + std::size_t index; + T value; +}; -void test_copy_assignment_same_index() { +TEST_CONSTEXPR_CXX20 void test_copy_assignment_same_index() { { using V = std::variant; V v1(43); V v2(42); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 0); assert(std::get<0>(v1) == 42); @@ -335,40 +363,28 @@ void test_copy_assignment_same_index() { using V = std::variant; V v1(43l); V v2(42l); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1) == 42); } { - using V = std::variant; - V v1(std::in_place_type, 43); - V v2(std::in_place_type, 42); - CopyAssign::reset(); - V &vref = (v1 = v2); + using V = std::variant; + int alive = 0; + int copy_construct = 0; + int copy_assign = 0; + int move_construct = 0; + int move_assign = 0; + V v1(std::in_place_type, 43, &alive, ©_construct, ©_assign, &move_construct, &move_assign); + V v2(std::in_place_type, 42, &alive, ©_construct, ©_assign, &move_construct, &move_assign); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1).value == 42); - assert(CopyAssign::copy_construct == 0); - assert(CopyAssign::move_construct == 0); - assert(CopyAssign::copy_assign == 1); + assert(copy_construct == 0); + assert(move_construct == 0); + assert(copy_assign == 1); } -#ifndef TEST_HAS_NO_EXCEPTIONS - using MET = MakeEmptyT; - { - using V = std::variant; - V v1(std::in_place_type); - MET &mref = std::get<1>(v1); - V v2(std::in_place_type); - try { - v1 = v2; - assert(false); - } catch (...) { - } - assert(v1.index() == 1); - assert(&std::get<1>(v1) == &mref); - } -#endif // TEST_HAS_NO_EXCEPTIONS // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). { @@ -429,34 +445,88 @@ void test_copy_assignment_same_index() { } } -void test_copy_assignment_different_index() { +TEST_CONSTEXPR_CXX20 void test_copy_assignment_different_index() { { using V = std::variant; V v1(43); V v2(42l); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1) == 42); } { - using V = std::variant; - CopyAssign::reset(); + using V = std::variant; + int alive = 0; + int copy_construct = 0; + int copy_assign = 0; + int move_construct = 0; + int move_assign = 0; V v1(std::in_place_type, 43u); - V v2(std::in_place_type, 42); - assert(CopyAssign::copy_construct == 0); - assert(CopyAssign::move_construct == 0); - assert(CopyAssign::alive == 1); - V &vref = (v1 = v2); + V v2(std::in_place_type, 42, &alive, ©_construct, ©_assign, &move_construct, &move_assign); + assert(copy_construct == 0); + assert(move_construct == 0); + assert(alive == 1); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1).value == 42); - assert(CopyAssign::alive == 2); - assert(CopyAssign::copy_construct == 1); - assert(CopyAssign::move_construct == 1); - assert(CopyAssign::copy_assign == 0); + assert(alive == 2); + assert(copy_construct == 1); + assert(move_construct == 1); + assert(copy_assign == 0); + } + + // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). + { + struct { + constexpr Result operator()() const { + using V = std::variant; + V v(43); + V v2(42l); + v = v2; + return {v.index(), std::get<1>(v)}; + } + } test; + constexpr auto result = test(); + static_assert(result.index == 1, ""); + static_assert(result.value == 42l, ""); } + { + struct { + constexpr Result operator()() const { + using V = std::variant; + V v(std::in_place_type, 43u); + V v2(std::in_place_type, 42); + v = v2; + return {v.index(), std::get<1>(v).value}; + } + } test; + constexpr auto result = test(); + static_assert(result.index == 1, ""); + static_assert(result.value == 42, ""); + } +} + +void test_assignment_throw() { #ifndef TEST_HAS_NO_EXCEPTIONS + using MET = MakeEmptyT; + // same index + { + using V = std::variant; + V v1(std::in_place_type); + MET& mref = std::get<1>(v1); + V v2(std::in_place_type); + try { + v1 = v2; + assert(false); + } catch (...) { + } + assert(v1.index() == 1); + assert(&std::get<1>(v1) == &mref); + } + + // difference indices { using V = std::variant; V v1(std::in_place_type, "hello"); @@ -496,7 +566,7 @@ void test_copy_assignment_different_index() { using V = std::variant; V v1(std::in_place_type); V v2(std::in_place_type, "hello"); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 2); assert(std::get<2>(v1) == "hello"); @@ -507,7 +577,7 @@ void test_copy_assignment_different_index() { using V = std::variant; V v1(std::in_place_type); V v2(std::in_place_type, "hello"); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 2); assert(std::get<2>(v1) == "hello"); @@ -515,69 +585,83 @@ void test_copy_assignment_different_index() { assert(std::get<2>(v2) == "hello"); } #endif // TEST_HAS_NO_EXCEPTIONS - - // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). - { - struct { - constexpr Result operator()() const { - using V = std::variant; - V v(43); - V v2(42l); - v = v2; - return {v.index(), std::get<1>(v)}; - } - } test; - constexpr auto result = test(); - static_assert(result.index == 1, ""); - static_assert(result.value == 42l, ""); - } - { - struct { - constexpr Result operator()() const { - using V = std::variant; - V v(std::in_place_type, 43u); - V v2(std::in_place_type, 42); - v = v2; - return {v.index(), std::get<1>(v).value}; - } - } test; - constexpr auto result = test(); - static_assert(result.index == 1, ""); - static_assert(result.value == 42, ""); - } } -template -constexpr bool test_constexpr_assign_imp( - std::variant&& v, ValueType&& new_value) -{ - const std::variant cp( - std::forward(new_value)); +template +constexpr void test_constexpr_assign_imp(T&& v, ValueType&& new_value) { + using Variant = std::decay_t; + const Variant cp(std::forward(new_value)); v = cp; - return v.index() == NewIdx && - std::get(v) == std::get(cp); + assert(v.index() == NewIdx); + assert(std::get(v) == std::get(cp)); } -void test_constexpr_copy_assignment() { +constexpr void test_constexpr_copy_assignment_trivial() { // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). using V = std::variant; static_assert(std::is_trivially_copyable::value, ""); static_assert(std::is_trivially_copy_assignable::value, ""); - static_assert(test_constexpr_assign_imp<0>(V(42l), 101l), ""); - static_assert(test_constexpr_assign_imp<0>(V(nullptr), 101l), ""); - static_assert(test_constexpr_assign_imp<1>(V(42l), nullptr), ""); - static_assert(test_constexpr_assign_imp<2>(V(42l), 101), ""); + test_constexpr_assign_imp<0>(V(42l), 101l); + test_constexpr_assign_imp<0>(V(nullptr), 101l); + test_constexpr_assign_imp<1>(V(42l), nullptr); + test_constexpr_assign_imp<2>(V(42l), 101); } -int main(int, char**) { +struct NonTrivialCopyAssign { + int i = 0; + constexpr NonTrivialCopyAssign(int ii) : i(ii) {} + constexpr NonTrivialCopyAssign(const NonTrivialCopyAssign& other) : i(other.i) {} + constexpr NonTrivialCopyAssign& operator=(const NonTrivialCopyAssign& o) { + i = o.i; + return *this; + } + TEST_CONSTEXPR_CXX20 ~NonTrivialCopyAssign() = default; + friend constexpr bool operator==(const NonTrivialCopyAssign& x, const NonTrivialCopyAssign& y) { return x.i == y.i; } +}; + +constexpr void test_constexpr_copy_assignment_non_trivial() { + // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). + using V = std::variant; + static_assert(!std::is_trivially_copyable::value, ""); + static_assert(!std::is_trivially_copy_assignable::value, ""); + test_constexpr_assign_imp<0>(V(42l), 101l); + test_constexpr_assign_imp<0>(V(nullptr), 101l); + test_constexpr_assign_imp<1>(V(42l), nullptr); + test_constexpr_assign_imp<2>(V(42l), NonTrivialCopyAssign(5)); + test_constexpr_assign_imp<2>(V(NonTrivialCopyAssign(3)), NonTrivialCopyAssign(5)); +} + +void non_constexpr_test() { test_copy_assignment_empty_empty(); test_copy_assignment_non_empty_empty(); test_copy_assignment_empty_non_empty(); - test_copy_assignment_same_index(); - test_copy_assignment_different_index(); + test_assignment_throw(); +} + +constexpr bool cxx17_constexpr_test() { test_copy_assignment_sfinae(); test_copy_assignment_not_noexcept(); - test_constexpr_copy_assignment(); + test_constexpr_copy_assignment_trivial(); + return true; +} + +TEST_CONSTEXPR_CXX20 bool cxx20_constexpr_test() { + test_copy_assignment_same_index(); + test_copy_assignment_different_index(); + test_constexpr_copy_assignment_non_trivial(); + + return true; +} + +int main(int, char**) { + non_constexpr_test(); + cxx17_constexpr_test(); + cxx20_constexpr_test(); + + static_assert(cxx17_constexpr_test()); +#if TEST_STD_VER >= 20 + static_assert(cxx20_constexpr_test()); +#endif return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp index 84094347aed3..157ff68f3748 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp @@ -24,71 +24,70 @@ #include "variant_test_helpers.h" struct NoCopy { - NoCopy(const NoCopy &) = delete; - NoCopy &operator=(const NoCopy &) = default; + NoCopy(const NoCopy&) = delete; + NoCopy& operator=(const NoCopy&) = default; }; struct CopyOnly { - CopyOnly(const CopyOnly &) = default; - CopyOnly(CopyOnly &&) = delete; - CopyOnly &operator=(const CopyOnly &) = default; - CopyOnly &operator=(CopyOnly &&) = delete; + CopyOnly(const CopyOnly&) = default; + CopyOnly(CopyOnly&&) = delete; + CopyOnly& operator=(const CopyOnly&) = default; + CopyOnly& operator=(CopyOnly&&) = delete; }; struct MoveOnly { - MoveOnly(const MoveOnly &) = delete; - MoveOnly(MoveOnly &&) = default; - MoveOnly &operator=(const MoveOnly &) = delete; - MoveOnly &operator=(MoveOnly &&) = default; + MoveOnly(const MoveOnly&) = delete; + MoveOnly(MoveOnly&&) = default; + MoveOnly& operator=(const MoveOnly&) = delete; + MoveOnly& operator=(MoveOnly&&) = default; }; struct MoveOnlyNT { - MoveOnlyNT(const MoveOnlyNT &) = delete; - MoveOnlyNT(MoveOnlyNT &&) {} - MoveOnlyNT &operator=(const MoveOnlyNT &) = delete; - MoveOnlyNT &operator=(MoveOnlyNT &&) = default; + MoveOnlyNT(const MoveOnlyNT&) = delete; + MoveOnlyNT(MoveOnlyNT&&) {} + MoveOnlyNT& operator=(const MoveOnlyNT&) = delete; + MoveOnlyNT& operator=(MoveOnlyNT&&) = default; }; struct MoveOnlyOddNothrow { - MoveOnlyOddNothrow(MoveOnlyOddNothrow &&) noexcept(false) {} - MoveOnlyOddNothrow(const MoveOnlyOddNothrow &) = delete; - MoveOnlyOddNothrow &operator=(MoveOnlyOddNothrow &&) noexcept = default; - MoveOnlyOddNothrow &operator=(const MoveOnlyOddNothrow &) = delete; + MoveOnlyOddNothrow(MoveOnlyOddNothrow&&) noexcept(false) {} + MoveOnlyOddNothrow(const MoveOnlyOddNothrow&) = delete; + MoveOnlyOddNothrow& operator=(MoveOnlyOddNothrow&&) noexcept = default; + MoveOnlyOddNothrow& operator=(const MoveOnlyOddNothrow&) = delete; }; struct MoveAssignOnly { - MoveAssignOnly(MoveAssignOnly &&) = delete; - MoveAssignOnly &operator=(MoveAssignOnly &&) = default; + MoveAssignOnly(MoveAssignOnly&&) = delete; + MoveAssignOnly& operator=(MoveAssignOnly&&) = default; }; struct MoveAssign { - static int move_construct; - static int move_assign; - static void reset() { move_construct = move_assign = 0; } - MoveAssign(int v) : value(v) {} - MoveAssign(MoveAssign &&o) : value(o.value) { - ++move_construct; + constexpr MoveAssign(int v, int* move_ctor, int* move_assi) + : value(v), move_construct(move_ctor), move_assign(move_assi) {} + constexpr MoveAssign(MoveAssign&& o) : value(o.value), move_construct(o.move_construct), move_assign(o.move_assign) { + ++*move_construct; o.value = -1; } - MoveAssign &operator=(MoveAssign &&o) { - value = o.value; - ++move_assign; + constexpr MoveAssign& operator=(MoveAssign&& o) { + value = o.value; + move_construct = o.move_construct; + move_assign = o.move_assign; + ++*move_assign; o.value = -1; return *this; } int value; + int* move_construct; + int* move_assign; }; -int MoveAssign::move_construct = 0; -int MoveAssign::move_assign = 0; - struct NTMoveAssign { constexpr NTMoveAssign(int v) : value(v) {} - NTMoveAssign(const NTMoveAssign &) = default; - NTMoveAssign(NTMoveAssign &&) = default; - NTMoveAssign &operator=(const NTMoveAssign &that) = default; - NTMoveAssign &operator=(NTMoveAssign &&that) { - value = that.value; + NTMoveAssign(const NTMoveAssign&) = default; + NTMoveAssign(NTMoveAssign&&) = default; + NTMoveAssign& operator=(const NTMoveAssign& that) = default; + NTMoveAssign& operator=(NTMoveAssign&& that) { + value = that.value; that.value = -1; return *this; }; @@ -100,10 +99,10 @@ static_assert(std::is_move_assignable::value, ""); struct TMoveAssign { constexpr TMoveAssign(int v) : value(v) {} - TMoveAssign(const TMoveAssign &) = delete; - TMoveAssign(TMoveAssign &&) = default; - TMoveAssign &operator=(const TMoveAssign &) = delete; - TMoveAssign &operator=(TMoveAssign &&) = default; + TMoveAssign(const TMoveAssign&) = delete; + TMoveAssign(TMoveAssign&&) = default; + TMoveAssign& operator=(const TMoveAssign&) = delete; + TMoveAssign& operator=(TMoveAssign&&) = default; int value; }; @@ -111,13 +110,13 @@ static_assert(std::is_trivially_move_assignable::value, ""); struct TMoveAssignNTCopyAssign { constexpr TMoveAssignNTCopyAssign(int v) : value(v) {} - TMoveAssignNTCopyAssign(const TMoveAssignNTCopyAssign &) = default; - TMoveAssignNTCopyAssign(TMoveAssignNTCopyAssign &&) = default; - TMoveAssignNTCopyAssign &operator=(const TMoveAssignNTCopyAssign &that) { + TMoveAssignNTCopyAssign(const TMoveAssignNTCopyAssign&) = default; + TMoveAssignNTCopyAssign(TMoveAssignNTCopyAssign&&) = default; + TMoveAssignNTCopyAssign& operator=(const TMoveAssignNTCopyAssign& that) { value = that.value; return *this; } - TMoveAssignNTCopyAssign &operator=(TMoveAssignNTCopyAssign &&) = default; + TMoveAssignNTCopyAssign& operator=(TMoveAssignNTCopyAssign&&) = default; int value; }; @@ -127,16 +126,13 @@ struct TrivialCopyNontrivialMove { TrivialCopyNontrivialMove(TrivialCopyNontrivialMove const&) = default; TrivialCopyNontrivialMove(TrivialCopyNontrivialMove&&) noexcept {} TrivialCopyNontrivialMove& operator=(TrivialCopyNontrivialMove const&) = default; - TrivialCopyNontrivialMove& operator=(TrivialCopyNontrivialMove&&) noexcept { - return *this; - } + TrivialCopyNontrivialMove& operator=(TrivialCopyNontrivialMove&&) noexcept { return *this; } }; static_assert(std::is_trivially_copy_assignable_v, ""); static_assert(!std::is_trivially_move_assignable_v, ""); - -void test_move_assignment_noexcept() { +constexpr void test_move_assignment_noexcept() { { using V = std::variant; static_assert(std::is_nothrow_move_assignable::value, ""); @@ -163,7 +159,7 @@ void test_move_assignment_noexcept() { } } -void test_move_assignment_sfinae() { +constexpr void test_move_assignment_sfinae() { { using V = std::variant; static_assert(std::is_move_assignable::value, ""); @@ -228,7 +224,7 @@ void test_move_assignment_empty_empty() { makeEmpty(v1); V v2(std::in_place_index<0>); makeEmpty(v2); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.valueless_by_exception()); assert(v1.index() == std::variant_npos); @@ -244,7 +240,7 @@ void test_move_assignment_non_empty_empty() { V v1(std::in_place_index<0>, 42); V v2(std::in_place_index<0>); makeEmpty(v2); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.valueless_by_exception()); assert(v1.index() == std::variant_npos); @@ -254,7 +250,7 @@ void test_move_assignment_non_empty_empty() { V v1(std::in_place_index<2>, "hello"); V v2(std::in_place_index<0>); makeEmpty(v2); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.valueless_by_exception()); assert(v1.index() == std::variant_npos); @@ -270,7 +266,7 @@ void test_move_assignment_empty_non_empty() { V v1(std::in_place_index<0>); makeEmpty(v1); V v2(std::in_place_index<0>, 42); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 0); assert(std::get<0>(v1) == 42); @@ -280,7 +276,7 @@ void test_move_assignment_empty_non_empty() { V v1(std::in_place_index<0>); makeEmpty(v1); V v2(std::in_place_type, "hello"); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 2); assert(std::get<2>(v1) == "hello"); @@ -288,14 +284,18 @@ void test_move_assignment_empty_non_empty() { #endif // TEST_HAS_NO_EXCEPTIONS } -template struct Result { std::size_t index; T value; }; +template +struct Result { + std::size_t index; + T value; +}; -void test_move_assignment_same_index() { +TEST_CONSTEXPR_CXX20 void test_move_assignment_same_index() { { using V = std::variant; V v1(43); V v2(42); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 0); assert(std::get<0>(v1) == 42); @@ -304,39 +304,24 @@ void test_move_assignment_same_index() { using V = std::variant; V v1(43l); V v2(42l); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1) == 42); } { - using V = std::variant; - V v1(std::in_place_type, 43); - V v2(std::in_place_type, 42); - MoveAssign::reset(); - V &vref = (v1 = std::move(v2)); + using V = std::variant; + int move_construct = 0; + int move_assign = 0; + V v1(std::in_place_type, 43, &move_construct, &move_assign); + V v2(std::in_place_type, 42, &move_construct, &move_assign); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1).value == 42); - assert(MoveAssign::move_construct == 0); - assert(MoveAssign::move_assign == 1); - } -#ifndef TEST_HAS_NO_EXCEPTIONS - using MET = MakeEmptyT; - { - using V = std::variant; - V v1(std::in_place_type); - MET &mref = std::get<1>(v1); - V v2(std::in_place_type); - try { - v1 = std::move(v2); - assert(false); - } catch (...) { - } - assert(v1.index() == 1); - assert(&std::get<1>(v1) == &mref); + assert(move_construct == 0); + assert(move_assign == 1); } -#endif // TEST_HAS_NO_EXCEPTIONS // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). { @@ -383,52 +368,29 @@ void test_move_assignment_same_index() { } } -void test_move_assignment_different_index() { +TEST_CONSTEXPR_CXX20 void test_move_assignment_different_index() { { using V = std::variant; V v1(43); V v2(42l); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1) == 42); } { - using V = std::variant; + using V = std::variant; + int move_construct = 0; + int move_assign = 0; V v1(std::in_place_type, 43u); - V v2(std::in_place_type, 42); - MoveAssign::reset(); - V &vref = (v1 = std::move(v2)); + V v2(std::in_place_type, 42, &move_construct, &move_assign); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1).value == 42); - assert(MoveAssign::move_construct == 1); - assert(MoveAssign::move_assign == 0); + assert(move_construct == 1); + assert(move_assign == 0); } -#ifndef TEST_HAS_NO_EXCEPTIONS - using MET = MakeEmptyT; - { - using V = std::variant; - V v1(std::in_place_type); - V v2(std::in_place_type); - try { - v1 = std::move(v2); - assert(false); - } catch (...) { - } - assert(v1.valueless_by_exception()); - assert(v1.index() == std::variant_npos); - } - { - using V = std::variant; - V v1(std::in_place_type); - V v2(std::in_place_type, "hello"); - V &vref = (v1 = std::move(v2)); - assert(&vref == &v1); - assert(v1.index() == 2); - assert(std::get<2>(v1) == "hello"); - } -#endif // TEST_HAS_NO_EXCEPTIONS // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). { @@ -461,38 +423,126 @@ void test_move_assignment_different_index() { } } -template -constexpr bool test_constexpr_assign_imp( - std::variant&& v, ValueType&& new_value) -{ - std::variant v2( - std::forward(new_value)); +void test_assignment_throw() { +#ifndef TEST_HAS_NO_EXCEPTIONS + using MET = MakeEmptyT; + // same index + { + using V = std::variant; + V v1(std::in_place_type); + MET& mref = std::get<1>(v1); + V v2(std::in_place_type); + try { + v1 = std::move(v2); + assert(false); + } catch (...) { + } + assert(v1.index() == 1); + assert(&std::get<1>(v1) == &mref); + } + + // different indices + { + using V = std::variant; + V v1(std::in_place_type); + V v2(std::in_place_type); + try { + v1 = std::move(v2); + assert(false); + } catch (...) { + } + assert(v1.valueless_by_exception()); + assert(v1.index() == std::variant_npos); + } + { + using V = std::variant; + V v1(std::in_place_type); + V v2(std::in_place_type, "hello"); + V& vref = (v1 = std::move(v2)); + assert(&vref == &v1); + assert(v1.index() == 2); + assert(std::get<2>(v1) == "hello"); + } +#endif // TEST_HAS_NO_EXCEPTIONS +} + +template +constexpr void test_constexpr_assign_imp(T&& v, ValueType&& new_value) { + using Variant = std::decay_t; + Variant v2(std::forward(new_value)); const auto cp = v2; - v = std::move(v2); - return v.index() == NewIdx && - std::get(v) == std::get(cp); + v = std::move(v2); + assert(v.index() == NewIdx); + assert(std::get(v) == std::get(cp)); } -void test_constexpr_move_assignment() { +constexpr void test_constexpr_move_assignment_trivial() { // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). using V = std::variant; static_assert(std::is_trivially_copyable::value, ""); static_assert(std::is_trivially_move_assignable::value, ""); - static_assert(test_constexpr_assign_imp<0>(V(42l), 101l), ""); - static_assert(test_constexpr_assign_imp<0>(V(nullptr), 101l), ""); - static_assert(test_constexpr_assign_imp<1>(V(42l), nullptr), ""); - static_assert(test_constexpr_assign_imp<2>(V(42l), 101), ""); + test_constexpr_assign_imp<0>(V(42l), 101l); + test_constexpr_assign_imp<0>(V(nullptr), 101l); + test_constexpr_assign_imp<1>(V(42l), nullptr); + test_constexpr_assign_imp<2>(V(42l), 101); } -int main(int, char**) { +struct NonTrivialMoveAssign { + int i = 0; + constexpr NonTrivialMoveAssign(int ii) : i(ii) {} + constexpr NonTrivialMoveAssign(const NonTrivialMoveAssign& other) = default; + constexpr NonTrivialMoveAssign(NonTrivialMoveAssign&& other) : i(other.i) {} + constexpr NonTrivialMoveAssign& operator=(const NonTrivialMoveAssign&) = default; + constexpr NonTrivialMoveAssign& operator=(NonTrivialMoveAssign&& o) { + i = o.i; + return *this; + } + TEST_CONSTEXPR_CXX20 ~NonTrivialMoveAssign() = default; + friend constexpr bool operator==(const NonTrivialMoveAssign& x, const NonTrivialMoveAssign& y) { return x.i == y.i; } +}; + +TEST_CONSTEXPR_CXX20 void test_constexpr_move_assignment_non_trivial() { + using V = std::variant; + static_assert(!std::is_trivially_copyable::value); + static_assert(!std::is_trivially_move_assignable::value); + test_constexpr_assign_imp<0>(V(42l), 101l); + test_constexpr_assign_imp<0>(V(nullptr), 101l); + test_constexpr_assign_imp<1>(V(42l), nullptr); + test_constexpr_assign_imp<2>(V(42l), NonTrivialMoveAssign(5)); + test_constexpr_assign_imp<2>(V(NonTrivialMoveAssign(3)), NonTrivialMoveAssign(5)); +} + +void non_constexpr_test() { test_move_assignment_empty_empty(); test_move_assignment_non_empty_empty(); test_move_assignment_empty_non_empty(); - test_move_assignment_same_index(); - test_move_assignment_different_index(); + test_assignment_throw(); +} + +constexpr bool cxx17_constexpr_test() { test_move_assignment_sfinae(); test_move_assignment_noexcept(); - test_constexpr_move_assignment(); + test_constexpr_move_assignment_trivial(); + + return true; +} +TEST_CONSTEXPR_CXX20 bool cxx20_constexpr_test() { + test_move_assignment_same_index(); + test_move_assignment_different_index(); + test_constexpr_move_assignment_non_trivial(); + + return true; +} + +int main(int, char**) { + non_constexpr_test(); + cxx17_constexpr_test(); + cxx20_constexpr_test(); + + static_assert(cxx17_constexpr_test()); +#if TEST_STD_VER >= 20 + static_assert(cxx20_constexpr_test()); +#endif return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/copy.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/copy.pass.cpp index d1e5768f58d2..820ff9e0d1a9 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/copy.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/copy.pass.cpp @@ -22,30 +22,30 @@ #include "test_workarounds.h" struct NonT { - NonT(int v) : value(v) {} - NonT(const NonT &o) : value(o.value) {} + constexpr NonT(int v) : value(v) {} + constexpr NonT(const NonT& o) : value(o.value) {} int value; }; static_assert(!std::is_trivially_copy_constructible::value, ""); struct NoCopy { - NoCopy(const NoCopy &) = delete; + NoCopy(const NoCopy&) = delete; }; struct MoveOnly { - MoveOnly(const MoveOnly &) = delete; - MoveOnly(MoveOnly &&) = default; + MoveOnly(const MoveOnly&) = delete; + MoveOnly(MoveOnly&&) = default; }; struct MoveOnlyNT { - MoveOnlyNT(const MoveOnlyNT &) = delete; - MoveOnlyNT(MoveOnlyNT &&) {} + MoveOnlyNT(const MoveOnlyNT&) = delete; + MoveOnlyNT(MoveOnlyNT&&) {} }; struct NTCopy { constexpr NTCopy(int v) : value(v) {} - NTCopy(const NTCopy &that) : value(that.value) {} - NTCopy(NTCopy &&) = delete; + NTCopy(const NTCopy& that) : value(that.value) {} + NTCopy(NTCopy&&) = delete; int value; }; @@ -54,8 +54,8 @@ static_assert(std::is_copy_constructible::value, ""); struct TCopy { constexpr TCopy(int v) : value(v) {} - TCopy(TCopy const &) = default; - TCopy(TCopy &&) = delete; + TCopy(TCopy const&) = default; + TCopy(TCopy&&) = delete; int value; }; @@ -74,20 +74,21 @@ static_assert(std::is_trivially_copy_constructible::value, ""); struct MakeEmptyT { static int alive; MakeEmptyT() { ++alive; } - MakeEmptyT(const MakeEmptyT &) { + MakeEmptyT(const MakeEmptyT&) { ++alive; // Don't throw from the copy constructor since variant's assignment // operator performs a copy before committing to the assignment. } - MakeEmptyT(MakeEmptyT &&) { throw 42; } - MakeEmptyT &operator=(const MakeEmptyT &) { throw 42; } - MakeEmptyT &operator=(MakeEmptyT &&) { throw 42; } + MakeEmptyT(MakeEmptyT&&) { throw 42; } + MakeEmptyT& operator=(const MakeEmptyT&) { throw 42; } + MakeEmptyT& operator=(MakeEmptyT&&) { throw 42; } ~MakeEmptyT() { --alive; } }; int MakeEmptyT::alive = 0; -template void makeEmpty(Variant &v) { +template +void makeEmpty(Variant& v) { Variant v2(std::in_place_type); try { v = std::move(v2); @@ -98,7 +99,7 @@ template void makeEmpty(Variant &v) { } #endif // TEST_HAS_NO_EXCEPTIONS -void test_copy_ctor_sfinae() { +constexpr void test_copy_ctor_sfinae() { { using V = std::variant; static_assert(std::is_copy_constructible::value, ""); @@ -136,7 +137,7 @@ void test_copy_ctor_sfinae() { } } -void test_copy_ctor_basic() { +TEST_CONSTEXPR_CXX20 void test_copy_ctor_basic() { { std::variant v(std::in_place_index<0>, 42); std::variant v2 = v; @@ -214,21 +215,21 @@ void test_copy_ctor_valueless_by_exception() { using V = std::variant; V v1; makeEmpty(v1); - const V &cv1 = v1; + const V& cv1 = v1; V v(cv1); assert(v.valueless_by_exception()); #endif // TEST_HAS_NO_EXCEPTIONS } -template -constexpr bool test_constexpr_copy_ctor_imp(std::variant const& v) { +template +constexpr void test_constexpr_copy_ctor_imp(const T& v) { auto v2 = v; - return v2.index() == v.index() && - v2.index() == Idx && - std::get(v2) == std::get(v); + assert(v2.index() == v.index()); + assert(v2.index() == Idx); + assert(std::get(v2) == std::get(v)); } -void test_constexpr_copy_ctor() { +constexpr void test_constexpr_copy_ctor_trivial() { // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). using V = std::variant; #ifdef TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE @@ -237,18 +238,57 @@ void test_constexpr_copy_ctor() { static_assert(std::is_trivially_move_constructible::value, ""); static_assert(!std::is_copy_assignable::value, ""); static_assert(!std::is_move_assignable::value, ""); -#else // TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE +#else // TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE static_assert(std::is_trivially_copyable::value, ""); #endif // TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE - static_assert(test_constexpr_copy_ctor_imp<0>(V(42l)), ""); - static_assert(test_constexpr_copy_ctor_imp<1>(V(nullptr)), ""); - static_assert(test_constexpr_copy_ctor_imp<2>(V(101)), ""); + static_assert(std::is_trivially_copy_constructible::value, ""); + test_constexpr_copy_ctor_imp<0>(V(42l)); + test_constexpr_copy_ctor_imp<1>(V(nullptr)); + test_constexpr_copy_ctor_imp<2>(V(101)); } -int main(int, char**) { - test_copy_ctor_basic(); - test_copy_ctor_valueless_by_exception(); +struct NonTrivialCopyCtor { + int i = 0; + constexpr NonTrivialCopyCtor(int ii) : i(ii) {} + constexpr NonTrivialCopyCtor(const NonTrivialCopyCtor& other) : i(other.i) {} + constexpr NonTrivialCopyCtor(NonTrivialCopyCtor&& other) = default; + TEST_CONSTEXPR_CXX20 ~NonTrivialCopyCtor() = default; + friend constexpr bool operator==(const NonTrivialCopyCtor& x, const NonTrivialCopyCtor& y) { return x.i == y.i; } +}; + +TEST_CONSTEXPR_CXX20 void test_constexpr_copy_ctor_non_trivial() { + // Test !is_trivially_move_constructible + using V = std::variant; + static_assert(!std::is_trivially_copy_constructible::value, ""); + test_constexpr_copy_ctor_imp<0>(V(42l)); + test_constexpr_copy_ctor_imp<1>(V(NonTrivialCopyCtor(5))); + test_constexpr_copy_ctor_imp<2>(V(nullptr)); +} + +void non_constexpr_test() { test_copy_ctor_valueless_by_exception(); } + +constexpr bool cxx17_constexpr_test() { test_copy_ctor_sfinae(); - test_constexpr_copy_ctor(); + test_constexpr_copy_ctor_trivial(); + + return true; +} + +TEST_CONSTEXPR_CXX20 bool cxx20_constexpr_test() { + test_copy_ctor_basic(); + test_constexpr_copy_ctor_non_trivial(); + + return true; +} + +int main(int, char**) { + non_constexpr_test(); + cxx17_constexpr_test(); + cxx20_constexpr_test(); + + static_assert(cxx17_constexpr_test()); +#if TEST_STD_VER >= 20 + static_assert(cxx20_constexpr_test()); +#endif return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/default.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/default.pass.cpp index 40db038a0033..9abf4d758d84 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/default.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/default.pass.cpp @@ -17,6 +17,7 @@ #include #include #include +#include #include "test_macros.h" #include "variant_test_helpers.h" @@ -35,7 +36,7 @@ struct DefaultCtorThrows { }; #endif -void test_default_ctor_sfinae() { +constexpr void test_default_ctor_sfinae() { { using V = std::variant; static_assert(std::is_default_constructible::value, ""); @@ -46,7 +47,7 @@ void test_default_ctor_sfinae() { } } -void test_default_ctor_noexcept() { +constexpr void test_default_ctor_noexcept() { { using V = std::variant; static_assert(std::is_nothrow_default_constructible::value, ""); @@ -63,7 +64,7 @@ void test_default_ctor_throws() { try { V v; assert(false); - } catch (const int &ex) { + } catch (const int& ex) { assert(ex == 42); } catch (...) { assert(false); @@ -71,7 +72,7 @@ void test_default_ctor_throws() { #endif } -void test_default_ctor_basic() { +constexpr void test_default_ctor_basic() { { std::variant v; assert(v.index() == 0); @@ -107,11 +108,24 @@ void test_default_ctor_basic() { } } -int main(int, char**) { +constexpr void issue_86686() { +#if TEST_STD_VER >= 20 + static_assert(std::variant{}.index() == 0); +#endif +} + +constexpr bool test() { test_default_ctor_basic(); test_default_ctor_sfinae(); test_default_ctor_noexcept(); - test_default_ctor_throws(); + issue_86686(); + return true; +} + +int main(int, char**) { + test(); + test_default_ctor_throws(); + static_assert(test()); return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/move.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/move.pass.cpp index e2518fe29caf..4e8453c23cf5 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/move.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/move.pass.cpp @@ -23,31 +23,31 @@ #include "test_workarounds.h" struct ThrowsMove { - ThrowsMove(ThrowsMove &&) noexcept(false) {} + ThrowsMove(ThrowsMove&&) noexcept(false) {} }; struct NoCopy { - NoCopy(const NoCopy &) = delete; + NoCopy(const NoCopy&) = delete; }; struct MoveOnly { int value; - MoveOnly(int v) : value(v) {} - MoveOnly(const MoveOnly &) = delete; - MoveOnly(MoveOnly &&) = default; + constexpr MoveOnly(int v) : value(v) {} + MoveOnly(const MoveOnly&) = delete; + MoveOnly(MoveOnly&&) = default; }; struct MoveOnlyNT { int value; - MoveOnlyNT(int v) : value(v) {} - MoveOnlyNT(const MoveOnlyNT &) = delete; - MoveOnlyNT(MoveOnlyNT &&other) : value(other.value) { other.value = -1; } + constexpr MoveOnlyNT(int v) : value(v) {} + MoveOnlyNT(const MoveOnlyNT&) = delete; + constexpr MoveOnlyNT(MoveOnlyNT&& other) : value(other.value) { other.value = -1; } }; struct NTMove { constexpr NTMove(int v) : value(v) {} - NTMove(const NTMove &) = delete; - NTMove(NTMove &&that) : value(that.value) { that.value = -1; } + NTMove(const NTMove&) = delete; + NTMove(NTMove&& that) : value(that.value) { that.value = -1; } int value; }; @@ -56,8 +56,8 @@ static_assert(std::is_move_constructible::value, ""); struct TMove { constexpr TMove(int v) : value(v) {} - TMove(const TMove &) = delete; - TMove(TMove &&) = default; + TMove(const TMove&) = delete; + TMove(TMove&&) = default; int value; }; @@ -76,20 +76,21 @@ static_assert(std::is_trivially_move_constructible::value, ""); struct MakeEmptyT { static int alive; MakeEmptyT() { ++alive; } - MakeEmptyT(const MakeEmptyT &) { + MakeEmptyT(const MakeEmptyT&) { ++alive; // Don't throw from the copy constructor since variant's assignment // operator performs a copy before committing to the assignment. } - MakeEmptyT(MakeEmptyT &&) { throw 42; } - MakeEmptyT &operator=(const MakeEmptyT &) { throw 42; } - MakeEmptyT &operator=(MakeEmptyT &&) { throw 42; } + MakeEmptyT(MakeEmptyT&&) { throw 42; } + MakeEmptyT& operator=(const MakeEmptyT&) { throw 42; } + MakeEmptyT& operator=(MakeEmptyT&&) { throw 42; } ~MakeEmptyT() { --alive; } }; int MakeEmptyT::alive = 0; -template void makeEmpty(Variant &v) { +template +void makeEmpty(Variant& v) { Variant v2(std::in_place_type); try { v = std::move(v2); @@ -100,7 +101,7 @@ template void makeEmpty(Variant &v) { } #endif // TEST_HAS_NO_EXCEPTIONS -void test_move_noexcept() { +constexpr void test_move_noexcept() { { using V = std::variant; static_assert(std::is_nothrow_move_constructible::value, ""); @@ -119,7 +120,7 @@ void test_move_noexcept() { } } -void test_move_ctor_sfinae() { +constexpr void test_move_ctor_sfinae() { { using V = std::variant; static_assert(std::is_move_constructible::value, ""); @@ -158,9 +159,12 @@ void test_move_ctor_sfinae() { } template -struct Result { std::size_t index; T value; }; +struct Result { + std::size_t index; + T value; +}; -void test_move_ctor_basic() { +TEST_CONSTEXPR_CXX20 void test_move_ctor_basic() { { std::variant v(std::in_place_index<0>, 42); std::variant v2 = std::move(v); @@ -289,16 +293,16 @@ void test_move_ctor_valueless_by_exception() { #endif // TEST_HAS_NO_EXCEPTIONS } -template -constexpr bool test_constexpr_ctor_imp(std::variant const& v) { +template +constexpr void test_constexpr_ctor_imp(const T& v) { auto copy = v; - auto v2 = std::move(copy); - return v2.index() == v.index() && - v2.index() == Idx && - std::get(v2) == std::get(v); + auto v2 = std::move(copy); + assert(v2.index() == v.index()); + assert(v2.index() == Idx); + assert(std::get(v2) == std::get(v)); } -void test_constexpr_move_ctor() { +constexpr void test_constexpr_move_ctor_trivial() { // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). using V = std::variant; #ifdef TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE @@ -307,21 +311,58 @@ void test_constexpr_move_ctor() { static_assert(std::is_trivially_move_constructible::value, ""); static_assert(!std::is_copy_assignable::value, ""); static_assert(!std::is_move_assignable::value, ""); -#else // TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE +#else // TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE static_assert(std::is_trivially_copyable::value, ""); #endif // TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE static_assert(std::is_trivially_move_constructible::value, ""); - static_assert(test_constexpr_ctor_imp<0>(V(42l)), ""); - static_assert(test_constexpr_ctor_imp<1>(V(nullptr)), ""); - static_assert(test_constexpr_ctor_imp<2>(V(101)), ""); + test_constexpr_ctor_imp<0>(V(42l)); + test_constexpr_ctor_imp<1>(V(nullptr)); + test_constexpr_ctor_imp<2>(V(101)); } -int main(int, char**) { - test_move_ctor_basic(); - test_move_ctor_valueless_by_exception(); +struct NonTrivialMoveCtor { + int i = 0; + constexpr NonTrivialMoveCtor(int ii) : i(ii) {} + constexpr NonTrivialMoveCtor(const NonTrivialMoveCtor& other) = default; + constexpr NonTrivialMoveCtor(NonTrivialMoveCtor&& other) : i(other.i) {} + TEST_CONSTEXPR_CXX20 ~NonTrivialMoveCtor() = default; + friend constexpr bool operator==(const NonTrivialMoveCtor& x, const NonTrivialMoveCtor& y) { return x.i == y.i; } +}; + +TEST_CONSTEXPR_CXX20 void test_constexpr_move_ctor_non_trivial() { + using V = std::variant; + static_assert(!std::is_trivially_move_constructible::value, ""); + test_constexpr_ctor_imp<0>(V(42l)); + test_constexpr_ctor_imp<1>(V(NonTrivialMoveCtor(5))); + test_constexpr_ctor_imp<2>(V(nullptr)); +} + +void non_constexpr_test() { test_move_ctor_valueless_by_exception(); } + +constexpr bool cxx17_constexpr_test() { test_move_noexcept(); test_move_ctor_sfinae(); - test_constexpr_move_ctor(); + test_constexpr_move_ctor_trivial(); + + return true; +} + +TEST_CONSTEXPR_CXX20 bool cxx20_constexpr_test() { + test_move_ctor_basic(); + test_constexpr_move_ctor_non_trivial(); + + return true; +} + +int main(int, char**) { + non_constexpr_test(); + cxx17_constexpr_test(); + cxx20_constexpr_test(); + + static_assert(cxx17_constexpr_test()); +#if TEST_STD_VER >= 20 + static_assert(cxx20_constexpr_test()); +#endif return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.dtor/dtor.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.dtor/dtor.pass.cpp index 2e026038c97a..53c5283b2edc 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.dtor/dtor.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.dtor/dtor.pass.cpp @@ -21,55 +21,76 @@ #include "test_macros.h" struct NonTDtor { - static int count; - NonTDtor() = default; - ~NonTDtor() { ++count; } + int* count; + constexpr NonTDtor(int* a, int*) : count(a) {} + TEST_CONSTEXPR_CXX20 ~NonTDtor() { ++*count; } }; -int NonTDtor::count = 0; static_assert(!std::is_trivially_destructible::value, ""); struct NonTDtor1 { - static int count; - NonTDtor1() = default; - ~NonTDtor1() { ++count; } + int* count; + constexpr NonTDtor1(int*, int* b) : count(b) {} + TEST_CONSTEXPR_CXX20 ~NonTDtor1() { ++*count; } }; -int NonTDtor1::count = 0; static_assert(!std::is_trivially_destructible::value, ""); struct TDtor { - TDtor(const TDtor &) {} // non-trivial copy - ~TDtor() = default; + constexpr TDtor() = default; + constexpr TDtor(const TDtor&) {} // non-trivial copy + TEST_CONSTEXPR_CXX20 ~TDtor() = default; }; static_assert(!std::is_trivially_copy_constructible::value, ""); static_assert(std::is_trivially_destructible::value, ""); -int main(int, char**) { +TEST_CONSTEXPR_CXX20 bool test() { { using V = std::variant; static_assert(std::is_trivially_destructible::value, ""); + [[maybe_unused]] V v(std::in_place_index<2>); } { using V = std::variant; static_assert(!std::is_trivially_destructible::value, ""); { - V v(std::in_place_index<0>); - assert(NonTDtor::count == 0); - assert(NonTDtor1::count == 0); + int count0 = 0; + int count1 = 0; + { + V v(std::in_place_index<0>, &count0, &count1); + assert(count0 == 0); + assert(count1 == 0); + } + assert(count0 == 1); + assert(count1 == 0); + } + { + int count0 = 0; + int count1 = 0; + { V v(std::in_place_index<1>); } + assert(count0 == 0); + assert(count1 == 0); } - assert(NonTDtor::count == 1); - assert(NonTDtor1::count == 0); - NonTDtor::count = 0; - { V v(std::in_place_index<1>); } - assert(NonTDtor::count == 0); - assert(NonTDtor1::count == 0); { - V v(std::in_place_index<2>); - assert(NonTDtor::count == 0); - assert(NonTDtor1::count == 0); + int count0 = 0; + int count1 = 0; + { + V v(std::in_place_index<2>, &count0, &count1); + assert(count0 == 0); + assert(count1 == 0); + } + assert(count0 == 0); + assert(count1 == 1); } - assert(NonTDtor::count == 0); - assert(NonTDtor1::count == 1); } + return true; +} + +int main(int, char**) { + test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif + return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp index 2fe9033dd816..f98d968f0eae 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp @@ -26,8 +26,8 @@ #include "variant_test_helpers.h" template -constexpr auto test_emplace_exists_imp(int) -> decltype( - std::declval().template emplace(std::declval()...), true) { +constexpr auto test_emplace_exists_imp(int) + -> decltype(std::declval().template emplace(std::declval()...), true) { return true; } @@ -36,28 +36,32 @@ constexpr auto test_emplace_exists_imp(long) -> bool { return false; } -template constexpr bool emplace_exists() { +template +constexpr bool emplace_exists() { return test_emplace_exists_imp(0); } -void test_emplace_sfinae() { +constexpr void test_emplace_sfinae() { { - using V = std::variant; + using V = std::variant; static_assert(emplace_exists(), ""); static_assert(emplace_exists(), ""); - static_assert(!emplace_exists(), - "cannot construct"); + static_assert(!emplace_exists(), "cannot construct"); static_assert(emplace_exists(), ""); - static_assert(emplace_exists(), ""); - static_assert(!emplace_exists(), ""); + static_assert(emplace_exists(), ""); + static_assert(!emplace_exists(), ""); static_assert(!emplace_exists(), "cannot construct"); - static_assert(emplace_exists(), ""); - static_assert(emplace_exists(), ""); + static_assert(emplace_exists(), ""); + static_assert(emplace_exists(), ""); static_assert(!emplace_exists(), "cannot construct"); } } -void test_basic() { +struct NoCtor { + NoCtor() = delete; +}; + +TEST_CONSTEXPR_CXX20 void test_basic() { { using V = std::variant; V v(42); @@ -70,9 +74,9 @@ void test_basic() { assert(std::get<0>(v) == 42); assert(&ref2 == &std::get<0>(v)); } + { - using V = - std::variant; + using V = std::variant; const int x = 100; V v(std::in_place_index<0>, -1); // default emplace a value @@ -92,9 +96,19 @@ void test_basic() { } } -int main(int, char**) { +TEST_CONSTEXPR_CXX20 bool test() { test_basic(); test_emplace_sfinae(); + return true; +} + +int main(int, char**) { + test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif + return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_init_list_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_init_list_args.pass.cpp index 9068aacc4359..4c635570bd56 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_init_list_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_init_list_args.pass.cpp @@ -32,13 +32,12 @@ struct InitList { struct InitListArg { std::size_t size; int value; - constexpr InitListArg(std::initializer_list il, int v) - : size(il.size()), value(v) {} + constexpr InitListArg(std::initializer_list il, int v) : size(il.size()), value(v) {} }; template -constexpr auto test_emplace_exists_imp(int) -> decltype( - std::declval().template emplace(std::declval()...), true) { +constexpr auto test_emplace_exists_imp(int) + -> decltype(std::declval().template emplace(std::declval()...), true) { return true; } @@ -47,13 +46,13 @@ constexpr auto test_emplace_exists_imp(long) -> bool { return false; } -template constexpr bool emplace_exists() { +template +constexpr bool emplace_exists() { return test_emplace_exists_imp(0); } -void test_emplace_sfinae() { - using V = - std::variant; +constexpr void test_emplace_sfinae() { + using V = std::variant; using IL = std::initializer_list; static_assert(!emplace_exists(), "no such constructor"); static_assert(emplace_exists(), ""); @@ -65,8 +64,12 @@ void test_emplace_sfinae() { static_assert(!emplace_exists(), "too many args"); } -void test_basic() { - using V = std::variant; +struct NoCtor { + NoCtor() = delete; +}; + +TEST_CONSTEXPR_CXX20 void test_basic() { + using V = std::variant; V v; auto& ref1 = v.emplace<1>({1, 2, 3}); static_assert(std::is_same_v, ""); @@ -83,9 +86,19 @@ void test_basic() { assert(&ref3 == &std::get<1>(v)); } -int main(int, char**) { +TEST_CONSTEXPR_CXX20 bool test() { test_basic(); test_emplace_sfinae(); + return true; +} + +int main(int, char**) { + test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif + return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp index 4e9f67775d10..c2ed54d8a625 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp @@ -25,8 +25,8 @@ #include "variant_test_helpers.h" template -constexpr auto test_emplace_exists_imp(int) -> decltype( - std::declval().template emplace(std::declval()...), true) { +constexpr auto test_emplace_exists_imp(int) + -> decltype(std::declval().template emplace(std::declval()...), true) { return true; } @@ -35,28 +35,32 @@ constexpr auto test_emplace_exists_imp(long) -> bool { return false; } -template constexpr bool emplace_exists() { +template +constexpr bool emplace_exists() { return test_emplace_exists_imp(0); } -void test_emplace_sfinae() { +constexpr void test_emplace_sfinae() { { - using V = std::variant; + using V = std::variant; static_assert(emplace_exists(), ""); static_assert(emplace_exists(), ""); - static_assert(!emplace_exists(), - "cannot construct"); - static_assert(emplace_exists(), ""); - static_assert(!emplace_exists(), "cannot construct"); - static_assert(emplace_exists(), ""); - static_assert(!emplace_exists(), ""); - static_assert(emplace_exists(), ""); - static_assert(emplace_exists(), ""); + static_assert(!emplace_exists(), "cannot construct"); + static_assert(emplace_exists(), ""); + static_assert(!emplace_exists(), "cannot construct"); + static_assert(emplace_exists(), ""); + static_assert(!emplace_exists(), ""); + static_assert(emplace_exists(), ""); + static_assert(emplace_exists(), ""); static_assert(!emplace_exists(), "cannot construct"); } } -void test_basic() { +struct NoCtor { + NoCtor() = delete; +}; + +TEST_CONSTEXPR_CXX20 void test_basic() { { using V = std::variant; V v(42); @@ -70,8 +74,7 @@ void test_basic() { assert(&ref2 == &std::get<0>(v)); } { - using V = - std::variant; + using V = std::variant; const int x = 100; V v(std::in_place_type, -1); // default emplace a value @@ -79,8 +82,8 @@ void test_basic() { static_assert(std::is_same_v, ""); assert(std::get<1>(v) == 0); assert(&ref1 == &std::get<1>(v)); - auto& ref2 = v.emplace(&x); - static_assert(std::is_same_v, ""); + auto& ref2 = v.emplace(&x); + static_assert(std::is_same_v, ""); assert(std::get<2>(v) == &x); assert(&ref2 == &std::get<2>(v)); // emplace with multiple args @@ -91,9 +94,19 @@ void test_basic() { } } -int main(int, char**) { +TEST_CONSTEXPR_CXX20 bool test() { test_basic(); test_emplace_sfinae(); + return true; +} + +int main(int, char**) { + test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif + return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_init_list_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_init_list_args.pass.cpp index 74d834b9b345..644f2418b925 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_init_list_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_init_list_args.pass.cpp @@ -32,13 +32,12 @@ struct InitList { struct InitListArg { std::size_t size; int value; - constexpr InitListArg(std::initializer_list il, int v) - : size(il.size()), value(v) {} + constexpr InitListArg(std::initializer_list il, int v) : size(il.size()), value(v) {} }; template -constexpr auto test_emplace_exists_imp(int) -> decltype( - std::declval().template emplace(std::declval()...), true) { +constexpr auto test_emplace_exists_imp(int) + -> decltype(std::declval().template emplace(std::declval()...), true) { return true; } @@ -47,13 +46,13 @@ constexpr auto test_emplace_exists_imp(long) -> bool { return false; } -template constexpr bool emplace_exists() { +template +constexpr bool emplace_exists() { return test_emplace_exists_imp(0); } -void test_emplace_sfinae() { - using V = - std::variant; +constexpr void test_emplace_sfinae() { + using V = std::variant; using IL = std::initializer_list; static_assert(emplace_exists(), ""); static_assert(!emplace_exists(), "args don't match"); @@ -61,31 +60,44 @@ void test_emplace_sfinae() { static_assert(emplace_exists(), ""); static_assert(!emplace_exists(), "args don't match"); static_assert(!emplace_exists(), "too few args"); - static_assert(!emplace_exists(), - "too many args"); + static_assert(!emplace_exists(), "too many args"); } -void test_basic() { - using V = std::variant; +struct NoCtor { + NoCtor() = delete; +}; + +TEST_CONSTEXPR_CXX20 void test_basic() { + using V = std::variant; V v; auto& ref1 = v.emplace({1, 2, 3}); - static_assert(std::is_same_v, ""); + static_assert(std::is_same_v, ""); assert(std::get(v).size == 3); assert(&ref1 == &std::get(v)); auto& ref2 = v.emplace({1, 2, 3, 4}, 42); - static_assert(std::is_same_v, ""); + static_assert(std::is_same_v, ""); assert(std::get(v).size == 4); assert(std::get(v).value == 42); assert(&ref2 == &std::get(v)); auto& ref3 = v.emplace({1}); - static_assert(std::is_same_v, ""); + static_assert(std::is_same_v, ""); assert(std::get(v).size == 1); assert(&ref3 == &std::get(v)); } -int main(int, char**) { +TEST_CONSTEXPR_CXX20 bool test() { test_basic(); test_emplace_sfinae(); + return true; +} + +int main(int, char**) { + test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif + return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.swap/swap.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.swap/swap.pass.cpp index 1802bc4670bb..db05691c5581 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.swap/swap.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.swap/swap.pass.cpp @@ -25,37 +25,39 @@ #include "variant_test_helpers.h" struct NotSwappable {}; -void swap(NotSwappable &, NotSwappable &) = delete; +void swap(NotSwappable&, NotSwappable&) = delete; struct NotCopyable { - NotCopyable() = default; - NotCopyable(const NotCopyable &) = delete; - NotCopyable &operator=(const NotCopyable &) = delete; + NotCopyable() = default; + NotCopyable(const NotCopyable&) = delete; + NotCopyable& operator=(const NotCopyable&) = delete; }; struct NotCopyableWithSwap { - NotCopyableWithSwap() = default; - NotCopyableWithSwap(const NotCopyableWithSwap &) = delete; - NotCopyableWithSwap &operator=(const NotCopyableWithSwap &) = delete; + NotCopyableWithSwap() = default; + NotCopyableWithSwap(const NotCopyableWithSwap&) = delete; + NotCopyableWithSwap& operator=(const NotCopyableWithSwap&) = delete; }; -void swap(NotCopyableWithSwap &, NotCopyableWithSwap) {} +constexpr void swap(NotCopyableWithSwap&, NotCopyableWithSwap) {} struct NotMoveAssignable { - NotMoveAssignable() = default; - NotMoveAssignable(NotMoveAssignable &&) = default; - NotMoveAssignable &operator=(NotMoveAssignable &&) = delete; + NotMoveAssignable() = default; + NotMoveAssignable(NotMoveAssignable&&) = default; + NotMoveAssignable& operator=(NotMoveAssignable&&) = delete; }; struct NotMoveAssignableWithSwap { - NotMoveAssignableWithSwap() = default; - NotMoveAssignableWithSwap(NotMoveAssignableWithSwap &&) = default; - NotMoveAssignableWithSwap &operator=(NotMoveAssignableWithSwap &&) = delete; + NotMoveAssignableWithSwap() = default; + NotMoveAssignableWithSwap(NotMoveAssignableWithSwap&&) = default; + NotMoveAssignableWithSwap& operator=(NotMoveAssignableWithSwap&&) = delete; }; -void swap(NotMoveAssignableWithSwap &, NotMoveAssignableWithSwap &) noexcept {} +constexpr void swap(NotMoveAssignableWithSwap&, NotMoveAssignableWithSwap&) noexcept {} -template void do_throw() {} +template +constexpr void do_throw() {} -template <> void do_throw() { +template <> +void do_throw() { #ifndef TEST_HAS_NO_EXCEPTIONS throw 42; #else @@ -63,60 +65,49 @@ template <> void do_throw() { #endif } -template +template struct NothrowTypeImp { - static int move_called; - static int move_assign_called; - static int swap_called; - static void reset() { move_called = move_assign_called = swap_called = 0; } - NothrowTypeImp() = default; - explicit NothrowTypeImp(int v) : value(v) {} - NothrowTypeImp(const NothrowTypeImp &o) noexcept(NT_Copy) : value(o.value) { - assert(false); - } // never called by test - NothrowTypeImp(NothrowTypeImp &&o) noexcept(NT_Move) : value(o.value) { - ++move_called; + int value; + int* move_called; + int* move_assign_called; + int* swap_called; + + constexpr NothrowTypeImp(int v, int* mv_ctr, int* mv_assign, int* swap) + : value(v), move_called(mv_ctr), move_assign_called(mv_assign), swap_called(swap) {} + + NothrowTypeImp(const NothrowTypeImp& o) noexcept(NT_Copy) : value(o.value) { assert(false); } // never called by test + + constexpr NothrowTypeImp(NothrowTypeImp&& o) noexcept(NT_Move) + : value(o.value), + move_called(o.move_called), + move_assign_called(o.move_assign_called), + swap_called(o.swap_called) { + ++*move_called; do_throw(); o.value = -1; } - NothrowTypeImp &operator=(const NothrowTypeImp &) noexcept(NT_CopyAssign) { + + NothrowTypeImp& operator=(const NothrowTypeImp&) noexcept(NT_CopyAssign) { assert(false); return *this; } // never called by the tests - NothrowTypeImp &operator=(NothrowTypeImp &&o) noexcept(NT_MoveAssign) { - ++move_assign_called; + + constexpr NothrowTypeImp& operator=(NothrowTypeImp&& o) noexcept(NT_MoveAssign) { + ++*move_assign_called; do_throw(); - value = o.value; + value = o.value; o.value = -1; return *this; } - int value; }; -template -int NothrowTypeImp::move_called = 0; -template -int NothrowTypeImp::move_assign_called = 0; -template -int NothrowTypeImp::swap_called = 0; - -template -void swap(NothrowTypeImp &lhs, - NothrowTypeImp &rhs) noexcept(NT_Swap) { - lhs.swap_called++; + +template +constexpr void +swap(NothrowTypeImp& lhs, + NothrowTypeImp& rhs) noexcept(NT_Swap) { + ++*lhs.swap_called; do_throw(); - int tmp = lhs.value; - lhs.value = rhs.value; - rhs.value = tmp; + std::swap(lhs.value, rhs.value); } // throwing copy, nothrow move ctor/assign, no swap provided @@ -124,53 +115,42 @@ using NothrowMoveable = NothrowTypeImp; // throwing copy and move assign, nothrow move ctor, no swap provided using NothrowMoveCtor = NothrowTypeImp; // nothrow move ctor, throwing move assignment, swap provided -using NothrowMoveCtorWithThrowingSwap = - NothrowTypeImp; +using NothrowMoveCtorWithThrowingSwap = NothrowTypeImp; // throwing move ctor, nothrow move assignment, no swap provided -using ThrowingMoveCtor = - NothrowTypeImp; +using ThrowingMoveCtor = NothrowTypeImp; // throwing special members, nothrowing swap -using ThrowingTypeWithNothrowSwap = - NothrowTypeImp; -using NothrowTypeWithThrowingSwap = - NothrowTypeImp; +using ThrowingTypeWithNothrowSwap = NothrowTypeImp; +using NothrowTypeWithThrowingSwap = NothrowTypeImp; // throwing move assign with nothrow move and nothrow swap -using ThrowingMoveAssignNothrowMoveCtorWithSwap = - NothrowTypeImp; +using ThrowingMoveAssignNothrowMoveCtorWithSwap = NothrowTypeImp; // throwing move assign with nothrow move but no swap. -using ThrowingMoveAssignNothrowMoveCtor = - NothrowTypeImp; +using ThrowingMoveAssignNothrowMoveCtor = NothrowTypeImp; struct NonThrowingNonNoexceptType { - static int move_called; - static void reset() { move_called = 0; } - NonThrowingNonNoexceptType() = default; - NonThrowingNonNoexceptType(int v) : value(v) {} - NonThrowingNonNoexceptType(NonThrowingNonNoexceptType &&o) noexcept(false) - : value(o.value) { - ++move_called; + int value; + int* move_called; + constexpr NonThrowingNonNoexceptType(int v, int* mv_called) : value(v), move_called(mv_called) {} + constexpr NonThrowingNonNoexceptType(NonThrowingNonNoexceptType&& o) noexcept(false) + : value(o.value), move_called(o.move_called) { + ++*move_called; o.value = -1; } - NonThrowingNonNoexceptType & - operator=(NonThrowingNonNoexceptType &&) noexcept(false) { + NonThrowingNonNoexceptType& operator=(NonThrowingNonNoexceptType&&) noexcept(false) { assert(false); // never called by the tests. return *this; } - int value; }; -int NonThrowingNonNoexceptType::move_called = 0; struct ThrowsOnSecondMove { int value; int move_count; ThrowsOnSecondMove(int v) : value(v), move_count(0) {} - ThrowsOnSecondMove(ThrowsOnSecondMove &&o) noexcept(false) - : value(o.value), move_count(o.move_count + 1) { + ThrowsOnSecondMove(ThrowsOnSecondMove&& o) noexcept(false) : value(o.value), move_count(o.move_count + 1) { if (move_count == 2) do_throw(); o.value = -1; } - ThrowsOnSecondMove &operator=(ThrowsOnSecondMove &&) { + ThrowsOnSecondMove& operator=(ThrowsOnSecondMove&&) { assert(false); // not called by test return *this; } @@ -224,265 +204,293 @@ void test_swap_valueless_by_exception() { #endif } -void test_swap_same_alternative() { +TEST_CONSTEXPR_CXX20 void test_swap_same_alternative() { { - using T = ThrowingTypeWithNothrowSwap; - using V = std::variant; - T::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<0>, 100); + using V = std::variant; + int move_called = 0; + int move_assign_called = 0; + int swap_called = 0; + V v1(std::in_place_index<0>, 42, &move_called, &move_assign_called, &swap_called); + V v2(std::in_place_index<0>, 100, &move_called, &move_assign_called, &swap_called); v1.swap(v2); - assert(T::swap_called == 1); + assert(swap_called == 1); assert(std::get<0>(v1).value == 100); assert(std::get<0>(v2).value == 42); swap(v1, v2); - assert(T::swap_called == 2); + assert(swap_called == 2); assert(std::get<0>(v1).value == 42); assert(std::get<0>(v2).value == 100); + + assert(move_called == 0); + assert(move_assign_called == 0); } { - using T = NothrowMoveable; - using V = std::variant; - T::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<0>, 100); + using V = std::variant; + int move_called = 0; + int move_assign_called = 0; + int swap_called = 0; + V v1(std::in_place_index<0>, 42, &move_called, &move_assign_called, &swap_called); + V v2(std::in_place_index<0>, 100, &move_called, &move_assign_called, &swap_called); v1.swap(v2); - assert(T::swap_called == 0); - assert(T::move_called == 1); - assert(T::move_assign_called == 2); + assert(swap_called == 0); + assert(move_called == 1); + assert(move_assign_called == 2); assert(std::get<0>(v1).value == 100); assert(std::get<0>(v2).value == 42); - T::reset(); + + move_called = 0; + move_assign_called = 0; + swap_called = 0; + swap(v1, v2); - assert(T::swap_called == 0); - assert(T::move_called == 1); - assert(T::move_assign_called == 2); + assert(swap_called == 0); + assert(move_called == 1); + assert(move_assign_called == 2); assert(std::get<0>(v1).value == 42); assert(std::get<0>(v2).value == 100); } +} + +void test_swap_same_alternative_throws(){ #ifndef TEST_HAS_NO_EXCEPTIONS - { - using T = NothrowTypeWithThrowingSwap; - using V = std::variant; - T::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<0>, 100); - try { - v1.swap(v2); - assert(false); - } catch (int) { - } - assert(T::swap_called == 1); - assert(T::move_called == 0); - assert(T::move_assign_called == 0); - assert(std::get<0>(v1).value == 42); - assert(std::get<0>(v2).value == 100); - } - { - using T = ThrowingMoveCtor; - using V = std::variant; - T::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<0>, 100); - try { - v1.swap(v2); - assert(false); - } catch (int) { - } - assert(T::move_called == 1); // call threw - assert(T::move_assign_called == 0); - assert(std::get<0>(v1).value == - 42); // throw happened before v1 was moved from - assert(std::get<0>(v2).value == 100); + {using V = std::variant; +int move_called = 0; +int move_assign_called = 0; +int swap_called = 0; +V v1(std::in_place_index<0>, 42, &move_called, &move_assign_called, &swap_called); +V v2(std::in_place_index<0>, 100, &move_called, &move_assign_called, &swap_called); +try { + v1.swap(v2); + assert(false); +} catch (int) { +} +assert(swap_called == 1); +assert(move_called == 0); +assert(move_assign_called == 0); +assert(std::get<0>(v1).value == 42); +assert(std::get<0>(v2).value == 100); +} + +{ + using V = std::variant; + int move_called = 0; + int move_assign_called = 0; + int swap_called = 0; + V v1(std::in_place_index<0>, 42, &move_called, &move_assign_called, &swap_called); + V v2(std::in_place_index<0>, 100, &move_called, &move_assign_called, &swap_called); + try { + v1.swap(v2); + assert(false); + } catch (int) { } - { - using T = ThrowingMoveAssignNothrowMoveCtor; - using V = std::variant; - T::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<0>, 100); - try { - v1.swap(v2); - assert(false); - } catch (int) { - } - assert(T::move_called == 1); - assert(T::move_assign_called == 1); // call threw and didn't complete - assert(std::get<0>(v1).value == -1); // v1 was moved from - assert(std::get<0>(v2).value == 100); + assert(move_called == 1); // call threw + assert(move_assign_called == 0); + assert(swap_called == 0); + assert(std::get<0>(v1).value == 42); // throw happened before v1 was moved from + assert(std::get<0>(v2).value == 100); +} +{ + using V = std::variant; + int move_called = 0; + int move_assign_called = 0; + int swap_called = 0; + V v1(std::in_place_index<0>, 42, &move_called, &move_assign_called, &swap_called); + V v2(std::in_place_index<0>, 100, &move_called, &move_assign_called, &swap_called); + try { + v1.swap(v2); + assert(false); + } catch (int) { } + assert(move_called == 1); + assert(move_assign_called == 1); // call threw and didn't complete + assert(swap_called == 0); + assert(std::get<0>(v1).value == -1); // v1 was moved from + assert(std::get<0>(v2).value == 100); +} #endif } -void test_swap_different_alternatives() { +TEST_CONSTEXPR_CXX20 void test_swap_different_alternatives() { { - using T = NothrowMoveCtorWithThrowingSwap; - using V = std::variant; - T::reset(); - V v1(std::in_place_index<0>, 42); + using V = std::variant; + int move_called = 0; + int move_assign_called = 0; + int swap_called = 0; + V v1(std::in_place_index<0>, 42, &move_called, &move_assign_called, &swap_called); V v2(std::in_place_index<1>, 100); v1.swap(v2); - assert(T::swap_called == 0); + assert(swap_called == 0); // The libc++ implementation double copies the argument, and not // the variant swap is called on. - LIBCPP_ASSERT(T::move_called == 1); - assert(T::move_called <= 2); - assert(T::move_assign_called == 0); + LIBCPP_ASSERT(move_called == 1); + assert(move_called <= 2); + assert(move_assign_called == 0); assert(std::get<1>(v1) == 100); assert(std::get<0>(v2).value == 42); - T::reset(); + + move_called = 0; + move_assign_called = 0; + swap_called = 0; + swap(v1, v2); - assert(T::swap_called == 0); - LIBCPP_ASSERT(T::move_called == 2); - assert(T::move_called <= 2); - assert(T::move_assign_called == 0); + assert(swap_called == 0); + LIBCPP_ASSERT(move_called == 2); + assert(move_called <= 2); + assert(move_assign_called == 0); assert(std::get<0>(v1).value == 42); assert(std::get<1>(v2) == 100); } +} + +void test_swap_different_alternatives_throws() { #ifndef TEST_HAS_NO_EXCEPTIONS { - using T1 = ThrowingTypeWithNothrowSwap; - using T2 = NonThrowingNonNoexceptType; - using V = std::variant; - T1::reset(); - T2::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<1>, 100); + using V = std::variant; + int move_called1 = 0; + int move_assign_called1 = 0; + int swap_called1 = 0; + int move_called2 = 0; + V v1(std::in_place_index<0>, 42, &move_called1, &move_assign_called1, &swap_called1); + V v2(std::in_place_index<1>, 100, &move_called2); try { v1.swap(v2); assert(false); } catch (int) { } - assert(T1::swap_called == 0); - assert(T1::move_called == 1); // throws - assert(T1::move_assign_called == 0); + assert(swap_called1 == 0); + assert(move_called1 == 1); // throws + assert(move_assign_called1 == 0); // FIXME: libc++ shouldn't move from T2 here. - LIBCPP_ASSERT(T2::move_called == 1); - assert(T2::move_called <= 1); + LIBCPP_ASSERT(move_called2 == 1); + assert(move_called2 <= 1); assert(std::get<0>(v1).value == 42); - if (T2::move_called != 0) + if (move_called2 != 0) assert(v2.valueless_by_exception()); else assert(std::get<1>(v2).value == 100); } { - using T1 = NonThrowingNonNoexceptType; - using T2 = ThrowingTypeWithNothrowSwap; - using V = std::variant; - T1::reset(); - T2::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<1>, 100); + using V = std::variant; + int move_called1 = 0; + int move_called2 = 0; + int move_assign_called2 = 0; + int swap_called2 = 0; + V v1(std::in_place_index<0>, 42, &move_called1); + V v2(std::in_place_index<1>, 100, &move_called2, &move_assign_called2, &swap_called2); try { v1.swap(v2); assert(false); } catch (int) { } - LIBCPP_ASSERT(T1::move_called == 0); - assert(T1::move_called <= 1); - assert(T2::swap_called == 0); - assert(T2::move_called == 1); // throws - assert(T2::move_assign_called == 0); - if (T1::move_called != 0) + LIBCPP_ASSERT(move_called1 == 0); + assert(move_called1 <= 1); + assert(swap_called2 == 0); + assert(move_called2 == 1); // throws + assert(move_assign_called2 == 0); + if (move_called1 != 0) assert(v1.valueless_by_exception()); else assert(std::get<0>(v1).value == 42); assert(std::get<1>(v2).value == 100); } // FIXME: The tests below are just very libc++ specific -#ifdef _LIBCPP_VERSION +# ifdef _LIBCPP_VERSION { - using T1 = ThrowsOnSecondMove; - using T2 = NonThrowingNonNoexceptType; - using V = std::variant; - T2::reset(); + using V = std::variant; + int move_called = 0; V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<1>, 100); + V v2(std::in_place_index<1>, 100, &move_called); v1.swap(v2); - assert(T2::move_called == 2); + assert(move_called == 2); assert(std::get<1>(v1).value == 100); assert(std::get<0>(v2).value == 42); assert(std::get<0>(v2).move_count == 1); } { - using T1 = NonThrowingNonNoexceptType; - using T2 = ThrowsOnSecondMove; - using V = std::variant; - T1::reset(); - V v1(std::in_place_index<0>, 42); + using V = std::variant; + int move_called = 0; + V v1(std::in_place_index<0>, 42, &move_called); V v2(std::in_place_index<1>, 100); try { v1.swap(v2); assert(false); } catch (int) { } - assert(T1::move_called == 1); + assert(move_called == 1); assert(v1.valueless_by_exception()); assert(std::get<0>(v2).value == 42); } -#endif -// testing libc++ extension. If either variant stores a nothrow move -// constructible type v1.swap(v2) provides the strong exception safety -// guarantee. -#ifdef _LIBCPP_VERSION +# endif + // testing libc++ extension. If either variant stores a nothrow move + // constructible type v1.swap(v2) provides the strong exception safety + // guarantee. +# ifdef _LIBCPP_VERSION { - - using T1 = ThrowingTypeWithNothrowSwap; - using T2 = NothrowMoveable; - using V = std::variant; - T1::reset(); - T2::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<1>, 100); + using V = std::variant; + int move_called1 = 0; + int move_assign_called1 = 0; + int swap_called1 = 0; + int move_called2 = 0; + int move_assign_called2 = 0; + int swap_called2 = 0; + V v1(std::in_place_index<0>, 42, &move_called1, &move_assign_called1, &swap_called1); + V v2(std::in_place_index<1>, 100, &move_called2, &move_assign_called2, &swap_called2); try { v1.swap(v2); assert(false); } catch (int) { } - assert(T1::swap_called == 0); - assert(T1::move_called == 1); - assert(T1::move_assign_called == 0); - assert(T2::swap_called == 0); - assert(T2::move_called == 2); - assert(T2::move_assign_called == 0); + assert(swap_called1 == 0); + assert(move_called1 == 1); + assert(move_assign_called1 == 0); + assert(swap_called2 == 0); + assert(move_called2 == 2); + assert(move_assign_called2 == 0); assert(std::get<0>(v1).value == 42); assert(std::get<1>(v2).value == 100); // swap again, but call v2's swap. - T1::reset(); - T2::reset(); + + move_called1 = 0; + move_assign_called1 = 0; + swap_called1 = 0; + move_called2 = 0; + move_assign_called2 = 0; + swap_called2 = 0; + try { v2.swap(v1); assert(false); } catch (int) { } - assert(T1::swap_called == 0); - assert(T1::move_called == 1); - assert(T1::move_assign_called == 0); - assert(T2::swap_called == 0); - assert(T2::move_called == 2); - assert(T2::move_assign_called == 0); + assert(swap_called1 == 0); + assert(move_called1 == 1); + assert(move_assign_called1 == 0); + assert(swap_called2 == 0); + assert(move_called2 == 2); + assert(move_assign_called2 == 0); assert(std::get<0>(v1).value == 42); assert(std::get<1>(v2).value == 100); } -#endif // _LIBCPP_VERSION +# endif // _LIBCPP_VERSION #endif } template -constexpr auto has_swap_member_imp(int) - -> decltype(std::declval().swap(std::declval()), true) { +constexpr auto has_swap_member_imp(int) -> decltype(std::declval().swap(std::declval()), true) { return true; } -template constexpr auto has_swap_member_imp(long) -> bool { +template +constexpr auto has_swap_member_imp(long) -> bool { return false; } -template constexpr bool has_swap_member() { +template +constexpr bool has_swap_member() { return has_swap_member_imp(0); } -void test_swap_sfinae() { +constexpr void test_swap_sfinae() { { // This variant type does not provide either a member or non-member swap // but is still swappable via the generic swap algorithm, since the @@ -508,7 +516,7 @@ void test_swap_sfinae() { } } -void test_swap_noexcept() { +_LIBCPP_CONSTEXPR_SINCE_CXX20 void test_swap_noexcept() { { using V = std::variant; static_assert(std::is_swappable_v && has_swap_member(), ""); @@ -581,12 +589,28 @@ void test_swap_noexcept() { template class std::variant; #endif -int main(int, char**) { +void non_constexpr_test() { test_swap_valueless_by_exception(); + test_swap_same_alternative_throws(); + test_swap_different_alternatives_throws(); +} + +TEST_CONSTEXPR_CXX20 bool test() { test_swap_same_alternative(); test_swap_different_alternatives(); test_swap_sfinae(); test_swap_noexcept(); + return true; +} + +int main(int, char**) { + non_constexpr_test(); + test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif + return 0; } -- GitLab From 9232591b04d7a4586e88bdbd1c3e513775c73560 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Fri, 10 May 2024 08:42:52 -0600 Subject: [PATCH 267/328] [libc++][NFC] Use TestEachPointerType in TestEachAtomicType (#91480) That way, if we ever expand TestEachPointerType we will pick up those changes in TestEachAtomicType. --- libcxx/test/support/atomic_helpers.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/libcxx/test/support/atomic_helpers.h b/libcxx/test/support/atomic_helpers.h index 9a32b1ffe85e..0266a0961067 100644 --- a/libcxx/test/support/atomic_helpers.h +++ b/libcxx/test/support/atomic_helpers.h @@ -116,6 +116,7 @@ template